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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Jani Nikula78b36b12019-03-15 15:56:19 +020028#include <linux/bitfield.h>
Jani Nikula09b434d2019-03-15 15:56:18 +020029#include <linux/bits.h>
30
Jani Nikula1aa920e2017-08-10 15:29:44 +030031/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
Jani Nikula27be41d2020-04-17 16:01:09 +030037 * File Layout
38 * ~~~~~~~~~~~
Jani Nikula1aa920e2017-08-10 15:29:44 +030039 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
Jani Nikulabaa09e72019-03-15 15:56:20 +020065 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
Jani Nikula1aa920e2017-08-10 15:29:44 +030070 *
Jani Nikula09b434d2019-03-15 15:56:18 +020071 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
Jani Nikula1aa920e2017-08-10 15:29:44 +030072 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
Jonathan Corbet551bd332019-05-23 10:06:46 -060082 * ~~~~~~
Jani Nikula1aa920e2017-08-10 15:29:44 +030083 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
Jonathan Corbet551bd332019-05-23 10:06:46 -0600100 * ~~~~~~~~
Jani Nikula1aa920e2017-08-10 15:29:44 +0300101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
Jani Nikula09b434d2019-03-15 15:56:18 +0200109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
Jani Nikulabaa09e72019-03-15 15:56:20 +0200111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
Jani Nikula1aa920e2017-08-10 15:29:44 +0300114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
Jani Nikula09b434d2019-03-15 15:56:18 +0200119/**
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
122 *
123 * Local wrapper for BIT() to force u32, with compile time checks.
124 *
125 * @return: Value with bit @__n set.
126 */
127#define REG_BIT(__n) \
128 ((u32)(BIT(__n) + \
Jani Nikula591d4dc2019-05-24 21:52:53 +0300129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
Jani Nikula09b434d2019-03-15 15:56:18 +0200130 ((__n) < 0 || (__n) > 31))))
131
132/**
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
136 *
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
138 *
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
140 */
141#define REG_GENMASK(__high, __low) \
142 ((u32)(GENMASK(__high, __low) + \
Jani Nikula591d4dc2019-05-24 21:52:53 +0300143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144 __is_constexpr(__low) && \
Jani Nikula09b434d2019-03-15 15:56:18 +0200145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146
Jani Nikulabaa09e72019-03-15 15:56:20 +0200147/*
148 * Local integer constant expression version of is_power_of_2().
149 */
150#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
151
Jani Nikula78b36b12019-03-15 15:56:19 +0200152/**
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
154 * @__mask: shifted mask defining the field's length and position
155 * @__val: value to put in the field
Jani Nikulaaffa22b2019-06-05 12:56:57 +0300156 *
Jani Nikulabaa09e72019-03-15 15:56:20 +0200157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
Jani Nikula78b36b12019-03-15 15:56:19 +0200159 *
160 * @return: @__val masked and shifted into the field defined by @__mask.
161 */
Jani Nikulabaa09e72019-03-15 15:56:20 +0200162#define REG_FIELD_PREP(__mask, __val) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
Chris Wilsonab7529f2019-03-20 15:40:21 +0000164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
Jani Nikulabaa09e72019-03-15 15:56:20 +0200165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
Chris Wilsonab7529f2019-03-20 15:40:21 +0000167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
Jani Nikula78b36b12019-03-15 15:56:19 +0200168
169/**
170 * REG_FIELD_GET() - Extract a u32 bitfield value
171 * @__mask: shifted mask defining the field's length and position
172 * @__val: value to extract the bitfield value from
173 *
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176 *
177 * @return: Masked and shifted value of the field defined by @__mask in @__val.
178 */
179#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
180
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200181typedef struct {
Jani Nikula739f3ab2019-01-16 11:15:19 +0200182 u32 reg;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200183} i915_reg_t;
184
185#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186
187#define INVALID_MMIO_REG _MMIO(0)
188
Al Viro502f78c2020-04-23 14:29:05 -0400189static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200190{
191 return reg.reg;
192}
193
194static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195{
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197}
198
199static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200{
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202}
203
Jani Nikulaed5eb1b2018-12-31 16:56:42 +0200204#define VLV_DISPLAY_BASE 0x180000
205#define VLV_MIPI_BASE VLV_DISPLAY_BASE
206#define BXT_MIPI_BASE 0x60000
207
208#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
209
Jani Nikulae67005e2018-06-29 13:20:39 +0300210/*
211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212 * numbers, pick the 0-based __index'th value.
213 *
214 * Always prefer this over _PICK() if the numbers are evenly spaced.
215 */
216#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
217
218/*
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220 *
221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222 */
Jani Nikulace646452017-01-27 17:57:06 +0200223#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
224
Jani Nikulae67005e2018-06-29 13:20:39 +0300225/*
226 * Named helper wrappers around _PICK_EVEN() and _PICK().
227 */
Jani Nikula8d97b4a2018-10-31 13:04:52 +0200228#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
229#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
230#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
231#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
232#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
Lucas De Marchi11ffe972020-11-06 13:00:06 -0800233#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
Jani Nikula8d97b4a2018-10-31 13:04:52 +0200234
235#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
236#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
237#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
238#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
239#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
Lucas De Marchi11ffe972020-11-06 13:00:06 -0800240#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
Jani Nikula8d97b4a2018-10-31 13:04:52 +0200241
242#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
243
244#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
245#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
246#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
Aditya Swarup049c6512020-10-14 12:19:30 -0700247#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
248
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300249
Jani Nikulaa7c01492018-10-31 13:04:53 +0200250/*
251 * Device info offset array based helpers for groups of registers with unevenly
252 * spaced base offsets.
253 */
Jani Nikulaa0f04cc2018-12-31 16:56:44 +0200254#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
255 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
Jani Nikulaed5eb1b2018-12-31 16:56:42 +0200256 DISPLAY_MMIO_BASE(dev_priv))
José Roberto de Souza270b9992019-07-30 15:47:51 -0700257#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
258 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
259 DISPLAY_MMIO_BASE(dev_priv))
260#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
Jani Nikulaa0f04cc2018-12-31 16:56:44 +0200261#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
262 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
Jani Nikulaed5eb1b2018-12-31 16:56:42 +0200263 DISPLAY_MMIO_BASE(dev_priv))
Jani Nikulaa7c01492018-10-31 13:04:53 +0200264
Chris Wilson5ee4a7a2018-06-18 10:41:50 +0100265#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
Damien Lespiau98533252014-12-08 17:33:51 +0000266#define _MASKED_FIELD(mask, value) ({ \
267 if (__builtin_constant_p(mask)) \
268 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
269 if (__builtin_constant_p(value)) \
270 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
271 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
272 BUILD_BUG_ON_MSG((value) & ~(mask), \
273 "Incorrect value for mask"); \
Chris Wilson5ee4a7a2018-06-18 10:41:50 +0100274 __MASKED_FIELD(mask, value); })
Damien Lespiau98533252014-12-08 17:33:51 +0000275#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
276#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
277
Jesse Barnes585fb112008-07-29 11:54:06 -0700278/* PCI config space */
279
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300280#define MCHBAR_I915 0x44
281#define MCHBAR_I965 0x48
282#define MCHBAR_SIZE (4 * 4096)
283
284#define DEVEN 0x54
285#define DEVEN_MCHBAR_EN (1 << 28)
286
Joonas Lahtinen40006c42016-10-12 10:18:54 +0300287/* BSM in include/drm/i915_drm.h */
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300288
Ville Syrjälä1b1d2712015-05-22 11:22:31 +0300289#define HPLLCC 0xc0 /* 85x only */
290#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700291#define GC_CLOCK_133_200 (0 << 0)
292#define GC_CLOCK_100_200 (1 << 0)
293#define GC_CLOCK_100_133 (2 << 0)
Ville Syrjälä1b1d2712015-05-22 11:22:31 +0300294#define GC_CLOCK_133_266 (3 << 0)
295#define GC_CLOCK_133_200_2 (4 << 0)
296#define GC_CLOCK_133_266_2 (5 << 0)
297#define GC_CLOCK_166_266 (6 << 0)
298#define GC_CLOCK_166_250 (7 << 0)
299
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300300#define I915_GDRST 0xc0 /* PCI config register */
301#define GRDOM_FULL (0 << 2)
302#define GRDOM_RENDER (1 << 2)
303#define GRDOM_MEDIA (3 << 2)
304#define GRDOM_MASK (3 << 2)
305#define GRDOM_RESET_STATUS (1 << 1)
306#define GRDOM_RESET_ENABLE (1 << 0)
307
Ville Syrjälä8fdded82016-12-07 19:28:12 +0200308/* BSpec only has register offset, PCI device and bit found empirically */
309#define I830_CLOCK_GATE 0xc8 /* device 0 */
310#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
311
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300312#define GCDGMBUS 0xcc
313
Jesse Barnesf97108d2010-01-29 11:27:07 -0800314#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -0700315#define GCFGC 0xf0 /* 915+ only */
316#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
317#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
Arthur Heymans62480172017-02-01 00:50:26 +0100318#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +0200319#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
320#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
321#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
322#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
323#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
324#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700325#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -0700326#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
327#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
328#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
329#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
330#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
331#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
332#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
333#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
334#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
335#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
336#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
337#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
338#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
339#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
340#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
341#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
342#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
343#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
344#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +0100345
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300346#define ASLE 0xe4
347#define ASLS 0xfc
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700348
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300349#define SWSCI 0xe8
350#define SWSCI_SCISEL (1 << 15)
351#define SWSCI_GSSCIE (1 << 0)
352
353#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
354
Jesse Barnes585fb112008-07-29 11:54:06 -0700355
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200356#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700357#define ILK_GRDOM_FULL (0 << 1)
358#define ILK_GRDOM_RENDER (1 << 1)
359#define ILK_GRDOM_MEDIA (3 << 1)
360#define ILK_GRDOM_MASK (3 << 1)
361#define ILK_GRDOM_RESET_ENABLE (1 << 0)
Ville Syrjäläb3a3f032014-05-19 19:23:24 +0300362
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200363#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700364#define GEN6_MBC_SNPCR_SHIFT 21
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700365#define GEN6_MBC_SNPCR_MASK (3 << 21)
366#define GEN6_MBC_SNPCR_MAX (0 << 21)
367#define GEN6_MBC_SNPCR_MED (1 << 21)
368#define GEN6_MBC_SNPCR_LOW (2 << 21)
369#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700370
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200371#define VLV_G3DCTL _MMIO(0x9024)
372#define VLV_GSCKGCTL _MMIO(0x9028)
Imre Deak9e72b462014-05-05 15:13:55 +0300373
Ville Syrjälä9ddfa5a2021-11-04 16:45:17 +0200374#define FBC_LLC_READ_CTRL _MMIO(0x9044)
375#define FBC_LLC_FULLY_OPEN REG_BIT(30)
376
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200377#define GEN6_MBCTL _MMIO(0x0907c)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100378#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
379#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
380#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
381#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
382#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
383
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200384#define GEN6_GDRST _MMIO(0x941c)
Eric Anholtcff458c2010-11-18 09:31:14 +0800385#define GEN6_GRDOM_FULL (1 << 0)
386#define GEN6_GRDOM_RENDER (1 << 1)
387#define GEN6_GRDOM_MEDIA (1 << 2)
388#define GEN6_GRDOM_BLT (1 << 3)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200389#define GEN6_GRDOM_VECS (1 << 4)
Arun Siluvery6b332fa2016-04-04 18:50:56 +0100390#define GEN9_GRDOM_GUC (1 << 5)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200391#define GEN8_GRDOM_MEDIA2 (1 << 7)
Michel Thierrye34b0342018-04-05 17:00:48 +0300392/* GEN11 changed all bit defs except for FULL & RENDER */
393#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
394#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
395#define GEN11_GRDOM_BLT (1 << 2)
396#define GEN11_GRDOM_GUC (1 << 3)
397#define GEN11_GRDOM_MEDIA (1 << 5)
398#define GEN11_GRDOM_MEDIA2 (1 << 6)
399#define GEN11_GRDOM_MEDIA3 (1 << 7)
400#define GEN11_GRDOM_MEDIA4 (1 << 8)
John Harrisonddabf722021-07-23 10:42:13 -0700401#define GEN11_GRDOM_MEDIA5 (1 << 9)
402#define GEN11_GRDOM_MEDIA6 (1 << 10)
403#define GEN11_GRDOM_MEDIA7 (1 << 11)
404#define GEN11_GRDOM_MEDIA8 (1 << 12)
Michel Thierrye34b0342018-04-05 17:00:48 +0300405#define GEN11_GRDOM_VECS (1 << 13)
406#define GEN11_GRDOM_VECS2 (1 << 14)
John Harrisonddabf722021-07-23 10:42:13 -0700407#define GEN11_GRDOM_VECS3 (1 << 15)
408#define GEN11_GRDOM_VECS4 (1 << 16)
Oscar Mateof513ac72018-12-13 09:15:22 +0000409#define GEN11_GRDOM_SFC0 (1 << 17)
410#define GEN11_GRDOM_SFC1 (1 << 18)
John Harrisonddabf722021-07-23 10:42:13 -0700411#define GEN11_GRDOM_SFC2 (1 << 19)
412#define GEN11_GRDOM_SFC3 (1 << 20)
Oscar Mateof513ac72018-12-13 09:15:22 +0000413
414#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
415#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
416
417#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
418#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
419#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
420#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
421#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
422
423#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
424#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
425#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
426#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
427#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
428#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
Eric Anholtcff458c2010-11-18 09:31:14 +0800429
Aditya Swarup5b26d572021-05-26 02:48:52 -0700430#define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
431#define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)
432#define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
433#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
434#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
435
Matt Roper82929a212021-07-28 16:34:11 -0700436#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
Mika Kuoppalae50dbdb2019-10-29 18:38:40 +0200437#define GEN12_SFC_DONE_MAX 4
438
Daniele Ceraolo Spuriobaba6e52019-03-25 14:49:40 -0700439#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
440#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
441#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100442#define PP_DIR_DCLV_2G 0xffffffff
443
Chris Wilson6d425722019-04-05 13:38:31 +0100444#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
445#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800446
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200447#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
Jeff McGee0cea6502015-02-13 10:27:56 -0600448#define GEN8_RPCS_ENABLE (1 << 31)
449#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
450#define GEN8_RPCS_S_CNT_SHIFT 15
451#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
Tvrtko Ursulinb212f0a2018-09-03 12:30:07 +0100452#define GEN11_RPCS_S_CNT_SHIFT 12
453#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
Jeff McGee0cea6502015-02-13 10:27:56 -0600454#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
455#define GEN8_RPCS_SS_CNT_SHIFT 8
456#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
457#define GEN8_RPCS_EU_MAX_SHIFT 4
458#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
459#define GEN8_RPCS_EU_MIN_SHIFT 0
460#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
461
Lionel Landwerlinf89823c2017-08-03 18:05:50 +0100462#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
463/* HSW only */
464#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
465#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
466#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
467#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
468/* HSW+ */
469#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
470#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
471#define HSW_RCS_INHIBIT (1 << 8)
472/* Gen8 */
473#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
474#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
475#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
476#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
477#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
478#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
479#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
480#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
481#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
482#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
483
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200484#define GAM_ECOCHK _MMIO(0x4090)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700485#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
486#define ECOCHK_SNB_BIT (1 << 10)
487#define ECOCHK_DIS_TLB (1 << 8)
488#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
489#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
490#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
491#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
492#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
493#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
494#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
495#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100496
Imre Deak2248a282019-10-17 16:38:31 +0300497#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
498
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200499#define GAC_ECO_BITS _MMIO(0x14090)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700500#define ECOBITS_SNB_BIT (1 << 13)
501#define ECOBITS_PPGTT_CACHE64B (3 << 8)
502#define ECOBITS_PPGTT_CACHE4B (0 << 8)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200503
Stuart Summersd73dd1f2021-11-02 15:25:09 -0700504#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
505#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
506#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
507
Matt Roper645cc0b2021-11-02 15:25:10 -0700508#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
509#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
510#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
511#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
512
Stuart Summersd73dd1f2021-11-02 15:25:09 -0700513#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
514#define FORCE_MISS_FTLB REG_BIT(3)
515
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200516#define GAB_CTL _MMIO(0x24000)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700517#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
Daniel Vetterbe901a52012-04-11 20:42:39 +0200518
Matt Roperc256af02021-04-20 14:18:42 +0100519#define GU_CNTL _MMIO(0x101010)
520#define LMEM_INIT REG_BIT(7)
521
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200522#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
Paulo Zanoni3774eb52015-08-10 14:57:32 -0300523#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
524#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
525#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
526#define GEN6_STOLEN_RESERVED_1M (0 << 4)
527#define GEN6_STOLEN_RESERVED_512K (1 << 4)
528#define GEN6_STOLEN_RESERVED_256K (2 << 4)
529#define GEN6_STOLEN_RESERVED_128K (3 << 4)
530#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
531#define GEN7_STOLEN_RESERVED_1M (0 << 5)
532#define GEN7_STOLEN_RESERVED_256K (1 << 5)
533#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
534#define GEN8_STOLEN_RESERVED_1M (0 << 7)
535#define GEN8_STOLEN_RESERVED_2M (1 << 7)
536#define GEN8_STOLEN_RESERVED_4M (2 << 7)
537#define GEN8_STOLEN_RESERVED_8M (3 << 7)
Ville Syrjälädb7fb602017-11-02 17:17:35 +0200538#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
Paulo Zanoni185441e2018-05-04 13:32:52 -0700539#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
Daniel Vetter40bae732014-09-11 13:28:08 +0200540
Jesse Barnes585fb112008-07-29 11:54:06 -0700541/* VGA stuff */
542
543#define VGA_ST01_MDA 0x3ba
544#define VGA_ST01_CGA 0x3da
545
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200546#define _VGA_MSR_WRITE _MMIO(0x3c2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700547#define VGA_MSR_WRITE 0x3c2
548#define VGA_MSR_READ 0x3cc
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700549#define VGA_MSR_MEM_EN (1 << 1)
550#define VGA_MSR_CGA_MODE (1 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700551
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300552#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100553#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300554#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700555
556#define VGA_AR_INDEX 0x3c0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700557#define VGA_AR_VID_EN (1 << 5)
Jesse Barnes585fb112008-07-29 11:54:06 -0700558#define VGA_AR_DATA_WRITE 0x3c0
559#define VGA_AR_DATA_READ 0x3c1
560
561#define VGA_GR_INDEX 0x3ce
562#define VGA_GR_DATA 0x3cf
563/* GR05 */
564#define VGA_GR_MEM_READ_MODE_SHIFT 3
565#define VGA_GR_MEM_READ_MODE_PLANE 1
566/* GR06 */
567#define VGA_GR_MEM_MODE_MASK 0xc
568#define VGA_GR_MEM_MODE_SHIFT 2
569#define VGA_GR_MEM_A0000_AFFFF 0
570#define VGA_GR_MEM_A0000_BFFFF 1
571#define VGA_GR_MEM_B0000_B7FFF 2
572#define VGA_GR_MEM_B0000_BFFFF 3
573
574#define VGA_DACMASK 0x3c6
575#define VGA_DACRX 0x3c7
576#define VGA_DACWX 0x3c8
577#define VGA_DACDATA 0x3c9
578
579#define VGA_CR_INDEX_MDA 0x3b4
580#define VGA_CR_DATA_MDA 0x3b5
581#define VGA_CR_INDEX_CGA 0x3d4
582#define VGA_CR_DATA_CGA 0x3d5
583
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200584#define MI_PREDICATE_SRC0 _MMIO(0x2400)
585#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
586#define MI_PREDICATE_SRC1 _MMIO(0x2408)
587#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
Lionel Landwerlindaed3e42019-10-12 08:23:07 +0100588#define MI_PREDICATE_DATA _MMIO(0x2410)
589#define MI_PREDICATE_RESULT _MMIO(0x2418)
590#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200591#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700592#define LOWER_SLICE_ENABLED (1 << 0)
593#define LOWER_SLICE_DISABLED (0 << 0)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300594
Jesse Barnes585fb112008-07-29 11:54:06 -0700595/*
Brad Volkin5947de92014-02-18 10:15:50 -0800596 * Registers used only by the command parser
597 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200598#define BCS_SWCTRL _MMIO(0x22200)
Zbigniew Kempczyński79eb8c72020-04-30 07:49:57 +0100599#define BCS_SRC_Y REG_BIT(0)
600#define BCS_DST_Y REG_BIT(1)
Brad Volkin5947de92014-02-18 10:15:50 -0800601
Jon Bloomfield0f2f3972018-04-23 11:12:15 -0700602/* There are 16 GPR registers */
603#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
604#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
605
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200606#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
607#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
608#define HS_INVOCATION_COUNT _MMIO(0x2300)
609#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
610#define DS_INVOCATION_COUNT _MMIO(0x2308)
611#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
612#define IA_VERTICES_COUNT _MMIO(0x2310)
613#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
614#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
615#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
616#define VS_INVOCATION_COUNT _MMIO(0x2320)
617#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
618#define GS_INVOCATION_COUNT _MMIO(0x2328)
619#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
620#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
621#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
622#define CL_INVOCATION_COUNT _MMIO(0x2338)
623#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
624#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
625#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
626#define PS_INVOCATION_COUNT _MMIO(0x2348)
627#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
628#define PS_DEPTH_COUNT _MMIO(0x2350)
629#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800630
631/* There are the 4 64-bit counter registers, one for each stream output */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200632#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
633#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800634
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200635#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
636#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
Brad Volkin113a0472014-04-08 14:18:58 -0700637
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200638#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
639#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
640#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
641#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
642#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
643#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
Brad Volkin113a0472014-04-08 14:18:58 -0700644
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200645#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
646#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
647#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
Jordan Justen7b9748c2015-10-01 23:09:58 -0700648
Jordan Justen1b850662016-03-06 23:30:29 -0800649/* There are the 16 64-bit CS General Purpose Registers */
650#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
651#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
652
Robert Bragga9417952016-11-07 19:49:48 +0000653#define GEN7_OACONTROL _MMIO(0x2360)
Robert Braggd7965152016-11-07 19:49:52 +0000654#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
655#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
656#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700657#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
658#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
659#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
660#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
661#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
662#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
663#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
664#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
665#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
Robert Braggd7965152016-11-07 19:49:52 +0000666#define GEN7_OACONTROL_FORMAT_SHIFT 2
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700667#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
668#define GEN7_OACONTROL_ENABLE (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000669
670#define GEN8_OACTXID _MMIO(0x2364)
671
Robert Bragg19f81df2017-06-13 12:23:03 +0100672#define GEN8_OA_DEBUG _MMIO(0x2B04)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700673#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
674#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
675#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
676#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
Robert Bragg19f81df2017-06-13 12:23:03 +0100677
Robert Braggd7965152016-11-07 19:49:52 +0000678#define GEN8_OACONTROL _MMIO(0x2B00)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700679#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
680#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
681#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
682#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
Robert Braggd7965152016-11-07 19:49:52 +0000683#define GEN8_OA_REPORT_FORMAT_SHIFT 2
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700684#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
685#define GEN8_OA_COUNTER_ENABLE (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000686
687#define GEN8_OACTXCONTROL _MMIO(0x2360)
688#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
689#define GEN8_OA_TIMER_PERIOD_SHIFT 2
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700690#define GEN8_OA_TIMER_ENABLE (1 << 1)
691#define GEN8_OA_COUNTER_RESUME (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000692
693#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700694#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
695#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
696#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
697#define GEN7_OABUFFER_RESUME (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000698
Robert Bragg19f81df2017-06-13 12:23:03 +0100699#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
Robert Braggd7965152016-11-07 19:49:52 +0000700#define GEN8_OABUFFER _MMIO(0x2b14)
Lionel Landwerlinb82ed432018-03-26 10:08:26 +0100701#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
Robert Braggd7965152016-11-07 19:49:52 +0000702
703#define GEN7_OASTATUS1 _MMIO(0x2364)
704#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700705#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
706#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
707#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000708
709#define GEN7_OASTATUS2 _MMIO(0x2368)
Lionel Landwerlinb82ed432018-03-26 10:08:26 +0100710#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
711#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
Robert Braggd7965152016-11-07 19:49:52 +0000712
713#define GEN8_OASTATUS _MMIO(0x2b08)
Lionel Landwerlin059a0be2020-11-17 15:01:24 +0200714#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
715#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700716#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
717#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
718#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
719#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
Robert Braggd7965152016-11-07 19:49:52 +0000720
721#define GEN8_OAHEADPTR _MMIO(0x2B0C)
Robert Bragg19f81df2017-06-13 12:23:03 +0100722#define GEN8_OAHEADPTR_MASK 0xffffffc0
Robert Braggd7965152016-11-07 19:49:52 +0000723#define GEN8_OATAILPTR _MMIO(0x2B10)
Robert Bragg19f81df2017-06-13 12:23:03 +0100724#define GEN8_OATAILPTR_MASK 0xffffffc0
Robert Braggd7965152016-11-07 19:49:52 +0000725
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700726#define OABUFFER_SIZE_128K (0 << 3)
727#define OABUFFER_SIZE_256K (1 << 3)
728#define OABUFFER_SIZE_512K (2 << 3)
729#define OABUFFER_SIZE_1M (3 << 3)
730#define OABUFFER_SIZE_2M (4 << 3)
731#define OABUFFER_SIZE_4M (5 << 3)
732#define OABUFFER_SIZE_8M (6 << 3)
733#define OABUFFER_SIZE_16M (7 << 3)
Robert Braggd7965152016-11-07 19:49:52 +0000734
Umesh Nerlige Ramappaa639b0c2020-03-09 14:10:57 -0700735#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
736
Matt Roper212e6562021-11-02 15:25:11 -0700737#define GEN12_SQCM _MMIO(0x8724)
738#define EN_32B_ACCESS REG_BIT(30)
739
Lionel Landwerlin00a7f0d2019-10-25 12:37:46 -0700740/* Gen12 OAR unit */
741#define GEN12_OAR_OACONTROL _MMIO(0x2960)
742#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
743#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
744
745#define GEN12_OACTXCONTROL _MMIO(0x2360)
746#define GEN12_OAR_OASTATUS _MMIO(0x2968)
747
748/* Gen12 OAG unit */
749#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
750#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
751#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
752#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
753
754#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
755#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
756#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
757#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
758
759#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
760#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
761#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
762#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
763
764#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
765#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
766#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
767
768#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
769#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
770#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
771#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
772#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
773
774#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
775#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
776#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
777#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
778
Robert Bragg19f81df2017-06-13 12:23:03 +0100779/*
780 * Flexible, Aggregate EU Counter Registers.
781 * Note: these aren't contiguous
782 */
Robert Braggd7965152016-11-07 19:49:52 +0000783#define EU_PERF_CNTL0 _MMIO(0xe458)
Robert Bragg19f81df2017-06-13 12:23:03 +0100784#define EU_PERF_CNTL1 _MMIO(0xe558)
785#define EU_PERF_CNTL2 _MMIO(0xe658)
786#define EU_PERF_CNTL3 _MMIO(0xe758)
787#define EU_PERF_CNTL4 _MMIO(0xe45c)
788#define EU_PERF_CNTL5 _MMIO(0xe55c)
789#define EU_PERF_CNTL6 _MMIO(0xe65c)
Robert Braggd7965152016-11-07 19:49:52 +0000790
Matt Roper645cc0b2021-11-02 15:25:10 -0700791#define RT_CTRL _MMIO(0xe530)
792#define DIS_NULL_QUERY REG_BIT(10)
793
Robert Braggd7965152016-11-07 19:49:52 +0000794/*
795 * OA Boolean state
796 */
797
Robert Braggd7965152016-11-07 19:49:52 +0000798#define OASTARTTRIG1 _MMIO(0x2710)
799#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
800#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
801
802#define OASTARTTRIG2 _MMIO(0x2714)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700803#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
804#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
805#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
806#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
807#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
808#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
809#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
810#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
811#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
812#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
813#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
814#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
815#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
816#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
817#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
818#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
819#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
820#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
821#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
822#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
823#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
824#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
825#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
826#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
827#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
828#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
829#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
830#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
831#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
Robert Braggd7965152016-11-07 19:49:52 +0000832
833#define OASTARTTRIG3 _MMIO(0x2718)
834#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
835#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
836#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
837#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
838#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
839#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
840#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
841#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
842#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
843
844#define OASTARTTRIG4 _MMIO(0x271c)
845#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
846#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
847#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
848#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
849#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
850#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
851#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
852#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
853#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
854
855#define OASTARTTRIG5 _MMIO(0x2720)
856#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
857#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
858
859#define OASTARTTRIG6 _MMIO(0x2724)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700860#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
861#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
862#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
863#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
864#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
865#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
866#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
867#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
868#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
869#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
870#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
871#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
872#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
873#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
874#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
875#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
876#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
877#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
878#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
879#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
880#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
881#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
882#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
883#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
884#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
885#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
886#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
887#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
888#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
Robert Braggd7965152016-11-07 19:49:52 +0000889
890#define OASTARTTRIG7 _MMIO(0x2728)
891#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
892#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
893#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
894#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
895#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
896#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
897#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
898#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
899#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
900
901#define OASTARTTRIG8 _MMIO(0x272c)
902#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
903#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
904#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
905#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
906#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
907#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
908#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
909#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
910#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
911
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100912#define OAREPORTTRIG1 _MMIO(0x2740)
913#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
Flavio Suligoi6f48fd82020-07-03 14:50:46 +0200914#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100915
916#define OAREPORTTRIG2 _MMIO(0x2744)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700917#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
918#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
919#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
920#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
921#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
922#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
923#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
924#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
925#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
926#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
927#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
928#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
929#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
930#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
931#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
932#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
933#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
934#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
935#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
936#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
937#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
938#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
939#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
940#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
941#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100942
943#define OAREPORTTRIG3 _MMIO(0x2748)
944#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
945#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
946#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
947#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
948#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
949#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
950#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
951#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
952#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
953
954#define OAREPORTTRIG4 _MMIO(0x274c)
955#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
956#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
957#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
958#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
959#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
960#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
961#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
962#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
963#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
964
965#define OAREPORTTRIG5 _MMIO(0x2750)
966#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
Flavio Suligoi6f48fd82020-07-03 14:50:46 +0200967#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100968
969#define OAREPORTTRIG6 _MMIO(0x2754)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -0700970#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
971#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
972#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
973#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
974#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
975#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
976#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
977#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
978#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
979#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
980#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
981#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
982#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
983#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
984#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
985#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
986#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
987#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
988#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
989#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
990#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
991#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
992#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
993#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
994#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100995
996#define OAREPORTTRIG7 _MMIO(0x2758)
997#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
998#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
999#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1000#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1001#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1002#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1003#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1004#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1005#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1006
1007#define OAREPORTTRIG8 _MMIO(0x275c)
1008#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1009#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1010#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1011#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1012#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1013#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1014#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1015#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1016#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1017
Lionel Landwerlin00a7f0d2019-10-25 12:37:46 -07001018/* Same layout as OASTARTTRIGX */
1019#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
1020#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
1021#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
1022#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
1023#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
1024#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
1025#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
1026#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
1027
1028/* Same layout as OAREPORTTRIGX */
1029#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
1030#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
1031#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
1032#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
1033#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
1034#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
1035#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
1036#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1037
Robert Braggd7965152016-11-07 19:49:52 +00001038/* CECX_0 */
1039#define OACEC_COMPARE_LESS_OR_EQUAL 6
1040#define OACEC_COMPARE_NOT_EQUAL 5
1041#define OACEC_COMPARE_LESS_THAN 4
1042#define OACEC_COMPARE_GREATER_OR_EQUAL 3
1043#define OACEC_COMPARE_EQUAL 2
1044#define OACEC_COMPARE_GREATER_THAN 1
1045#define OACEC_COMPARE_ANY_EQUAL 0
1046
1047#define OACEC_COMPARE_VALUE_MASK 0xffff
1048#define OACEC_COMPARE_VALUE_SHIFT 3
1049
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001050#define OACEC_SELECT_NOA (0 << 19)
1051#define OACEC_SELECT_PREV (1 << 19)
1052#define OACEC_SELECT_BOOLEAN (2 << 19)
Robert Braggd7965152016-11-07 19:49:52 +00001053
Lionel Landwerlin00a7f0d2019-10-25 12:37:46 -07001054/* 11-bit array 0: pass-through, 1: negated */
1055#define GEN12_OASCEC_NEGATE_MASK 0x7ff
1056#define GEN12_OASCEC_NEGATE_SHIFT 21
1057
Robert Braggd7965152016-11-07 19:49:52 +00001058/* CECX_1 */
1059#define OACEC_MASK_MASK 0xffff
1060#define OACEC_CONSIDERATIONS_MASK 0xffff
1061#define OACEC_CONSIDERATIONS_SHIFT 16
1062
1063#define OACEC0_0 _MMIO(0x2770)
1064#define OACEC0_1 _MMIO(0x2774)
1065#define OACEC1_0 _MMIO(0x2778)
1066#define OACEC1_1 _MMIO(0x277c)
1067#define OACEC2_0 _MMIO(0x2780)
1068#define OACEC2_1 _MMIO(0x2784)
1069#define OACEC3_0 _MMIO(0x2788)
1070#define OACEC3_1 _MMIO(0x278c)
1071#define OACEC4_0 _MMIO(0x2790)
1072#define OACEC4_1 _MMIO(0x2794)
1073#define OACEC5_0 _MMIO(0x2798)
1074#define OACEC5_1 _MMIO(0x279c)
1075#define OACEC6_0 _MMIO(0x27a0)
1076#define OACEC6_1 _MMIO(0x27a4)
1077#define OACEC7_0 _MMIO(0x27a8)
1078#define OACEC7_1 _MMIO(0x27ac)
1079
Lionel Landwerlin00a7f0d2019-10-25 12:37:46 -07001080/* Same layout as CECX_Y */
1081#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1082#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1083#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1084#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1085#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1086#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1087#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1088#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1089#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1090#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1091#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1092#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1093#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1094#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1095#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1096#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1097
1098/* Same layout as CECX_Y + negate 11-bit array */
1099#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1100#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1101#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1102#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1103#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1104#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1105#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1106#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1107#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1108#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1109#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1110#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1111#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1112#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1113#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1114#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1115
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001116/* OA perf counters */
1117#define OA_PERFCNT1_LO _MMIO(0x91B8)
1118#define OA_PERFCNT1_HI _MMIO(0x91BC)
1119#define OA_PERFCNT2_LO _MMIO(0x91C0)
1120#define OA_PERFCNT2_HI _MMIO(0x91C4)
Lionel Landwerlin95690a02017-11-10 19:08:43 +00001121#define OA_PERFCNT3_LO _MMIO(0x91C8)
1122#define OA_PERFCNT3_HI _MMIO(0x91CC)
1123#define OA_PERFCNT4_LO _MMIO(0x91D8)
1124#define OA_PERFCNT4_HI _MMIO(0x91DC)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001125
1126#define OA_PERFMATRIX_LO _MMIO(0x91C8)
1127#define OA_PERFMATRIX_HI _MMIO(0x91CC)
1128
1129/* RPM unit config (Gen8+) */
1130#define RPM_CONFIG0 _MMIO(0x0D00)
Lionel Landwerlindab91782017-11-10 19:08:44 +00001131#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1132#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1133#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1134#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
Paulo Zanonid775a7b2018-01-09 21:28:35 -02001135#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1136#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1137#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
1138#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
1139#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
1140#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
Lionel Landwerlindab91782017-11-10 19:08:44 +00001141#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1142#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1143
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001144#define RPM_CONFIG1 _MMIO(0x0D04)
Lionel Landwerlin95690a02017-11-10 19:08:43 +00001145#define GEN10_GT_NOA_ENABLE (1 << 9)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001146
Lionel Landwerlindab91782017-11-10 19:08:44 +00001147/* GPM unit config (Gen9+) */
1148#define CTC_MODE _MMIO(0xA26C)
1149#define CTC_SOURCE_PARAMETER_MASK 1
1150#define CTC_SOURCE_CRYSTAL_CLOCK 0
1151#define CTC_SOURCE_DIVIDE_LOGIC 1
1152#define CTC_SHIFT_PARAMETER_SHIFT 1
1153#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1154
Lionel Landwerlin58885762017-11-10 19:08:42 +00001155/* RCP unit config (Gen8+) */
1156#define RCP_CONFIG _MMIO(0x0D08)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001157
Lionel Landwerlina54b19f2017-11-10 19:08:39 +00001158/* NOA (HSW) */
1159#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1160#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1161#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1162#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1163#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1164#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1165#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1166#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1167#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1168#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1169
1170#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1171
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001172/* NOA (Gen8+) */
1173#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1174
1175#define MICRO_BP0_0 _MMIO(0x9800)
1176#define MICRO_BP0_2 _MMIO(0x9804)
1177#define MICRO_BP0_1 _MMIO(0x9808)
1178
1179#define MICRO_BP1_0 _MMIO(0x980C)
1180#define MICRO_BP1_2 _MMIO(0x9810)
1181#define MICRO_BP1_1 _MMIO(0x9814)
1182
1183#define MICRO_BP2_0 _MMIO(0x9818)
1184#define MICRO_BP2_2 _MMIO(0x981C)
1185#define MICRO_BP2_1 _MMIO(0x9820)
1186
1187#define MICRO_BP3_0 _MMIO(0x9824)
1188#define MICRO_BP3_2 _MMIO(0x9828)
1189#define MICRO_BP3_1 _MMIO(0x982C)
1190
1191#define MICRO_BP_TRIGGER _MMIO(0x9830)
1192#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1193#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1194#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1195
Lionel Landwerlin00a7f0d2019-10-25 12:37:46 -07001196#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1197#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1198#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1199
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001200#define GDT_CHICKEN_BITS _MMIO(0x9840)
1201#define GT_NOA_ENABLE 0x00000080
1202
1203#define NOA_DATA _MMIO(0x986C)
1204#define NOA_WRITE _MMIO(0x9888)
Lionel Landwerlinbf210f62019-06-02 01:58:45 +03001205#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
Kenneth Graunke180b8132014-03-25 22:52:03 -07001206
Brad Volkin220375a2014-02-18 10:15:51 -08001207#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1208#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001209#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
Brad Volkin220375a2014-02-18 10:15:51 -08001210
Brad Volkin5947de92014-02-18 10:15:50 -08001211/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001212 * Reset registers
1213 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001214#define DEBUG_RESET_I830 _MMIO(0x6070)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001215#define DEBUG_RESET_FULL (1 << 7)
1216#define DEBUG_RESET_RENDER (1 << 8)
1217#define DEBUG_RESET_DISPLAY (1 << 9)
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001218
Jesse Barnes57f350b2012-03-28 13:39:25 -07001219/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001220 * IOSF sideband
1221 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001222#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001223#define IOSF_DEVFN_SHIFT 24
1224#define IOSF_OPCODE_SHIFT 16
1225#define IOSF_PORT_SHIFT 8
1226#define IOSF_BYTE_ENABLES_SHIFT 4
1227#define IOSF_BAR_SHIFT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001228#define IOSF_SB_BUSY (1 << 0)
Jani Nikula4688d452016-02-04 12:50:53 +02001229#define IOSF_PORT_BUNIT 0x03
1230#define IOSF_PORT_PUNIT 0x04
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001231#define IOSF_PORT_NC 0x11
1232#define IOSF_PORT_DPIO 0x12
Jani Nikulae9f882a2013-08-27 15:12:14 +03001233#define IOSF_PORT_GPIO_NC 0x13
1234#define IOSF_PORT_CCK 0x14
Jani Nikula4688d452016-02-04 12:50:53 +02001235#define IOSF_PORT_DPIO_2 0x1a
1236#define IOSF_PORT_FLISDSI 0x1b
Deepak Mdfb19ed2016-02-04 18:55:15 +02001237#define IOSF_PORT_GPIO_SC 0x48
1238#define IOSF_PORT_GPIO_SUS 0xa8
Jani Nikula4688d452016-02-04 12:50:53 +02001239#define IOSF_PORT_CCU 0xa9
Jani Nikula7071af92016-03-18 13:11:15 +02001240#define CHV_IOSF_PORT_GPIO_N 0x13
1241#define CHV_IOSF_PORT_GPIO_SE 0x48
1242#define CHV_IOSF_PORT_GPIO_E 0xa8
1243#define CHV_IOSF_PORT_GPIO_SW 0xb2
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001244#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1245#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001246
Jesse Barnes30a970c2013-11-04 13:48:12 -08001247/* See configdb bunit SB addr map */
1248#define BUNIT_REG_BISOC 0x11
1249
Ville Syrjälä5e0b66972018-11-29 19:55:04 +02001250/* PUNIT_REG_*SSPM0 */
1251#define _SSPM0_SSC(val) ((val) << 0)
1252#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1253#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1254#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1255#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1256#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1257#define _SSPM0_SSS(val) ((val) << 24)
1258#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1259#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1260#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1261#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1262#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1263
1264/* PUNIT_REG_*SSPM1 */
1265#define SSPM1_FREQSTAT_SHIFT 24
1266#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1267#define SSPM1_FREQGUAR_SHIFT 8
1268#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1269#define SSPM1_FREQ_SHIFT 0
1270#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1271
1272#define PUNIT_REG_VEDSSPM0 0x32
1273#define PUNIT_REG_VEDSSPM1 0x33
1274
Ville Syrjäläc11b8132018-11-29 19:55:03 +02001275#define PUNIT_REG_DSPSSPM 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +03001276#define DSPFREQSTAT_SHIFT_CHV 24
1277#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1278#define DSPFREQGUAR_SHIFT_CHV 8
1279#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -08001280#define DSPFREQSTAT_SHIFT 30
1281#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1282#define DSPFREQGUAR_SHIFT 14
1283#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjäläcfb41412015-03-05 21:19:51 +02001284#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1285#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1286#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
Ville Syrjälä26972b02014-06-28 02:04:11 +03001287#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1288#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1289#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1290#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1291#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1292#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1293#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1294#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1295#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1296#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1297#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1298#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +02001299
Ville Syrjälä5e0b66972018-11-29 19:55:04 +02001300#define PUNIT_REG_ISPSSPM0 0x39
1301#define PUNIT_REG_ISPSSPM1 0x3a
1302
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +08001303#define PUNIT_REG_PWRGT_CTRL 0x60
1304#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deakd13dd052018-08-06 12:58:38 +03001305#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1306#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1307#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1308#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1309#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1310
1311#define PUNIT_PWGT_IDX_RENDER 0
1312#define PUNIT_PWGT_IDX_MEDIA 1
1313#define PUNIT_PWGT_IDX_DISP2D 3
1314#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1315#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1316#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1317#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1318#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1319#define PUNIT_PWGT_IDX_DPIO_RX0 10
1320#define PUNIT_PWGT_IDX_DPIO_RX1 11
1321#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +08001322
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001323#define PUNIT_REG_GPU_LFM 0xd3
1324#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1325#define PUNIT_REG_GPU_FREQ_STS 0xd8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001326#define GPLLENABLE (1 << 4)
1327#define GENFREQSTATUS (1 << 0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001328#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -04001329#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001330
1331#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1332#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1333
Deepak S095acd52015-01-17 11:05:59 +05301334#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1335#define FB_GFX_FREQ_FUSE_MASK 0xff
1336#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1337#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1338#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1339
1340#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1341#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1342
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +02001343#define PUNIT_REG_DDR_SETUP2 0x139
1344#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1345#define FORCE_DDR_LOW_FREQ (1 << 1)
1346#define FORCE_DDR_HIGH_FREQ (1 << 0)
1347
Deepak S2b6b3a02014-05-27 15:59:30 +05301348#define PUNIT_GPU_STATUS_REG 0xdb
1349#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1350#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1351#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1352#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1353
1354#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1355#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1356#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1357
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001358#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1359#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1360#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1361#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1362#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1363#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1364#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1365#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1366#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1367#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1368
Paulo Zanoniaf7187b2018-06-12 16:56:53 -07001369#define VLV_TURBO_SOC_OVERRIDE 0x04
1370#define VLV_OVERRIDE_EN 1
1371#define VLV_SOC_TDP_EN (1 << 1)
1372#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1373#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
Deepak S3ef62342015-04-29 08:36:24 +05301374
ymohanmabe4fc042013-08-27 23:40:56 +03001375/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08001376#define CCK_FUSE_REG 0x8
1377#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +03001378#define CCK_REG_DSI_PLL_FUSE 0x44
1379#define CCK_REG_DSI_PLL_CONTROL 0x48
1380#define DSI_PLL_VCO_EN (1 << 31)
1381#define DSI_PLL_LDO_GATE (1 << 30)
1382#define DSI_PLL_P1_POST_DIV_SHIFT 17
1383#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1384#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1385#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1386#define DSI_PLL_MUX_MASK (3 << 9)
1387#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1388#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1389#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1390#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1391#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1392#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1393#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1394#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1395#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1396#define DSI_PLL_LOCK (1 << 0)
1397#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1398#define DSI_PLL_LFSR (1 << 31)
1399#define DSI_PLL_FRACTION_EN (1 << 30)
1400#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1401#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1402#define DSI_PLL_USYNC_CNT_SHIFT 18
1403#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1404#define DSI_PLL_N1_DIV_SHIFT 16
1405#define DSI_PLL_N1_DIV_MASK (3 << 16)
1406#define DSI_PLL_M1_DIV_SHIFT 0
1407#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03001408#define CCK_CZ_CLOCK_CONTROL 0x62
Ville Syrjäläc30fec62016-03-04 21:43:02 +02001409#define CCK_GPLL_CLOCK_CONTROL 0x67
Jesse Barnes30a970c2013-11-04 13:48:12 -08001410#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä35d38d12016-03-02 17:22:16 +02001411#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
Vandana Kannan87d5d252015-09-24 23:29:17 +03001412#define CCK_TRUNK_FORCE_ON (1 << 17)
1413#define CCK_TRUNK_FORCE_OFF (1 << 16)
1414#define CCK_FREQUENCY_STATUS (0x1f << 8)
1415#define CCK_FREQUENCY_STATUS_SHIFT 8
1416#define CCK_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +03001417
Ander Conselvan de Oliveiraf38861b2016-10-06 19:22:18 +03001418/* DPIO registers */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001419#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001420
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001421#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001422#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1423#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1424#define DPIO_SFR_BYPASS (1 << 1)
1425#define DPIO_CMNRST (1 << 0)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001426
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001427#define DPIO_PHY(pipe) ((pipe) >> 1)
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001428
Daniel Vetter598fac62013-04-18 22:01:46 +02001429/*
1430 * Per pipe/PLL DPIO regs
1431 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001432#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -07001433#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +02001434#define DPIO_POST_DIV_DAC 0
1435#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1436#define DPIO_POST_DIV_LVDS1 2
1437#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -07001438#define DPIO_K_SHIFT (24) /* 4 bits */
1439#define DPIO_P1_SHIFT (21) /* 3 bits */
1440#define DPIO_P2_SHIFT (16) /* 5 bits */
1441#define DPIO_N_SHIFT (12) /* 4 bits */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001442#define DPIO_ENABLE_CALIBRATION (1 << 11)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001443#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1444#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001445#define _VLV_PLL_DW3_CH1 0x802c
1446#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001447
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001448#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -07001449#define DPIO_REFSEL_OVERRIDE 27
1450#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1451#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1452#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301453#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -07001454#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1455#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001456#define _VLV_PLL_DW5_CH1 0x8034
1457#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001458
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001459#define _VLV_PLL_DW7_CH0 0x801c
1460#define _VLV_PLL_DW7_CH1 0x803c
1461#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001462
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001463#define _VLV_PLL_DW8_CH0 0x8040
1464#define _VLV_PLL_DW8_CH1 0x8060
1465#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001466
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001467#define VLV_PLL_DW9_BCAST 0xc044
1468#define _VLV_PLL_DW9_CH0 0x8044
1469#define _VLV_PLL_DW9_CH1 0x8064
1470#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001471
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001472#define _VLV_PLL_DW10_CH0 0x8048
1473#define _VLV_PLL_DW10_CH1 0x8068
1474#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001475
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001476#define _VLV_PLL_DW11_CH0 0x804c
1477#define _VLV_PLL_DW11_CH1 0x806c
1478#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001479
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001480/* Spec for ref block start counts at DW10 */
1481#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +02001482
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001483#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001484
Daniel Vetter598fac62013-04-18 22:01:46 +02001485/*
1486 * Per DDI channel DPIO regs
1487 */
1488
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001489#define _VLV_PCS_DW0_CH0 0x8200
1490#define _VLV_PCS_DW0_CH1 0x8400
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001491#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1492#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1493#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1494#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001495#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001496
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001497#define _VLV_PCS01_DW0_CH0 0x200
1498#define _VLV_PCS23_DW0_CH0 0x400
1499#define _VLV_PCS01_DW0_CH1 0x2600
1500#define _VLV_PCS23_DW0_CH1 0x2800
1501#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1502#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1503
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001504#define _VLV_PCS_DW1_CH0 0x8204
1505#define _VLV_PCS_DW1_CH1 0x8404
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001506#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1507#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1508#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
Daniel Vetter598fac62013-04-18 22:01:46 +02001509#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001510#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001511#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001512
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001513#define _VLV_PCS01_DW1_CH0 0x204
1514#define _VLV_PCS23_DW1_CH0 0x404
1515#define _VLV_PCS01_DW1_CH1 0x2604
1516#define _VLV_PCS23_DW1_CH1 0x2804
1517#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1518#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1519
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001520#define _VLV_PCS_DW8_CH0 0x8220
1521#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +03001522#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1523#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001524#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001525
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001526#define _VLV_PCS01_DW8_CH0 0x0220
1527#define _VLV_PCS23_DW8_CH0 0x0420
1528#define _VLV_PCS01_DW8_CH1 0x2620
1529#define _VLV_PCS23_DW8_CH1 0x2820
1530#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1531#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001532
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001533#define _VLV_PCS_DW9_CH0 0x8224
1534#define _VLV_PCS_DW9_CH1 0x8424
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001535#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1536#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1537#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1538#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1539#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1540#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001541#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001542
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001543#define _VLV_PCS01_DW9_CH0 0x224
1544#define _VLV_PCS23_DW9_CH0 0x424
1545#define _VLV_PCS01_DW9_CH1 0x2624
1546#define _VLV_PCS23_DW9_CH1 0x2824
1547#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1548#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1549
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001550#define _CHV_PCS_DW10_CH0 0x8228
1551#define _CHV_PCS_DW10_CH1 0x8428
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001552#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1553#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1554#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1555#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1556#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1557#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1558#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1559#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001560#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1561
Ville Syrjälä1966e592014-04-09 13:29:04 +03001562#define _VLV_PCS01_DW10_CH0 0x0228
1563#define _VLV_PCS23_DW10_CH0 0x0428
1564#define _VLV_PCS01_DW10_CH1 0x2628
1565#define _VLV_PCS23_DW10_CH1 0x2828
1566#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1567#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1568
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001569#define _VLV_PCS_DW11_CH0 0x822c
1570#define _VLV_PCS_DW11_CH1 0x842c
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001571#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1572#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1573#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1574#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001575#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001576
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001577#define _VLV_PCS01_DW11_CH0 0x022c
1578#define _VLV_PCS23_DW11_CH0 0x042c
1579#define _VLV_PCS01_DW11_CH1 0x262c
1580#define _VLV_PCS23_DW11_CH1 0x282c
Ville Syrjälä142d2ec2014-10-16 20:52:32 +03001581#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1582#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001583
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001584#define _VLV_PCS01_DW12_CH0 0x0230
1585#define _VLV_PCS23_DW12_CH0 0x0430
1586#define _VLV_PCS01_DW12_CH1 0x2630
1587#define _VLV_PCS23_DW12_CH1 0x2830
1588#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1589#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1590
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001591#define _VLV_PCS_DW12_CH0 0x8230
1592#define _VLV_PCS_DW12_CH1 0x8430
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001593#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1594#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1595#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1596#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1597#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001598#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001599
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001600#define _VLV_PCS_DW14_CH0 0x8238
1601#define _VLV_PCS_DW14_CH1 0x8438
1602#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001603
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001604#define _VLV_PCS_DW23_CH0 0x825c
1605#define _VLV_PCS_DW23_CH1 0x845c
1606#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001607
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001608#define _VLV_TX_DW2_CH0 0x8288
1609#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001610#define DPIO_SWING_MARGIN000_SHIFT 16
1611#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001612#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001613#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001614
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001615#define _VLV_TX_DW3_CH0 0x828c
1616#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001617/* The following bit for CHV phy */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001618#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001619#define DPIO_SWING_MARGIN101_SHIFT 16
1620#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001621#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1622
1623#define _VLV_TX_DW4_CH0 0x8290
1624#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001625#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1626#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001627#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1628#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001629#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1630
1631#define _VLV_TX3_DW4_CH0 0x690
1632#define _VLV_TX3_DW4_CH1 0x2a90
1633#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1634
1635#define _VLV_TX_DW5_CH0 0x8294
1636#define _VLV_TX_DW5_CH1 0x8494
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001637#define DPIO_TX_OCALINIT_EN (1 << 31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001638#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001639
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001640#define _VLV_TX_DW11_CH0 0x82ac
1641#define _VLV_TX_DW11_CH1 0x84ac
1642#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001643
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001644#define _VLV_TX_DW14_CH0 0x82b8
1645#define _VLV_TX_DW14_CH1 0x84b8
1646#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301647
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001648/* CHV dpPhy registers */
1649#define _CHV_PLL_DW0_CH0 0x8000
1650#define _CHV_PLL_DW0_CH1 0x8180
1651#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1652
1653#define _CHV_PLL_DW1_CH0 0x8004
1654#define _CHV_PLL_DW1_CH1 0x8184
1655#define DPIO_CHV_N_DIV_SHIFT 8
1656#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1657#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1658
1659#define _CHV_PLL_DW2_CH0 0x8008
1660#define _CHV_PLL_DW2_CH1 0x8188
1661#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1662
1663#define _CHV_PLL_DW3_CH0 0x800c
1664#define _CHV_PLL_DW3_CH1 0x818c
1665#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1666#define DPIO_CHV_FIRST_MOD (0 << 8)
1667#define DPIO_CHV_SECOND_MOD (1 << 8)
1668#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05301669#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001670#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1671
1672#define _CHV_PLL_DW6_CH0 0x8018
1673#define _CHV_PLL_DW6_CH1 0x8198
1674#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1675#define DPIO_CHV_INT_COEFF_SHIFT 8
1676#define DPIO_CHV_PROP_COEFF_SHIFT 0
1677#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1678
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301679#define _CHV_PLL_DW8_CH0 0x8020
1680#define _CHV_PLL_DW8_CH1 0x81A0
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05301681#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1682#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301683#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1684
1685#define _CHV_PLL_DW9_CH0 0x8024
1686#define _CHV_PLL_DW9_CH1 0x81A4
1687#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05301688#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301689#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1690#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1691
Ville Syrjälä6669e392015-07-08 23:46:00 +03001692#define _CHV_CMN_DW0_CH0 0x8100
1693#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1694#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1695#define DPIO_ALLDL_POWERDOWN (1 << 1)
1696#define DPIO_ANYDL_POWERDOWN (1 << 0)
1697
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001698#define _CHV_CMN_DW5_CH0 0x8114
1699#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1700#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1701#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1702#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1703#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1704#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1705#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1706#define CHV_BUFLEFTENA1_MASK (3 << 22)
1707
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001708#define _CHV_CMN_DW13_CH0 0x8134
1709#define _CHV_CMN_DW0_CH1 0x8080
1710#define DPIO_CHV_S1_DIV_SHIFT 21
1711#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1712#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1713#define DPIO_CHV_K_DIV_SHIFT 4
1714#define DPIO_PLL_FREQLOCK (1 << 1)
1715#define DPIO_PLL_LOCK (1 << 0)
1716#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1717
1718#define _CHV_CMN_DW14_CH0 0x8138
1719#define _CHV_CMN_DW1_CH1 0x8084
1720#define DPIO_AFC_RECAL (1 << 14)
1721#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001722#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1723#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1724#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1725#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1726#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1727#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1728#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1729#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001730#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1731
Ville Syrjälä9197c882014-04-09 13:29:05 +03001732#define _CHV_CMN_DW19_CH0 0x814c
1733#define _CHV_CMN_DW6_CH1 0x8098
Ville Syrjälä6669e392015-07-08 23:46:00 +03001734#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1735#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001736#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
Ville Syrjälä9197c882014-04-09 13:29:05 +03001737#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001738
Ville Syrjälä9197c882014-04-09 13:29:05 +03001739#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1740
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001741#define CHV_CMN_DW28 0x8170
1742#define DPIO_CL1POWERDOWNEN (1 << 23)
1743#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
Ville Syrjäläee279212015-07-08 23:45:57 +03001744#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1745#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1746#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1747#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001748
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001749#define CHV_CMN_DW30 0x8178
Ville Syrjälä3e288782015-07-08 23:45:58 +03001750#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001751#define DPIO_LRC_BYPASS (1 << 3)
1752
1753#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1754 (lane) * 0x200 + (offset))
1755
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001756#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1757#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1758#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1759#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1760#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1761#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1762#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1763#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1764#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1765#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1766#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001767#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1768#define DPIO_FRC_LATENCY_SHFIT 8
1769#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1770#define DPIO_UPAR_SHIFT 30
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301771
1772/* BXT PHY registers */
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001773#define _BXT_PHY0_BASE 0x6C000
1774#define _BXT_PHY1_BASE 0x162000
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001775#define _BXT_PHY2_BASE 0x163000
1776#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1777 _BXT_PHY1_BASE, \
1778 _BXT_PHY2_BASE)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001779
1780#define _BXT_PHY(phy, reg) \
1781 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1782
1783#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1784 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1785 (reg_ch1) - _BXT_PHY0_BASE))
1786#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1787 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301788
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001789#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
Uma Shankar1881a422017-01-25 19:43:23 +05301790#define MIPIO_RST_CTRL (1 << 2)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301791
Imre Deake93da0a2016-06-13 16:44:37 +03001792#define _BXT_PHY_CTL_DDI_A 0x64C00
1793#define _BXT_PHY_CTL_DDI_B 0x64C10
1794#define _BXT_PHY_CTL_DDI_C 0x64C20
1795#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1796#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1797#define BXT_PHY_LANE_ENABLED (1 << 8)
1798#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1799 _BXT_PHY_CTL_DDI_B)
1800
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301801#define _PHY_CTL_FAMILY_EDP 0x64C80
1802#define _PHY_CTL_FAMILY_DDI 0x64C90
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001803#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301804#define COMMON_RESET_DIS (1 << 31)
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001805#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1806 _PHY_CTL_FAMILY_EDP, \
1807 _PHY_CTL_FAMILY_DDI_C)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301808
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301809/* BXT PHY PLL registers */
1810#define _PORT_PLL_A 0x46074
1811#define _PORT_PLL_B 0x46078
1812#define _PORT_PLL_C 0x4607c
1813#define PORT_PLL_ENABLE (1 << 31)
1814#define PORT_PLL_LOCK (1 << 30)
1815#define PORT_PLL_REF_SEL (1 << 27)
Madhav Chauhanf7044dd2016-12-02 10:23:53 +02001816#define PORT_PLL_POWER_ENABLE (1 << 26)
1817#define PORT_PLL_POWER_STATE (1 << 25)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001818#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301819
1820#define _PORT_PLL_EBB_0_A 0x162034
1821#define _PORT_PLL_EBB_0_B 0x6C034
1822#define _PORT_PLL_EBB_0_C 0x6C340
Imre Deakaa610dc2015-06-22 23:35:52 +03001823#define PORT_PLL_P1_SHIFT 13
1824#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1825#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1826#define PORT_PLL_P2_SHIFT 8
1827#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1828#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001829#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1830 _PORT_PLL_EBB_0_B, \
1831 _PORT_PLL_EBB_0_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301832
1833#define _PORT_PLL_EBB_4_A 0x162038
1834#define _PORT_PLL_EBB_4_B 0x6C038
1835#define _PORT_PLL_EBB_4_C 0x6C344
1836#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1837#define PORT_PLL_RECALIBRATE (1 << 14)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001838#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1839 _PORT_PLL_EBB_4_B, \
1840 _PORT_PLL_EBB_4_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301841
1842#define _PORT_PLL_0_A 0x162100
1843#define _PORT_PLL_0_B 0x6C100
1844#define _PORT_PLL_0_C 0x6C380
1845/* PORT_PLL_0_A */
1846#define PORT_PLL_M2_MASK 0xFF
1847/* PORT_PLL_1_A */
Imre Deakaa610dc2015-06-22 23:35:52 +03001848#define PORT_PLL_N_SHIFT 8
1849#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1850#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301851/* PORT_PLL_2_A */
1852#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1853/* PORT_PLL_3_A */
1854#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1855/* PORT_PLL_6_A */
1856#define PORT_PLL_PROP_COEFF_MASK 0xF
1857#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1858#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1859#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1860#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1861/* PORT_PLL_8_A */
1862#define PORT_PLL_TARGET_CNT_MASK 0x3FF
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301863/* PORT_PLL_9_A */
Imre Deak05712c12015-06-18 17:25:54 +03001864#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1865#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301866/* PORT_PLL_10_A */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001867#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
Vandana Kannane6292552015-07-01 17:02:57 +05301868#define PORT_PLL_DCO_AMP_DEFAULT 15
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301869#define PORT_PLL_DCO_AMP_MASK 0x3c00
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07001870#define PORT_PLL_DCO_AMP(x) ((x) << 10)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001871#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1872 _PORT_PLL_0_B, \
1873 _PORT_PLL_0_C)
1874#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1875 (idx) * 4)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301876
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301877/* BXT PHY common lane registers */
1878#define _PORT_CL1CM_DW0_A 0x162000
1879#define _PORT_CL1CM_DW0_BC 0x6C000
1880#define PHY_POWER_GOOD (1 << 16)
Vandana Kannanb61e7992016-03-31 23:15:54 +05301881#define PHY_RESERVED (1 << 7)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001882#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301883
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001884#define _PORT_CL1CM_DW9_A 0x162024
1885#define _PORT_CL1CM_DW9_BC 0x6C024
1886#define IREF0RC_OFFSET_SHIFT 8
1887#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1888#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07001889
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001890#define _PORT_CL1CM_DW10_A 0x162028
1891#define _PORT_CL1CM_DW10_BC 0x6C028
1892#define IREF1RC_OFFSET_SHIFT 8
1893#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1894#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1895
1896#define _PORT_CL1CM_DW28_A 0x162070
1897#define _PORT_CL1CM_DW28_BC 0x6C070
1898#define OCL1_POWER_DOWN_EN (1 << 23)
1899#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1900#define SUS_CLK_CONFIG 0x3
1901#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1902
1903#define _PORT_CL1CM_DW30_A 0x162078
1904#define _PORT_CL1CM_DW30_BC 0x6C078
1905#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1906#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1907
1908/*
Lucas De Marchia4d082f2021-07-28 14:59:45 -07001909 * ICL Port/COMBO-PHY Registers
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001910 */
Lucas De Marchi4e538402018-10-15 19:35:17 -07001911#define _ICL_COMBOPHY_A 0x162000
1912#define _ICL_COMBOPHY_B 0x6C000
Matt Roper0e933162019-06-25 17:03:49 -07001913#define _EHL_COMBOPHY_C 0x160000
Matt Roperaefaa1f2020-06-03 14:15:19 -07001914#define _RKL_COMBOPHY_D 0x161000
Anusha Srivatsaa84b4bd2021-01-25 06:07:47 -08001915#define _ADL_COMBOPHY_E 0x16B000
1916
Matt Roperdc867bc2019-07-09 11:39:32 -07001917#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
Matt Roper0e933162019-06-25 17:03:49 -07001918 _ICL_COMBOPHY_B, \
Matt Roperaefaa1f2020-06-03 14:15:19 -07001919 _EHL_COMBOPHY_C, \
Anusha Srivatsaa84b4bd2021-01-25 06:07:47 -08001920 _RKL_COMBOPHY_D, \
1921 _ADL_COMBOPHY_E)
Lucas De Marchi4e538402018-10-15 19:35:17 -07001922
Lucas De Marchia4d082f2021-07-28 14:59:45 -07001923/* ICL Port CL_DW registers */
Matt Roperdc867bc2019-07-09 11:39:32 -07001924#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07001925 4 * (dw))
1926
Matt Roperdc867bc2019-07-09 11:39:32 -07001927#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001928#define CL_POWER_DOWN_ENABLE (1 << 4)
1929#define SUS_CLOCK_CONFIG (3 << 0)
Paulo Zanoniad186f32018-02-05 13:40:43 -02001930
Matt Roperdc867bc2019-07-09 11:39:32 -07001931#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
Madhav Chauhan166869b2018-07-05 19:19:36 +05301932#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1933#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1934#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1935#define PWR_UP_ALL_LANES (0x0 << 4)
1936#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1937#define PWR_DOWN_LN_3_2 (0xc << 4)
1938#define PWR_DOWN_LN_3 (0x8 << 4)
1939#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1940#define PWR_DOWN_LN_1_0 (0x3 << 4)
Madhav Chauhan166869b2018-07-05 19:19:36 +05301941#define PWR_DOWN_LN_3_1 (0xa << 4)
1942#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1943#define PWR_DOWN_LN_MASK (0xf << 4)
1944#define PWR_DOWN_LN_SHIFT 4
José Roberto de Souza81619f42020-07-15 10:56:37 -07001945#define EDP4K2K_MODE_OVRD_EN (1 << 3)
1946#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
Madhav Chauhan166869b2018-07-05 19:19:36 +05301947
Matt Roperdc867bc2019-07-09 11:39:32 -07001948#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
Imre Deak67ca07e2018-06-26 17:22:32 +03001949#define ICL_LANE_ENABLE_AUX (1 << 0)
Imre Deak67ca07e2018-06-26 17:22:32 +03001950
Lucas De Marchia4d082f2021-07-28 14:59:45 -07001951/* ICL Port COMP_DW registers */
Lucas De Marchi4e538402018-10-15 19:35:17 -07001952#define _ICL_PORT_COMP 0x100
Matt Roperdc867bc2019-07-09 11:39:32 -07001953#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07001954 _ICL_PORT_COMP + 4 * (dw))
1955
Matt Roperdc867bc2019-07-09 11:39:32 -07001956#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
Matt Roper3f8210f2020-08-03 21:40:24 -07001957#define COMP_INIT (1 << 31)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301958
Matt Roperdc867bc2019-07-09 11:39:32 -07001959#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
Lucas De Marchi4e538402018-10-15 19:35:17 -07001960
Matt Roperdc867bc2019-07-09 11:39:32 -07001961#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001962#define PROCESS_INFO_DOT_0 (0 << 26)
1963#define PROCESS_INFO_DOT_1 (1 << 26)
1964#define PROCESS_INFO_DOT_4 (2 << 26)
1965#define PROCESS_INFO_MASK (7 << 26)
1966#define PROCESS_INFO_SHIFT 26
1967#define VOLTAGE_INFO_0_85V (0 << 24)
1968#define VOLTAGE_INFO_0_95V (1 << 24)
1969#define VOLTAGE_INFO_1_05V (2 << 24)
1970#define VOLTAGE_INFO_MASK (3 << 24)
1971#define VOLTAGE_INFO_SHIFT 24
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301972
Matt Roperdc867bc2019-07-09 11:39:32 -07001973#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
Imre Deak4361cca2019-05-24 20:35:32 +03001974#define IREFGEN (1 << 24)
1975
Matt Roperdc867bc2019-07-09 11:39:32 -07001976#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001977
Matt Roperdc867bc2019-07-09 11:39:32 -07001978#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
Mahesh Kumard72e84c2018-10-12 16:47:17 -07001979
Lucas De Marchia4d082f2021-07-28 14:59:45 -07001980/* ICL Port PCS registers */
Lucas De Marchi4e538402018-10-15 19:35:17 -07001981#define _ICL_PORT_PCS_AUX 0x300
1982#define _ICL_PORT_PCS_GRP 0x600
1983#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
Matt Roperdc867bc2019-07-09 11:39:32 -07001984#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07001985 _ICL_PORT_PCS_AUX + 4 * (dw))
Matt Roperdc867bc2019-07-09 11:39:32 -07001986#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07001987 _ICL_PORT_PCS_GRP + 4 * (dw))
Matt Roperdc867bc2019-07-09 11:39:32 -07001988#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07001989 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
Matt Roperdc867bc2019-07-09 11:39:32 -07001990#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1991#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
Ville Syrjäläe6908582021-10-06 23:49:25 +03001992#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
José Roberto de Souza239bef62020-06-25 12:52:52 -07001993#define DCC_MODE_SELECT_MASK (0x3 << 20)
1994#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
Rodrigo Vivi04416102017-06-09 15:26:06 -07001995#define COMMON_KEEPER_EN (1 << 26)
Vandita Kulkarni6a7bafe2019-06-19 16:31:33 -07001996#define LATENCY_OPTIM_MASK (0x3 << 2)
1997#define LATENCY_OPTIM_VAL(x) ((x) << 2)
Rodrigo Vivi04416102017-06-09 15:26:06 -07001998
Lucas De Marchia4d082f2021-07-28 14:59:45 -07001999/* ICL Port TX registers */
Lucas De Marchi4e538402018-10-15 19:35:17 -07002000#define _ICL_PORT_TX_AUX 0x380
2001#define _ICL_PORT_TX_GRP 0x680
2002#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
2003
Matt Roperdc867bc2019-07-09 11:39:32 -07002004#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07002005 _ICL_PORT_TX_AUX + 4 * (dw))
Matt Roperdc867bc2019-07-09 11:39:32 -07002006#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07002007 _ICL_PORT_TX_GRP + 4 * (dw))
Matt Roperdc867bc2019-07-09 11:39:32 -07002008#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
Lucas De Marchi4e538402018-10-15 19:35:17 -07002009 _ICL_PORT_TX_LN(ln) + 4 * (dw))
2010
Matt Roperdc867bc2019-07-09 11:39:32 -07002011#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2012#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
Ville Syrjäläe6908582021-10-06 23:49:25 +03002013#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
Paulo Zanoni74875082018-03-23 12:58:53 -07002014#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002015#define SWING_SEL_UPPER_MASK (1 << 15)
Paulo Zanoni74875082018-03-23 12:58:53 -07002016#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002017#define SWING_SEL_LOWER_MASK (0x7 << 11)
Madhav Chauhand61d1b32018-07-05 19:19:38 +05302018#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
2019#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002020#define RCOMP_SCALAR(x) ((x) << 0)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002021#define RCOMP_SCALAR_MASK (0xFF << 0)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002022
Matt Roperdc867bc2019-07-09 11:39:32 -07002023#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2024#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
Matt Roperdc867bc2019-07-09 11:39:32 -07002025#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
Rodrigo Vivi04416102017-06-09 15:26:06 -07002026#define LOADGEN_SELECT (1 << 31)
2027#define POST_CURSOR_1(x) ((x) << 12)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002028#define POST_CURSOR_1_MASK (0x3F << 12)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002029#define POST_CURSOR_2(x) ((x) << 6)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002030#define POST_CURSOR_2_MASK (0x3F << 6)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002031#define CURSOR_COEFF(x) ((x) << 0)
Navare, Manasi Dfcace3b2017-06-29 18:14:01 -07002032#define CURSOR_COEFF_MASK (0x3F << 0)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002033
Matt Roperdc867bc2019-07-09 11:39:32 -07002034#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2035#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
Ville Syrjäläe6908582021-10-06 23:49:25 +03002036#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
Rodrigo Vivi04416102017-06-09 15:26:06 -07002037#define TX_TRAINING_EN (1 << 31)
Manasi Navare5bb975d2018-03-23 10:24:13 -07002038#define TAP2_DISABLE (1 << 30)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002039#define TAP3_DISABLE (1 << 29)
2040#define SCALING_MODE_SEL(x) ((x) << 18)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002041#define SCALING_MODE_SEL_MASK (0x7 << 18)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002042#define RTERM_SELECT(x) ((x) << 3)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002043#define RTERM_SELECT_MASK (0x7 << 3)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002044
Matt Roperdc867bc2019-07-09 11:39:32 -07002045#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2046#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
Matt Roperdc867bc2019-07-09 11:39:32 -07002047#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
Rodrigo Vivi04416102017-06-09 15:26:06 -07002048#define N_SCALAR(x) ((x) << 24)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002049#define N_SCALAR_MASK (0x7F << 24)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002050
José Roberto de Souza239bef62020-06-25 12:52:52 -07002051#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
2052#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
Ville Syrjäläe6908582021-10-06 23:49:25 +03002053#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
José Roberto de Souza239bef62020-06-25 12:52:52 -07002054#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
2055#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
2056#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2057
José Roberto de Souza683d6722019-06-19 16:31:34 -07002058#define _ICL_DPHY_CHKN_REG 0x194
2059#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2060#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2061
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002062#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2063 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
Manasi Navarec92f47b2018-03-23 10:24:15 -07002064
Manasi Navarea38bb302018-07-13 12:43:13 -07002065#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
2066#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
2067#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
2068#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
2069#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
2070#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
2071#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
2072#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002073#define MG_TX1_LINK_PARAMS(ln, tc_port) \
2074 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2075 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2076 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002077
Manasi Navarea38bb302018-07-13 12:43:13 -07002078#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
2079#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
2080#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
2081#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
2082#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
2083#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
2084#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
2085#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002086#define MG_TX2_LINK_PARAMS(ln, tc_port) \
2087 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2088 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2089 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002090#define CRI_USE_FS32 (1 << 5)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002091
Manasi Navarea38bb302018-07-13 12:43:13 -07002092#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
2093#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
2094#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
2095#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
2096#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2097#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2098#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2099#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002100#define MG_TX1_PISO_READLOAD(ln, tc_port) \
2101 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2102 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2103 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002104
Manasi Navarea38bb302018-07-13 12:43:13 -07002105#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2106#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2107#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2108#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2109#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2110#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2111#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2112#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002113#define MG_TX2_PISO_READLOAD(ln, tc_port) \
2114 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2115 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2116 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002117#define CRI_CALCINIT (1 << 1)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002118
Manasi Navarea38bb302018-07-13 12:43:13 -07002119#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2120#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2121#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2122#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2123#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2124#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2125#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2126#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002127#define MG_TX1_SWINGCTRL(ln, tc_port) \
2128 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2129 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2130 MG_TX_SWINGCTRL_TX1LN1_PORT1)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002131
Manasi Navarea38bb302018-07-13 12:43:13 -07002132#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2133#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2134#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2135#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2136#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2137#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2138#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2139#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002140#define MG_TX2_SWINGCTRL(ln, tc_port) \
2141 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2142 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2143 MG_TX_SWINGCTRL_TX2LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002144#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2145#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002146
Manasi Navarea38bb302018-07-13 12:43:13 -07002147#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2148#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2149#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2150#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2151#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2152#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2153#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2154#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002155#define MG_TX1_DRVCTRL(ln, tc_port) \
2156 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2157 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2158 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002159
Manasi Navarea38bb302018-07-13 12:43:13 -07002160#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2161#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2162#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2163#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2164#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2165#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2166#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2167#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002168#define MG_TX2_DRVCTRL(ln, tc_port) \
2169 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2170 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2171 MG_TX_DRVCTRL_TX2LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002172#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2173#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2174#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2175#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2176#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2177#define CRI_LOADGEN_SEL(x) ((x) << 12)
2178#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2179
2180#define MG_CLKHUB_LN0_PORT1 0x16839C
2181#define MG_CLKHUB_LN1_PORT1 0x16879C
2182#define MG_CLKHUB_LN0_PORT2 0x16939C
2183#define MG_CLKHUB_LN1_PORT2 0x16979C
2184#define MG_CLKHUB_LN0_PORT3 0x16A39C
2185#define MG_CLKHUB_LN1_PORT3 0x16A79C
2186#define MG_CLKHUB_LN0_PORT4 0x16B39C
2187#define MG_CLKHUB_LN1_PORT4 0x16B79C
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002188#define MG_CLKHUB(ln, tc_port) \
2189 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2190 MG_CLKHUB_LN0_PORT2, \
2191 MG_CLKHUB_LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002192#define CFG_LOW_RATE_LKREN_EN (1 << 11)
2193
2194#define MG_TX_DCC_TX1LN0_PORT1 0x168110
2195#define MG_TX_DCC_TX1LN1_PORT1 0x168510
2196#define MG_TX_DCC_TX1LN0_PORT2 0x169110
2197#define MG_TX_DCC_TX1LN1_PORT2 0x169510
2198#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2199#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2200#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2201#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002202#define MG_TX1_DCC(ln, tc_port) \
2203 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2204 MG_TX_DCC_TX1LN0_PORT2, \
2205 MG_TX_DCC_TX1LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002206#define MG_TX_DCC_TX2LN0_PORT1 0x168090
2207#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2208#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2209#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2210#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2211#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2212#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2213#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002214#define MG_TX2_DCC(ln, tc_port) \
2215 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2216 MG_TX_DCC_TX2LN0_PORT2, \
2217 MG_TX_DCC_TX2LN1_PORT1)
Manasi Navarea38bb302018-07-13 12:43:13 -07002218#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2219#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2220#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
Manasi Navarec92f47b2018-03-23 10:24:15 -07002221
Paulo Zanoni340a44b2018-07-24 17:28:12 -07002222#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2223#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2224#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2225#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2226#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2227#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2228#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2229#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
José Roberto de Souzaf21e8b82019-10-01 12:37:29 -07002230#define MG_DP_MODE(ln, tc_port) \
2231 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2232 MG_DP_MODE_LN0_ACU_PORT2, \
2233 MG_DP_MODE_LN1_ACU_PORT1)
Paulo Zanoni340a44b2018-07-24 17:28:12 -07002234#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2235#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2236
Matt Roper29081002021-07-23 10:42:32 -07002237/*
2238 * DG2 SNPS PHY registers (TC1 = PHY_E)
2239 */
2240#define _SNPS_PHY_A_BASE 0x168000
2241#define _SNPS_PHY_B_BASE 0x169000
2242#define _SNPS_PHY(phy) _PHY(phy, \
2243 _SNPS_PHY_A_BASE, \
2244 _SNPS_PHY_B_BASE)
2245#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
2246 _SNPS_PHY_A_BASE + (reg))
2247#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
2248#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
2249 (reg) + (ln) * 0x10))
2250
2251#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
2252#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
2253#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
2254#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
2255#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
2256
2257#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
2258#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
Animesh Manna45cbbe52021-08-27 13:38:43 +03002259#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
Matt Roper29081002021-07-23 10:42:32 -07002260#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
2261#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
2262#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
Animesh Manna45cbbe52021-08-27 13:38:43 +03002263#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
Matt Roper29081002021-07-23 10:42:32 -07002264#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
Animesh Manna45cbbe52021-08-27 13:38:43 +03002265#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
2266#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
Matt Roper29081002021-07-23 10:42:32 -07002267#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
Jani Nikula61b98482021-12-02 16:44:56 +02002268#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
Matt Roper29081002021-07-23 10:42:32 -07002269
2270#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
2271#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
2272#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
2273#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
2274
2275#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
2276#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
2277#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
2278
2279#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
2280#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
Matt Roper865b73e2021-07-23 10:42:33 -07002281#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
Matt Roper29081002021-07-23 10:42:32 -07002282#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
2283
2284#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
2285#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
2286
2287#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
Matt Roper865b73e2021-07-23 10:42:33 -07002288#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
2289#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
Matt Roper29081002021-07-23 10:42:32 -07002290#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
2291#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
2292
2293#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
2294#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
2295
Gwan-gyeong Mun77117492021-07-23 10:42:37 -07002296#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
2297#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
2298
Matt Ropera046a0d2021-07-23 10:42:34 -07002299#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
2300#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
2301#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
2302#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
2303
Ander Conselvan de Oliveira842d4162016-10-06 19:22:20 +03002304/* The spec defines this only for BXT PHY0, but lets assume that this
2305 * would exist for PHY1 too if it had a second channel.
2306 */
2307#define _PORT_CL2CM_DW6_A 0x162358
2308#define _PORT_CL2CM_DW6_BC 0x6C358
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002309#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302310#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2311
Anusha Srivatsaa6576a82018-11-01 11:55:57 -07002312#define FIA1_BASE 0x163000
Anusha Srivatsa0caf6252019-07-11 22:57:05 -07002313#define FIA2_BASE 0x16E000
2314#define FIA3_BASE 0x16F000
2315#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2316#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
Anusha Srivatsaa6576a82018-11-01 11:55:57 -07002317
Manasi Navarea2bc69a2018-05-25 12:03:52 -07002318/* ICL PHY DFLEX registers */
José Roberto de Souza31d9ae92019-09-20 13:58:06 -07002319#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2320#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
2321#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
2322#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
2323#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
2324#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
2325#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
Manasi Navarea2bc69a2018-05-25 12:03:52 -07002326
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302327/* BXT PHY Ref registers */
2328#define _PORT_REF_DW3_A 0x16218C
2329#define _PORT_REF_DW3_BC 0x6C18C
2330#define GRC_DONE (1 << 22)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002331#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302332
2333#define _PORT_REF_DW6_A 0x162198
2334#define _PORT_REF_DW6_BC 0x6C198
Imre Deakd1e082f2016-04-01 16:02:33 +03002335#define GRC_CODE_SHIFT 24
2336#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302337#define GRC_CODE_FAST_SHIFT 16
Imre Deakd1e082f2016-04-01 16:02:33 +03002338#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302339#define GRC_CODE_SLOW_SHIFT 8
2340#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2341#define GRC_CODE_NOM_MASK 0xFF
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002342#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302343
2344#define _PORT_REF_DW8_A 0x1621A0
2345#define _PORT_REF_DW8_BC 0x6C1A0
2346#define GRC_DIS (1 << 15)
2347#define GRC_RDY_OVRD (1 << 1)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002348#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302349
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302350/* BXT PHY PCS registers */
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302351#define _PORT_PCS_DW10_LN01_A 0x162428
2352#define _PORT_PCS_DW10_LN01_B 0x6C428
2353#define _PORT_PCS_DW10_LN01_C 0x6C828
2354#define _PORT_PCS_DW10_GRP_A 0x162C28
2355#define _PORT_PCS_DW10_GRP_B 0x6CC28
2356#define _PORT_PCS_DW10_GRP_C 0x6CE28
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002357#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2358 _PORT_PCS_DW10_LN01_B, \
2359 _PORT_PCS_DW10_LN01_C)
2360#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2361 _PORT_PCS_DW10_GRP_B, \
2362 _PORT_PCS_DW10_GRP_C)
2363
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302364#define TX2_SWING_CALC_INIT (1 << 31)
2365#define TX1_SWING_CALC_INIT (1 << 30)
2366
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302367#define _PORT_PCS_DW12_LN01_A 0x162430
2368#define _PORT_PCS_DW12_LN01_B 0x6C430
2369#define _PORT_PCS_DW12_LN01_C 0x6C830
2370#define _PORT_PCS_DW12_LN23_A 0x162630
2371#define _PORT_PCS_DW12_LN23_B 0x6C630
2372#define _PORT_PCS_DW12_LN23_C 0x6CA30
2373#define _PORT_PCS_DW12_GRP_A 0x162c30
2374#define _PORT_PCS_DW12_GRP_B 0x6CC30
2375#define _PORT_PCS_DW12_GRP_C 0x6CE30
2376#define LANESTAGGER_STRAP_OVRD (1 << 6)
2377#define LANE_STAGGER_MASK 0x1F
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002378#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2379 _PORT_PCS_DW12_LN01_B, \
2380 _PORT_PCS_DW12_LN01_C)
2381#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2382 _PORT_PCS_DW12_LN23_B, \
2383 _PORT_PCS_DW12_LN23_C)
2384#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2385 _PORT_PCS_DW12_GRP_B, \
2386 _PORT_PCS_DW12_GRP_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302387
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302388/* BXT PHY TX registers */
2389#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2390 ((lane) & 1) * 0x80)
2391
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302392#define _PORT_TX_DW2_LN0_A 0x162508
2393#define _PORT_TX_DW2_LN0_B 0x6C508
2394#define _PORT_TX_DW2_LN0_C 0x6C908
2395#define _PORT_TX_DW2_GRP_A 0x162D08
2396#define _PORT_TX_DW2_GRP_B 0x6CD08
2397#define _PORT_TX_DW2_GRP_C 0x6CF08
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002398#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2399 _PORT_TX_DW2_LN0_B, \
2400 _PORT_TX_DW2_LN0_C)
2401#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2402 _PORT_TX_DW2_GRP_B, \
2403 _PORT_TX_DW2_GRP_C)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302404#define MARGIN_000_SHIFT 16
2405#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2406#define UNIQ_TRANS_SCALE_SHIFT 8
2407#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2408
2409#define _PORT_TX_DW3_LN0_A 0x16250C
2410#define _PORT_TX_DW3_LN0_B 0x6C50C
2411#define _PORT_TX_DW3_LN0_C 0x6C90C
2412#define _PORT_TX_DW3_GRP_A 0x162D0C
2413#define _PORT_TX_DW3_GRP_B 0x6CD0C
2414#define _PORT_TX_DW3_GRP_C 0x6CF0C
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002415#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2416 _PORT_TX_DW3_LN0_B, \
2417 _PORT_TX_DW3_LN0_C)
2418#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2419 _PORT_TX_DW3_GRP_B, \
2420 _PORT_TX_DW3_GRP_C)
Sonika Jindal9c58a042015-09-24 10:22:54 +05302421#define SCALE_DCOMP_METHOD (1 << 26)
2422#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302423
2424#define _PORT_TX_DW4_LN0_A 0x162510
2425#define _PORT_TX_DW4_LN0_B 0x6C510
2426#define _PORT_TX_DW4_LN0_C 0x6C910
2427#define _PORT_TX_DW4_GRP_A 0x162D10
2428#define _PORT_TX_DW4_GRP_B 0x6CD10
2429#define _PORT_TX_DW4_GRP_C 0x6CF10
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002430#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2431 _PORT_TX_DW4_LN0_B, \
2432 _PORT_TX_DW4_LN0_C)
2433#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2434 _PORT_TX_DW4_GRP_B, \
2435 _PORT_TX_DW4_GRP_C)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302436#define DEEMPH_SHIFT 24
2437#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2438
Ander Conselvan de Oliveira51b3ee32016-12-02 10:23:52 +02002439#define _PORT_TX_DW5_LN0_A 0x162514
2440#define _PORT_TX_DW5_LN0_B 0x6C514
2441#define _PORT_TX_DW5_LN0_C 0x6C914
2442#define _PORT_TX_DW5_GRP_A 0x162D14
2443#define _PORT_TX_DW5_GRP_B 0x6CD14
2444#define _PORT_TX_DW5_GRP_C 0x6CF14
2445#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2446 _PORT_TX_DW5_LN0_B, \
2447 _PORT_TX_DW5_LN0_C)
2448#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2449 _PORT_TX_DW5_GRP_B, \
2450 _PORT_TX_DW5_GRP_C)
2451#define DCC_DELAY_RANGE_1 (1 << 9)
2452#define DCC_DELAY_RANGE_2 (1 << 8)
2453
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302454#define _PORT_TX_DW14_LN0_A 0x162538
2455#define _PORT_TX_DW14_LN0_B 0x6C538
2456#define _PORT_TX_DW14_LN0_C 0x6C938
2457#define LATENCY_OPTIM_SHIFT 30
2458#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002459#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2460 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2461 _PORT_TX_DW14_LN0_C) + \
2462 _BXT_LANE_OFFSET(lane))
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302463
David Weinehallf8896f52015-06-25 11:11:03 +03002464/* UAIMI scratch pad register 1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002465#define UAIMI_SPR1 _MMIO(0x4F074)
David Weinehallf8896f52015-06-25 11:11:03 +03002466/* SKL VccIO mask */
2467#define SKL_VCCIO_MASK 0x1
2468/* SKL balance leg register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002469#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
David Weinehallf8896f52015-06-25 11:11:03 +03002470/* I_boost values */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002471#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2472#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
David Weinehallf8896f52015-06-25 11:11:03 +03002473/* Balance leg disable bits */
2474#define BALANCE_LEG_DISABLE_SHIFT 23
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03002475#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
David Weinehallf8896f52015-06-25 11:11:03 +03002476
Jesse Barnes585fb112008-07-29 11:54:06 -07002477/*
Jesse Barnesde151cf2008-11-12 10:03:55 -08002478 * Fence registers
Ville Syrjäläeecf6132015-09-21 18:05:14 +03002479 * [0-7] @ 0x2000 gen2,gen3
2480 * [8-15] @ 0x3000 945,g33,pnv
2481 *
2482 * [0-15] @ 0x3000 gen4,gen5
2483 *
2484 * [0-15] @ 0x100000 gen6,vlv,chv
2485 * [0-31] @ 0x100000 gen7+
Jesse Barnesde151cf2008-11-12 10:03:55 -08002486 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002487#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002488#define I830_FENCE_START_MASK 0x07f80000
2489#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -08002490#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002491#define I830_FENCE_PITCH_SHIFT 4
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002492#define I830_FENCE_REG_VALID (1 << 0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02002493#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07002494#define I830_FENCE_MAX_PITCH_VAL 6
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002495#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002496
2497#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08002498#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002499
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002500#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2501#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002502#define I965_FENCE_PITCH_SHIFT 2
2503#define I965_FENCE_TILING_Y_SHIFT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002504#define I965_FENCE_REG_VALID (1 << 0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002505#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08002506
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002507#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2508#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
Ville Syrjäläeecf6132015-09-21 18:05:14 +03002509#define GEN6_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03002510#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07002511
Deepak S2b6b3a02014-05-27 15:59:30 +05302512
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002513/* control register for cpu gtt access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002514#define TILECTL _MMIO(0x101000)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002515#define TILECTL_SWZCTL (1 << 0)
Robert Beckette3a29052015-03-11 10:28:25 +02002516#define TILECTL_TLBPF (1 << 1)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002517#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2518#define TILECTL_BACKSNOOP_DIS (1 << 3)
2519
Jesse Barnesde151cf2008-11-12 10:03:55 -08002520/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002521 * Instruction and interrupt control regs
2522 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002523#define PGTBL_CTL _MMIO(0x02020)
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03002524#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2525#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002526#define PGTBL_ER _MMIO(0x02024)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002527#define PRB0_BASE (0x2030 - 0x30)
2528#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2529#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2530#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2531#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2532#define SRB2_BASE (0x2120 - 0x30) /* 830 */
2533#define SRB3_BASE (0x2130 - 0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02002534#define RENDER_RING_BASE 0x02000
2535#define BSD_RING_BASE 0x04000
2536#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08002537#define GEN8_BSD2_RING_BASE 0x1c000
Oscar Mateo5f79e7c2018-03-02 18:14:57 +02002538#define GEN11_BSD_RING_BASE 0x1c0000
2539#define GEN11_BSD2_RING_BASE 0x1c4000
2540#define GEN11_BSD3_RING_BASE 0x1d0000
2541#define GEN11_BSD4_RING_BASE 0x1d4000
John Harrison938c7782021-07-23 12:10:24 -07002542#define XEHP_BSD5_RING_BASE 0x1e0000
2543#define XEHP_BSD6_RING_BASE 0x1e4000
2544#define XEHP_BSD7_RING_BASE 0x1f0000
2545#define XEHP_BSD8_RING_BASE 0x1f4000
Ben Widawsky1950de12013-05-28 19:22:20 -07002546#define VEBOX_RING_BASE 0x1a000
Oscar Mateo5f79e7c2018-03-02 18:14:57 +02002547#define GEN11_VEBOX_RING_BASE 0x1c8000
2548#define GEN11_VEBOX2_RING_BASE 0x1d8000
John Harrison938c7782021-07-23 12:10:24 -07002549#define XEHP_VEBOX3_RING_BASE 0x1e8000
2550#define XEHP_VEBOX4_RING_BASE 0x1f8000
Chris Wilson549f7362010-10-19 11:19:32 +01002551#define BLT_RING_BASE 0x22000
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002552#define RING_TAIL(base) _MMIO((base) + 0x30)
2553#define RING_HEAD(base) _MMIO((base) + 0x34)
2554#define RING_START(base) _MMIO((base) + 0x38)
2555#define RING_CTL(base) _MMIO((base) + 0x3c)
Chris Wilson62ae14b2016-10-04 21:11:25 +01002556#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002557#define RING_SYNC_0(base) _MMIO((base) + 0x40)
2558#define RING_SYNC_1(base) _MMIO((base) + 0x44)
2559#define RING_SYNC_2(base) _MMIO((base) + 0x48)
Ben Widawsky1950de12013-05-28 19:22:20 -07002560#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2561#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2562#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2563#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2564#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2565#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2566#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2567#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2568#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2569#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2570#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2571#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002572#define GEN6_NOSYNC INVALID_MMIO_REG
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002573#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2574#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2575#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
Stuart Summersda9427502020-10-14 12:19:34 -07002576#define RING_ID(base) _MMIO((base) + 0x8c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002577#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
Ayaz A Siddiquid79a1d72021-09-03 14:51:50 +05302578
2579#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
2580/*
2581 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
2582 * The lsb of each can be considered a separate enabling bit for encryption.
2583 * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
2584 * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
2585 * 15:14 == Reserved => 31:30 are set to 0.
2586 */
2587#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
2588#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
2589#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
2590 CMD_CCTL_READ_OVERRIDE_MASK)
2591#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
2592 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
2593 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
2594
Ayaz A Siddiquic6b24842021-09-03 14:51:51 +05302595#define BLIT_CCTL(base) _MMIO((base) + 0x204)
2596#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
2597#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
2598#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
2599 BLIT_CCTL_SRC_MOCS_MASK)
2600#define BLIT_CCTL_MOCS(dst, src) \
2601 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
2602 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
2603
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002604#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
Mika Kuoppala5ce5f612019-04-12 19:53:53 +03002605#define RESET_CTL_CAT_ERROR REG_BIT(2)
2606#define RESET_CTL_READY_TO_RESET REG_BIT(1)
2607#define RESET_CTL_REQUEST_RESET REG_BIT(0)
2608
Mika Kuoppala39e78232018-06-07 20:24:44 +03002609#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
Imre Deak9e72b462014-05-05 15:13:55 +03002610
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002611#define HSW_GTT_CACHE_EN _MMIO(0x4024)
Ville Syrjälä6d50b062015-05-19 20:32:57 +03002612#define GTT_CACHE_EN_ALL 0xF0007FFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002613#define GEN7_WR_WATERMARK _MMIO(0x4028)
2614#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2615#define ARB_MODE _MMIO(0x4030)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002616#define ARB_MODE_SWIZZLE_SNB (1 << 4)
2617#define ARB_MODE_SWIZZLE_IVB (1 << 5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002618#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2619#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
Imre Deak9e72b462014-05-05 15:13:55 +03002620/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002621#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03002622#define GEN7_LRA_LIMITS_REG_NUM 13
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002623#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2624#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
Imre Deak9e72b462014-05-05 15:13:55 +03002625
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002626#define GAMTARBMODE _MMIO(0x04a08)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002627#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2628#define ARB_MODE_SWIZZLE_BDW (1 << 1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002629#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
Lucas De Marchi816753c2021-07-22 17:25:51 -07002630
2631#define _RING_FAULT_REG_RCS 0x4094
2632#define _RING_FAULT_REG_VCS 0x4194
2633#define _RING_FAULT_REG_BCS 0x4294
2634#define _RING_FAULT_REG_VECS 0x4394
2635#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
2636 _RING_FAULT_REG_RCS, \
2637 _RING_FAULT_REG_VCS, \
2638 _RING_FAULT_REG_VECS, \
2639 _RING_FAULT_REG_BCS))
Michel Thierryb03ec3d2017-11-13 09:36:28 -08002640#define GEN8_RING_FAULT_REG _MMIO(0x4094)
Lucas De Marchi91b59cd2019-07-30 11:04:03 -07002641#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
Michel Thierryb03ec3d2017-11-13 09:36:28 -08002642#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002643#define RING_FAULT_GTTSEL_MASK (1 << 11)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002644#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2645#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002646#define RING_FAULT_VALID (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002647#define DONE_REG _MMIO(0x40b0)
Mika Kuoppala811bb3d2019-10-29 18:38:41 +02002648#define GEN12_GAM_DONE _MMIO(0xcf68)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002649#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2650#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002651#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
Michel Thierryb41e63d2019-08-17 02:38:54 -07002652#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002653#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
Mika Kuoppalad248b372020-05-06 19:53:10 +03002654#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
Mika Kuoppala972282c2020-05-07 17:20:45 +03002655#define GEN12_VD0_AUX_NV _MMIO(0x4218)
2656#define GEN12_VD1_AUX_NV _MMIO(0x4228)
2657#define GEN12_VD2_AUX_NV _MMIO(0x4298)
2658#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
2659#define GEN12_VE0_AUX_NV _MMIO(0x4238)
2660#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
Mika Kuoppalad248b372020-05-06 19:53:10 +03002661#define AUX_INV REG_BIT(0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002662#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2663#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002664#define RING_ACTHD(base) _MMIO((base) + 0x74)
2665#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2666#define RING_NOPID(base) _MMIO((base) + 0x94)
2667#define RING_IMR(base) _MMIO((base) + 0xa8)
2668#define RING_HWSTAM(base) _MMIO((base) + 0x98)
2669#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2670#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002671#define TAIL_ADDR 0x001FFFF8
2672#define HEAD_WRAP_COUNT 0xFFE00000
2673#define HEAD_WRAP_ONE 0x00200000
2674#define HEAD_ADDR 0x001FFFFC
2675#define RING_NR_PAGES 0x001FF000
2676#define RING_REPORT_MASK 0x00000006
2677#define RING_REPORT_64K 0x00000002
2678#define RING_REPORT_128K 0x00000004
2679#define RING_NO_REPORT 0x00000000
2680#define RING_VALID_MASK 0x00000001
2681#define RING_VALID 0x00000001
2682#define RING_INVALID 0x00000000
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002683#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2684#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2685#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03002686
Umesh Nerlige Ramappab3f74932022-01-10 17:55:23 -08002687#define MISC_STATUS0 _MMIO(0xA500)
2688#define MISC_STATUS1 _MMIO(0xA504)
Umesh Nerlige Ramappa77cdd052021-10-26 17:48:21 -07002689
Michał Winiarski74b20892019-09-26 12:06:33 +02002690/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2691#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
2692#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
2693
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002694#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
Mika Kuoppala6b441c62019-10-24 14:03:31 +03002695#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
John Harrison1e2b7f42019-07-12 00:07:43 -07002696#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
2697#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2698#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2699#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2700#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
John Harrison5380d0b2019-06-17 18:01:05 -07002701#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
2702#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2703#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2704#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
John Harrison1e2b7f42019-07-12 00:07:43 -07002705#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2706#define RING_FORCE_TO_NONPRIV_MASK_VALID \
2707 (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2708 | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
Arun Siluvery33136b02016-01-21 21:43:47 +00002709#define RING_MAX_NONPRIV_SLOTS 12
2710
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002711#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
Imre Deak9e72b462014-05-05 15:13:55 +03002712
Mika Kuoppala4ba9c1f2016-07-20 14:26:12 +03002713#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002714#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
Mika Kuoppala4ba9c1f2016-07-20 14:26:12 +03002715
Matthew Auld9a6330c2017-10-06 23:18:22 +01002716#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2717#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
Mika Kuoppala85f04aa2018-11-09 16:53:32 +02002718#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
Matthew Auld9a6330c2017-10-06 23:18:22 +01002719
Mika Kuoppalac0b730d2016-06-07 17:19:06 +03002720#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
Oscar Mateo4ece66b2018-05-25 15:05:39 -07002721#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2722#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2723#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
Mika Kuoppalac0b730d2016-06-07 17:19:06 +03002724
Tvrtko Ursulin7938d612021-10-19 13:27:10 +01002725#define GEN8_RTCR _MMIO(0x4260)
2726#define GEN8_M1TCR _MMIO(0x4264)
2727#define GEN8_M2TCR _MMIO(0x4268)
2728#define GEN8_BTCR _MMIO(0x426c)
2729#define GEN8_VTCR _MMIO(0x4270)
2730
Chris Wilson8168bd42010-11-11 17:54:52 +00002731#if 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002732#define PRB0_TAIL _MMIO(0x2030)
2733#define PRB0_HEAD _MMIO(0x2034)
2734#define PRB0_START _MMIO(0x2038)
2735#define PRB0_CTL _MMIO(0x203c)
2736#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2737#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2738#define PRB1_START _MMIO(0x2048) /* 915+ only */
2739#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00002740#endif
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002741#define IPEIR_I965 _MMIO(0x2064)
2742#define IPEHR_I965 _MMIO(0x2068)
2743#define GEN7_SC_INSTDONE _MMIO(0x7100)
Lionel Landwerlinf7043102020-01-29 20:16:38 +02002744#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
2745#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002746#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2747#define GEN7_ROW_INSTDONE _MMIO(0xe164)
Matt Roper89f2e7a2021-08-05 09:36:41 -07002748#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
Matt Roper927dfdd2021-07-29 09:59:55 -07002749#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
2750#define SF_MCR_SELECTOR _MMIO(0xfd8)
Ben Widawskyf9e61372016-09-20 16:54:33 +03002751#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2752#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2753#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2754#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2755#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
Kelvin Gardinerd3d57922018-03-16 14:14:51 +02002756#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2757#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2758#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2759#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002760#define RING_IPEIR(base) _MMIO((base) + 0x64)
2761#define RING_IPEHR(base) _MMIO((base) + 0x68)
Chris Wilson70a76a92020-01-28 20:43:15 +00002762#define RING_EIR(base) _MMIO((base) + 0xb0)
2763#define RING_EMR(base) _MMIO((base) + 0xb4)
2764#define RING_ESR(base) _MMIO((base) + 0xb8)
Imre Deakf1d54342015-09-30 23:00:42 +03002765/*
2766 * On GEN4, only the render ring INSTDONE exists and has a different
2767 * layout than the GEN7+ version.
Imre Deakbd93a502015-09-30 23:00:43 +03002768 * The GEN2 counterpart of this register is GEN2_INSTDONE.
Imre Deakf1d54342015-09-30 23:00:42 +03002769 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002770#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2771#define RING_INSTPS(base) _MMIO((base) + 0x70)
2772#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2773#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2774#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2775#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
Mika Kuoppalab8a11812020-04-25 02:06:32 +03002776#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002777#define INSTPS _MMIO(0x2070) /* 965+ only */
2778#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2779#define ACTHD_I965 _MMIO(0x2074)
2780#define HWS_PGA _MMIO(0x2080)
Jesse Barnes585fb112008-07-29 11:54:06 -07002781#define HWS_ADDRESS_MASK 0xfffff000
2782#define HWS_START_ADDRESS_SHIFT 4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002783#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002784#define PWRCTX_EN (1 << 0)
Daniele Ceraolo Spuriobaba6e52019-03-25 14:49:40 -07002785#define IPEIR(base) _MMIO((base) + 0x88)
2786#define IPEHR(base) _MMIO((base) + 0x8c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002787#define GEN2_INSTDONE _MMIO(0x2090)
2788#define NOPID _MMIO(0x2094)
2789#define HWSTAM _MMIO(0x2098)
Daniele Ceraolo Spuriobaba6e52019-03-25 14:49:40 -07002790#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002791#define RING_BBSTATE(base) _MMIO((base) + 0x110)
Ville Syrjälä35dc3f92015-11-04 23:20:10 +02002792#define RING_BB_PPGTT (1 << 5)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002793#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2794#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2795#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2796#define RING_BBADDR(base) _MMIO((base) + 0x140)
2797#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2798#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2799#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2800#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2801#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08002802
Swathi Dhanavanthricade4692021-03-24 13:05:02 -07002803#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
2804#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
2805
Matt Roper645cc0b2021-11-02 15:25:10 -07002806#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
2807#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
2808
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002809#define ERROR_GEN6 _MMIO(0x40a0)
2810#define GEN7_ERR_INT _MMIO(0x44040)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002811#define ERR_INT_POISON (1 << 31)
2812#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2813#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2814#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2815#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2816#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2817#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2818#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2819#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2820#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
Chris Wilsonf4068392010-10-27 20:36:41 +01002821
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002822#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2823#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
Lucas De Marchi91b59cd2019-07-30 11:04:03 -07002824#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2825#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
Oscar Mateo5a3f58d2017-12-22 14:38:49 -08002826#define FAULT_VA_HIGH_BITS (0xf << 0)
2827#define FAULT_GTT_SEL (1 << 4)
Mika Kuoppala6c826f32015-03-24 14:54:19 +02002828
Tvrtko Ursulin7938d612021-10-19 13:27:10 +01002829#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
2830#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
2831#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
2832#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
2833
Lionel Landwerlinba1d18e2019-10-25 15:17:18 +03002834#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
2835
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002836#define FPGA_DBG _MMIO(0x42300)
Ville Syrjälä6bb0a0e2021-11-12 21:38:13 +02002837#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03002838
Mika Kuoppala8ac3e1b2015-12-15 19:45:42 +02002839#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
Ville Syrjälä6bb0a0e2021-11-12 21:38:13 +02002840#define CLAIM_ER_CLR REG_BIT(31)
2841#define CLAIM_ER_OVERFLOW REG_BIT(16)
2842#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
Mika Kuoppala8ac3e1b2015-12-15 19:45:42 +02002843
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002844#define DERRMR _MMIO(0x44050)
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07002845/* Note that HBLANK events are reserved on bdw+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002846#define DERRMR_PIPEA_SCANLINE (1 << 0)
2847#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2848#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2849#define DERRMR_PIPEA_VBLANK (1 << 3)
2850#define DERRMR_PIPEA_HBLANK (1 << 5)
Paulo Zanoniaf7187b2018-06-12 16:56:53 -07002851#define DERRMR_PIPEB_SCANLINE (1 << 8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002852#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2853#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2854#define DERRMR_PIPEB_VBLANK (1 << 11)
2855#define DERRMR_PIPEB_HBLANK (1 << 13)
Chris Wilsonffe74d72013-08-26 20:58:12 +01002856/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002857#define DERRMR_PIPEC_SCANLINE (1 << 14)
2858#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2859#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2860#define DERRMR_PIPEC_VBLANK (1 << 21)
2861#define DERRMR_PIPEC_HBLANK (1 << 22)
Chris Wilsonffe74d72013-08-26 20:58:12 +01002862
Chris Wilson0f3b6842013-01-15 12:05:55 +00002863
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002864/* GM45+ chicken bits -- debug workaround bits that may be required
2865 * for various sorts of correct behavior. The top 16 bits of each are
2866 * the enables for writing to the corresponding low bit.
2867 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002868#define _3D_CHICKEN _MMIO(0x2084)
Daniel Vetter42839082012-12-14 23:38:28 +01002869#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002870#define _3D_CHICKEN2 _MMIO(0x208c)
Kenneth Graunkeb77422f2018-06-15 20:06:05 +01002871
2872#define FF_SLICE_CHICKEN _MMIO(0x2088)
2873#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2874
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002875/* Disables pipelining of read flushes past the SF-WIZ interface.
2876 * Required on all Ironlake steppings according to the B-Spec, but the
2877 * particular danger of not doing so is not specified.
2878 */
2879# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002880#define _3D_CHICKEN3 _MMIO(0x2090)
Kenneth Graunkeb77422f2018-06-15 20:06:05 +01002881#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
Jesse Barnes87f80202012-10-02 17:43:41 -05002882#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Rodrigo Vivi1a25db62017-08-15 16:16:51 -07002883#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07002884#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002885#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02002886#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002887
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002888#define MI_MODE _MMIO(0x209c)
Eric Anholt71cf39b2010-03-08 23:41:55 -08002889# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08002890# define MI_FLUSH_ENABLE (1 << 12)
Matt Roper9e9dfd02021-08-05 09:36:46 -07002891# define TGL_NESTED_BB_EN (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00002892# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05302893# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01002894# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08002895
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002896#define GEN6_GT_MODE _MMIO(0x20d0)
2897#define GEN7_GT_MODE _MMIO(0x7008)
Ville Syrjälä8d85d272014-02-04 21:59:15 +02002898#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2899#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2900#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2901#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
Damien Lespiau98533252014-12-08 17:33:51 +00002902#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01002903#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002904#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2905#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07002906
Tim Gorea8ab5ed2016-06-13 12:15:01 +01002907/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2908#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2909#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
Radhakrishna Sripada622b3f62018-10-30 01:45:01 -07002910#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
Tim Gorea8ab5ed2016-06-13 12:15:01 +01002911
Stuart Summersd73dd1f2021-11-02 15:25:09 -07002912#define SCCGCTL94DC _MMIO(0x94dc)
2913#define CG3DDISURB REG_BIT(14)
2914
2915#define MLTICTXCTL _MMIO(0xb170)
2916#define TDONRENDER REG_BIT(2)
2917
2918#define L3SQCREG1_CCS0 _MMIO(0xb200)
2919#define FLUSHALLNONCOH REG_BIT(5)
2920
Tim Goreb1e429f2016-03-21 14:37:29 +00002921/* WaClearTdlStateAckDirtyBits */
2922#define GEN8_STATE_ACK _MMIO(0x20F0)
2923#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2924#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2925#define GEN9_STATE_ACK_TDL0 (1 << 12)
2926#define GEN9_STATE_ACK_TDL1 (1 << 13)
2927#define GEN9_STATE_ACK_TDL2 (1 << 14)
2928#define GEN9_STATE_ACK_TDL3 (1 << 15)
2929#define GEN9_SUBSLICE_TDL_ACK_BITS \
2930 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2931 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2932
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002933#define GFX_MODE _MMIO(0x2520)
2934#define GFX_MODE_GEN7 _MMIO(0x229c)
Tvrtko Ursulindbc65182019-06-07 09:45:20 +01002935#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002936#define GFX_RUN_LIST_ENABLE (1 << 15)
2937#define GFX_INTERRUPT_STEERING (1 << 14)
2938#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2939#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2940#define GFX_REPLAY_MODE (1 << 11)
2941#define GFX_PSMI_GRANULARITY (1 << 10)
2942#define GFX_PPGTT_ENABLE (1 << 9)
2943#define GEN8_GFX_PPGTT_48B (1 << 7)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002944
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002945#define GFX_FORWARD_VBLANK_MASK (3 << 5)
2946#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2947#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2948#define GFX_FORWARD_VBLANK_COND (2 << 5)
Dave Gordon4df001d2015-08-12 15:43:42 +01002949
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002950#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
Kelvin Gardiner225701f2018-01-30 11:49:17 -02002951
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002952#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2953#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2954#define SCPD0 _MMIO(0x209c) /* 915+ only */
Ville Syrjälä5cecf502020-07-02 18:37:23 +03002955#define SCPD_FBC_IGNORE_3D (1 << 6)
Ville Syrjälä7d423af2019-10-03 17:02:31 +03002956#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
Paulo Zanoni9d9523d2019-04-10 16:53:42 -07002957#define GEN2_IER _MMIO(0x20a0)
2958#define GEN2_IIR _MMIO(0x20a4)
2959#define GEN2_IMR _MMIO(0x20a8)
2960#define GEN2_ISR _MMIO(0x20ac)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002961#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002962#define GINT_DIS (1 << 22)
2963#define GCFG_DIS (1 << 8)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002964#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2965#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2966#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2967#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2968#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2969#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2970#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05302971#define VLV_PCBR_ADDR_SHIFT 12
2972
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002973#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002974#define EIR _MMIO(0x20b0)
2975#define EMR _MMIO(0x20b4)
2976#define ESR _MMIO(0x20b8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002977#define GM45_ERROR_PAGE_TABLE (1 << 5)
2978#define GM45_ERROR_MEM_PRIV (1 << 4)
2979#define I915_ERROR_PAGE_TABLE (1 << 4)
2980#define GM45_ERROR_CP_PRIV (1 << 3)
2981#define I915_ERROR_MEMORY_REFRESH (1 << 1)
2982#define I915_ERROR_INSTRUCTION (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002983#define INSTPM _MMIO(0x20c0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002984#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2985#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00002986 will not assert AGPBUSY# and will only
2987 be delivered when out of C3. */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002988#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2989#define INSTPM_TLB_INVALIDATE (1 << 9)
2990#define INSTPM_SYNC_FLUSH (1 << 5)
Daniele Ceraolo Spuriobaba6e52019-03-25 14:49:40 -07002991#define ACTHD(base) _MMIO((base) + 0xc8)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002992#define MEM_MODE _MMIO(0x20cc)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002993#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2994#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2995#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002996#define FW_BLC _MMIO(0x20d8)
2997#define FW_BLC2 _MMIO(0x20dc)
2998#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07002999#define FW_BLC_SELF_EN_MASK (1 << 31)
3000#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
3001#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003002#define MM_BURST_LENGTH 0x00700000
3003#define MM_FIFO_WATERMARK 0x0001F000
3004#define LM_BURST_LENGTH 0x00000700
3005#define LM_FIFO_WATERMARK 0x0000001F
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003006#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07003007
Matt Roper62afef22020-06-05 19:57:34 -07003008#define _MBUS_ABOX0_CTL 0x45038
3009#define _MBUS_ABOX1_CTL 0x45048
3010#define _MBUS_ABOX2_CTL 0x4504C
3011#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
3012 _MBUS_ABOX1_CTL, \
3013 _MBUS_ABOX2_CTL))
Mahesh Kumar78005492018-01-30 11:49:14 -02003014#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
3015#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
3016#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
3017#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
3018#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
3019#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
3020#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
3021#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
3022
3023#define _PIPEA_MBUS_DBOX_CTL 0x7003C
3024#define _PIPEB_MBUS_DBOX_CTL 0x7103C
3025#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
3026 _PIPEB_MBUS_DBOX_CTL)
3027#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
3028#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
3029#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
3030#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
3031#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
3032#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
3033
3034#define MBUS_UBOX_CTL _MMIO(0x4503C)
3035#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
3036#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
3037
Vandita Kulkarnif4dc0082021-05-18 17:06:17 -07003038#define MBUS_CTL _MMIO(0x4438C)
3039#define MBUS_JOIN REG_BIT(31)
3040#define MBUS_HASHING_MODE_MASK REG_BIT(30)
3041#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
3042#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
3043#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
3044#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
3045#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
3046
Matt Roperddff9a602020-07-16 15:05:50 -07003047#define HDPORT_STATE _MMIO(0x45050)
Aditya Swarup80d0f7652021-01-25 06:07:48 -08003048#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
José Roberto de Souzaff7fb442021-01-08 05:48:02 -08003049#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
Matt Roperddff9a602020-07-16 15:05:50 -07003050#define HDPORT_ENABLED REG_BIT(0)
3051
Keith Packard45503de2010-07-19 21:12:35 -07003052/* Make render/texture TLB fetches lower priorty than associated data
3053 * fetches. This is not turned on by default
3054 */
3055#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
3056
3057/* Isoch request wait on GTT enable (Display A/B/C streams).
3058 * Make isoch requests stall on the TLB update. May cause
3059 * display underruns (test mode only)
3060 */
3061#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
3062
3063/* Block grant count for isoch requests when block count is
3064 * set to a finite value.
3065 */
3066#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
3067#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
3068#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
3069#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
3070#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
3071
3072/* Enable render writes to complete in C2/C3/C4 power states.
3073 * If this isn't enabled, render writes are prevented in low
3074 * power states. That seems bad to me.
3075 */
3076#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
3077
3078/* This acknowledges an async flip immediately instead
3079 * of waiting for 2TLB fetches.
3080 */
3081#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
3082
3083/* Enables non-sequential data reads through arbiter
3084 */
Akshay Joshi0206e352011-08-16 15:34:10 -04003085#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07003086
3087/* Disable FSB snooping of cacheable write cycles from binner/render
3088 * command stream
3089 */
3090#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
3091
3092/* Arbiter time slice for non-isoch streams */
3093#define MI_ARB_TIME_SLICE_MASK (7 << 5)
3094#define MI_ARB_TIME_SLICE_1 (0 << 5)
3095#define MI_ARB_TIME_SLICE_2 (1 << 5)
3096#define MI_ARB_TIME_SLICE_4 (2 << 5)
3097#define MI_ARB_TIME_SLICE_6 (3 << 5)
3098#define MI_ARB_TIME_SLICE_8 (4 << 5)
3099#define MI_ARB_TIME_SLICE_10 (5 << 5)
3100#define MI_ARB_TIME_SLICE_14 (6 << 5)
3101#define MI_ARB_TIME_SLICE_16 (7 << 5)
3102
3103/* Low priority grace period page size */
3104#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
3105#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
3106
3107/* Disable display A/B trickle feed */
3108#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
3109
3110/* Set display plane priority */
3111#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
3112#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
3113
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003114#define MI_STATE _MMIO(0x20e4) /* gen2 only */
Ville Syrjälä54e472a2014-02-25 15:13:40 +02003115#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
3116#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
3117
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003118#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003119#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
3120#define CM0_IZ_OPT_DISABLE (1 << 6)
3121#define CM0_ZR_OPT_DISABLE (1 << 5)
3122#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
3123#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
3124#define CM0_COLOR_EVICT_DISABLE (1 << 3)
3125#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
3126#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003127#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
3128#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003129#define GFX_FLSH_CNTL_EN (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003130#define ECOSKPD _MMIO(0x21d0)
Chris Wilson9ce9bdb2019-04-19 18:27:20 +01003131#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003132#define ECO_GATING_CX_ONLY (1 << 3)
3133#define ECO_FLIP_DONE (1 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003134
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003135#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003136#define RC_OP_FLUSH_ENABLE (1 << 0)
3137#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003138#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003139#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
3140#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
3141#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
Jesse Barnesfb046852012-03-28 13:39:26 -07003142
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003143#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
Jesse Barnes4efe0702011-01-18 11:25:41 -08003144#define GEN6_BLITTER_LOCK_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003145#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
Jesse Barnes4efe0702011-01-18 11:25:41 -08003146
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003147#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
Chris Wilson2c550182014-12-16 10:02:27 +00003148#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
Mika Kuoppala99db8c592019-10-15 18:44:48 +03003149#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02003150#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003151#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02003152
Robert Bragg19f81df2017-06-13 12:23:03 +01003153#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3154#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3155
Talha Nassar0b904c82019-01-31 17:08:44 -08003156#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
Matt Roper645cc0b2021-11-02 15:25:10 -07003157#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
3158#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
Talha Nassar0b904c82019-01-31 17:08:44 -08003159
Deepak S693d11c2015-01-16 20:42:16 +05303160/* Fuse readout registers for GT */
Lionel Landwerlinb8ec7592018-02-21 20:49:02 +00003161#define HSW_PAVP_FUSE1 _MMIO(0x911C)
Matt Roperff04f8b2021-09-17 09:12:02 -07003162#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
3163#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
Lionel Landwerlinb8ec7592018-02-21 20:49:02 +00003164#define HSW_F1_EU_DIS_10EUS 0
3165#define HSW_F1_EU_DIS_8EUS 1
3166#define HSW_F1_EU_DIS_6EUS 2
3167
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003168#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
Jeff McGeec93043a2015-02-27 12:12:28 -08003169#define CHV_FGT_DISABLE_SS0 (1 << 10)
3170#define CHV_FGT_DISABLE_SS1 (1 << 11)
Deepak S693d11c2015-01-16 20:42:16 +05303171#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
3172#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3173#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
3174#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3175#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
3176#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3177#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
3178#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3179
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003180#define GEN8_FUSE2 _MMIO(0x9120)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02003181#define GEN8_F2_SS_DIS_SHIFT 21
3182#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
Jeff McGee38732182015-02-13 10:27:54 -06003183#define GEN8_F2_S_ENA_SHIFT 25
3184#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
3185
3186#define GEN9_F2_SS_DIS_SHIFT 20
3187#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
3188
Ben Widawsky4e9767b2017-09-20 11:35:24 -07003189#define GEN10_F2_S_ENA_SHIFT 22
3190#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
3191#define GEN10_F2_SS_DIS_SHIFT 18
3192#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
3193
Yunwei Zhangfe864b72018-05-18 15:41:25 -07003194#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
3195#define GEN10_L3BANK_PAIR_COUNT 4
3196#define GEN10_L3BANK_MASK 0x0F
Daniele Ceraolo Spurio3ffe82d2021-07-29 09:59:51 -07003197/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
3198#define GEN12_MAX_MSLICES 4
3199#define GEN12_MEML3_EN_MASK 0x0F
Yunwei Zhangfe864b72018-05-18 15:41:25 -07003200
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003201#define GEN8_EU_DISABLE0 _MMIO(0x9134)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02003202#define GEN8_EU_DIS0_S0_MASK 0xffffff
3203#define GEN8_EU_DIS0_S1_SHIFT 24
3204#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
3205
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003206#define GEN8_EU_DISABLE1 _MMIO(0x9138)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02003207#define GEN8_EU_DIS1_S1_MASK 0xffff
3208#define GEN8_EU_DIS1_S2_SHIFT 16
3209#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
3210
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003211#define GEN8_EU_DISABLE2 _MMIO(0x913c)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02003212#define GEN8_EU_DIS2_S2_MASK 0xff
3213
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003214#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
Jeff McGee38732182015-02-13 10:27:54 -06003215
Ben Widawsky4e9767b2017-09-20 11:35:24 -07003216#define GEN10_EU_DISABLE3 _MMIO(0x9140)
3217#define GEN10_EU_DIS_SS_MASK 0xff
3218
Oscar Mateo26376a72018-03-16 14:14:49 +02003219#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
3220#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
3221#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
José Roberto de Souza547fcf92019-03-26 16:02:23 -07003222#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
Oscar Mateo26376a72018-03-16 14:14:49 +02003223
Kelvin Gardiner8b5eb5e2018-03-20 12:45:21 -07003224#define GEN11_EU_DISABLE _MMIO(0x9134)
3225#define GEN11_EU_DIS_MASK 0xFF
3226
3227#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3228#define GEN11_GT_S_ENA_MASK 0xFF
3229
3230#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3231
Stuart Summersd16de9a2021-08-06 10:29:01 -07003232#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913C)
3233#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
Daniele Ceraolo Spurio601734f2019-09-13 08:51:37 +01003234
Matthew Auld05b78d22021-07-29 09:59:58 -07003235#define XEHP_EU_ENABLE _MMIO(0x9134)
3236#define XEHP_EU_ENA_MASK 0xFF
3237
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003238#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
Chris Wilson12f55812012-07-05 17:14:01 +01003239#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
3240#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
3241#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
3242#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01003243
Ben Widawskycc609d52013-05-28 19:22:29 -07003244/* On modern GEN architectures interrupt control consists of two sets
3245 * of registers. The first set pertains to the ring generating the
3246 * interrupt. The second control is for the functional block generating the
3247 * interrupt. These are PM, GT, DE, etc.
3248 *
3249 * Luckily *knocks on wood* all the ring interrupt bits match up with the
3250 * GT interrupt bits, so we don't need to duplicate the defines.
3251 *
3252 * These defines should cover us well from SNB->HSW with minor exceptions
3253 * it can also work on ILK.
3254 */
3255#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3256#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
3257#define GT_BLT_USER_INTERRUPT (1 << 22)
3258#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
3259#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003260#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Chris Wilsonc4e8ba72020-04-07 14:08:11 +01003261#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
Oscar Mateo73d477f2014-07-24 17:04:31 +01003262#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07003263#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
3264#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
Chris Wilson70a76a92020-01-28 20:43:15 +00003265#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
Ben Widawskycc609d52013-05-28 19:22:29 -07003266#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
3267#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
3268#define GT_RENDER_USER_INTERRUPT (1 << 0)
3269
Ben Widawsky12638c52013-05-28 19:22:31 -07003270#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
3271#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
3272
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01003273#define GT_PARITY_ERROR(dev_priv) \
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003274 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01003275 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003276
Ben Widawskycc609d52013-05-28 19:22:29 -07003277/* These are all the "old" interrupts */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003278#define ILK_BSD_USER_INTERRUPT (1 << 5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03003279
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003280#define I915_PM_INTERRUPT (1 << 31)
3281#define I915_ISP_INTERRUPT (1 << 22)
3282#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
3283#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
3284#define I915_MIPIC_INTERRUPT (1 << 19)
3285#define I915_MIPIA_INTERRUPT (1 << 18)
3286#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
3287#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
3288#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
3289#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003290#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
3291#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3292#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
3293#define I915_HWB_OOM_INTERRUPT (1 << 13)
3294#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
3295#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
3296#define I915_MISC_INTERRUPT (1 << 11)
3297#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
3298#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
3299#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
3300#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
3301#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
3302#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
3303#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
3304#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
3305#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
3306#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
3307#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
3308#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
3309#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
3310#define I915_DEBUG_INTERRUPT (1 << 2)
3311#define I915_WINVALID_INTERRUPT (1 << 1)
3312#define I915_USER_INTERRUPT (1 << 1)
3313#define I915_ASLE_INTERRUPT (1 << 0)
3314#define I915_BSD_USER_INTERRUPT (1 << 25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01003315
Jerome Anandeef57322017-01-25 04:27:49 +05303316#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3317#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
3318
Pierre-Louis Bossartd5d8c3a2017-01-31 14:16:49 -06003319/* DisplayPort Audio w/ LPE */
Takashi Iwai9db13e52017-02-02 11:03:48 +01003320#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3321#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
3322
Pierre-Louis Bossartd5d8c3a2017-01-31 14:16:49 -06003323#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3324#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3325#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3326#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3327 _VLV_AUD_PORT_EN_B_DBG, \
3328 _VLV_AUD_PORT_EN_C_DBG, \
3329 _VLV_AUD_PORT_EN_D_DBG)
3330#define VLV_AMP_MUTE (1 << 1)
3331
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003332#define GEN6_BSD_RNCID _MMIO(0x12198)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01003333
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003334#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
Ben Widawskya1e969e2012-04-14 18:41:32 -07003335#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08003336#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Mika Kuoppala561db822020-02-07 17:51:37 +02003337#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003338#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
3339#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
3340#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3341#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08003342#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003343#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
3344#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
3345#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3346#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
3347#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
3348#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
3349#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
3350#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
Ben Widawskya1e969e2012-04-14 18:41:32 -07003351
Xiang, Haihao881f47b2010-09-19 14:40:43 +01003352/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003353 * Framebuffer compression (915+ only)
3354 */
3355
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003356#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
3357#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
3358#define FBC_CONTROL _MMIO(0x3208)
Ville Syrjäläa4b17f72021-11-04 16:45:16 +02003359#define FBC_CTL_EN REG_BIT(31)
3360#define FBC_CTL_PERIODIC REG_BIT(30)
3361#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
3362#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3363#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
3364#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
3365#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
3366#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
3367#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3368#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
3369#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003370#define FBC_COMMAND _MMIO(0x320c)
Ville Syrjäläa4b17f72021-11-04 16:45:16 +02003371#define FBC_CMD_COMPRESS REG_BIT(0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003372#define FBC_STATUS _MMIO(0x3210)
Ville Syrjäläa4b17f72021-11-04 16:45:16 +02003373#define FBC_STAT_COMPRESSING REG_BIT(31)
3374#define FBC_STAT_COMPRESSED REG_BIT(30)
3375#define FBC_STAT_MODIFIED REG_BIT(29)
3376#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
3377#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
3378#define FBC_CTL_FENCE_DBL REG_BIT(4)
3379#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
3380#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
3381#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
3382#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
3383#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
3384#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
3385#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
3386#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
3387#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
3388#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
3389#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
3390#define FBC_MOD_NUM_VALID REG_BIT(0)
3391#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
3392#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
3393#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
3394#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
3395#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
3396#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
Jesse Barnes585fb112008-07-29 11:54:06 -07003397
3398#define FBC_LL_SIZE (1536)
3399
Jesse Barnes74dff282009-09-14 15:39:40 -07003400/* Framebuffer compression for GM45+ */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003401#define DPFC_CB_BASE _MMIO(0x3200)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003402#define ILK_DPFC_CB_BASE _MMIO(0x43200)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003403#define DPFC_CONTROL _MMIO(0x3208)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003404#define ILK_DPFC_CONTROL _MMIO(0x43208)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003405#define DPFC_CTL_EN REG_BIT(31)
3406#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
3407#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
3408#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
3409#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
3410#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
3411#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
3412#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
3413#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
3414#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
3415#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
3416#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
3417#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
3418#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
3419#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
3420#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
3421#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
3422#define DPFC_RECOMP_CTL _MMIO(0x320c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003423#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003424#define DPFC_RECOMP_STALL_EN REG_BIT(27)
3425#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
3426#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
3427#define DPFC_STATUS _MMIO(0x3210)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003428#define ILK_DPFC_STATUS _MMIO(0x43210)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003429#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
3430#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
3431#define DPFC_STATUS2 _MMIO(0x3214)
3432#define ILK_DPFC_STATUS2 _MMIO(0x43214)
3433#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
3434#define DPFC_FENCE_YOFF _MMIO(0x3218)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003435#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003436#define DPFC_CHICKEN _MMIO(0x3224)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003437#define ILK_DPFC_CHICKEN _MMIO(0x43224)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003438#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
3439#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
3440#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
3441#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
3442
Ville Syrjälä2f051f62021-09-21 18:25:15 +03003443#define GLK_FBC_STRIDE _MMIO(0x43228)
3444#define FBC_STRIDE_OVERRIDE REG_BIT(15)
3445#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
3446#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003447
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003448#define ILK_FBC_RT_BASE _MMIO(0x2128)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003449#define ILK_FBC_RT_VALID REG_BIT(0)
3450#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003451
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003452#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003453#define ILK_FBCQ_DIS (1 << 22)
Ville Syrjäläb7a70532021-02-20 12:33:03 +02003454#define ILK_PABSTRETCH_DIS REG_BIT(21)
3455#define ILK_SABSTRETCH_DIS REG_BIT(20)
3456#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
3457#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
3458#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
3459#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
3460#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
3461#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
3462#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
3463#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
3464#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
3465#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
Yuanhan Liu13982612010-12-15 15:42:31 +08003466
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003467
Jesse Barnes585fb112008-07-29 11:54:06 -07003468/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003469 * Framebuffer compression for Sandybridge
3470 *
3471 * The following two registers are of type GTTMMADR
3472 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003473#define SNB_DPFC_CTL_SA _MMIO(0x100100)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003474#define SNB_DPFC_FENCE_EN REG_BIT(29)
3475#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
3476#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
3477#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003478
Rodrigo Viviabe959c2013-05-06 19:37:33 -03003479/* Framebuffer compression for Ivybridge */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003480#define IVB_FBC_RT_BASE _MMIO(0x7020)
Matt Roperd0ed5102020-03-11 09:22:57 -07003481#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03003482
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003483#define IPS_CTL _MMIO(0x43408)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003484#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003485
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003486#define MSG_FBC_REND_STATE _MMIO(0x50380)
Ville Syrjälä73ab6ec2021-11-04 16:45:15 +02003487#define FBC_REND_NUKE REG_BIT(2)
3488#define FBC_REND_CACHE_CLEAN REG_BIT(1)
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03003489
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003490/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003491 * GPIO regs
3492 */
Lucas De Marchidce88872018-07-27 12:36:47 -07003493#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3494 4 * (gpio))
3495
Jesse Barnes585fb112008-07-29 11:54:06 -07003496# define GPIO_CLOCK_DIR_MASK (1 << 0)
3497# define GPIO_CLOCK_DIR_IN (0 << 1)
3498# define GPIO_CLOCK_DIR_OUT (1 << 1)
3499# define GPIO_CLOCK_VAL_MASK (1 << 2)
3500# define GPIO_CLOCK_VAL_OUT (1 << 3)
3501# define GPIO_CLOCK_VAL_IN (1 << 4)
3502# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3503# define GPIO_DATA_DIR_MASK (1 << 8)
3504# define GPIO_DATA_DIR_IN (0 << 9)
3505# define GPIO_DATA_DIR_OUT (1 << 9)
3506# define GPIO_DATA_VAL_MASK (1 << 10)
3507# define GPIO_DATA_VAL_OUT (1 << 11)
3508# define GPIO_DATA_VAL_IN (1 << 12)
3509# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3510
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003511#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003512#define GMBUS_AKSV_SELECT (1 << 11)
3513#define GMBUS_RATE_100KHZ (0 << 8)
3514#define GMBUS_RATE_50KHZ (1 << 8)
3515#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3516#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3517#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
Ramalingam Cd5dc0f42018-06-28 19:04:49 +05303518#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
Anusha Srivatsa5c749c52018-01-11 16:00:09 -02003519
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003520#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003521#define GMBUS_SW_CLR_INT (1 << 31)
3522#define GMBUS_SW_RDY (1 << 30)
3523#define GMBUS_ENT (1 << 29) /* enable timeout */
3524#define GMBUS_CYCLE_NONE (0 << 25)
3525#define GMBUS_CYCLE_WAIT (1 << 25)
3526#define GMBUS_CYCLE_INDEX (2 << 25)
3527#define GMBUS_CYCLE_STOP (4 << 25)
Chris Wilsonf899fc62010-07-20 15:44:45 -07003528#define GMBUS_BYTE_COUNT_SHIFT 16
Dmitry Torokhov9535c472015-04-21 09:49:11 -07003529#define GMBUS_BYTE_COUNT_MAX 256U
Ramalingam C73675cf2018-06-28 19:04:48 +05303530#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
Chris Wilsonf899fc62010-07-20 15:44:45 -07003531#define GMBUS_SLAVE_INDEX_SHIFT 8
3532#define GMBUS_SLAVE_ADDR_SHIFT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003533#define GMBUS_SLAVE_READ (1 << 0)
3534#define GMBUS_SLAVE_WRITE (0 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003535#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003536#define GMBUS_INUSE (1 << 15)
3537#define GMBUS_HW_WAIT_PHASE (1 << 14)
3538#define GMBUS_STALL_TIMEOUT (1 << 13)
3539#define GMBUS_INT (1 << 12)
3540#define GMBUS_HW_RDY (1 << 11)
3541#define GMBUS_SATOER (1 << 10)
3542#define GMBUS_ACTIVE (1 << 9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003543#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3544#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003545#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3546#define GMBUS_NAK_EN (1 << 3)
3547#define GMBUS_IDLE_EN (1 << 2)
3548#define GMBUS_HW_WAIT_EN (1 << 1)
3549#define GMBUS_HW_RDY_EN (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003550#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003551#define GMBUS_2BYTE_INDEX_EN (1 << 31)
Eric Anholtf0217c42009-12-01 11:56:30 -08003552
Jesse Barnes585fb112008-07-29 11:54:06 -07003553/*
3554 * Clock control & power management
3555 */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02003556#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3557#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3558#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003559#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07003560
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003561#define VGA0 _MMIO(0x6000)
3562#define VGA1 _MMIO(0x6004)
3563#define VGA_PD _MMIO(0x6010)
Jesse Barnes585fb112008-07-29 11:54:06 -07003564#define VGA0_PD_P2_DIV_4 (1 << 7)
3565#define VGA0_PD_P1_DIV_2 (1 << 5)
3566#define VGA0_PD_P1_SHIFT 0
3567#define VGA0_PD_P1_MASK (0x1f << 0)
3568#define VGA1_PD_P2_DIV_4 (1 << 15)
3569#define VGA1_PD_P1_DIV_2 (1 << 13)
3570#define VGA1_PD_P1_SHIFT 8
3571#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07003572#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02003573#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3574#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003575#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003576#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03003577#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07003578#define DPLL_VGA_MODE_DIS (1 << 28)
3579#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3580#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3581#define DPLL_MODE_MASK (3 << 26)
3582#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3583#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3584#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3585#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3586#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3587#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003588#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003589#define DPLL_LOCK_VLV (1 << 15)
3590#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3591#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3592#define DPLL_SSC_REF_CLK_CHV (1 << 13)
Daniel Vetter598fac62013-04-18 22:01:46 +02003593#define DPLL_PORTC_READY_MASK (0xf << 4)
3594#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003595
Jesse Barnes585fb112008-07-29 11:54:06 -07003596#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03003597
3598/* Additional CHV pll/phy registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003599#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03003600#define DPLL_PORTD_READY_MASK (0xf)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003601#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003602#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
Ville Syrjäläbc284542015-05-26 20:22:38 +03003603#define PHY_LDO_DELAY_0NS 0x0
3604#define PHY_LDO_DELAY_200NS 0x1
3605#define PHY_LDO_DELAY_600NS 0x2
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003606#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3607#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
Ville Syrjälä70722462015-04-10 18:21:28 +03003608#define PHY_CH_SU_PSR 0x1
3609#define PHY_CH_DEEP_PSR 0x7
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003610#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
Ville Syrjälä70722462015-04-10 18:21:28 +03003611#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003612#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003613#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3614#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3615#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03003616
Jesse Barnes585fb112008-07-29 11:54:06 -07003617/*
3618 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3619 * this field (only one bit may be set).
3620 */
3621#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3622#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003623#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07003624/* i830, required in DVO non-gang */
3625#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3626#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3627#define PLL_REF_INPUT_DREFCLK (0 << 13)
3628#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3629#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3630#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3631#define PLL_REF_INPUT_MASK (3 << 13)
3632#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003633/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003634# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3635# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003636# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003637# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3638# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3639
Jesse Barnes585fb112008-07-29 11:54:06 -07003640/*
3641 * Parallel to Serial Load Pulse phase selection.
3642 * Selects the phase for the 10X DPLL clock for the PCIe
3643 * digital display port. The range is 4 to 13; 10 or more
3644 * is just a flip delay. The default is 6
3645 */
3646#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3647#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3648/*
3649 * SDVO multiplier for 945G/GM. Not used on 965.
3650 */
3651#define SDVO_MULTIPLIER_MASK 0x000000ff
3652#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3653#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003654
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02003655#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3656#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3657#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003658#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003659
Jesse Barnes585fb112008-07-29 11:54:06 -07003660/*
3661 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3662 *
3663 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3664 */
3665#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3666#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3667/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3668#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3669#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3670/*
3671 * SDVO/UDI pixel multiplier.
3672 *
3673 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3674 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3675 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3676 * dummy bytes in the datastream at an increased clock rate, with both sides of
3677 * the link knowing how many bytes are fill.
3678 *
3679 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3680 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3681 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3682 * through an SDVO command.
3683 *
3684 * This register field has values of multiplication factor minus 1, with
3685 * a maximum multiplier of 5 for SDVO.
3686 */
3687#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3688#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3689/*
3690 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3691 * This best be set to the default value (3) or the CRT won't work. No,
3692 * I don't entirely understand what this does...
3693 */
3694#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3695#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003696
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +03003697#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3698
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003699#define _FPA0 0x6040
3700#define _FPA1 0x6044
3701#define _FPB0 0x6048
3702#define _FPB1 0x604c
3703#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3704#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07003705#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003706#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07003707#define FP_N_DIV_SHIFT 16
3708#define FP_M1_DIV_MASK 0x00003f00
3709#define FP_M1_DIV_SHIFT 8
3710#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003711#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07003712#define FP_M2_DIV_SHIFT 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003713#define DPLL_TEST _MMIO(0x606c)
Jesse Barnes585fb112008-07-29 11:54:06 -07003714#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3715#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3716#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3717#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3718#define DPLLB_TEST_N_BYPASS (1 << 19)
3719#define DPLLB_TEST_M_BYPASS (1 << 18)
3720#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3721#define DPLLA_TEST_N_BYPASS (1 << 3)
3722#define DPLLA_TEST_M_BYPASS (1 << 2)
3723#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003724#define D_STATE _MMIO(0x6104)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003725#define DSTATE_GFX_RESET_I830 (1 << 6)
3726#define DSTATE_PLL_D3_OFF (1 << 3)
3727#define DSTATE_GFX_CLOCK_GATING (1 << 1)
3728#define DSTATE_DOT_CLOCK_GATING (1 << 0)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02003729#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07003730# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3731# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3732# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3733# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3734# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3735# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3736# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
Ville Syrjäläad8059c2017-12-08 23:37:38 +02003737# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
Jesse Barnes652c3932009-08-17 13:31:43 -07003738# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3739# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3740# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3741# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3742# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3743# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3744# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3745# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3746# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3747# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3748# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3749# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3750# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3751# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3752# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3753# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3754# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3755# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3756# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3757# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3758# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003759/*
Jesse Barnes652c3932009-08-17 13:31:43 -07003760 * This bit must be set on the 830 to prevent hangs when turning off the
3761 * overlay scaler.
3762 */
3763# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3764# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3765# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3766# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3767# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3768
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003769#define RENCLK_GATE_D1 _MMIO(0x6204)
Jesse Barnes652c3932009-08-17 13:31:43 -07003770# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3771# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3772# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3773# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3774# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3775# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3776# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3777# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3778# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003779/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07003780# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3781# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3782# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3783# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003784/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07003785# define SV_CLOCK_GATE_DISABLE (1 << 0)
3786# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3787# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3788# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3789# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3790# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3791# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3792# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3793# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3794# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3795# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3796# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3797# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3798# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3799# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3800# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3801# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3802# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3803
3804# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003805/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07003806# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3807# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3808# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3809# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3810# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3811# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003812/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07003813# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3814# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3815# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3816# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3817# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3818# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3819# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3820# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3821# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3822# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3823# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3824# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3825# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3826# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3827# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3828# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3829# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3830# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3831# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3832
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003833#define RENCLK_GATE_D2 _MMIO(0x6208)
Jesse Barnes652c3932009-08-17 13:31:43 -07003834#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3835#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3836#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03003837
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003838#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03003839#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3840
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003841#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3842#define DEUC _MMIO(0x6214) /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003843
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003844#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003845#define FW_CSPWRDWNEN (1 << 15)
Jesse Barnesceb04242012-03-28 13:39:22 -07003846
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003847#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03003848
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003849#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08003850#define CDCLK_FREQ_SHIFT 4
3851#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3852#define CZCLK_FREQ_MASK 0xf
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02003853
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003854#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02003855#define PFI_CREDIT_63 (9 << 28) /* chv only */
3856#define PFI_CREDIT_31 (8 << 28) /* chv only */
3857#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3858#define PFI_CREDIT_RESEND (1 << 27)
3859#define VGA_FAST_MODE_DISABLE (1 << 14)
3860
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003861#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08003862
Jesse Barnes585fb112008-07-29 11:54:06 -07003863/*
3864 * Palette regs
3865 */
Jani Nikula74c1e8262018-10-31 13:04:50 +02003866#define _PALETTE_A 0xa000
3867#define _PALETTE_B 0xa800
3868#define _CHV_PALETTE_C 0xc000
Swati Sharma8efd0692019-09-09 17:31:42 +05303869#define PALETTE_RED_MASK REG_GENMASK(23, 16)
3870#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
3871#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02003872#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
Jani Nikula74c1e8262018-10-31 13:04:50 +02003873 _PICK((pipe), _PALETTE_A, \
3874 _PALETTE_B, _CHV_PALETTE_C) + \
3875 (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003876
Eric Anholt673a3942008-07-30 12:06:12 -07003877/* MCH MMIO space */
3878
3879/*
3880 * MCHBAR mirror.
3881 *
3882 * This mirrors the MCHBAR MMIO space whose location is determined by
3883 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3884 * every way. It is not accessible from the CP register read instructions.
3885 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03003886 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3887 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07003888 */
3889#define MCHBAR_MIRROR_BASE 0x10000
3890
Yuanhan Liu13982612010-12-15 15:42:31 +08003891#define MCHBAR_MIRROR_BASE_SNB 0x140000
3892
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003893#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3894#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
Ville Syrjälä7d316ae2015-09-16 21:28:50 +03003895#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3896#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
Ville Syrjälädb7fb602017-11-02 17:17:35 +02003897#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
Ville Syrjälä7d316ae2015-09-16 21:28:50 +03003898
Chris Wilson3ebecd02013-04-12 19:10:13 +01003899/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003900#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01003901
Ville Syrjälä646b4262014-04-25 20:14:30 +03003902/* 915-945 and GM965 MCH register controlling DRAM channel access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003903#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
Eric Anholt673a3942008-07-30 12:06:12 -07003904#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3905#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3906#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3907#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3908#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08003909#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003910#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
Daniel Vetter656bfa32014-11-20 09:26:30 +01003911#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
Eric Anholt673a3942008-07-30 12:06:12 -07003912
Ville Syrjälä646b4262014-04-25 20:14:30 +03003913/* Pineview MCH register contains DDR3 setting */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003914#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
Li Peng95534262010-05-18 18:58:44 +08003915#define CSHRDDR3CTL_DDR3 (1 << 2)
3916
Ville Syrjälä646b4262014-04-25 20:14:30 +03003917/* 965 MCH register controlling DRAM channel configuration */
Ville Syrjälä924ad0e2021-04-21 18:34:00 +03003918#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3919#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
Eric Anholt673a3942008-07-30 12:06:12 -07003920
Ville Syrjälä646b4262014-04-25 20:14:30 +03003921/* snb MCH registers for reading the DRAM channel configuration */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003922#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3923#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3924#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003925#define MAD_DIMM_ECC_MASK (0x3 << 24)
3926#define MAD_DIMM_ECC_OFF (0x0 << 24)
3927#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3928#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3929#define MAD_DIMM_ECC_ON (0x3 << 24)
3930#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3931#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3932#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3933#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3934#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3935#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3936#define MAD_DIMM_A_SELECT (0x1 << 16)
3937/* DIMM sizes are in multiples of 256mb. */
3938#define MAD_DIMM_B_SIZE_SHIFT 8
3939#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3940#define MAD_DIMM_A_SIZE_SHIFT 0
3941#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3942
Ville Syrjälä646b4262014-04-25 20:14:30 +03003943/* snb MCH registers for priority tuning */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003944#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01003945#define MCH_SSKPD_WM0_MASK 0x3f
3946#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003947
Keith Packardb11248d2009-06-11 22:28:56 -07003948/* Clocking configuration register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003949#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
Ville Syrjälä488e0172020-05-14 15:38:38 +03003950#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
3951#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07003952#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3953#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3954#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3955#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
Ville Syrjälä6f381232017-05-04 21:15:30 +03003956#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
Keith Packardb11248d2009-06-11 22:28:56 -07003957#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Ville Syrjälä6f381232017-05-04 21:15:30 +03003958#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
Ville Syrjälä6f62bda2020-05-14 15:38:36 +03003959#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07003960#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003961#define CLKCFG_MEM_533 (1 << 4)
3962#define CLKCFG_MEM_667 (2 << 4)
3963#define CLKCFG_MEM_800 (3 << 4)
3964#define CLKCFG_MEM_MASK (7 << 4)
3965
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003966#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3967#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
Ville Syrjälä34edce22015-05-22 11:22:33 +03003968
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003969#define TSC1 _MMIO(0x11001)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07003970#define TSE (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003971#define TR1 _MMIO(0x11006)
3972#define TSFS _MMIO(0x11020)
Jesse Barnes7648fa92010-05-20 14:28:11 -07003973#define TSFS_SLOPE_MASK 0x0000ff00
3974#define TSFS_SLOPE_SHIFT 8
3975#define TSFS_INTR_MASK 0x000000ff
3976
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003977#define CRSTANDVID _MMIO(0x11100)
3978#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003979#define PXVFREQ_PX_MASK 0x7f000000
3980#define PXVFREQ_PX_SHIFT 24
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003981#define VIDFREQ_BASE _MMIO(0x11110)
3982#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3983#define VIDFREQ2 _MMIO(0x11114)
3984#define VIDFREQ3 _MMIO(0x11118)
3985#define VIDFREQ4 _MMIO(0x1111c)
Jesse Barnesf97108d2010-01-29 11:27:07 -08003986#define VIDFREQ_P0_MASK 0x1f000000
3987#define VIDFREQ_P0_SHIFT 24
3988#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3989#define VIDFREQ_P0_CSCLK_SHIFT 20
3990#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3991#define VIDFREQ_P0_CRCLK_SHIFT 16
3992#define VIDFREQ_P1_MASK 0x00001f00
3993#define VIDFREQ_P1_SHIFT 8
3994#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3995#define VIDFREQ_P1_CSCLK_SHIFT 4
3996#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003997#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3998#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003999#define INTTOEXT_MAP3_SHIFT 24
4000#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
4001#define INTTOEXT_MAP2_SHIFT 16
4002#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
4003#define INTTOEXT_MAP1_SHIFT 8
4004#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
4005#define INTTOEXT_MAP0_SHIFT 0
4006#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004007#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08004008#define MEMCTL_CMD_MASK 0xe000
4009#define MEMCTL_CMD_SHIFT 13
4010#define MEMCTL_CMD_RCLK_OFF 0
4011#define MEMCTL_CMD_RCLK_ON 1
4012#define MEMCTL_CMD_CHFREQ 2
4013#define MEMCTL_CMD_CHVID 3
4014#define MEMCTL_CMD_VMMOFF 4
4015#define MEMCTL_CMD_VMMON 5
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004016#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
Jesse Barnesf97108d2010-01-29 11:27:07 -08004017 when command complete */
4018#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
4019#define MEMCTL_FREQ_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004020#define MEMCTL_SFCAVM (1 << 7)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004021#define MEMCTL_TGT_VID_MASK 0x007f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004022#define MEMIHYST _MMIO(0x1117c)
4023#define MEMINTREN _MMIO(0x11180) /* 16 bits */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004024#define MEMINT_RSEXIT_EN (1 << 8)
4025#define MEMINT_CX_SUPR_EN (1 << 7)
4026#define MEMINT_CONT_BUSY_EN (1 << 6)
4027#define MEMINT_AVG_BUSY_EN (1 << 5)
4028#define MEMINT_EVAL_CHG_EN (1 << 4)
4029#define MEMINT_MON_IDLE_EN (1 << 3)
4030#define MEMINT_UP_EVAL_EN (1 << 2)
4031#define MEMINT_DOWN_EVAL_EN (1 << 1)
4032#define MEMINT_SW_CMD_EN (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004033#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
Jesse Barnesf97108d2010-01-29 11:27:07 -08004034#define MEM_RSEXIT_MASK 0xc000
4035#define MEM_RSEXIT_SHIFT 14
4036#define MEM_CONT_BUSY_MASK 0x3000
4037#define MEM_CONT_BUSY_SHIFT 12
4038#define MEM_AVG_BUSY_MASK 0x0c00
4039#define MEM_AVG_BUSY_SHIFT 10
4040#define MEM_EVAL_CHG_MASK 0x0300
4041#define MEM_EVAL_BUSY_SHIFT 8
4042#define MEM_MON_IDLE_MASK 0x00c0
4043#define MEM_MON_IDLE_SHIFT 6
4044#define MEM_UP_EVAL_MASK 0x0030
4045#define MEM_UP_EVAL_SHIFT 4
4046#define MEM_DOWN_EVAL_MASK 0x000c
4047#define MEM_DOWN_EVAL_SHIFT 2
4048#define MEM_SW_CMD_MASK 0x0003
4049#define MEM_INT_STEER_GFX 0
4050#define MEM_INT_STEER_CMR 1
4051#define MEM_INT_STEER_SMI 2
4052#define MEM_INT_STEER_SCI 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004053#define MEMINTRSTS _MMIO(0x11184)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004054#define MEMINT_RSEXIT (1 << 7)
4055#define MEMINT_CONT_BUSY (1 << 6)
4056#define MEMINT_AVG_BUSY (1 << 5)
4057#define MEMINT_EVAL_CHG (1 << 4)
4058#define MEMINT_MON_IDLE (1 << 3)
4059#define MEMINT_UP_EVAL (1 << 2)
4060#define MEMINT_DOWN_EVAL (1 << 1)
4061#define MEMINT_SW_CMD (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004062#define MEMMODECTL _MMIO(0x11190)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004063#define MEMMODE_BOOST_EN (1 << 31)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004064#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
4065#define MEMMODE_BOOST_FREQ_SHIFT 24
4066#define MEMMODE_IDLE_MODE_MASK 0x00030000
4067#define MEMMODE_IDLE_MODE_SHIFT 16
4068#define MEMMODE_IDLE_MODE_EVAL 0
4069#define MEMMODE_IDLE_MODE_CONT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004070#define MEMMODE_HWIDLE_EN (1 << 15)
4071#define MEMMODE_SWMODE_EN (1 << 14)
4072#define MEMMODE_RCLK_GATE (1 << 13)
4073#define MEMMODE_HW_UPDATE (1 << 12)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004074#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
4075#define MEMMODE_FSTART_SHIFT 8
4076#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
4077#define MEMMODE_FMAX_SHIFT 4
4078#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004079#define RCBMAXAVG _MMIO(0x1119c)
4080#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08004081#define SWMEMCMD_RENDER_OFF (0 << 13)
4082#define SWMEMCMD_RENDER_ON (1 << 13)
4083#define SWMEMCMD_SWFREQ (2 << 13)
4084#define SWMEMCMD_TARVID (3 << 13)
4085#define SWMEMCMD_VRM_OFF (4 << 13)
4086#define SWMEMCMD_VRM_ON (5 << 13)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004087#define CMDSTS (1 << 12)
4088#define SFCAVM (1 << 11)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004089#define SWFREQ_MASK 0x0380 /* P0-7 */
4090#define SWFREQ_SHIFT 7
4091#define TARVID_MASK 0x001f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004092#define MEMSTAT_CTG _MMIO(0x111a0)
4093#define RCBMINAVG _MMIO(0x111a0)
4094#define RCUPEI _MMIO(0x111b0)
4095#define RCDNEI _MMIO(0x111b4)
4096#define RSTDBYCTL _MMIO(0x111b8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004097#define RS1EN (1 << 31)
4098#define RS2EN (1 << 30)
4099#define RS3EN (1 << 29)
4100#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
4101#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
4102#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
4103#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
4104#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
4105#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
4106#define RSX_STATUS_MASK (7 << 20)
4107#define RSX_STATUS_ON (0 << 20)
4108#define RSX_STATUS_RC1 (1 << 20)
4109#define RSX_STATUS_RC1E (2 << 20)
4110#define RSX_STATUS_RS1 (3 << 20)
4111#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
4112#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
4113#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
4114#define RSX_STATUS_RSVD2 (7 << 20)
4115#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
4116#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
4117#define JRSC (1 << 17) /* rsx coupled to cpu c-state */
4118#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
4119#define RS1CONTSAV_MASK (3 << 14)
4120#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
4121#define RS1CONTSAV_RSVD (1 << 14)
4122#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
4123#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
4124#define NORMSLEXLAT_MASK (3 << 12)
4125#define SLOW_RS123 (0 << 12)
4126#define SLOW_RS23 (1 << 12)
4127#define SLOW_RS3 (2 << 12)
4128#define NORMAL_RS123 (3 << 12)
4129#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
4130#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
4131#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
4132#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
4133#define RS_CSTATE_MASK (3 << 4)
4134#define RS_CSTATE_C367_RS1 (0 << 4)
4135#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
4136#define RS_CSTATE_RSVD (2 << 4)
4137#define RS_CSTATE_C367_RS2 (3 << 4)
4138#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
4139#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004140#define VIDCTL _MMIO(0x111c0)
4141#define VIDSTS _MMIO(0x111c8)
4142#define VIDSTART _MMIO(0x111cc) /* 8 bits */
4143#define MEMSTAT_ILK _MMIO(0x111f8)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004144#define MEMSTAT_VID_MASK 0x7f00
4145#define MEMSTAT_VID_SHIFT 8
4146#define MEMSTAT_PSTATE_MASK 0x00f8
4147#define MEMSTAT_PSTATE_SHIFT 3
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004148#define MEMSTAT_MON_ACTV (1 << 2)
Jesse Barnesf97108d2010-01-29 11:27:07 -08004149#define MEMSTAT_SRC_CTL_MASK 0x0003
4150#define MEMSTAT_SRC_CTL_CORE 0
4151#define MEMSTAT_SRC_CTL_TRB 1
4152#define MEMSTAT_SRC_CTL_THM 2
4153#define MEMSTAT_SRC_CTL_STDBY 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004154#define RCPREVBSYTUPAVG _MMIO(0x113b8)
4155#define RCPREVBSYTDNAVG _MMIO(0x113bc)
4156#define PMMISC _MMIO(0x11214)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004157#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004158#define SDEW _MMIO(0x1124c)
4159#define CSIEW0 _MMIO(0x11250)
4160#define CSIEW1 _MMIO(0x11254)
4161#define CSIEW2 _MMIO(0x11258)
4162#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
4163#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
4164#define MCHAFE _MMIO(0x112c0)
4165#define CSIEC _MMIO(0x112e0)
4166#define DMIEC _MMIO(0x112e4)
4167#define DDREC _MMIO(0x112e8)
4168#define PEG0EC _MMIO(0x112ec)
4169#define PEG1EC _MMIO(0x112f0)
4170#define GFXEC _MMIO(0x112f4)
4171#define RPPREVBSYTUPAVG _MMIO(0x113b8)
4172#define RPPREVBSYTDNAVG _MMIO(0x113bc)
4173#define ECR _MMIO(0x11600)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004174#define ECR_GPFE (1 << 31)
4175#define ECR_IMONE (1 << 30)
Jesse Barnes7648fa92010-05-20 14:28:11 -07004176#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004177#define OGW0 _MMIO(0x11608)
4178#define OGW1 _MMIO(0x1160c)
4179#define EG0 _MMIO(0x11610)
4180#define EG1 _MMIO(0x11614)
4181#define EG2 _MMIO(0x11618)
4182#define EG3 _MMIO(0x1161c)
4183#define EG4 _MMIO(0x11620)
4184#define EG5 _MMIO(0x11624)
4185#define EG6 _MMIO(0x11628)
4186#define EG7 _MMIO(0x1162c)
4187#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
4188#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
4189#define LCFUSE02 _MMIO(0x116c0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07004190#define LCFUSE_HIV_MASK 0x000000ff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004191#define CSIPLL0 _MMIO(0x12c10)
4192#define DDRMPLL1 _MMIO(0X12c20)
4193#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
Eric Anholt7d573822009-01-02 13:33:00 -08004194
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004195#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
Chris Wilsonc4de7b02012-07-02 11:51:03 -03004196#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
Chris Wilsonc4de7b02012-07-02 11:51:03 -03004197
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004198#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4199#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4200#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4201#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
Vinay Belgaumkar025cb072021-07-30 13:21:16 -07004202#define RP0_CAP_MASK REG_GENMASK(7, 0)
4203#define RP1_CAP_MASK REG_GENMASK(15, 8)
4204#define RPN_CAP_MASK REG_GENMASK(23, 16)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004205#define BXT_RP_STATE_CAP _MMIO(0x138170)
Chris Wilson9938ee22020-04-20 18:27:36 +01004206#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
Matt Roperad482232021-08-05 09:36:44 -07004207#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08004208
Ville Syrjälä8a292d02016-04-20 16:43:56 +03004209/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08004210 * Logical Context regs
4211 */
Daniele Ceraolo Spuriobaba6e52019-03-25 14:49:40 -07004212#define CCID(base) _MMIO((base) + 0x180)
Chris Wilsonec62ed32017-02-07 15:24:37 +00004213#define CCID_EN BIT(0)
4214#define CCID_EXTENDED_STATE_RESTORE BIT(2)
4215#define CCID_EXTENDED_STATE_SAVE BIT(3)
Ville Syrjäläe8016052013-08-22 19:23:13 +03004216/*
4217 * Notes on SNB/IVB/VLV context size:
4218 * - Power context is saved elsewhere (LLC or stolen)
4219 * - Ring/execlist context is saved on SNB, not on IVB
4220 * - Extended context size already includes render context size
4221 * - We always need to follow the extended context size.
4222 * SNB BSpec has comments indicating that we should use the
4223 * render context size instead if execlists are disabled, but
4224 * based on empirical testing that's just nonsense.
4225 * - Pipelined/VF state is saved on SNB/IVB respectively
4226 * - GT1 size just indicates how much of render context
4227 * doesn't need saving on GT1
4228 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004229#define CXT_SIZE _MMIO(0x21a0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03004230#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
4231#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
4232#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
4233#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4234#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03004235#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07004236 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4237 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004238#define GEN7_CXT_SIZE _MMIO(0x21a8)
Ville Syrjälä68d97532015-09-18 20:03:39 +03004239#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
4240#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
4241#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
4242#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4243#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
4244#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03004245#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07004246 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawsky88976442013-11-02 21:07:05 -07004247
Zhi Wangc01fc532016-06-16 08:07:02 -04004248enum {
4249 INTEL_ADVANCED_CONTEXT = 0,
4250 INTEL_LEGACY_32B_CONTEXT,
4251 INTEL_ADVANCED_AD_CONTEXT,
4252 INTEL_LEGACY_64B_CONTEXT
4253};
4254
Mika Kuoppala2355cf02017-01-27 15:03:09 +02004255enum {
4256 FAULT_AND_HANG = 0,
4257 FAULT_AND_HALT, /* Debug only */
4258 FAULT_AND_STREAM,
4259 FAULT_AND_CONTINUE /* Unsupported */
4260};
4261
Matthew Brost3a4cdf12021-07-21 14:50:49 -07004262#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004263#define GEN8_CTX_VALID (1 << 0)
4264#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4265#define GEN8_CTX_FORCE_RESTORE (1 << 2)
4266#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4267#define GEN8_CTX_PRIVILEGE (1 << 8)
Zhi Wangc01fc532016-06-16 08:07:02 -04004268#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
Zhi Wangc01fc532016-06-16 08:07:02 -04004269
Mika Kuoppala2355cf02017-01-27 15:03:09 +02004270#define GEN8_CTX_ID_SHIFT 32
4271#define GEN8_CTX_ID_WIDTH 21
Daniele Ceraolo Spurioac52da62018-03-02 18:14:58 +02004272#define GEN11_SW_CTX_ID_SHIFT 37
4273#define GEN11_SW_CTX_ID_WIDTH 11
4274#define GEN11_ENGINE_CLASS_SHIFT 61
4275#define GEN11_ENGINE_CLASS_WIDTH 3
4276#define GEN11_ENGINE_INSTANCE_SHIFT 48
4277#define GEN11_ENGINE_INSTANCE_WIDTH 6
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004278
Stuart Summers50a9ea02021-07-21 15:30:33 -07004279#define XEHP_SW_CTX_ID_SHIFT 39
4280#define XEHP_SW_CTX_ID_WIDTH 16
4281#define XEHP_SW_COUNTER_SHIFT 58
4282#define XEHP_SW_COUNTER_WIDTH 6
4283
Mika Kuoppala542a6b22014-07-09 14:55:56 +03004284#define CHV_CLK_CTL1 _MMIO(0x101100)
Jesse Barnese454a052013-09-26 17:55:58 -07004285#define VLV_CLK_CTL2 _MMIO(0x101104)
4286#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
4287
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08004288/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004289 * Overlay regs
4290 */
4291
4292#define OVADD _MMIO(0x30000)
4293#define DOVSTA _MMIO(0x30008)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004294#define OC_BUF (0x3 << 20)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004295#define OGAMC5 _MMIO(0x30010)
4296#define OGAMC4 _MMIO(0x30014)
4297#define OGAMC3 _MMIO(0x30018)
4298#define OGAMC2 _MMIO(0x3001c)
4299#define OGAMC1 _MMIO(0x30020)
4300#define OGAMC0 _MMIO(0x30024)
Jesse Barnes585fb112008-07-29 11:54:06 -07004301
4302/*
Imre Deakd965e7ac2015-12-01 10:23:52 +02004303 * GEN9 clock gating regs
4304 */
4305#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
Rodrigo Vividf49ec82017-11-10 16:03:19 -08004306#define DARBF_GATING_DIS (1 << 27)
Imre Deakd965e7ac2015-12-01 10:23:52 +02004307#define PWM2_GATING_DIS (1 << 14)
4308#define PWM1_GATING_DIS (1 << 13)
4309
Radhakrishna Sripadaf78d5da2020-01-09 14:37:27 -08004310#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
4311#define TGL_VRH_GATING_DIS REG_BIT(31)
Stuart Summersda9427502020-10-14 12:19:34 -07004312#define DPT_GATING_DIS REG_BIT(22)
Radhakrishna Sripadaf78d5da2020-01-09 14:37:27 -08004313
Ville Syrjälä6481d5e2017-12-21 22:24:32 +02004314#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
4315#define BXT_GMBUS_GATING_DIS (1 << 14)
4316
José Roberto de Souzaa8a56da2021-05-14 08:37:09 -07004317#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
4318#define DPCE_GATING_DIS REG_BIT(17)
4319
Imre Deaked69cd42017-10-02 10:55:57 +03004320#define _CLKGATE_DIS_PSL_A 0x46520
4321#define _CLKGATE_DIS_PSL_B 0x46524
4322#define _CLKGATE_DIS_PSL_C 0x46528
Vidya Srinivasc4a4efa2018-04-09 09:11:09 +05304323#define DUPS1_GATING_DIS (1 << 15)
4324#define DUPS2_GATING_DIS (1 << 19)
4325#define DUPS3_GATING_DIS (1 << 23)
Tejas Upadhyay11408ea2021-09-29 10:54:42 +05304326#define CURSOR_GATING_DIS REG_BIT(28)
Imre Deaked69cd42017-10-02 10:55:57 +03004327#define DPF_GATING_DIS (1 << 10)
4328#define DPF_RAM_GATING_DIS (1 << 9)
4329#define DPFR_GATING_DIS (1 << 8)
4330
4331#define CLKGATE_DIS_PSL(pipe) \
4332 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4333
Imre Deakd965e7ac2015-12-01 10:23:52 +02004334/*
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07004335 * GEN10 clock gating regs
4336 */
Stuart Summersd73dd1f2021-11-02 15:25:09 -07004337
4338#define UNSLCGCTL9440 _MMIO(0x9440)
4339#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
4340#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
4341#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
4342#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
4343#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
4344#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
4345#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
4346#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
4347#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
4348#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
4349#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
4350#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
4351
4352#define UNSLCGCTL9444 _MMIO(0x9444)
4353#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
4354#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
4355#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
4356#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
4357#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
4358#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
4359#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
4360#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
4361#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
4362#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
4363#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
4364#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
4365#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
4366#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
4367#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
4368#define LTCDD_CLKGATE_DIS REG_BIT(10)
4369
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07004370#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4371#define SARBUNIT_CLKGATE_DIS (1 << 5)
Rafael Antognolli0a607972017-11-03 11:30:27 -07004372#define RCCUNIT_CLKGATE_DIS (1 << 7)
Oscar Mateo0a437d42018-05-08 14:29:31 -07004373#define MSCUNIT_CLKGATE_DIS (1 << 10)
Matt Roper645cc0b2021-11-02 15:25:10 -07004374#define NODEDSS_CLKGATE_DIS REG_BIT(12)
Mika Kuoppalada5d2ca2019-10-15 18:44:11 +03004375#define L3_CLKGATE_DIS REG_BIT(16)
4376#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07004377
Rodrigo Vivia4713c52018-03-07 14:09:12 -08004378#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
Matt Roper645cc0b2021-11-02 15:25:10 -07004379#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
4380#define GWUNIT_CLKGATE_DIS REG_BIT(16)
Rodrigo Vivia4713c52018-03-07 14:09:12 -08004381
Mika Kuoppala65df78b2019-10-15 18:44:44 +03004382#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
4383#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
4384
Matt Roper645cc0b2021-11-02 15:25:10 -07004385#define SSMCGCTL9530 _MMIO(0x9530)
4386#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
4387
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08004388#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
Matt Roperb9cf9da2019-12-23 17:20:25 -08004389#define VFUNIT_CLKGATE_DIS REG_BIT(20)
Matt Roper645cc0b2021-11-02 15:25:10 -07004390#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
4391#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
4392#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
Matt Roperb9cf9da2019-12-23 17:20:25 -08004393#define HSUNIT_CLKGATE_DIS REG_BIT(8)
4394#define VSUNIT_CLKGATE_DIS REG_BIT(3)
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08004395
Matt Roper4ca15382019-12-23 17:20:26 -08004396#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
4397#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
Matt Roper1cd21a72019-12-31 11:07:13 -08004398#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
Matt Roper4ca15382019-12-23 17:20:26 -08004399
Oscar Mateo5ba700c2018-05-08 14:29:34 -07004400#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4401#define CGPSF_CLKGATE_DIS (1 << 3)
4402
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07004403/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004404 * Display engine regs
4405 */
4406
Shuang He8bf1e9f2013-10-15 18:55:27 +01004407/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004408#define _PIPE_CRC_CTL_A 0x60050
Ville Syrjälä51707f22021-11-12 21:38:11 +02004409#define PIPE_CRC_ENABLE REG_BIT(31)
Ville Syrjälä207a8152019-02-14 21:22:19 +02004410/* skl+ source selection */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004411#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
4412#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
4413#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
4414#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
4415#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
4416#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
4417#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
4418#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
4419#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004420/* ivb+ source selection */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004421#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
4422#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
4423#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
4424#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004425/* ilk+ source selection */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004426#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
4427#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
4428#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
4429#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
4430/* embedded DP port on the north display block */
4431#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
4432#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004433/* vlv source selection */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004434#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
4435#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
4436#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
4437#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004438/* with DP port the pipe source is invalid */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004439#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
4440#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
4441#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004442/* gen3+ source selection */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004443#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
4444#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
4445#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
4446#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004447/* with DP/TV port the pipe source is invalid */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004448#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
4449#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
4450#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
4451#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
4452#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004453/* gen2 doesn't have source selection bits */
Ville Syrjälä51707f22021-11-12 21:38:11 +02004454#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02004455
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02004456#define _PIPE_CRC_RES_1_A_IVB 0x60064
4457#define _PIPE_CRC_RES_2_A_IVB 0x60068
4458#define _PIPE_CRC_RES_3_A_IVB 0x6006c
4459#define _PIPE_CRC_RES_4_A_IVB 0x60070
4460#define _PIPE_CRC_RES_5_A_IVB 0x60074
4461
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004462#define _PIPE_CRC_RES_RED_A 0x60060
4463#define _PIPE_CRC_RES_GREEN_A 0x60064
4464#define _PIPE_CRC_RES_BLUE_A 0x60068
4465#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4466#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01004467
4468/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02004469#define _PIPE_CRC_RES_1_B_IVB 0x61064
4470#define _PIPE_CRC_RES_2_B_IVB 0x61068
4471#define _PIPE_CRC_RES_3_B_IVB 0x6106c
4472#define _PIPE_CRC_RES_4_B_IVB 0x61070
4473#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01004474
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004475#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4476#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4477#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4478#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4479#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4480#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01004481
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004482#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4483#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4484#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4485#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4486#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02004487
Jesse Barnes585fb112008-07-29 11:54:06 -07004488/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004489#define _HTOTAL_A 0x60000
4490#define _HBLANK_A 0x60004
4491#define _HSYNC_A 0x60008
4492#define _VTOTAL_A 0x6000c
4493#define _VBLANK_A 0x60010
4494#define _VSYNC_A 0x60014
Anshuman Guptae45e0002019-10-07 15:16:07 +05304495#define _EXITLINE_A 0x60018
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004496#define _PIPEASRC 0x6001c
4497#define _BCLRPAT_A 0x60020
4498#define _VSYNCSHIFT_A 0x60028
Clint Taylorebb69c92014-09-30 10:30:22 -07004499#define _PIPE_MULT_A 0x6002c
Jesse Barnes585fb112008-07-29 11:54:06 -07004500
4501/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004502#define _HTOTAL_B 0x61000
4503#define _HBLANK_B 0x61004
4504#define _HSYNC_B 0x61008
4505#define _VTOTAL_B 0x6100c
4506#define _VBLANK_B 0x61010
4507#define _VSYNC_B 0x61014
4508#define _PIPEBSRC 0x6101c
4509#define _BCLRPAT_B 0x61020
4510#define _VSYNCSHIFT_B 0x61028
Clint Taylorebb69c92014-09-30 10:30:22 -07004511#define _PIPE_MULT_B 0x6102c
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004512
Madhav Chauhan7b56caf2018-10-15 17:28:02 +03004513/* DSI 0 timing regs */
4514#define _HTOTAL_DSI0 0x6b000
4515#define _HSYNC_DSI0 0x6b008
4516#define _VTOTAL_DSI0 0x6b00c
4517#define _VSYNC_DSI0 0x6b014
4518#define _VSYNCSHIFT_DSI0 0x6b028
4519
4520/* DSI 1 timing regs */
4521#define _HTOTAL_DSI1 0x6b800
4522#define _HSYNC_DSI1 0x6b808
4523#define _VTOTAL_DSI1 0x6b80c
4524#define _VSYNC_DSI1 0x6b814
4525#define _VSYNCSHIFT_DSI1 0x6b828
4526
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004527#define TRANSCODER_A_OFFSET 0x60000
4528#define TRANSCODER_B_OFFSET 0x61000
4529#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03004530#define CHV_TRANSCODER_C_OFFSET 0x63000
Lucas De Marchif1f1d4f2019-07-11 10:30:55 -07004531#define TRANSCODER_D_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004532#define TRANSCODER_EDP_OFFSET 0x6f000
Madhav Chauhan49edbd42018-10-15 17:28:00 +03004533#define TRANSCODER_DSI0_OFFSET 0x6b000
4534#define TRANSCODER_DSI1_OFFSET 0x6b800
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004535
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004536#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4537#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4538#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4539#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4540#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4541#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4542#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4543#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4544#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4545#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
Chris Wilson5eddb702010-09-11 13:48:45 +01004546
Anshuman Guptae45e0002019-10-07 15:16:07 +05304547#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
4548#define EXITLINE_ENABLE REG_BIT(31)
4549#define EXITLINE_MASK REG_GENMASK(12, 0)
4550#define EXITLINE_SHIFT 0
4551
Aditya Swarup106d4ffd2020-03-18 18:59:41 -07004552/* VRR registers */
4553#define _TRANS_VRR_CTL_A 0x60420
4554#define _TRANS_VRR_CTL_B 0x61420
4555#define _TRANS_VRR_CTL_C 0x62420
4556#define _TRANS_VRR_CTL_D 0x63420
Ville Syrjälädc89bb82021-01-22 15:26:38 -08004557#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
4558#define VRR_CTL_VRR_ENABLE REG_BIT(31)
4559#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
4560#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
4561#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
4562#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
4563#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
Manasi Navarebb265db2021-05-25 17:06:55 -07004564#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
4565#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
Aditya Swarup106d4ffd2020-03-18 18:59:41 -07004566
4567#define _TRANS_VRR_VMAX_A 0x60424
4568#define _TRANS_VRR_VMAX_B 0x61424
4569#define _TRANS_VRR_VMAX_C 0x62424
4570#define _TRANS_VRR_VMAX_D 0x63424
4571#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
4572#define VRR_VMAX_MASK REG_GENMASK(19, 0)
4573
4574#define _TRANS_VRR_VMIN_A 0x60434
4575#define _TRANS_VRR_VMIN_B 0x61434
4576#define _TRANS_VRR_VMIN_C 0x62434
4577#define _TRANS_VRR_VMIN_D 0x63434
4578#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
4579#define VRR_VMIN_MASK REG_GENMASK(15, 0)
4580
4581#define _TRANS_VRR_VMAXSHIFT_A 0x60428
4582#define _TRANS_VRR_VMAXSHIFT_B 0x61428
4583#define _TRANS_VRR_VMAXSHIFT_C 0x62428
4584#define _TRANS_VRR_VMAXSHIFT_D 0x63428
4585#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
4586 _TRANS_VRR_VMAXSHIFT_A)
4587#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
4588#define VRR_VMAXSHIFT_DEC REG_BIT(16)
4589#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
4590
4591#define _TRANS_VRR_STATUS_A 0x6042C
4592#define _TRANS_VRR_STATUS_B 0x6142C
4593#define _TRANS_VRR_STATUS_C 0x6242C
4594#define _TRANS_VRR_STATUS_D 0x6342C
4595#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
4596#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
4597#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
4598#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
4599#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
4600#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
4601#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
4602#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
4603#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4604#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
4605#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
4606#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
4607#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
4608#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
4609#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
4610
4611#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
4612#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
4613#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
4614#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
4615#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
4616 _TRANS_VRR_VTOTAL_PREV_A)
4617#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
4618#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
4619#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
4620#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
4621
4622#define _TRANS_VRR_FLIPLINE_A 0x60438
4623#define _TRANS_VRR_FLIPLINE_B 0x61438
4624#define _TRANS_VRR_FLIPLINE_C 0x62438
4625#define _TRANS_VRR_FLIPLINE_D 0x63438
4626#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
4627 _TRANS_VRR_FLIPLINE_A)
4628#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
4629
4630#define _TRANS_VRR_STATUS2_A 0x6043C
4631#define _TRANS_VRR_STATUS2_B 0x6143C
4632#define _TRANS_VRR_STATUS2_C 0x6243C
4633#define _TRANS_VRR_STATUS2_D 0x6343C
4634#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
4635#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
4636
4637#define _TRANS_PUSH_A 0x60A70
4638#define _TRANS_PUSH_B 0x61A70
4639#define _TRANS_PUSH_C 0x62A70
4640#define _TRANS_PUSH_D 0x63A70
4641#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
4642#define TRANS_PUSH_EN REG_BIT(31)
4643#define TRANS_PUSH_SEND REG_BIT(30)
4644
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004645/*
4646 * HSW+ eDP PSR registers
4647 *
4648 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4649 * instance of it
4650 */
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004651#define _SRD_CTL_A 0x60800
4652#define _SRD_CTL_EDP 0x6f800
José Roberto de Souzaad264512021-08-27 10:42:51 -07004653#define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A))
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004654#define EDP_PSR_ENABLE (1 << 31)
4655#define BDW_PSR_SINGLE_FRAME (1 << 30)
4656#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4657#define EDP_PSR_LINK_STANDBY (1 << 27)
4658#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4659#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4660#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4661#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4662#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004663#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004664#define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4665#define EDP_PSR_TP1_TP2_SEL (0 << 11)
4666#define EDP_PSR_TP1_TP3_SEL (1 << 11)
José Roberto de Souza00c8f192018-06-26 13:16:44 -07004667#define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004668#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4669#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4670#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4671#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
José Roberto de Souza8a9a5602019-03-12 12:57:43 -07004672#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004673#define EDP_PSR_TP1_TIME_500us (0 << 4)
4674#define EDP_PSR_TP1_TIME_100us (1 << 4)
4675#define EDP_PSR_TP1_TIME_2500us (2 << 4)
4676#define EDP_PSR_TP1_TIME_0us (3 << 4)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004677#define EDP_PSR_IDLE_FRAME_SHIFT 0
4678
José Roberto de Souza8241cfb2019-09-04 14:34:15 -07004679/*
4680 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4681 * to transcoder and bits defined for each one as if using no shift (i.e. as if
4682 * it was for TRANSCODER_EDP)
4683 */
Daniel Vetterfc340442018-04-05 15:00:23 -07004684#define EDP_PSR_IMR _MMIO(0x64834)
4685#define EDP_PSR_IIR _MMIO(0x64838)
José Roberto de Souza8241cfb2019-09-04 14:34:15 -07004686#define _PSR_IMR_A 0x60814
4687#define _PSR_IIR_A 0x60818
4688#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
4689#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
José Roberto de Souza2f3b8712019-09-04 14:34:14 -07004690#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
4691 0 : ((trans) - TRANSCODER_A + 1) * 8)
4692#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4693#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4694#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4695#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
Daniel Vetterfc340442018-04-05 15:00:23 -07004696
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004697#define _SRD_AUX_DATA_A 0x60814
4698#define _SRD_AUX_DATA_EDP 0x6f814
José Roberto de Souzaad264512021-08-27 10:42:51 -07004699#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004700
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004701#define _SRD_STATUS_A 0x60840
4702#define _SRD_STATUS_EDP 0x6f840
José Roberto de Souzaad264512021-08-27 10:42:51 -07004703#define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A))
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004704#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
Vathsala Nagaraju00b06292018-06-27 13:38:30 +05304705#define EDP_PSR_STATUS_STATE_SHIFT 29
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004706#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4707#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4708#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4709#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4710#define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4711#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4712#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4713#define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4714#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4715#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4716#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004717#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4718#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4719#define EDP_PSR_STATUS_COUNT_SHIFT 16
4720#define EDP_PSR_STATUS_COUNT_MASK 0xf
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004721#define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4722#define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4723#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4724#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4725#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004726#define EDP_PSR_STATUS_IDLE_MASK 0xf
4727
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004728#define _SRD_PERF_CNT_A 0x60844
4729#define _SRD_PERF_CNT_EDP 0x6f844
José Roberto de Souzaad264512021-08-27 10:42:51 -07004730#define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004731#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004732
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004733/* PSR_MASK on SKL+ */
4734#define _SRD_DEBUG_A 0x60860
4735#define _SRD_DEBUG_EDP 0x6f860
José Roberto de Souzaad264512021-08-27 10:42:51 -07004736#define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004737#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4738#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4739#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4740#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
José Roberto de Souzafc6ff9d2018-10-03 13:50:26 -07004741#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004742#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004743
Gwan-gyeong Mun64cf40a2020-06-07 17:36:14 +03004744#define _PSR2_CTL_A 0x60900
4745#define _PSR2_CTL_EDP 0x6f900
4746#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
4747#define EDP_PSR2_ENABLE (1 << 31)
José Roberto de Souza36203e42021-06-25 16:55:59 -07004748#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
Gwan-gyeong Mun64cf40a2020-06-07 17:36:14 +03004749#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
4750#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
José Roberto de Souza38f46182021-04-21 15:02:24 -07004751#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
José Roberto de Souza61e88732021-06-16 13:31:56 -07004752#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
Gwan-gyeong Mun64cf40a2020-06-07 17:36:14 +03004753#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4754#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4755#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
4756#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4757#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
4758#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
José Roberto de Souza061093d2021-06-16 13:31:54 -07004759#define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13
4760#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
Gwan-gyeong Mun64cf40a2020-06-07 17:36:14 +03004761#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
4762#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
4763#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4764#define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
4765#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
José Roberto de Souza061093d2021-06-16 13:31:54 -07004766#define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10
4767#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
Gwan-gyeong Mun64cf40a2020-06-07 17:36:14 +03004768#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
4769#define EDP_PSR2_TP2_TIME_500us (0 << 8)
4770#define EDP_PSR2_TP2_TIME_100us (1 << 8)
4771#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4772#define EDP_PSR2_TP2_TIME_50us (3 << 8)
4773#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4774#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4775#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4776#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4777#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4778#define EDP_PSR2_IDLE_FRAME_SHIFT 0
Sonika Jindal474d1ec2015-04-02 11:02:44 +05304779
José Roberto de Souzabc18b4d2018-04-25 14:23:32 -07004780#define _PSR_EVENT_TRANS_A 0x60848
4781#define _PSR_EVENT_TRANS_B 0x61848
4782#define _PSR_EVENT_TRANS_C 0x62848
4783#define _PSR_EVENT_TRANS_D 0x63848
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004784#define _PSR_EVENT_TRANS_EDP 0x6f848
4785#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
José Roberto de Souzabc18b4d2018-04-25 14:23:32 -07004786#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4787#define PSR_EVENT_PSR2_DISABLED (1 << 16)
4788#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4789#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4790#define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4791#define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4792#define PSR_EVENT_MEMORY_UP (1 << 10)
4793#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4794#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4795#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
José Roberto de Souzafc6ff9d2018-10-03 13:50:26 -07004796#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
José Roberto de Souzabc18b4d2018-04-25 14:23:32 -07004797#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4798#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4799#define PSR_EVENT_VBI_ENABLE (1 << 2)
4800#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4801#define PSR_EVENT_PSR_DISABLE (1 << 0)
4802
José Roberto de Souzafed98c12021-10-05 16:18:51 -07004803#define _PSR2_STATUS_A 0x60940
4804#define _PSR2_STATUS_EDP 0x6f940
4805#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
4806#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
4807#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
Jesse Barnes585fb112008-07-29 11:54:06 -07004808
José Roberto de Souza4ab4fa12019-08-20 15:33:23 -07004809#define _PSR2_SU_STATUS_A 0x60914
4810#define _PSR2_SU_STATUS_EDP 0x6f914
4811#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4812#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
José Roberto de Souzacc8853f2019-01-17 12:55:47 -08004813#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4814#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4815#define PSR2_SU_STATUS_FRAMES 8
4816
José Roberto de Souza36203e42021-06-25 16:55:59 -07004817#define _PSR2_MAN_TRK_CTL_A 0x60910
4818#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
4819#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
4820#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
4821#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
4822#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
José Roberto de Souzaa5523e22020-06-25 18:01:49 -07004823#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
4824#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
José Roberto de Souza36203e42021-06-25 16:55:59 -07004825#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
4826#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
4827#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
4828#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
4829#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4830#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
4831#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4832#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
4833#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
José Roberto de Souzaa5523e22020-06-25 18:01:49 -07004834
Ville Syrjälä2849e1a2020-10-06 17:33:30 +03004835/* Icelake DSC Rate Control Range Parameter Registers */
4836#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
4837#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
4838#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
4839#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
4840#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
4841#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
4842#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
4843#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
4844#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
4845#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
4846#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
4847#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
4848#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4849 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
4850 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
4851#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4852 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
4853 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
4854#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4855 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
4856 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
4857#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4858 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
4859 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
4860#define RC_BPG_OFFSET_SHIFT 10
4861#define RC_MAX_QP_SHIFT 5
4862#define RC_MIN_QP_SHIFT 0
4863
4864#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
4865#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
4866#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
4867#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
4868#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
4869#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
4870#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
4871#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
4872#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
4873#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
4874#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
4875#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
4876#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4877 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
4878 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
4879#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4880 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
4881 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
4882#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4883 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
4884 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
4885#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4886 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
4887 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
4888
4889#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
4890#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
4891#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
4892#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
4893#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
4894#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
4895#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
4896#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
4897#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
4898#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
4899#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
4900#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
4901#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4902 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
4903 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
4904#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4905 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
4906 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
4907#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4908 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
4909 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
4910#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4911 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
4912 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
4913
4914#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
4915#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
4916#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
4917#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
4918#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
4919#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
4920#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
4921#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
4922#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
4923#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
4924#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
4925#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
4926#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4927 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
4928 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
4929#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4930 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
4931 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
4932#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4933 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
4934 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
4935#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4936 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
4937 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
4938
Jesse Barnes585fb112008-07-29 11:54:06 -07004939/* VGA port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004940#define ADPA _MMIO(0x61100)
4941#define PCH_ADPA _MMIO(0xe1100)
4942#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02004943
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004944#define ADPA_DAC_ENABLE (1 << 31)
Jesse Barnes585fb112008-07-29 11:54:06 -07004945#define ADPA_DAC_DISABLE 0
Ville Syrjälä6102a8e2018-05-14 20:24:19 +03004946#define ADPA_PIPE_SEL_SHIFT 30
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004947#define ADPA_PIPE_SEL_MASK (1 << 30)
Ville Syrjälä6102a8e2018-05-14 20:24:19 +03004948#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4949#define ADPA_PIPE_SEL_SHIFT_CPT 29
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004950#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
Ville Syrjälä6102a8e2018-05-14 20:24:19 +03004951#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02004952#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004953#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4954#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4955#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4956#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4957#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4958#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4959#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4960#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4961#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4962#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4963#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4964#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4965#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4966#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4967#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4968#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4969#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4970#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4971#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07004972#define ADPA_SETS_HVPOLARITY 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004973#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
Jesse Barnes585fb112008-07-29 11:54:06 -07004974#define ADPA_VSYNC_CNTL_ENABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004975#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
Jesse Barnes585fb112008-07-29 11:54:06 -07004976#define ADPA_HSYNC_CNTL_ENABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004977#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07004978#define ADPA_VSYNC_ACTIVE_LOW 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004979#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
Jesse Barnes585fb112008-07-29 11:54:06 -07004980#define ADPA_HSYNC_ACTIVE_LOW 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07004981#define ADPA_DPMS_MASK (~(3 << 10))
4982#define ADPA_DPMS_ON (0 << 10)
4983#define ADPA_DPMS_SUSPEND (1 << 10)
4984#define ADPA_DPMS_STANDBY (2 << 10)
4985#define ADPA_DPMS_OFF (3 << 10)
Jesse Barnes585fb112008-07-29 11:54:06 -07004986
Chris Wilson939fe4d2010-10-09 10:33:26 +01004987
Jesse Barnes585fb112008-07-29 11:54:06 -07004988/* Hotplug control (945+ only) */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02004989#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01004990#define PORTB_HOTPLUG_INT_EN (1 << 29)
4991#define PORTC_HOTPLUG_INT_EN (1 << 28)
4992#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07004993#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4994#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4995#define TV_HOTPLUG_INT_EN (1 << 18)
4996#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05004997#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4998 PORTC_HOTPLUG_INT_EN | \
4999 PORTD_HOTPLUG_INT_EN | \
5000 SDVOC_HOTPLUG_INT_EN | \
5001 SDVOB_HOTPLUG_INT_EN | \
5002 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07005003#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08005004#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
5005/* must use period 64 on GM45 according to docs */
5006#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
5007#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
5008#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
5009#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
5010#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
5011#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
5012#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
5013#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
5014#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
5015#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
5016#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
5017#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07005018
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005019#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02005020/*
Ville Syrjälä0780cd32016-02-10 19:59:05 +02005021 * HDMI/DP bits are g4x+
Daniel Vetter0ce99f72013-07-26 11:27:49 +02005022 *
5023 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
5024 * Please check the detailed lore in the commit message for for experimental
5025 * evidence.
5026 */
Ville Syrjälä0780cd32016-02-10 19:59:05 +02005027/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
5028#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
5029#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
5030#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
5031/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
5032#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
Todd Previte232a6ee2014-01-23 00:13:41 -07005033#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
Ville Syrjälä0780cd32016-02-10 19:59:05 +02005034#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01005035#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02005036#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
5037#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01005038#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02005039#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
5040#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01005041#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02005042#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
5043#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01005044/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07005045#define CRT_HOTPLUG_INT_STATUS (1 << 11)
5046#define TV_HOTPLUG_INT_STATUS (1 << 10)
5047#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
5048#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
5049#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
5050#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01005051#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
5052#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
5053#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02005054#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
5055
Chris Wilson084b6122012-05-11 18:01:33 +01005056/* SDVO is different across gen3/4 */
5057#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
5058#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02005059/*
5060 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
5061 * since reality corrobates that they're the same as on gen3. But keep these
5062 * bits here (and the comment!) to help any other lost wanderers back onto the
5063 * right tracks.
5064 */
Chris Wilson084b6122012-05-11 18:01:33 +01005065#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
5066#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
5067#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
5068#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05005069#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
5070 SDVOB_HOTPLUG_INT_STATUS_G4X | \
5071 SDVOC_HOTPLUG_INT_STATUS_G4X | \
5072 PORTB_HOTPLUG_INT_STATUS | \
5073 PORTC_HOTPLUG_INT_STATUS | \
5074 PORTD_HOTPLUG_INT_STATUS)
5075
Egbert Eiche5868a32013-02-28 04:17:12 -05005076#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
5077 SDVOB_HOTPLUG_INT_STATUS_I915 | \
5078 SDVOC_HOTPLUG_INT_STATUS_I915 | \
5079 PORTB_HOTPLUG_INT_STATUS | \
5080 PORTC_HOTPLUG_INT_STATUS | \
5081 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07005082
Paulo Zanonic20cd312013-02-19 16:21:45 -03005083/* SDVO and HDMI port control.
5084 * The same register may be used for SDVO or HDMI */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005085#define _GEN3_SDVOB 0x61140
5086#define _GEN3_SDVOC 0x61160
5087#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
5088#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005089#define GEN4_HDMIB GEN3_SDVOB
5090#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005091#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
5092#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
5093#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
5094#define PCH_SDVOB _MMIO(0xe1140)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005095#define PCH_HDMIB PCH_SDVOB
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005096#define PCH_HDMIC _MMIO(0xe1150)
5097#define PCH_HDMID _MMIO(0xe1160)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005098
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005099#define PORT_DFT_I9XX _MMIO(0x61150)
Daniel Vetter84093602013-11-01 10:50:21 +01005100#define DC_BALANCE_RESET (1 << 25)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005101#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01005102#define DC_BALANCE_RESET_VLV (1 << 31)
Ville Syrjäläeb736672014-12-09 21:28:28 +02005103#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
Ville Syrjälä51707f22021-11-12 21:38:11 +02005104#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
5105#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
5106#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
Daniel Vetter84093602013-11-01 10:50:21 +01005107
Paulo Zanonic20cd312013-02-19 16:21:45 -03005108/* Gen 3 SDVO bits: */
5109#define SDVO_ENABLE (1 << 31)
Ville Syrjälä76203462018-05-14 20:24:21 +03005110#define SDVO_PIPE_SEL_SHIFT 30
Paulo Zanonidc0fa712013-02-19 16:21:46 -03005111#define SDVO_PIPE_SEL_MASK (1 << 30)
Ville Syrjälä76203462018-05-14 20:24:21 +03005112#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005113#define SDVO_STALL_SELECT (1 << 29)
5114#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005115/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005116 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07005117 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07005118 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
5119 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03005120#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07005121#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03005122#define SDVO_PHASE_SELECT_MASK (15 << 19)
5123#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
5124#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
5125#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
5126#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
5127#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
5128#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07005129/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03005130#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
5131 SDVO_INTERRUPT_ENABLE)
5132#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
5133
5134/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03005135#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03005136#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005137#define SDVO_ENCODING_SDVO (0 << 10)
5138#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03005139#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
5140#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03005141#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Ville Syrjälädd6090f2019-04-09 17:40:50 +03005142#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03005143/* VSYNC/HSYNC bits new with 965, default is to be set */
5144#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
5145#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
5146
5147/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03005148#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03005149#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
5150
5151/* Gen 6 (CPT) SDVO/HDMI bits: */
Ville Syrjälä76203462018-05-14 20:24:21 +03005152#define SDVO_PIPE_SEL_SHIFT_CPT 29
Paulo Zanonidc0fa712013-02-19 16:21:46 -03005153#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Ville Syrjälä76203462018-05-14 20:24:21 +03005154#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03005155
Chon Ming Lee44f37d12014-04-09 13:28:21 +03005156/* CHV SDVO/HDMI bits: */
Ville Syrjälä76203462018-05-14 20:24:21 +03005157#define SDVO_PIPE_SEL_SHIFT_CHV 24
Chon Ming Lee44f37d12014-04-09 13:28:21 +03005158#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
Ville Syrjälä76203462018-05-14 20:24:21 +03005159#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03005160
Jesse Barnes585fb112008-07-29 11:54:06 -07005161
5162/* DVO port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005163#define _DVOA 0x61120
5164#define DVOA _MMIO(_DVOA)
5165#define _DVOB 0x61140
5166#define DVOB _MMIO(_DVOB)
5167#define _DVOC 0x61160
5168#define DVOC _MMIO(_DVOC)
Jesse Barnes585fb112008-07-29 11:54:06 -07005169#define DVO_ENABLE (1 << 31)
Ville Syrjäläb45a2582018-05-14 20:24:23 +03005170#define DVO_PIPE_SEL_SHIFT 30
5171#define DVO_PIPE_SEL_MASK (1 << 30)
5172#define DVO_PIPE_SEL(pipe) ((pipe) << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07005173#define DVO_PIPE_STALL_UNUSED (0 << 28)
5174#define DVO_PIPE_STALL (1 << 28)
5175#define DVO_PIPE_STALL_TV (2 << 28)
5176#define DVO_PIPE_STALL_MASK (3 << 28)
5177#define DVO_USE_VGA_SYNC (1 << 15)
5178#define DVO_DATA_ORDER_I740 (0 << 14)
5179#define DVO_DATA_ORDER_FP (1 << 14)
5180#define DVO_VSYNC_DISABLE (1 << 11)
5181#define DVO_HSYNC_DISABLE (1 << 10)
5182#define DVO_VSYNC_TRISTATE (1 << 9)
5183#define DVO_HSYNC_TRISTATE (1 << 8)
5184#define DVO_BORDER_ENABLE (1 << 7)
5185#define DVO_DATA_ORDER_GBRG (1 << 6)
5186#define DVO_DATA_ORDER_RGGB (0 << 6)
5187#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
5188#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
5189#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
5190#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
5191#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
5192#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
5193#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07005194#define DVO_PRESERVE_MASK (0x7 << 24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005195#define DVOA_SRCDIM _MMIO(0x61124)
5196#define DVOB_SRCDIM _MMIO(0x61144)
5197#define DVOC_SRCDIM _MMIO(0x61164)
Jesse Barnes585fb112008-07-29 11:54:06 -07005198#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
5199#define DVO_SRCDIM_VERTICAL_SHIFT 0
5200
5201/* LVDS port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005202#define LVDS _MMIO(0x61180)
Jesse Barnes585fb112008-07-29 11:54:06 -07005203/*
5204 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
5205 * the DPLL semantics change when the LVDS is assigned to that pipe.
5206 */
5207#define LVDS_PORT_EN (1 << 31)
5208/* Selects pipe B for LVDS data. Must be set on pre-965. */
Ville Syrjäläa44628b2018-05-14 21:28:27 +03005209#define LVDS_PIPE_SEL_SHIFT 30
5210#define LVDS_PIPE_SEL_MASK (1 << 30)
5211#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
5212#define LVDS_PIPE_SEL_SHIFT_CPT 29
5213#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
5214#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
Zhao Yakui898822c2010-01-04 16:29:30 +08005215/* LVDS dithering flag on 965/g4x platform */
5216#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08005217/* LVDS sync polarity flags. Set to invert (i.e. negative) */
5218#define LVDS_VSYNC_POLARITY (1 << 21)
5219#define LVDS_HSYNC_POLARITY (1 << 20)
5220
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005221/* Enable border for unscaled (or aspect-scaled) display */
5222#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07005223/*
5224 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
5225 * pixel.
5226 */
5227#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
5228#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
5229#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
5230/*
5231 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
5232 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
5233 * on.
5234 */
5235#define LVDS_A3_POWER_MASK (3 << 6)
5236#define LVDS_A3_POWER_DOWN (0 << 6)
5237#define LVDS_A3_POWER_UP (3 << 6)
5238/*
5239 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
5240 * is set.
5241 */
5242#define LVDS_CLKB_POWER_MASK (3 << 4)
5243#define LVDS_CLKB_POWER_DOWN (0 << 4)
5244#define LVDS_CLKB_POWER_UP (3 << 4)
5245/*
5246 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
5247 * setting for whether we are in dual-channel mode. The B3 pair will
5248 * additionally only be powered up when LVDS_A3_POWER_UP is set.
5249 */
5250#define LVDS_B0B3_POWER_MASK (3 << 2)
5251#define LVDS_B0B3_POWER_DOWN (0 << 2)
5252#define LVDS_B0B3_POWER_UP (3 << 2)
5253
David Härdeman3c17fe42010-09-24 21:44:32 +02005254/* Video Data Island Packet control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005255#define VIDEO_DIP_DATA _MMIO(0x61178)
Yannick Guerrinifd0753c2015-02-28 17:20:41 +01005256/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
Paulo Zanoniadf00b22012-09-25 13:23:34 -03005257 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
5258 * of the infoframe structure specified by CEA-861. */
5259#define VIDEO_DIP_DATA_SIZE 32
Gwan-gyeong Mun922430d2019-09-19 22:53:09 +03005260#define VIDEO_DIP_GMP_DATA_SIZE 36
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03005261#define VIDEO_DIP_VSC_DATA_SIZE 36
Manasi Navare4c614832018-11-28 12:26:20 -08005262#define VIDEO_DIP_PPS_DATA_SIZE 132
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005263#define VIDEO_DIP_CTL _MMIO(0x61170)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03005264/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02005265#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02005266#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03005267#define VIDEO_DIP_PORT_MASK (3 << 29)
Ville Syrjälä5cb3c1a2019-02-25 19:40:58 +02005268#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
David Härdeman3c17fe42010-09-24 21:44:32 +02005269#define VIDEO_DIP_ENABLE_AVI (1 << 21)
5270#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Ville Syrjälä5cb3c1a2019-02-25 19:40:58 +02005271#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
David Härdeman3c17fe42010-09-24 21:44:32 +02005272#define VIDEO_DIP_ENABLE_SPD (8 << 21)
5273#define VIDEO_DIP_SELECT_AVI (0 << 19)
5274#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
Ville Syrjälä5cb3c1a2019-02-25 19:40:58 +02005275#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02005276#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07005277#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02005278#define VIDEO_DIP_FREQ_ONCE (0 << 16)
5279#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
5280#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03005281#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03005282/* HSW and later: */
Ville Syrjälä44b42eb2019-05-17 21:52:25 +05305283#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
Dhinakaran Pandiyana670be32018-10-05 11:56:43 -07005284#define PSR_VSC_BIT_7_SET (1 << 27)
5285#define VSC_SELECT_MASK (0x3 << 25)
5286#define VSC_SELECT_SHIFT 25
5287#define VSC_DIP_HW_HEA_DATA (0 << 25)
5288#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
5289#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
5290#define VSC_DIP_SW_HEA_DATA (3 << 25)
5291#define VDIP_ENABLE_PPS (1 << 24)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03005292#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
5293#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03005294#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03005295#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
5296#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03005297#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02005298
Jesse Barnes585fb112008-07-29 11:54:06 -07005299/* Panel power sequencing */
Imre Deak44cb7342016-08-10 14:07:29 +03005300#define PPS_BASE 0x61200
5301#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
5302#define PCH_PPS_BASE 0xC7200
5303
5304#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
5305 PPS_BASE + (reg) + \
5306 (pps_idx) * 0x100)
5307
5308#define _PP_STATUS 0x61200
5309#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
Jani Nikula09b434d2019-03-15 15:56:18 +02005310#define PP_ON REG_BIT(31)
Jesse Barnes585fb112008-07-29 11:54:06 -07005311/*
5312 * Indicates that all dependencies of the panel are on:
5313 *
5314 * - PLL enabled
5315 * - pipe enabled
5316 * - LVDS/DVOB/DVOC on
5317 */
Jani Nikula09b434d2019-03-15 15:56:18 +02005318#define PP_READY REG_BIT(30)
5319#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
Jani Nikulabaa09e72019-03-15 15:56:20 +02005320#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5321#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
5322#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
Jani Nikula09b434d2019-03-15 15:56:18 +02005323#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
5324#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
Jani Nikulabaa09e72019-03-15 15:56:20 +02005325#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5326#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5327#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5328#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5329#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5330#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5331#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5332#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5333#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
Imre Deak44cb7342016-08-10 14:07:29 +03005334
5335#define _PP_CONTROL 0x61204
5336#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
Jani Nikula09b434d2019-03-15 15:56:18 +02005337#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
Jani Nikulabaa09e72019-03-15 15:56:20 +02005338#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
Jani Nikula09b434d2019-03-15 15:56:18 +02005339#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
Jani Nikula09b434d2019-03-15 15:56:18 +02005340#define EDP_FORCE_VDD REG_BIT(3)
5341#define EDP_BLC_ENABLE REG_BIT(2)
5342#define PANEL_POWER_RESET REG_BIT(1)
5343#define PANEL_POWER_ON REG_BIT(0)
Imre Deak44cb7342016-08-10 14:07:29 +03005344
5345#define _PP_ON_DELAYS 0x61208
5346#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
Jani Nikula09b434d2019-03-15 15:56:18 +02005347#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
Jani Nikulabaa09e72019-03-15 15:56:20 +02005348#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5349#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
5350#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
5351#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
5352#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
Jani Nikula09b434d2019-03-15 15:56:18 +02005353#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
Jani Nikula09b434d2019-03-15 15:56:18 +02005354#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
Imre Deak44cb7342016-08-10 14:07:29 +03005355
5356#define _PP_OFF_DELAYS 0x6120C
5357#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
Jani Nikula09b434d2019-03-15 15:56:18 +02005358#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
Jani Nikula09b434d2019-03-15 15:56:18 +02005359#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
Imre Deak44cb7342016-08-10 14:07:29 +03005360
5361#define _PP_DIVISOR 0x61210
5362#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
Jani Nikula09b434d2019-03-15 15:56:18 +02005363#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
Jani Nikula09b434d2019-03-15 15:56:18 +02005364#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07005365
5366/* Panel fitting */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005367#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07005368#define PFIT_ENABLE (1 << 31)
5369#define PFIT_PIPE_MASK (3 << 29)
5370#define PFIT_PIPE_SHIFT 29
Ville Syrjälä9877db72020-02-12 18:17:31 +02005371#define PFIT_PIPE(pipe) ((pipe) << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07005372#define VERT_INTERP_DISABLE (0 << 10)
5373#define VERT_INTERP_BILINEAR (1 << 10)
5374#define VERT_INTERP_MASK (3 << 10)
5375#define VERT_AUTO_SCALE (1 << 9)
5376#define HORIZ_INTERP_DISABLE (0 << 6)
5377#define HORIZ_INTERP_BILINEAR (1 << 6)
5378#define HORIZ_INTERP_MASK (3 << 6)
5379#define HORIZ_AUTO_SCALE (1 << 5)
5380#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08005381#define PFIT_FILTER_FUZZY (0 << 24)
5382#define PFIT_SCALING_AUTO (0 << 26)
5383#define PFIT_SCALING_PROGRAMMED (1 << 26)
5384#define PFIT_SCALING_PILLAR (2 << 26)
5385#define PFIT_SCALING_LETTER (3 << 26)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005386#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08005387/* Pre-965 */
5388#define PFIT_VERT_SCALE_SHIFT 20
5389#define PFIT_VERT_SCALE_MASK 0xfff00000
5390#define PFIT_HORIZ_SCALE_SHIFT 4
5391#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
5392/* 965+ */
5393#define PFIT_VERT_SCALE_SHIFT_965 16
5394#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
5395#define PFIT_HORIZ_SCALE_SHIFT_965 0
5396#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
5397
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005398#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07005399
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005400#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5401#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005402#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
5403 _VLV_BLC_PWM_CTL2_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02005404
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005405#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5406#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005407#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
5408 _VLV_BLC_PWM_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02005409
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005410#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5411#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005412#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
5413 _VLV_BLC_HIST_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02005414
Jesse Barnes585fb112008-07-29 11:54:06 -07005415/* Backlight control */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005416#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02005417#define BLM_PWM_ENABLE (1 << 31)
5418#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
5419#define BLM_PIPE_SELECT (1 << 29)
5420#define BLM_PIPE_SELECT_IVB (3 << 29)
5421#define BLM_PIPE_A (0 << 29)
5422#define BLM_PIPE_B (1 << 29)
5423#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03005424#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
5425#define BLM_TRANSCODER_B BLM_PIPE_B
5426#define BLM_TRANSCODER_C BLM_PIPE_C
5427#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02005428#define BLM_PIPE(pipe) ((pipe) << 29)
5429#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
5430#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
5431#define BLM_PHASE_IN_ENABLE (1 << 25)
5432#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
5433#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
5434#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
5435#define BLM_PHASE_IN_COUNT_SHIFT (8)
5436#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
5437#define BLM_PHASE_IN_INCR_SHIFT (0)
5438#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005439#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01005440/*
5441 * This is the most significant 15 bits of the number of backlight cycles in a
5442 * complete cycle of the modulated backlight control.
5443 *
5444 * The actual value is this field multiplied by two.
5445 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02005446#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
5447#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
5448#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07005449/*
5450 * This is the number of cycles out of the backlight modulation cycle for which
5451 * the backlight is on.
5452 *
5453 * This field must be no greater than the number of cycles in the complete
5454 * backlight modulation cycle.
5455 */
5456#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
5457#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02005458#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
5459#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07005460
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02005461#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
Jani Nikula2059ac32015-06-26 14:18:56 +03005462#define BLM_HISTOGRAM_ENABLE (1 << 31)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07005463
Daniel Vetter7cf41602012-06-05 10:07:09 +02005464/* New registers for PCH-split platforms. Safe where new bits show up, the
5465 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005466#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
5467#define BLC_PWM_CPU_CTL _MMIO(0x48254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02005468
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005469#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005470
Daniel Vetter7cf41602012-06-05 10:07:09 +02005471/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5472 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005473#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
Daniel Vetter4b4147c2012-07-11 00:31:06 +02005474#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02005475#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
5476#define BLM_PCH_POLARITY (1 << 29)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005477#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02005478
Vandita Kulkarni64ad5322019-11-11 16:40:21 +05305479#define UTIL_PIN_CTL _MMIO(0x48400)
5480#define UTIL_PIN_ENABLE (1 << 31)
5481#define UTIL_PIN_PIPE_MASK (3 << 29)
5482#define UTIL_PIN_PIPE(x) ((x) << 29)
5483#define UTIL_PIN_MODE_MASK (0xf << 24)
5484#define UTIL_PIN_MODE_DATA (0 << 24)
5485#define UTIL_PIN_MODE_PWM (1 << 24)
5486#define UTIL_PIN_MODE_VBLANK (4 << 24)
5487#define UTIL_PIN_MODE_VSYNC (5 << 24)
5488#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
5489#define UTIL_PIN_OUTPUT_DATA (1 << 23)
5490#define UTIL_PIN_POLARITY (1 << 22)
5491#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
5492#define UTIL_PIN_INPUT_DATA (1 << 16)
Sunil Kamath022e4e52015-09-30 22:34:57 +05305493
Vandana Kannan0fb890c2015-05-05 14:51:56 +05305494/* BXT backlight register definition. */
Sunil Kamath022e4e52015-09-30 22:34:57 +05305495#define _BXT_BLC_PWM_CTL1 0xC8250
Vandana Kannan0fb890c2015-05-05 14:51:56 +05305496#define BXT_BLC_PWM_ENABLE (1 << 31)
5497#define BXT_BLC_PWM_POLARITY (1 << 29)
Sunil Kamath022e4e52015-09-30 22:34:57 +05305498#define _BXT_BLC_PWM_FREQ1 0xC8254
5499#define _BXT_BLC_PWM_DUTY1 0xC8258
Vandana Kannan0fb890c2015-05-05 14:51:56 +05305500
Sunil Kamath022e4e52015-09-30 22:34:57 +05305501#define _BXT_BLC_PWM_CTL2 0xC8350
5502#define _BXT_BLC_PWM_FREQ2 0xC8354
5503#define _BXT_BLC_PWM_DUTY2 0xC8358
Vandana Kannan0fb890c2015-05-05 14:51:56 +05305504
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005505#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05305506 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005507#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05305508 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005509#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05305510 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
Vandana Kannan0fb890c2015-05-05 14:51:56 +05305511
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005512#define PCH_GTC_CTL _MMIO(0xe7000)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005513#define PCH_GTC_ENABLE (1 << 31)
5514
Jesse Barnes585fb112008-07-29 11:54:06 -07005515/* TV port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005516#define TV_CTL _MMIO(0x68000)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005517/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07005518# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005519/* Sources the TV encoder input from pipe B instead of A. */
Ville Syrjälä4add0f62018-05-14 20:24:22 +03005520# define TV_ENC_PIPE_SEL_SHIFT 30
5521# define TV_ENC_PIPE_SEL_MASK (1 << 30)
5522# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005523/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005524# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005525/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005526# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005527/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005528# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005529/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005530# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
5531# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005532/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005533# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005534/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07005535# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005536/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07005537# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005538/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07005539# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005540/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07005541# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjäläe3bb3552018-11-12 18:59:58 +02005542# define TV_OVERSAMPLE_MASK (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005543/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07005544# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005545/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005546# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005547/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07005548# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005549/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07005550# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005551/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005552 * Enables a fix for the 915GM only.
5553 *
5554 * Not sure what it does.
5555 */
5556# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005557/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08005558# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07005559# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005560/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07005561# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005562/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07005563# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005564/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005565# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005566/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07005567# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005568/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07005569# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005570/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07005571# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005572/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07005573# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005574/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07005575# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005576/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07005577# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005578/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005579 * This test mode forces the DACs to 50% of full output.
5580 *
5581 * This is used for load detection in combination with TVDAC_SENSE_MASK
5582 */
5583# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
5584# define TV_TEST_MODE_MASK (7 << 0)
5585
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005586#define TV_DAC _MMIO(0x68004)
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01005587# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03005588/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005589 * Reports that DAC state change logic has reported change (RO).
5590 *
5591 * This gets cleared when TV_DAC_STATE_EN is cleared
5592*/
5593# define TVDAC_STATE_CHG (1 << 31)
5594# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005595/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07005596# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005597/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07005598# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005599/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07005600# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005601/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005602 * Enables DAC state detection logic, for load-based TV detection.
5603 *
5604 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5605 * to off, for load detection to work.
5606 */
5607# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005608/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07005609# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005610/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07005611# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005612/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07005613# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005614/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07005615# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005616/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07005617# define ENC_TVDAC_SLEW_FAST (1 << 6)
5618# define DAC_A_1_3_V (0 << 4)
5619# define DAC_A_1_1_V (1 << 4)
5620# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08005621# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07005622# define DAC_B_1_3_V (0 << 2)
5623# define DAC_B_1_1_V (1 << 2)
5624# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08005625# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07005626# define DAC_C_1_3_V (0 << 0)
5627# define DAC_C_1_1_V (1 << 0)
5628# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08005629# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07005630
Ville Syrjälä646b4262014-04-25 20:14:30 +03005631/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005632 * CSC coefficients are stored in a floating point format with 9 bits of
5633 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5634 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5635 * -1 (0x3) being the only legal negative value.
5636 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005637#define TV_CSC_Y _MMIO(0x68010)
Jesse Barnes585fb112008-07-29 11:54:06 -07005638# define TV_RY_MASK 0x07ff0000
5639# define TV_RY_SHIFT 16
5640# define TV_GY_MASK 0x00000fff
5641# define TV_GY_SHIFT 0
5642
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005643#define TV_CSC_Y2 _MMIO(0x68014)
Jesse Barnes585fb112008-07-29 11:54:06 -07005644# define TV_BY_MASK 0x07ff0000
5645# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005646/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005647 * Y attenuation for component video.
5648 *
5649 * Stored in 1.9 fixed point.
5650 */
5651# define TV_AY_MASK 0x000003ff
5652# define TV_AY_SHIFT 0
5653
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005654#define TV_CSC_U _MMIO(0x68018)
Jesse Barnes585fb112008-07-29 11:54:06 -07005655# define TV_RU_MASK 0x07ff0000
5656# define TV_RU_SHIFT 16
5657# define TV_GU_MASK 0x000007ff
5658# define TV_GU_SHIFT 0
5659
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005660#define TV_CSC_U2 _MMIO(0x6801c)
Jesse Barnes585fb112008-07-29 11:54:06 -07005661# define TV_BU_MASK 0x07ff0000
5662# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005663/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005664 * U attenuation for component video.
5665 *
5666 * Stored in 1.9 fixed point.
5667 */
5668# define TV_AU_MASK 0x000003ff
5669# define TV_AU_SHIFT 0
5670
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005671#define TV_CSC_V _MMIO(0x68020)
Jesse Barnes585fb112008-07-29 11:54:06 -07005672# define TV_RV_MASK 0x0fff0000
5673# define TV_RV_SHIFT 16
5674# define TV_GV_MASK 0x000007ff
5675# define TV_GV_SHIFT 0
5676
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005677#define TV_CSC_V2 _MMIO(0x68024)
Jesse Barnes585fb112008-07-29 11:54:06 -07005678# define TV_BV_MASK 0x07ff0000
5679# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005680/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005681 * V attenuation for component video.
5682 *
5683 * Stored in 1.9 fixed point.
5684 */
5685# define TV_AV_MASK 0x000007ff
5686# define TV_AV_SHIFT 0
5687
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005688#define TV_CLR_KNOBS _MMIO(0x68028)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005689/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07005690# define TV_BRIGHTNESS_MASK 0xff000000
5691# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03005692/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07005693# define TV_CONTRAST_MASK 0x00ff0000
5694# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005695/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07005696# define TV_SATURATION_MASK 0x0000ff00
5697# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03005698/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07005699# define TV_HUE_MASK 0x000000ff
5700# define TV_HUE_SHIFT 0
5701
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005702#define TV_CLR_LEVEL _MMIO(0x6802c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005703/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07005704# define TV_BLACK_LEVEL_MASK 0x01ff0000
5705# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005706/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07005707# define TV_BLANK_LEVEL_MASK 0x000001ff
5708# define TV_BLANK_LEVEL_SHIFT 0
5709
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005710#define TV_H_CTL_1 _MMIO(0x68030)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005711/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005712# define TV_HSYNC_END_MASK 0x1fff0000
5713# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005714/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07005715# define TV_HTOTAL_MASK 0x00001fff
5716# define TV_HTOTAL_SHIFT 0
5717
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005718#define TV_H_CTL_2 _MMIO(0x68034)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005719/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005720# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005721/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005722# define TV_HBURST_START_SHIFT 16
5723# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03005724/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07005725# define TV_HBURST_LEN_SHIFT 0
5726# define TV_HBURST_LEN_MASK 0x0001fff
5727
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005728#define TV_H_CTL_3 _MMIO(0x68038)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005729/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07005730# define TV_HBLANK_END_SHIFT 16
5731# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03005732/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07005733# define TV_HBLANK_START_SHIFT 0
5734# define TV_HBLANK_START_MASK 0x0001fff
5735
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005736#define TV_V_CTL_1 _MMIO(0x6803c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005737/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07005738# define TV_NBR_END_SHIFT 16
5739# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03005740/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07005741# define TV_VI_END_F1_SHIFT 8
5742# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03005743/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07005744# define TV_VI_END_F2_SHIFT 0
5745# define TV_VI_END_F2_MASK 0x0000003f
5746
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005747#define TV_V_CTL_2 _MMIO(0x68040)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005748/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07005749# define TV_VSYNC_LEN_MASK 0x07ff0000
5750# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005751/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07005752 * number of half lines.
5753 */
5754# define TV_VSYNC_START_F1_MASK 0x00007f00
5755# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03005756/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005757 * Offset of the start of vsync in field 2, measured in one less than the
5758 * number of half lines.
5759 */
5760# define TV_VSYNC_START_F2_MASK 0x0000007f
5761# define TV_VSYNC_START_F2_SHIFT 0
5762
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005763#define TV_V_CTL_3 _MMIO(0x68044)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005764/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07005765# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005766/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07005767# define TV_VEQ_LEN_MASK 0x007f0000
5768# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005769/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07005770 * the number of half lines.
5771 */
5772# define TV_VEQ_START_F1_MASK 0x0007f00
5773# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03005774/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005775 * Offset of the start of equalization in field 2, measured in one less than
5776 * the number of half lines.
5777 */
5778# define TV_VEQ_START_F2_MASK 0x000007f
5779# define TV_VEQ_START_F2_SHIFT 0
5780
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005781#define TV_V_CTL_4 _MMIO(0x68048)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005782/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005783 * Offset to start of vertical colorburst, measured in one less than the
5784 * number of lines from vertical start.
5785 */
5786# define TV_VBURST_START_F1_MASK 0x003f0000
5787# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005788/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005789 * Offset to the end of vertical colorburst, measured in one less than the
5790 * number of lines from the start of NBR.
5791 */
5792# define TV_VBURST_END_F1_MASK 0x000000ff
5793# define TV_VBURST_END_F1_SHIFT 0
5794
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005795#define TV_V_CTL_5 _MMIO(0x6804c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005796/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005797 * Offset to start of vertical colorburst, measured in one less than the
5798 * number of lines from vertical start.
5799 */
5800# define TV_VBURST_START_F2_MASK 0x003f0000
5801# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005802/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005803 * Offset to the end of vertical colorburst, measured in one less than the
5804 * number of lines from the start of NBR.
5805 */
5806# define TV_VBURST_END_F2_MASK 0x000000ff
5807# define TV_VBURST_END_F2_SHIFT 0
5808
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005809#define TV_V_CTL_6 _MMIO(0x68050)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005810/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005811 * Offset to start of vertical colorburst, measured in one less than the
5812 * number of lines from vertical start.
5813 */
5814# define TV_VBURST_START_F3_MASK 0x003f0000
5815# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005816/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005817 * Offset to the end of vertical colorburst, measured in one less than the
5818 * number of lines from the start of NBR.
5819 */
5820# define TV_VBURST_END_F3_MASK 0x000000ff
5821# define TV_VBURST_END_F3_SHIFT 0
5822
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005823#define TV_V_CTL_7 _MMIO(0x68054)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005824/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005825 * Offset to start of vertical colorburst, measured in one less than the
5826 * number of lines from vertical start.
5827 */
5828# define TV_VBURST_START_F4_MASK 0x003f0000
5829# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005830/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005831 * Offset to the end of vertical colorburst, measured in one less than the
5832 * number of lines from the start of NBR.
5833 */
5834# define TV_VBURST_END_F4_MASK 0x000000ff
5835# define TV_VBURST_END_F4_SHIFT 0
5836
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005837#define TV_SC_CTL_1 _MMIO(0x68060)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005838/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005839# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005840/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005841# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005842/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005843# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005844/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005845# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005846/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005847# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005848/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005849# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005850/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07005851# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005852/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07005853# define TV_BURST_LEVEL_MASK 0x00ff0000
5854# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005855/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005856# define TV_SCDDA1_INC_MASK 0x00000fff
5857# define TV_SCDDA1_INC_SHIFT 0
5858
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005859#define TV_SC_CTL_2 _MMIO(0x68064)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005860/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005861# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5862# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005863/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005864# define TV_SCDDA2_INC_MASK 0x00007fff
5865# define TV_SCDDA2_INC_SHIFT 0
5866
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005867#define TV_SC_CTL_3 _MMIO(0x68068)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005868/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005869# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5870# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005871/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005872# define TV_SCDDA3_INC_MASK 0x00007fff
5873# define TV_SCDDA3_INC_SHIFT 0
5874
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005875#define TV_WIN_POS _MMIO(0x68070)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005876/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07005877# define TV_XPOS_MASK 0x1fff0000
5878# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005879/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005880# define TV_YPOS_MASK 0x00000fff
5881# define TV_YPOS_SHIFT 0
5882
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005883#define TV_WIN_SIZE _MMIO(0x68074)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005884/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07005885# define TV_XSIZE_MASK 0x1fff0000
5886# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005887/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005888 * Vertical size of the display window, measured in pixels.
5889 *
5890 * Must be even for interlaced modes.
5891 */
5892# define TV_YSIZE_MASK 0x00000fff
5893# define TV_YSIZE_SHIFT 0
5894
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005895#define TV_FILTER_CTL_1 _MMIO(0x68080)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005896/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005897 * Enables automatic scaling calculation.
5898 *
5899 * If set, the rest of the registers are ignored, and the calculated values can
5900 * be read back from the register.
5901 */
5902# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005903/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005904 * Disables the vertical filter.
5905 *
5906 * This is required on modes more than 1024 pixels wide */
5907# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005908/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07005909# define TV_VADAPT (1 << 28)
5910# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005911/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005912# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005913/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005914# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005915/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005916# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005917/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005918 * Sets the horizontal scaling factor.
5919 *
5920 * This should be the fractional part of the horizontal scaling factor divided
5921 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5922 *
5923 * (src width - 1) / ((oversample * dest width) - 1)
5924 */
5925# define TV_HSCALE_FRAC_MASK 0x00003fff
5926# define TV_HSCALE_FRAC_SHIFT 0
5927
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005928#define TV_FILTER_CTL_2 _MMIO(0x68084)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005929/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005930 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5931 *
5932 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5933 */
5934# define TV_VSCALE_INT_MASK 0x00038000
5935# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03005936/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005937 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5938 *
5939 * \sa TV_VSCALE_INT_MASK
5940 */
5941# define TV_VSCALE_FRAC_MASK 0x00007fff
5942# define TV_VSCALE_FRAC_SHIFT 0
5943
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005944#define TV_FILTER_CTL_3 _MMIO(0x68088)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005945/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005946 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5947 *
5948 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5949 *
5950 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5951 */
5952# define TV_VSCALE_IP_INT_MASK 0x00038000
5953# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03005954/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005955 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5956 *
5957 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5958 *
5959 * \sa TV_VSCALE_IP_INT_MASK
5960 */
5961# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5962# define TV_VSCALE_IP_FRAC_SHIFT 0
5963
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005964#define TV_CC_CONTROL _MMIO(0x68090)
Jesse Barnes585fb112008-07-29 11:54:06 -07005965# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005966/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005967 * Specifies which field to send the CC data in.
5968 *
5969 * CC data is usually sent in field 0.
5970 */
5971# define TV_CC_FID_MASK (1 << 27)
5972# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03005973/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005974# define TV_CC_HOFF_MASK 0x03ff0000
5975# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005976/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07005977# define TV_CC_LINE_MASK 0x0000003f
5978# define TV_CC_LINE_SHIFT 0
5979
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005980#define TV_CC_DATA _MMIO(0x68094)
Jesse Barnes585fb112008-07-29 11:54:06 -07005981# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005982/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005983# define TV_CC_DATA_2_MASK 0x007f0000
5984# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005985/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005986# define TV_CC_DATA_1_MASK 0x0000007f
5987# define TV_CC_DATA_1_SHIFT 0
5988
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005989#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5990#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5991#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5992#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
Jesse Barnes585fb112008-07-29 11:54:06 -07005993
Keith Packard040d87f2009-05-30 20:42:33 -07005994/* Display Port */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005995#define DP_A _MMIO(0x64000) /* eDP */
5996#define DP_B _MMIO(0x64100)
5997#define DP_C _MMIO(0x64200)
5998#define DP_D _MMIO(0x64300)
Keith Packard040d87f2009-05-30 20:42:33 -07005999
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006000#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
6001#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
6002#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
Ville Syrjäläe66eb812015-09-18 20:03:34 +03006003
Keith Packard040d87f2009-05-30 20:42:33 -07006004#define DP_PORT_EN (1 << 31)
Ville Syrjälä59b74c42018-05-18 18:29:28 +03006005#define DP_PIPE_SEL_SHIFT 30
6006#define DP_PIPE_SEL_MASK (1 << 30)
6007#define DP_PIPE_SEL(pipe) ((pipe) << 30)
6008#define DP_PIPE_SEL_SHIFT_IVB 29
6009#define DP_PIPE_SEL_MASK_IVB (3 << 29)
6010#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
6011#define DP_PIPE_SEL_SHIFT_CHV 16
6012#define DP_PIPE_SEL_MASK_CHV (3 << 16)
6013#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08006014
Keith Packard040d87f2009-05-30 20:42:33 -07006015/* Link training mode - select a suitable mode for each stage */
6016#define DP_LINK_TRAIN_PAT_1 (0 << 28)
6017#define DP_LINK_TRAIN_PAT_2 (1 << 28)
6018#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
6019#define DP_LINK_TRAIN_OFF (3 << 28)
6020#define DP_LINK_TRAIN_MASK (3 << 28)
6021#define DP_LINK_TRAIN_SHIFT 28
6022
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006023/* CPT Link training mode */
6024#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
6025#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
6026#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
6027#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
6028#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
6029#define DP_LINK_TRAIN_SHIFT_CPT 8
6030
Keith Packard040d87f2009-05-30 20:42:33 -07006031/* Signal voltages. These are mostly controlled by the other end */
6032#define DP_VOLTAGE_0_4 (0 << 25)
6033#define DP_VOLTAGE_0_6 (1 << 25)
6034#define DP_VOLTAGE_0_8 (2 << 25)
6035#define DP_VOLTAGE_1_2 (3 << 25)
6036#define DP_VOLTAGE_MASK (7 << 25)
6037#define DP_VOLTAGE_SHIFT 25
6038
6039/* Signal pre-emphasis levels, like voltages, the other end tells us what
6040 * they want
6041 */
6042#define DP_PRE_EMPHASIS_0 (0 << 22)
6043#define DP_PRE_EMPHASIS_3_5 (1 << 22)
6044#define DP_PRE_EMPHASIS_6 (2 << 22)
6045#define DP_PRE_EMPHASIS_9_5 (3 << 22)
6046#define DP_PRE_EMPHASIS_MASK (7 << 22)
6047#define DP_PRE_EMPHASIS_SHIFT 22
6048
6049/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02006050#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07006051#define DP_PORT_WIDTH_MASK (7 << 19)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03006052#define DP_PORT_WIDTH_SHIFT 19
Keith Packard040d87f2009-05-30 20:42:33 -07006053
6054/* Mystic DPCD version 1.1 special mode */
6055#define DP_ENHANCED_FRAMING (1 << 18)
6056
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006057/* eDP */
6058#define DP_PLL_FREQ_270MHZ (0 << 16)
Ville Syrjäläb377e0d2015-10-29 21:25:59 +02006059#define DP_PLL_FREQ_162MHZ (1 << 16)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006060#define DP_PLL_FREQ_MASK (3 << 16)
6061
Ville Syrjälä646b4262014-04-25 20:14:30 +03006062/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07006063#define DP_PORT_REVERSAL (1 << 15)
6064
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006065/* eDP */
6066#define DP_PLL_ENABLE (1 << 14)
6067
Ville Syrjälä646b4262014-04-25 20:14:30 +03006068/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07006069#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
6070
6071#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006072#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07006073
Ville Syrjälä646b4262014-04-25 20:14:30 +03006074/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07006075#define DP_COLOR_RANGE_16_235 (1 << 8)
6076
Ville Syrjälä646b4262014-04-25 20:14:30 +03006077/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07006078#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
6079
Ville Syrjälä646b4262014-04-25 20:14:30 +03006080/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07006081#define DP_SYNC_VS_HIGH (1 << 4)
6082#define DP_SYNC_HS_HIGH (1 << 3)
6083
Ville Syrjälä646b4262014-04-25 20:14:30 +03006084/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07006085#define DP_DETECTED (1 << 2)
6086
Ville Syrjälä646b4262014-04-25 20:14:30 +03006087/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07006088 * signal sink for DDC etc. Max packet size supported
6089 * is 20 bytes in each direction, hence the 5 fixed
6090 * data registers
6091 */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006092#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
6093#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006094
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006095#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
6096#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
Rodrigo Vivia324fca2018-01-29 15:22:15 -08006097
Ville Syrjäläbdabdb62018-02-22 20:10:30 +02006098#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
6099#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Keith Packard040d87f2009-05-30 20:42:33 -07006100
6101#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
6102#define DP_AUX_CH_CTL_DONE (1 << 30)
6103#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
6104#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
6105#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
6106#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
6107#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
James Ausmus6fa228b2017-10-12 14:30:36 -07006108#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
Keith Packard040d87f2009-05-30 20:42:33 -07006109#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
6110#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
6111#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
6112#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
6113#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
6114#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
6115#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
6116#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
6117#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
6118#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
6119#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
6120#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
6121#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
Sonika Jindale3d99842015-01-22 14:30:54 +05306122#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
6123#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
6124#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
Anusha Srivatsa6f211ed2018-07-26 16:35:15 -07006125#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
Ville Syrjälä395b2912015-09-18 20:03:40 +03006126#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
Sonika Jindale3d99842015-01-22 14:30:54 +05306127#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00006128#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
Keith Packard040d87f2009-05-30 20:42:33 -07006129
6130/*
6131 * Computing GMCH M and N values for the Display Port link
6132 *
6133 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
6134 *
6135 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
6136 *
6137 * The GMCH value is used internally
6138 *
6139 * bytes_per_pixel is the number of bytes coming out of the plane,
6140 * which is after the LUTs, so we want the bytes for our color format.
6141 * For our current usage, this is always 3, one byte for R, G and B.
6142 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02006143#define _PIPEA_DATA_M_G4X 0x70050
6144#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07006145
6146/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006147#define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02006148#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006149#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07006150
Ville Syrjäläa65851a2013-04-23 15:03:34 +03006151#define DATA_LINK_M_N_MASK (0xffffff)
6152#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07006153
Daniel Vettere3b95f12013-05-03 11:49:49 +02006154#define _PIPEA_DATA_N_G4X 0x70054
6155#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07006156#define PIPE_GMCH_DATA_N_MASK (0xffffff)
6157
6158/*
6159 * Computing Link M and N values for the Display Port link
6160 *
6161 * Link M / N = pixel_clock / ls_clk
6162 *
6163 * (the DP spec calls pixel_clock the 'strm_clk')
6164 *
6165 * The Link value is transmitted in the Main Stream
6166 * Attributes and VB-ID.
6167 */
6168
Daniel Vettere3b95f12013-05-03 11:49:49 +02006169#define _PIPEA_LINK_M_G4X 0x70060
6170#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07006171#define PIPEA_DP_LINK_M_MASK (0xffffff)
6172
Daniel Vettere3b95f12013-05-03 11:49:49 +02006173#define _PIPEA_LINK_N_G4X 0x70064
6174#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07006175#define PIPEA_DP_LINK_N_MASK (0xffffff)
6176
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006177#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
6178#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
6179#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
6180#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006181
Jesse Barnes585fb112008-07-29 11:54:06 -07006182/* Display & cursor control */
6183
6184/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006185#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03006186#define DSL_LINEMASK_GEN2 0x00000fff
6187#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006188#define _PIPEACONF 0x70008
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006189#define PIPECONF_ENABLE (1 << 31)
Chris Wilson5eddb702010-09-11 13:48:45 +01006190#define PIPECONF_DISABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006191#define PIPECONF_DOUBLE_WIDE (1 << 30)
6192#define I965_PIPECONF_ACTIVE (1 << 30)
6193#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
Ville Syrjäläcc7a4cf2019-10-24 15:21:38 +03006194#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
6195#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
Chris Wilson5eddb702010-09-11 13:48:45 +01006196#define PIPECONF_SINGLE_WIDE 0
6197#define PIPECONF_PIPE_UNLOCKED 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006198#define PIPECONF_PIPE_LOCKED (1 << 25)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006199#define PIPECONF_FORCE_BORDER (1 << 25)
Ville Syrjälä9d5441d2019-02-07 22:21:40 +02006200#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
6201#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
6202#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
6203#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
6204#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
6205#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
6206#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
6207#define PIPECONF_GAMMA_MODE_SHIFT 24
Christian Schmidt59df7b12011-12-19 20:03:33 +01006208#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006209#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01006210/* Note that pre-gen3 does not support interlaced display directly. Panel
6211 * fitting must be disabled on pre-ilk for interlaced. */
6212#define PIPECONF_PROGRESSIVE (0 << 21)
6213#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
6214#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
6215#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
6216#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
6217/* Ironlake and later have a complete new set of values for interlaced. PFIT
6218 * means panel fitter required, PF means progressive fetch, DBL means power
6219 * saving pixel doubling. */
6220#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
6221#define PIPECONF_INTERLACED_ILK (3 << 21)
6222#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
6223#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006224#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05306225#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006226#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05306227#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006228#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Ville Syrjäläd1844602019-07-18 17:50:53 +03006229#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
6230#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
6231#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
6232#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
Ville Syrjäläac0f01c2019-07-18 17:50:50 +03006233#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006234#define PIPECONF_BPC_MASK (0x7 << 5)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006235#define PIPECONF_8BPC (0 << 5)
6236#define PIPECONF_10BPC (1 << 5)
6237#define PIPECONF_6BPC (2 << 5)
6238#define PIPECONF_12BPC (3 << 5)
6239#define PIPECONF_DITHER_EN (1 << 4)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07006240#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006241#define PIPECONF_DITHER_TYPE_SP (0 << 2)
6242#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
6243#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
6244#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006245#define _PIPEASTAT 0x70024
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006246#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
6247#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
6248#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
6249#define PIPE_CRC_DONE_ENABLE (1UL << 28)
6250#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
6251#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
6252#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
6253#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
6254#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
6255#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
6256#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
6257#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
6258#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
6259#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
6260#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
6261#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
6262#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
6263#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
6264#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
6265#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
6266#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
6267#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
6268#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
6269#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
6270#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
6271#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
6272#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
6273#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
6274#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
6275#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
6276#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
6277#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
6278#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
6279#define PIPE_DPST_EVENT_STATUS (1UL << 7)
6280#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
6281#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
6282#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
6283#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
6284#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
6285#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
6286#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
6287#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
6288#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
6289#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
6290#define PIPE_HBLANK_INT_STATUS (1UL << 0)
6291#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07006292
Imre Deak755e9012014-02-10 18:42:47 +02006293#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
6294#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
6295
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03006296#define PIPE_A_OFFSET 0x70000
6297#define PIPE_B_OFFSET 0x71000
6298#define PIPE_C_OFFSET 0x72000
Lucas De Marchif1f1d4f2019-07-11 10:30:55 -07006299#define PIPE_D_OFFSET 0x73000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03006300#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006301/*
6302 * There's actually no pipe EDP. Some pipe registers have
6303 * simply shifted from the pipe to the transcoder, while
6304 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
6305 * to access such registers in transcoder EDP.
6306 */
6307#define PIPE_EDP_OFFSET 0x7f000
6308
Madhav Chauhan372610f2018-10-15 17:28:04 +03006309/* ICL DSI 0 and 1 */
6310#define PIPE_DSI0_OFFSET 0x7b000
6311#define PIPE_DSI1_OFFSET 0x7b800
6312
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006313#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
6314#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
6315#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
6316#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
6317#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01006318
Ville Syrjäläe2625682019-04-01 23:02:29 +03006319#define _PIPEAGCMAX 0x70010
6320#define _PIPEBGCMAX 0x71010
6321#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
6322
Ville Syrjälä0b869522021-05-26 20:36:00 +03006323#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
6324#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
6325#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
6326
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006327#define _PIPE_MISC_A 0x70030
6328#define _PIPE_MISC_B 0x71030
Ville Syrjäläb10d1172019-07-18 17:50:49 +03006329#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
6330#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
Ville Syrjälä09b25812019-04-12 21:30:09 +03006331#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006332#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
Ville Syrjälä041be482020-02-26 18:30:54 +02006333#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
Ankit Nautiyal70418a62021-08-11 10:48:57 +05306334/*
6335 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
6336 * valid values of: 6, 8, 10 BPC.
6337 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
6338 * 6, 8, 10, 12 BPC.
6339 */
6340#define PIPEMISC_BPC_MASK (7 << 5)
6341#define PIPEMISC_8_BPC (0 << 5)
6342#define PIPEMISC_10_BPC (1 << 5)
6343#define PIPEMISC_6_BPC (2 << 5)
6344#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006345#define PIPEMISC_DITHER_ENABLE (1 << 4)
6346#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
6347#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006348#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006349
Anusha Srivatsae2ca7572021-05-18 17:06:24 -07006350#define _PIPE_MISC2_A 0x7002C
6351#define _PIPE_MISC2_B 0x7102C
6352#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
6353#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
6354#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
6355#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
6356
Matt Roperc0550302019-01-30 10:51:20 -08006357/* Skylake+ pipe bottom (background) color */
6358#define _SKL_BOTTOM_COLOR_A 0x70034
6359#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
6360#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
6361#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
6362
Matt Roper8bcc0842021-05-25 17:06:54 -07006363#define _ICL_PIPE_A_STATUS 0x70058
6364#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
6365#define PIPE_STATUS_UNDERRUN REG_BIT(31)
6366#define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
6367#define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
6368#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
6369
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006370#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
Ville Syrjälä7d938bc2021-11-12 21:38:12 +02006371#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
6372#define PIPEB_HLINE_INT_EN REG_BIT(28)
6373#define PIPEB_VBLANK_INT_EN REG_BIT(27)
6374#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
6375#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
6376#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
6377#define PIPE_PSR_INT_EN REG_BIT(22)
6378#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
6379#define PIPEA_HLINE_INT_EN REG_BIT(20)
6380#define PIPEA_VBLANK_INT_EN REG_BIT(19)
6381#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
6382#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
6383#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
6384#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
6385#define PIPEC_HLINE_INT_EN REG_BIT(12)
6386#define PIPEC_VBLANK_INT_EN REG_BIT(11)
6387#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
6388#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
6389#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07006390
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006391#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
Ville Syrjälä7d938bc2021-11-12 21:38:12 +02006392#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
6393#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
6394#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
6395#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
6396#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
6397#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
6398#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
6399#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
6400#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
6401#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
6402#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
6403#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
6404#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
6405#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
6406#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
6407#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
6408#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
6409#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
6410#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
6411#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
6412#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
6413#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
6414#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
6415#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
6416#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
6417#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
6418#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
6419#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07006420
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006421#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
Jesse Barnes585fb112008-07-29 11:54:06 -07006422#define DSPARB_CSTART_MASK (0x7f << 7)
6423#define DSPARB_CSTART_SHIFT 7
6424#define DSPARB_BSTART_MASK (0x7f)
6425#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08006426#define DSPARB_BEND_SHIFT 9 /* on 855 */
6427#define DSPARB_AEND_SHIFT 0
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03006428#define DSPARB_SPRITEA_SHIFT_VLV 0
6429#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
6430#define DSPARB_SPRITEB_SHIFT_VLV 8
6431#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
6432#define DSPARB_SPRITEC_SHIFT_VLV 16
6433#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
6434#define DSPARB_SPRITED_SHIFT_VLV 24
6435#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006436#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03006437#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
6438#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
6439#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
6440#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
6441#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
6442#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
6443#define DSPARB_SPRITED_HI_SHIFT_VLV 12
6444#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
6445#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
6446#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
6447#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
6448#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006449#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03006450#define DSPARB_SPRITEE_SHIFT_VLV 0
6451#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
6452#define DSPARB_SPRITEF_SHIFT_VLV 8
6453#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
Ville Syrjäläb5004722015-03-05 21:19:47 +02006454
Ville Syrjälä0a560672014-06-11 16:51:18 +03006455/* pnv/gen4/g4x/vlv/chv */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006456#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006457#define DSPFW_SR_SHIFT 23
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006458#define DSPFW_SR_MASK (0x1ff << 23)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006459#define DSPFW_CURSORB_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006460#define DSPFW_CURSORB_MASK (0x3f << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006461#define DSPFW_PLANEB_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006462#define DSPFW_PLANEB_MASK (0x7f << 8)
6463#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006464#define DSPFW_PLANEA_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006465#define DSPFW_PLANEA_MASK (0x7f << 0)
6466#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006467#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006468#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006469#define DSPFW_FBC_SR_SHIFT 28
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006470#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006471#define DSPFW_FBC_HPLL_SR_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006472#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006473#define DSPFW_SPRITEB_SHIFT (16)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006474#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
6475#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006476#define DSPFW_CURSORA_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006477#define DSPFW_CURSORA_MASK (0x3f << 8)
Ville Syrjäläf4998962015-03-10 17:02:21 +02006478#define DSPFW_PLANEC_OLD_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006479#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006480#define DSPFW_SPRITEA_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006481#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
6482#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006483#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006484#define DSPFW_HPLL_SR_EN (1 << 31)
6485#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006486#define DSPFW_CURSOR_SR_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006487#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
Zhao Yakuid4294342010-03-22 22:45:36 +08006488#define DSPFW_HPLL_CURSOR_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006489#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006490#define DSPFW_HPLL_SR_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006491#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006492
6493/* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006494#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006495#define DSPFW_SPRITEB_WM1_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006496#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006497#define DSPFW_CURSORA_WM1_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006498#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006499#define DSPFW_SPRITEA_WM1_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006500#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006501#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006502#define DSPFW_PLANEB_WM1_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006503#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006504#define DSPFW_PLANEA_WM1_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006505#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006506#define DSPFW_CURSORB_WM1_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006507#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006508#define DSPFW_CURSOR_SR_WM1_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006509#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006510#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006511#define DSPFW_SR_WM1_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006512#define DSPFW_SR_WM1_MASK (0x1ff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006513#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
6514#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006515#define DSPFW_SPRITED_WM1_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006516#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006517#define DSPFW_SPRITED_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006518#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006519#define DSPFW_SPRITEC_WM1_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006520#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006521#define DSPFW_SPRITEC_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006522#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006523#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006524#define DSPFW_SPRITEF_WM1_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006525#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006526#define DSPFW_SPRITEF_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006527#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006528#define DSPFW_SPRITEE_WM1_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006529#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006530#define DSPFW_SPRITEE_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006531#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006532#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006533#define DSPFW_PLANEC_WM1_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006534#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006535#define DSPFW_PLANEC_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006536#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006537#define DSPFW_CURSORC_WM1_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006538#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006539#define DSPFW_CURSORC_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006540#define DSPFW_CURSORC_MASK (0x3f << 0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006541
6542/* vlv/chv high order bits */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006543#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006544#define DSPFW_SR_HI_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006545#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006546#define DSPFW_SPRITEF_HI_SHIFT 23
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006547#define DSPFW_SPRITEF_HI_MASK (1 << 23)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006548#define DSPFW_SPRITEE_HI_SHIFT 22
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006549#define DSPFW_SPRITEE_HI_MASK (1 << 22)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006550#define DSPFW_PLANEC_HI_SHIFT 21
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006551#define DSPFW_PLANEC_HI_MASK (1 << 21)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006552#define DSPFW_SPRITED_HI_SHIFT 20
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006553#define DSPFW_SPRITED_HI_MASK (1 << 20)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006554#define DSPFW_SPRITEC_HI_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006555#define DSPFW_SPRITEC_HI_MASK (1 << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006556#define DSPFW_PLANEB_HI_SHIFT 12
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006557#define DSPFW_PLANEB_HI_MASK (1 << 12)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006558#define DSPFW_SPRITEB_HI_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006559#define DSPFW_SPRITEB_HI_MASK (1 << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006560#define DSPFW_SPRITEA_HI_SHIFT 4
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006561#define DSPFW_SPRITEA_HI_MASK (1 << 4)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006562#define DSPFW_PLANEA_HI_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006563#define DSPFW_PLANEA_HI_MASK (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006564#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006565#define DSPFW_SR_WM1_HI_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006566#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03006567#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006568#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006569#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006570#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006571#define DSPFW_PLANEC_WM1_HI_SHIFT 21
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006572#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006573#define DSPFW_SPRITED_WM1_HI_SHIFT 20
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006574#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006575#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006576#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006577#define DSPFW_PLANEB_WM1_HI_SHIFT 12
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006578#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006579#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006580#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006581#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006582#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
Ville Syrjälä0a560672014-06-11 16:51:18 +03006583#define DSPFW_PLANEA_WM1_HI_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006584#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08006585
Gajanan Bhat12a3c052012-03-28 13:39:30 -07006586/* drain latency register values*/
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006587#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03006588#define DDL_CURSOR_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006589#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03006590#define DDL_PLANE_SHIFT 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006591#define DDL_PRECISION_HIGH (1 << 7)
6592#define DDL_PRECISION_LOW (0 << 7)
Gajanan Bhat0948c262014-08-07 01:58:24 +05306593#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07006594
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006595#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006596#define CBR_PND_DEADLINE_DISABLE (1 << 31)
6597#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
Ville Syrjäläc6beb132015-03-05 21:19:48 +02006598
Ville Syrjäläc2317752016-03-15 16:39:56 +02006599#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006600#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
Ville Syrjäläc2317752016-03-15 16:39:56 +02006601
Shaohua Li7662c8b2009-06-26 11:23:55 +08006602/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09006603#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08006604#define I915_FIFO_LINE_SIZE 64
6605#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09006606
Jesse Barnesceb04242012-03-28 13:39:22 -07006607#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09006608#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08006609#define I965_FIFO_SIZE 512
6610#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08006611#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07006612#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08006613#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09006614
Jesse Barnesceb04242012-03-28 13:39:22 -07006615#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09006616#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08006617#define I915_MAX_WM 0x3f
6618
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006619#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
6620#define PINEVIEW_FIFO_LINE_SIZE 64
6621#define PINEVIEW_MAX_WM 0x1ff
6622#define PINEVIEW_DFT_WM 0x3f
6623#define PINEVIEW_DFT_HPLLOFF_WM 0
6624#define PINEVIEW_GUARD_WM 10
6625#define PINEVIEW_CURSOR_FIFO 64
6626#define PINEVIEW_CURSOR_MAX_WM 0x3f
6627#define PINEVIEW_CURSOR_DFT_WM 0
6628#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08006629
Jesse Barnesceb04242012-03-28 13:39:22 -07006630#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08006631#define I965_CURSOR_FIFO 64
6632#define I965_CURSOR_MAX_WM 32
6633#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006634
Pradeep Bhatfae12672014-11-04 17:06:39 +00006635/* Watermark register definitions for SKL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006636#define _CUR_WM_A_0 0x70140
6637#define _CUR_WM_B_0 0x71140
Matt Roper7959ffe2021-05-18 17:06:11 -07006638#define _CUR_WM_SAGV_A 0x70158
6639#define _CUR_WM_SAGV_B 0x71158
6640#define _CUR_WM_SAGV_TRANS_A 0x7015C
6641#define _CUR_WM_SAGV_TRANS_B 0x7115C
6642#define _CUR_WM_TRANS_A 0x70168
6643#define _CUR_WM_TRANS_B 0x71168
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006644#define _PLANE_WM_1_A_0 0x70240
6645#define _PLANE_WM_1_B_0 0x71240
6646#define _PLANE_WM_2_A_0 0x70340
6647#define _PLANE_WM_2_B_0 0x71340
Matt Roper7959ffe2021-05-18 17:06:11 -07006648#define _PLANE_WM_SAGV_1_A 0x70258
6649#define _PLANE_WM_SAGV_1_B 0x71258
6650#define _PLANE_WM_SAGV_2_A 0x70358
6651#define _PLANE_WM_SAGV_2_B 0x71358
6652#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
6653#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
6654#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
6655#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
6656#define _PLANE_WM_TRANS_1_A 0x70268
6657#define _PLANE_WM_TRANS_1_B 0x71268
6658#define _PLANE_WM_TRANS_2_A 0x70368
6659#define _PLANE_WM_TRANS_2_B 0x71368
Pradeep Bhatfae12672014-11-04 17:06:39 +00006660#define PLANE_WM_EN (1 << 31)
Ville Syrjälä2ed8e1f2019-02-13 18:54:23 +02006661#define PLANE_WM_IGNORE_LINES (1 << 30)
Matt Roper47d263a2021-05-14 08:36:59 -07006662#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
6663#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00006664
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006665#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006666#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
Matt Roper7959ffe2021-05-18 17:06:11 -07006667#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
6668#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
6669#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006670#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6671#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
Matt Roper7959ffe2021-05-18 17:06:11 -07006672#define _PLANE_WM_BASE(pipe, plane) \
6673 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6674#define PLANE_WM(pipe, plane, level) \
6675 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6676#define _PLANE_WM_SAGV_1(pipe) \
6677 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
6678#define _PLANE_WM_SAGV_2(pipe) \
6679 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
6680#define PLANE_WM_SAGV(pipe, plane) \
6681 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
6682#define _PLANE_WM_SAGV_TRANS_1(pipe) \
6683 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
6684#define _PLANE_WM_SAGV_TRANS_2(pipe) \
6685 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
6686#define PLANE_WM_SAGV_TRANS(pipe, plane) \
6687 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
6688#define _PLANE_WM_TRANS_1(pipe) \
6689 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
6690#define _PLANE_WM_TRANS_2(pipe) \
6691 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
6692#define PLANE_WM_TRANS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006693 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
Pradeep Bhatfae12672014-11-04 17:06:39 +00006694
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006695/* define the Watermark register on Ironlake */
Ville Syrjälä96eaeb3d2018-12-12 23:17:38 +02006696#define _WM0_PIPEA_ILK 0x45100
6697#define _WM0_PIPEB_ILK 0x45104
6698#define _WM0_PIPEC_IVB 0x45200
6699#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
6700 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006701#define WM0_PIPE_PLANE_MASK (0xffff << 16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006702#define WM0_PIPE_PLANE_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006703#define WM0_PIPE_SPRITE_MASK (0xff << 8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006704#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03006705#define WM0_PIPE_CURSOR_MASK (0xff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006706#define WM1_LP_ILK _MMIO(0x45108)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006707#define WM1_LP_SR_EN (1 << 31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006708#define WM1_LP_LATENCY_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006709#define WM1_LP_LATENCY_MASK (0x7f << 24)
6710#define WM1_LP_FBC_MASK (0xf << 20)
Chris Wilson4ed765f2010-09-11 10:46:47 +01006711#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07006712#define WM1_LP_FBC_SHIFT_BDW 19
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006713#define WM1_LP_SR_MASK (0x7ff << 8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006714#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03006715#define WM1_LP_CURSOR_MASK (0xff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006716#define WM2_LP_ILK _MMIO(0x4510c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006717#define WM2_LP_EN (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006718#define WM3_LP_ILK _MMIO(0x45110)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006719#define WM3_LP_EN (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006720#define WM1S_LP_ILK _MMIO(0x45120)
6721#define WM2S_LP_IVB _MMIO(0x45124)
6722#define WM3S_LP_IVB _MMIO(0x45128)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006723#define WM1S_LP_EN (1 << 31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006724
Paulo Zanonicca32e92013-05-31 11:45:06 -03006725#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6726 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6727 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6728
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006729/* Memory latency timer register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006730#define MLTR_ILK _MMIO(0x11222)
Jesse Barnesb79d4992010-12-21 13:10:23 -08006731#define MLTR_WM1_SHIFT 0
6732#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006733/* the unit of memory self-refresh latency time is 0.5us */
6734#define ILK_SRLT_MASK 0x3f
6735
Yuanhan Liu13982612010-12-15 15:42:31 +08006736
6737/* the address where we get all kinds of latency value */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006738#define SSKPD _MMIO(0x5d10)
Yuanhan Liu13982612010-12-15 15:42:31 +08006739#define SSKPD_WM_MASK 0x3f
6740#define SSKPD_WM0_SHIFT 0
6741#define SSKPD_WM1_SHIFT 8
6742#define SSKPD_WM2_SHIFT 16
6743#define SSKPD_WM3_SHIFT 24
6744
Jesse Barnes585fb112008-07-29 11:54:06 -07006745/*
6746 * The two pipe frame counter registers are not synchronized, so
6747 * reading a stable value is somewhat tricky. The following code
6748 * should work:
6749 *
6750 * do {
6751 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6752 * PIPE_FRAME_HIGH_SHIFT;
6753 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6754 * PIPE_FRAME_LOW_SHIFT);
6755 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6756 * PIPE_FRAME_HIGH_SHIFT);
6757 * } while (high1 != high2);
6758 * frame = (high1 << 8) | low1;
6759 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03006760#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07006761#define PIPE_FRAME_HIGH_MASK 0x0000ffff
6762#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03006763#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07006764#define PIPE_FRAME_LOW_MASK 0xff000000
6765#define PIPE_FRAME_LOW_SHIFT 24
6766#define PIPE_PIXEL_MASK 0x00ffffff
6767#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08006768/* GM45+ just has to be different */
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03006769#define _PIPEA_FRMCOUNT_G4X 0x70040
6770#define _PIPEA_FLIPCOUNT_G4X 0x70044
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006771#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6772#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
Jesse Barnes585fb112008-07-29 11:54:06 -07006773
6774/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03006775#define _CURACNTR 0x70080
Jesse Barnes14b603912009-05-20 16:47:08 -04006776/* Old style CUR*CNTR flags (desktop 8xx) */
6777#define CURSOR_ENABLE 0x80000000
6778#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03006779#define CURSOR_STRIDE_SHIFT 28
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006780#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Jesse Barnes14b603912009-05-20 16:47:08 -04006781#define CURSOR_FORMAT_SHIFT 24
6782#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6783#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6784#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6785#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6786#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6787#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6788/* New style CUR*CNTR flags */
Ville Syrjäläb99b9ec2018-01-31 16:37:09 +02006789#define MCURSOR_MODE 0x27
6790#define MCURSOR_MODE_DISABLE 0x00
6791#define MCURSOR_MODE_128_32B_AX 0x02
6792#define MCURSOR_MODE_256_32B_AX 0x03
6793#define MCURSOR_MODE_64_32B_AX 0x07
6794#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6795#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6796#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
Ville Syrjälä0b869522021-05-26 20:36:00 +03006797#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
6798#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
Ville Syrjäläeade6c82018-01-30 22:38:03 +02006799#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6800#define MCURSOR_PIPE_SELECT_SHIFT 28
Ville Syrjäläd509e282017-03-27 21:55:32 +03006801#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07006802#define MCURSOR_GAMMA_ENABLE (1 << 26)
Ville Syrjälä8271b2e2019-02-07 22:21:42 +02006803#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006804#define MCURSOR_ROTATE_180 (1 << 15)
Ville Syrjäläb99b9ec2018-01-31 16:37:09 +02006805#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03006806#define _CURABASE 0x70084
6807#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07006808#define CURSOR_POS_MASK 0x007FF
6809#define CURSOR_POS_SIGN 0x8000
6810#define CURSOR_X_SHIFT 0
6811#define CURSOR_Y_SHIFT 16
Ville Syrjälä024faac2017-03-27 21:55:42 +03006812#define CURSIZE _MMIO(0x700a0) /* 845/865 */
6813#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6814#define CUR_FBC_CTL_EN (1 << 31)
Rodrigo Vivia8ada062018-03-12 14:05:28 -07006815#define _CURASURFLIVE 0x700ac /* g4x+ */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03006816#define _CURBCNTR 0x700c0
6817#define _CURBBASE 0x700c4
6818#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07006819
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006820#define _CURBCNTR_IVB 0x71080
6821#define _CURBBASE_IVB 0x71084
6822#define _CURBPOS_IVB 0x71088
6823
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03006824#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6825#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6826#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
Ville Syrjälä024faac2017-03-27 21:55:42 +03006827#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
Rodrigo Vivia8ada062018-03-12 14:05:28 -07006828#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03006829
6830#define CURSOR_A_OFFSET 0x70080
6831#define CURSOR_B_OFFSET 0x700c0
6832#define CHV_CURSOR_C_OFFSET 0x700e0
6833#define IVB_CURSOR_B_OFFSET 0x71080
6834#define IVB_CURSOR_C_OFFSET 0x72080
Ankit Nautiyal6ea3cee2019-09-24 13:01:52 +05306835#define TGL_CURSOR_D_OFFSET 0x73080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006836
Jesse Barnes585fb112008-07-29 11:54:06 -07006837/* Display A control */
Ville Syrjälä6ede6b062021-01-11 18:37:11 +02006838#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006839#define _DSPACNTR 0x70180
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006840#define DISPLAY_PLANE_ENABLE (1 << 31)
Jesse Barnes585fb112008-07-29 11:54:06 -07006841#define DISPLAY_PLANE_DISABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006842#define DISPPLANE_GAMMA_ENABLE (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07006843#define DISPPLANE_GAMMA_DISABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006844#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6845#define DISPPLANE_YUV422 (0x0 << 26)
6846#define DISPPLANE_8BPP (0x2 << 26)
6847#define DISPPLANE_BGRA555 (0x3 << 26)
6848#define DISPPLANE_BGRX555 (0x4 << 26)
6849#define DISPPLANE_BGRX565 (0x5 << 26)
6850#define DISPPLANE_BGRX888 (0x6 << 26)
6851#define DISPPLANE_BGRA888 (0x7 << 26)
6852#define DISPPLANE_RGBX101010 (0x8 << 26)
6853#define DISPPLANE_RGBA101010 (0x9 << 26)
6854#define DISPPLANE_BGRX101010 (0xa << 26)
Ville Syrjälä73263cb2019-10-31 18:56:47 +02006855#define DISPPLANE_BGRA101010 (0xb << 26)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006856#define DISPPLANE_RGBX161616 (0xc << 26)
6857#define DISPPLANE_RGBX888 (0xe << 26)
6858#define DISPPLANE_RGBA888 (0xf << 26)
6859#define DISPPLANE_STEREO_ENABLE (1 << 25)
Jesse Barnes585fb112008-07-29 11:54:06 -07006860#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä8271b2e2019-02-07 22:21:42 +02006861#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006862#define DISPPLANE_SEL_PIPE_SHIFT 24
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006863#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6864#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6865#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
Jesse Barnes585fb112008-07-29 11:54:06 -07006866#define DISPPLANE_SRC_KEY_DISABLE 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006867#define DISPPLANE_LINE_DOUBLE (1 << 20)
Jesse Barnes585fb112008-07-29 11:54:06 -07006868#define DISPPLANE_NO_LINE_DOUBLE 0
6869#define DISPPLANE_STEREO_POLARITY_FIRST 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006870#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6871#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6872#define DISPPLANE_ROTATE_180 (1 << 15)
6873#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6874#define DISPPLANE_TILED (1 << 10)
Ville Syrjäläcda195f2021-01-11 18:37:08 +02006875#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006876#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006877#define _DSPAADDR 0x70184
6878#define _DSPASTRIDE 0x70188
6879#define _DSPAPOS 0x7018C /* reserved */
6880#define _DSPASIZE 0x70190
6881#define _DSPASURF 0x7019C /* 965+ only */
6882#define _DSPATILEOFF 0x701A4 /* 965+ only */
6883#define _DSPAOFFSET 0x701A4 /* HSW */
6884#define _DSPASURFLIVE 0x701AC
Ville Syrjälä94e15722019-07-03 23:08:21 +03006885#define _DSPAGAMC 0x701E0
Jesse Barnes585fb112008-07-29 11:54:06 -07006886
Ville Syrjälä6ede6b062021-01-11 18:37:11 +02006887#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006888#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6889#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6890#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6891#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6892#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6893#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6894#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6895#define DSPLINOFF(plane) DSPADDR(plane)
6896#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6897#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
Ville Syrjälä94e15722019-07-03 23:08:21 +03006898#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
Chris Wilson5eddb702010-09-11 13:48:45 +01006899
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006900/* CHV pipe B blender and primary plane */
6901#define _CHV_BLEND_A 0x60a00
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006902#define CHV_BLEND_LEGACY (0 << 30)
6903#define CHV_BLEND_ANDROID (1 << 30)
6904#define CHV_BLEND_MPO (2 << 30)
6905#define CHV_BLEND_MASK (3 << 30)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006906#define _CHV_CANVAS_A 0x60a04
6907#define _PRIMPOS_A 0x60a08
6908#define _PRIMSIZE_A 0x60a0c
6909#define _PRIMCNSTALPHA_A 0x60a10
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006910#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006911
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006912#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6913#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6914#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6915#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6916#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006917
Armin Reese446f2542012-03-30 16:20:16 -07006918/* Display/Sprite base address macros */
6919#define DISP_BASEADDR_MASK (0xfffff000)
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07006920#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6921#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07006922
Ville Syrjälä85fa7922015-09-18 20:03:43 +03006923/*
6924 * VBIOS flags
6925 * gen2:
6926 * [00:06] alm,mgm
6927 * [10:16] all
6928 * [30:32] alm,mgm
6929 * gen3+:
6930 * [00:0f] all
6931 * [10:1f] all
6932 * [30:32] all
6933 */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006934#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6935#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6936#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006937#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07006938
6939/* Pipe B */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006940#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6941#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6942#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03006943#define _PIPEBFRAMEHIGH 0x71040
6944#define _PIPEBFRAMEPIXEL 0x71044
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006945#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6946#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08006947
Jesse Barnes585fb112008-07-29 11:54:06 -07006948
6949/* Display B control */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006950#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006951#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07006952#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6953#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6954#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02006955#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6956#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6957#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6958#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6959#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6960#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6961#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6962#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07006963
Madhav Chauhan372610f2018-10-15 17:28:04 +03006964/* ICL DSI 0 and 1 */
6965#define _PIPEDSI0CONF 0x7b008
6966#define _PIPEDSI1CONF 0x7b808
6967
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006968/* Sprite A control */
6969#define _DVSACNTR 0x72180
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006970#define DVS_ENABLE (1 << 31)
6971#define DVS_GAMMA_ENABLE (1 << 30)
6972#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6973#define DVS_PIXFORMAT_MASK (3 << 25)
6974#define DVS_FORMAT_YUV422 (0 << 25)
6975#define DVS_FORMAT_RGBX101010 (1 << 25)
6976#define DVS_FORMAT_RGBX888 (2 << 25)
6977#define DVS_FORMAT_RGBX161616 (3 << 25)
6978#define DVS_PIPE_CSC_ENABLE (1 << 24)
6979#define DVS_SOURCE_KEY (1 << 22)
6980#define DVS_RGB_ORDER_XBGR (1 << 20)
6981#define DVS_YUV_FORMAT_BT709 (1 << 18)
Ville Syrjälä62f887a2021-12-01 17:25:40 +02006982#define DVS_YUV_ORDER_MASK (3 << 16)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07006983#define DVS_YUV_ORDER_YUYV (0 << 16)
6984#define DVS_YUV_ORDER_UYVY (1 << 16)
6985#define DVS_YUV_ORDER_YVYU (2 << 16)
6986#define DVS_YUV_ORDER_VYUY (3 << 16)
6987#define DVS_ROTATE_180 (1 << 15)
6988#define DVS_DEST_KEY (1 << 2)
6989#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6990#define DVS_TILED (1 << 10)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006991#define _DVSALINOFF 0x72184
6992#define _DVSASTRIDE 0x72188
6993#define _DVSAPOS 0x7218c
6994#define _DVSASIZE 0x72190
6995#define _DVSAKEYVAL 0x72194
6996#define _DVSAKEYMSK 0x72198
6997#define _DVSASURF 0x7219c
6998#define _DVSAKEYMAXVAL 0x721a0
6999#define _DVSATILEOFF 0x721a4
7000#define _DVSASURFLIVE 0x721ac
Ville Syrjälä94e15722019-07-03 23:08:21 +03007001#define _DVSAGAMC_G4X 0x721e0 /* g4x */
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007002#define _DVSASCALE 0x72204
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007003#define DVS_SCALE_ENABLE (1 << 31)
7004#define DVS_FILTER_MASK (3 << 29)
7005#define DVS_FILTER_MEDIUM (0 << 29)
7006#define DVS_FILTER_ENHANCING (1 << 29)
7007#define DVS_FILTER_SOFTENING (2 << 29)
7008#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
7009#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
Ville Syrjälä94e15722019-07-03 23:08:21 +03007010#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
7011#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007012
7013#define _DVSBCNTR 0x73180
7014#define _DVSBLINOFF 0x73184
7015#define _DVSBSTRIDE 0x73188
7016#define _DVSBPOS 0x7318c
7017#define _DVSBSIZE 0x73190
7018#define _DVSBKEYVAL 0x73194
7019#define _DVSBKEYMSK 0x73198
7020#define _DVSBSURF 0x7319c
7021#define _DVSBKEYMAXVAL 0x731a0
7022#define _DVSBTILEOFF 0x731a4
7023#define _DVSBSURFLIVE 0x731ac
Ville Syrjälä94e15722019-07-03 23:08:21 +03007024#define _DVSBGAMC_G4X 0x731e0 /* g4x */
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007025#define _DVSBSCALE 0x73204
Ville Syrjälä94e15722019-07-03 23:08:21 +03007026#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
7027#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007028
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007029#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
7030#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
7031#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
7032#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
7033#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
7034#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
7035#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
7036#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
7037#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
7038#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
7039#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
7040#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Ville Syrjälä94e15722019-07-03 23:08:21 +03007041#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
7042#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
7043#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007044
7045#define _SPRA_CTL 0x70280
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007046#define SPRITE_ENABLE (1 << 31)
7047#define SPRITE_GAMMA_ENABLE (1 << 30)
7048#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7049#define SPRITE_PIXFORMAT_MASK (7 << 25)
7050#define SPRITE_FORMAT_YUV422 (0 << 25)
7051#define SPRITE_FORMAT_RGBX101010 (1 << 25)
7052#define SPRITE_FORMAT_RGBX888 (2 << 25)
7053#define SPRITE_FORMAT_RGBX161616 (3 << 25)
7054#define SPRITE_FORMAT_YUV444 (4 << 25)
7055#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
7056#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
7057#define SPRITE_SOURCE_KEY (1 << 22)
7058#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
7059#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
7060#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
Ville Syrjälä62f887a2021-12-01 17:25:40 +02007061#define SPRITE_YUV_ORDER_MASK (3 << 16)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007062#define SPRITE_YUV_ORDER_YUYV (0 << 16)
7063#define SPRITE_YUV_ORDER_UYVY (1 << 16)
7064#define SPRITE_YUV_ORDER_YVYU (2 << 16)
7065#define SPRITE_YUV_ORDER_VYUY (3 << 16)
7066#define SPRITE_ROTATE_180 (1 << 15)
7067#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä423ee8e2019-07-03 23:08:20 +03007068#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007069#define SPRITE_TILED (1 << 10)
7070#define SPRITE_DEST_KEY (1 << 2)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007071#define _SPRA_LINOFF 0x70284
7072#define _SPRA_STRIDE 0x70288
7073#define _SPRA_POS 0x7028c
7074#define _SPRA_SIZE 0x70290
7075#define _SPRA_KEYVAL 0x70294
7076#define _SPRA_KEYMSK 0x70298
7077#define _SPRA_SURF 0x7029c
7078#define _SPRA_KEYMAX 0x702a0
7079#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01007080#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02007081#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007082#define _SPRA_SCALE 0x70304
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007083#define SPRITE_SCALE_ENABLE (1 << 31)
7084#define SPRITE_FILTER_MASK (3 << 29)
7085#define SPRITE_FILTER_MEDIUM (0 << 29)
7086#define SPRITE_FILTER_ENHANCING (1 << 29)
7087#define SPRITE_FILTER_SOFTENING (2 << 29)
7088#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
7089#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007090#define _SPRA_GAMC 0x70400
Ville Syrjälä94e15722019-07-03 23:08:21 +03007091#define _SPRA_GAMC16 0x70440
7092#define _SPRA_GAMC17 0x7044c
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007093
7094#define _SPRB_CTL 0x71280
7095#define _SPRB_LINOFF 0x71284
7096#define _SPRB_STRIDE 0x71288
7097#define _SPRB_POS 0x7128c
7098#define _SPRB_SIZE 0x71290
7099#define _SPRB_KEYVAL 0x71294
7100#define _SPRB_KEYMSK 0x71298
7101#define _SPRB_SURF 0x7129c
7102#define _SPRB_KEYMAX 0x712a0
7103#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01007104#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02007105#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007106#define _SPRB_SCALE 0x71304
7107#define _SPRB_GAMC 0x71400
Ville Syrjälä94e15722019-07-03 23:08:21 +03007108#define _SPRB_GAMC16 0x71440
7109#define _SPRB_GAMC17 0x7144c
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007110
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007111#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
7112#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
7113#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
7114#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
7115#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
7116#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
7117#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
7118#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
7119#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
7120#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
7121#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
7122#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
Ville Syrjälä94e15722019-07-03 23:08:21 +03007123#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
7124#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
7125#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007126#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007127
Ville Syrjälä921c3b62013-06-25 14:16:35 +03007128#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007129#define SP_ENABLE (1 << 31)
7130#define SP_GAMMA_ENABLE (1 << 30)
7131#define SP_PIXFORMAT_MASK (0xf << 26)
Ville Syrjäläd8aa1a42019-10-31 18:56:48 +02007132#define SP_FORMAT_YUV422 (0x0 << 26)
Ville Syrjäläed940342019-10-31 18:56:49 +02007133#define SP_FORMAT_8BPP (0x2 << 26)
Ville Syrjäläd8aa1a42019-10-31 18:56:48 +02007134#define SP_FORMAT_BGR565 (0x5 << 26)
7135#define SP_FORMAT_BGRX8888 (0x6 << 26)
7136#define SP_FORMAT_BGRA8888 (0x7 << 26)
7137#define SP_FORMAT_RGBX1010102 (0x8 << 26)
7138#define SP_FORMAT_RGBA1010102 (0x9 << 26)
7139#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
7140#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007141#define SP_FORMAT_RGBX8888 (0xe << 26)
7142#define SP_FORMAT_RGBA8888 (0xf << 26)
7143#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
7144#define SP_SOURCE_KEY (1 << 22)
7145#define SP_YUV_FORMAT_BT709 (1 << 18)
Ville Syrjälä62f887a2021-12-01 17:25:40 +02007146#define SP_YUV_ORDER_MASK (3 << 16)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007147#define SP_YUV_ORDER_YUYV (0 << 16)
7148#define SP_YUV_ORDER_UYVY (1 << 16)
7149#define SP_YUV_ORDER_YVYU (2 << 16)
7150#define SP_YUV_ORDER_VYUY (3 << 16)
7151#define SP_ROTATE_180 (1 << 15)
7152#define SP_TILED (1 << 10)
7153#define SP_MIRROR (1 << 8) /* CHV pipe B */
Ville Syrjälä921c3b62013-06-25 14:16:35 +03007154#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
7155#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
7156#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
7157#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
7158#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
7159#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
7160#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
7161#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
7162#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
7163#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007164#define SP_CONST_ALPHA_ENABLE (1 << 31)
Ville Syrjälä5deae912018-02-14 21:23:23 +02007165#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
7166#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
7167#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
7168#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
7169#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
7170#define SP_SH_COS(x) (x) /* u3.7 */
Ville Syrjälä94e15722019-07-03 23:08:21 +03007171#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07007172
Ville Syrjälä921c3b62013-06-25 14:16:35 +03007173#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
7174#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
7175#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
7176#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
7177#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
7178#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
7179#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
7180#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
7181#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
7182#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
7183#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
Ville Syrjälä5deae912018-02-14 21:23:23 +02007184#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
7185#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
Ville Syrjälä94e15722019-07-03 23:08:21 +03007186#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07007187
Ville Syrjälä94e15722019-07-03 23:08:21 +03007188#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
7189 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007190#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
Ville Syrjälä94e15722019-07-03 23:08:21 +03007191 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007192
7193#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
7194#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
7195#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
7196#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
7197#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
7198#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
7199#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
7200#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
7201#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
7202#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
7203#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
Ville Syrjälä5deae912018-02-14 21:23:23 +02007204#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
7205#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
Ville Syrjälä94e15722019-07-03 23:08:21 +03007206#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
Jesse Barnes7f1f3852013-04-02 11:22:20 -07007207
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03007208/*
7209 * CHV pipe B sprite CSC
7210 *
7211 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
7212 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
7213 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
7214 */
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007215#define _MMIO_CHV_SPCSC(plane_id, reg) \
7216 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
7217
7218#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
7219#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
7220#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03007221#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
7222#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
7223
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007224#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
7225#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
7226#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
7227#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
7228#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03007229#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
7230#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
7231
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007232#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
7233#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
7234#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03007235#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
7236#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
7237
Ville Syrjälä83c04a62016-11-22 18:02:00 +02007238#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
7239#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
7240#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03007241#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
7242#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
7243
Damien Lespiau70d21f02013-07-03 21:06:04 +01007244/* Skylake plane registers */
7245
7246#define _PLANE_CTL_1_A 0x70180
7247#define _PLANE_CTL_2_A 0x70280
7248#define _PLANE_CTL_3_A 0x70380
7249#define PLANE_CTL_ENABLE (1 << 31)
Ville Syrjälä0b869522021-05-26 20:36:00 +03007250#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
7251#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
James Ausmus4036c782017-11-13 10:11:28 -08007252#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
Ville Syrjäläc8624ed2018-02-14 21:23:27 +02007253#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
James Ausmusb5972772018-01-30 11:49:16 -02007254/*
7255 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
7256 * expanded to include bit 23 as well. However, the shift-24 based values
7257 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
7258 */
Damien Lespiau70d21f02013-07-03 21:06:04 +01007259#define PLANE_CTL_FORMAT_MASK (0xf << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007260#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
7261#define PLANE_CTL_FORMAT_NV12 (1 << 24)
7262#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
Juha-Pekka Heikkilae1312212019-03-04 17:26:30 +05307263#define PLANE_CTL_FORMAT_P010 (3 << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007264#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
Juha-Pekka Heikkilae1312212019-03-04 17:26:30 +05307265#define PLANE_CTL_FORMAT_P012 (5 << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007266#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
Juha-Pekka Heikkilae1312212019-03-04 17:26:30 +05307267#define PLANE_CTL_FORMAT_P016 (7 << 24)
Stanislav Lisovskiyda904172020-04-07 14:55:46 -07007268#define PLANE_CTL_FORMAT_XYUV (8 << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007269#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
7270#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
James Ausmusb5972772018-01-30 11:49:16 -02007271#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
James Ausmus4036c782017-11-13 10:11:28 -08007272#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
Swati Sharma696fa002019-03-04 17:26:34 +05307273#define PLANE_CTL_FORMAT_Y210 (1 << 23)
7274#define PLANE_CTL_FORMAT_Y212 (3 << 23)
7275#define PLANE_CTL_FORMAT_Y216 (5 << 23)
7276#define PLANE_CTL_FORMAT_Y410 (7 << 23)
7277#define PLANE_CTL_FORMAT_Y412 (9 << 23)
7278#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007279#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007280#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
7281#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
Damien Lespiau70d21f02013-07-03 21:06:04 +01007282#define PLANE_CTL_ORDER_BGRX (0 << 20)
7283#define PLANE_CTL_ORDER_RGBX (1 << 20)
Maarten Lankhorst1e364f92018-10-18 13:51:33 +02007284#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +02007285#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
Damien Lespiau70d21f02013-07-03 21:06:04 +01007286#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
Ville Syrjälä62f887a2021-12-01 17:25:40 +02007287#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
7288#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
7289#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
7290#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
Dhinakaran Pandiyan53867b42018-08-21 18:50:53 -07007291#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
Damien Lespiau70d21f02013-07-03 21:06:04 +01007292#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
Dhinakaran Pandiyanb3e57bc2019-12-21 14:05:39 +02007293#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
James Ausmus4036c782017-11-13 10:11:28 -08007294#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
Damien Lespiau70d21f02013-07-03 21:06:04 +01007295#define PLANE_CTL_TILED_MASK (0x7 << 10)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007296#define PLANE_CTL_TILED_LINEAR (0 << 10)
7297#define PLANE_CTL_TILED_X (1 << 10)
7298#define PLANE_CTL_TILED_Y (4 << 10)
7299#define PLANE_CTL_TILED_YF (5 << 10)
Karthik B Sc5e07e02020-09-21 16:32:04 +05307300#define PLANE_CTL_ASYNC_FLIP (1 << 9)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007301#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
Dhinakaran Pandiyan2dfbf9d2019-12-17 15:23:29 +02007302#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
James Ausmus4036c782017-11-13 10:11:28 -08007303#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007304#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
7305#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
7306#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
Sonika Jindal1447dde2014-10-04 10:53:31 +01007307#define PLANE_CTL_ROTATE_MASK 0x3
7308#define PLANE_CTL_ROTATE_0 0x0
Sonika Jindal3b7a5112015-04-10 14:37:29 +05307309#define PLANE_CTL_ROTATE_90 0x1
Sonika Jindal1447dde2014-10-04 10:53:31 +01007310#define PLANE_CTL_ROTATE_180 0x2
Sonika Jindal3b7a5112015-04-10 14:37:29 +05307311#define PLANE_CTL_ROTATE_270 0x3
Damien Lespiau70d21f02013-07-03 21:06:04 +01007312#define _PLANE_STRIDE_1_A 0x70188
7313#define _PLANE_STRIDE_2_A 0x70288
7314#define _PLANE_STRIDE_3_A 0x70388
7315#define _PLANE_POS_1_A 0x7018c
7316#define _PLANE_POS_2_A 0x7028c
7317#define _PLANE_POS_3_A 0x7038c
7318#define _PLANE_SIZE_1_A 0x70190
7319#define _PLANE_SIZE_2_A 0x70290
7320#define _PLANE_SIZE_3_A 0x70390
7321#define _PLANE_SURF_1_A 0x7019c
7322#define _PLANE_SURF_2_A 0x7029c
7323#define _PLANE_SURF_3_A 0x7039c
7324#define _PLANE_OFFSET_1_A 0x701a4
7325#define _PLANE_OFFSET_2_A 0x702a4
7326#define _PLANE_OFFSET_3_A 0x703a4
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007327#define _PLANE_KEYVAL_1_A 0x70194
7328#define _PLANE_KEYVAL_2_A 0x70294
7329#define _PLANE_KEYMSK_1_A 0x70198
7330#define _PLANE_KEYMSK_2_A 0x70298
Maarten Lankhorstb2081522018-08-15 12:34:05 +02007331#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007332#define _PLANE_KEYMAX_1_A 0x701a0
7333#define _PLANE_KEYMAX_2_A 0x702a0
Ville Syrjälä7b012bd2018-11-07 20:41:38 +02007334#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
Radhakrishna Sripadad1e27752021-01-15 23:39:52 +02007335#define _PLANE_CC_VAL_1_A 0x701b4
7336#define _PLANE_CC_VAL_2_A 0x702b4
Ville Syrjälä2e2adb02017-08-01 09:58:13 -07007337#define _PLANE_AUX_DIST_1_A 0x701c0
7338#define _PLANE_AUX_DIST_2_A 0x702c0
7339#define _PLANE_AUX_OFFSET_1_A 0x701c4
7340#define _PLANE_AUX_OFFSET_2_A 0x702c4
Maarten Lankhorstcb2458b2018-10-18 13:51:32 +02007341#define _PLANE_CUS_CTL_1_A 0x701c8
7342#define _PLANE_CUS_CTL_2_A 0x702c8
7343#define PLANE_CUS_ENABLE (1 << 31)
Ville Syrjäläd96c5ed2021-12-01 17:25:43 +02007344#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
7345#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
7346#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
7347#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
Maarten Lankhorstcb2458b2018-10-18 13:51:32 +02007348#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
7349#define PLANE_CUS_HPHASE_0 (0 << 16)
7350#define PLANE_CUS_HPHASE_0_25 (1 << 16)
7351#define PLANE_CUS_HPHASE_0_5 (2 << 16)
7352#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
7353#define PLANE_CUS_VPHASE_0 (0 << 12)
7354#define PLANE_CUS_VPHASE_0_25 (1 << 12)
7355#define PLANE_CUS_VPHASE_0_5 (2 << 12)
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02007356#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
7357#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
7358#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
James Ausmus077ef1f2018-03-28 14:57:56 -07007359#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
Ville Syrjäläc8624ed2018-02-14 21:23:27 +02007360#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
Anshuman Gupta6eba56f2021-09-24 12:14:49 -07007361#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
Uma Shankar6a255da2018-11-02 00:40:19 +05307362#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
James Ausmus077ef1f2018-03-28 14:57:56 -07007363#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
Ville Syrjälä38f24f22018-02-14 21:23:24 +02007364#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
Kishore Kadiyalaa0196dd2020-06-01 13:05:44 +05307365#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
Ville Syrjälä38f24f22018-02-14 21:23:24 +02007366#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
7367#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
7368#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02007369#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
James Ausmus4036c782017-11-13 10:11:28 -08007370#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
7371#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
7372#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
7373#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
Damien Lespiau8211bd52014-11-04 17:06:44 +00007374#define _PLANE_BUF_CFG_1_A 0x7027c
7375#define _PLANE_BUF_CFG_2_A 0x7037c
Chandra Konduru2cd601c2015-04-27 15:47:37 -07007376#define _PLANE_NV12_BUF_CFG_1_A 0x70278
7377#define _PLANE_NV12_BUF_CFG_2_A 0x70378
Damien Lespiau70d21f02013-07-03 21:06:04 +01007378
Ville Syrjäläf84b3362021-12-01 17:25:39 +02007379#define _PLANE_CC_VAL_1_B 0x711b4
7380#define _PLANE_CC_VAL_2_B 0x712b4
7381#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
7382#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
7383#define PLANE_CC_VAL(pipe, plane, dw) \
7384 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
Radhakrishna Sripadad1e27752021-01-15 23:39:52 +02007385
Uma Shankar6a255da2018-11-02 00:40:19 +05307386/* Input CSC Register Definitions */
7387#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
7388#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
7389
7390#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
7391#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
7392
7393#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
7394 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
7395 _PLANE_INPUT_CSC_RY_GY_1_B)
7396#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
7397 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7398 _PLANE_INPUT_CSC_RY_GY_2_B)
7399
7400#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
7401 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
7402 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
7403
7404#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
7405#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
7406
7407#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
7408#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
7409
7410#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
7411 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
7412 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
7413#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
7414 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
7415 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
7416#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
7417 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
7418 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
7419
7420#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
7421#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
7422
7423#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
7424#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
7425
7426#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
7427 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
7428 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
7429#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
7430 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
7431 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
7432#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
7433 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
7434 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02007435
Damien Lespiau70d21f02013-07-03 21:06:04 +01007436#define _PLANE_CTL_1_B 0x71180
7437#define _PLANE_CTL_2_B 0x71280
7438#define _PLANE_CTL_3_B 0x71380
7439#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
7440#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
7441#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
7442#define PLANE_CTL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007443 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01007444
7445#define _PLANE_STRIDE_1_B 0x71188
7446#define _PLANE_STRIDE_2_B 0x71288
7447#define _PLANE_STRIDE_3_B 0x71388
7448#define _PLANE_STRIDE_1(pipe) \
7449 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
7450#define _PLANE_STRIDE_2(pipe) \
7451 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
7452#define _PLANE_STRIDE_3(pipe) \
7453 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
7454#define PLANE_STRIDE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007455 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
Juha-Pekka Heikkiläe7367af12021-05-06 19:19:26 +03007456#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
7457#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
Damien Lespiau70d21f02013-07-03 21:06:04 +01007458
7459#define _PLANE_POS_1_B 0x7118c
7460#define _PLANE_POS_2_B 0x7128c
7461#define _PLANE_POS_3_B 0x7138c
7462#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
7463#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
7464#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
7465#define PLANE_POS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007466 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01007467
7468#define _PLANE_SIZE_1_B 0x71190
7469#define _PLANE_SIZE_2_B 0x71290
7470#define _PLANE_SIZE_3_B 0x71390
7471#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
7472#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
7473#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
7474#define PLANE_SIZE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007475 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01007476
7477#define _PLANE_SURF_1_B 0x7119c
7478#define _PLANE_SURF_2_B 0x7129c
7479#define _PLANE_SURF_3_B 0x7139c
7480#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
7481#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
7482#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
7483#define PLANE_SURF(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007484 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
Anshuman Guptaef6ba312021-09-24 12:14:48 -07007485#define PLANE_SURF_DECRYPT REG_BIT(2)
Damien Lespiau70d21f02013-07-03 21:06:04 +01007486
7487#define _PLANE_OFFSET_1_B 0x711a4
7488#define _PLANE_OFFSET_2_B 0x712a4
7489#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
7490#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
7491#define PLANE_OFFSET(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007492 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01007493
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007494#define _PLANE_KEYVAL_1_B 0x71194
7495#define _PLANE_KEYVAL_2_B 0x71294
7496#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
7497#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
7498#define PLANE_KEYVAL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007499 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007500
7501#define _PLANE_KEYMSK_1_B 0x71198
7502#define _PLANE_KEYMSK_2_B 0x71298
7503#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
7504#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
7505#define PLANE_KEYMSK(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007506 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007507
7508#define _PLANE_KEYMAX_1_B 0x711a0
7509#define _PLANE_KEYMAX_2_B 0x712a0
7510#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
7511#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
7512#define PLANE_KEYMAX(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007513 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00007514
Damien Lespiau8211bd52014-11-04 17:06:44 +00007515#define _PLANE_BUF_CFG_1_B 0x7127c
7516#define _PLANE_BUF_CFG_2_B 0x7137c
Vandita Kulkarni247bdac2021-05-18 17:06:15 -07007517#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
Mahesh Kumar37cde112018-04-26 19:55:17 +05307518#define DDB_ENTRY_END_SHIFT 16
Damien Lespiau8211bd52014-11-04 17:06:44 +00007519#define _PLANE_BUF_CFG_1(pipe) \
7520 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7521#define _PLANE_BUF_CFG_2(pipe) \
7522 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7523#define PLANE_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007524 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
Damien Lespiau8211bd52014-11-04 17:06:44 +00007525
Chandra Konduru2cd601c2015-04-27 15:47:37 -07007526#define _PLANE_NV12_BUF_CFG_1_B 0x71278
7527#define _PLANE_NV12_BUF_CFG_2_B 0x71378
7528#define _PLANE_NV12_BUF_CFG_1(pipe) \
7529 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7530#define _PLANE_NV12_BUF_CFG_2(pipe) \
7531 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7532#define PLANE_NV12_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007533 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
Chandra Konduru2cd601c2015-04-27 15:47:37 -07007534
Ville Syrjälä2e2adb02017-08-01 09:58:13 -07007535#define _PLANE_AUX_DIST_1_B 0x711c0
7536#define _PLANE_AUX_DIST_2_B 0x712c0
7537#define _PLANE_AUX_DIST_1(pipe) \
7538 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7539#define _PLANE_AUX_DIST_2(pipe) \
7540 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7541#define PLANE_AUX_DIST(pipe, plane) \
7542 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7543
7544#define _PLANE_AUX_OFFSET_1_B 0x711c4
7545#define _PLANE_AUX_OFFSET_2_B 0x712c4
7546#define _PLANE_AUX_OFFSET_1(pipe) \
7547 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7548#define _PLANE_AUX_OFFSET_2(pipe) \
7549 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7550#define PLANE_AUX_OFFSET(pipe, plane) \
7551 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7552
Maarten Lankhorstcb2458b2018-10-18 13:51:32 +02007553#define _PLANE_CUS_CTL_1_B 0x711c8
7554#define _PLANE_CUS_CTL_2_B 0x712c8
7555#define _PLANE_CUS_CTL_1(pipe) \
7556 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7557#define _PLANE_CUS_CTL_2(pipe) \
7558 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7559#define PLANE_CUS_CTL(pipe, plane) \
7560 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7561
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02007562#define _PLANE_COLOR_CTL_1_B 0x711CC
7563#define _PLANE_COLOR_CTL_2_B 0x712CC
7564#define _PLANE_COLOR_CTL_3_B 0x713CC
7565#define _PLANE_COLOR_CTL_1(pipe) \
7566 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7567#define _PLANE_COLOR_CTL_2(pipe) \
7568 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7569#define PLANE_COLOR_CTL(pipe, plane) \
7570 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7571
José Roberto de Souzaa5523e22020-06-25 18:01:49 -07007572#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
7573#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
7574#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
7575#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
7576#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
7577#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
7578#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
7579#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
7580#define _SEL_FETCH_PLANE_BASE_1_B 0x70990
7581
7582#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
7583 _SEL_FETCH_PLANE_BASE_1_A, \
7584 _SEL_FETCH_PLANE_BASE_2_A, \
7585 _SEL_FETCH_PLANE_BASE_3_A, \
7586 _SEL_FETCH_PLANE_BASE_4_A, \
7587 _SEL_FETCH_PLANE_BASE_5_A, \
7588 _SEL_FETCH_PLANE_BASE_6_A, \
7589 _SEL_FETCH_PLANE_BASE_7_A, \
7590 _SEL_FETCH_PLANE_BASE_CUR_A)
7591#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
7592#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7593 _SEL_FETCH_PLANE_BASE_1_A + \
7594 _SEL_FETCH_PLANE_BASE_A(plane))
7595
7596#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
7597#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7598 _SEL_FETCH_PLANE_CTL_1_A - \
7599 _SEL_FETCH_PLANE_BASE_1_A)
7600#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
7601
7602#define _SEL_FETCH_PLANE_POS_1_A 0x70894
7603#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7604 _SEL_FETCH_PLANE_POS_1_A - \
7605 _SEL_FETCH_PLANE_BASE_1_A)
7606
7607#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
7608#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7609 _SEL_FETCH_PLANE_SIZE_1_A - \
7610 _SEL_FETCH_PLANE_BASE_1_A)
7611
7612#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
7613#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7614 _SEL_FETCH_PLANE_OFFSET_1_A - \
7615 _SEL_FETCH_PLANE_BASE_1_A)
7616
7617/* SKL new cursor registers */
Damien Lespiau8211bd52014-11-04 17:06:44 +00007618#define _CUR_BUF_CFG_A 0x7017c
7619#define _CUR_BUF_CFG_B 0x7117c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007620#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
Damien Lespiau8211bd52014-11-04 17:06:44 +00007621
Jesse Barnes585fb112008-07-29 11:54:06 -07007622/* VBIOS regs */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007623#define VGACNTRL _MMIO(0x71400)
Jesse Barnes585fb112008-07-29 11:54:06 -07007624# define VGA_DISP_DISABLE (1 << 31)
7625# define VGA_2X_MODE (1 << 30)
7626# define VGA_PIPE_B_SELECT (1 << 29)
7627
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007628#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02007629
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007630/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08007631
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007632#define CPU_VGACNTRL _MMIO(0x41000)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007633
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007634#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007635#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
7636#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
7637#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
7638#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
7639#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
7640#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
7641#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
7642#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
7643#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
7644#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007645
7646/* refresh rate hardware control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007647#define RR_HW_CTL _MMIO(0x45300)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007648#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
7649#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
7650
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007651#define FDI_PLL_BIOS_0 _MMIO(0x46000)
Chris Wilson021357a2010-09-07 20:54:59 +01007652#define FDI_PLL_FB_CLOCK_MASK 0xff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007653#define FDI_PLL_BIOS_1 _MMIO(0x46004)
7654#define FDI_PLL_BIOS_2 _MMIO(0x46008)
7655#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
7656#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
7657#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007658
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007659#define PCH_3DCGDIS0 _MMIO(0x46020)
Eric Anholt8956c8b2010-03-18 13:21:14 -07007660# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
7661# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
7662
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007663#define PCH_3DCGDIS1 _MMIO(0x46024)
Eric Anholt06f37752010-12-14 10:06:46 -08007664# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
7665
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007666#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007667#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007668#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
7669#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
7670
7671
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007672#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01007673#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007674#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01007675#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08007676
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007677#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01007678#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007679#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01007680#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08007681
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007682#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01007683#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007684#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01007685#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08007686
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007687#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01007688#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007689#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01007690#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08007691
7692/* PIPEB timing regs are same start from 0x61000 */
7693
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007694#define _PIPEB_DATA_M1 0x61030
7695#define _PIPEB_DATA_N1 0x61034
7696#define _PIPEB_DATA_M2 0x61038
7697#define _PIPEB_DATA_N2 0x6103c
7698#define _PIPEB_LINK_M1 0x61040
7699#define _PIPEB_LINK_N1 0x61044
7700#define _PIPEB_LINK_M2 0x61048
7701#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08007702
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007703#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7704#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7705#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7706#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7707#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7708#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7709#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7710#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007711
7712/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007713/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7714#define _PFA_CTL_1 0x68080
7715#define _PFB_CTL_1 0x68880
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007716#define PF_ENABLE (1 << 31)
7717#define PF_PIPE_SEL_MASK_IVB (3 << 29)
7718#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
7719#define PF_FILTER_MASK (3 << 23)
7720#define PF_FILTER_PROGRAMMED (0 << 23)
7721#define PF_FILTER_MED_3x3 (1 << 23)
7722#define PF_FILTER_EDGE_ENHANCE (2 << 23)
7723#define PF_FILTER_EDGE_SOFTEN (3 << 23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007724#define _PFA_WIN_SZ 0x68074
7725#define _PFB_WIN_SZ 0x68874
7726#define _PFA_WIN_POS 0x68070
7727#define _PFB_WIN_POS 0x68870
7728#define _PFA_VSCALE 0x68084
7729#define _PFB_VSCALE 0x68884
7730#define _PFA_HSCALE 0x68090
7731#define _PFB_HSCALE 0x68890
7732
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007733#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7734#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7735#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7736#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7737#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007738
Jesse Barnesbd2e2442014-11-13 17:51:47 +00007739#define _PSA_CTL 0x68180
7740#define _PSB_CTL 0x68980
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007741#define PS_ENABLE (1 << 31)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00007742#define _PSA_WIN_SZ 0x68174
7743#define _PSB_WIN_SZ 0x68974
7744#define _PSA_WIN_POS 0x68170
7745#define _PSB_WIN_POS 0x68970
7746
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007747#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7748#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7749#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00007750
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007751/*
7752 * Skylake scalers
7753 */
7754#define _PS_1A_CTRL 0x68180
7755#define _PS_2A_CTRL 0x68280
7756#define _PS_1B_CTRL 0x68980
7757#define _PS_2B_CTRL 0x68A80
7758#define _PS_1C_CTRL 0x69180
7759#define PS_SCALER_EN (1 << 31)
Maarten Lankhorst0aaf29b2018-09-21 16:44:37 +02007760#define SKL_PS_SCALER_MODE_MASK (3 << 28)
7761#define SKL_PS_SCALER_MODE_DYN (0 << 28)
7762#define SKL_PS_SCALER_MODE_HQ (1 << 28)
Chandra Kondurue6e19482018-04-09 09:11:11 +05307763#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7764#define PS_SCALER_MODE_PLANAR (1 << 29)
Maarten Lankhorstb1554e22018-10-18 13:51:31 +02007765#define PS_SCALER_MODE_NORMAL (0 << 29)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007766#define PS_PLANE_SEL_MASK (7 << 25)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007767#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007768#define PS_FILTER_MASK (3 << 23)
7769#define PS_FILTER_MEDIUM (0 << 23)
Pankaj Bharadiya105c9e12020-10-20 21:44:24 +05307770#define PS_FILTER_PROGRAMMED (1 << 23)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007771#define PS_FILTER_EDGE_ENHANCE (2 << 23)
7772#define PS_FILTER_BILINEAR (3 << 23)
7773#define PS_VERT3TAP (1 << 21)
7774#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7775#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7776#define PS_PWRUP_PROGRESS (1 << 17)
7777#define PS_V_FILTER_BYPASS (1 << 8)
7778#define PS_VADAPT_EN (1 << 7)
7779#define PS_VADAPT_MODE_MASK (3 << 5)
7780#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7781#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7782#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
Maarten Lankhorstb1554e22018-10-18 13:51:31 +02007783#define PS_PLANE_Y_SEL_MASK (7 << 5)
7784#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
Pankaj Bharadiya105c9e12020-10-20 21:44:24 +05307785#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
7786#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
7787#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
7788#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007789
7790#define _PS_PWR_GATE_1A 0x68160
7791#define _PS_PWR_GATE_2A 0x68260
7792#define _PS_PWR_GATE_1B 0x68960
7793#define _PS_PWR_GATE_2B 0x68A60
7794#define _PS_PWR_GATE_1C 0x69160
7795#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7796#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7797#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7798#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7799#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7800#define PS_PWR_GATE_SLPEN_8 0
7801#define PS_PWR_GATE_SLPEN_16 1
7802#define PS_PWR_GATE_SLPEN_24 2
7803#define PS_PWR_GATE_SLPEN_32 3
7804
7805#define _PS_WIN_POS_1A 0x68170
7806#define _PS_WIN_POS_2A 0x68270
7807#define _PS_WIN_POS_1B 0x68970
7808#define _PS_WIN_POS_2B 0x68A70
7809#define _PS_WIN_POS_1C 0x69170
7810
7811#define _PS_WIN_SZ_1A 0x68174
7812#define _PS_WIN_SZ_2A 0x68274
7813#define _PS_WIN_SZ_1B 0x68974
7814#define _PS_WIN_SZ_2B 0x68A74
7815#define _PS_WIN_SZ_1C 0x69174
7816
7817#define _PS_VSCALE_1A 0x68184
7818#define _PS_VSCALE_2A 0x68284
7819#define _PS_VSCALE_1B 0x68984
7820#define _PS_VSCALE_2B 0x68A84
7821#define _PS_VSCALE_1C 0x69184
7822
7823#define _PS_HSCALE_1A 0x68190
7824#define _PS_HSCALE_2A 0x68290
7825#define _PS_HSCALE_1B 0x68990
7826#define _PS_HSCALE_2B 0x68A90
7827#define _PS_HSCALE_1C 0x69190
7828
7829#define _PS_VPHASE_1A 0x68188
7830#define _PS_VPHASE_2A 0x68288
7831#define _PS_VPHASE_1B 0x68988
7832#define _PS_VPHASE_2B 0x68A88
7833#define _PS_VPHASE_1C 0x69188
Ville Syrjälä0a599522018-05-21 21:56:13 +03007834#define PS_Y_PHASE(x) ((x) << 16)
7835#define PS_UV_RGB_PHASE(x) ((x) << 0)
7836#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7837#define PS_PHASE_TRIP (1 << 0)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007838
7839#define _PS_HPHASE_1A 0x68194
7840#define _PS_HPHASE_2A 0x68294
7841#define _PS_HPHASE_1B 0x68994
7842#define _PS_HPHASE_2B 0x68A94
7843#define _PS_HPHASE_1C 0x69194
7844
7845#define _PS_ECC_STAT_1A 0x681D0
7846#define _PS_ECC_STAT_2A 0x682D0
7847#define _PS_ECC_STAT_1B 0x689D0
7848#define _PS_ECC_STAT_2B 0x68AD0
7849#define _PS_ECC_STAT_1C 0x691D0
7850
Pankaj Bharadiya105c9e12020-10-20 21:44:24 +05307851#define _PS_COEF_SET0_INDEX_1A 0x68198
7852#define _PS_COEF_SET0_INDEX_2A 0x68298
7853#define _PS_COEF_SET0_INDEX_1B 0x68998
7854#define _PS_COEF_SET0_INDEX_2B 0x68A98
7855#define PS_COEE_INDEX_AUTO_INC (1 << 10)
7856
7857#define _PS_COEF_SET0_DATA_1A 0x6819C
7858#define _PS_COEF_SET0_DATA_2A 0x6829C
7859#define _PS_COEF_SET0_DATA_1B 0x6899C
7860#define _PS_COEF_SET0_DATA_2B 0x68A9C
7861
Jani Nikulae67005e2018-06-29 13:20:39 +03007862#define _ID(id, a, b) _PICK_EVEN(id, a, b)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007863#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007864 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7865 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007866#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007867 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7868 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007869#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007870 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7871 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007872#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007873 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7874 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007875#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007876 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7877 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007878#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007879 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7880 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007881#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007882 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7883 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007884#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007885 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7886 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007887#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007888 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
Ville Syrjälä9bca5d02015-11-04 23:20:16 +02007889 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
Lucas De Marchi4a8b03a2021-07-28 14:59:36 -07007890#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
Pankaj Bharadiya105c9e12020-10-20 21:44:24 +05307891 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
7892 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07007893
Lucas De Marchi4a8b03a2021-07-28 14:59:36 -07007894#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
Pankaj Bharadiya105c9e12020-10-20 21:44:24 +05307895 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
7896 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007897/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007898#define _LGC_PALETTE_A 0x4a000
7899#define _LGC_PALETTE_B 0x4a800
Swati Sharma1af22382019-09-04 00:52:55 +05307900#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
7901#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
7902#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007903#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007904
Ville Syrjälä514462c2019-04-01 23:02:28 +03007905/* ilk/snb precision palette */
7906#define _PREC_PALETTE_A 0x4b000
7907#define _PREC_PALETTE_B 0x4c000
Swati Sharma6b97b112019-09-04 00:52:56 +05307908#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
7909#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7910#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
Ville Syrjälä514462c2019-04-01 23:02:28 +03007911#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7912
7913#define _PREC_PIPEAGCMAX 0x4d000
7914#define _PREC_PIPEBGCMAX 0x4d010
7915#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7916
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007917#define _GAMMA_MODE_A 0x4a480
7918#define _GAMMA_MODE_B 0x4ac80
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007919#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
Uma Shankar13717ce2019-02-11 19:20:22 +05307920#define PRE_CSC_GAMMA_ENABLE (1 << 31)
7921#define POST_CSC_GAMMA_ENABLE (1 << 30)
Ville Syrjälä5bda1ac2019-04-01 23:02:26 +03007922#define GAMMA_MODE_MODE_MASK (3 << 0)
Uma Shankar13717ce2019-02-11 19:20:22 +05307923#define GAMMA_MODE_MODE_8BIT (0 << 0)
7924#define GAMMA_MODE_MODE_10BIT (1 << 0)
7925#define GAMMA_MODE_MODE_12BIT (2 << 0)
Uma Shankar377c70e2019-06-12 12:14:58 +05307926#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7927#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007928
Anusha Srivatsa0633cdc2021-05-18 14:34:42 -07007929/* DMC */
Anusha Srivatsa3d5928a2021-06-21 12:14:13 -07007930#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
Anusha Srivatsa0633cdc2021-05-18 14:34:42 -07007931#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
7932#define DMC_HTP_ADDR_SKL 0x00500034
7933#define DMC_SSP_BASE _MMIO(0x8F074)
7934#define DMC_HTP_SKL _MMIO(0x8F004)
7935#define DMC_LAST_WRITE _MMIO(0x8F034)
7936#define DMC_LAST_WRITE_VALUE 0xc003b400
7937/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
7938#define DMC_MMIO_START_RANGE 0x80000
7939#define DMC_MMIO_END_RANGE 0x8FFFF
7940#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
7941#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
7942#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
José Roberto de Souza5d571062019-07-25 17:24:10 -07007943#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7944#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
Anshuman Gupta5bcc95c2020-10-14 12:19:36 -07007945#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
Damien Lespiau83372062015-10-30 17:53:32 +02007946
Anshuman Gupta41286862019-10-03 13:47:38 +05307947#define DMC_DEBUG3 _MMIO(0x101090)
7948
Uma Shankar1d85a292018-08-07 21:15:35 +05307949/* Display Internal Timeout Register */
7950#define RM_TIMEOUT _MMIO(0x42060)
7951#define MMIO_TIMEOUT_US(us) ((us) << 0)
7952
Zhenyu Wangb9055052009-06-05 15:38:38 +08007953/* interrupts */
7954#define DE_MASTER_IRQ_CONTROL (1 << 31)
7955#define DE_SPRITEB_FLIP_DONE (1 << 29)
7956#define DE_SPRITEA_FLIP_DONE (1 << 28)
7957#define DE_PLANEB_FLIP_DONE (1 << 27)
7958#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c22013-10-21 18:04:36 +02007959#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08007960#define DE_PCU_EVENT (1 << 25)
7961#define DE_GTT_FAULT (1 << 24)
7962#define DE_POISON (1 << 23)
7963#define DE_PERFORM_COUNTER (1 << 22)
7964#define DE_PCH_EVENT (1 << 21)
7965#define DE_AUX_CHANNEL_A (1 << 20)
7966#define DE_DP_A_HOTPLUG (1 << 19)
7967#define DE_GSE (1 << 18)
7968#define DE_PIPEB_VBLANK (1 << 15)
7969#define DE_PIPEB_EVEN_FIELD (1 << 14)
7970#define DE_PIPEB_ODD_FIELD (1 << 13)
7971#define DE_PIPEB_LINE_COMPARE (1 << 12)
7972#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02007973#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007974#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7975#define DE_PIPEA_VBLANK (1 << 7)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007976#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08007977#define DE_PIPEA_EVEN_FIELD (1 << 6)
7978#define DE_PIPEA_ODD_FIELD (1 << 5)
7979#define DE_PIPEA_LINE_COMPARE (1 << 4)
7980#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02007981#define DE_PIPEA_CRC_DONE (1 << 2)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007982#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08007983#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007984#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08007985
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07007986/* More Ivybridge lolz */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07007987#define DE_ERR_INT_IVB (1 << 30)
7988#define DE_GSE_IVB (1 << 29)
7989#define DE_PCH_EVENT_IVB (1 << 28)
7990#define DE_DP_A_HOTPLUG_IVB (1 << 27)
7991#define DE_AUX_CHANNEL_A_IVB (1 << 26)
7992#define DE_EDP_PSR_INT_HSW (1 << 19)
7993#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7994#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7995#define DE_PIPEC_VBLANK_IVB (1 << 10)
7996#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7997#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7998#define DE_PIPEB_VBLANK_IVB (1 << 5)
7999#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
8000#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
8001#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
8002#define DE_PIPEA_VBLANK_IVB (1 << 0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008003#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
Paulo Zanonib5184212013-07-12 20:00:08 -03008004
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008005#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008006#define MASTER_INTERRUPT_ENABLE (1 << 31)
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07008007
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008008#define DEISR _MMIO(0x44000)
8009#define DEIMR _MMIO(0x44004)
8010#define DEIIR _MMIO(0x44008)
8011#define DEIER _MMIO(0x4400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008012
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008013#define GTISR _MMIO(0x44010)
8014#define GTIMR _MMIO(0x44014)
8015#define GTIIR _MMIO(0x44018)
8016#define GTIER _MMIO(0x4401c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008017
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008018#define GEN8_MASTER_IRQ _MMIO(0x44200)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008019#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
8020#define GEN8_PCU_IRQ (1 << 30)
8021#define GEN8_DE_PCH_IRQ (1 << 23)
8022#define GEN8_DE_MISC_IRQ (1 << 22)
8023#define GEN8_DE_PORT_IRQ (1 << 20)
8024#define GEN8_DE_PIPE_C_IRQ (1 << 18)
8025#define GEN8_DE_PIPE_B_IRQ (1 << 17)
8026#define GEN8_DE_PIPE_A_IRQ (1 << 16)
8027#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
8028#define GEN8_GT_VECS_IRQ (1 << 6)
8029#define GEN8_GT_GUC_IRQ (1 << 5)
8030#define GEN8_GT_PM_IRQ (1 << 4)
Chris Wilson8a68d462019-03-05 18:03:30 +00008031#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
8032#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008033#define GEN8_GT_BCS_IRQ (1 << 1)
8034#define GEN8_GT_RCS_IRQ (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008035
Matt Roper0e53fb82021-05-11 21:21:42 -07008036#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
8037
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008038#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
8039#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
8040#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
8041#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
Ben Widawskyabd58f02013-11-02 21:07:09 -07008042
Ben Widawskyabd58f02013-11-02 21:07:09 -07008043#define GEN8_RCS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01008044#define GEN8_BCS_IRQ_SHIFT 16
Chris Wilson8a68d462019-03-05 18:03:30 +00008045#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
8046#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
Ben Widawskyabd58f02013-11-02 21:07:09 -07008047#define GEN8_VECS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01008048#define GEN8_WD_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07008049
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008050#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
8051#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
8052#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
8053#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01008054#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008055#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
8056#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
Matt Roper8bcc0842021-05-25 17:06:54 -07008057#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
8058#define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008059#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
8060#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
8061#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
8062#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01008063#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008064#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
8065#define GEN8_PIPE_VSYNC (1 << 1)
8066#define GEN8_PIPE_VBLANK (1 << 0)
Damien Lespiau770de83d2014-03-20 20:45:01 +00008067#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
Matt Roperd506a652019-10-08 14:17:16 -07008068#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
8069#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
8070#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
Damien Lespiaub21249c2015-03-17 11:39:33 +02008071#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
Damien Lespiau770de83d2014-03-20 20:45:01 +00008072#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
8073#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
8074#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
Damien Lespiaub21249c2015-03-17 11:39:33 +02008075#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
Damien Lespiau770de83d2014-03-20 20:45:01 +00008076#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
8077#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
8078#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008079#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
Daniel Vetter30100f22013-11-07 14:49:24 +01008080#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
8081 (GEN8_PIPE_CURSOR_FAULT | \
8082 GEN8_PIPE_SPRITE_FAULT | \
8083 GEN8_PIPE_PRIMARY_FAULT)
Damien Lespiau770de83d2014-03-20 20:45:01 +00008084#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
8085 (GEN9_PIPE_CURSOR_FAULT | \
Damien Lespiaub21249c2015-03-17 11:39:33 +02008086 GEN9_PIPE_PLANE4_FAULT | \
Damien Lespiau770de83d2014-03-20 20:45:01 +00008087 GEN9_PIPE_PLANE3_FAULT | \
8088 GEN9_PIPE_PLANE2_FAULT | \
8089 GEN9_PIPE_PLANE1_FAULT)
Matt Roperd506a652019-10-08 14:17:16 -07008090#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
8091 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
8092 GEN11_PIPE_PLANE7_FAULT | \
8093 GEN11_PIPE_PLANE6_FAULT | \
8094 GEN11_PIPE_PLANE5_FAULT)
Matt Roper99e2d8b2020-05-04 15:52:12 -07008095#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
8096 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
8097 GEN11_PIPE_PLANE5_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008098
Ville Syrjälä8625b222020-10-28 23:33:11 +02008099#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
Ville Syrjälä5b76e862020-10-28 23:33:14 +02008100#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
Ville Syrjälä8625b222020-10-28 23:33:11 +02008101
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008102#define GEN8_DE_PORT_ISR _MMIO(0x44440)
8103#define GEN8_DE_PORT_IMR _MMIO(0x44444)
8104#define GEN8_DE_PORT_IIR _MMIO(0x44448)
8105#define GEN8_DE_PORT_IER _MMIO(0x4444c)
Vandita Kulkarni64ad5322019-11-11 16:40:21 +05308106#define DSI1_NON_TE (1 << 31)
8107#define DSI0_NON_TE (1 << 30)
James Ausmusbb187e92018-06-11 17:25:12 -07008108#define ICL_AUX_CHANNEL_E (1 << 29)
Lucas De Marchi938a8a92021-07-28 14:59:37 -07008109#define ICL_AUX_CHANNEL_F (1 << 28)
Jesse Barnes88e04702014-11-13 17:51:48 +00008110#define GEN9_AUX_CHANNEL_D (1 << 27)
8111#define GEN9_AUX_CHANNEL_C (1 << 26)
8112#define GEN9_AUX_CHANNEL_B (1 << 25)
Vandita Kulkarni64ad5322019-11-11 16:40:21 +05308113#define DSI1_TE (1 << 24)
8114#define DSI0_TE (1 << 23)
Ville Syrjäläe5abaab2020-10-28 23:33:12 +02008115#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
8116#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
8117 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
8118 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
8119#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
Shashank Sharma9e637432014-08-22 17:40:43 +05308120#define BXT_DE_PORT_GMBUS (1 << 1)
Daniel Vetter6d766f02013-11-07 14:49:55 +01008121#define GEN8_AUX_CHANNEL_A (1 << 0)
Matt Roper20fe7782021-05-11 21:21:38 -07008122#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
8123#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
8124#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
8125#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
8126#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
8127#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
8128#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
8129#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
8130#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
8131#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
8132#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008133
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008134#define GEN8_DE_MISC_ISR _MMIO(0x44460)
8135#define GEN8_DE_MISC_IMR _MMIO(0x44464)
8136#define GEN8_DE_MISC_IIR _MMIO(0x44468)
8137#define GEN8_DE_MISC_IER _MMIO(0x4446c)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008138#define GEN8_DE_MISC_GSE (1 << 27)
Ville Syrjäläe04f7ec2018-04-03 14:24:18 -07008139#define GEN8_DE_EDP_PSR (1 << 19)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008140
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008141#define GEN8_PCU_ISR _MMIO(0x444e0)
8142#define GEN8_PCU_IMR _MMIO(0x444e4)
8143#define GEN8_PCU_IIR _MMIO(0x444e8)
8144#define GEN8_PCU_IER _MMIO(0x444ec)
Ben Widawskyabd58f02013-11-02 21:07:09 -07008145
Dhinakaran Pandiyandf0d28c2018-06-15 17:05:28 -07008146#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
8147#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
8148#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
8149#define GEN11_GU_MISC_IER _MMIO(0x444fc)
8150#define GEN11_GU_MISC_GSE (1 << 27)
8151
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008152#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
8153#define GEN11_MASTER_IRQ (1 << 31)
8154#define GEN11_PCU_IRQ (1 << 30)
Dhinakaran Pandiyandf0d28c2018-06-15 17:05:28 -07008155#define GEN11_GU_MISC_IRQ (1 << 29)
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008156#define GEN11_DISPLAY_IRQ (1 << 16)
8157#define GEN11_GT_DW_IRQ(x) (1 << (x))
8158#define GEN11_GT_DW1_IRQ (1 << 1)
8159#define GEN11_GT_DW0_IRQ (1 << 0)
8160
Paulo Zanoni22e26af2021-07-21 15:30:29 -07008161#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
Lucas De Marchi97b492f2020-07-13 11:23:19 -07008162#define DG1_MSTR_IRQ REG_BIT(31)
Paulo Zanoni22e26af2021-07-21 15:30:29 -07008163#define DG1_MSTR_TILE(t) REG_BIT(t)
Lucas De Marchi97b492f2020-07-13 11:23:19 -07008164
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008165#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
8166#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
8167#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
8168#define GEN11_DE_PCH_IRQ (1 << 23)
8169#define GEN11_DE_MISC_IRQ (1 << 22)
Dhinakaran Pandiyan121e7582018-06-15 17:05:29 -07008170#define GEN11_DE_HPD_IRQ (1 << 21)
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008171#define GEN11_DE_PORT_IRQ (1 << 20)
8172#define GEN11_DE_PIPE_C (1 << 18)
8173#define GEN11_DE_PIPE_B (1 << 17)
8174#define GEN11_DE_PIPE_A (1 << 16)
8175
Dhinakaran Pandiyan121e7582018-06-15 17:05:29 -07008176#define GEN11_DE_HPD_ISR _MMIO(0x44470)
8177#define GEN11_DE_HPD_IMR _MMIO(0x44474)
8178#define GEN11_DE_HPD_IIR _MMIO(0x44478)
8179#define GEN11_DE_HPD_IER _MMIO(0x4447c)
Ville Syrjälä5b76e862020-10-28 23:33:14 +02008180#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
8181#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
8182 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
8183 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
8184 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
8185 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
8186 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
8187#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
8188#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
8189 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
8190 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
8191 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
8192 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
8193 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
Dhinakaran Pandiyan121e7582018-06-15 17:05:29 -07008194
Dhinakaran Pandiyanb796b972018-06-15 17:05:30 -07008195#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
Dhinakaran Pandiyan121e7582018-06-15 17:05:29 -07008196#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
Ville Syrjälä5b76e862020-10-28 23:33:14 +02008197#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
8198#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
8199#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
8200#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
Dhinakaran Pandiyan121e7582018-06-15 17:05:29 -07008201
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008202#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
8203#define GEN11_CSME (31)
8204#define GEN11_GUNIT (28)
8205#define GEN11_GUC (25)
8206#define GEN11_WDPERF (20)
8207#define GEN11_KCR (19)
8208#define GEN11_GTPM (16)
8209#define GEN11_BCS (15)
8210#define GEN11_RCS0 (0)
8211
8212#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
8213#define GEN11_VECS(x) (31 - (x))
8214#define GEN11_VCS(x) (x)
8215
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07008216#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008217
8218#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
8219#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
8220#define GEN11_INTR_DATA_VALID (1 << 31)
Mika Kuoppalaf744dbc2018-04-06 12:31:45 +03008221#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
8222#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
8223#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
Daniele Ceraolo Spurio3d7b3032019-08-15 18:23:39 -07008224/* irq instances for OTHER_CLASS */
8225#define OTHER_GUC_INSTANCE 0
8226#define OTHER_GTPM_INSTANCE 1
Huang, Sean Z2ae09682021-09-24 12:14:44 -07008227#define OTHER_KCR_INSTANCE 4
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008228
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07008229#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008230
8231#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
8232#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
8233
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07008234#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008235
8236#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
8237#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
8238#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
8239#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
8240#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
8241#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
8242
8243#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
8244#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
8245#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
8246#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
John Harrison1b16b6b2021-07-23 10:42:12 -07008247#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
8248#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008249#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
John Harrison1b16b6b2021-07-23 10:42:12 -07008250#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02008251#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
8252#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
8253#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
8254#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
8255
Oscar Mateo54c52a82019-05-27 18:36:08 +00008256#define ENGINE1_MASK REG_GENMASK(31, 16)
8257#define ENGINE0_MASK REG_GENMASK(15, 0)
8258
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008259#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
Eric Anholt67e92af2010-11-06 14:53:33 -07008260/* Required on all Ironlake and Sandybridge according to the B-Spec. */
8261#define ILK_ELPIN_409_SELECT (1 << 25)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008262#define ILK_DPARB_GATE (1 << 22)
8263#define ILK_VSDPFD_FULL (1 << 21)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008264#define FUSE_STRAP _MMIO(0x42014)
Damien Lespiaue3589902014-02-07 19:12:50 +00008265#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
8266#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
8267#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
Gabriel Feceoru8c448ca2016-01-22 13:28:45 +02008268#define IVB_PIPE_C_DISABLE (1 << 28)
Damien Lespiaue3589902014-02-07 19:12:50 +00008269#define ILK_HDCP_DISABLE (1 << 25)
8270#define ILK_eDP_A_DISABLE (1 << 24)
8271#define HSW_CDCLK_LIMIT (1 << 24)
8272#define ILK_DESKTOP (1 << 23)
Ville Syrjäläb16c7ed2019-06-04 23:09:29 +03008273#define HSW_CPU_SSC_ENABLE (1 << 21)
Yuanhan Liu13982612010-12-15 15:42:31 +08008274
Ville Syrjälä86761782019-06-04 23:09:33 +03008275#define FUSE_STRAP3 _MMIO(0x42020)
8276#define HSW_REF_CLK_SELECT (1 << 1)
8277
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008278#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
Damien Lespiau231e54f2012-10-19 17:55:41 +01008279#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
8280#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
8281#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
8282#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
8283#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008284
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008285#define IVB_CHICKEN3 _MMIO(0x4200c)
Eric Anholt116ac8d2011-12-21 10:31:09 -08008286# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
8287# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
8288
José Roberto de Souzaa5523e22020-06-25 18:01:49 -07008289#define CHICKEN_PAR1_1 _MMIO(0x42080)
Tejas Upadhyay544021e2021-06-15 16:26:13 +05308290#define IGNORE_KVMR_PIPE_A REG_BIT(23)
Ville Syrjälä562ad8a2020-09-24 22:48:10 +03008291#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
José Roberto de Souzaa170f4f2020-08-10 10:41:44 -07008292#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
Ville Syrjälä93564042017-08-24 22:10:51 +03008293#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
José Roberto de Souzaa5523e22020-06-25 18:01:49 -07008294#define DPA_MASK_VBLANK_SRD (1 << 15)
8295#define FORCE_ARB_IDLE_PLANES (1 << 14)
8296#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
8297#define IGNORE_PSR2_HW_TRACKING (1 << 1)
Paulo Zanoni90a88642013-05-03 17:23:45 -03008298
Mika Kuoppala17e0adf2016-06-07 17:19:02 +03008299#define CHICKEN_PAR2_1 _MMIO(0x42090)
8300#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
8301
Ander Conselvan de Oliveiraf4f4b592017-02-22 08:34:29 +02008302#define CHICKEN_MISC_2 _MMIO(0x42084)
Ville Syrjälä562ad8a2020-09-24 22:48:10 +03008303#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
8304#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
Ander Conselvan de Oliveiraf4f4b592017-02-22 08:34:29 +02008305#define GLK_CL2_PWR_DOWN (1 << 12)
Paulo Zanoni746a5172017-07-14 14:52:28 -03008306#define GLK_CL1_PWR_DOWN (1 << 11)
8307#define GLK_CL0_PWR_DOWN (1 << 10)
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07008308
Praveen Paneri5654a162017-08-11 00:00:33 +05308309#define CHICKEN_MISC_4 _MMIO(0x4208c)
Ville Syrjälä2670ff52021-07-02 23:45:59 +03008310#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
8311#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
8312#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
Praveen Paneri5654a162017-08-11 00:00:33 +05308313
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07008314#define _CHICKEN_PIPESL_1_A 0x420b0
8315#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjäläb7a70532021-02-20 12:33:03 +02008316#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
8317#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
8318#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
8319#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
8320#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
8321#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
8322#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
8323#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
8324#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
8325#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02008326#define HSW_FBCQ_DIS (1 << 22)
8327#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ville Syrjäläd08df3b2021-09-30 22:09:42 +03008328#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
8329#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
8330#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
8331#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
8332#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008333#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07008334
Ville Syrjälä12c4d4c2019-10-24 15:21:36 +03008335#define _CHICKEN_TRANS_A 0x420c0
8336#define _CHICKEN_TRANS_B 0x420c4
8337#define _CHICKEN_TRANS_C 0x420c8
8338#define _CHICKEN_TRANS_EDP 0x420cc
Ville Syrjälä1d581dc2019-10-24 15:21:37 +03008339#define _CHICKEN_TRANS_D 0x420d8
Ville Syrjälä12c4d4c2019-10-24 15:21:36 +03008340#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
8341 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
8342 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
8343 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
Ville Syrjälä1d581dc2019-10-24 15:21:37 +03008344 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
8345 [TRANSCODER_D] = _CHICKEN_TRANS_D))
Matt Roper3c735532021-07-23 10:06:18 -07008346#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
8347#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
Lucas De Marchia4d082f2021-07-28 14:59:45 -07008348#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
Matt Roper3c735532021-07-23 10:06:18 -07008349#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
8350#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
José Roberto de Souza641dd822021-09-14 14:25:07 -07008351#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
Matt Roper3c735532021-07-23 10:06:18 -07008352#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
8353#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
8354#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
8355#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
8356#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
Nagaraju, Vathsalad86f0482017-01-13 00:31:31 +05308357
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008358#define DISP_ARB_CTL _MMIO(0x45000)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008359#define DISP_FBC_MEMORY_WAKE (1 << 31)
8360#define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
8361#define DISP_FBC_WM_DIS (1 << 15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008362#define DISP_ARB_CTL2 _MMIO(0x45004)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008363#define DISP_DATA_PARTITION_5_6 (1 << 6)
8364#define DISP_IPC_ENABLE (1 << 3)
José Roberto de Souza359d0ef2020-10-19 10:39:06 -07008365
Vandita Kulkarni247bdac2021-05-18 17:06:15 -07008366/*
8367 * The below are numbered starting from "S1" on gen11/gen12, but starting
Rodrigo Vivi7a279c12021-10-15 05:16:50 -04008368 * with display 13, the bspec switches to a 0-based numbering scheme
Vandita Kulkarni247bdac2021-05-18 17:06:15 -07008369 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
8370 * We'll just use the 0-based numbering here for all platforms since it's the
8371 * way things will be named by the hardware team going forward, plus it's more
8372 * consistent with how most of the rest of our registers are named.
8373 */
8374#define _DBUF_CTL_S0 0x45008
8375#define _DBUF_CTL_S1 0x44FE8
8376#define _DBUF_CTL_S2 0x44300
8377#define _DBUF_CTL_S3 0x44304
8378#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
8379 _DBUF_CTL_S0, \
8380 _DBUF_CTL_S1, \
8381 _DBUF_CTL_S2, \
8382 _DBUF_CTL_S3))
José Roberto de Souza359d0ef2020-10-19 10:39:06 -07008383#define DBUF_POWER_REQUEST REG_BIT(31)
8384#define DBUF_POWER_STATE REG_BIT(30)
8385#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
8386#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
Vandita Kulkarnif4dc0082021-05-18 17:06:17 -07008387#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
8388#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
José Roberto de Souza359d0ef2020-10-19 10:39:06 -07008389
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008390#define GEN7_MSG_CTL _MMIO(0x45010)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008391#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
8392#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
Matt Roper3fa01d62019-12-05 14:48:48 -08008393
Matt Roper62afef22020-06-05 19:57:34 -07008394#define _BW_BUDDY0_CTL 0x45130
8395#define _BW_BUDDY1_CTL 0x45140
8396#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
8397 _BW_BUDDY0_CTL, \
8398 _BW_BUDDY1_CTL))
Matt Roper3fa01d62019-12-05 14:48:48 -08008399#define BW_BUDDY_DISABLE REG_BIT(31)
Matt Roper87e04f72020-02-19 13:56:55 -08008400#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
Matt Roper62afef22020-06-05 19:57:34 -07008401#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
Matt Roper3fa01d62019-12-05 14:48:48 -08008402
Matt Roper62afef22020-06-05 19:57:34 -07008403#define _BW_BUDDY0_PAGE_MASK 0x45134
8404#define _BW_BUDDY1_PAGE_MASK 0x45144
8405#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
8406 _BW_BUDDY0_PAGE_MASK, \
8407 _BW_BUDDY1_PAGE_MASK))
Matt Roper3fa01d62019-12-05 14:48:48 -08008408
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008409#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008410#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08008411
Mika Kuoppala590e8ff2016-06-07 17:19:13 +03008412#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
José Roberto de Souza95568292021-10-28 16:04:49 -07008413#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
8414#define ICL_DELAY_PMRSP REG_BIT(22)
8415#define DISABLE_FLR_SRC REG_BIT(15)
8416#define MASK_WAKEMEM REG_BIT(13)
Mika Kuoppala590e8ff2016-06-07 17:19:13 +03008417
Matt Atwoodaf9e1032020-06-24 14:57:23 -07008418#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
8419#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
8420#define DCPR_MASK_LPMODE REG_BIT(26)
8421#define DCPR_SEND_RESP_IMM REG_BIT(25)
8422#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
8423
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008424#define SKL_DFSM _MMIO(0x51000)
José Roberto de Souza7a40aac2019-10-25 17:13:21 -07008425#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
José Roberto de Souza74393102019-10-25 17:13:20 -07008426#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
José Roberto de Souzaa20e26d2019-10-25 17:13:19 -07008427#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
8428#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
8429#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
8430#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
8431#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
José Roberto de Souzaee595882019-10-25 17:13:22 -07008432#define ICL_DFSM_DMC_DISABLE (1 << 23)
José Roberto de Souzaa20e26d2019-10-25 17:13:19 -07008433#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
8434#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
8435#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
8436#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
Lucas De Marchia4d082f2021-07-28 14:59:45 -07008437#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
Damien Lespiaua9419e82015-06-04 18:21:30 +01008438
Paulo Zanoni186a2772018-02-06 17:33:46 -02008439#define SKL_DSSM _MMIO(0x51004)
Paulo Zanoni186a2772018-02-06 17:33:46 -02008440#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
8441#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
8442#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
8443#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
Ville Syrjälä945f2672017-06-09 15:25:58 -07008444
Arun Siluverya78536e2016-01-21 21:43:53 +00008445#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008446#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
Arun Siluverya78536e2016-01-21 21:43:53 +00008447
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008448#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008449#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
8450#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
Damien Lespiau2caa3b22015-02-09 19:33:20 +00008451
Arun Siluvery2c8580e2016-01-21 21:43:50 +00008452#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
Mika Kuoppala99739f92019-10-15 18:44:43 +03008453#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
arun.siluvery@linux.intel.com6bb628552016-06-06 09:52:49 +01008454#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
Mika Kuoppala79bfa602019-10-15 18:44:47 +03008455#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
8456
Matt Roper645cc0b2021-11-02 15:25:10 -07008457#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20EC)
8458#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
8459
Arun Siluverye0f3fa02016-01-21 21:43:48 +00008460#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008461#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
Michał Winiarski5152def2017-10-03 21:34:46 +01008462#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
8463#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8464#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8465#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8466#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
Arun Siluverye0f3fa02016-01-21 21:43:48 +00008467
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08008468/* GEN7 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008469#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
Chris Wilson19f1f622020-06-11 09:01:36 +01008470 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
Oscar Mateob1f88822018-05-25 15:05:31 -07008471 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
8472
8473#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
8474 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
8475 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
8476 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
8477 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
8478
Tvrtko Ursulincbe3e1d2019-05-20 12:04:42 +01008479#define GEN8_L3CNTLREG _MMIO(0x7034)
8480 #define GEN8_ERRDETBCTRL (1 << 9)
8481
Stuart Summersda9427502020-10-14 12:19:34 -07008482#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
Matt Roper645cc0b2021-11-02 15:25:10 -07008483#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
8484#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
8485#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
8486#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
Kenneth Graunked71de142012-02-08 12:53:52 -08008487
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008488#define HIZ_CHICKEN _MMIO(0x7018)
Stuart Summersda9427502020-10-14 12:19:34 -07008489# define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
8490# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
8491# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
Kenneth Graunked60de812015-01-10 18:02:22 -08008492
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008493#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008494#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
Damien Lespiau183c6da2015-02-09 19:33:11 +00008495
Kenneth Graunkeab062632018-01-05 00:59:05 -08008496#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
Oscar Mateof63c7b42018-05-25 15:05:30 -07008497#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
Kenneth Graunkeab062632018-01-05 00:59:05 -08008498
Radhakrishna Sripada0c7d2ae2018-10-04 11:29:38 -07008499#define GEN7_SARCHKMD _MMIO(0xB000)
8500#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
Anuj Phogat71ffd492018-10-04 11:29:39 -07008501#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
Radhakrishna Sripada0c7d2ae2018-10-04 11:29:38 -07008502
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008503#define GEN7_L3SQCREG1 _MMIO(0xB010)
Ville Syrjälä031994e2014-01-22 21:32:46 +02008504#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
8505
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008506#define GEN8_L3SQCREG1 _MMIO(0xB100)
Imre Deak450174f2016-05-03 15:54:21 +03008507/*
8508 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8509 * Using the formula in BSpec leads to a hang, while the formula here works
8510 * fine and matches the formulas for all other platforms. A BSpec change
8511 * request has been filed to clarify this.
8512 */
Imre Deak36579cb2016-05-03 15:54:20 +03008513#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
8514#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
Oscar Mateo930a7842017-10-17 13:25:45 -07008515#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
Rodrigo Vivi51ce4db2015-03-31 16:03:21 -07008516
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008517#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
Chris Wilson1af84522014-02-14 22:34:43 +00008518#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008519#define GEN7_L3AGDIS (1 << 19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008520#define GEN7_L3CNTLREG2 _MMIO(0xB020)
8521#define GEN7_L3CNTLREG3 _MMIO(0xB024)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08008522
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008523#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
Oscar Mateo5215eef2018-05-08 14:29:33 -07008524#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
8525#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
8526#define GEN11_I2M_WRITE_DISABLE (1 << 28)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08008527
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008528#define GEN7_L3SQCREG4 _MMIO(0xb034)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008529#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
Jesse Barnes61939d92012-10-02 17:43:38 -05008530
Tvrtko Ursulinb83a3092019-07-17 19:06:24 +01008531#define GEN11_SCRATCH2 _MMIO(0xb140)
8532#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
8533
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008534#define GEN8_L3SQCREG4 _MMIO(0xb118)
Oscar Mateo5246ae42018-05-08 14:29:28 -07008535#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
8536#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
8537#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
Chris Wilson58586682021-01-25 22:01:52 +00008538#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00008539
Matt Roper212e6562021-11-02 15:25:11 -07008540#define GEN11_L3SQCREG5 _MMIO(0xb158)
8541#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
8542
8543#define XEHP_L3SCQREG7 _MMIO(0xb188)
8544#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
8545
Ben Widawsky63801f22013-12-12 17:26:03 -08008546/* GEN8 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008547#define HDC_CHICKEN0 _MMIO(0x7300)
Oscar Mateocc38cae2018-05-08 14:29:23 -07008548#define ICL_HDC_MODE _MMIO(0xE5F4)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008549#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
8550#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
8551#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
8552#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
8553#define HDC_FORCE_NON_COHERENT (1 << 4)
8554#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
Ben Widawsky63801f22013-12-12 17:26:03 -08008555
Matt Roper645cc0b2021-11-02 15:25:10 -07008556#define GEN12_HDC_CHICKEN0 _MMIO(0xE5F0)
8557#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
8558
8559#define SARB_CHICKEN1 _MMIO(0xe90c)
8560#define COMP_CKN_IN REG_GENMASK(30, 29)
8561
Arun Siluvery3669ab62016-01-21 21:43:49 +00008562#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
8563
Ben Widawsky38a39a72015-03-11 10:54:53 +02008564/* GEN9 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008565#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
Ben Widawsky38a39a72015-03-11 10:54:53 +02008566#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
8567
Michel Thierry0c79f9c2018-05-10 13:07:08 -07008568#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
8569#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
8570
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08008571/* WaCatErrorRejectionIssue */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008572#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008573#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08008574
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008575#define HSW_SCRATCH1 _MMIO(0xb038)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008576#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07008577
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008578#define BDW_SCRATCH1 _MMIO(0xb11c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008579#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
Damien Lespiau77719d22015-02-09 19:33:13 +00008580
Vandita Kulkarnie16a3752018-06-21 20:43:56 +05308581/*GEN11 chicken */
Aditya Swarup26eeea12019-03-06 18:14:12 -08008582#define _PIPEA_CHICKEN 0x70038
8583#define _PIPEB_CHICKEN 0x71038
8584#define _PIPEC_CHICKEN 0x72038
8585#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
8586 _PIPEB_CHICKEN)
Matt Roperba3b0492021-07-27 07:50:56 -07008587#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
8588#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
Matt Roper7cbea1b2021-11-16 09:48:15 -08008589#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
8590#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
8591#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
Vandita Kulkarnie16a3752018-06-21 20:43:56 +05308592
Matt Roper645cc0b2021-11-02 15:25:10 -07008593#define VFLSKPD _MMIO(0x62a8)
8594#define DIS_OVER_FETCH_CACHE REG_BIT(1)
8595#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
8596
Michel Thierryff690b22019-11-28 07:40:05 +05308597#define FF_MODE2 _MMIO(0x6604)
Clint Taylor84f9cbf2020-06-03 15:11:50 -07008598#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
8599#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
Michel Thierryff690b22019-11-28 07:40:05 +05308600#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
8601#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
8602
Zhenyu Wangb9055052009-06-05 15:38:38 +08008603/* PCH */
8604
Lucas De Marchidce88872018-07-27 12:36:47 -07008605#define PCH_DISPLAY_BASE 0xc0000u
8606
Adam Jackson23e81d62012-06-06 15:45:44 -04008607/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08008608#define SDE_AUDIO_POWER_D (1 << 27)
8609#define SDE_AUDIO_POWER_C (1 << 26)
8610#define SDE_AUDIO_POWER_B (1 << 25)
8611#define SDE_AUDIO_POWER_SHIFT (25)
8612#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
8613#define SDE_GMBUS (1 << 24)
8614#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
8615#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
8616#define SDE_AUDIO_HDCP_MASK (3 << 22)
8617#define SDE_AUDIO_TRANSB (1 << 21)
8618#define SDE_AUDIO_TRANSA (1 << 20)
8619#define SDE_AUDIO_TRANS_MASK (3 << 20)
8620#define SDE_POISON (1 << 19)
8621/* 18 reserved */
8622#define SDE_FDI_RXB (1 << 17)
8623#define SDE_FDI_RXA (1 << 16)
8624#define SDE_FDI_MASK (3 << 16)
8625#define SDE_AUXD (1 << 15)
8626#define SDE_AUXC (1 << 14)
8627#define SDE_AUXB (1 << 13)
8628#define SDE_AUX_MASK (7 << 13)
8629/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08008630#define SDE_CRT_HOTPLUG (1 << 11)
8631#define SDE_PORTD_HOTPLUG (1 << 10)
8632#define SDE_PORTC_HOTPLUG (1 << 9)
8633#define SDE_PORTB_HOTPLUG (1 << 8)
8634#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05008635#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
8636 SDE_SDVOB_HOTPLUG | \
8637 SDE_PORTB_HOTPLUG | \
8638 SDE_PORTC_HOTPLUG | \
8639 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08008640#define SDE_TRANSB_CRC_DONE (1 << 5)
8641#define SDE_TRANSB_CRC_ERR (1 << 4)
8642#define SDE_TRANSB_FIFO_UNDER (1 << 3)
8643#define SDE_TRANSA_CRC_DONE (1 << 2)
8644#define SDE_TRANSA_CRC_ERR (1 << 1)
8645#define SDE_TRANSA_FIFO_UNDER (1 << 0)
8646#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04008647
Anusha Srivatsa31604222018-06-26 13:52:23 -07008648/* south display engine interrupt: CPT - CNP */
Adam Jackson23e81d62012-06-06 15:45:44 -04008649#define SDE_AUDIO_POWER_D_CPT (1 << 31)
8650#define SDE_AUDIO_POWER_C_CPT (1 << 30)
8651#define SDE_AUDIO_POWER_B_CPT (1 << 29)
8652#define SDE_AUDIO_POWER_SHIFT_CPT 29
8653#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
8654#define SDE_AUXD_CPT (1 << 27)
8655#define SDE_AUXC_CPT (1 << 26)
8656#define SDE_AUXB_CPT (1 << 25)
8657#define SDE_AUX_MASK_CPT (7 << 25)
Xiong Zhang26951ca2015-08-17 15:55:50 +08008658#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
Ville Syrjälä74c0b392015-08-27 23:56:07 +03008659#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08008660#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
8661#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
8662#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04008663#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01008664#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01008665#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01008666 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01008667 SDE_PORTD_HOTPLUG_CPT | \
8668 SDE_PORTC_HOTPLUG_CPT | \
8669 SDE_PORTB_HOTPLUG_CPT)
Xiong Zhang26951ca2015-08-17 15:55:50 +08008670#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
8671 SDE_PORTD_HOTPLUG_CPT | \
8672 SDE_PORTC_HOTPLUG_CPT | \
Ville Syrjälä74c0b392015-08-27 23:56:07 +03008673 SDE_PORTB_HOTPLUG_CPT | \
8674 SDE_PORTA_HOTPLUG_SPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04008675#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03008676#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04008677#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
8678#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
8679#define SDE_FDI_RXC_CPT (1 << 8)
8680#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
8681#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
8682#define SDE_FDI_RXB_CPT (1 << 4)
8683#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
8684#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
8685#define SDE_FDI_RXA_CPT (1 << 0)
8686#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
8687 SDE_AUDIO_CP_REQ_B_CPT | \
8688 SDE_AUDIO_CP_REQ_A_CPT)
8689#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
8690 SDE_AUDIO_CP_CHG_B_CPT | \
8691 SDE_AUDIO_CP_CHG_A_CPT)
8692#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
8693 SDE_FDI_RXB_CPT | \
8694 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008695
Lucas De Marchi52dfdba2019-07-25 16:48:11 -07008696/* south display engine interrupt: ICP/TGP */
Anusha Srivatsa31604222018-06-26 13:52:23 -07008697#define SDE_GMBUS_ICP (1 << 23)
Ville Syrjälä97011352020-10-28 23:33:15 +02008698#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
Ville Syrjälä5f371a82020-10-28 23:33:13 +02008699#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
Ville Syrjäläe76ab2c2020-10-28 23:33:20 +02008700#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
8701 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
Ville Syrjälä5f371a82020-10-28 23:33:13 +02008702 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
8703 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
Ville Syrjäläe76ab2c2020-10-28 23:33:20 +02008704#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
Ville Syrjälä97011352020-10-28 23:33:15 +02008705 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
8706 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
8707 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
8708 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
8709 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
Anusha Srivatsa31604222018-06-26 13:52:23 -07008710
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008711#define SDEISR _MMIO(0xc4000)
8712#define SDEIMR _MMIO(0xc4004)
8713#define SDEIIR _MMIO(0xc4008)
8714#define SDEIER _MMIO(0xc400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008715
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008716#define SERR_INT _MMIO(0xc4040)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008717#define SERR_INT_POISON (1 << 31)
8718#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
Paulo Zanoni86642812013-04-12 17:57:57 -03008719
Zhenyu Wangb9055052009-06-05 15:38:38 +08008720/* digital port hotplug */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008721#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
Ville Syrjälä195baa02015-08-27 23:56:00 +03008722#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05308723#define BXT_DDIA_HPD_INVERT (1 << 27)
Ville Syrjälä195baa02015-08-27 23:56:00 +03008724#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
8725#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
8726#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
8727#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008728#define PORTD_HOTPLUG_ENABLE (1 << 20)
8729#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
8730#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
8731#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
8732#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
8733#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
8734#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
Damien Lespiaub6965192012-12-13 16:08:59 +00008735#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
8736#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
8737#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008738#define PORTC_HOTPLUG_ENABLE (1 << 12)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05308739#define BXT_DDIC_HPD_INVERT (1 << 11)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008740#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
8741#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
8742#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
8743#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
8744#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
8745#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
Damien Lespiaub6965192012-12-13 16:08:59 +00008746#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
8747#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
8748#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008749#define PORTB_HOTPLUG_ENABLE (1 << 4)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05308750#define BXT_DDIB_HPD_INVERT (1 << 3)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008751#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
8752#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
8753#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
8754#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
8755#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
8756#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
Damien Lespiaub6965192012-12-13 16:08:59 +00008757#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
8758#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
8759#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05308760#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
8761 BXT_DDIB_HPD_INVERT | \
8762 BXT_DDIC_HPD_INVERT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008763
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008764#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03008765#define PORTE_HOTPLUG_ENABLE (1 << 4)
8766#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
Xiong Zhang26951ca2015-08-17 15:55:50 +08008767#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
8768#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
8769#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
8770
Anusha Srivatsa31604222018-06-26 13:52:23 -07008771/* This register is a reuse of PCH_PORT_HOTPLUG register. The
8772 * functionality covered in PCH_PORT_HOTPLUG is split into
8773 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8774 */
8775
Lucas De Marchied3126f2019-08-29 14:15:23 -07008776#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
Ville Syrjälä5f371a82020-10-28 23:33:13 +02008777#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
8778#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8779#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
8780#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
8781#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
8782#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
Anusha Srivatsa31604222018-06-26 13:52:23 -07008783
8784#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
Ville Syrjälä97011352020-10-28 23:33:15 +02008785#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
8786#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
8787#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
Matt Roperf49108d2019-11-27 14:13:14 -08008788
8789#define SHPD_FILTER_CNT _MMIO(0xc4038)
8790#define SHPD_FILTER_CNT_500_ADJ 0x001D9
8791
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008792#define _PCH_DPLL_A 0xc6014
8793#define _PCH_DPLL_B 0xc6018
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07008794#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008795
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008796#define _PCH_FPA0 0xc6040
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008797#define FP_CB_TUNE (0x3 << 22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008798#define _PCH_FPA1 0xc6044
8799#define _PCH_FPB0 0xc6048
8800#define _PCH_FPB1 0xc604c
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07008801#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8802#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008803
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008804#define PCH_DPLL_TEST _MMIO(0xc606c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008805
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008806#define PCH_DREF_CONTROL _MMIO(0xC6200)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008807#define DREF_CONTROL_MASK 0x7fc3
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008808#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
8809#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
8810#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
8811#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
8812#define DREF_SSC_SOURCE_DISABLE (0 << 11)
8813#define DREF_SSC_SOURCE_ENABLE (2 << 11)
8814#define DREF_SSC_SOURCE_MASK (3 << 11)
8815#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
8816#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
8817#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
8818#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
8819#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
8820#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
8821#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
8822#define DREF_SSC4_DOWNSPREAD (0 << 6)
8823#define DREF_SSC4_CENTERSPREAD (1 << 6)
8824#define DREF_SSC1_DISABLE (0 << 1)
8825#define DREF_SSC1_ENABLE (1 << 1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008826#define DREF_SSC4_DISABLE (0)
8827#define DREF_SSC4_ENABLE (1)
8828
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008829#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008830#define FDL_TP1_TIMER_SHIFT 12
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008831#define FDL_TP1_TIMER_MASK (3 << 12)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008832#define FDL_TP2_TIMER_SHIFT 10
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008833#define FDL_TP2_TIMER_MASK (3 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008834#define RAWCLK_FREQ_MASK 0x3ff
Rodrigo Vivi9d81a992017-06-02 13:06:41 -07008835#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
8836#define CNP_RAWCLK_DIV(div) ((div) << 16)
8837#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
Paulo Zanoni228a5cf2018-11-12 15:23:12 -08008838#define CNP_RAWCLK_DEN(den) ((den) << 26)
Anusha Srivatsa4ef99ab2018-01-11 16:00:06 -02008839#define ICP_RAWCLK_NUM(num) ((num) << 11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008840
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008841#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008842
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008843#define PCH_SSC4_PARMS _MMIO(0xc6210)
8844#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
Zhenyu Wangb9055052009-06-05 15:38:38 +08008845
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008846#define PCH_DPLL_SEL _MMIO(0xc7000)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008847#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
Daniel Vetter11887392013-06-05 13:34:09 +02008848#define TRANS_DPLLA_SEL(pipe) 0
Ville Syrjälä68d97532015-09-18 20:03:39 +03008849#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08008850
Zhenyu Wangb9055052009-06-05 15:38:38 +08008851/* transcoder */
8852
Daniel Vetter275f01b22013-05-03 11:49:47 +02008853#define _PCH_TRANS_HTOTAL_A 0xe0000
8854#define TRANS_HTOTAL_SHIFT 16
8855#define TRANS_HACTIVE_SHIFT 0
8856#define _PCH_TRANS_HBLANK_A 0xe0004
8857#define TRANS_HBLANK_END_SHIFT 16
8858#define TRANS_HBLANK_START_SHIFT 0
8859#define _PCH_TRANS_HSYNC_A 0xe0008
8860#define TRANS_HSYNC_END_SHIFT 16
8861#define TRANS_HSYNC_START_SHIFT 0
8862#define _PCH_TRANS_VTOTAL_A 0xe000c
8863#define TRANS_VTOTAL_SHIFT 16
8864#define TRANS_VACTIVE_SHIFT 0
8865#define _PCH_TRANS_VBLANK_A 0xe0010
8866#define TRANS_VBLANK_END_SHIFT 16
8867#define TRANS_VBLANK_START_SHIFT 0
8868#define _PCH_TRANS_VSYNC_A 0xe0014
Paulo Zanoniaf7187b2018-06-12 16:56:53 -07008869#define TRANS_VSYNC_END_SHIFT 16
Daniel Vetter275f01b22013-05-03 11:49:47 +02008870#define TRANS_VSYNC_START_SHIFT 0
8871#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08008872
Daniel Vettere3b95f12013-05-03 11:49:49 +02008873#define _PCH_TRANSA_DATA_M1 0xe0030
8874#define _PCH_TRANSA_DATA_N1 0xe0034
8875#define _PCH_TRANSA_DATA_M2 0xe0038
8876#define _PCH_TRANSA_DATA_N2 0xe003c
8877#define _PCH_TRANSA_LINK_M1 0xe0040
8878#define _PCH_TRANSA_LINK_N1 0xe0044
8879#define _PCH_TRANSA_LINK_M2 0xe0048
8880#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08008881
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03008882/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07008883#define _VIDEO_DIP_CTL_A 0xe0200
8884#define _VIDEO_DIP_DATA_A 0xe0208
8885#define _VIDEO_DIP_GCP_A 0xe0210
Ville Syrjälä6d674152015-05-05 17:06:20 +03008886#define GCP_COLOR_INDICATION (1 << 2)
8887#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8888#define GCP_AV_MUTE (1 << 0)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07008889
8890#define _VIDEO_DIP_CTL_B 0xe1200
8891#define _VIDEO_DIP_DATA_B 0xe1208
8892#define _VIDEO_DIP_GCP_B 0xe1210
8893
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008894#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8895#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8896#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07008897
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03008898/* Per-transcoder DIP controls (VLV) */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008899#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8900#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8901#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008902
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008903#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8904#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8905#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008906
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008907#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8908#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8909#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03008910
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008911#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008912 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008913 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008914#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008915 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008916 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008917#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008918 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008919 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07008920
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03008921/* Haswell DIP controls */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008922
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008923#define _HSW_VIDEO_DIP_CTL_A 0x60200
8924#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8925#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8926#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8927#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8928#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
Ville Syrjälä44b42eb2019-05-17 21:52:25 +05308929#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008930#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8931#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8932#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8933#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8934#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8935#define _HSW_VIDEO_DIP_GCP_A 0x60210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03008936
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008937#define _HSW_VIDEO_DIP_CTL_B 0x61200
8938#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8939#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8940#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8941#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8942#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
Ville Syrjälä44b42eb2019-05-17 21:52:25 +05308943#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008944#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8945#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8946#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8947#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8948#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8949#define _HSW_VIDEO_DIP_GCP_B 0x61210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03008950
Anusha Srivatsa7af2be62018-07-17 14:10:58 -07008951/* Icelake PPS_DATA and _ECC DIP Registers.
8952 * These are available for transcoders B,C and eDP.
8953 * Adding the _A so as to reuse the _MMIO_TRANS2
8954 * definition, with which it offsets to the right location.
8955 */
8956
8957#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8958#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8959#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8960#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8961
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008962#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
Ville Syrjälä5cb3c1a2019-02-25 19:40:58 +02008963#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008964#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8965#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8966#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
Ville Syrjälä5cb3c1a2019-02-25 19:40:58 +02008967#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008968#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
Ville Syrjälä44b42eb2019-05-17 21:52:25 +05308969#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
Anusha Srivatsa7af2be62018-07-17 14:10:58 -07008970#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8971#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03008972
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008973#define _HSW_STEREO_3D_CTL_A 0x70020
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07008974#define S3D_ENABLE (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008975#define _HSW_STEREO_3D_CTL_B 0x71020
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03008976
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008977#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03008978
Daniel Vetter275f01b22013-05-03 11:49:47 +02008979#define _PCH_TRANS_HTOTAL_B 0xe1000
8980#define _PCH_TRANS_HBLANK_B 0xe1004
8981#define _PCH_TRANS_HSYNC_B 0xe1008
8982#define _PCH_TRANS_VTOTAL_B 0xe100c
8983#define _PCH_TRANS_VBLANK_B 0xe1010
8984#define _PCH_TRANS_VSYNC_B 0xe1014
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008985#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08008986
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008987#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8988#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8989#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8990#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8991#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8992#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8993#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01008994
Daniel Vettere3b95f12013-05-03 11:49:49 +02008995#define _PCH_TRANSB_DATA_M1 0xe1030
8996#define _PCH_TRANSB_DATA_N1 0xe1034
8997#define _PCH_TRANSB_DATA_M2 0xe1038
8998#define _PCH_TRANSB_DATA_N2 0xe103c
8999#define _PCH_TRANSB_LINK_M1 0xe1040
9000#define _PCH_TRANSB_LINK_N1 0xe1044
9001#define _PCH_TRANSB_LINK_M2 0xe1048
9002#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08009003
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009004#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
9005#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
9006#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
9007#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
9008#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
9009#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
9010#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
9011#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08009012
Daniel Vetterab9412b2013-05-03 11:49:46 +02009013#define _PCH_TRANSACONF 0xf0008
9014#define _PCH_TRANSBCONF 0xf1008
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009015#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
9016#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009017#define TRANS_DISABLE (0 << 31)
9018#define TRANS_ENABLE (1 << 31)
9019#define TRANS_STATE_MASK (1 << 30)
9020#define TRANS_STATE_DISABLE (0 << 30)
9021#define TRANS_STATE_ENABLE (1 << 30)
Ville Syrjäläcc7a4cf2019-10-24 15:21:38 +03009022#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
9023#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009024#define TRANS_INTERLACE_MASK (7 << 21)
9025#define TRANS_PROGRESSIVE (0 << 21)
9026#define TRANS_INTERLACED (3 << 21)
9027#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
9028#define TRANS_8BPC (0 << 5)
9029#define TRANS_10BPC (1 << 5)
9030#define TRANS_6BPC (2 << 5)
9031#define TRANS_12BPC (3 << 5)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009032
Daniel Vetterce401412012-10-31 22:52:30 +01009033#define _TRANSA_CHICKEN1 0xf0060
9034#define _TRANSB_CHICKEN1 0xf1060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009035#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009036#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
9037#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07009038#define _TRANSA_CHICKEN2 0xf0064
9039#define _TRANSB_CHICKEN2 0xf1064
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009040#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009041#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
9042#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
9043#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
Ville Syrjäläcc7a4cf2019-10-24 15:21:38 +03009044#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009045#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
9046#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07009047
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009048#define SOUTH_CHICKEN1 _MMIO(0xc2000)
Jesse Barnes291427f2011-07-29 12:42:37 -07009049#define FDIA_PHASE_SYNC_SHIFT_OVR 19
9050#define FDIA_PHASE_SYNC_SHIFT_EN 18
Clinton A Taylorb18c1eb2020-10-21 01:20:30 -07009051#define INVERT_DDID_HPD (1 << 18)
9052#define INVERT_DDIC_HPD (1 << 17)
9053#define INVERT_DDIB_HPD (1 << 16)
9054#define INVERT_DDIA_HPD (1 << 15)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009055#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
9056#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
Daniel Vetter01a415f2012-10-27 15:58:40 +02009057#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Rodrigo Vivi3b92e262017-09-19 14:57:03 -07009058#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
9059#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
Matt Roper9b2383a2020-05-01 14:37:01 -07009060#define SBCLK_RUN_REFCLK_DIS (1 << 7)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009061#define SPT_PWM_GRANULARITY (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009062#define SOUTH_CHICKEN2 _MMIO(0xc2004)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009063#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
9064#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
9065#define LPT_PWM_GRANULARITY (1 << 5)
9066#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07009067
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009068#define _FDI_RXA_CHICKEN 0xc200c
9069#define _FDI_RXB_CHICKEN 0xc2010
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009070#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
9071#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009072#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009073
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009074#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009075#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
9076#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
9077#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
José Roberto de Souzac7460632020-07-27 09:47:29 -07009078#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009079#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
9080#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
9081#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
Jesse Barnes382b0932010-10-07 16:01:25 -07009082
Zhenyu Wangb9055052009-06-05 15:38:38 +08009083/* CPU: FDI_TX */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009084#define _FDI_TXA_CTL 0x60100
9085#define _FDI_TXB_CTL 0x61100
9086#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009087#define FDI_TX_DISABLE (0 << 31)
9088#define FDI_TX_ENABLE (1 << 31)
9089#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
9090#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
9091#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
9092#define FDI_LINK_TRAIN_NONE (3 << 28)
9093#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
9094#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
9095#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
9096#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
9097#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
9098#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
9099#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
9100#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009101/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
9102 SNB has different settings. */
9103/* SNB A-stepping */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009104#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
9105#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
9106#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
9107#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009108/* SNB B-stepping */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009109#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
9110#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
9111#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
9112#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
9113#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009114#define FDI_DP_PORT_WIDTH_SHIFT 19
9115#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
9116#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009117#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05009118/* Ironlake: hardwired to 1 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009119#define FDI_TX_PLL_ENABLE (1 << 14)
Jesse Barnes357555c2011-04-28 15:09:55 -07009120
9121/* Ivybridge has different bits for lolz */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009122#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
9123#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
9124#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
9125#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
Jesse Barnes357555c2011-04-28 15:09:55 -07009126
Zhenyu Wangb9055052009-06-05 15:38:38 +08009127/* both Tx and Rx */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009128#define FDI_COMPOSITE_SYNC (1 << 11)
9129#define FDI_LINK_TRAIN_AUTO (1 << 10)
9130#define FDI_SCRAMBLING_ENABLE (0 << 7)
9131#define FDI_SCRAMBLING_DISABLE (1 << 7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009132
9133/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08009134#define _FDI_RXA_CTL 0xf000c
9135#define _FDI_RXB_CTL 0xf100c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009136#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009137#define FDI_RX_ENABLE (1 << 31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009138/* train, dp width same as FDI_TX */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009139#define FDI_FS_ERRC_ENABLE (1 << 27)
9140#define FDI_FE_ERRC_ENABLE (1 << 26)
9141#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
9142#define FDI_8BPC (0 << 16)
9143#define FDI_10BPC (1 << 16)
9144#define FDI_6BPC (2 << 16)
9145#define FDI_12BPC (3 << 16)
9146#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
9147#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
9148#define FDI_RX_PLL_ENABLE (1 << 13)
9149#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
9150#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
9151#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
9152#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
9153#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
9154#define FDI_PCDCLK (1 << 4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009155/* CPT */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009156#define FDI_AUTO_TRAINING (1 << 10)
9157#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
9158#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
9159#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
9160#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
9161#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009162
Paulo Zanoni04945642012-11-01 21:00:59 -02009163#define _FDI_RXA_MISC 0xf0010
9164#define _FDI_RXB_MISC 0xf1010
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009165#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
9166#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
9167#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
9168#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
9169#define FDI_RX_TP1_TO_TP2_48 (2 << 20)
9170#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
9171#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009172#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
Paulo Zanoni04945642012-11-01 21:00:59 -02009173
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009174#define _FDI_RXA_TUSIZE1 0xf0030
9175#define _FDI_RXA_TUSIZE2 0xf0038
9176#define _FDI_RXB_TUSIZE1 0xf1030
9177#define _FDI_RXB_TUSIZE2 0xf1038
9178#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
9179#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009180
9181/* FDI_RX interrupt register format */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009182#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
9183#define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
9184#define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
9185#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
9186#define FDI_RX_FS_CODE_ERR (1 << 6)
9187#define FDI_RX_FE_CODE_ERR (1 << 5)
9188#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
9189#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
9190#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
9191#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
9192#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009193
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009194#define _FDI_RXA_IIR 0xf0014
9195#define _FDI_RXA_IMR 0xf0018
9196#define _FDI_RXB_IIR 0xf1014
9197#define _FDI_RXB_IMR 0xf1018
9198#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
9199#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009200
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009201#define FDI_PLL_CTL_1 _MMIO(0xfe000)
9202#define FDI_PLL_CTL_2 _MMIO(0xfe004)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009203
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009204#define PCH_LVDS _MMIO(0xe1180)
Zhenyu Wangb9055052009-06-05 15:38:38 +08009205#define LVDS_DETECTED (1 << 1)
9206
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009207#define _PCH_DP_B 0xe4100
9208#define PCH_DP_B _MMIO(_PCH_DP_B)
Ville Syrjälä750a9512015-11-11 20:34:12 +02009209#define _PCH_DPB_AUX_CH_CTL 0xe4110
9210#define _PCH_DPB_AUX_CH_DATA1 0xe4114
9211#define _PCH_DPB_AUX_CH_DATA2 0xe4118
9212#define _PCH_DPB_AUX_CH_DATA3 0xe411c
9213#define _PCH_DPB_AUX_CH_DATA4 0xe4120
9214#define _PCH_DPB_AUX_CH_DATA5 0xe4124
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009215
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009216#define _PCH_DP_C 0xe4200
9217#define PCH_DP_C _MMIO(_PCH_DP_C)
Ville Syrjälä750a9512015-11-11 20:34:12 +02009218#define _PCH_DPC_AUX_CH_CTL 0xe4210
9219#define _PCH_DPC_AUX_CH_DATA1 0xe4214
9220#define _PCH_DPC_AUX_CH_DATA2 0xe4218
9221#define _PCH_DPC_AUX_CH_DATA3 0xe421c
9222#define _PCH_DPC_AUX_CH_DATA4 0xe4220
9223#define _PCH_DPC_AUX_CH_DATA5 0xe4224
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009224
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009225#define _PCH_DP_D 0xe4300
9226#define PCH_DP_D _MMIO(_PCH_DP_D)
Ville Syrjälä750a9512015-11-11 20:34:12 +02009227#define _PCH_DPD_AUX_CH_CTL 0xe4310
9228#define _PCH_DPD_AUX_CH_DATA1 0xe4314
9229#define _PCH_DPD_AUX_CH_DATA2 0xe4318
9230#define _PCH_DPD_AUX_CH_DATA3 0xe431c
9231#define _PCH_DPD_AUX_CH_DATA4 0xe4320
9232#define _PCH_DPD_AUX_CH_DATA5 0xe4324
9233
Ville Syrjäläbdabdb62018-02-22 20:10:30 +02009234#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
9235#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009236
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009237/* CPT */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02009238#define _TRANS_DP_CTL_A 0xe0300
9239#define _TRANS_DP_CTL_B 0xe1300
9240#define _TRANS_DP_CTL_C 0xe2300
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009241#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009242#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
Ville Syrjäläf67dc6d2018-05-18 18:29:26 +03009243#define TRANS_DP_PORT_SEL_MASK (3 << 29)
9244#define TRANS_DP_PORT_SEL_NONE (3 << 29)
9245#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009246#define TRANS_DP_AUDIO_ONLY (1 << 26)
9247#define TRANS_DP_ENH_FRAMING (1 << 18)
9248#define TRANS_DP_8BPC (0 << 9)
9249#define TRANS_DP_10BPC (1 << 9)
9250#define TRANS_DP_6BPC (2 << 9)
9251#define TRANS_DP_12BPC (3 << 9)
9252#define TRANS_DP_BPC_MASK (3 << 9)
9253#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009254#define TRANS_DP_VSYNC_ACTIVE_LOW 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009255#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009256#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009257#define TRANS_DP_SYNC_MASK (3 << 3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009258
Jani Nikula59821ed2021-08-23 19:18:08 +03009259#define _TRANS_DP2_CTL_A 0x600a0
9260#define _TRANS_DP2_CTL_B 0x610a0
9261#define _TRANS_DP2_CTL_C 0x620a0
9262#define _TRANS_DP2_CTL_D 0x630a0
9263#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
9264#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
9265#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
9266#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
9267
Jani Nikula1db18262021-08-23 19:18:10 +03009268#define _TRANS_DP2_VFREQHIGH_A 0x600a4
9269#define _TRANS_DP2_VFREQHIGH_B 0x610a4
9270#define _TRANS_DP2_VFREQHIGH_C 0x620a4
9271#define _TRANS_DP2_VFREQHIGH_D 0x630a4
9272#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
9273#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
9274#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
9275
9276#define _TRANS_DP2_VFREQLOW_A 0x600a8
9277#define _TRANS_DP2_VFREQLOW_B 0x610a8
9278#define _TRANS_DP2_VFREQLOW_C 0x620a8
9279#define _TRANS_DP2_VFREQLOW_D 0x630a8
9280#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
9281
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009282/* SNB eDP training params */
9283/* SNB A-stepping */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009284#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
9285#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
9286#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
9287#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009288/* SNB B-stepping */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009289#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
9290#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
9291#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
9292#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
9293#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
9294#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08009295
Keith Packard1a2eb462011-11-16 16:26:07 -08009296/* IVB */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009297#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
9298#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
9299#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
9300#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
9301#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
9302#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
9303#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
Keith Packard1a2eb462011-11-16 16:26:07 -08009304
9305/* legacy values */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009306#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
9307#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
9308#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
9309#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
9310#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
Keith Packard1a2eb462011-11-16 16:26:07 -08009311
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009312#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
Keith Packard1a2eb462011-11-16 16:26:07 -08009313
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009314#define VLV_PMWGICZ _MMIO(0x1300a4)
Imre Deak9e72b462014-05-05 15:13:55 +03009315
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05309316#define RC6_LOCATION _MMIO(0xD40)
9317#define RC6_CTX_IN_DRAM (1 << 0)
9318#define RC6_CTX_BASE _MMIO(0xD48)
9319#define RC6_CTX_BASE_MASK 0xFFFFFFF0
9320#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
9321#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
9322#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
9323#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
9324#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
9325#define IDLE_TIME_MASK 0xFFFFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009326#define FORCEWAKE _MMIO(0xA18C)
9327#define FORCEWAKE_VLV _MMIO(0x1300b0)
9328#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
9329#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
9330#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
9331#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
9332#define FORCEWAKE_ACK _MMIO(0x130090)
9333#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
Imre Deak981a5ae2014-04-14 20:24:22 +03009334#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
9335#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
9336#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
9337
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009338#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
Imre Deak981a5ae2014-04-14 20:24:22 +03009339#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
9340#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
9341#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
9342#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009343#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
9344#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
Daniele Ceraolo Spurioa89a70a2018-03-02 18:15:01 +02009345#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
9346#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009347#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
Matt Roper55e3c172020-10-09 12:44:40 -07009348#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009349#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
Daniele Ceraolo Spurioa89a70a2018-03-02 18:15:01 +02009350#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
9351#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009352#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
Matt Roper55e3c172020-10-09 12:44:40 -07009353#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
Mika Kuoppala71306302017-11-02 11:48:36 +02009354#define FORCEWAKE_KERNEL BIT(0)
9355#define FORCEWAKE_USER BIT(1)
9356#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009357#define FORCEWAKE_MT_ACK _MMIO(0x130040)
9358#define ECOBUS _MMIO(0xa180)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009359#define FORCEWAKE_MT_ENABLE (1 << 5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009360#define VLV_SPAREG2H _MMIO(0xA194)
Akash Goelf2dd7572016-06-27 20:10:01 +05309361#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
9362#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
9363#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
Chris Wilson8fd26852010-12-08 18:40:43 +00009364
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009365#define GTFIFODBG _MMIO(0x120000)
Ville Syrjälä297b32e2016-04-13 21:09:30 +03009366#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
9367#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009368#define GT_FIFO_SBDROPERR (1 << 6)
9369#define GT_FIFO_BLOBDROPERR (1 << 5)
9370#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
9371#define GT_FIFO_DROPERR (1 << 3)
9372#define GT_FIFO_OVFERR (1 << 2)
9373#define GT_FIFO_IAWRERR (1 << 1)
9374#define GT_FIFO_IARDERR (1 << 0)
Ben Widawskydd202c62012-02-09 10:15:18 +01009375
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009376#define GTFIFOCTL _MMIO(0x120008)
Ville Syrjälä46520e22013-11-14 02:00:00 +02009377#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01009378#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Deepak Sa04f90a2015-04-16 08:51:28 +05309379#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
9380#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
Chris Wilson91355832011-03-04 19:22:40 +00009381
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009382#define HSW_IDICR _MMIO(0x9008)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07009383#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
Mika Kuoppala3accaf72016-04-13 17:26:43 +03009384#define HSW_EDRAM_CAP _MMIO(0x120010)
Damien Lespiau2db59d52015-02-03 14:25:14 +00009385#define EDRAM_ENABLED 0x1
Mika Kuoppalac02e85a2016-04-13 17:26:44 +03009386#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
9387#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
9388#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07009389
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009390#define GEN6_UCGCTL1 _MMIO(0x9400)
Mika Kuoppala8aeb7f62016-06-07 17:19:05 +03009391# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03009392# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02009393# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02009394# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02009395
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009396#define GEN6_UCGCTL2 _MMIO(0x9404)
Damien Lespiauf9fc42f2015-02-26 18:20:39 +00009397# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
Jesse Barnes0f846f82012-06-14 11:04:47 -07009398# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07009399# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08009400# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08009401# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08009402# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08009403
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009404#define GEN6_UCGCTL3 _MMIO(0x9408)
Robert Braggd7965152016-11-07 19:49:52 +00009405# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
Imre Deak9e72b462014-05-05 15:13:55 +03009406
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009407#define GEN7_UCGCTL4 _MMIO(0x940c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009408#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
9409#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
Jesse Barnese3f33d42012-06-14 11:04:50 -07009410
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009411#define GEN6_RCGCTL1 _MMIO(0x9410)
9412#define GEN6_RCGCTL2 _MMIO(0x9414)
9413#define GEN6_RSTCTL _MMIO(0x9420)
Imre Deak9e72b462014-05-05 15:13:55 +03009414
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009415#define GEN8_UCGCTL6 _MMIO(0x9430)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009416#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
9417#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
9418#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02009419
Matt Roper645cc0b2021-11-02 15:25:10 -07009420#define UNSLCGCTL9430 _MMIO(0x9430)
9421#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
9422
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009423#define GEN6_GFXPAUSE _MMIO(0xA000)
9424#define GEN6_RPNSWREQ _MMIO(0xA008)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009425#define GEN6_TURBO_DISABLE (1 << 31)
9426#define GEN6_FREQUENCY(x) ((x) << 25)
9427#define HSW_FREQUENCY(x) ((x) << 24)
9428#define GEN9_FREQUENCY(x) ((x) << 23)
9429#define GEN6_OFFSET(x) ((x) << 19)
9430#define GEN6_AGGRESSIVE_TURBO (0 << 15)
Vinay Belgaumkar41e5c172021-07-30 13:21:17 -07009431#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23
Vinay Belgaumkar1c40d402021-12-16 15:30:22 -08009432#define GEN9_IGNORE_SLICE_RATIO (0 << 0)
Vinay Belgaumkar41e5c172021-07-30 13:21:17 -07009433
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009434#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
9435#define GEN6_RC_CONTROL _MMIO(0xA090)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009436#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
9437#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
9438#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
9439#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
9440#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
9441#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
9442#define GEN7_RC_CTL_TO_MODE (1 << 28)
9443#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
9444#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009445#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
9446#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
9447#define GEN6_RPSTAT1 _MMIO(0xA01C)
Jesse Barnesccab5c82011-01-18 15:49:25 -08009448#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08009449#define HSW_CAGF_SHIFT 7
Akash Goelde43ae92015-03-06 11:07:14 +05309450#define GEN9_CAGF_SHIFT 23
Jesse Barnesccab5c82011-01-18 15:49:25 -08009451#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08009452#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Akash Goelde43ae92015-03-06 11:07:14 +05309453#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009454#define GEN6_RP_CONTROL _MMIO(0xA024)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009455#define GEN6_RP_MEDIA_TURBO (1 << 11)
9456#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
9457#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
9458#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
9459#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
9460#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
9461#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
9462#define GEN6_RP_ENABLE (1 << 7)
9463#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
9464#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
9465#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
9466#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
9467#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
Vinay Belgaumkar1c40d402021-12-16 15:30:22 -08009468#define GEN6_RPSWCTL_SHIFT 9
9469#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
9470#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009471#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
9472#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
9473#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
Chris Wilson7466c292016-08-15 09:49:33 +01009474#define GEN6_RP_EI_MASK 0xffffff
9475#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009476#define GEN6_RP_CUR_UP _MMIO(0xA054)
Chris Wilson7466c292016-08-15 09:49:33 +01009477#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009478#define GEN6_RP_PREV_UP _MMIO(0xA058)
9479#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
Chris Wilson7466c292016-08-15 09:49:33 +01009480#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009481#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
9482#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
9483#define GEN6_RP_UP_EI _MMIO(0xA068)
9484#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
9485#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
9486#define GEN6_RPDEUHWTC _MMIO(0xA080)
9487#define GEN6_RPDEUC _MMIO(0xA084)
9488#define GEN6_RPDEUCSW _MMIO(0xA088)
9489#define GEN6_RC_STATE _MMIO(0xA094)
Imre Deakfc619842016-06-29 19:13:55 +03009490#define RC_SW_TARGET_STATE_SHIFT 16
9491#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009492#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
9493#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
9494#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
Rodrigo Vivi0aab2012017-10-23 15:46:12 -07009495#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009496#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
9497#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
9498#define GEN6_RC_SLEEP _MMIO(0xA0B0)
9499#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
9500#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
9501#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
9502#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
9503#define VLV_RCEDATA _MMIO(0xA0BC)
9504#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
9505#define GEN6_PMINTRMSK _MMIO(0xA168)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009506#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
9507#define ARAT_EXPIRED_INTRMSK (1 << 9)
Imre Deakfc619842016-06-29 19:13:55 +03009508#define GEN8_MISC_CTRL0 _MMIO(0xA180)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009509#define VLV_PWRDWNUPCTL _MMIO(0xA294)
9510#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
9511#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
9512#define GEN9_PG_ENABLE _MMIO(0xA210)
Rodrigo Vivi695dc552020-11-11 09:09:36 -05009513#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
9514#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
9515#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
9516#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
9517#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
Imre Deakfc619842016-06-29 19:13:55 +03009518#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
9519#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
9520#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
Chris Wilson8fd26852010-12-08 18:40:43 +00009521
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009522#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
Gaurav K Singha9da9bc2014-12-05 14:13:41 +05309523#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
9524#define PIXEL_OVERLAP_CNT_SHIFT 30
9525
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009526#define GEN6_PMISR _MMIO(0x44020)
9527#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
9528#define GEN6_PMIIR _MMIO(0x44028)
9529#define GEN6_PMIER _MMIO(0x4402C)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009530#define GEN6_PM_MBOX_EVENT (1 << 25)
9531#define GEN6_PM_THERMAL_EVENT (1 << 24)
Mika Kuoppala917dc6b2019-04-10 13:59:22 +03009532
9533/*
9534 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
9535 * registers. Shifting is handled on accessing the imr and ier.
9536 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009537#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
9538#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
9539#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
9540#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
9541#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
Chris Wilson4668f692018-08-02 11:06:30 +01009542#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
9543 GEN6_PM_RP_UP_THRESHOLD | \
9544 GEN6_PM_RP_DOWN_EI_EXPIRED | \
9545 GEN6_PM_RP_DOWN_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07009546 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00009547
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009548#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03009549#define GEN7_GT_SCRATCH_REG_NUM 8
9550
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009551#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009552#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
9553#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
Deepak S76c3552f2014-01-30 23:08:16 +05309554
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009555#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
9556#define VLV_COUNTER_CONTROL _MMIO(0x138104)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009557#define VLV_COUNT_RANGE_HIGH (1 << 15)
9558#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
9559#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
9560#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
9561#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009562#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
9563#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
9564#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
Imre Deak9cc19be2014-04-14 20:24:24 +03009565
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009566#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
9567#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
9568#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
9569#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
Ben Widawskycce66a22012-03-27 18:59:38 -07009570
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009571#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009572#define GEN6_PCODE_READY (1 << 31)
Lyude87660502016-08-17 15:55:53 -04009573#define GEN6_PCODE_ERROR_MASK 0xFF
9574#define GEN6_PCODE_SUCCESS 0x0
9575#define GEN6_PCODE_ILLEGAL_CMD 0x1
9576#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9577#define GEN6_PCODE_TIMEOUT 0x3
9578#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
9579#define GEN7_PCODE_TIMEOUT 0x2
9580#define GEN7_PCODE_ILLEGAL_DATA 0x3
Matt Roperf22fd332020-01-10 17:45:11 -08009581#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
9582#define GEN11_PCODE_LOCKED 0x6
Stanislav Lisovskiyf136c582020-05-05 13:22:45 +03009583#define GEN11_PCODE_REJECTED 0x11
Lyude87660502016-08-17 15:55:53 -04009584#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
Ville Syrjälä3e8ddd92017-09-12 18:34:10 +03009585#define GEN6_PCODE_WRITE_RC6VIDS 0x4
9586#define GEN6_PCODE_READ_RC6VIDS 0x5
Damien Lespiau9043ae02015-04-30 16:39:18 +01009587#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
9588#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009589#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
Damien Lespiau57520bc2015-04-30 16:39:19 +01009590#define GEN9_PCODE_READ_MEM_LATENCY 0x6
9591#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
9592#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
9593#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
9594#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
Sean Paulee5e5e72018-01-08 14:55:39 -05009595#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01009596#define SKL_PCODE_CDCLK_CONTROL 0x7
9597#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
9598#define SKL_CDCLK_READY_FOR_CHANGE 0x1
Damien Lespiau9043ae02015-04-30 16:39:18 +01009599#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
9600#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
9601#define GEN6_READ_OC_PARAMS 0xc
Ville Syrjäläc457d9c2019-05-24 18:36:14 +03009602#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
9603#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
9604#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
Stanislav Lisovskiy192fbfb2021-05-31 09:48:45 +03009605#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
Stanislav Lisovskiyf136c582020-05-05 13:22:45 +03009606#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
9607#define ICL_PCODE_POINTS_RESTRICTED 0x0
Stanislav Lisovskiy192fbfb2021-05-31 09:48:45 +03009608#define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf
9609#define ADLS_PSF_PT_SHIFT 8
9610#define ADLS_QGV_PT_MASK REG_GENMASK(7, 0)
9611#define ADLS_PSF_PT_MASK REG_GENMASK(10, 8)
Paulo Zanoni515b2392013-09-10 19:36:37 -03009612#define GEN6_PCODE_READ_D_COMP 0x10
9613#define GEN6_PCODE_WRITE_D_COMP 0x11
José Roberto de Souzafeb7e0e2020-04-14 12:49:52 -07009614#define ICL_PCODE_EXIT_TCCOLD 0x12
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309615#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
Ben Widawsky2a114cc2013-11-02 21:07:47 -07009616#define DISPLAY_IPS_CONTROL 0x19
José Roberto de Souza3c029342020-04-14 12:49:54 -07009617#define TGL_PCODE_TCCOLD 0x26
9618#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
Imre Deak05e31dd2020-08-05 18:00:56 +03009619#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
9620#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
Ville Syrjälä61843f02017-09-12 18:34:11 +03009621 /* See also IPS_CTL */
9622#define IPS_PCODE_CONTROL (1 << 30)
Ville Syrjälä3e8ddd92017-09-12 18:34:10 +03009623#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
Lyude656d1b82016-08-17 15:55:54 -04009624#define GEN9_PCODE_SAGV_CONTROL 0x21
9625#define GEN9_SAGV_DISABLE 0x0
9626#define GEN9_SAGV_IS_DISABLED 0x1
9627#define GEN9_SAGV_ENABLE 0x3
Matt Roperf9c730ed2020-09-30 23:39:17 -07009628#define DG1_PCODE_STATUS 0x7E
9629#define DG1_UNCORE_GET_INIT_STATUS 0x0
9630#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
James Ausmusda80f042019-10-09 10:23:15 -07009631#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009632#define GEN6_PCODE_DATA _MMIO(0x138128)
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07009633#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01009634#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009635#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
Chris Wilson8fd26852010-12-08 18:40:43 +00009636
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009637#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009638#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
Ben Widawsky4d855292011-12-12 19:34:16 -08009639#define GEN6_RCn_MASK 7
9640#define GEN6_RC0 0
9641#define GEN6_RC3 2
9642#define GEN6_RC6 3
9643#define GEN6_RC7 4
9644
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009645#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02009646#define GEN8_LSLICESTAT_MASK 0x7
9647
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009648#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
9649#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009650#define CHV_SS_PG_ENABLE (1 << 1)
9651#define CHV_EU08_PG_ENABLE (1 << 9)
9652#define CHV_EU19_PG_ENABLE (1 << 17)
9653#define CHV_EU210_PG_ENABLE (1 << 25)
Jeff McGee5575f032015-02-27 10:22:32 -08009654
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009655#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
9656#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009657#define CHV_EU311_PG_ENABLE (1 << 1)
Jeff McGee5575f032015-02-27 10:22:32 -08009658
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009659#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07009660#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
9661 ((slice) % 3) * 0x4)
Jeff McGee7f992ab2015-02-13 10:27:55 -06009662#define GEN9_PGCTL_SLICE_ACK (1 << 0)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009663#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07009664#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
Jeff McGee7f992ab2015-02-13 10:27:55 -06009665
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009666#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07009667#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
9668 ((slice) % 3) * 0x8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009669#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07009670#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9671 ((slice) % 3) * 0x8)
Jeff McGee7f992ab2015-02-13 10:27:55 -06009672#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
9673#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
9674#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
9675#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
9676#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
9677#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
9678#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
9679#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
9680
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009681#define GEN7_MISCCPCTL _MMIO(0x9424)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009682#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
9683#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
9684#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
9685#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
Ben Widawskye3689192012-05-25 16:56:22 -07009686
Oscar Mateo5bcebe72018-05-08 14:29:25 -07009687#define GEN8_GARBCNTL _MMIO(0xB004)
9688#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
9689#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
Oscar Mateod41bab62018-05-08 14:29:26 -07009690#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
9691#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
9692
9693#define GEN11_GLBLINVL _MMIO(0xB404)
9694#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
9695#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
Arun Siluvery245d9662015-08-03 20:24:56 +01009696
Oscar Mateod65dc3e2018-05-08 14:29:24 -07009697#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
9698#define DFR_DISABLE (1 << 9)
9699
Oscar Mateof4a35712018-05-08 14:29:27 -07009700#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
9701#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
9702#define GEN11_HASH_CTRL_BIT0 (1 << 0)
9703#define GEN11_HASH_CTRL_BIT4 (1 << 12)
9704
Oscar Mateo6b967dc2018-05-08 14:29:29 -07009705#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
9706#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
9707#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
9708
Oscar Mateof57f9372018-10-30 01:45:04 -07009709#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
Clint Taylora91da662020-08-25 19:57:24 -07009710#define ENABLE_SMALLPL REG_BIT(15)
Dongwon Kim397049a2019-04-25 06:50:05 +01009711#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
Oscar Mateof57f9372018-10-30 01:45:04 -07009712
Ben Widawskye3689192012-05-25 16:56:22 -07009713/* IVYBRIDGE DPF */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009714#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009715#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
9716#define GEN7_PARITY_ERROR_VALID (1 << 13)
9717#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
9718#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
Ben Widawskye3689192012-05-25 16:56:22 -07009719#define GEN7_PARITY_ERROR_ROW(reg) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07009720 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
Ben Widawskye3689192012-05-25 16:56:22 -07009721#define GEN7_PARITY_ERROR_BANK(reg) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07009722 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
Ben Widawskye3689192012-05-25 16:56:22 -07009723#define GEN7_PARITY_ERROR_SUBBANK(reg) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -07009724 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009725#define GEN7_L3CDERRST1_ENABLE (1 << 7)
Ben Widawskye3689192012-05-25 16:56:22 -07009726
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009727#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
Ben Widawskyb9524a12012-05-25 16:56:24 -07009728#define GEN7_L3LOG_SIZE 0x80
9729
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009730#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
9731#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009732#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
9733#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
9734#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
9735#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
Jesse Barnes12f33822012-10-25 12:15:45 -07009736
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009737#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009738#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
9739#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00009740
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009741#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
Matt Roper645cc0b2021-11-02 15:25:10 -07009742#define FLOW_CONTROL_ENABLE REG_BIT(15)
9743#define UGM_BACKUP_MODE REG_BIT(13)
9744#define MDQ_ARBITRATION_MODE REG_BIT(12)
9745#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
9746#define STALL_DOP_GATING_DISABLE REG_BIT(5)
9747#define THROTTLE_12_5 REG_GENMASK(4, 2)
9748#define DISABLE_EARLY_EOT REG_BIT(1)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08009749
José Roberto de Souzaec1e1262020-02-27 14:00:51 -08009750#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
Matt Roper645cc0b2021-11-02 15:25:10 -07009751#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
José Roberto de Souzaec1e1262020-02-27 14:00:51 -08009752#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
Matt Roper645cc0b2021-11-02 15:25:10 -07009753#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
José Roberto de Souzaec1e1262020-02-27 14:00:51 -08009754#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
Mika Kuoppala0db1a5f2020-02-07 17:51:38 +02009755
Matt Roper645cc0b2021-11-02 15:25:10 -07009756#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
9757#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
9758#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
9759#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
9760#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
9761#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
9762#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
9763#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
9764
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009765#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
Oscar Mateo3c7ab272018-05-25 15:05:29 -07009766#define DOP_CLOCK_GATING_DISABLE (1 << 0)
9767#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
9768#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
Jesse Barnes8ab43972012-10-25 12:15:42 -07009769
Matt Roper645cc0b2021-11-02 15:25:10 -07009770#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
9771#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
9772#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
9773#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
9774#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
Matt Atwood52c2e4e2020-02-27 14:00:53 -08009775
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009776#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07009777#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
9778
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009779#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009780#define GEN8_ST_PO_DISABLE (1 << 13)
Robert Beckett6b6d5622015-09-08 10:31:52 +01009781
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009782#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009783#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
9784#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
9785#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -07009786#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08009787
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009788#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
Matt Roper645cc0b2021-11-02 15:25:10 -07009789#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
9790#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
9791#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
9792#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
Nick Hoathcac23df2015-02-05 10:47:22 +00009793
Jani Nikulac46f1112014-10-27 16:26:52 +02009794/* Audio */
Jani Nikulaed5eb1b2018-12-31 16:56:42 +02009795#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
Jani Nikulac46f1112014-10-27 16:26:52 +02009796#define INTEL_AUDIO_DEVCL 0x808629FB
9797#define INTEL_AUDIO_DEVBLC 0x80862801
9798#define INTEL_AUDIO_DEVCTG 0x80862802
Wu Fengguange0dac652011-09-05 14:25:34 +08009799
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009800#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
Jani Nikulac46f1112014-10-27 16:26:52 +02009801#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
9802#define G4X_ELDV_DEVCTG (1 << 14)
9803#define G4X_ELD_ADDR_MASK (0xf << 5)
9804#define G4X_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009805#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
Wu Fengguange0dac652011-09-05 14:25:34 +08009806
Jani Nikulac46f1112014-10-27 16:26:52 +02009807#define _IBX_HDMIW_HDMIEDID_A 0xE2050
9808#define _IBX_HDMIW_HDMIEDID_B 0xE2150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009809#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9810 _IBX_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009811#define _IBX_AUD_CNTL_ST_A 0xE20B4
9812#define _IBX_AUD_CNTL_ST_B 0xE21B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009813#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9814 _IBX_AUD_CNTL_ST_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009815#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
9816#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
9817#define IBX_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009818#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
Jani Nikula82910ac2014-10-27 16:26:59 +02009819#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9820#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
Wu Fengguange0dac652011-09-05 14:25:34 +08009821
Jani Nikulac46f1112014-10-27 16:26:52 +02009822#define _CPT_HDMIW_HDMIEDID_A 0xE5050
9823#define _CPT_HDMIW_HDMIEDID_B 0xE5150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009824#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009825#define _CPT_AUD_CNTL_ST_A 0xE50B4
9826#define _CPT_AUD_CNTL_ST_B 0xE51B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009827#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9828#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
Wu Fengguange0dac652011-09-05 14:25:34 +08009829
Jani Nikulac46f1112014-10-27 16:26:52 +02009830#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9831#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009832#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009833#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9834#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009835#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9836#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04009837
Eric Anholtae662d32012-01-03 09:23:29 -08009838/* These are the 4 32-bit write offset registers for each stream
9839 * output buffer. It determines the offset from the
9840 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9841 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009842#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
Eric Anholtae662d32012-01-03 09:23:29 -08009843
Jani Nikulac46f1112014-10-27 16:26:52 +02009844#define _IBX_AUD_CONFIG_A 0xe2000
9845#define _IBX_AUD_CONFIG_B 0xe2100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009846#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009847#define _CPT_AUD_CONFIG_A 0xe5000
9848#define _CPT_AUD_CONFIG_B 0xe5100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009849#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02009850#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9851#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009852#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04009853
Wu Fengguangb6daa022012-01-06 14:41:31 -06009854#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
9855#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
9856#define AUD_CONFIG_UPPER_N_SHIFT 20
Jani Nikulac46f1112014-10-27 16:26:52 +02009857#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
Wu Fengguangb6daa022012-01-06 14:41:31 -06009858#define AUD_CONFIG_LOWER_N_SHIFT 4
Jani Nikulac46f1112014-10-27 16:26:52 +02009859#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
Jani Nikula25613892016-10-10 18:04:06 +03009860#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9861#define AUD_CONFIG_N(n) \
9862 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
9863 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
Wu Fengguangb6daa022012-01-06 14:41:31 -06009864#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03009865#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
9866#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
9867#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
9868#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
9869#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
9870#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
9871#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
9872#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
9873#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
9874#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
9875#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Kai Vehmanen1aae3062020-03-10 18:23:38 +02009876#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
9877#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
9878#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
9879#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06009880#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
9881
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009882/* HSW Audio */
Jani Nikulac46f1112014-10-27 16:26:52 +02009883#define _HSW_AUD_CONFIG_A 0x65000
9884#define _HSW_AUD_CONFIG_B 0x65100
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009885#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009886
Jani Nikulac46f1112014-10-27 16:26:52 +02009887#define _HSW_AUD_MISC_CTRL_A 0x65010
9888#define _HSW_AUD_MISC_CTRL_B 0x65110
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009889#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009890
Libin Yang6014ac12016-10-25 17:54:18 +03009891#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
9892#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009893#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
Libin Yang6014ac12016-10-25 17:54:18 +03009894#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
9895#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
9896#define AUD_CONFIG_M_MASK 0xfffff
9897
Jani Nikulac46f1112014-10-27 16:26:52 +02009898#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
9899#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009900#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009901
9902/* Audio Digital Converter */
Jani Nikulac46f1112014-10-27 16:26:52 +02009903#define _HSW_AUD_DIG_CNVT_1 0x65080
9904#define _HSW_AUD_DIG_CNVT_2 0x65180
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009905#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
Jani Nikulac46f1112014-10-27 16:26:52 +02009906#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009907
Jani Nikulac46f1112014-10-27 16:26:52 +02009908#define _HSW_AUD_EDID_DATA_A 0x65050
9909#define _HSW_AUD_EDID_DATA_B 0x65150
Ville Syrjälä3904fb72019-04-30 17:29:01 +03009910#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009911
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009912#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
9913#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
Jani Nikula82910ac2014-10-27 16:26:59 +02009914#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
9915#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
9916#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
9917#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08009918
Jani Nikula7d4fed82021-10-01 13:03:16 +03009919#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
9920#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
9921#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
9922#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
9923
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009924#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
Lu, Han632f3ab2015-05-05 09:05:47 +08009925#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
9926
Kai Vehmanen87c16942019-09-20 11:39:18 +03009927#define AUD_FREQ_CNTRL _MMIO(0x65900)
Kai Vehmanen1580d3c2019-10-03 11:55:30 +03009928#define AUD_PIN_BUF_CTL _MMIO(0x48414)
9929#define AUD_PIN_BUF_ENABLE REG_BIT(31)
Kai Vehmanen87c16942019-09-20 11:39:18 +03009930
Kai Vehmanen112a87c2021-10-21 13:59:15 +03009931#define AUD_TS_CDCLK_M _MMIO(0x65ea0)
9932#define AUD_TS_CDCLK_M_EN REG_BIT(31)
9933#define AUD_TS_CDCLK_N _MMIO(0x65ea4)
9934
Uma Shankar48b8b042020-04-16 16:24:19 +05309935/* Display Audio Config Reg */
9936#define AUD_CONFIG_BE _MMIO(0x65ef0)
9937#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
9938#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
9939#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
9940#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
9941#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
9942#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
9943
9944#define HBLANK_START_COUNT_8 0
9945#define HBLANK_START_COUNT_16 1
9946#define HBLANK_START_COUNT_32 2
9947#define HBLANK_START_COUNT_64 3
9948#define HBLANK_START_COUNT_96 4
9949#define HBLANK_START_COUNT_128 5
9950
Imre Deak9c3a16c2017-08-14 18:15:30 +03009951/*
Imre Deak75e39682018-08-06 12:58:39 +03009952 * HSW - ICL power wells
9953 *
9954 * Platforms have up to 3 power well control register sets, each set
9955 * controlling up to 16 power wells via a request/status HW flag tuple:
9956 * - main (HSW_PWR_WELL_CTL[1-4])
9957 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9958 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9959 * Each control register set consists of up to 4 registers used by different
9960 * sources that can request a power well to be enabled:
9961 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9962 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9963 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9964 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
Imre Deak9c3a16c2017-08-14 18:15:30 +03009965 */
Imre Deak75e39682018-08-06 12:58:39 +03009966#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
9967#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
9968#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
9969#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
9970#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
9971#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
Imre Deak9c3a16c2017-08-14 18:15:30 +03009972
Imre Deak75e39682018-08-06 12:58:39 +03009973/* HSW/BDW power well */
9974#define HSW_PW_CTL_IDX_GLOBAL 15
9975
Lucas De Marchia4d082f2021-07-28 14:59:45 -07009976/* SKL/BXT/GLK power wells */
Imre Deak75e39682018-08-06 12:58:39 +03009977#define SKL_PW_CTL_IDX_PW_2 15
9978#define SKL_PW_CTL_IDX_PW_1 14
Imre Deak75e39682018-08-06 12:58:39 +03009979#define GLK_PW_CTL_IDX_AUX_C 10
9980#define GLK_PW_CTL_IDX_AUX_B 9
9981#define GLK_PW_CTL_IDX_AUX_A 8
Imre Deak75e39682018-08-06 12:58:39 +03009982#define SKL_PW_CTL_IDX_DDI_D 4
9983#define SKL_PW_CTL_IDX_DDI_C 3
9984#define SKL_PW_CTL_IDX_DDI_B 2
9985#define SKL_PW_CTL_IDX_DDI_A_E 1
9986#define GLK_PW_CTL_IDX_DDI_A 1
9987#define SKL_PW_CTL_IDX_MISC_IO 0
9988
Imre Deak656409b2019-07-11 10:31:02 -07009989/* ICL/TGL - power wells */
Mika Kahola1db27a72019-07-11 10:31:03 -07009990#define TGL_PW_CTL_IDX_PW_5 4
Imre Deak75e39682018-08-06 12:58:39 +03009991#define ICL_PW_CTL_IDX_PW_4 3
9992#define ICL_PW_CTL_IDX_PW_3 2
9993#define ICL_PW_CTL_IDX_PW_2 1
9994#define ICL_PW_CTL_IDX_PW_1 0
9995
Matt Ropera6922f42021-05-11 21:21:40 -07009996/* XE_LPD - power wells */
9997#define XELPD_PW_CTL_IDX_PW_D 8
9998#define XELPD_PW_CTL_IDX_PW_C 7
9999#define XELPD_PW_CTL_IDX_PW_B 6
10000#define XELPD_PW_CTL_IDX_PW_A 5
10001
Imre Deak75e39682018-08-06 12:58:39 +030010002#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
10003#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
10004#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
Imre Deak656409b2019-07-11 10:31:02 -070010005#define TGL_PW_CTL_IDX_AUX_TBT6 14
10006#define TGL_PW_CTL_IDX_AUX_TBT5 13
10007#define TGL_PW_CTL_IDX_AUX_TBT4 12
Imre Deak75e39682018-08-06 12:58:39 +030010008#define ICL_PW_CTL_IDX_AUX_TBT4 11
Imre Deak656409b2019-07-11 10:31:02 -070010009#define TGL_PW_CTL_IDX_AUX_TBT3 11
Imre Deak75e39682018-08-06 12:58:39 +030010010#define ICL_PW_CTL_IDX_AUX_TBT3 10
Imre Deak656409b2019-07-11 10:31:02 -070010011#define TGL_PW_CTL_IDX_AUX_TBT2 10
Imre Deak75e39682018-08-06 12:58:39 +030010012#define ICL_PW_CTL_IDX_AUX_TBT2 9
Imre Deak656409b2019-07-11 10:31:02 -070010013#define TGL_PW_CTL_IDX_AUX_TBT1 9
Imre Deak75e39682018-08-06 12:58:39 +030010014#define ICL_PW_CTL_IDX_AUX_TBT1 8
Imre Deak656409b2019-07-11 10:31:02 -070010015#define TGL_PW_CTL_IDX_AUX_TC6 8
Matt Ropera6922f42021-05-11 21:21:40 -070010016#define XELPD_PW_CTL_IDX_AUX_E 8
Imre Deak656409b2019-07-11 10:31:02 -070010017#define TGL_PW_CTL_IDX_AUX_TC5 7
Matt Ropera6922f42021-05-11 21:21:40 -070010018#define XELPD_PW_CTL_IDX_AUX_D 7
Imre Deak656409b2019-07-11 10:31:02 -070010019#define TGL_PW_CTL_IDX_AUX_TC4 6
Imre Deak75e39682018-08-06 12:58:39 +030010020#define ICL_PW_CTL_IDX_AUX_F 5
Imre Deak656409b2019-07-11 10:31:02 -070010021#define TGL_PW_CTL_IDX_AUX_TC3 5
Imre Deak75e39682018-08-06 12:58:39 +030010022#define ICL_PW_CTL_IDX_AUX_E 4
Imre Deak656409b2019-07-11 10:31:02 -070010023#define TGL_PW_CTL_IDX_AUX_TC2 4
Imre Deak75e39682018-08-06 12:58:39 +030010024#define ICL_PW_CTL_IDX_AUX_D 3
Imre Deak656409b2019-07-11 10:31:02 -070010025#define TGL_PW_CTL_IDX_AUX_TC1 3
Imre Deak75e39682018-08-06 12:58:39 +030010026#define ICL_PW_CTL_IDX_AUX_C 2
10027#define ICL_PW_CTL_IDX_AUX_B 1
10028#define ICL_PW_CTL_IDX_AUX_A 0
10029
10030#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
10031#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
10032#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
Matt Ropera6922f42021-05-11 21:21:40 -070010033#define XELPD_PW_CTL_IDX_DDI_E 8
Imre Deak656409b2019-07-11 10:31:02 -070010034#define TGL_PW_CTL_IDX_DDI_TC6 8
Matt Ropera6922f42021-05-11 21:21:40 -070010035#define XELPD_PW_CTL_IDX_DDI_D 7
Imre Deak656409b2019-07-11 10:31:02 -070010036#define TGL_PW_CTL_IDX_DDI_TC5 7
10037#define TGL_PW_CTL_IDX_DDI_TC4 6
Imre Deak75e39682018-08-06 12:58:39 +030010038#define ICL_PW_CTL_IDX_DDI_F 5
Imre Deak656409b2019-07-11 10:31:02 -070010039#define TGL_PW_CTL_IDX_DDI_TC3 5
Imre Deak75e39682018-08-06 12:58:39 +030010040#define ICL_PW_CTL_IDX_DDI_E 4
Imre Deak656409b2019-07-11 10:31:02 -070010041#define TGL_PW_CTL_IDX_DDI_TC2 4
Imre Deak75e39682018-08-06 12:58:39 +030010042#define ICL_PW_CTL_IDX_DDI_D 3
Imre Deak656409b2019-07-11 10:31:02 -070010043#define TGL_PW_CTL_IDX_DDI_TC1 3
Imre Deak75e39682018-08-06 12:58:39 +030010044#define ICL_PW_CTL_IDX_DDI_C 2
10045#define ICL_PW_CTL_IDX_DDI_B 1
10046#define ICL_PW_CTL_IDX_DDI_A 0
10047
10048/* HSW - power well misc debug registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010049#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010050#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
10051#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
10052#define HSW_PWR_WELL_FORCE_ON (1 << 19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010053#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -030010054
Satheeshakrishna M94dd5132015-02-04 13:57:44 +000010055/* SKL Fuse Status */
Imre Deakb2891eb2017-07-11 23:42:35 +030010056enum skl_power_gate {
10057 SKL_PG0,
10058 SKL_PG1,
10059 SKL_PG2,
Imre Deak1a260e12018-08-06 12:58:43 +030010060 ICL_PG3,
10061 ICL_PG4,
Imre Deakb2891eb2017-07-11 23:42:35 +030010062};
10063
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010064#define SKL_FUSE_STATUS _MMIO(0x42000)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010065#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
Imre Deak75e39682018-08-06 12:58:39 +030010066/*
10067 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
10068 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
10069 */
10070#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
10071 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
10072/*
10073 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
10074 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
10075 */
10076#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
10077 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
Imre Deakb2891eb2017-07-11 23:42:35 +030010078#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
Satheeshakrishna M94dd5132015-02-04 13:57:44 +000010079
Lucas De Marchiffd7e322018-10-12 14:57:58 -070010080#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
10081#define _ICL_AUX_ANAOVRD1_A 0x162398
10082#define _ICL_AUX_ANAOVRD1_B 0x6C398
10083#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
10084 _ICL_AUX_ANAOVRD1_A, \
Matt Roperab340252019-12-12 16:15:10 -080010085 _ICL_AUX_ANAOVRD1_B))
Lucas De Marchiffd7e322018-10-12 14:57:58 -070010086#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
10087#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
10088
Sean Paulee5e5e72018-01-08 14:55:39 -050010089/* HDCP Key Registers */
Ramalingam C2834d9d2018-02-03 03:39:10 +053010090#define HDCP_KEY_CONF _MMIO(0x66c00)
Sean Paulee5e5e72018-01-08 14:55:39 -050010091#define HDCP_AKSV_SEND_TRIGGER BIT(31)
10092#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
Ramalingam Cfdddd082018-01-18 11:18:05 +053010093#define HDCP_KEY_LOAD_TRIGGER BIT(8)
Ramalingam C2834d9d2018-02-03 03:39:10 +053010094#define HDCP_KEY_STATUS _MMIO(0x66c04)
10095#define HDCP_FUSE_IN_PROGRESS BIT(7)
Sean Paulee5e5e72018-01-08 14:55:39 -050010096#define HDCP_FUSE_ERROR BIT(6)
Ramalingam C2834d9d2018-02-03 03:39:10 +053010097#define HDCP_FUSE_DONE BIT(5)
10098#define HDCP_KEY_LOAD_STATUS BIT(1)
Sean Paulee5e5e72018-01-08 14:55:39 -050010099#define HDCP_KEY_LOAD_DONE BIT(0)
Ramalingam C2834d9d2018-02-03 03:39:10 +053010100#define HDCP_AKSV_LO _MMIO(0x66c10)
10101#define HDCP_AKSV_HI _MMIO(0x66c14)
Sean Paulee5e5e72018-01-08 14:55:39 -050010102
10103/* HDCP Repeater Registers */
Ramalingam C2834d9d2018-02-03 03:39:10 +053010104#define HDCP_REP_CTL _MMIO(0x66d00)
Ramalingam C69205932019-08-28 22:12:16 +053010105#define HDCP_TRANSA_REP_PRESENT BIT(31)
10106#define HDCP_TRANSB_REP_PRESENT BIT(30)
10107#define HDCP_TRANSC_REP_PRESENT BIT(29)
10108#define HDCP_TRANSD_REP_PRESENT BIT(28)
Ramalingam C2834d9d2018-02-03 03:39:10 +053010109#define HDCP_DDIB_REP_PRESENT BIT(30)
10110#define HDCP_DDIA_REP_PRESENT BIT(29)
10111#define HDCP_DDIC_REP_PRESENT BIT(28)
10112#define HDCP_DDID_REP_PRESENT BIT(27)
10113#define HDCP_DDIF_REP_PRESENT BIT(26)
10114#define HDCP_DDIE_REP_PRESENT BIT(25)
Ramalingam C69205932019-08-28 22:12:16 +053010115#define HDCP_TRANSA_SHA1_M0 (1 << 20)
10116#define HDCP_TRANSB_SHA1_M0 (2 << 20)
10117#define HDCP_TRANSC_SHA1_M0 (3 << 20)
10118#define HDCP_TRANSD_SHA1_M0 (4 << 20)
Sean Paulee5e5e72018-01-08 14:55:39 -050010119#define HDCP_DDIB_SHA1_M0 (1 << 20)
10120#define HDCP_DDIA_SHA1_M0 (2 << 20)
10121#define HDCP_DDIC_SHA1_M0 (3 << 20)
10122#define HDCP_DDID_SHA1_M0 (4 << 20)
10123#define HDCP_DDIF_SHA1_M0 (5 << 20)
10124#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
Ramalingam C2834d9d2018-02-03 03:39:10 +053010125#define HDCP_SHA1_BUSY BIT(16)
Sean Paulee5e5e72018-01-08 14:55:39 -050010126#define HDCP_SHA1_READY BIT(17)
10127#define HDCP_SHA1_COMPLETE BIT(18)
10128#define HDCP_SHA1_V_MATCH BIT(19)
10129#define HDCP_SHA1_TEXT_32 (1 << 1)
10130#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
10131#define HDCP_SHA1_TEXT_24 (4 << 1)
10132#define HDCP_SHA1_TEXT_16 (5 << 1)
10133#define HDCP_SHA1_TEXT_8 (6 << 1)
10134#define HDCP_SHA1_TEXT_0 (7 << 1)
10135#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
10136#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
10137#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
10138#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
10139#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070010140#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
Ramalingam C2834d9d2018-02-03 03:39:10 +053010141#define HDCP_SHA_TEXT _MMIO(0x66d18)
Sean Paulee5e5e72018-01-08 14:55:39 -050010142
10143/* HDCP Auth Registers */
10144#define _PORTA_HDCP_AUTHENC 0x66800
10145#define _PORTB_HDCP_AUTHENC 0x66500
10146#define _PORTC_HDCP_AUTHENC 0x66600
10147#define _PORTD_HDCP_AUTHENC 0x66700
10148#define _PORTE_HDCP_AUTHENC 0x66A00
10149#define _PORTF_HDCP_AUTHENC 0x66900
10150#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
10151 _PORTA_HDCP_AUTHENC, \
10152 _PORTB_HDCP_AUTHENC, \
10153 _PORTC_HDCP_AUTHENC, \
10154 _PORTD_HDCP_AUTHENC, \
10155 _PORTE_HDCP_AUTHENC, \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070010156 _PORTF_HDCP_AUTHENC) + (x))
Ramalingam C2834d9d2018-02-03 03:39:10 +053010157#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
Ramalingam C69205932019-08-28 22:12:16 +053010158#define _TRANSA_HDCP_CONF 0x66400
10159#define _TRANSB_HDCP_CONF 0x66500
10160#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
10161 _TRANSB_HDCP_CONF)
10162#define HDCP_CONF(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010163 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010164 TRANS_HDCP_CONF(trans) : \
10165 PORT_HDCP_CONF(port))
10166
Ramalingam C2834d9d2018-02-03 03:39:10 +053010167#define HDCP_CONF_CAPTURE_AN BIT(0)
10168#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
10169#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
Ramalingam C69205932019-08-28 22:12:16 +053010170#define _TRANSA_HDCP_ANINIT 0x66404
10171#define _TRANSB_HDCP_ANINIT 0x66504
10172#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
10173 _TRANSA_HDCP_ANINIT, \
10174 _TRANSB_HDCP_ANINIT)
10175#define HDCP_ANINIT(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010176 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010177 TRANS_HDCP_ANINIT(trans) : \
10178 PORT_HDCP_ANINIT(port))
10179
Ramalingam C2834d9d2018-02-03 03:39:10 +053010180#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
Ramalingam C69205932019-08-28 22:12:16 +053010181#define _TRANSA_HDCP_ANLO 0x66408
10182#define _TRANSB_HDCP_ANLO 0x66508
10183#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
10184 _TRANSB_HDCP_ANLO)
10185#define HDCP_ANLO(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010186 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010187 TRANS_HDCP_ANLO(trans) : \
10188 PORT_HDCP_ANLO(port))
10189
Ramalingam C2834d9d2018-02-03 03:39:10 +053010190#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
Ramalingam C69205932019-08-28 22:12:16 +053010191#define _TRANSA_HDCP_ANHI 0x6640C
10192#define _TRANSB_HDCP_ANHI 0x6650C
10193#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
10194 _TRANSB_HDCP_ANHI)
10195#define HDCP_ANHI(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010196 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010197 TRANS_HDCP_ANHI(trans) : \
10198 PORT_HDCP_ANHI(port))
10199
Ramalingam C2834d9d2018-02-03 03:39:10 +053010200#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
Ramalingam C69205932019-08-28 22:12:16 +053010201#define _TRANSA_HDCP_BKSVLO 0x66410
10202#define _TRANSB_HDCP_BKSVLO 0x66510
10203#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
10204 _TRANSA_HDCP_BKSVLO, \
10205 _TRANSB_HDCP_BKSVLO)
10206#define HDCP_BKSVLO(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010207 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010208 TRANS_HDCP_BKSVLO(trans) : \
10209 PORT_HDCP_BKSVLO(port))
10210
Ramalingam C2834d9d2018-02-03 03:39:10 +053010211#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
Ramalingam C69205932019-08-28 22:12:16 +053010212#define _TRANSA_HDCP_BKSVHI 0x66414
10213#define _TRANSB_HDCP_BKSVHI 0x66514
10214#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
10215 _TRANSA_HDCP_BKSVHI, \
10216 _TRANSB_HDCP_BKSVHI)
10217#define HDCP_BKSVHI(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010218 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010219 TRANS_HDCP_BKSVHI(trans) : \
10220 PORT_HDCP_BKSVHI(port))
10221
Ramalingam C2834d9d2018-02-03 03:39:10 +053010222#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
Ramalingam C69205932019-08-28 22:12:16 +053010223#define _TRANSA_HDCP_RPRIME 0x66418
10224#define _TRANSB_HDCP_RPRIME 0x66518
10225#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
10226 _TRANSA_HDCP_RPRIME, \
10227 _TRANSB_HDCP_RPRIME)
10228#define HDCP_RPRIME(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010229 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010230 TRANS_HDCP_RPRIME(trans) : \
10231 PORT_HDCP_RPRIME(port))
10232
Ramalingam C2834d9d2018-02-03 03:39:10 +053010233#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
Ramalingam C69205932019-08-28 22:12:16 +053010234#define _TRANSA_HDCP_STATUS 0x6641C
10235#define _TRANSB_HDCP_STATUS 0x6651C
10236#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
10237 _TRANSA_HDCP_STATUS, \
10238 _TRANSB_HDCP_STATUS)
10239#define HDCP_STATUS(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010240 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010241 TRANS_HDCP_STATUS(trans) : \
10242 PORT_HDCP_STATUS(port))
10243
Sean Paulee5e5e72018-01-08 14:55:39 -050010244#define HDCP_STATUS_STREAM_A_ENC BIT(31)
10245#define HDCP_STATUS_STREAM_B_ENC BIT(30)
10246#define HDCP_STATUS_STREAM_C_ENC BIT(29)
10247#define HDCP_STATUS_STREAM_D_ENC BIT(28)
10248#define HDCP_STATUS_AUTH BIT(21)
10249#define HDCP_STATUS_ENC BIT(20)
Ramalingam C2834d9d2018-02-03 03:39:10 +053010250#define HDCP_STATUS_RI_MATCH BIT(19)
10251#define HDCP_STATUS_R0_READY BIT(18)
10252#define HDCP_STATUS_AN_READY BIT(17)
Sean Paulee5e5e72018-01-08 14:55:39 -050010253#define HDCP_STATUS_CIPHER BIT(16)
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070010254#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
Sean Paulee5e5e72018-01-08 14:55:39 -050010255
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010256/* HDCP2.2 Registers */
10257#define _PORTA_HDCP2_BASE 0x66800
10258#define _PORTB_HDCP2_BASE 0x66500
10259#define _PORTC_HDCP2_BASE 0x66600
10260#define _PORTD_HDCP2_BASE 0x66700
10261#define _PORTE_HDCP2_BASE 0x66A00
10262#define _PORTF_HDCP2_BASE 0x66900
10263#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
10264 _PORTA_HDCP2_BASE, \
10265 _PORTB_HDCP2_BASE, \
10266 _PORTC_HDCP2_BASE, \
10267 _PORTD_HDCP2_BASE, \
10268 _PORTE_HDCP2_BASE, \
10269 _PORTF_HDCP2_BASE) + (x))
Anshuman Guptad631b982021-01-11 13:41:17 +053010270
Ramalingam C69205932019-08-28 22:12:16 +053010271#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
10272#define _TRANSA_HDCP2_AUTH 0x66498
10273#define _TRANSB_HDCP2_AUTH 0x66598
10274#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
10275 _TRANSB_HDCP2_AUTH)
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010276#define AUTH_LINK_AUTHENTICATED BIT(31)
10277#define AUTH_LINK_TYPE BIT(30)
10278#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
10279#define AUTH_CLR_KEYS BIT(18)
Ramalingam C69205932019-08-28 22:12:16 +053010280#define HDCP2_AUTH(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010281 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010282 TRANS_HDCP2_AUTH(trans) : \
10283 PORT_HDCP2_AUTH(port))
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010284
Ramalingam C69205932019-08-28 22:12:16 +053010285#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
10286#define _TRANSA_HDCP2_CTL 0x664B0
10287#define _TRANSB_HDCP2_CTL 0x665B0
10288#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
10289 _TRANSB_HDCP2_CTL)
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010290#define CTL_LINK_ENCRYPTION_REQ BIT(31)
Ramalingam C69205932019-08-28 22:12:16 +053010291#define HDCP2_CTL(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010292 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010293 TRANS_HDCP2_CTL(trans) : \
10294 PORT_HDCP2_CTL(port))
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010295
Ramalingam C69205932019-08-28 22:12:16 +053010296#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
10297#define _TRANSA_HDCP2_STATUS 0x664B4
10298#define _TRANSB_HDCP2_STATUS 0x665B4
10299#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
10300 _TRANSA_HDCP2_STATUS, \
10301 _TRANSB_HDCP2_STATUS)
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010302#define LINK_TYPE_STATUS BIT(22)
10303#define LINK_AUTH_STATUS BIT(21)
10304#define LINK_ENCRYPTION_STATUS BIT(20)
Ramalingam C69205932019-08-28 22:12:16 +053010305#define HDCP2_STATUS(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010306 (GRAPHICS_VER(dev_priv) >= 12 ? \
Ramalingam C69205932019-08-28 22:12:16 +053010307 TRANS_HDCP2_STATUS(trans) : \
10308 PORT_HDCP2_STATUS(port))
Ramalingam C3ab0a6e2018-10-29 15:15:51 +053010309
Anshuman Guptad631b982021-01-11 13:41:17 +053010310#define _PIPEA_HDCP2_STREAM_STATUS 0x668C0
10311#define _PIPEB_HDCP2_STREAM_STATUS 0x665C0
10312#define _PIPEC_HDCP2_STREAM_STATUS 0x666C0
10313#define _PIPED_HDCP2_STREAM_STATUS 0x667C0
10314#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
10315 _PIPEA_HDCP2_STREAM_STATUS, \
10316 _PIPEB_HDCP2_STREAM_STATUS, \
10317 _PIPEC_HDCP2_STREAM_STATUS, \
10318 _PIPED_HDCP2_STREAM_STATUS))
10319
10320#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
10321#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
10322#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
10323 _TRANSA_HDCP2_STREAM_STATUS, \
10324 _TRANSB_HDCP2_STREAM_STATUS)
10325#define STREAM_ENCRYPTION_STATUS BIT(31)
10326#define STREAM_TYPE_STATUS BIT(30)
10327#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010328 (GRAPHICS_VER(dev_priv) >= 12 ? \
Anshuman Guptad631b982021-01-11 13:41:17 +053010329 TRANS_HDCP2_STREAM_STATUS(trans) : \
10330 PIPE_HDCP2_STREAM_STATUS(pipe))
10331
10332#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
10333#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
10334#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
10335 _PORTA_HDCP2_AUTH_STREAM, \
10336 _PORTB_HDCP2_AUTH_STREAM)
10337#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
10338#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
10339#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
10340 _TRANSA_HDCP2_AUTH_STREAM, \
10341 _TRANSB_HDCP2_AUTH_STREAM)
10342#define AUTH_STREAM_TYPE BIT(31)
10343#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
Lucas De Marchi161058f2021-06-05 21:50:50 -070010344 (GRAPHICS_VER(dev_priv) >= 12 ? \
Anshuman Guptad631b982021-01-11 13:41:17 +053010345 TRANS_HDCP2_AUTH_STREAM(trans) : \
10346 PORT_HDCP2_AUTH_STREAM(port))
10347
Eugeni Dodonove7e104c2012-03-29 12:32:23 -030010348/* Per-pipe DDI Function Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010349#define _TRANS_DDI_FUNC_CTL_A 0x60400
10350#define _TRANS_DDI_FUNC_CTL_B 0x61400
10351#define _TRANS_DDI_FUNC_CTL_C 0x62400
Lucas De Marchif1f1d4f2019-07-11 10:30:55 -070010352#define _TRANS_DDI_FUNC_CTL_D 0x63400
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010353#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
Madhav Chauhan49edbd42018-10-15 17:28:00 +030010354#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
10355#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010356#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
Antti Koskipaaa57c7742014-02-04 14:22:24 +020010357
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010358#define TRANS_DDI_FUNC_ENABLE (1 << 31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -030010359/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Daniel Vetter26804af2014-06-25 22:01:55 +030010360#define TRANS_DDI_PORT_SHIFT 28
Mahesh Kumardf16b632019-07-12 18:09:20 -070010361#define TGL_TRANS_DDI_PORT_SHIFT 27
10362#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
10363#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
10364#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
10365#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010366#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
10367#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
10368#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
10369#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
10370#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
Jani Nikula7bb97db2021-09-09 15:51:57 +030010371#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010372#define TRANS_DDI_BPC_MASK (7 << 20)
10373#define TRANS_DDI_BPC_8 (0 << 20)
10374#define TRANS_DDI_BPC_10 (1 << 20)
10375#define TRANS_DDI_BPC_6 (2 << 20)
10376#define TRANS_DDI_BPC_12 (3 << 20)
Lucas De Marchia4d082f2021-07-28 14:59:45 -070010377#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
Ville Syrjälädc5b8ed2020-03-13 18:48:26 +020010378#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010379#define TRANS_DDI_PVSYNC (1 << 17)
10380#define TRANS_DDI_PHSYNC (1 << 16)
Lucas De Marchia4d082f2021-07-28 14:59:45 -070010381#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010382#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
10383#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
10384#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
10385#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
10386#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
José Roberto de Souza4d89adc2019-11-07 13:45:58 -080010387#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
José Roberto de Souzabb747fa2019-11-07 13:45:57 -080010388#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
Lucas De Marchib3545e02019-10-28 20:50:49 -070010389#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
10390 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010391#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
10392#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
10393#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
10394#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
Anshuman Gupta1a67a162021-01-11 13:41:08 +053010395#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010396#define TRANS_DDI_BFI_ENABLE (1 << 4)
10397#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
10398#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
Shashank Sharma15953632017-03-13 16:54:03 +053010399#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
10400 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
10401 | TRANS_DDI_HDMI_SCRAMBLING)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -030010402
Madhav Chauhan49edbd42018-10-15 17:28:00 +030010403#define _TRANS_DDI_FUNC_CTL2_A 0x60404
10404#define _TRANS_DDI_FUNC_CTL2_B 0x61404
10405#define _TRANS_DDI_FUNC_CTL2_C 0x62404
10406#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
10407#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
10408#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
Ville Syrjäläd4d7d9c2020-03-13 18:48:23 +020010409#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
10410#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
10411#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
10412#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
Madhav Chauhan49edbd42018-10-15 17:28:00 +030010413
Imre Deak573d7ce2021-07-27 16:44:00 +030010414#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
10415#define DISABLE_DPT_CLK_GATING REG_BIT(1)
10416
Eugeni Dodonov0e87f662012-03-29 12:32:24 -030010417/* DisplayPort Transport Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010418#define _DP_TP_CTL_A 0x64040
10419#define _DP_TP_CTL_B 0x64140
Lucas De Marchi4444df62019-09-04 14:34:17 -070010420#define _TGL_DP_TP_CTL_A 0x60540
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010421#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
Lucas De Marchi4444df62019-09-04 14:34:17 -070010422#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010423#define DP_TP_CTL_ENABLE (1 << 31)
Anusha Srivatsa5c44b932018-11-28 12:26:27 -080010424#define DP_TP_CTL_FEC_ENABLE (1 << 30)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010425#define DP_TP_CTL_MODE_SST (0 << 27)
10426#define DP_TP_CTL_MODE_MST (1 << 27)
10427#define DP_TP_CTL_FORCE_ACT (1 << 25)
10428#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
10429#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
10430#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
10431#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
10432#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
10433#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
10434#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
10435#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
10436#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
10437#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -030010438
Eugeni Dodonove411b2c2012-03-29 12:32:25 -030010439/* DisplayPort Transport Status */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010440#define _DP_TP_STATUS_A 0x64044
10441#define _DP_TP_STATUS_B 0x64144
Lucas De Marchi4444df62019-09-04 14:34:17 -070010442#define _TGL_DP_TP_STATUS_A 0x60544
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010443#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
Lucas De Marchi4444df62019-09-04 14:34:17 -070010444#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
Anusha Srivatsa5c44b932018-11-28 12:26:27 -080010445#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010446#define DP_TP_STATUS_IDLE_DONE (1 << 25)
10447#define DP_TP_STATUS_ACT_SENT (1 << 24)
10448#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
10449#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
Dave Airlie01b887c2014-05-02 11:17:41 +100010450#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
10451#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
10452#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -030010453
Eugeni Dodonov03f896a2012-03-29 12:32:26 -030010454/* DDI Buffer Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010455#define _DDI_BUF_CTL_A 0x64000
10456#define _DDI_BUF_CTL_B 0x64100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010457#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010458#define DDI_BUF_CTL_ENABLE (1 << 31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +053010459#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010460#define DDI_BUF_EMP_MASK (0xf << 24)
Imre Deak414002f2021-05-18 17:06:23 -070010461#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010462#define DDI_BUF_PORT_REVERSAL (1 << 16)
10463#define DDI_BUF_IS_IDLE (1 << 7)
José Roberto de Souza55ce3062021-05-18 17:06:13 -070010464#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010465#define DDI_A_4_LANES (1 << 4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +020010466#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030010467#define DDI_PORT_WIDTH_MASK (7 << 1)
10468#define DDI_PORT_WIDTH_SHIFT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010469#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -030010470
Eugeni Dodonovbb879a42012-03-29 12:32:27 -030010471/* DDI Buffer Translations */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010472#define _DDI_BUF_TRANS_A 0x64E00
10473#define _DDI_BUF_TRANS_B 0x64E60
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010474#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
Ville Syrjäläc110ae62016-07-12 15:59:29 +030010475#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010476#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -030010477
Animesh Mannafce214a2020-03-24 10:41:11 +053010478/* DDI DP Compliance Control */
10479#define _DDI_DP_COMP_CTL_A 0x605F0
10480#define _DDI_DP_COMP_CTL_B 0x615F0
10481#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
10482#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
10483#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
10484#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
10485#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
10486#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
10487#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
10488#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
10489#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
10490
10491/* DDI DP Compliance Pattern */
10492#define _DDI_DP_COMP_PAT_A 0x605F4
10493#define _DDI_DP_COMP_PAT_B 0x615F4
10494#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
10495
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -030010496/* Sideband Interface (SBI) is programmed indirectly, via
10497 * SBI_ADDR, which contains the register offset; and SBI_DATA,
10498 * which contains the payload */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010499#define SBI_ADDR _MMIO(0xC6000)
10500#define SBI_DATA _MMIO(0xC6004)
10501#define SBI_CTL_STAT _MMIO(0xC6008)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010502#define SBI_CTL_DEST_ICLK (0x0 << 16)
10503#define SBI_CTL_DEST_MPHY (0x1 << 16)
10504#define SBI_CTL_OP_IORD (0x2 << 8)
10505#define SBI_CTL_OP_IOWR (0x3 << 8)
10506#define SBI_CTL_OP_CRRD (0x6 << 8)
10507#define SBI_CTL_OP_CRWR (0x7 << 8)
10508#define SBI_RESPONSE_FAIL (0x1 << 1)
10509#define SBI_RESPONSE_SUCCESS (0x0 << 1)
10510#define SBI_BUSY (0x1 << 0)
10511#define SBI_READY (0x0 << 0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -030010512
Eugeni Dodonovccf1c862012-03-29 12:32:34 -030010513/* SBI offsets */
Ville Syrjäläf7be2c22015-12-04 22:19:39 +020010514#define SBI_SSCDIVINTPHASE 0x0200
Paulo Zanoni5e49cea2012-08-08 14:15:31 -030010515#define SBI_SSCDIVINTPHASE6 0x0600
Ville Syrjälä8802e5b2016-02-17 21:41:12 +020010516#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010517#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
10518#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
Ville Syrjälä8802e5b2016-02-17 21:41:12 +020010519#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010520#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
10521#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
10522#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
10523#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
Ville Syrjäläf7be2c22015-12-04 22:19:39 +020010524#define SBI_SSCDITHPHASE 0x0204
Paulo Zanoni5e49cea2012-08-08 14:15:31 -030010525#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -030010526#define SBI_SSCCTL6 0x060C
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010527#define SBI_SSCCTL_PATHALT (1 << 3)
10528#define SBI_SSCCTL_DISABLE (1 << 0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -030010529#define SBI_SSCAUXDIV6 0x0610
Ville Syrjälä8802e5b2016-02-17 21:41:12 +020010530#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010531#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
10532#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -030010533#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -030010534#define SBI_GEN0 0x1f00
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010535#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -030010536
Eugeni Dodonov52f025e2012-03-29 12:32:31 -030010537/* LPT PIXCLK_GATE */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010538#define PIXCLK_GATE _MMIO(0xC6020)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010539#define PIXCLK_GATE_UNGATE (1 << 0)
10540#define PIXCLK_GATE_GATE (0 << 0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -030010541
Eugeni Dodonove93ea062012-03-29 12:32:32 -030010542/* SPLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010543#define SPLL_CTL _MMIO(0x46020)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010544#define SPLL_PLL_ENABLE (1 << 31)
Ville Syrjälä4a95e362019-06-10 16:36:09 +030010545#define SPLL_REF_BCLK (0 << 28)
10546#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10547#define SPLL_REF_NON_SSC_HSW (2 << 28)
10548#define SPLL_REF_PCH_SSC_BDW (2 << 28)
10549#define SPLL_REF_LCPLL (3 << 28)
10550#define SPLL_REF_MASK (3 << 28)
10551#define SPLL_FREQ_810MHz (0 << 26)
10552#define SPLL_FREQ_1350MHz (1 << 26)
10553#define SPLL_FREQ_2700MHz (2 << 26)
10554#define SPLL_FREQ_MASK (3 << 26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -030010555
Eugeni Dodonov4dffc402012-03-29 12:32:36 -030010556/* WRPLL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010557#define _WRPLL_CTL1 0x46040
10558#define _WRPLL_CTL2 0x46060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010559#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010560#define WRPLL_PLL_ENABLE (1 << 31)
Ville Syrjälä4a95e362019-06-10 16:36:09 +030010561#define WRPLL_REF_BCLK (0 << 28)
10562#define WRPLL_REF_PCH_SSC (1 << 28)
10563#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10564#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10565#define WRPLL_REF_LCPLL (3 << 28)
10566#define WRPLL_REF_MASK (3 << 28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -030010567/* WRPLL divider programming */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010568#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
Jesse Barnes11578552014-01-21 12:42:10 -080010569#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010570#define WRPLL_DIVIDER_POST(x) ((x) << 8)
10571#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
Jesse Barnes11578552014-01-21 12:42:10 -080010572#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010573#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
Jesse Barnes11578552014-01-21 12:42:10 -080010574#define WRPLL_DIVIDER_FB_SHIFT 16
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010575#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -030010576
Eugeni Dodonovfec91812012-03-29 12:32:33 -030010577/* Port clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010578#define _PORT_CLK_SEL_A 0x46100
10579#define _PORT_CLK_SEL_B 0x46104
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010580#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010581#define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
10582#define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
10583#define PORT_CLK_SEL_LCPLL_810 (2 << 29)
10584#define PORT_CLK_SEL_SPLL (3 << 29)
10585#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
10586#define PORT_CLK_SEL_WRPLL1 (4 << 29)
10587#define PORT_CLK_SEL_WRPLL2 (5 << 29)
10588#define PORT_CLK_SEL_NONE (7 << 29)
10589#define PORT_CLK_SEL_MASK (7 << 29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -030010590
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010591/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
10592#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
10593#define DDI_CLK_SEL_NONE (0x0 << 28)
10594#define DDI_CLK_SEL_MG (0x8 << 28)
Paulo Zanoni1fa11ee2018-05-21 17:25:48 -070010595#define DDI_CLK_SEL_TBT_162 (0xC << 28)
10596#define DDI_CLK_SEL_TBT_270 (0xD << 28)
10597#define DDI_CLK_SEL_TBT_540 (0xE << 28)
10598#define DDI_CLK_SEL_TBT_810 (0xF << 28)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010599#define DDI_CLK_SEL_MASK (0xF << 28)
10600
Paulo Zanonibb523fc2012-10-23 18:29:56 -020010601/* Transcoder clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010602#define _TRANS_CLK_SEL_A 0x46140
10603#define _TRANS_CLK_SEL_B 0x46144
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010604#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
Paulo Zanonibb523fc2012-10-23 18:29:56 -020010605/* For each transcoder, we need to select the corresponding port clock */
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010606#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
10607#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
Mahesh Kumardf16b632019-07-12 18:09:20 -070010608#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
10609#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
10610
Eugeni Dodonovfec91812012-03-29 12:32:33 -030010611
Ville Syrjälä7f1052a2016-04-26 19:46:32 +030010612#define CDCLK_FREQ _MMIO(0x46200)
10613
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010614#define _TRANSA_MSA_MISC 0x60410
10615#define _TRANSB_MSA_MISC 0x61410
10616#define _TRANSC_MSA_MISC 0x62410
10617#define _TRANS_EDP_MSA_MISC 0x6f410
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010618#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
Ville Syrjälä3e706df2019-07-18 17:50:47 +030010619/* See DP_MSA_MISC_* for the bit definitions */
Paulo Zanonidae84792012-10-15 15:51:30 -030010620
José Roberto de Souza1d53ccd2021-06-16 13:31:55 -070010621#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
10622#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
10623#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
10624#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
10625#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
10626#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
10627#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
10628
Eugeni Dodonov90e8d312012-03-29 12:32:35 -030010629/* LCPLL Control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010630#define LCPLL_CTL _MMIO(0x130040)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010631#define LCPLL_PLL_DISABLE (1 << 31)
10632#define LCPLL_PLL_LOCK (1 << 30)
Ville Syrjälä4a95e362019-06-10 16:36:09 +030010633#define LCPLL_REF_NON_SSC (0 << 28)
10634#define LCPLL_REF_BCLK (2 << 28)
10635#define LCPLL_REF_PCH_SSC (3 << 28)
10636#define LCPLL_REF_MASK (3 << 28)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010637#define LCPLL_CLK_FREQ_MASK (3 << 26)
10638#define LCPLL_CLK_FREQ_450 (0 << 26)
10639#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
10640#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
10641#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
10642#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
10643#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
10644#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
10645#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
10646#define LCPLL_CD_SOURCE_FCLK (1 << 21)
10647#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
Paulo Zanonibe256dc2013-07-23 11:19:26 -030010648
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010649/*
10650 * SKL Clocks
10651 */
10652
10653/* CDCLK_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010654#define CDCLK_CTL _MMIO(0x46000)
Paulo Zanoni186a2772018-02-06 17:33:46 -020010655#define CDCLK_FREQ_SEL_MASK (3 << 26)
10656#define CDCLK_FREQ_450_432 (0 << 26)
10657#define CDCLK_FREQ_540 (1 << 26)
10658#define CDCLK_FREQ_337_308 (2 << 26)
10659#define CDCLK_FREQ_675_617 (3 << 26)
10660#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
10661#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
10662#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
10663#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
10664#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
10665#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
10666#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
Ville Syrjälä7fe62752016-05-11 22:44:51 +030010667#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
Matt Roper385ba622019-08-29 17:48:28 -070010668#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
Paulo Zanoni186a2772018-02-06 17:33:46 -020010669#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
Matt Roper385ba622019-08-29 17:48:28 -070010670#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
10671#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
Paulo Zanoni186a2772018-02-06 17:33:46 -020010672#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
Ville Syrjälä7fe62752016-05-11 22:44:51 +030010673#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
Vandana Kannanf8437dd12014-11-24 13:37:39 +053010674
Mika Kahola2060a682021-11-19 15:13:46 +020010675/* CDCLK_SQUASH_CTL */
10676#define CDCLK_SQUASH_CTL _MMIO(0x46008)
10677#define CDCLK_SQUASH_ENABLE REG_BIT(31)
10678#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
10679#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
10680#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
10681#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
10682
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010683/* LCPLL_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010684#define LCPLL1_CTL _MMIO(0x46010)
10685#define LCPLL2_CTL _MMIO(0x46014)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010686#define LCPLL_PLL_ENABLE (1 << 31)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010687
10688/* DPLL control1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010689#define DPLL_CTRL1 _MMIO(0x6C058)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010690#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
10691#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
10692#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
10693#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
10694#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
10695#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
Damien Lespiau71cd8422015-04-30 16:39:17 +010010696#define DPLL_CTRL1_LINK_RATE_2700 0
10697#define DPLL_CTRL1_LINK_RATE_1350 1
10698#define DPLL_CTRL1_LINK_RATE_810 2
10699#define DPLL_CTRL1_LINK_RATE_1620 3
10700#define DPLL_CTRL1_LINK_RATE_1080 4
10701#define DPLL_CTRL1_LINK_RATE_2160 5
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010702
10703/* DPLL control2 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010704#define DPLL_CTRL2 _MMIO(0x6C05C)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010705#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
10706#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
10707#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
10708#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
10709#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010710
10711/* DPLL Status */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010712#define DPLL_STATUS _MMIO(0x6C060)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010713#define DPLL_LOCK(id) (1 << ((id) * 8))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010714
10715/* DPLL cfg */
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010716#define _DPLL1_CFGCR1 0x6C040
10717#define _DPLL2_CFGCR1 0x6C048
10718#define _DPLL3_CFGCR1 0x6C050
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010719#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
10720#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
10721#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010722#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
10723
Ville Syrjälä086f8e82015-11-04 23:20:01 +020010724#define _DPLL1_CFGCR2 0x6C044
10725#define _DPLL2_CFGCR2 0x6C04C
10726#define _DPLL3_CFGCR2 0x6C054
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070010727#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
10728#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
10729#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
10730#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
10731#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
10732#define DPLL_CFGCR2_KDIV_5 (0 << 5)
10733#define DPLL_CFGCR2_KDIV_2 (1 << 5)
10734#define DPLL_CFGCR2_KDIV_3 (2 << 5)
10735#define DPLL_CFGCR2_KDIV_1 (3 << 5)
10736#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
10737#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
10738#define DPLL_CFGCR2_PDIV_1 (0 << 2)
10739#define DPLL_CFGCR2_PDIV_2 (1 << 2)
10740#define DPLL_CFGCR2_PDIV_3 (2 << 2)
10741#define DPLL_CFGCR2_PDIV_7 (4 << 2)
Imre Deak7a8a95f2020-10-06 04:35:55 +030010742#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +000010743#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
10744
Lyudeda3b8912016-02-04 10:43:21 -050010745#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020010746#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
Satheeshakrishna M540e7322014-11-13 14:55:16 +000010747
Lucas De Marchi11ffe972020-11-06 13:00:06 -080010748/* ICL Clocks */
Matt Roperbefa3722019-07-09 11:39:31 -070010749#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
Aditya Swarupd6d2bc92021-01-25 06:07:49 -080010750#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
Matt Ropercd803bb2020-07-16 15:05:47 -070010751#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
Ville Syrjälä320c6702020-10-28 23:33:05 +020010752#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
Mahesh Kumaraaf70b92019-07-12 18:09:21 -070010753 (tc_port) + 12 : \
Ville Syrjälä320c6702020-10-28 23:33:05 +020010754 (tc_port) - TC_PORT_4 + 21))
Matt Roperbefa3722019-07-09 11:39:31 -070010755#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
10756#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10757#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
Matt Ropercd803bb2020-07-16 15:05:47 -070010758#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
10759#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
10760 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10761#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
10762 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
Matt Roperbefa3722019-07-09 11:39:31 -070010763
Lucas De Marchi11ffe972020-11-06 13:00:06 -080010764/*
10765 * DG1 Clocks
10766 * First registers controls the first A and B, while the second register
10767 * controls the phy C and D. The bits on these registers are the
10768 * same, but refer to different phys
10769 */
10770#define _DG1_DPCLKA_CFGCR0 0x164280
10771#define _DG1_DPCLKA1_CFGCR0 0x16C280
10772#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
10773#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
Lucas De Marchi11ffe972020-11-06 13:00:06 -080010774#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
10775 _DG1_DPCLKA_CFGCR0, \
10776 _DG1_DPCLKA1_CFGCR0)
10777#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
10778#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
10779#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10780#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
Lucas De Marchi11ffe972020-11-06 13:00:06 -080010781
Aditya Swarupd6d2bc92021-01-25 06:07:49 -080010782/* ADLS Clocks */
10783#define _ADLS_DPCLKA_CFGCR0 0x164280
10784#define _ADLS_DPCLKA_CFGCR1 0x1642BC
10785#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
10786 _ADLS_DPCLKA_CFGCR0, \
10787 _ADLS_DPCLKA_CFGCR1)
10788#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
10789/* ADLS DPCLKA_CFGCR0 DDI mask */
10790#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
10791#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
10792#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
10793/* ADLS DPCLKA_CFGCR1 DDI mask */
10794#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
10795#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
10796#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
10797 ADLS_DPCLKA_DDIA_SEL_MASK, \
10798 ADLS_DPCLKA_DDIB_SEL_MASK, \
10799 ADLS_DPCLKA_DDII_SEL_MASK, \
10800 ADLS_DPCLKA_DDIJ_SEL_MASK, \
10801 ADLS_DPCLKA_DDIK_SEL_MASK)
10802
Lucas De Marchi8de358c2021-07-29 16:39:35 -070010803/* ICL PLL */
Rodrigo Vivia927c922017-06-09 15:26:04 -070010804#define DPLL0_ENABLE 0x46010
10805#define DPLL1_ENABLE 0x46014
Aditya Swarup80d0f7652021-01-25 06:07:48 -080010806#define _ADLS_DPLL2_ENABLE 0x46018
10807#define _ADLS_DPLL3_ENABLE 0x46030
Rodrigo Vivia927c922017-06-09 15:26:04 -070010808#define PLL_ENABLE (1 << 31)
10809#define PLL_LOCK (1 << 30)
10810#define PLL_POWER_ENABLE (1 << 27)
10811#define PLL_POWER_STATE (1 << 26)
Lucas De Marchi8de358c2021-07-29 16:39:35 -070010812#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
Aditya Swarup80d0f7652021-01-25 06:07:48 -080010813 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
Rodrigo Vivia927c922017-06-09 15:26:04 -070010814
Matt Roper29081002021-07-23 10:42:32 -070010815#define _DG2_PLL3_ENABLE 0x4601C
10816
10817#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10818 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
10819
Paulo Zanoni1fa11ee2018-05-21 17:25:48 -070010820#define TBT_PLL_ENABLE _MMIO(0x46020)
10821
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010822#define _MG_PLL1_ENABLE 0x46030
10823#define _MG_PLL2_ENABLE 0x46034
10824#define _MG_PLL3_ENABLE 0x46038
10825#define _MG_PLL4_ENABLE 0x4603C
10826/* Bits are the same as DPLL0_ENABLE */
Lucas De Marchi584fca12019-01-25 14:24:41 -080010827#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010828 _MG_PLL2_ENABLE)
10829
Lucas De Marchi0dac17a2020-10-14 12:19:32 -070010830/* DG1 PLL */
10831#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10832 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
10833
Anusha Srivatsa226c8322021-05-18 17:06:22 -070010834/* ADL-P Type C PLL */
10835#define PORTTC1_PLL_ENABLE 0x46038
10836#define PORTTC2_PLL_ENABLE 0x46040
10837
10838#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
10839 PORTTC1_PLL_ENABLE, \
10840 PORTTC2_PLL_ENABLE)
10841
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010842#define _MG_REFCLKIN_CTL_PORT1 0x16892C
10843#define _MG_REFCLKIN_CTL_PORT2 0x16992C
10844#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
10845#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
10846#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
Imre Deakbd99ce02018-06-19 19:41:15 +030010847#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010848#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10849 _MG_REFCLKIN_CTL_PORT1, \
10850 _MG_REFCLKIN_CTL_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010851
10852#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
10853#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
10854#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
10855#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
10856#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
Imre Deakbd99ce02018-06-19 19:41:15 +030010857#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010858#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
Imre Deakbd99ce02018-06-19 19:41:15 +030010859#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010860#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10861 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10862 _MG_CLKTOP2_CORECLKCTL1_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010863
10864#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
10865#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
10866#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
10867#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
10868#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
Imre Deakbd99ce02018-06-19 19:41:15 +030010869#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010870#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
Imre Deakbd99ce02018-06-19 19:41:15 +030010871#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
Imre Deakbd99ce02018-06-19 19:41:15 +030010872#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
Manasi Navarebcaad532018-08-17 14:52:08 -070010873#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
10874#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
10875#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
10876#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010877#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
Manasi Navare7b19f542018-08-17 14:52:09 -070010878#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
Imre Deakbd99ce02018-06-19 19:41:15 +030010879#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010880#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10881 _MG_CLKTOP2_HSCLKCTL_PORT1, \
10882 _MG_CLKTOP2_HSCLKCTL_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010883
10884#define _MG_PLL_DIV0_PORT1 0x168A00
10885#define _MG_PLL_DIV0_PORT2 0x169A00
10886#define _MG_PLL_DIV0_PORT3 0x16AA00
10887#define _MG_PLL_DIV0_PORT4 0x16BA00
10888#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
Manasi Navare7b19f542018-08-17 14:52:09 -070010889#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
10890#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010891#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
Manasi Navare7b19f542018-08-17 14:52:09 -070010892#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010893#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010894#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10895 _MG_PLL_DIV0_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010896
10897#define _MG_PLL_DIV1_PORT1 0x168A04
10898#define _MG_PLL_DIV1_PORT2 0x169A04
10899#define _MG_PLL_DIV1_PORT3 0x16AA04
10900#define _MG_PLL_DIV1_PORT4 0x16BA04
10901#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
10902#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
10903#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
10904#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
10905#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
10906#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
Manasi Navare7b19f542018-08-17 14:52:09 -070010907#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010908#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010909#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10910 _MG_PLL_DIV1_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010911
10912#define _MG_PLL_LF_PORT1 0x168A08
10913#define _MG_PLL_LF_PORT2 0x169A08
10914#define _MG_PLL_LF_PORT3 0x16AA08
10915#define _MG_PLL_LF_PORT4 0x16BA08
10916#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
10917#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
10918#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
10919#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
10920#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
10921#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010922#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10923 _MG_PLL_LF_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010924
10925#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
10926#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
10927#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
10928#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
10929#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
10930#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
10931#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
10932#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
10933#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
10934#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010935#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10936 _MG_PLL_FRAC_LOCK_PORT1, \
10937 _MG_PLL_FRAC_LOCK_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010938
10939#define _MG_PLL_SSC_PORT1 0x168A10
10940#define _MG_PLL_SSC_PORT2 0x169A10
10941#define _MG_PLL_SSC_PORT3 0x16AA10
10942#define _MG_PLL_SSC_PORT4 0x16BA10
10943#define MG_PLL_SSC_EN (1 << 28)
10944#define MG_PLL_SSC_TYPE(x) ((x) << 26)
10945#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
10946#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
10947#define MG_PLL_SSC_FLLEN (1 << 9)
10948#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010949#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10950 _MG_PLL_SSC_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010951
10952#define _MG_PLL_BIAS_PORT1 0x168A14
10953#define _MG_PLL_BIAS_PORT2 0x169A14
10954#define _MG_PLL_BIAS_PORT3 0x16AA14
10955#define _MG_PLL_BIAS_PORT4 0x16BA14
10956#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
Imre Deakbd99ce02018-06-19 19:41:15 +030010957#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010958#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
Imre Deakbd99ce02018-06-19 19:41:15 +030010959#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010960#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
Imre Deakbd99ce02018-06-19 19:41:15 +030010961#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010962#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
10963#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
Imre Deakbd99ce02018-06-19 19:41:15 +030010964#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010965#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
Imre Deakbd99ce02018-06-19 19:41:15 +030010966#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010967#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
Imre Deakbd99ce02018-06-19 19:41:15 +030010968#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010969#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10970 _MG_PLL_BIAS_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010971
10972#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
10973#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
10974#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
10975#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
10976#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
10977#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
10978#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
10979#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
10980#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
Lucas De Marchi584fca12019-01-25 14:24:41 -080010981#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10982 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10983 _MG_PLL_TDC_COLDST_BIAS_PORT2)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010984
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070010985#define _ICL_DPLL0_CFGCR0 0x164000
10986#define _ICL_DPLL1_CFGCR0 0x164080
10987#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10988 _ICL_DPLL1_CFGCR0)
Lucas De Marchia4d082f2021-07-28 14:59:45 -070010989#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
10990#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
10991#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
10992#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
10993#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
10994#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
10995#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
10996#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
10997#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
10998#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
10999#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
11000#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
11001#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
11002#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
11003#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
11004#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070011005
11006#define _ICL_DPLL0_CFGCR1 0x164004
11007#define _ICL_DPLL1_CFGCR1 0x164084
11008#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
11009 _ICL_DPLL1_CFGCR1)
Lucas De Marchia4d082f2021-07-28 14:59:45 -070011010#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
11011#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
11012#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
11013#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
11014#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
11015#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
11016#define DPLL_CFGCR1_KDIV_SHIFT (6)
11017#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
11018#define DPLL_CFGCR1_KDIV_1 (1 << 6)
11019#define DPLL_CFGCR1_KDIV_2 (2 << 6)
11020#define DPLL_CFGCR1_KDIV_3 (4 << 6)
11021#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
11022#define DPLL_CFGCR1_PDIV_SHIFT (2)
11023#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
11024#define DPLL_CFGCR1_PDIV_2 (1 << 2)
11025#define DPLL_CFGCR1_PDIV_3 (2 << 2)
11026#define DPLL_CFGCR1_PDIV_5 (4 << 2)
11027#define DPLL_CFGCR1_PDIV_7 (8 << 2)
11028#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
11029#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
11030#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
Paulo Zanoni78b60ce2018-03-28 14:57:57 -070011031
Lucas De Marchi36ca5332019-07-11 10:31:14 -070011032#define _TGL_DPLL0_CFGCR0 0x164284
11033#define _TGL_DPLL1_CFGCR0 0x16428C
Lucas De Marchi36ca5332019-07-11 10:31:14 -070011034#define _TGL_TBTPLL_CFGCR0 0x16429C
11035#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11036 _TGL_DPLL1_CFGCR0, \
11037 _TGL_TBTPLL_CFGCR0)
Matt Ropere66f6092020-07-16 15:05:49 -070011038#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
11039 _TGL_DPLL1_CFGCR0)
Lucas De Marchi36ca5332019-07-11 10:31:14 -070011040
11041#define _TGL_DPLL0_CFGCR1 0x164288
11042#define _TGL_DPLL1_CFGCR1 0x164290
Lucas De Marchi36ca5332019-07-11 10:31:14 -070011043#define _TGL_TBTPLL_CFGCR1 0x1642A0
11044#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11045 _TGL_DPLL1_CFGCR1, \
11046 _TGL_TBTPLL_CFGCR1)
Matt Ropere66f6092020-07-16 15:05:49 -070011047#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
11048 _TGL_DPLL1_CFGCR1)
Lucas De Marchi36ca5332019-07-11 10:31:14 -070011049
Aditya Swarup049c6512020-10-14 12:19:30 -070011050#define _DG1_DPLL2_CFGCR0 0x16C284
11051#define _DG1_DPLL3_CFGCR0 0x16C28C
11052#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11053 _TGL_DPLL1_CFGCR0, \
11054 _DG1_DPLL2_CFGCR0, \
11055 _DG1_DPLL3_CFGCR0)
11056
11057#define _DG1_DPLL2_CFGCR1 0x16C288
11058#define _DG1_DPLL3_CFGCR1 0x16C290
11059#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11060 _TGL_DPLL1_CFGCR1, \
11061 _DG1_DPLL2_CFGCR1, \
11062 _DG1_DPLL3_CFGCR1)
11063
Aditya Swarup80d0f7652021-01-25 06:07:48 -080011064/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
11065#define _ADLS_DPLL3_CFGCR0 0x1642C0
11066#define _ADLS_DPLL4_CFGCR0 0x164294
11067#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11068 _TGL_DPLL1_CFGCR0, \
11069 _ADLS_DPLL4_CFGCR0, \
11070 _ADLS_DPLL3_CFGCR0)
11071
11072#define _ADLS_DPLL3_CFGCR1 0x1642C4
11073#define _ADLS_DPLL4_CFGCR1 0x164298
11074#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11075 _TGL_DPLL1_CFGCR1, \
11076 _ADLS_DPLL4_CFGCR1, \
11077 _ADLS_DPLL3_CFGCR1)
11078
Vandita Kulkarnif15a4eb2019-09-20 13:58:08 -070011079#define _DKL_PHY1_BASE 0x168000
11080#define _DKL_PHY2_BASE 0x169000
11081#define _DKL_PHY3_BASE 0x16A000
11082#define _DKL_PHY4_BASE 0x16B000
11083#define _DKL_PHY5_BASE 0x16C000
11084#define _DKL_PHY6_BASE 0x16D000
11085
11086/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
11087#define _DKL_PLL_DIV0 0x200
11088#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
11089#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
11090#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
11091#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
11092#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
11093#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
11094#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
11095#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
11096#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
11097#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11098 _DKL_PHY2_BASE) + \
11099 _DKL_PLL_DIV0)
11100
11101#define _DKL_PLL_DIV1 0x204
11102#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
11103#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
11104#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
11105#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
11106#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11107 _DKL_PHY2_BASE) + \
11108 _DKL_PLL_DIV1)
11109
11110#define _DKL_PLL_SSC 0x210
11111#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
11112#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
11113#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
11114#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
11115#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
11116#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
11117#define DKL_PLL_SSC_EN (1 << 9)
11118#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11119 _DKL_PHY2_BASE) + \
11120 _DKL_PLL_SSC)
11121
11122#define _DKL_PLL_BIAS 0x214
11123#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
11124#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
11125#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
11126#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
11127#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11128 _DKL_PHY2_BASE) + \
11129 _DKL_PLL_BIAS)
11130
11131#define _DKL_PLL_TDC_COLDST_BIAS 0x218
11132#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
11133#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
11134#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
11135#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
11136#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
11137 _DKL_PHY1_BASE, \
11138 _DKL_PHY2_BASE) + \
11139 _DKL_PLL_TDC_COLDST_BIAS)
11140
11141#define _DKL_REFCLKIN_CTL 0x12C
11142/* Bits are the same as MG_REFCLKIN_CTL */
11143#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
11144 _DKL_PHY1_BASE, \
11145 _DKL_PHY2_BASE) + \
11146 _DKL_REFCLKIN_CTL)
11147
11148#define _DKL_CLKTOP2_HSCLKCTL 0xD4
11149/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
11150#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
11151 _DKL_PHY1_BASE, \
11152 _DKL_PHY2_BASE) + \
11153 _DKL_CLKTOP2_HSCLKCTL)
11154
11155#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
11156/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
11157#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
11158 _DKL_PHY1_BASE, \
11159 _DKL_PHY2_BASE) + \
11160 _DKL_CLKTOP2_CORECLKCTL1)
11161
11162#define _DKL_TX_DPCNTL0 0x2C0
11163#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
11164#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
11165#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
11166#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
11167#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
11168#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
11169#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
11170 _DKL_PHY1_BASE, \
11171 _DKL_PHY2_BASE) + \
11172 _DKL_TX_DPCNTL0)
11173
11174#define _DKL_TX_DPCNTL1 0x2C4
11175/* Bits are the same as DKL_TX_DPCNTRL0 */
11176#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
11177 _DKL_PHY1_BASE, \
11178 _DKL_PHY2_BASE) + \
11179 _DKL_TX_DPCNTL1)
11180
José Roberto de Souzae26602b2022-01-13 09:48:26 -080011181#define _DKL_TX_DPCNTL2 0x2C8
11182#define DKL_TX_DP20BITMODE REG_BIT(2)
11183#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
11184#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
11185#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
11186#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
Vandita Kulkarnif15a4eb2019-09-20 13:58:08 -070011187#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
11188 _DKL_PHY1_BASE, \
11189 _DKL_PHY2_BASE) + \
11190 _DKL_TX_DPCNTL2)
11191
11192#define _DKL_TX_FW_CALIB 0x2F8
11193#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
11194#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
11195 _DKL_PHY1_BASE, \
11196 _DKL_PHY2_BASE) + \
11197 _DKL_TX_FW_CALIB)
11198
José Roberto de Souza2d69c422019-10-21 15:34:08 -070011199#define _DKL_TX_PMD_LANE_SUS 0xD00
11200#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
11201 _DKL_PHY1_BASE, \
11202 _DKL_PHY2_BASE) + \
11203 _DKL_TX_PMD_LANE_SUS)
11204
Vandita Kulkarnif15a4eb2019-09-20 13:58:08 -070011205#define _DKL_TX_DW17 0xDC4
11206#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
11207 _DKL_PHY1_BASE, \
11208 _DKL_PHY2_BASE) + \
11209 _DKL_TX_DW17)
11210
11211#define _DKL_TX_DW18 0xDC8
11212#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
11213 _DKL_PHY1_BASE, \
11214 _DKL_PHY2_BASE) + \
11215 _DKL_TX_DW18)
11216
11217#define _DKL_DP_MODE 0xA0
Vandita Kulkarnif15a4eb2019-09-20 13:58:08 -070011218#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
11219 _DKL_PHY1_BASE, \
11220 _DKL_PHY2_BASE) + \
11221 _DKL_DP_MODE)
11222
11223#define _DKL_CMN_UC_DW27 0x36C
11224#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
11225#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
11226 _DKL_PHY1_BASE, \
11227 _DKL_PHY2_BASE) + \
11228 _DKL_CMN_UC_DW27)
11229
11230/*
11231 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
11232 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
11233 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
11234 * bits that point the 4KB window into the full PHY register space.
11235 */
11236#define _HIP_INDEX_REG0 0x1010A0
11237#define _HIP_INDEX_REG1 0x1010A4
11238#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
11239 : _HIP_INDEX_REG1)
11240#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
11241#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
11242
Vandana Kannanf8437dd12014-11-24 13:37:39 +053011243/* BXT display engine PLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011244#define BXT_DE_PLL_CTL _MMIO(0x6d000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +053011245#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
11246#define BXT_DE_PLL_RATIO_MASK 0xff
11247
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011248#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
Vandana Kannanf8437dd12014-11-24 13:37:39 +053011249#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
11250#define BXT_DE_PLL_LOCK (1 << 30)
Stanislav Lisovskiyd62686b2021-06-03 09:50:38 +030011251#define BXT_DE_PLL_FREQ_REQ (1 << 23)
11252#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
Lucas De Marchi1d895092021-07-28 14:59:23 -070011253#define ICL_CDCLK_PLL_RATIO(x) (x)
11254#define ICL_CDCLK_PLL_RATIO_MASK 0xff
Vandana Kannanf8437dd12014-11-24 13:37:39 +053011255
A.Sunil Kamath664326f2014-11-24 13:37:44 +053011256/* GEN9 DC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011257#define DC_STATE_EN _MMIO(0x45504)
Imre Deak13ae3a02015-11-04 19:24:16 +020011258#define DC_STATE_DISABLE 0
Anshuman Guptae45e0002019-10-07 15:16:07 +053011259#define DC_STATE_EN_DC3CO REG_BIT(30)
11260#define DC_STATE_DC3CO_STATUS REG_BIT(29)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070011261#define DC_STATE_EN_UPTO_DC5 (1 << 0)
11262#define DC_STATE_EN_DC9 (1 << 3)
11263#define DC_STATE_EN_UPTO_DC6 (2 << 0)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +053011264#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
11265
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011266#define DC_STATE_DEBUG _MMIO(0x45520)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070011267#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
11268#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +053011269
Mahesh Kumarcbfa59d2018-08-24 15:02:21 +053011270#define BXT_D_CR_DRP0_DUNIT8 0x1000
11271#define BXT_D_CR_DRP0_DUNIT9 0x1200
11272#define BXT_D_CR_DRP0_DUNIT_START 8
11273#define BXT_D_CR_DRP0_DUNIT_END 11
11274#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
11275 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
11276 BXT_D_CR_DRP0_DUNIT9))
11277#define BXT_DRAM_RANK_MASK 0x3
11278#define BXT_DRAM_RANK_SINGLE 0x1
11279#define BXT_DRAM_RANK_DUAL 0x3
11280#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
11281#define BXT_DRAM_WIDTH_SHIFT 4
11282#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
11283#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
11284#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
11285#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
11286#define BXT_DRAM_SIZE_MASK (0x7 << 6)
11287#define BXT_DRAM_SIZE_SHIFT 6
Ville Syrjälä88603432019-03-06 22:35:44 +020011288#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
11289#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
11290#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
11291#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
11292#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
Ville Syrjäläb185a352019-03-06 22:35:51 +020011293#define BXT_DRAM_TYPE_MASK (0x7 << 22)
11294#define BXT_DRAM_TYPE_SHIFT 22
11295#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
11296#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
11297#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
11298#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
Mahesh Kumarcbfa59d2018-08-24 15:02:21 +053011299
Mahesh Kumar5771caf2018-08-24 15:02:22 +053011300#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
Clint Taylor4de06242021-07-08 10:52:26 -070011301#define DG1_GEAR_TYPE REG_BIT(16)
Mahesh Kumar5771caf2018-08-24 15:02:22 +053011302
Ville Syrjäläb185a352019-03-06 22:35:51 +020011303#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
11304#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
11305#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
11306#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
11307#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
11308#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
11309
Mahesh Kumar5771caf2018-08-24 15:02:22 +053011310#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
11311#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
11312#define SKL_DRAM_S_SHIFT 16
11313#define SKL_DRAM_SIZE_MASK 0x3F
11314#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
11315#define SKL_DRAM_WIDTH_SHIFT 8
11316#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
11317#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
11318#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
11319#define SKL_DRAM_RANK_MASK (0x1 << 10)
11320#define SKL_DRAM_RANK_SHIFT 10
Ville Syrjälä6d9c1e92019-03-06 22:35:50 +020011321#define SKL_DRAM_RANK_1 (0x0 << 10)
11322#define SKL_DRAM_RANK_2 (0x1 << 10)
11323#define SKL_DRAM_RANK_MASK (0x1 << 10)
Lucas De Marchia2db1942021-07-28 14:59:41 -070011324#define ICL_DRAM_SIZE_MASK 0x7F
11325#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
11326#define ICL_DRAM_WIDTH_SHIFT 7
11327#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
11328#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
11329#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
11330#define ICL_DRAM_RANK_MASK (0x3 << 9)
11331#define ICL_DRAM_RANK_SHIFT 9
11332#define ICL_DRAM_RANK_1 (0x0 << 9)
11333#define ICL_DRAM_RANK_2 (0x1 << 9)
11334#define ICL_DRAM_RANK_3 (0x2 << 9)
11335#define ICL_DRAM_RANK_4 (0x3 << 9)
Mahesh Kumar5771caf2018-08-24 15:02:22 +053011336
Clint Taylor4de06242021-07-08 10:52:26 -070011337#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
11338#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
11339#define DG1_QCLK_REFERENCE REG_BIT(10)
11340
11341#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
11342#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
11343#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
11344#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
11345#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
11346#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
11347
Jani Nikula54b3f0e2020-11-30 13:16:01 +020011348/*
11349 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
11350 * since on HSW we can't write to it using intel_uncore_write.
11351 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011352#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
11353#define D_COMP_BDW _MMIO(0x138144)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070011354#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
11355#define D_COMP_COMP_FORCE (1 << 8)
11356#define D_COMP_COMP_DISABLE (1 << 0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -030011357
Eugeni Dodonov69e94b72012-03-29 12:32:37 -030011358/* Pipe WM_LINETIME - watermark line time */
Ville Syrjälä0560b0c2020-01-20 19:47:11 +020011359#define _WM_LINETIME_A 0x45270
11360#define _WM_LINETIME_B 0x45274
11361#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
11362#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
11363#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
11364#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
11365#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
Eugeni Dodonov96d6e352012-03-29 12:32:38 -030011366
11367/* SFUSE_STRAP */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011368#define SFUSE_STRAP _MMIO(0xc2014)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070011369#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
11370#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
11371#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
11372#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
11373#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
11374#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
11375#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
11376#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -030011377
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011378#define WM_MISC _MMIO(0x45260)
Paulo Zanoni801bcff2013-05-31 10:08:35 -030011379#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
11380
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011381#define WM_DBG _MMIO(0x45280)
Paulo Zanoni5ee8ee82018-06-18 11:09:43 -070011382#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
11383#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
11384#define WM_DBG_DISALLOW_SPRITE (1 << 2)
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -030011385
Ville Syrjälä86d3efc2013-01-18 19:11:38 +020011386/* pipe CSC */
11387#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
11388#define _PIPE_A_CSC_COEFF_BY 0x49014
11389#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
11390#define _PIPE_A_CSC_COEFF_BU 0x4901c
11391#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
11392#define _PIPE_A_CSC_COEFF_BV 0x49024
Uma Shankar255fcfb2019-02-11 19:20:23 +053011393
Ville Syrjälä86d3efc2013-01-18 19:11:38 +020011394#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjäläaf28cc42019-07-18 17:50:52 +030011395#define ICL_CSC_ENABLE (1 << 31) /* icl+ */
11396#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
11397#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
11398#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
11399#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
Uma Shankar255fcfb2019-02-11 19:20:23 +053011400
Ville Syrjälä86d3efc2013-01-18 19:11:38 +020011401#define _PIPE_A_CSC_PREOFF_HI 0x49030
11402#define _PIPE_A_CSC_PREOFF_ME 0x49034
11403#define _PIPE_A_CSC_PREOFF_LO 0x49038
11404#define _PIPE_A_CSC_POSTOFF_HI 0x49040
11405#define _PIPE_A_CSC_POSTOFF_ME 0x49044
11406#define _PIPE_A_CSC_POSTOFF_LO 0x49048
11407
11408#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
11409#define _PIPE_B_CSC_COEFF_BY 0x49114
11410#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
11411#define _PIPE_B_CSC_COEFF_BU 0x4911c
11412#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
11413#define _PIPE_B_CSC_COEFF_BV 0x49124
11414#define _PIPE_B_CSC_MODE 0x49128
11415#define _PIPE_B_CSC_PREOFF_HI 0x49130
11416#define _PIPE_B_CSC_PREOFF_ME 0x49134
11417#define _PIPE_B_CSC_PREOFF_LO 0x49138
11418#define _PIPE_B_CSC_POSTOFF_HI 0x49140
11419#define _PIPE_B_CSC_POSTOFF_ME 0x49144
11420#define _PIPE_B_CSC_POSTOFF_LO 0x49148
11421
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011422#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
11423#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
11424#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
11425#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
11426#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
11427#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
11428#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
11429#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
11430#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
11431#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
11432#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
11433#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
11434#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +020011435
Uma Shankara91de582019-02-11 19:20:24 +053011436/* Pipe Output CSC */
11437#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
11438#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
11439#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
11440#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
11441#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
11442#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
11443#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
11444#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
11445#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
11446#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
11447#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
11448#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
11449
11450#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
11451#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
11452#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
11453#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
11454#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
11455#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
11456#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
11457#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
11458#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
11459#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
11460#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
11461#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
11462
11463#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
11464 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
11465 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
11466#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
11467 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
11468 _PIPE_B_OUTPUT_CSC_COEFF_BY)
11469#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
11470 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
11471 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
11472#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
11473 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
11474 _PIPE_B_OUTPUT_CSC_COEFF_BU)
11475#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
11476 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
11477 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
11478#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
11479 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
11480 _PIPE_B_OUTPUT_CSC_COEFF_BV)
11481#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
11482 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
11483 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
11484#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
11485 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
11486 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
11487#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
11488 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
11489 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
11490#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
11491 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
11492 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
11493#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
11494 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
11495 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
11496#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
11497 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
11498 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
11499
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000011500/* pipe degamma/gamma LUTs on IVB+ */
11501#define _PAL_PREC_INDEX_A 0x4A400
11502#define _PAL_PREC_INDEX_B 0x4AC00
11503#define _PAL_PREC_INDEX_C 0x4B400
11504#define PAL_PREC_10_12_BIT (0 << 31)
11505#define PAL_PREC_SPLIT_MODE (1 << 31)
11506#define PAL_PREC_AUTO_INCREMENT (1 << 15)
Ander Conselvan de Oliveira2fcb2062017-01-26 13:24:23 +020011507#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
Ville Syrjälä5bda1ac2019-04-01 23:02:26 +030011508#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000011509#define _PAL_PREC_DATA_A 0x4A404
11510#define _PAL_PREC_DATA_B 0x4AC04
11511#define _PAL_PREC_DATA_C 0x4B404
11512#define _PAL_PREC_GC_MAX_A 0x4A410
11513#define _PAL_PREC_GC_MAX_B 0x4AC10
11514#define _PAL_PREC_GC_MAX_C 0x4B410
Swati Sharma4bb6a9d2019-09-04 00:52:57 +053011515#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
11516#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
11517#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000011518#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
11519#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
11520#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
Ander Conselvan de Oliveira9751baf2017-01-27 11:02:30 +020011521#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
11522#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
11523#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000011524
11525#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
11526#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
11527#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
11528#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
Uma Shankar502da132019-03-29 19:59:16 +053011529#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000011530
Ander Conselvan de Oliveira9751baf2017-01-27 11:02:30 +020011531#define _PRE_CSC_GAMC_INDEX_A 0x4A484
11532#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
11533#define _PRE_CSC_GAMC_INDEX_C 0x4B484
11534#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
11535#define _PRE_CSC_GAMC_DATA_A 0x4A488
11536#define _PRE_CSC_GAMC_DATA_B 0x4AC88
11537#define _PRE_CSC_GAMC_DATA_C 0x4B488
11538
11539#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
11540#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
11541
Uma Shankar377c70e2019-06-12 12:14:58 +053011542/* ICL Multi segmented gamma */
11543#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
11544#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
11545#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
11546#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
11547
11548#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
11549#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
Swati Sharmab4ab7aa2020-03-17 19:27:36 +053011550#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
11551#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
11552#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
11553#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
11554#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
11555#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
Uma Shankar377c70e2019-06-12 12:14:58 +053011556
11557#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
11558 _PAL_PREC_MULTI_SEG_INDEX_A, \
11559 _PAL_PREC_MULTI_SEG_INDEX_B)
11560#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
11561 _PAL_PREC_MULTI_SEG_DATA_A, \
11562 _PAL_PREC_MULTI_SEG_DATA_B)
11563
Anshuman Gupta6eba56f2021-09-24 12:14:49 -070011564#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
11565
11566/* Plane CSC Registers */
11567#define _PLANE_CSC_RY_GY_1_A 0x70210
11568#define _PLANE_CSC_RY_GY_2_A 0x70310
11569
11570#define _PLANE_CSC_RY_GY_1_B 0x71210
11571#define _PLANE_CSC_RY_GY_2_B 0x71310
11572
11573#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
11574 _PLANE_CSC_RY_GY_1_B)
11575#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
11576 _PLANE_INPUT_CSC_RY_GY_2_B)
11577#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
11578 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
11579 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
11580
11581#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
11582#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
11583
11584#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
11585#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
11586
11587#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
11588 _PLANE_CSC_PREOFF_HI_1_B)
11589#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
11590 _PLANE_CSC_PREOFF_HI_2_B)
11591#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
11592 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
11593 (index) * 4)
11594
11595#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
11596#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
11597
11598#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
11599#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
11600
11601#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
11602 _PLANE_CSC_POSTOFF_HI_1_B)
11603#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
11604 _PLANE_CSC_POSTOFF_HI_2_B)
11605#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
11606 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
11607 (index) * 4)
11608
Lionel Landwerlin29dc3732016-03-16 10:57:17 +000011609/* pipe CSC & degamma/gamma LUTs on CHV */
11610#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
11611#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
11612#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
11613#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
11614#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
11615#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
Ville Syrjälä3d041e92020-09-25 16:16:54 +030011616#define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0)
11617#define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16)
11618#define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0)
Lionel Landwerlin29dc3732016-03-16 10:57:17 +000011619#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
Ville Syrjälä3d041e92020-09-25 16:16:54 +030011620#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
11621#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
11622#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
Lionel Landwerlin29dc3732016-03-16 10:57:17 +000011623#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
11624#define CGM_PIPE_MODE_GAMMA (1 << 2)
11625#define CGM_PIPE_MODE_CSC (1 << 1)
11626#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
11627
11628#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
11629#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
11630#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
11631#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
11632#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
11633#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
11634#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
11635#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
11636
11637#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
11638#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
11639#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
11640#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
11641#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
11642#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
11643#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
11644#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
11645
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011646/* MIPI DSI registers */
11647
Hans de Goede0ad4dc82017-05-18 13:06:44 +020011648#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011649#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
Jani Nikula3230bf12013-08-27 15:12:16 +030011650
Madhav Chauhan292272e2018-10-15 17:27:57 +030011651/* Gen11 DSI */
11652#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11653 dsi0, dsi1)
11654
Deepak Mbcc65702017-02-17 18:13:34 +053011655#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
11656#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
11657#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
11658#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
11659
Madhav Chauhan27efd252018-07-05 18:31:48 +053011660#define _ICL_DSI_ESC_CLK_DIV0 0x6b090
11661#define _ICL_DSI_ESC_CLK_DIV1 0x6b890
11662#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11663 _ICL_DSI_ESC_CLK_DIV0, \
11664 _ICL_DSI_ESC_CLK_DIV1)
11665#define _ICL_DPHY_ESC_CLK_DIV0 0x162190
11666#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
11667#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11668 _ICL_DPHY_ESC_CLK_DIV0, \
11669 _ICL_DPHY_ESC_CLK_DIV1)
11670#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
11671#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
11672#define ICL_ESC_CLK_DIV_MASK 0x1ff
11673#define ICL_ESC_CLK_DIV_SHIFT 0
Madhav Chauhanfcfe0bd2018-07-05 19:19:33 +053011674#define DSI_MAX_ESC_CLK 20000 /* in KHz */
Madhav Chauhan27efd252018-07-05 18:31:48 +053011675
Mika Kahola510b2812021-05-18 17:06:18 -070011676#define _ADL_MIPIO_REG 0x180
11677#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
11678#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16)
11679#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
11680#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
11681
Vandita Kulkarni64ad5322019-11-11 16:40:21 +053011682#define _DSI_CMD_FRMCTL_0 0x6b034
11683#define _DSI_CMD_FRMCTL_1 0x6b834
11684#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \
11685 _DSI_CMD_FRMCTL_0,\
11686 _DSI_CMD_FRMCTL_1)
11687#define DSI_FRAME_UPDATE_REQUEST (1 << 31)
11688#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29)
11689#define DSI_NULL_PACKET_ENABLE (1 << 28)
11690#define DSI_FRAME_IN_PROGRESS (1 << 0)
11691
11692#define _DSI_INTR_MASK_REG_0 0x6b070
11693#define _DSI_INTR_MASK_REG_1 0x6b870
11694#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \
11695 _DSI_INTR_MASK_REG_0,\
11696 _DSI_INTR_MASK_REG_1)
11697
11698#define _DSI_INTR_IDENT_REG_0 0x6b074
11699#define _DSI_INTR_IDENT_REG_1 0x6b874
11700#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \
11701 _DSI_INTR_IDENT_REG_0,\
11702 _DSI_INTR_IDENT_REG_1)
11703#define DSI_TE_EVENT (1 << 31)
11704#define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30)
11705#define DSI_TX_DATA (1 << 29)
11706#define DSI_ULPS_ENTRY_DONE (1 << 28)
11707#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27)
11708#define DSI_HOST_CHKSUM_ERROR (1 << 26)
11709#define DSI_HOST_MULTI_ECC_ERROR (1 << 25)
11710#define DSI_HOST_SINGL_ECC_ERROR (1 << 24)
11711#define DSI_HOST_CONTENTION_DETECTED (1 << 23)
11712#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22)
11713#define DSI_HOST_TIMEOUT_ERROR (1 << 21)
11714#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20)
11715#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19)
11716#define DSI_FRAME_UPDATE_DONE (1 << 16)
11717#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15)
11718#define DSI_INVALID_TX_LENGTH (1 << 13)
11719#define DSI_INVALID_VC (1 << 12)
11720#define DSI_INVALID_DATA_TYPE (1 << 11)
11721#define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10)
11722#define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9)
11723#define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8)
11724#define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7)
11725#define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6)
11726#define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5)
11727#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4)
11728#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)
11729#define DSI_EOT_SYNC_ERROR (1 << 2)
11730#define DSI_SOT_SYNC_ERROR (1 << 1)
11731#define DSI_SOT_ERROR (1 << 0)
11732
Uma Shankaraec02462017-09-25 19:26:01 +053011733/* Gen4+ Timestamp and Pipe Frame time stamp registers */
11734#define GEN4_TIMESTAMP _MMIO(0x2358)
11735#define ILK_TIMESTAMP_HI _MMIO(0x70070)
11736#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
11737
Lionel Landwerlindab91782017-11-10 19:08:44 +000011738#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
11739#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
11740#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
11741#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
11742#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
11743
Uma Shankaraec02462017-09-25 19:26:01 +053011744#define _PIPE_FRMTMSTMP_A 0x70048
11745#define PIPE_FRMTMSTMP(pipe) \
11746 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
11747
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011748/* BXT MIPI clock controls */
11749#define BXT_MAX_VAR_OUTPUT_KHZ 39500
11750
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011751#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011752#define BXT_MIPI1_DIV_SHIFT 26
11753#define BXT_MIPI2_DIV_SHIFT 10
11754#define BXT_MIPI_DIV_SHIFT(port) \
11755 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
11756 BXT_MIPI2_DIV_SHIFT)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011757
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011758/* TX control divider to select actual TX clock output from (8x/var) */
Deepak M782d25c2016-02-15 22:43:57 +053011759#define BXT_MIPI1_TX_ESCLK_SHIFT 26
11760#define BXT_MIPI2_TX_ESCLK_SHIFT 10
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011761#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
11762 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
11763 BXT_MIPI2_TX_ESCLK_SHIFT)
Deepak M782d25c2016-02-15 22:43:57 +053011764#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
11765#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011766#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
11767 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
Deepak M782d25c2016-02-15 22:43:57 +053011768 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
11769#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070011770 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
Deepak M782d25c2016-02-15 22:43:57 +053011771/* RX upper control divider to select actual RX clock output from 8x */
11772#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
11773#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
11774#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
11775 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
11776 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
11777#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
11778#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
11779#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
11780 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
11781 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
11782#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070011783 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
Deepak M782d25c2016-02-15 22:43:57 +053011784/* 8/3X divider to select the actual 8/3X clock output from 8x */
11785#define BXT_MIPI1_8X_BY3_SHIFT 19
11786#define BXT_MIPI2_8X_BY3_SHIFT 3
11787#define BXT_MIPI_8X_BY3_SHIFT(port) \
11788 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
11789 BXT_MIPI2_8X_BY3_SHIFT)
11790#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
11791#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
11792#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
11793 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
11794 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
11795#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070011796 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
Deepak M782d25c2016-02-15 22:43:57 +053011797/* RX lower control divider to select actual RX clock output from 8x */
11798#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
11799#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
11800#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
11801 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
11802 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
11803#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
11804#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
11805#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
11806 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
11807 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
11808#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
Paulo Zanoni9e8789e2018-06-12 16:56:54 -070011809 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
Deepak M782d25c2016-02-15 22:43:57 +053011810
11811#define RX_DIVIDER_BIT_1_2 0x3
11812#define RX_DIVIDER_BIT_3_4 0xC
Shashank Sharma11b8e4f2015-09-23 23:27:17 +053011813
Shashank Sharmad2e08c02015-09-01 19:41:40 +053011814/* BXT MIPI mode configure */
11815#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
11816#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011817#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +053011818 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
11819
11820#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
11821#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011822#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +053011823 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
11824
11825#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
11826#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011827#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +053011828 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
11829
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011830#define BXT_DSI_PLL_CTL _MMIO(0x161000)
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011831#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
11832#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11833#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
Deepak Mf340c2f2017-02-17 18:13:32 +053011834#define BXT_DSIC_16X_BY1 (0 << 10)
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011835#define BXT_DSIC_16X_BY2 (1 << 10)
11836#define BXT_DSIC_16X_BY3 (2 << 10)
11837#define BXT_DSIC_16X_BY4 (3 << 10)
Imre Deakdb18b6a2016-03-24 12:41:40 +020011838#define BXT_DSIC_16X_MASK (3 << 10)
Deepak Mf340c2f2017-02-17 18:13:32 +053011839#define BXT_DSIA_16X_BY1 (0 << 8)
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011840#define BXT_DSIA_16X_BY2 (1 << 8)
11841#define BXT_DSIA_16X_BY3 (2 << 8)
11842#define BXT_DSIA_16X_BY4 (3 << 8)
Imre Deakdb18b6a2016-03-24 12:41:40 +020011843#define BXT_DSIA_16X_MASK (3 << 8)
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011844#define BXT_DSI_FREQ_SEL_SHIFT 8
11845#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
11846
11847#define BXT_DSI_PLL_RATIO_MAX 0x7D
11848#define BXT_DSI_PLL_RATIO_MIN 0x22
Deepak Mf340c2f2017-02-17 18:13:32 +053011849#define GLK_DSI_PLL_RATIO_MAX 0x6F
11850#define GLK_DSI_PLL_RATIO_MIN 0x22
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011851#define BXT_DSI_PLL_RATIO_MASK 0xFF
Deepak M61ad9922015-12-04 19:47:38 +053011852#define BXT_REF_CLOCK_KHZ 19200
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011853
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011854#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
Shashank Sharmacfe01a52015-09-01 19:41:38 +053011855#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
11856#define BXT_DSI_PLL_LOCKED (1 << 30)
11857
Jani Nikula3230bf12013-08-27 15:12:16 +030011858#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011859#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011860#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +053011861
11862 /* BXT port control */
11863#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
11864#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011865#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +053011866
Madhav Chauhan21652f32018-07-05 19:19:34 +053011867/* ICL DSI MODE control */
11868#define _ICL_DSI_IO_MODECTL_0 0x6B094
11869#define _ICL_DSI_IO_MODECTL_1 0x6B894
11870#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
11871 _ICL_DSI_IO_MODECTL_0, \
11872 _ICL_DSI_IO_MODECTL_1)
11873#define COMBO_PHY_MODE_DSI (1 << 0)
11874
Vandita Kulkarnif87c46c2021-08-26 11:18:10 +053011875/* TGL DSI Chicken register */
11876#define _TGL_DSI_CHKN_REG_0 0x6B0C0
11877#define _TGL_DSI_CHKN_REG_1 0x6B8C0
11878#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
11879 _TGL_DSI_CHKN_REG_0, \
11880 _TGL_DSI_CHKN_REG_1)
Vandita Kulkarni6f077072021-10-19 20:44:32 +053011881#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
11882#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
11883 (byte_clocks))
Vandita Kulkarnif87c46c2021-08-26 11:18:10 +053011884
Anusha Srivatsa8b1b5582018-10-30 13:56:35 +020011885/* Display Stream Splitter Control */
11886#define DSS_CTL1 _MMIO(0x67400)
11887#define SPLITTER_ENABLE (1 << 31)
11888#define JOINER_ENABLE (1 << 30)
11889#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
11890#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
11891#define OVERLAP_PIXELS_MASK (0xf << 16)
11892#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
11893#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11894#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
Anusha Srivatsa18cde292018-11-01 14:42:16 -070011895#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
Anusha Srivatsa8b1b5582018-10-30 13:56:35 +020011896
11897#define DSS_CTL2 _MMIO(0x67404)
11898#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
11899#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
11900#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11901#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
11902
Anusha Srivatsa18cde292018-11-01 14:42:16 -070011903#define _ICL_PIPE_DSS_CTL1_PB 0x78200
11904#define _ICL_PIPE_DSS_CTL1_PC 0x78400
11905#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11906 _ICL_PIPE_DSS_CTL1_PB, \
11907 _ICL_PIPE_DSS_CTL1_PC)
Anusha Srivatsa8b1b5582018-10-30 13:56:35 +020011908#define BIG_JOINER_ENABLE (1 << 29)
11909#define MASTER_BIG_JOINER_ENABLE (1 << 28)
11910#define VGA_CENTERING_ENABLE (1 << 27)
Jani Nikula63e654f2021-02-11 16:52:15 +020011911#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
11912#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
11913#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
Animesh Mannad961eb22021-05-14 08:37:07 -070011914#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
11915#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
Anusha Srivatsa8b1b5582018-10-30 13:56:35 +020011916
Anusha Srivatsa18cde292018-11-01 14:42:16 -070011917#define _ICL_PIPE_DSS_CTL2_PB 0x78204
11918#define _ICL_PIPE_DSS_CTL2_PC 0x78404
11919#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11920 _ICL_PIPE_DSS_CTL2_PB, \
11921 _ICL_PIPE_DSS_CTL2_PC)
Anusha Srivatsa8b1b5582018-10-30 13:56:35 +020011922
Uma Shankar1881a422017-01-25 19:43:23 +053011923#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
11924#define STAP_SELECT (1 << 0)
11925
11926#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
11927#define HS_IO_CTRL_SELECT (1 << 0)
11928
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011929#define DPI_ENABLE (1 << 31) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +030011930#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
11931#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
Gaurav K Singh369602d2014-12-05 14:09:28 +053011932#define DUAL_LINK_MODE_SHIFT 26
Jani Nikula3230bf12013-08-27 15:12:16 +030011933#define DUAL_LINK_MODE_MASK (1 << 26)
11934#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
11935#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011936#define DITHERING_ENABLE (1 << 25) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +030011937#define FLOPPED_HSTX (1 << 23)
11938#define DE_INVERT (1 << 19) /* XXX */
11939#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
11940#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
11941#define AFE_LATCHOUT (1 << 17)
11942#define LP_OUTPUT_HOLD (1 << 16)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011943#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
11944#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
11945#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
11946#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
Jani Nikula3230bf12013-08-27 15:12:16 +030011947#define CSB_SHIFT 9
11948#define CSB_MASK (3 << 9)
11949#define CSB_20MHZ (0 << 9)
11950#define CSB_10MHZ (1 << 9)
11951#define CSB_40MHZ (2 << 9)
11952#define BANDGAP_MASK (1 << 8)
11953#define BANDGAP_PNW_CIRCUIT (0 << 8)
11954#define BANDGAP_LNC_CIRCUIT (1 << 8)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011955#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
11956#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
11957#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
11958#define TEARING_EFFECT_SHIFT 2 /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +030011959#define TEARING_EFFECT_MASK (3 << 2)
11960#define TEARING_EFFECT_OFF (0 << 2)
11961#define TEARING_EFFECT_DSI (1 << 2)
11962#define TEARING_EFFECT_GPIO (2 << 2)
11963#define LANE_CONFIGURATION_SHIFT 0
11964#define LANE_CONFIGURATION_MASK (3 << 0)
11965#define LANE_CONFIGURATION_4LANE (0 << 0)
11966#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
11967#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
11968
11969#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011970#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011971#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +030011972#define TEARING_EFFECT_DELAY_SHIFT 0
11973#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
11974
11975/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053011976#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +030011977
11978/* MIPI DSI Controller and D-PHY registers */
11979
Shashank Sharma4ad83e92014-06-02 18:07:47 +053011980#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011981#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011982#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +030011983#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
11984#define ULPS_STATE_MASK (3 << 1)
11985#define ULPS_STATE_ENTER (2 << 1)
11986#define ULPS_STATE_EXIT (1 << 1)
11987#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
11988#define DEVICE_READY (1 << 0)
11989
Shashank Sharma4ad83e92014-06-02 18:07:47 +053011990#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011991#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011992#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +053011993#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020011994#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011995#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +030011996#define TEARING_EFFECT (1 << 31)
11997#define SPL_PKT_SENT_INTERRUPT (1 << 30)
11998#define GEN_READ_DATA_AVAIL (1 << 29)
11999#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
12000#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
12001#define RX_PROT_VIOLATION (1 << 26)
12002#define RX_INVALID_TX_LENGTH (1 << 25)
12003#define ACK_WITH_NO_ERROR (1 << 24)
12004#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
12005#define LP_RX_TIMEOUT (1 << 22)
12006#define HS_TX_TIMEOUT (1 << 21)
12007#define DPI_FIFO_UNDERRUN (1 << 20)
12008#define LOW_CONTENTION (1 << 19)
12009#define HIGH_CONTENTION (1 << 18)
12010#define TXDSI_VC_ID_INVALID (1 << 17)
12011#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
12012#define TXCHECKSUM_ERROR (1 << 15)
12013#define TXECC_MULTIBIT_ERROR (1 << 14)
12014#define TXECC_SINGLE_BIT_ERROR (1 << 13)
12015#define TXFALSE_CONTROL_ERROR (1 << 12)
12016#define RXDSI_VC_ID_INVALID (1 << 11)
12017#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
12018#define RXCHECKSUM_ERROR (1 << 9)
12019#define RXECC_MULTIBIT_ERROR (1 << 8)
12020#define RXECC_SINGLE_BIT_ERROR (1 << 7)
12021#define RXFALSE_CONTROL_ERROR (1 << 6)
12022#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
12023#define RX_LP_TX_SYNC_ERROR (1 << 4)
12024#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
12025#define RXEOT_SYNC_ERROR (1 << 2)
12026#define RXSOT_SYNC_ERROR (1 << 1)
12027#define RXSOT_ERROR (1 << 0)
12028
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012029#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012030#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012031#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +030012032#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
12033#define CMD_MODE_NOT_SUPPORTED (0 << 13)
12034#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
12035#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
12036#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
12037#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
12038#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
12039#define VID_MODE_FORMAT_MASK (0xf << 7)
12040#define VID_MODE_NOT_SUPPORTED (0 << 7)
12041#define VID_MODE_FORMAT_RGB565 (1 << 7)
Jani Nikula42c151e2016-03-16 12:21:39 +020012042#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
12043#define VID_MODE_FORMAT_RGB666 (3 << 7)
Jani Nikula3230bf12013-08-27 15:12:16 +030012044#define VID_MODE_FORMAT_RGB888 (4 << 7)
12045#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
12046#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
12047#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
12048#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
12049#define DATA_LANES_PRG_REG_SHIFT 0
12050#define DATA_LANES_PRG_REG_MASK (7 << 0)
12051
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012052#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012053#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012054#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012055#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
12056
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012057#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012058#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012059#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012060#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
12061
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012062#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012063#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012064#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012065#define TURN_AROUND_TIMEOUT_MASK 0x3f
12066
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012067#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012068#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012069#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +030012070#define DEVICE_RESET_TIMER_MASK 0xffff
12071
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012072#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012073#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012074#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +030012075#define VERTICAL_ADDRESS_SHIFT 16
12076#define VERTICAL_ADDRESS_MASK (0xffff << 16)
12077#define HORIZONTAL_ADDRESS_SHIFT 0
12078#define HORIZONTAL_ADDRESS_MASK 0xffff
12079
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012080#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012081#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012082#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +030012083#define DBI_FIFO_EMPTY_HALF (0 << 0)
12084#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
12085#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
12086
12087/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012088#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012089#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012090#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012091
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012092#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012093#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012094#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012095
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012096#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012097#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012098#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012099
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012100#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012101#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012102#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012103
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012104#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012105#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012106#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012107
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012108#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012109#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012110#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012111
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012112#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012113#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012114#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012115
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012116#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012117#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012118#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012119
Jani Nikula3230bf12013-08-27 15:12:16 +030012120/* regs above are bits 15:0 */
12121
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012122#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012123#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012124#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +030012125#define DPI_LP_MODE (1 << 6)
12126#define BACKLIGHT_OFF (1 << 5)
12127#define BACKLIGHT_ON (1 << 4)
12128#define COLOR_MODE_OFF (1 << 3)
12129#define COLOR_MODE_ON (1 << 2)
12130#define TURN_ON (1 << 1)
12131#define SHUTDOWN (1 << 0)
12132
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012133#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012134#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012135#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +030012136#define COMMAND_BYTE_SHIFT 0
12137#define COMMAND_BYTE_MASK (0x3f << 0)
12138
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012139#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012140#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012141#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012142#define MASTER_INIT_TIMER_SHIFT 0
12143#define MASTER_INIT_TIMER_MASK (0xffff << 0)
12144
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012145#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012146#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012147#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012148 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +030012149#define MAX_RETURN_PKT_SIZE_SHIFT 0
12150#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
12151
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012152#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012153#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012154#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012155#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
12156#define DISABLE_VIDEO_BTA (1 << 3)
12157#define IP_TG_CONFIG (1 << 2)
12158#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
12159#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
12160#define VIDEO_MODE_BURST (3 << 0)
12161
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012162#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012163#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012164#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
Jani Nikulaf90e8c32016-06-03 17:57:05 +030012165#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
12166#define BXT_DPHY_DEFEATURE_EN (1 << 8)
Jani Nikula3230bf12013-08-27 15:12:16 +030012167#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
12168#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
12169#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
12170#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
12171#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
12172#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
12173#define CLOCKSTOP (1 << 1)
12174#define EOT_DISABLE (1 << 0)
12175
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012176#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012177#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012178#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +030012179#define LP_BYTECLK_SHIFT 0
12180#define LP_BYTECLK_MASK (0xffff << 0)
12181
Deepak Mb426f982017-02-17 18:13:30 +053012182#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
12183#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
12184#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
12185
12186#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
12187#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
12188#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
12189
Jani Nikula3230bf12013-08-27 15:12:16 +030012190/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012191#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012192#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012193#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +030012194
12195/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012196#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012197#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012198#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +030012199
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012200#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012201#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012202#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012203#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012204#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012205#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +030012206#define LONG_PACKET_WORD_COUNT_SHIFT 8
12207#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
12208#define SHORT_PACKET_PARAM_SHIFT 8
12209#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
12210#define VIRTUAL_CHANNEL_SHIFT 6
12211#define VIRTUAL_CHANNEL_MASK (3 << 6)
12212#define DATA_TYPE_SHIFT 0
Ville Syrjälä395b2912015-09-18 20:03:40 +030012213#define DATA_TYPE_MASK (0x3f << 0)
Jani Nikula3230bf12013-08-27 15:12:16 +030012214/* data type values, see include/video/mipi_display.h */
12215
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012216#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012217#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012218#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012219#define DPI_FIFO_EMPTY (1 << 28)
12220#define DBI_FIFO_EMPTY (1 << 27)
12221#define LP_CTRL_FIFO_EMPTY (1 << 26)
12222#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
12223#define LP_CTRL_FIFO_FULL (1 << 24)
12224#define HS_CTRL_FIFO_EMPTY (1 << 18)
12225#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
12226#define HS_CTRL_FIFO_FULL (1 << 16)
12227#define LP_DATA_FIFO_EMPTY (1 << 10)
12228#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
12229#define LP_DATA_FIFO_FULL (1 << 8)
12230#define HS_DATA_FIFO_EMPTY (1 << 2)
12231#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
12232#define HS_DATA_FIFO_FULL (1 << 0)
12233
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012234#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012235#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012236#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +030012237#define DBI_HS_LP_MODE_MASK (1 << 0)
12238#define DBI_LP_MODE (1 << 0)
12239#define DBI_HS_MODE (0 << 0)
12240
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012241#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012242#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012243#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +030012244#define EXIT_ZERO_COUNT_SHIFT 24
12245#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
12246#define TRAIL_COUNT_SHIFT 16
12247#define TRAIL_COUNT_MASK (0x1f << 16)
12248#define CLK_ZERO_COUNT_SHIFT 8
12249#define CLK_ZERO_COUNT_MASK (0xff << 8)
12250#define PREPARE_COUNT_SHIFT 0
12251#define PREPARE_COUNT_MASK (0x3f << 0)
12252
Madhav Chauhan146cdf32018-07-10 15:10:05 +053012253#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
12254#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
12255#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
12256 _ICL_DSI_T_INIT_MASTER_0,\
12257 _ICL_DSI_T_INIT_MASTER_1)
12258
Madhav Chauhan33868a92018-09-16 16:23:28 +053012259#define _DPHY_CLK_TIMING_PARAM_0 0x162180
12260#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
12261#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
12262 _DPHY_CLK_TIMING_PARAM_0,\
12263 _DPHY_CLK_TIMING_PARAM_1)
12264#define _DSI_CLK_TIMING_PARAM_0 0x6b080
12265#define _DSI_CLK_TIMING_PARAM_1 0x6b880
12266#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
12267 _DSI_CLK_TIMING_PARAM_0,\
12268 _DSI_CLK_TIMING_PARAM_1)
12269#define CLK_PREPARE_OVERRIDE (1 << 31)
12270#define CLK_PREPARE(x) ((x) << 28)
12271#define CLK_PREPARE_MASK (0x7 << 28)
12272#define CLK_PREPARE_SHIFT 28
12273#define CLK_ZERO_OVERRIDE (1 << 27)
12274#define CLK_ZERO(x) ((x) << 20)
12275#define CLK_ZERO_MASK (0xf << 20)
12276#define CLK_ZERO_SHIFT 20
12277#define CLK_PRE_OVERRIDE (1 << 19)
12278#define CLK_PRE(x) ((x) << 16)
12279#define CLK_PRE_MASK (0x3 << 16)
12280#define CLK_PRE_SHIFT 16
12281#define CLK_POST_OVERRIDE (1 << 15)
12282#define CLK_POST(x) ((x) << 8)
12283#define CLK_POST_MASK (0x7 << 8)
12284#define CLK_POST_SHIFT 8
12285#define CLK_TRAIL_OVERRIDE (1 << 7)
12286#define CLK_TRAIL(x) ((x) << 0)
12287#define CLK_TRAIL_MASK (0xf << 0)
12288#define CLK_TRAIL_SHIFT 0
12289
12290#define _DPHY_DATA_TIMING_PARAM_0 0x162184
12291#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
12292#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
12293 _DPHY_DATA_TIMING_PARAM_0,\
12294 _DPHY_DATA_TIMING_PARAM_1)
12295#define _DSI_DATA_TIMING_PARAM_0 0x6B084
12296#define _DSI_DATA_TIMING_PARAM_1 0x6B884
12297#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
12298 _DSI_DATA_TIMING_PARAM_0,\
12299 _DSI_DATA_TIMING_PARAM_1)
12300#define HS_PREPARE_OVERRIDE (1 << 31)
12301#define HS_PREPARE(x) ((x) << 24)
12302#define HS_PREPARE_MASK (0x7 << 24)
12303#define HS_PREPARE_SHIFT 24
12304#define HS_ZERO_OVERRIDE (1 << 23)
12305#define HS_ZERO(x) ((x) << 16)
12306#define HS_ZERO_MASK (0xf << 16)
12307#define HS_ZERO_SHIFT 16
12308#define HS_TRAIL_OVERRIDE (1 << 15)
12309#define HS_TRAIL(x) ((x) << 8)
12310#define HS_TRAIL_MASK (0x7 << 8)
12311#define HS_TRAIL_SHIFT 8
12312#define HS_EXIT_OVERRIDE (1 << 7)
12313#define HS_EXIT(x) ((x) << 0)
12314#define HS_EXIT_MASK (0x7 << 0)
12315#define HS_EXIT_SHIFT 0
12316
Madhav Chauhan35c37ad2018-09-16 16:23:30 +053012317#define _DPHY_TA_TIMING_PARAM_0 0x162188
12318#define _DPHY_TA_TIMING_PARAM_1 0x6c188
12319#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
12320 _DPHY_TA_TIMING_PARAM_0,\
12321 _DPHY_TA_TIMING_PARAM_1)
12322#define _DSI_TA_TIMING_PARAM_0 0x6b098
12323#define _DSI_TA_TIMING_PARAM_1 0x6b898
12324#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
12325 _DSI_TA_TIMING_PARAM_0,\
12326 _DSI_TA_TIMING_PARAM_1)
12327#define TA_SURE_OVERRIDE (1 << 31)
12328#define TA_SURE(x) ((x) << 16)
12329#define TA_SURE_MASK (0x1f << 16)
12330#define TA_SURE_SHIFT 16
12331#define TA_GO_OVERRIDE (1 << 15)
12332#define TA_GO(x) ((x) << 8)
12333#define TA_GO_MASK (0xf << 8)
12334#define TA_GO_SHIFT 8
12335#define TA_GET_OVERRIDE (1 << 7)
12336#define TA_GET(x) ((x) << 0)
12337#define TA_GET_MASK (0xf << 0)
12338#define TA_GET_SHIFT 0
12339
Madhav Chauhan5ffce252018-10-15 17:27:58 +030012340/* DSI transcoder configuration */
12341#define _DSI_TRANS_FUNC_CONF_0 0x6b030
12342#define _DSI_TRANS_FUNC_CONF_1 0x6b830
12343#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
12344 _DSI_TRANS_FUNC_CONF_0,\
12345 _DSI_TRANS_FUNC_CONF_1)
12346#define OP_MODE_MASK (0x3 << 28)
12347#define OP_MODE_SHIFT 28
12348#define CMD_MODE_NO_GATE (0x0 << 28)
12349#define CMD_MODE_TE_GATE (0x1 << 28)
12350#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
12351#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
Vandita Kulkarni64ad5322019-11-11 16:40:21 +053012352#define TE_SOURCE_GPIO (1 << 27)
Madhav Chauhan5ffce252018-10-15 17:27:58 +030012353#define LINK_READY (1 << 20)
12354#define PIX_FMT_MASK (0x3 << 16)
12355#define PIX_FMT_SHIFT 16
12356#define PIX_FMT_RGB565 (0x0 << 16)
12357#define PIX_FMT_RGB666_PACKED (0x1 << 16)
12358#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
12359#define PIX_FMT_RGB888 (0x3 << 16)
12360#define PIX_FMT_RGB101010 (0x4 << 16)
12361#define PIX_FMT_RGB121212 (0x5 << 16)
12362#define PIX_FMT_COMPRESSED (0x6 << 16)
12363#define BGR_TRANSMISSION (1 << 15)
12364#define PIX_VIRT_CHAN(x) ((x) << 12)
12365#define PIX_VIRT_CHAN_MASK (0x3 << 12)
12366#define PIX_VIRT_CHAN_SHIFT 12
12367#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
12368#define PIX_BUF_THRESHOLD_SHIFT 10
12369#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
12370#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
12371#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
12372#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
12373#define CONTINUOUS_CLK_MASK (0x3 << 8)
12374#define CONTINUOUS_CLK_SHIFT 8
12375#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
12376#define CLK_HS_OR_LP (0x2 << 8)
12377#define CLK_HS_CONTINUOUS (0x3 << 8)
12378#define LINK_CALIBRATION_MASK (0x3 << 4)
12379#define LINK_CALIBRATION_SHIFT 4
12380#define CALIBRATION_DISABLED (0x0 << 4)
12381#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
12382#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
Vandita Kulkarni32d38e62019-07-30 13:06:48 +053012383#define BLANKING_PACKET_ENABLE (1 << 2)
Madhav Chauhan5ffce252018-10-15 17:27:58 +030012384#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
12385#define EOTP_DISABLED (1 << 0)
12386
Madhav Chauhan60230aa2018-10-15 17:28:06 +030012387#define _DSI_CMD_RXCTL_0 0x6b0d4
12388#define _DSI_CMD_RXCTL_1 0x6b8d4
12389#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
12390 _DSI_CMD_RXCTL_0,\
12391 _DSI_CMD_RXCTL_1)
12392#define READ_UNLOADS_DW (1 << 16)
12393#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
12394#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
12395#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
12396#define RECEIVED_RESET_TRIGGER (1 << 12)
12397#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
12398#define RECEIVED_CRC_WAS_LOST (1 << 10)
12399#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
12400#define NUMBER_RX_PLOAD_DW_SHIFT 0
12401
12402#define _DSI_CMD_TXCTL_0 0x6b0d0
12403#define _DSI_CMD_TXCTL_1 0x6b8d0
12404#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
12405 _DSI_CMD_TXCTL_0,\
12406 _DSI_CMD_TXCTL_1)
12407#define KEEP_LINK_IN_HS (1 << 24)
12408#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
12409#define FREE_HEADER_CREDIT_SHIFT 0x8
12410#define FREE_PLOAD_CREDIT_MASK (0xff << 0)
12411#define FREE_PLOAD_CREDIT_SHIFT 0
12412#define MAX_HEADER_CREDIT 0x10
12413#define MAX_PLOAD_CREDIT 0x40
12414
Madhav Chauhan808517e2018-10-30 13:56:26 +020012415#define _DSI_CMD_TXHDR_0 0x6b100
12416#define _DSI_CMD_TXHDR_1 0x6b900
12417#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
12418 _DSI_CMD_TXHDR_0,\
12419 _DSI_CMD_TXHDR_1)
12420#define PAYLOAD_PRESENT (1 << 31)
12421#define LP_DATA_TRANSFER (1 << 30)
12422#define VBLANK_FENCE (1 << 29)
12423#define PARAM_WC_MASK (0xffff << 8)
12424#define PARAM_WC_LOWER_SHIFT 8
12425#define PARAM_WC_UPPER_SHIFT 16
12426#define VC_MASK (0x3 << 6)
12427#define VC_SHIFT 6
12428#define DT_MASK (0x3f << 0)
12429#define DT_SHIFT 0
12430
12431#define _DSI_CMD_TXPYLD_0 0x6b104
12432#define _DSI_CMD_TXPYLD_1 0x6b904
12433#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
12434 _DSI_CMD_TXPYLD_0,\
12435 _DSI_CMD_TXPYLD_1)
12436
Madhav Chauhan60230aa2018-10-15 17:28:06 +030012437#define _DSI_LP_MSG_0 0x6b0d8
12438#define _DSI_LP_MSG_1 0x6b8d8
12439#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
12440 _DSI_LP_MSG_0,\
12441 _DSI_LP_MSG_1)
12442#define LPTX_IN_PROGRESS (1 << 17)
12443#define LINK_IN_ULPS (1 << 16)
12444#define LINK_ULPS_TYPE_LP11 (1 << 8)
12445#define LINK_ENTER_ULPS (1 << 0)
12446
Madhav Chauhan8bffd202018-10-30 13:56:21 +020012447/* DSI timeout registers */
12448#define _DSI_HSTX_TO_0 0x6b044
12449#define _DSI_HSTX_TO_1 0x6b844
12450#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
12451 _DSI_HSTX_TO_0,\
12452 _DSI_HSTX_TO_1)
12453#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
12454#define HSTX_TIMEOUT_VALUE_SHIFT 16
12455#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
12456#define HSTX_TIMED_OUT (1 << 0)
12457
12458#define _DSI_LPRX_HOST_TO_0 0x6b048
12459#define _DSI_LPRX_HOST_TO_1 0x6b848
12460#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
12461 _DSI_LPRX_HOST_TO_0,\
12462 _DSI_LPRX_HOST_TO_1)
12463#define LPRX_TIMED_OUT (1 << 16)
12464#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
12465#define LPRX_TIMEOUT_VALUE_SHIFT 0
12466#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
12467
12468#define _DSI_PWAIT_TO_0 0x6b040
12469#define _DSI_PWAIT_TO_1 0x6b840
12470#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
12471 _DSI_PWAIT_TO_0,\
12472 _DSI_PWAIT_TO_1)
12473#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
12474#define PRESET_TIMEOUT_VALUE_SHIFT 16
12475#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
12476#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
12477#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
12478#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
12479
12480#define _DSI_TA_TO_0 0x6b04c
12481#define _DSI_TA_TO_1 0x6b84c
12482#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
12483 _DSI_TA_TO_0,\
12484 _DSI_TA_TO_1)
12485#define TA_TIMED_OUT (1 << 16)
12486#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
12487#define TA_TIMEOUT_VALUE_SHIFT 0
12488#define TA_TIMEOUT_VALUE(x) ((x) << 0)
12489
Jani Nikula3230bf12013-08-27 15:12:16 +030012490/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012491#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012492#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012493#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +030012494
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012495#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
12496#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
12497#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +030012498#define LP_HS_SSW_CNT_SHIFT 16
12499#define LP_HS_SSW_CNT_MASK (0xffff << 16)
12500#define HS_LP_PWR_SW_CNT_SHIFT 0
12501#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
12502
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012503#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012504#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012505#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +030012506#define STOP_STATE_STALL_COUNTER_SHIFT 0
12507#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
12508
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012509#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012510#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012511#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012512#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012513#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012514#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +030012515#define RX_CONTENTION_DETECTED (1 << 0)
12516
12517/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012518#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +030012519#define DBI_TYPEC_ENABLE (1 << 31)
12520#define DBI_TYPEC_WIP (1 << 30)
12521#define DBI_TYPEC_OPTION_SHIFT 28
12522#define DBI_TYPEC_OPTION_MASK (3 << 28)
12523#define DBI_TYPEC_FREQ_SHIFT 24
12524#define DBI_TYPEC_FREQ_MASK (0xf << 24)
12525#define DBI_TYPEC_OVERRIDE (1 << 8)
12526#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
12527#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
12528
12529
12530/* MIPI adapter registers */
12531
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012532#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012533#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012534#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +030012535#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
12536#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
12537#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
12538#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
12539#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
12540#define READ_REQUEST_PRIORITY_SHIFT 3
12541#define READ_REQUEST_PRIORITY_MASK (3 << 3)
12542#define READ_REQUEST_PRIORITY_LOW (0 << 3)
12543#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
12544#define RGB_FLIP_TO_BGR (1 << 2)
12545
Jani Nikula6b93e9c2016-03-15 21:51:12 +020012546#define BXT_PIPE_SELECT_SHIFT 7
Shashank Sharmad2e08c02015-09-01 19:41:40 +053012547#define BXT_PIPE_SELECT_MASK (7 << 7)
Deepak M56c48972015-12-09 20:14:04 +053012548#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
Deepak M093d6802016-12-15 14:31:32 +053012549#define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
12550#define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
12551#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
12552#define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
12553#define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
12554#define GLK_LP_WAKE (1 << 22)
12555#define GLK_LP11_LOW_PWR_MODE (1 << 21)
12556#define GLK_LP00_LOW_PWR_MODE (1 << 20)
12557#define GLK_FIREWALL_ENABLE (1 << 16)
12558#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
12559#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
12560#define BXT_DSC_ENABLE (1 << 3)
12561#define BXT_RGB_FLIP (1 << 2)
12562#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
12563#define GLK_MIPIIO_ENABLE (1 << 0)
Shashank Sharmad2e08c02015-09-01 19:41:40 +053012564
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012565#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012566#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012567#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +030012568#define DATA_MEM_ADDRESS_SHIFT 5
12569#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
12570#define DATA_VALID (1 << 0)
12571
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012572#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012573#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012574#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +030012575#define DATA_LENGTH_SHIFT 0
12576#define DATA_LENGTH_MASK (0xfffff << 0)
12577
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012578#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012579#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012580#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +030012581#define COMMAND_MEM_ADDRESS_SHIFT 5
12582#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
12583#define AUTO_PWG_ENABLE (1 << 2)
12584#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
12585#define COMMAND_VALID (1 << 0)
12586
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012587#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012588#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012589#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +030012590#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
12591#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
12592
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012593#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012594#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012595#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +030012596
Shashank Sharma4ad83e92014-06-02 18:07:47 +053012597#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
Jani Nikulae7d7cad2014-11-14 16:54:21 +020012598#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012599#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +030012600#define READ_DATA_VALID(n) (1 << (n))
12601
Peter Antoine3bbaba02015-07-10 20:13:11 +030012602/* MOCS (Memory Object Control State) registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020012603#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
John Harrison6de12da12021-07-26 17:23:30 -070012604#define GEN9_LNCFCMOCS_REG_COUNT 32
Peter Antoine3bbaba02015-07-10 20:13:11 +030012605
Chris Wilsonf8a0c7a2019-11-12 22:35:59 +000012606#define __GEN9_RCS0_MOCS0 0xc800
12607#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
12608#define __GEN9_VCS0_MOCS0 0xc900
12609#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
12610#define __GEN9_VCS1_MOCS0 0xca00
12611#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
12612#define __GEN9_VECS0_MOCS0 0xcb00
12613#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
12614#define __GEN9_BCS0_MOCS0 0xcc00
12615#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
12616#define __GEN11_VCS2_MOCS0 0x10000
12617#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
Peter Antoine3bbaba02015-07-10 20:13:11 +030012618
Chris Wilson58586682021-01-25 22:01:52 +000012619#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
12620#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
12621
12622#define GEN9_SCRATCH1 _MMIO(0xb11c)
12623#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
12624
Oscar Mateo73f4e8a2018-05-08 14:29:35 -070012625#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
12626#define PMFLUSHDONE_LNICRSDROP (1 << 20)
12627#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
12628#define PMFLUSHDONE_LNEBLK (1 << 22)
12629
Matt Roper645cc0b2021-11-02 15:25:10 -070012630#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
12631#define XEHP_LNESPARE REG_BIT(19)
12632
Michel Thierrya7a7a0e2019-07-30 11:04:06 -070012633#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
12634
CQ Tang7f2aa5b2021-01-27 13:14:12 +000012635#define GEN12_GSMBASE _MMIO(0x108100)
CQ Tangd57d4a12021-04-21 11:46:55 +010012636#define GEN12_DSMBASE _MMIO(0x1080C0)
CQ Tang7f2aa5b2021-01-27 13:14:12 +000012637
Stuart Summersd73dd1f2021-11-02 15:25:09 -070012638#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
Matt Roper645cc0b2021-11-02 15:25:10 -070012639#define SGSI_SIDECLK_DIS REG_BIT(17)
12640#define SGGI_DIS REG_BIT(15)
Stuart Summersd73dd1f2021-11-02 15:25:09 -070012641#define SGR_DIS REG_BIT(13)
12642
Tim Gored5165eb2016-02-04 11:49:34 +000012643/* gamt regs */
12644#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12645#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
12646#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
12647#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
12648#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
12649
Ville Syrjälä93564042017-08-24 22:10:51 +030012650#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
12651#define MMCD_PCLA (1 << 31)
12652#define MMCD_HOTSPOT_EN (1 << 27)
12653
Paulo Zanoniad186f32018-02-05 13:40:43 -020012654#define _ICL_PHY_MISC_A 0x64C00
12655#define _ICL_PHY_MISC_B 0x64C04
12656#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
12657 _ICL_PHY_MISC_B)
Matt Roperbdeb18d2019-06-18 10:51:31 -070012658#define ICL_PHY_MISC_MUX_DDID (1 << 28)
Paulo Zanoniad186f32018-02-05 13:40:43 -020012659#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
Matt Ropera6a12812021-07-23 10:42:36 -070012660#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
Paulo Zanoniad186f32018-02-05 13:40:43 -020012661
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012662/* Icelake Display Stream Compression Registers */
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012663#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
12664#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012665#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
12666#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
12667#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
12668#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
12669#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12670 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
12671 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
12672#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12673 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
12674 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
12675#define DSC_VBR_ENABLE (1 << 19)
12676#define DSC_422_ENABLE (1 << 18)
12677#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
12678#define DSC_BLOCK_PREDICTION (1 << 16)
12679#define DSC_LINE_BUF_DEPTH_SHIFT 12
12680#define DSC_BPC_SHIFT 8
12681#define DSC_VER_MIN_SHIFT 4
12682#define DSC_VER_MAJ (0x1 << 0)
12683
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012684#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
12685#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012686#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
12687#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
12688#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
12689#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
12690#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12691 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
12692 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
12693#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12694 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
12695 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
12696#define DSC_BPP(bpp) ((bpp) << 0)
12697
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012698#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
12699#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012700#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
12701#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
12702#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
12703#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
12704#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12705 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
12706 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
12707#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12708 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
12709 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
12710#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
12711#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
12712
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012713#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
12714#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012715#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
12716#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
12717#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
12718#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
12719#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12720 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
12721 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
12722#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12723 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
12724 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
12725#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
12726#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12727
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012728#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
12729#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012730#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
12731#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
12732#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
12733#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
12734#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12735 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
12736 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
12737#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
Manasi Navare5df52392018-08-23 18:48:07 -070012738 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012739 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
12740#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
12741#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
12742
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012743#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
12744#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012745#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
12746#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
12747#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
12748#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
12749#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12750 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
12751 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
12752#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
Manasi Navare5df52392018-08-23 18:48:07 -070012753 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012754 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012755#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012756#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
12757
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012758#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
12759#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012760#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
12761#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
12762#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
12763#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
12764#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12765 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
12766 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
12767#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12768 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
12769 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012770#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
12771#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012772#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
12773#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
12774
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012775#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
12776#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012777#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
12778#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
12779#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
12780#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
12781#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12782 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
12783 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
12784#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12785 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
12786 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
12787#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
12788#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
12789
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012790#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
12791#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012792#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
12793#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
12794#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
12795#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
12796#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12797 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
12798 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
12799#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12800 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
12801 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
12802#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
12803#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
12804
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012805#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
12806#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012807#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
12808#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
12809#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
12810#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
12811#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12812 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
12813 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
12814#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12815 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
12816 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
12817#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
12818#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
12819
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012820#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
12821#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012822#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
12823#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
12824#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
12825#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
12826#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12827 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
12828 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
12829#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12830 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
12831 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
12832#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
12833#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
12834#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
12835#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
12836
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012837#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
12838#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012839#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
12840#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
12841#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
12842#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
12843#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12844 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
12845 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
12846#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12847 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
12848 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
12849
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012850#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
12851#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012852#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
12853#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
12854#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
12855#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
12856#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12857 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
12858 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
12859#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12860 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
12861 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
12862
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012863#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
12864#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012865#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
12866#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
12867#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
12868#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
12869#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12870 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
12871 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
12872#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12873 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
12874 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
12875
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012876#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
12877#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012878#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
12879#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
12880#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
12881#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
12882#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12883 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
12884 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
12885#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12886 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
12887 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
12888
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012889#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
12890#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012891#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
12892#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
12893#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
12894#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
12895#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12896 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
12897 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
12898#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12899 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
12900 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
12901
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012902#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
12903#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012904#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
12905#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
12906#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
12907#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
12908#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12909 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
12910 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
12911#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12912 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
12913 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
Anusha Srivatsa35b876d2018-10-30 17:19:17 -070012914#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012915#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
Anusha Srivatsa6f15a7d2018-07-20 14:42:42 -070012916#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
Anusha Srivatsa2efbb2f2018-07-17 14:10:59 -070012917
Anusha Srivatsadbda5112018-07-17 14:11:00 -070012918/* Icelake Rate Control Buffer Threshold Registers */
12919#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
12920#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
12921#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
12922#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
12923#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
12924#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
12925#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
12926#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
12927#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
12928#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
12929#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
12930#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
12931#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12932 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
12933 _ICL_DSC0_RC_BUF_THRESH_0_PC)
12934#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12935 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12936 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12937#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12938 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
12939 _ICL_DSC1_RC_BUF_THRESH_0_PC)
12940#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12941 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12942 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12943
12944#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
12945#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
12946#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
12947#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
12948#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
12949#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
12950#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
12951#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
12952#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
12953#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
12954#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
12955#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
12956#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12957 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
12958 _ICL_DSC0_RC_BUF_THRESH_1_PC)
12959#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12960 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12961 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12962#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12963 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
12964 _ICL_DSC1_RC_BUF_THRESH_1_PC)
12965#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12966 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12967 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12968
Anusha Srivatsa0caf6252019-07-11 22:57:05 -070012969#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
12970#define MODULAR_FIA_MASK (1 << 4)
José Roberto de Souza31d9ae92019-09-20 13:58:06 -070012971#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
12972#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
12973#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
12974#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
12975#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
Paulo Zanonib9fcdda2018-07-25 12:59:27 -070012976
Anusha Srivatsa0caf6252019-07-11 22:57:05 -070012977#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
José Roberto de Souza31d9ae92019-09-20 13:58:06 -070012978#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
Paulo Zanoni39d1e2342018-08-01 10:34:41 -070012979
Anusha Srivatsa0caf6252019-07-11 22:57:05 -070012980#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
José Roberto de Souza31d9ae92019-09-20 13:58:06 -070012981#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
Paulo Zanoni39d1e2342018-08-01 10:34:41 -070012982
Clinton A Taylor3b51be42019-09-26 14:06:56 -070012983#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
12984#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
12985#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
12986#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
12987
José Roberto de Souza55ce3062021-05-18 17:06:13 -070012988#define _TCSS_DDI_STATUS_1 0x161500
12989#define _TCSS_DDI_STATUS_2 0x161504
12990#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
12991 _TCSS_DDI_STATUS_1, \
12992 _TCSS_DDI_STATUS_2))
12993#define TCSS_DDI_STATUS_READY REG_BIT(2)
12994#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
12995#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
12996
Animesh Mannaa6e58d92019-09-20 17:29:25 +053012997/* This register controls the Display State Buffer (DSB) engines. */
12998#define _DSBSL_INSTANCE_BASE 0x70B00
12999#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
Animesh Mannad04a6612019-12-05 18:05:13 +053013000 (pipe) * 0x1000 + (id) * 0x100)
Animesh Manna1abf3292019-09-20 17:29:27 +053013001#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
13002#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
Animesh Mannaa6e58d92019-09-20 17:29:25 +053013003#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
Animesh Mannaf7619c42019-09-20 17:29:26 +053013004#define DSB_ENABLE (1 << 31)
Animesh Mannaa6e58d92019-09-20 17:29:25 +053013005#define DSB_STATUS (1 << 0)
13006
José Roberto de Souza1d3cc7a2020-08-07 12:26:28 -070013007#define TGL_ROOT_DEVICE_ID 0x9A00
13008#define TGL_ROOT_DEVICE_MASK 0xFF00
13009#define TGL_ROOT_DEVICE_SKU_MASK 0xF
13010#define TGL_ROOT_DEVICE_SKU_ULX 0x2
13011#define TGL_ROOT_DEVICE_SKU_ULT 0x4
13012
José Roberto de Souza41c70d22021-04-08 13:49:16 -070013013#define CLKREQ_POLICY _MMIO(0x101038)
13014#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
13015
José Roberto de Souza641dd822021-09-14 14:25:07 -070013016#define CLKGATE_DIS_MISC _MMIO(0x46534)
13017#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
13018
Matt Roper645cc0b2021-11-02 15:25:10 -070013019#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C)
13020#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
13021
Jesse Barnes585fb112008-07-29 11:54:06 -070013022#endif /* _I915_REG_H_ */