| commit | b377e0df1118e63873f3fd5182ebd6c918f2805c | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Thu Oct 29 21:25:59 2015 +0200 |
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | Tue Nov 10 16:23:42 2015 +0200 |
| tree | e67791386a6e91c3ad6aaa08be3d72462dcde51c | |
| parent | d6fbdd157c1c986662deb53d8c16a19cc25eede1 [diff] [blame] |
drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ The DP link frequency is 162MHz, not 160MHz. Rename the ILK eDP PLL defines to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-11-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2183a6e..3b24993 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4199,7 +4199,7 @@ /* eDP */ #define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) +#define DP_PLL_FREQ_162MHZ (1 << 16) #define DP_PLL_FREQ_MASK (3 << 16) /* locked once port is enabled */