commit 7f1bdbcb325b5cdae8c440980dabb5ed081012d5
author Daniel Vetter <daniel.vetter@ffwll.ch> Thu Jan 16 16:42:54 2014 +0100
committer Daniel Vetter <daniel.vetter@ffwll.ch> Fri Jan 24 17:22:45 2014 +0100
tree 4436f1db19b5daf256021369dc51ece58080b514
parent cc9bd499d3bcdb31709a37b3c637cbff96e70f58

drm/i915: Only restore backlight combination mode reg for ums

This was forgotten in

commit 565ee3897f0cb1e9b09905747b3784e6605767e8
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Wed Nov 13 12:56:29 2013 +0200

    drm/i915: do not save/restore backlight registers in KMS

Since the confusion was likely due to the duplicated definition for
this pci config register, let's unify that, too.

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a48b7ca..bad97ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -73,7 +73,8 @@
 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
-#define LBB	0xf4
+#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
+
 
 /* Graphics reset regs */
 #define I965_GDRST 0xc0 /* PCI config register */