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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Daniel Vetter5a6b5c82013-10-16 22:55:47 +020029#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))
Paulo Zanonia5c961d2012-10-24 15:59:34 -020030#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
Chris Wilson5eddb702010-09-11 13:48:45 +010031
Eugeni Dodonov2b139522012-03-29 12:32:22 -030032#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
33
Daniel Vetter6b26c862012-04-24 14:04:12 +020034#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
35#define _MASKED_BIT_DISABLE(a) ((a) << 16)
36
Jesse Barnes585fb112008-07-29 11:54:06 -070037/* PCI config space */
38
39#define HPLLCC 0xc0 /* 855 only */
Jesse Barnes652c3932009-08-17 13:31:43 -070040#define GC_CLOCK_CONTROL_MASK (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070041#define GC_CLOCK_133_200 (0 << 0)
42#define GC_CLOCK_100_200 (1 << 0)
43#define GC_CLOCK_100_133 (2 << 0)
44#define GC_CLOCK_166_250 (3 << 0)
Jesse Barnesf97108d2010-01-29 11:27:07 -080045#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070046#define GCFGC 0xf0 /* 915+ only */
47#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
48#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
49#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +020050#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
52#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
53#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
54#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
55#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070056#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070057#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
58#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
59#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
60#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
61#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
62#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
63#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
64#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
65#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
66#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
67#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
68#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
69#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
70#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
71#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
72#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
73#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
74#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
75#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070076#define LBB 0xf4
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070077
78/* Graphics reset regs */
Kenneth Graunke0573ed42010-09-11 03:17:19 -070079#define I965_GDRST 0xc0 /* PCI config register */
80#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070081#define GRDOM_FULL (0<<2)
82#define GRDOM_RENDER (1<<2)
83#define GRDOM_MEDIA (3<<2)
Jesse Barnes8a5c2ae2013-03-28 13:57:19 -070084#define GRDOM_MASK (3<<2)
Daniel Vetter5ccce182012-04-27 15:17:45 +020085#define GRDOM_RESET_ENABLE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -070086
Jesse Barnes07b7ddd2011-08-03 11:28:44 -070087#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
88#define GEN6_MBC_SNPCR_SHIFT 21
89#define GEN6_MBC_SNPCR_MASK (3<<21)
90#define GEN6_MBC_SNPCR_MAX (0<<21)
91#define GEN6_MBC_SNPCR_MED (1<<21)
92#define GEN6_MBC_SNPCR_LOW (2<<21)
93#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
94
Daniel Vetter5eb719c2012-02-09 17:15:48 +010095#define GEN6_MBCTL 0x0907c
96#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
101
Eric Anholtcff458c2010-11-18 09:31:14 +0800102#define GEN6_GDRST 0x941c
103#define GEN6_GRDOM_FULL (1 << 0)
104#define GEN6_GRDOM_RENDER (1 << 1)
105#define GEN6_GRDOM_MEDIA (1 << 2)
106#define GEN6_GRDOM_BLT (1 << 3)
107
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100108#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
109#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
110#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
111#define PP_DIR_DCLV_2G 0xffffffff
112
113#define GAM_ECOCHK 0x4090
114#define ECOCHK_SNB_BIT (1<<10)
Ben Widawskye3dff582013-03-20 14:49:14 -0700115#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100116#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
117#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300118#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
119#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
120#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
121#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
122#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100123
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200124#define GAC_ECO_BITS 0x14090
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300125#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200126#define ECOBITS_PPGTT_CACHE64B (3<<8)
127#define ECOBITS_PPGTT_CACHE4B (0<<8)
128
Daniel Vetterbe901a52012-04-11 20:42:39 +0200129#define GAB_CTL 0x24000
130#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
131
Jesse Barnes585fb112008-07-29 11:54:06 -0700132/* VGA stuff */
133
134#define VGA_ST01_MDA 0x3ba
135#define VGA_ST01_CGA 0x3da
136
137#define VGA_MSR_WRITE 0x3c2
138#define VGA_MSR_READ 0x3cc
139#define VGA_MSR_MEM_EN (1<<1)
140#define VGA_MSR_CGA_MODE (1<<0)
141
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300142#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100143#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300144#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700145
146#define VGA_AR_INDEX 0x3c0
147#define VGA_AR_VID_EN (1<<5)
148#define VGA_AR_DATA_WRITE 0x3c0
149#define VGA_AR_DATA_READ 0x3c1
150
151#define VGA_GR_INDEX 0x3ce
152#define VGA_GR_DATA 0x3cf
153/* GR05 */
154#define VGA_GR_MEM_READ_MODE_SHIFT 3
155#define VGA_GR_MEM_READ_MODE_PLANE 1
156/* GR06 */
157#define VGA_GR_MEM_MODE_MASK 0xc
158#define VGA_GR_MEM_MODE_SHIFT 2
159#define VGA_GR_MEM_A0000_AFFFF 0
160#define VGA_GR_MEM_A0000_BFFFF 1
161#define VGA_GR_MEM_B0000_B7FFF 2
162#define VGA_GR_MEM_B0000_BFFFF 3
163
164#define VGA_DACMASK 0x3c6
165#define VGA_DACRX 0x3c7
166#define VGA_DACWX 0x3c8
167#define VGA_DACDATA 0x3c9
168
169#define VGA_CR_INDEX_MDA 0x3b4
170#define VGA_CR_DATA_MDA 0x3b5
171#define VGA_CR_INDEX_CGA 0x3d4
172#define VGA_CR_DATA_CGA 0x3d5
173
174/*
175 * Memory interface instructions used by the kernel
176 */
177#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
178
179#define MI_NOOP MI_INSTR(0, 0)
180#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
181#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200182#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700183#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
184#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
185#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
186#define MI_FLUSH MI_INSTR(0x04, 0)
187#define MI_READ_FLUSH (1 << 0)
188#define MI_EXE_FLUSH (1 << 1)
189#define MI_NO_WRITE_FLUSH (1 << 2)
190#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
191#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800192#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Jesse Barnes585fb112008-07-29 11:54:06 -0700193#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800194#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
195#define MI_SUSPEND_FLUSH_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700196#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400197#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200198#define MI_OVERLAY_CONTINUE (0x0<<21)
199#define MI_OVERLAY_ON (0x1<<21)
200#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700201#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500202#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700203#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500204#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200205/* IVB has funny definitions for which plane to flip. */
206#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
207#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
208#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
209#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
210#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
211#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Ben Widawskye37ec392012-06-04 14:42:48 -0700212#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
213#define MI_ARB_ENABLE (1<<0)
214#define MI_ARB_DISABLE (0<<0)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200215
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800216#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
217#define MI_MM_SPACE_GTT (1<<8)
218#define MI_MM_SPACE_PHYSICAL (0<<8)
219#define MI_SAVE_EXT_STATE_EN (1<<3)
220#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800221#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800222#define MI_RESTORE_INHIBIT (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700223#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
224#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
225#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
226#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000227/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
228 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
229 * simply ignores the register load under certain conditions.
230 * - One can actually load arbitrary many arbitrary registers: Simply issue x
231 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
232 */
233#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
Chris Wilsonffe74d72013-08-26 20:58:12 +0100234#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
Chris Wilson71a77e02011-02-02 12:13:49 +0000235#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700236#define MI_FLUSH_DW_STORE_INDEX (1<<21)
237#define MI_INVALIDATE_TLB (1<<18)
238#define MI_FLUSH_DW_OP_STOREDW (1<<14)
239#define MI_INVALIDATE_BSD (1<<7)
240#define MI_FLUSH_DW_USE_GTT (1<<2)
241#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700242#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100243#define MI_BATCH_NON_SECURE (1)
244/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
245#define MI_BATCH_NON_SECURE_I965 (1<<8)
246#define MI_BATCH_PPGTT_HSW (1<<8)
247#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700248#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100249#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000250#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
251#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
252#define MI_SEMAPHORE_UPDATE (1<<21)
253#define MI_SEMAPHORE_COMPARE (1<<20)
254#define MI_SEMAPHORE_REGISTER (1<<18)
Ben Widawsky1950de12013-05-28 19:22:20 -0700255#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
256#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
257#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
258#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
259#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
260#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
261#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
262#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
263#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
264#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
265#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
266#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
267#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300268
269#define MI_PREDICATE_RESULT_2 (0x2214)
270#define LOWER_SLICE_ENABLED (1<<0)
271#define LOWER_SLICE_DISABLED (0<<0)
272
Jesse Barnes585fb112008-07-29 11:54:06 -0700273/*
274 * 3D instructions used by the kernel
275 */
276#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
277
278#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
279#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
280#define SC_UPDATE_SCISSOR (0x1<<1)
281#define SC_ENABLE_MASK (0x1<<0)
282#define SC_ENABLE (0x1<<0)
283#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
284#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
285#define SCI_YMIN_MASK (0xffff<<16)
286#define SCI_XMIN_MASK (0xffff<<0)
287#define SCI_YMAX_MASK (0xffff<<16)
288#define SCI_XMAX_MASK (0xffff<<0)
289#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
290#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
291#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
292#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
293#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
294#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
295#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
296#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
297#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
298#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
299#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
300#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
301#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
302#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
303#define BLT_DEPTH_8 (0<<24)
304#define BLT_DEPTH_16_565 (1<<24)
305#define BLT_DEPTH_16_1555 (2<<24)
306#define BLT_DEPTH_32 (3<<24)
307#define BLT_ROP_GXCOPY (0xcc<<16)
308#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
309#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
310#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
311#define ASYNC_FLIP (1<<22)
312#define DISPLAY_PLANE_A (0<<20)
313#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200314#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200315#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Jesse Barnes8d315282011-10-16 10:23:31 +0200316#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700317#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200318#define PIPE_CONTROL_QW_WRITE (1<<14)
319#define PIPE_CONTROL_DEPTH_STALL (1<<13)
320#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200321#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200322#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
323#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
324#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
325#define PIPE_CONTROL_NOTIFY (1<<8)
Jesse Barnes8d315282011-10-16 10:23:31 +0200326#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
327#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
328#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200329#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200330#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700331#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700332
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100333
334/*
335 * Reset registers
336 */
337#define DEBUG_RESET_I830 0x6070
338#define DEBUG_RESET_FULL (1<<7)
339#define DEBUG_RESET_RENDER (1<<8)
340#define DEBUG_RESET_DISPLAY (1<<9)
341
Jesse Barnes57f350b2012-03-28 13:39:25 -0700342/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300343 * IOSF sideband
344 */
345#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
346#define IOSF_DEVFN_SHIFT 24
347#define IOSF_OPCODE_SHIFT 16
348#define IOSF_PORT_SHIFT 8
349#define IOSF_BYTE_ENABLES_SHIFT 4
350#define IOSF_BAR_SHIFT 1
351#define IOSF_SB_BUSY (1<<0)
Jesse Barnesf3419152013-11-04 11:52:44 -0800352#define IOSF_PORT_BUNIT 0x3
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300353#define IOSF_PORT_PUNIT 0x4
354#define IOSF_PORT_NC 0x11
355#define IOSF_PORT_DPIO 0x12
Jani Nikulae9f882a2013-08-27 15:12:14 +0300356#define IOSF_PORT_GPIO_NC 0x13
357#define IOSF_PORT_CCK 0x14
358#define IOSF_PORT_CCU 0xA9
359#define IOSF_PORT_GPS_CORE 0x48
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300360#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
361#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
362
Jesse Barnes30a970c2013-11-04 13:48:12 -0800363/* See configdb bunit SB addr map */
364#define BUNIT_REG_BISOC 0x11
365
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300366#define PUNIT_OPCODE_REG_READ 6
367#define PUNIT_OPCODE_REG_WRITE 7
368
Jesse Barnes30a970c2013-11-04 13:48:12 -0800369#define PUNIT_REG_DSPFREQ 0x36
370#define DSPFREQSTAT_SHIFT 30
371#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
372#define DSPFREQGUAR_SHIFT 14
373#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800374#define PUNIT_REG_PWRGT_CTRL 0x60
375#define PUNIT_REG_PWRGT_STATUS 0x61
376#define PUNIT_CLK_GATE 1
377#define PUNIT_PWR_RESET 2
378#define PUNIT_PWR_GATE 3
379#define RENDER_PWRGT (PUNIT_PWR_GATE << 0)
380#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2)
381#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6)
382
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300383#define PUNIT_REG_GPU_LFM 0xd3
384#define PUNIT_REG_GPU_FREQ_REQ 0xd4
385#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläe8474402013-06-26 17:43:24 +0300386#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300387#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
388
389#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
390#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
391
392#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
393#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
394#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
395#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
396#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
397#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
398#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
399#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
400#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
401#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
402
ymohanmabe4fc042013-08-27 23:40:56 +0300403/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800404#define CCK_FUSE_REG 0x8
405#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300406#define CCK_REG_DSI_PLL_FUSE 0x44
407#define CCK_REG_DSI_PLL_CONTROL 0x48
408#define DSI_PLL_VCO_EN (1 << 31)
409#define DSI_PLL_LDO_GATE (1 << 30)
410#define DSI_PLL_P1_POST_DIV_SHIFT 17
411#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
412#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
413#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
414#define DSI_PLL_MUX_MASK (3 << 9)
415#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
416#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
417#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
418#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
419#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
420#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
421#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
422#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
423#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
424#define DSI_PLL_LOCK (1 << 0)
425#define CCK_REG_DSI_PLL_DIVIDER 0x4c
426#define DSI_PLL_LFSR (1 << 31)
427#define DSI_PLL_FRACTION_EN (1 << 30)
428#define DSI_PLL_FRAC_COUNTER_SHIFT 27
429#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
430#define DSI_PLL_USYNC_CNT_SHIFT 18
431#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
432#define DSI_PLL_N1_DIV_SHIFT 16
433#define DSI_PLL_N1_DIV_MASK (3 << 16)
434#define DSI_PLL_M1_DIV_SHIFT 0
435#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800436#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
ymohanmabe4fc042013-08-27 23:40:56 +0300437
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300438/*
439 * DPIO - a special bus for various display related registers to hide behind
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200440 *
441 * DPIO is VLV only.
Daniel Vetter598fac62013-04-18 22:01:46 +0200442 *
443 * Note: digital port B is DDI0, digital pot C is DDI1
Jesse Barnes57f350b2012-03-28 13:39:25 -0700444 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300445#define DPIO_DEVFN 0
446#define DPIO_OPCODE_REG_WRITE 1
447#define DPIO_OPCODE_REG_READ 0
448
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200449#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700450#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
451#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
452#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700453#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700454
Daniel Vetter598fac62013-04-18 22:01:46 +0200455#define _DPIO_TX3_SWING_CTL4_A 0x690
456#define _DPIO_TX3_SWING_CTL4_B 0x2a90
Chon Ming Lee93d1f992013-10-30 10:05:19 +0800457#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \
Daniel Vetter598fac62013-04-18 22:01:46 +0200458 _DPIO_TX3_SWING_CTL4_B)
459
460/*
461 * Per pipe/PLL DPIO regs
462 */
Jesse Barnes57f350b2012-03-28 13:39:25 -0700463#define _DPIO_DIV_A 0x800c
464#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200465#define DPIO_POST_DIV_DAC 0
466#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
467#define DPIO_POST_DIV_LVDS1 2
468#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700469#define DPIO_K_SHIFT (24) /* 4 bits */
470#define DPIO_P1_SHIFT (21) /* 3 bits */
471#define DPIO_P2_SHIFT (16) /* 5 bits */
472#define DPIO_N_SHIFT (12) /* 4 bits */
473#define DPIO_ENABLE_CALIBRATION (1<<11)
474#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
475#define DPIO_M2DIV_MASK 0xff
476#define _DPIO_DIV_B 0x802c
477#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
478
479#define _DPIO_REFSFR_A 0x8014
480#define DPIO_REFSEL_OVERRIDE 27
481#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
482#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
483#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530484#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700485#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
486#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
487#define _DPIO_REFSFR_B 0x8034
488#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
489
490#define _DPIO_CORE_CLK_A 0x801c
491#define _DPIO_CORE_CLK_B 0x803c
492#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
493
Daniel Vetter598fac62013-04-18 22:01:46 +0200494#define _DPIO_IREF_CTL_A 0x8040
495#define _DPIO_IREF_CTL_B 0x8060
496#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
497
498#define DPIO_IREF_BCAST 0xc044
499#define _DPIO_IREF_A 0x8044
500#define _DPIO_IREF_B 0x8064
501#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
502
503#define _DPIO_PLL_CML_A 0x804c
504#define _DPIO_PLL_CML_B 0x806c
505#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
506
Ville Syrjälä4abb2c32013-06-14 14:02:53 +0300507#define _DPIO_LPF_COEFF_A 0x8048
508#define _DPIO_LPF_COEFF_B 0x8068
509#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700510
Daniel Vetter598fac62013-04-18 22:01:46 +0200511#define DPIO_CALIBRATION 0x80ac
512
Jesse Barnes57f350b2012-03-28 13:39:25 -0700513#define DPIO_FASTCLK_DISABLE 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100514
Daniel Vetter598fac62013-04-18 22:01:46 +0200515/*
516 * Per DDI channel DPIO regs
517 */
518
519#define _DPIO_PCS_TX_0 0x8200
520#define _DPIO_PCS_TX_1 0x8400
521#define DPIO_PCS_TX_LANE2_RESET (1<<16)
522#define DPIO_PCS_TX_LANE1_RESET (1<<7)
523#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
524
525#define _DPIO_PCS_CLK_0 0x8204
526#define _DPIO_PCS_CLK_1 0x8404
527#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
528#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
529#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
530#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
531#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
532
533#define _DPIO_PCS_CTL_OVR1_A 0x8224
534#define _DPIO_PCS_CTL_OVR1_B 0x8424
535#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
536 _DPIO_PCS_CTL_OVR1_B)
537
538#define _DPIO_PCS_STAGGER0_A 0x822c
539#define _DPIO_PCS_STAGGER0_B 0x842c
540#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
541 _DPIO_PCS_STAGGER0_B)
542
543#define _DPIO_PCS_STAGGER1_A 0x8230
544#define _DPIO_PCS_STAGGER1_B 0x8430
545#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
546 _DPIO_PCS_STAGGER1_B)
547
548#define _DPIO_PCS_CLOCKBUF0_A 0x8238
549#define _DPIO_PCS_CLOCKBUF0_B 0x8438
550#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
551 _DPIO_PCS_CLOCKBUF0_B)
552
553#define _DPIO_PCS_CLOCKBUF8_A 0x825c
554#define _DPIO_PCS_CLOCKBUF8_B 0x845c
555#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
556 _DPIO_PCS_CLOCKBUF8_B)
557
558#define _DPIO_TX_SWING_CTL2_A 0x8288
559#define _DPIO_TX_SWING_CTL2_B 0x8488
560#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
561 _DPIO_TX_SWING_CTL2_B)
562
563#define _DPIO_TX_SWING_CTL3_A 0x828c
564#define _DPIO_TX_SWING_CTL3_B 0x848c
565#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
566 _DPIO_TX_SWING_CTL3_B)
567
568#define _DPIO_TX_SWING_CTL4_A 0x8290
569#define _DPIO_TX_SWING_CTL4_B 0x8490
570#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
571 _DPIO_TX_SWING_CTL4_B)
572
573#define _DPIO_TX_OCALINIT_0 0x8294
574#define _DPIO_TX_OCALINIT_1 0x8494
575#define DPIO_TX_OCALINIT_EN (1<<31)
576#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
577 _DPIO_TX_OCALINIT_1)
578
579#define _DPIO_TX_CTL_0 0x82ac
580#define _DPIO_TX_CTL_1 0x84ac
581#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
582
583#define _DPIO_TX_LANE_0 0x82b8
584#define _DPIO_TX_LANE_1 0x84b8
585#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
586
587#define _DPIO_DATA_CHANNEL1 0x8220
588#define _DPIO_DATA_CHANNEL2 0x8420
589#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
590
591#define _DPIO_PORT0_PCS0 0x0220
592#define _DPIO_PORT0_PCS1 0x0420
593#define _DPIO_PORT1_PCS2 0x2620
594#define _DPIO_PORT1_PCS3 0x2820
595#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
596#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
597#define DPIO_DATA_CHANNEL1 0x8220
598#define DPIO_DATA_CHANNEL2 0x8420
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530599
Jesse Barnes585fb112008-07-29 11:54:06 -0700600/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800601 * Fence registers
602 */
603#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -0700604#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -0800605#define I830_FENCE_START_MASK 0x07f80000
606#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -0800607#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800608#define I830_FENCE_PITCH_SHIFT 4
609#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +0200610#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -0700611#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200612#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800613
614#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -0800615#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800616
617#define FENCE_REG_965_0 0x03000
618#define I965_FENCE_PITCH_SHIFT 2
619#define I965_FENCE_TILING_Y_SHIFT 1
620#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200621#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -0800622
Eric Anholt4e901fd2009-10-26 16:44:17 -0700623#define FENCE_REG_SANDYBRIDGE_0 0x100000
624#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +0300625#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -0700626
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100627/* control register for cpu gtt access */
628#define TILECTL 0x101000
629#define TILECTL_SWZCTL (1 << 0)
630#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
631#define TILECTL_BACKSNOOP_DIS (1 << 3)
632
Jesse Barnesde151cf2008-11-12 10:03:55 -0800633/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700634 * Instruction and interrupt control regs
635 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700636#define PGTBL_ER 0x02024
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200637#define RENDER_RING_BASE 0x02000
638#define BSD_RING_BASE 0x04000
639#define GEN6_BSD_RING_BASE 0x12000
Ben Widawsky1950de12013-05-28 19:22:20 -0700640#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +0100641#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +0200642#define RING_TAIL(base) ((base)+0x30)
643#define RING_HEAD(base) ((base)+0x34)
644#define RING_START(base) ((base)+0x38)
645#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000646#define RING_SYNC_0(base) ((base)+0x40)
647#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawsky1950de12013-05-28 19:22:20 -0700648#define RING_SYNC_2(base) ((base)+0x48)
649#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
650#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
651#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
652#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
653#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
654#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
655#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
656#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
657#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
658#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
659#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
660#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ben Widawskyad776f82013-05-28 19:22:18 -0700661#define GEN6_NOSYNC 0
Chris Wilson8fd26852010-12-08 18:40:43 +0000662#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +0200663#define RING_HWS_PGA(base) ((base)+0x80)
664#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100665#define ARB_MODE 0x04030
666#define ARB_MODE_SWIZZLE_SNB (1<<4)
667#define ARB_MODE_SWIZZLE_IVB (1<<5)
Eric Anholt45930102011-05-06 17:12:35 -0700668#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +0100669#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -0700670#define RING_FAULT_GTTSEL_MASK (1<<11)
671#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
672#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
673#define RING_FAULT_VALID (1<<0)
Daniel Vetter33f3f512011-12-14 13:57:39 +0100674#define DONE_REG 0x40b0
Eric Anholt45930102011-05-06 17:12:35 -0700675#define BSD_HWS_PGA_GEN7 (0x04180)
676#define BLT_HWS_PGA_GEN7 (0x04280)
Ben Widawsky9a8a2212013-05-28 19:22:23 -0700677#define VEBOX_HWS_PGA_GEN7 (0x04380)
Daniel Vetter3d281d82010-09-24 21:14:22 +0200678#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000679#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +0000680#define RING_IMR(base) ((base)+0xa8)
Ben Widawskyc0c7bab2012-07-12 11:01:05 -0700681#define RING_TIMESTAMP(base) ((base)+0x358)
Jesse Barnes585fb112008-07-29 11:54:06 -0700682#define TAIL_ADDR 0x001FFFF8
683#define HEAD_WRAP_COUNT 0xFFE00000
684#define HEAD_WRAP_ONE 0x00200000
685#define HEAD_ADDR 0x001FFFFC
686#define RING_NR_PAGES 0x001FF000
687#define RING_REPORT_MASK 0x00000006
688#define RING_REPORT_64K 0x00000002
689#define RING_REPORT_128K 0x00000004
690#define RING_NO_REPORT 0x00000000
691#define RING_VALID_MASK 0x00000001
692#define RING_VALID 0x00000001
693#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +0100694#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
695#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000696#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Chris Wilson8168bd42010-11-11 17:54:52 +0000697#if 0
698#define PRB0_TAIL 0x02030
699#define PRB0_HEAD 0x02034
700#define PRB0_START 0x02038
701#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -0700702#define PRB1_TAIL 0x02040 /* 915+ only */
703#define PRB1_HEAD 0x02044 /* 915+ only */
704#define PRB1_START 0x02048 /* 915+ only */
705#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +0000706#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700707#define IPEIR_I965 0x02064
708#define IPEHR_I965 0x02068
709#define INSTDONE_I965 0x0206c
Ben Widawskyd53bd482012-08-22 11:32:14 -0700710#define GEN7_INSTDONE_1 0x0206c
711#define GEN7_SC_INSTDONE 0x07100
712#define GEN7_SAMPLER_INSTDONE 0x0e160
713#define GEN7_ROW_INSTDONE 0x0e164
714#define I915_NUM_INSTDONE_REG 4
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100715#define RING_IPEIR(base) ((base)+0x64)
716#define RING_IPEHR(base) ((base)+0x68)
717#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100718#define RING_INSTPS(base) ((base)+0x70)
719#define RING_DMA_FADD(base) ((base)+0x78)
720#define RING_INSTPM(base) ((base)+0xc0)
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700721#define INSTPS 0x02070 /* 965+ only */
722#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -0700723#define ACTHD_I965 0x02074
724#define HWS_PGA 0x02080
725#define HWS_ADDRESS_MASK 0xfffff000
726#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -0700727#define PWRCTXA 0x2088 /* 965GM+ only */
728#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700729#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700730#define IPEHR 0x0208c
731#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -0700732#define NOPID 0x02094
733#define HWSTAM 0x02098
Daniel Vetter9d2f41f2012-04-02 21:41:45 +0200734#define DMA_FADD_I8XX 0x020d0
Chris Wilson94e39e22013-10-30 09:28:22 +0000735#define RING_BBSTATE(base) ((base)+0x110)
Eric Anholt71cf39b2010-03-08 23:41:55 -0800736
Chris Wilsonf4068392010-10-27 20:36:41 +0100737#define ERROR_GEN6 0x040a0
Ben Widawsky71e172e2012-08-20 16:15:13 -0700738#define GEN7_ERR_INT 0x44040
Paulo Zanonide032bf2013-04-12 17:57:58 -0300739#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -0300740#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +0100741#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -0300742#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +0100743#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -0300744#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +0100745#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Daniel Vetter5a69b892013-10-16 22:55:52 +0200746#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -0300747#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Daniel Vetter7336df62013-07-09 22:59:16 +0200748#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Chris Wilsonf4068392010-10-27 20:36:41 +0100749
Paulo Zanoni3f1e1092013-02-18 19:00:21 -0300750#define FPGA_DBG 0x42300
751#define FPGA_DBG_RM_NOCLAIM (1<<31)
752
Chris Wilson0f3b6842013-01-15 12:05:55 +0000753#define DERRMR 0x44050
Chris Wilsonffe74d72013-08-26 20:58:12 +0100754#define DERRMR_PIPEA_SCANLINE (1<<0)
755#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
756#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
757#define DERRMR_PIPEA_VBLANK (1<<3)
758#define DERRMR_PIPEA_HBLANK (1<<5)
759#define DERRMR_PIPEB_SCANLINE (1<<8)
760#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
761#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
762#define DERRMR_PIPEB_VBLANK (1<<11)
763#define DERRMR_PIPEB_HBLANK (1<<13)
764/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
765#define DERRMR_PIPEC_SCANLINE (1<<14)
766#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
767#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
768#define DERRMR_PIPEC_VBLANK (1<<21)
769#define DERRMR_PIPEC_HBLANK (1<<22)
770
Chris Wilson0f3b6842013-01-15 12:05:55 +0000771
Eric Anholtde6e2ea2010-11-06 14:53:32 -0700772/* GM45+ chicken bits -- debug workaround bits that may be required
773 * for various sorts of correct behavior. The top 16 bits of each are
774 * the enables for writing to the corresponding low bit.
775 */
776#define _3D_CHICKEN 0x02084
Daniel Vetter42839082012-12-14 23:38:28 +0100777#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Eric Anholtde6e2ea2010-11-06 14:53:32 -0700778#define _3D_CHICKEN2 0x0208c
779/* Disables pipelining of read flushes past the SF-WIZ interface.
780 * Required on all Ironlake steppings according to the B-Spec, but the
781 * particular danger of not doing so is not specified.
782 */
783# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
784#define _3D_CHICKEN3 0x02090
Jesse Barnes87f80202012-10-02 17:43:41 -0500785#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -0700786#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Eric Anholtde6e2ea2010-11-06 14:53:32 -0700787
Eric Anholt71cf39b2010-03-08 23:41:55 -0800788#define MI_MODE 0x0209c
789# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -0800790# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +0000791# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Eric Anholt71cf39b2010-03-08 23:41:55 -0800792
Ben Widawskyf8f2ac92012-10-03 19:34:24 -0700793#define GEN6_GT_MODE 0x20d0
Daniel Vetter6547fbd2012-12-14 23:38:29 +0100794#define GEN6_GT_MODE_HI (1 << 9)
795#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ben Widawskyf8f2ac92012-10-03 19:34:24 -0700796
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000797#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -0700798#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100799#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000800#define GFX_RUN_LIST_ENABLE (1<<15)
801#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
802#define GFX_SURFACE_FAULT_ENABLE (1<<12)
803#define GFX_REPLAY_MODE (1<<11)
804#define GFX_PSMI_GRANULARITY (1<<10)
805#define GFX_PPGTT_ENABLE (1<<9)
806
Daniel Vettera7e806d2012-07-11 16:27:55 +0200807#define VLV_DISPLAY_BASE 0x180000
808
Jesse Barnes585fb112008-07-29 11:54:06 -0700809#define SCPD0 0x0209c /* 915+ only */
810#define IER 0x020a0
811#define IIR 0x020a4
812#define IMR 0x020a8
813#define ISR 0x020ac
Ville Syrjälä07ec7ec2013-01-24 15:29:51 +0200814#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
Jesse Barnes2d809572012-10-25 12:15:44 -0700815#define GCFG_DIS (1<<8)
Ville Syrjäläff763012013-01-24 15:29:52 +0200816#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
817#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
818#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
819#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
820#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
Jesse Barnesc9cddff2013-05-08 10:45:13 -0700821#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
Ville Syrjälä90a72f82013-02-19 23:16:44 +0200822#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Jesse Barnes585fb112008-07-29 11:54:06 -0700823#define EIR 0x020b0
824#define EMR 0x020b4
825#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700826#define GM45_ERROR_PAGE_TABLE (1<<5)
827#define GM45_ERROR_MEM_PRIV (1<<4)
828#define I915_ERROR_PAGE_TABLE (1<<4)
829#define GM45_ERROR_CP_PRIV (1<<3)
830#define I915_ERROR_MEMORY_REFRESH (1<<1)
831#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700832#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +0800833#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Chris Wilson8692d00e2011-02-05 10:08:21 +0000834#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
835 will not assert AGPBUSY# and will only
836 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -0800837#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +0100838#define INSTPM_TLB_INVALIDATE (1<<9)
839#define INSTPM_SYNC_FLUSH (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -0700840#define ACTHD 0x020c8
841#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +0000842#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -0700843#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +0800844#define FW_BLC_SELF_EN_MASK (1<<31)
845#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
846#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +0800847#define MM_BURST_LENGTH 0x00700000
848#define MM_FIFO_WATERMARK 0x0001F000
849#define LM_BURST_LENGTH 0x00000700
850#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -0700851#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -0700852
853/* Make render/texture TLB fetches lower priorty than associated data
854 * fetches. This is not turned on by default
855 */
856#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
857
858/* Isoch request wait on GTT enable (Display A/B/C streams).
859 * Make isoch requests stall on the TLB update. May cause
860 * display underruns (test mode only)
861 */
862#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
863
864/* Block grant count for isoch requests when block count is
865 * set to a finite value.
866 */
867#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
868#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
869#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
870#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
871#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
872
873/* Enable render writes to complete in C2/C3/C4 power states.
874 * If this isn't enabled, render writes are prevented in low
875 * power states. That seems bad to me.
876 */
877#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
878
879/* This acknowledges an async flip immediately instead
880 * of waiting for 2TLB fetches.
881 */
882#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
883
884/* Enables non-sequential data reads through arbiter
885 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400886#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -0700887
888/* Disable FSB snooping of cacheable write cycles from binner/render
889 * command stream
890 */
891#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
892
893/* Arbiter time slice for non-isoch streams */
894#define MI_ARB_TIME_SLICE_MASK (7 << 5)
895#define MI_ARB_TIME_SLICE_1 (0 << 5)
896#define MI_ARB_TIME_SLICE_2 (1 << 5)
897#define MI_ARB_TIME_SLICE_4 (2 << 5)
898#define MI_ARB_TIME_SLICE_6 (3 << 5)
899#define MI_ARB_TIME_SLICE_8 (4 << 5)
900#define MI_ARB_TIME_SLICE_10 (5 << 5)
901#define MI_ARB_TIME_SLICE_14 (6 << 5)
902#define MI_ARB_TIME_SLICE_16 (7 << 5)
903
904/* Low priority grace period page size */
905#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
906#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
907
908/* Disable display A/B trickle feed */
909#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
910
911/* Set display plane priority */
912#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
913#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
914
Jesse Barnes585fb112008-07-29 11:54:06 -0700915#define CACHE_MODE_0 0x02120 /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +0200916#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -0700917#define CM0_IZ_OPT_DISABLE (1<<6)
918#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +0200919#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -0700920#define CM0_DEPTH_EVICT_DISABLE (1<<4)
921#define CM0_COLOR_EVICT_DISABLE (1<<3)
922#define CM0_DEPTH_WRITE_DISABLE (1<<1)
923#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
Chris Wilson9df30792010-02-18 10:24:56 +0000924#define BB_ADDR 0x02140 /* 8 bytes */
Jesse Barnes585fb112008-07-29 11:54:06 -0700925#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Ben Widawsky0f9b91c2012-11-04 09:21:30 -0800926#define GFX_FLSH_CNTL_GEN6 0x101008
927#define GFX_FLSH_CNTL_EN (1<<0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700928#define ECOSKPD 0x021d0
929#define ECO_GATING_CX_ONLY (1<<3)
930#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700931
Jesse Barnesfb046852012-03-28 13:39:26 -0700932#define CACHE_MODE_1 0x7004 /* IVB+ */
933#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
934
Jesse Barnes4efe0702011-01-18 11:25:41 -0800935#define GEN6_BLITTER_ECOSKPD 0x221d0
936#define GEN6_BLITTER_LOCK_SHIFT 16
937#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
938
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100939#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
Chris Wilson12f55812012-07-05 17:14:01 +0100940#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
941#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
942#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
943#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100944
Ben Widawskycc609d52013-05-28 19:22:29 -0700945/* On modern GEN architectures interrupt control consists of two sets
946 * of registers. The first set pertains to the ring generating the
947 * interrupt. The second control is for the functional block generating the
948 * interrupt. These are PM, GT, DE, etc.
949 *
950 * Luckily *knocks on wood* all the ring interrupt bits match up with the
951 * GT interrupt bits, so we don't need to duplicate the defines.
952 *
953 * These defines should cover us well from SNB->HSW with minor exceptions
954 * it can also work on ILK.
955 */
956#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
957#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
958#define GT_BLT_USER_INTERRUPT (1 << 22)
959#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
960#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700961#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Ben Widawskycc609d52013-05-28 19:22:29 -0700962#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
963#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
964#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
965#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
966#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
967#define GT_RENDER_USER_INTERRUPT (1 << 0)
968
Ben Widawsky12638c52013-05-28 19:22:31 -0700969#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
970#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
971
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700972#define GT_PARITY_ERROR(dev) \
973 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +0300974 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700975
Ben Widawskycc609d52013-05-28 19:22:29 -0700976/* These are all the "old" interrupts */
977#define ILK_BSD_USER_INTERRUPT (1<<5)
978#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
979#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
980#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
981#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
982#define I915_HWB_OOM_INTERRUPT (1<<13)
983#define I915_SYNC_STATUS_INTERRUPT (1<<12)
984#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
985#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
986#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
987#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
988#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
989#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
990#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
991#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
992#define I915_DEBUG_INTERRUPT (1<<2)
993#define I915_USER_INTERRUPT (1<<1)
994#define I915_ASLE_INTERRUPT (1<<0)
995#define I915_BSD_USER_INTERRUPT (1 << 25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100996
997#define GEN6_BSD_RNCID 0x12198
998
Ben Widawskya1e969e2012-04-14 18:41:32 -0700999#define GEN7_FF_THREAD_MODE 0x20a0
1000#define GEN7_FF_SCHED_MASK 0x0077070
1001#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1002#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1003#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1004#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08001005#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001006#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1007#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1008#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1009#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1010#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1011#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1012#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1013#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1014
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001015/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001016 * Framebuffer compression (915+ only)
1017 */
1018
1019#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1020#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1021#define FBC_CONTROL 0x03208
1022#define FBC_CTL_EN (1<<31)
1023#define FBC_CTL_PERIODIC (1<<30)
1024#define FBC_CTL_INTERVAL_SHIFT (16)
1025#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02001026#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07001027#define FBC_CTL_STRIDE_SHIFT (5)
1028#define FBC_CTL_FENCENO (1<<0)
1029#define FBC_COMMAND 0x0320c
1030#define FBC_CMD_COMPRESS (1<<0)
1031#define FBC_STATUS 0x03210
1032#define FBC_STAT_COMPRESSING (1<<31)
1033#define FBC_STAT_COMPRESSED (1<<30)
1034#define FBC_STAT_MODIFIED (1<<29)
1035#define FBC_STAT_CURRENT_LINE (1<<0)
1036#define FBC_CONTROL2 0x03214
1037#define FBC_CTL_FENCE_DBL (0<<4)
1038#define FBC_CTL_IDLE_IMM (0<<2)
1039#define FBC_CTL_IDLE_FULL (1<<2)
1040#define FBC_CTL_IDLE_LINE (2<<2)
1041#define FBC_CTL_IDLE_DEBUG (3<<2)
1042#define FBC_CTL_CPU_FENCE (1<<1)
1043#define FBC_CTL_PLANEA (0<<0)
1044#define FBC_CTL_PLANEB (1<<0)
1045#define FBC_FENCE_OFF 0x0321b
Jesse Barnes80824002009-09-10 15:28:06 -07001046#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -07001047
1048#define FBC_LL_SIZE (1536)
1049
Jesse Barnes74dff282009-09-14 15:39:40 -07001050/* Framebuffer compression for GM45+ */
1051#define DPFC_CB_BASE 0x3200
1052#define DPFC_CONTROL 0x3208
1053#define DPFC_CTL_EN (1<<31)
1054#define DPFC_CTL_PLANEA (0<<30)
1055#define DPFC_CTL_PLANEB (1<<30)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001056#define IVB_DPFC_CTL_PLANE_SHIFT (29)
Jesse Barnes74dff282009-09-14 15:39:40 -07001057#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001058#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01001059#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07001060#define DPFC_SR_EN (1<<10)
1061#define DPFC_CTL_LIMIT_1X (0<<6)
1062#define DPFC_CTL_LIMIT_2X (1<<6)
1063#define DPFC_CTL_LIMIT_4X (2<<6)
1064#define DPFC_RECOMP_CTL 0x320c
1065#define DPFC_RECOMP_STALL_EN (1<<27)
1066#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1067#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1068#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1069#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1070#define DPFC_STATUS 0x3210
1071#define DPFC_INVAL_SEG_SHIFT (16)
1072#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1073#define DPFC_COMP_SEG_SHIFT (0)
1074#define DPFC_COMP_SEG_MASK (0x000003ff)
1075#define DPFC_STATUS2 0x3214
1076#define DPFC_FENCE_YOFF 0x3218
1077#define DPFC_CHICKEN 0x3224
1078#define DPFC_HT_MODIFY (1<<31)
1079
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001080/* Framebuffer compression for Ironlake */
1081#define ILK_DPFC_CB_BASE 0x43200
1082#define ILK_DPFC_CONTROL 0x43208
1083/* The bit 28-8 is reserved */
1084#define DPFC_RESERVED (0x1FFFFF00)
1085#define ILK_DPFC_RECOMP_CTL 0x4320c
1086#define ILK_DPFC_STATUS 0x43210
1087#define ILK_DPFC_FENCE_YOFF 0x43218
1088#define ILK_DPFC_CHICKEN 0x43224
1089#define ILK_FBC_RT_BASE 0x2128
1090#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001091#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001092
1093#define ILK_DISPLAY_CHICKEN1 0x42000
1094#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04001095#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08001096
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001097
Jesse Barnes585fb112008-07-29 11:54:06 -07001098/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001099 * Framebuffer compression for Sandybridge
1100 *
1101 * The following two registers are of type GTTMMADR
1102 */
1103#define SNB_DPFC_CTL_SA 0x100100
1104#define SNB_CPU_FENCE_ENABLE (1<<29)
1105#define DPFC_CPU_FENCE_OFFSET 0x100104
1106
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001107/* Framebuffer compression for Ivybridge */
1108#define IVB_FBC_RT_BASE 0x7020
1109
Paulo Zanoni42db64e2013-05-31 16:33:22 -03001110#define IPS_CTL 0x43408
1111#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001112
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001113#define MSG_FBC_REND_STATE 0x50380
1114#define FBC_REND_NUKE (1<<2)
1115#define FBC_REND_CACHE_CLEAN (1<<1)
1116
Rodrigo Vivi28554162013-05-06 19:37:37 -03001117#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
1118#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
1119#define HSW_BYPASS_FBC_QUEUE (1<<22)
1120#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1121 _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1122 _HSW_PIPE_SLICE_CHICKEN_1_B)
1123
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001124/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001125 * GPIO regs
1126 */
1127#define GPIOA 0x5010
1128#define GPIOB 0x5014
1129#define GPIOC 0x5018
1130#define GPIOD 0x501c
1131#define GPIOE 0x5020
1132#define GPIOF 0x5024
1133#define GPIOG 0x5028
1134#define GPIOH 0x502c
1135# define GPIO_CLOCK_DIR_MASK (1 << 0)
1136# define GPIO_CLOCK_DIR_IN (0 << 1)
1137# define GPIO_CLOCK_DIR_OUT (1 << 1)
1138# define GPIO_CLOCK_VAL_MASK (1 << 2)
1139# define GPIO_CLOCK_VAL_OUT (1 << 3)
1140# define GPIO_CLOCK_VAL_IN (1 << 4)
1141# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1142# define GPIO_DATA_DIR_MASK (1 << 8)
1143# define GPIO_DATA_DIR_IN (0 << 9)
1144# define GPIO_DATA_DIR_OUT (1 << 9)
1145# define GPIO_DATA_VAL_MASK (1 << 10)
1146# define GPIO_DATA_VAL_OUT (1 << 11)
1147# define GPIO_DATA_VAL_IN (1 << 12)
1148# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1149
Chris Wilsonf899fc62010-07-20 15:44:45 -07001150#define GMBUS0 0x5100 /* clock/port select */
1151#define GMBUS_RATE_100KHZ (0<<8)
1152#define GMBUS_RATE_50KHZ (1<<8)
1153#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1154#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1155#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1156#define GMBUS_PORT_DISABLED 0
1157#define GMBUS_PORT_SSC 1
1158#define GMBUS_PORT_VGADDC 2
1159#define GMBUS_PORT_PANEL 3
1160#define GMBUS_PORT_DPC 4 /* HDMIC */
1161#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
Daniel Kurtze4fd17a2012-03-28 02:36:12 +08001162#define GMBUS_PORT_DPD 6 /* HDMID */
1163#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001164#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
Chris Wilsonf899fc62010-07-20 15:44:45 -07001165#define GMBUS1 0x5104 /* command/status */
1166#define GMBUS_SW_CLR_INT (1<<31)
1167#define GMBUS_SW_RDY (1<<30)
1168#define GMBUS_ENT (1<<29) /* enable timeout */
1169#define GMBUS_CYCLE_NONE (0<<25)
1170#define GMBUS_CYCLE_WAIT (1<<25)
1171#define GMBUS_CYCLE_INDEX (2<<25)
1172#define GMBUS_CYCLE_STOP (4<<25)
1173#define GMBUS_BYTE_COUNT_SHIFT 16
1174#define GMBUS_SLAVE_INDEX_SHIFT 8
1175#define GMBUS_SLAVE_ADDR_SHIFT 1
1176#define GMBUS_SLAVE_READ (1<<0)
1177#define GMBUS_SLAVE_WRITE (0<<0)
1178#define GMBUS2 0x5108 /* status */
1179#define GMBUS_INUSE (1<<15)
1180#define GMBUS_HW_WAIT_PHASE (1<<14)
1181#define GMBUS_STALL_TIMEOUT (1<<13)
1182#define GMBUS_INT (1<<12)
1183#define GMBUS_HW_RDY (1<<11)
1184#define GMBUS_SATOER (1<<10)
1185#define GMBUS_ACTIVE (1<<9)
1186#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1187#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1188#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1189#define GMBUS_NAK_EN (1<<3)
1190#define GMBUS_IDLE_EN (1<<2)
1191#define GMBUS_HW_WAIT_EN (1<<1)
1192#define GMBUS_HW_RDY_EN (1<<0)
1193#define GMBUS5 0x5120 /* byte index */
1194#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08001195
Jesse Barnes585fb112008-07-29 11:54:06 -07001196/*
1197 * Clock control & power management
1198 */
1199
1200#define VGA0 0x6000
1201#define VGA1 0x6004
1202#define VGA_PD 0x6010
1203#define VGA0_PD_P2_DIV_4 (1 << 7)
1204#define VGA0_PD_P1_DIV_2 (1 << 5)
1205#define VGA0_PD_P1_SHIFT 0
1206#define VGA0_PD_P1_MASK (0x1f << 0)
1207#define VGA1_PD_P2_DIV_4 (1 << 15)
1208#define VGA1_PD_P1_DIV_2 (1 << 13)
1209#define VGA1_PD_P1_SHIFT 8
1210#define VGA1_PD_P1_MASK (0x1f << 8)
Ville Syrjäläfc2de402013-01-25 21:44:41 +02001211#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
1212#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001213#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
Jesse Barnes585fb112008-07-29 11:54:06 -07001214#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02001215#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1216#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001217#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07001218#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001219#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07001220#define DPLL_VGA_MODE_DIS (1 << 28)
1221#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1222#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1223#define DPLL_MODE_MASK (3 << 26)
1224#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1225#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1226#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1227#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1228#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1229#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001230#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07001231#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02001232#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001233#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02001234#define DPLL_PORTC_READY_MASK (0xf << 4)
1235#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07001236
Jesse Barnes585fb112008-07-29 11:54:06 -07001237#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1238/*
1239 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1240 * this field (only one bit may be set).
1241 */
1242#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1243#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001244#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07001245/* i830, required in DVO non-gang */
1246#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1247#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1248#define PLL_REF_INPUT_DREFCLK (0 << 13)
1249#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1250#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1251#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1252#define PLL_REF_INPUT_MASK (3 << 13)
1253#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001254/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08001255# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1256# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1257# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1258# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1259# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1260
Jesse Barnes585fb112008-07-29 11:54:06 -07001261/*
1262 * Parallel to Serial Load Pulse phase selection.
1263 * Selects the phase for the 10X DPLL clock for the PCIe
1264 * digital display port. The range is 4 to 13; 10 or more
1265 * is just a flip delay. The default is 6
1266 */
1267#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1268#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1269/*
1270 * SDVO multiplier for 945G/GM. Not used on 965.
1271 */
1272#define SDVO_MULTIPLIER_MASK 0x000000ff
1273#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1274#define SDVO_MULTIPLIER_SHIFT_VGA 0
Ville Syrjäläfc2de402013-01-25 21:44:41 +02001275#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001276/*
1277 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1278 *
1279 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1280 */
1281#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1282#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1283/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1284#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1285#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1286/*
1287 * SDVO/UDI pixel multiplier.
1288 *
1289 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1290 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1291 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1292 * dummy bytes in the datastream at an increased clock rate, with both sides of
1293 * the link knowing how many bytes are fill.
1294 *
1295 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1296 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1297 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1298 * through an SDVO command.
1299 *
1300 * This register field has values of multiplication factor minus 1, with
1301 * a maximum multiplier of 5 for SDVO.
1302 */
1303#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1304#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1305/*
1306 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1307 * This best be set to the default value (3) or the CRT won't work. No,
1308 * I don't entirely understand what this does...
1309 */
1310#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1311#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Ville Syrjäläfc2de402013-01-25 21:44:41 +02001312#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001313#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001314
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001315#define _FPA0 0x06040
1316#define _FPA1 0x06044
1317#define _FPB0 0x06048
1318#define _FPB1 0x0604c
1319#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1320#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07001321#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001322#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07001323#define FP_N_DIV_SHIFT 16
1324#define FP_M1_DIV_MASK 0x00003f00
1325#define FP_M1_DIV_SHIFT 8
1326#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001327#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07001328#define FP_M2_DIV_SHIFT 0
1329#define DPLL_TEST 0x606c
1330#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1331#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1332#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1333#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1334#define DPLLB_TEST_N_BYPASS (1 << 19)
1335#define DPLLB_TEST_M_BYPASS (1 << 18)
1336#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1337#define DPLLA_TEST_N_BYPASS (1 << 3)
1338#define DPLLA_TEST_M_BYPASS (1 << 2)
1339#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1340#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001341#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07001342#define DSTATE_PLL_D3_OFF (1<<3)
1343#define DSTATE_GFX_CLOCK_GATING (1<<1)
1344#define DSTATE_DOT_CLOCK_GATING (1<<0)
Ville Syrjäläd7fe0cc2013-05-21 18:01:50 +03001345#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07001346# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1347# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1348# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1349# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1350# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1351# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1352# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1353# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1354# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1355# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1356# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1357# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1358# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1359# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1360# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1361# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1362# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1363# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1364# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1365# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1366# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1367# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1368# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1369# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1370# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1371# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1372# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1373# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1374/**
1375 * This bit must be set on the 830 to prevent hangs when turning off the
1376 * overlay scaler.
1377 */
1378# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1379# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1380# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1381# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1382# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1383
1384#define RENCLK_GATE_D1 0x6204
1385# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1386# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1387# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1388# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1389# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1390# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1391# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1392# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1393# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1394/** This bit must be unset on 855,865 */
1395# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1396# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1397# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1398# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1399/** This bit must be set on 855,865. */
1400# define SV_CLOCK_GATE_DISABLE (1 << 0)
1401# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1402# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1403# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1404# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1405# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1406# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1407# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1408# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1409# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1410# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1411# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1412# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1413# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1414# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1415# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1416# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1417# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1418
1419# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1420/** This bit must always be set on 965G/965GM */
1421# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1422# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1423# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1424# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1425# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1426# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1427/** This bit must always be set on 965G */
1428# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1429# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1430# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1431# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1432# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1433# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1434# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1435# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1436# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1437# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1438# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1439# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1440# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1441# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1442# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1443# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1444# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1445# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1446# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1447
1448#define RENCLK_GATE_D2 0x6208
1449#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1450#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1451#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1452#define RAMCLK_GATE_D 0x6210 /* CRL only */
1453#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001454
Ville Syrjäläd88b2272013-01-24 15:29:48 +02001455#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07001456#define FW_CSPWRDWNEN (1<<15)
1457
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03001458#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1459
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08001460#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1461#define CDCLK_FREQ_SHIFT 4
1462#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1463#define CZCLK_FREQ_MASK 0xf
1464#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1465
Jesse Barnes585fb112008-07-29 11:54:06 -07001466/*
1467 * Palette regs
1468 */
1469
Ville Syrjälä4b059982013-01-24 15:29:47 +02001470#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
1471#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001472#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
Jesse Barnes585fb112008-07-29 11:54:06 -07001473
Eric Anholt673a3942008-07-30 12:06:12 -07001474/* MCH MMIO space */
1475
1476/*
1477 * MCHBAR mirror.
1478 *
1479 * This mirrors the MCHBAR MMIO space whose location is determined by
1480 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1481 * every way. It is not accessible from the CP register read instructions.
1482 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03001483 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1484 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07001485 */
1486#define MCHBAR_MIRROR_BASE 0x10000
1487
Yuanhan Liu13982612010-12-15 15:42:31 +08001488#define MCHBAR_MIRROR_BASE_SNB 0x140000
1489
Chris Wilson3ebecd02013-04-12 19:10:13 +01001490/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ben Widawsky153b4b952013-10-22 22:05:09 -07001491#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01001492
Eric Anholt673a3942008-07-30 12:06:12 -07001493/** 915-945 and GM965 MCH register controlling DRAM channel access */
1494#define DCC 0x10200
1495#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1496#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1497#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1498#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1499#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08001500#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -07001501
Li Peng95534262010-05-18 18:58:44 +08001502/** Pineview MCH register contains DDR3 setting */
1503#define CSHRDDR3CTL 0x101a8
1504#define CSHRDDR3CTL_DDR3 (1 << 2)
1505
Eric Anholt673a3942008-07-30 12:06:12 -07001506/** 965 MCH register controlling DRAM channel configuration */
1507#define C0DRB3 0x10206
1508#define C1DRB3 0x10606
1509
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001510/** snb MCH registers for reading the DRAM channel configuration */
1511#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1512#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1513#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1514#define MAD_DIMM_ECC_MASK (0x3 << 24)
1515#define MAD_DIMM_ECC_OFF (0x0 << 24)
1516#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1517#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1518#define MAD_DIMM_ECC_ON (0x3 << 24)
1519#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1520#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1521#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1522#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1523#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1524#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1525#define MAD_DIMM_A_SELECT (0x1 << 16)
1526/* DIMM sizes are in multiples of 256mb. */
1527#define MAD_DIMM_B_SIZE_SHIFT 8
1528#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1529#define MAD_DIMM_A_SIZE_SHIFT 0
1530#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1531
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01001532/** snb MCH registers for priority tuning */
1533#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1534#define MCH_SSKPD_WM0_MASK 0x3f
1535#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001536
Jesse Barnesec013e72013-08-20 10:29:23 +01001537#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1538
Keith Packardb11248d2009-06-11 22:28:56 -07001539/* Clocking configuration register */
1540#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08001541#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07001542#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1543#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1544#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1545#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1546#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001547/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07001548#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001549#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07001550#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001551#define CLKCFG_MEM_533 (1 << 4)
1552#define CLKCFG_MEM_667 (2 << 4)
1553#define CLKCFG_MEM_800 (3 << 4)
1554#define CLKCFG_MEM_MASK (7 << 4)
1555
Jesse Barnesea056c12010-09-10 10:02:13 -07001556#define TSC1 0x11001
1557#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07001558#define TR1 0x11006
1559#define TSFS 0x11020
1560#define TSFS_SLOPE_MASK 0x0000ff00
1561#define TSFS_SLOPE_SHIFT 8
1562#define TSFS_INTR_MASK 0x000000ff
1563
Jesse Barnesf97108d2010-01-29 11:27:07 -08001564#define CRSTANDVID 0x11100
1565#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1566#define PXVFREQ_PX_MASK 0x7f000000
1567#define PXVFREQ_PX_SHIFT 24
1568#define VIDFREQ_BASE 0x11110
1569#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1570#define VIDFREQ2 0x11114
1571#define VIDFREQ3 0x11118
1572#define VIDFREQ4 0x1111c
1573#define VIDFREQ_P0_MASK 0x1f000000
1574#define VIDFREQ_P0_SHIFT 24
1575#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1576#define VIDFREQ_P0_CSCLK_SHIFT 20
1577#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1578#define VIDFREQ_P0_CRCLK_SHIFT 16
1579#define VIDFREQ_P1_MASK 0x00001f00
1580#define VIDFREQ_P1_SHIFT 8
1581#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1582#define VIDFREQ_P1_CSCLK_SHIFT 4
1583#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1584#define INTTOEXT_BASE_ILK 0x11300
1585#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1586#define INTTOEXT_MAP3_SHIFT 24
1587#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1588#define INTTOEXT_MAP2_SHIFT 16
1589#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1590#define INTTOEXT_MAP1_SHIFT 8
1591#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1592#define INTTOEXT_MAP0_SHIFT 0
1593#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1594#define MEMSWCTL 0x11170 /* Ironlake only */
1595#define MEMCTL_CMD_MASK 0xe000
1596#define MEMCTL_CMD_SHIFT 13
1597#define MEMCTL_CMD_RCLK_OFF 0
1598#define MEMCTL_CMD_RCLK_ON 1
1599#define MEMCTL_CMD_CHFREQ 2
1600#define MEMCTL_CMD_CHVID 3
1601#define MEMCTL_CMD_VMMOFF 4
1602#define MEMCTL_CMD_VMMON 5
1603#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1604 when command complete */
1605#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1606#define MEMCTL_FREQ_SHIFT 8
1607#define MEMCTL_SFCAVM (1<<7)
1608#define MEMCTL_TGT_VID_MASK 0x007f
1609#define MEMIHYST 0x1117c
1610#define MEMINTREN 0x11180 /* 16 bits */
1611#define MEMINT_RSEXIT_EN (1<<8)
1612#define MEMINT_CX_SUPR_EN (1<<7)
1613#define MEMINT_CONT_BUSY_EN (1<<6)
1614#define MEMINT_AVG_BUSY_EN (1<<5)
1615#define MEMINT_EVAL_CHG_EN (1<<4)
1616#define MEMINT_MON_IDLE_EN (1<<3)
1617#define MEMINT_UP_EVAL_EN (1<<2)
1618#define MEMINT_DOWN_EVAL_EN (1<<1)
1619#define MEMINT_SW_CMD_EN (1<<0)
1620#define MEMINTRSTR 0x11182 /* 16 bits */
1621#define MEM_RSEXIT_MASK 0xc000
1622#define MEM_RSEXIT_SHIFT 14
1623#define MEM_CONT_BUSY_MASK 0x3000
1624#define MEM_CONT_BUSY_SHIFT 12
1625#define MEM_AVG_BUSY_MASK 0x0c00
1626#define MEM_AVG_BUSY_SHIFT 10
1627#define MEM_EVAL_CHG_MASK 0x0300
1628#define MEM_EVAL_BUSY_SHIFT 8
1629#define MEM_MON_IDLE_MASK 0x00c0
1630#define MEM_MON_IDLE_SHIFT 6
1631#define MEM_UP_EVAL_MASK 0x0030
1632#define MEM_UP_EVAL_SHIFT 4
1633#define MEM_DOWN_EVAL_MASK 0x000c
1634#define MEM_DOWN_EVAL_SHIFT 2
1635#define MEM_SW_CMD_MASK 0x0003
1636#define MEM_INT_STEER_GFX 0
1637#define MEM_INT_STEER_CMR 1
1638#define MEM_INT_STEER_SMI 2
1639#define MEM_INT_STEER_SCI 3
1640#define MEMINTRSTS 0x11184
1641#define MEMINT_RSEXIT (1<<7)
1642#define MEMINT_CONT_BUSY (1<<6)
1643#define MEMINT_AVG_BUSY (1<<5)
1644#define MEMINT_EVAL_CHG (1<<4)
1645#define MEMINT_MON_IDLE (1<<3)
1646#define MEMINT_UP_EVAL (1<<2)
1647#define MEMINT_DOWN_EVAL (1<<1)
1648#define MEMINT_SW_CMD (1<<0)
1649#define MEMMODECTL 0x11190
1650#define MEMMODE_BOOST_EN (1<<31)
1651#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1652#define MEMMODE_BOOST_FREQ_SHIFT 24
1653#define MEMMODE_IDLE_MODE_MASK 0x00030000
1654#define MEMMODE_IDLE_MODE_SHIFT 16
1655#define MEMMODE_IDLE_MODE_EVAL 0
1656#define MEMMODE_IDLE_MODE_CONT 1
1657#define MEMMODE_HWIDLE_EN (1<<15)
1658#define MEMMODE_SWMODE_EN (1<<14)
1659#define MEMMODE_RCLK_GATE (1<<13)
1660#define MEMMODE_HW_UPDATE (1<<12)
1661#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1662#define MEMMODE_FSTART_SHIFT 8
1663#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1664#define MEMMODE_FMAX_SHIFT 4
1665#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1666#define RCBMAXAVG 0x1119c
1667#define MEMSWCTL2 0x1119e /* Cantiga only */
1668#define SWMEMCMD_RENDER_OFF (0 << 13)
1669#define SWMEMCMD_RENDER_ON (1 << 13)
1670#define SWMEMCMD_SWFREQ (2 << 13)
1671#define SWMEMCMD_TARVID (3 << 13)
1672#define SWMEMCMD_VRM_OFF (4 << 13)
1673#define SWMEMCMD_VRM_ON (5 << 13)
1674#define CMDSTS (1<<12)
1675#define SFCAVM (1<<11)
1676#define SWFREQ_MASK 0x0380 /* P0-7 */
1677#define SWFREQ_SHIFT 7
1678#define TARVID_MASK 0x001f
1679#define MEMSTAT_CTG 0x111a0
1680#define RCBMINAVG 0x111a0
1681#define RCUPEI 0x111b0
1682#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08001683#define RSTDBYCTL 0x111b8
1684#define RS1EN (1<<31)
1685#define RS2EN (1<<30)
1686#define RS3EN (1<<29)
1687#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1688#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1689#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1690#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1691#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1692#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1693#define RSX_STATUS_MASK (7<<20)
1694#define RSX_STATUS_ON (0<<20)
1695#define RSX_STATUS_RC1 (1<<20)
1696#define RSX_STATUS_RC1E (2<<20)
1697#define RSX_STATUS_RS1 (3<<20)
1698#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1699#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1700#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1701#define RSX_STATUS_RSVD2 (7<<20)
1702#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1703#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1704#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1705#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1706#define RS1CONTSAV_MASK (3<<14)
1707#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1708#define RS1CONTSAV_RSVD (1<<14)
1709#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1710#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1711#define NORMSLEXLAT_MASK (3<<12)
1712#define SLOW_RS123 (0<<12)
1713#define SLOW_RS23 (1<<12)
1714#define SLOW_RS3 (2<<12)
1715#define NORMAL_RS123 (3<<12)
1716#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1717#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1718#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1719#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1720#define RS_CSTATE_MASK (3<<4)
1721#define RS_CSTATE_C367_RS1 (0<<4)
1722#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1723#define RS_CSTATE_RSVD (2<<4)
1724#define RS_CSTATE_C367_RS2 (3<<4)
1725#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1726#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08001727#define VIDCTL 0x111c0
1728#define VIDSTS 0x111c8
1729#define VIDSTART 0x111cc /* 8 bits */
1730#define MEMSTAT_ILK 0x111f8
1731#define MEMSTAT_VID_MASK 0x7f00
1732#define MEMSTAT_VID_SHIFT 8
1733#define MEMSTAT_PSTATE_MASK 0x00f8
1734#define MEMSTAT_PSTATE_SHIFT 3
1735#define MEMSTAT_MON_ACTV (1<<2)
1736#define MEMSTAT_SRC_CTL_MASK 0x0003
1737#define MEMSTAT_SRC_CTL_CORE 0
1738#define MEMSTAT_SRC_CTL_TRB 1
1739#define MEMSTAT_SRC_CTL_THM 2
1740#define MEMSTAT_SRC_CTL_STDBY 3
1741#define RCPREVBSYTUPAVG 0x113b8
1742#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07001743#define PMMISC 0x11214
1744#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07001745#define SDEW 0x1124c
1746#define CSIEW0 0x11250
1747#define CSIEW1 0x11254
1748#define CSIEW2 0x11258
1749#define PEW 0x1125c
1750#define DEW 0x11270
1751#define MCHAFE 0x112c0
1752#define CSIEC 0x112e0
1753#define DMIEC 0x112e4
1754#define DDREC 0x112e8
1755#define PEG0EC 0x112ec
1756#define PEG1EC 0x112f0
1757#define GFXEC 0x112f4
1758#define RPPREVBSYTUPAVG 0x113b8
1759#define RPPREVBSYTDNAVG 0x113bc
1760#define ECR 0x11600
1761#define ECR_GPFE (1<<31)
1762#define ECR_IMONE (1<<30)
1763#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1764#define OGW0 0x11608
1765#define OGW1 0x1160c
1766#define EG0 0x11610
1767#define EG1 0x11614
1768#define EG2 0x11618
1769#define EG3 0x1161c
1770#define EG4 0x11620
1771#define EG5 0x11624
1772#define EG6 0x11628
1773#define EG7 0x1162c
1774#define PXW 0x11664
1775#define PXWL 0x11680
1776#define LCFUSE02 0x116c0
1777#define LCFUSE_HIV_MASK 0x000000ff
1778#define CSIPLL0 0x12c10
1779#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08001780#define PEG_BAND_GAP_DATA 0x14d68
1781
Chris Wilsonc4de7b02012-07-02 11:51:03 -03001782#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1783#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1784#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1785
Ben Widawsky153b4b952013-10-22 22:05:09 -07001786#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
1787#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
1788#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001789
Jesse Barnes585fb112008-07-29 11:54:06 -07001790/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08001791 * Logical Context regs
1792 */
1793#define CCID 0x2180
1794#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03001795/*
1796 * Notes on SNB/IVB/VLV context size:
1797 * - Power context is saved elsewhere (LLC or stolen)
1798 * - Ring/execlist context is saved on SNB, not on IVB
1799 * - Extended context size already includes render context size
1800 * - We always need to follow the extended context size.
1801 * SNB BSpec has comments indicating that we should use the
1802 * render context size instead if execlists are disabled, but
1803 * based on empirical testing that's just nonsense.
1804 * - Pipelined/VF state is saved on SNB/IVB respectively
1805 * - GT1 size just indicates how much of render context
1806 * doesn't need saving on GT1
1807 */
Ben Widawskyfe1cc682012-06-04 14:42:41 -07001808#define CXT_SIZE 0x21a0
1809#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1810#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1811#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1812#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1813#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03001814#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07001815 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1816 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ben Widawsky4f91dd62012-07-18 10:10:09 -07001817#define GEN7_CXT_SIZE 0x21a8
Ben Widawsky6a4ea1242012-07-18 10:10:10 -07001818#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1819#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
Ben Widawsky4f91dd62012-07-18 10:10:09 -07001820#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1821#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1822#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1823#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03001824#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07001825 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07001826/* Haswell does have the CXT_SIZE register however it does not appear to be
1827 * valid. Now, docs explain in dwords what is in the context object. The full
1828 * size is 70720 bytes, however, the power context and execlist context will
1829 * never be saved (power context is stored elsewhere, and execlists don't work
1830 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1831 */
1832#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawskyfe1cc682012-06-04 14:42:41 -07001833
Jesse Barnese454a052013-09-26 17:55:58 -07001834#define VLV_CLK_CTL2 0x101104
1835#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1836
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08001837/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001838 * Overlay regs
1839 */
1840
1841#define OVADD 0x30000
1842#define DOVSTA 0x30008
1843#define OC_BUF (0x3<<20)
1844#define OGAMC5 0x30010
1845#define OGAMC4 0x30014
1846#define OGAMC3 0x30018
1847#define OGAMC2 0x3001c
1848#define OGAMC1 0x30020
1849#define OGAMC0 0x30024
1850
1851/*
1852 * Display engine regs
1853 */
1854
Shuang He8bf1e9f2013-10-15 18:55:27 +01001855/* Pipe A CRC regs */
1856#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050)
1857#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02001858/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01001859#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
1860#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
1861#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02001862/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02001863#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
1864#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
1865#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
1866/* embedded DP port on the north display block, reserved on ivb */
1867#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
1868#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02001869/* vlv source selection */
1870#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
1871#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
1872#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
1873/* with DP port the pipe source is invalid */
1874#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
1875#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
1876#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
1877/* gen3+ source selection */
1878#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
1879#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
1880#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
1881/* with DP/TV port the pipe source is invalid */
1882#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
1883#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
1884#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
1885#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
1886#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
1887/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02001888#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02001889
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02001890#define _PIPE_CRC_RES_1_A_IVB 0x60064
1891#define _PIPE_CRC_RES_2_A_IVB 0x60068
1892#define _PIPE_CRC_RES_3_A_IVB 0x6006c
1893#define _PIPE_CRC_RES_4_A_IVB 0x60070
1894#define _PIPE_CRC_RES_5_A_IVB 0x60074
1895
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001896#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060)
1897#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064)
1898#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068)
1899#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c)
1900#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001901
1902/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02001903#define _PIPE_CRC_RES_1_B_IVB 0x61064
1904#define _PIPE_CRC_RES_2_B_IVB 0x61068
1905#define _PIPE_CRC_RES_3_B_IVB 0x6106c
1906#define _PIPE_CRC_RES_4_B_IVB 0x61070
1907#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01001908
Daniel Vetterb073aea2013-10-16 22:55:57 +02001909#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001910#define PIPE_CRC_RES_1_IVB(pipe) \
1911 _PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
1912#define PIPE_CRC_RES_2_IVB(pipe) \
1913 _PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
1914#define PIPE_CRC_RES_3_IVB(pipe) \
1915 _PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
1916#define PIPE_CRC_RES_4_IVB(pipe) \
1917 _PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
1918#define PIPE_CRC_RES_5_IVB(pipe) \
1919 _PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
1920
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001921#define PIPE_CRC_RES_RED(pipe) \
1922 _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000)
1923#define PIPE_CRC_RES_GREEN(pipe) \
1924 _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000)
1925#define PIPE_CRC_RES_BLUE(pipe) \
1926 _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000)
1927#define PIPE_CRC_RES_RES1_I915(pipe) \
1928 _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000)
1929#define PIPE_CRC_RES_RES2_G4X(pipe) \
1930 _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02001931
Jesse Barnes585fb112008-07-29 11:54:06 -07001932/* Pipe A timing regs */
Ville Syrjälä4e8e7eb2013-01-24 15:29:46 +02001933#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
1934#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
1935#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
1936#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
1937#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
1938#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
1939#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
1940#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
1941#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
Jesse Barnes585fb112008-07-29 11:54:06 -07001942
1943/* Pipe B timing regs */
Ville Syrjälä4e8e7eb2013-01-24 15:29:46 +02001944#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
1945#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
1946#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
1947#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
1948#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
1949#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
1950#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
1951#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
1952#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
Daniel Vetter0529a0d2012-01-28 14:49:24 +01001953
Paulo Zanonife2b8f92012-10-23 18:30:02 -02001954#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1955#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1956#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1957#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1958#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1959#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001960#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02001961#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01001962
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001963/* HSW eDP PSR registers */
Ben Widawsky18b59922013-09-20 09:35:30 -07001964#define EDP_PSR_BASE(dev) 0x64800
1965#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001966#define EDP_PSR_ENABLE (1<<31)
1967#define EDP_PSR_LINK_DISABLE (0<<27)
1968#define EDP_PSR_LINK_STANDBY (1<<27)
1969#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
1970#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
1971#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
1972#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
1973#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
1974#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
1975#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
1976#define EDP_PSR_TP1_TP2_SEL (0<<11)
1977#define EDP_PSR_TP1_TP3_SEL (1<<11)
1978#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
1979#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
1980#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
1981#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
1982#define EDP_PSR_TP1_TIME_500us (0<<4)
1983#define EDP_PSR_TP1_TIME_100us (1<<4)
1984#define EDP_PSR_TP1_TIME_2500us (2<<4)
1985#define EDP_PSR_TP1_TIME_0us (3<<4)
1986#define EDP_PSR_IDLE_FRAME_SHIFT 0
1987
Ben Widawsky18b59922013-09-20 09:35:30 -07001988#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
1989#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001990#define EDP_PSR_DPCD_COMMAND 0x80060000
Ben Widawsky18b59922013-09-20 09:35:30 -07001991#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001992#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
Ben Widawsky18b59922013-09-20 09:35:30 -07001993#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
1994#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
1995#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001996
Ben Widawsky18b59922013-09-20 09:35:30 -07001997#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001998#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001999#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2000#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2001#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2002#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2003#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2004#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2005#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2006#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2007#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2008#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2009#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2010#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2011#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2012#define EDP_PSR_STATUS_COUNT_SHIFT 16
2013#define EDP_PSR_STATUS_COUNT_MASK 0xf
2014#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2015#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2016#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2017#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2018#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2019#define EDP_PSR_STATUS_IDLE_MASK 0xf
2020
Ben Widawsky18b59922013-09-20 09:35:30 -07002021#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002022#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002023
Ben Widawsky18b59922013-09-20 09:35:30 -07002024#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002025#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2026#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2027#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2028
Jesse Barnes585fb112008-07-29 11:54:06 -07002029/* VGA port control */
2030#define ADPA 0x61100
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002031#define PCH_ADPA 0xe1100
Daniel Vetter540a8952012-07-11 16:27:57 +02002032#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002033
Jesse Barnes585fb112008-07-29 11:54:06 -07002034#define ADPA_DAC_ENABLE (1<<31)
2035#define ADPA_DAC_DISABLE 0
2036#define ADPA_PIPE_SELECT_MASK (1<<30)
2037#define ADPA_PIPE_A_SELECT 0
2038#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07002039#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002040/* CPT uses bits 29:30 for pch transcoder select */
2041#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2042#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2043#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2044#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2045#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2046#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2047#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2048#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2049#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2050#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2051#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2052#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2053#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2054#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2055#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2056#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2057#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2058#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2059#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07002060#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2061#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002062#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07002063#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002064#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07002065#define ADPA_HSYNC_CNTL_ENABLE 0
2066#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2067#define ADPA_VSYNC_ACTIVE_LOW 0
2068#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2069#define ADPA_HSYNC_ACTIVE_LOW 0
2070#define ADPA_DPMS_MASK (~(3<<10))
2071#define ADPA_DPMS_ON (0<<10)
2072#define ADPA_DPMS_SUSPEND (1<<10)
2073#define ADPA_DPMS_STANDBY (2<<10)
2074#define ADPA_DPMS_OFF (3<<10)
2075
Chris Wilson939fe4d2010-10-09 10:33:26 +01002076
Jesse Barnes585fb112008-07-29 11:54:06 -07002077/* Hotplug control (945+ only) */
Ville Syrjälä67d62c52013-01-24 15:29:44 +02002078#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01002079#define PORTB_HOTPLUG_INT_EN (1 << 29)
2080#define PORTC_HOTPLUG_INT_EN (1 << 28)
2081#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07002082#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2083#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2084#define TV_HOTPLUG_INT_EN (1 << 18)
2085#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05002086#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2087 PORTC_HOTPLUG_INT_EN | \
2088 PORTD_HOTPLUG_INT_EN | \
2089 SDVOC_HOTPLUG_INT_EN | \
2090 SDVOB_HOTPLUG_INT_EN | \
2091 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07002092#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08002093#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2094/* must use period 64 on GM45 according to docs */
2095#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2096#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2097#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2098#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2099#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2100#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2101#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2102#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2103#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2104#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2105#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2106#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002107
Ville Syrjälä67d62c52013-01-24 15:29:44 +02002108#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02002109/*
2110 * HDMI/DP bits are gen4+
2111 *
2112 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2113 * Please check the detailed lore in the commit message for for experimental
2114 * evidence.
2115 */
2116#define PORTD_HOTPLUG_LIVE_STATUS (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01002117#define PORTC_HOTPLUG_LIVE_STATUS (1 << 28)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02002118#define PORTB_HOTPLUG_LIVE_STATUS (1 << 27)
Daniel Vetter26739f12013-02-07 12:42:32 +01002119#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2120#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2121#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01002122/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07002123#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2124#define TV_HOTPLUG_INT_STATUS (1 << 10)
2125#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2126#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2127#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2128#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Chris Wilson084b6122012-05-11 18:01:33 +01002129/* SDVO is different across gen3/4 */
2130#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2131#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02002132/*
2133 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2134 * since reality corrobates that they're the same as on gen3. But keep these
2135 * bits here (and the comment!) to help any other lost wanderers back onto the
2136 * right tracks.
2137 */
Chris Wilson084b6122012-05-11 18:01:33 +01002138#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2139#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2140#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2141#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05002142#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2143 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2144 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2145 PORTB_HOTPLUG_INT_STATUS | \
2146 PORTC_HOTPLUG_INT_STATUS | \
2147 PORTD_HOTPLUG_INT_STATUS)
2148
Egbert Eiche5868a32013-02-28 04:17:12 -05002149#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2150 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2151 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2152 PORTB_HOTPLUG_INT_STATUS | \
2153 PORTC_HOTPLUG_INT_STATUS | \
2154 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07002155
Paulo Zanonic20cd312013-02-19 16:21:45 -03002156/* SDVO and HDMI port control.
2157 * The same register may be used for SDVO or HDMI */
2158#define GEN3_SDVOB 0x61140
2159#define GEN3_SDVOC 0x61160
2160#define GEN4_HDMIB GEN3_SDVOB
2161#define GEN4_HDMIC GEN3_SDVOC
2162#define PCH_SDVOB 0xe1140
2163#define PCH_HDMIB PCH_SDVOB
2164#define PCH_HDMIC 0xe1150
2165#define PCH_HDMID 0xe1160
2166
Daniel Vetter84093602013-11-01 10:50:21 +01002167#define PORT_DFT_I9XX 0x61150
2168#define DC_BALANCE_RESET (1 << 25)
2169#define PORT_DFT2_G4X 0x61154
2170#define DC_BALANCE_RESET_VLV (1 << 31)
2171#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2172#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2173#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2174
Paulo Zanonic20cd312013-02-19 16:21:45 -03002175/* Gen 3 SDVO bits: */
2176#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002177#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2178#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002179#define SDVO_PIPE_B_SELECT (1 << 30)
2180#define SDVO_STALL_SELECT (1 << 29)
2181#define SDVO_INTERRUPT_ENABLE (1 << 26)
Jesse Barnes585fb112008-07-29 11:54:06 -07002182/**
2183 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07002184 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07002185 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2186 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002187#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07002188#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03002189#define SDVO_PHASE_SELECT_MASK (15 << 19)
2190#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2191#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2192#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2193#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2194#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2195#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002196/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002197#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2198 SDVO_INTERRUPT_ENABLE)
2199#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2200
2201/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002202#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03002203#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002204#define SDVO_ENCODING_SDVO (0 << 10)
2205#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002206#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2207#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002208#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002209#define SDVO_AUDIO_ENABLE (1 << 6)
2210/* VSYNC/HSYNC bits new with 965, default is to be set */
2211#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2212#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2213
2214/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002215#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002216#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2217
2218/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002219#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2220#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002221
Jesse Barnes585fb112008-07-29 11:54:06 -07002222
2223/* DVO port control */
2224#define DVOA 0x61120
2225#define DVOB 0x61140
2226#define DVOC 0x61160
2227#define DVO_ENABLE (1 << 31)
2228#define DVO_PIPE_B_SELECT (1 << 30)
2229#define DVO_PIPE_STALL_UNUSED (0 << 28)
2230#define DVO_PIPE_STALL (1 << 28)
2231#define DVO_PIPE_STALL_TV (2 << 28)
2232#define DVO_PIPE_STALL_MASK (3 << 28)
2233#define DVO_USE_VGA_SYNC (1 << 15)
2234#define DVO_DATA_ORDER_I740 (0 << 14)
2235#define DVO_DATA_ORDER_FP (1 << 14)
2236#define DVO_VSYNC_DISABLE (1 << 11)
2237#define DVO_HSYNC_DISABLE (1 << 10)
2238#define DVO_VSYNC_TRISTATE (1 << 9)
2239#define DVO_HSYNC_TRISTATE (1 << 8)
2240#define DVO_BORDER_ENABLE (1 << 7)
2241#define DVO_DATA_ORDER_GBRG (1 << 6)
2242#define DVO_DATA_ORDER_RGGB (0 << 6)
2243#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2244#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2245#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2246#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2247#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2248#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2249#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2250#define DVO_PRESERVE_MASK (0x7<<24)
2251#define DVOA_SRCDIM 0x61124
2252#define DVOB_SRCDIM 0x61144
2253#define DVOC_SRCDIM 0x61164
2254#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2255#define DVO_SRCDIM_VERTICAL_SHIFT 0
2256
2257/* LVDS port control */
2258#define LVDS 0x61180
2259/*
2260 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2261 * the DPLL semantics change when the LVDS is assigned to that pipe.
2262 */
2263#define LVDS_PORT_EN (1 << 31)
2264/* Selects pipe B for LVDS data. Must be set on pre-965. */
2265#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002266#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07002267#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08002268/* LVDS dithering flag on 965/g4x platform */
2269#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08002270/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2271#define LVDS_VSYNC_POLARITY (1 << 21)
2272#define LVDS_HSYNC_POLARITY (1 << 20)
2273
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08002274/* Enable border for unscaled (or aspect-scaled) display */
2275#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07002276/*
2277 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2278 * pixel.
2279 */
2280#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2281#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2282#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2283/*
2284 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2285 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2286 * on.
2287 */
2288#define LVDS_A3_POWER_MASK (3 << 6)
2289#define LVDS_A3_POWER_DOWN (0 << 6)
2290#define LVDS_A3_POWER_UP (3 << 6)
2291/*
2292 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2293 * is set.
2294 */
2295#define LVDS_CLKB_POWER_MASK (3 << 4)
2296#define LVDS_CLKB_POWER_DOWN (0 << 4)
2297#define LVDS_CLKB_POWER_UP (3 << 4)
2298/*
2299 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2300 * setting for whether we are in dual-channel mode. The B3 pair will
2301 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2302 */
2303#define LVDS_B0B3_POWER_MASK (3 << 2)
2304#define LVDS_B0B3_POWER_DOWN (0 << 2)
2305#define LVDS_B0B3_POWER_UP (3 << 2)
2306
David Härdeman3c17fe42010-09-24 21:44:32 +02002307/* Video Data Island Packet control */
2308#define VIDEO_DIP_DATA 0x61178
Paulo Zanoniadf00b22012-09-25 13:23:34 -03002309/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2310 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2311 * of the infoframe structure specified by CEA-861. */
2312#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002313#define VIDEO_DIP_VSC_DATA_SIZE 36
David Härdeman3c17fe42010-09-24 21:44:32 +02002314#define VIDEO_DIP_CTL 0x61170
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002315/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02002316#define VIDEO_DIP_ENABLE (1 << 31)
2317#define VIDEO_DIP_PORT_B (1 << 29)
2318#define VIDEO_DIP_PORT_C (2 << 29)
Paulo Zanoni4e89ee12012-05-04 17:18:26 -03002319#define VIDEO_DIP_PORT_D (3 << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03002320#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002321#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02002322#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2323#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002324#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02002325#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2326#define VIDEO_DIP_SELECT_AVI (0 << 19)
2327#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2328#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07002329#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02002330#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2331#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2332#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03002333#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002334/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002335#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2336#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002337#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002338#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2339#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002340#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02002341
Jesse Barnes585fb112008-07-29 11:54:06 -07002342/* Panel power sequencing */
2343#define PP_STATUS 0x61200
2344#define PP_ON (1 << 31)
2345/*
2346 * Indicates that all dependencies of the panel are on:
2347 *
2348 * - PLL enabled
2349 * - pipe enabled
2350 * - LVDS/DVOB/DVOC on
2351 */
2352#define PP_READY (1 << 30)
2353#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07002354#define PP_SEQUENCE_POWER_UP (1 << 28)
2355#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2356#define PP_SEQUENCE_MASK (3 << 28)
2357#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002358#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002359#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07002360#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2361#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2362#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2363#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2364#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2365#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2366#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2367#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2368#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07002369#define PP_CONTROL 0x61204
2370#define POWER_TARGET_ON (1 << 0)
2371#define PP_ON_DELAYS 0x61208
2372#define PP_OFF_DELAYS 0x6120c
2373#define PP_DIVISOR 0x61210
2374
2375/* Panel fitting */
Ville Syrjälä7e470ab2013-01-24 15:29:43 +02002376#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07002377#define PFIT_ENABLE (1 << 31)
2378#define PFIT_PIPE_MASK (3 << 29)
2379#define PFIT_PIPE_SHIFT 29
2380#define VERT_INTERP_DISABLE (0 << 10)
2381#define VERT_INTERP_BILINEAR (1 << 10)
2382#define VERT_INTERP_MASK (3 << 10)
2383#define VERT_AUTO_SCALE (1 << 9)
2384#define HORIZ_INTERP_DISABLE (0 << 6)
2385#define HORIZ_INTERP_BILINEAR (1 << 6)
2386#define HORIZ_INTERP_MASK (3 << 6)
2387#define HORIZ_AUTO_SCALE (1 << 5)
2388#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002389#define PFIT_FILTER_FUZZY (0 << 24)
2390#define PFIT_SCALING_AUTO (0 << 26)
2391#define PFIT_SCALING_PROGRAMMED (1 << 26)
2392#define PFIT_SCALING_PILLAR (2 << 26)
2393#define PFIT_SCALING_LETTER (3 << 26)
Ville Syrjälä7e470ab2013-01-24 15:29:43 +02002394#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002395/* Pre-965 */
2396#define PFIT_VERT_SCALE_SHIFT 20
2397#define PFIT_VERT_SCALE_MASK 0xfff00000
2398#define PFIT_HORIZ_SCALE_SHIFT 4
2399#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2400/* 965+ */
2401#define PFIT_VERT_SCALE_SHIFT_965 16
2402#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2403#define PFIT_HORIZ_SCALE_SHIFT_965 0
2404#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2405
Ville Syrjälä7e470ab2013-01-24 15:29:43 +02002406#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07002407
2408/* Backlight control */
Jesse Barnes12569ad2013-03-08 10:45:59 -08002409#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002410#define BLM_PWM_ENABLE (1 << 31)
2411#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2412#define BLM_PIPE_SELECT (1 << 29)
2413#define BLM_PIPE_SELECT_IVB (3 << 29)
2414#define BLM_PIPE_A (0 << 29)
2415#define BLM_PIPE_B (1 << 29)
2416#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03002417#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2418#define BLM_TRANSCODER_B BLM_PIPE_B
2419#define BLM_TRANSCODER_C BLM_PIPE_C
2420#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02002421#define BLM_PIPE(pipe) ((pipe) << 29)
2422#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2423#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2424#define BLM_PHASE_IN_ENABLE (1 << 25)
2425#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2426#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2427#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2428#define BLM_PHASE_IN_COUNT_SHIFT (8)
2429#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2430#define BLM_PHASE_IN_INCR_SHIFT (0)
2431#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Jesse Barnes12569ad2013-03-08 10:45:59 -08002432#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01002433/*
2434 * This is the most significant 15 bits of the number of backlight cycles in a
2435 * complete cycle of the modulated backlight control.
2436 *
2437 * The actual value is this field multiplied by two.
2438 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002439#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2440#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2441#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002442/*
2443 * This is the number of cycles out of the backlight modulation cycle for which
2444 * the backlight is on.
2445 *
2446 * This field must be no greater than the number of cycles in the complete
2447 * backlight modulation cycle.
2448 */
2449#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2450#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02002451#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2452#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002453
Jesse Barnes12569ad2013-03-08 10:45:59 -08002454#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07002455
Daniel Vetter7cf41602012-06-05 10:07:09 +02002456/* New registers for PCH-split platforms. Safe where new bits show up, the
2457 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2458#define BLC_PWM_CPU_CTL2 0x48250
2459#define BLC_PWM_CPU_CTL 0x48254
2460
Paulo Zanonibe256dc2013-07-23 11:19:26 -03002461#define HSW_BLC_PWM2_CTL 0x48350
2462
Daniel Vetter7cf41602012-06-05 10:07:09 +02002463/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2464 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2465#define BLC_PWM_PCH_CTL1 0xc8250
Daniel Vetter4b4147c2012-07-11 00:31:06 +02002466#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02002467#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2468#define BLM_PCH_POLARITY (1 << 29)
2469#define BLC_PWM_PCH_CTL2 0xc8254
2470
Paulo Zanonibe256dc2013-07-23 11:19:26 -03002471#define UTIL_PIN_CTL 0x48400
2472#define UTIL_PIN_ENABLE (1 << 31)
2473
2474#define PCH_GTC_CTL 0xe7000
2475#define PCH_GTC_ENABLE (1 << 31)
2476
Jesse Barnes585fb112008-07-29 11:54:06 -07002477/* TV port control */
2478#define TV_CTL 0x68000
2479/** Enables the TV encoder */
2480# define TV_ENC_ENABLE (1 << 31)
2481/** Sources the TV encoder input from pipe B instead of A. */
2482# define TV_ENC_PIPEB_SELECT (1 << 30)
2483/** Outputs composite video (DAC A only) */
2484# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2485/** Outputs SVideo video (DAC B/C) */
2486# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2487/** Outputs Component video (DAC A/B/C) */
2488# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2489/** Outputs Composite and SVideo (DAC A/B/C) */
2490# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2491# define TV_TRILEVEL_SYNC (1 << 21)
2492/** Enables slow sync generation (945GM only) */
2493# define TV_SLOW_SYNC (1 << 20)
2494/** Selects 4x oversampling for 480i and 576p */
2495# define TV_OVERSAMPLE_4X (0 << 18)
2496/** Selects 2x oversampling for 720p and 1080i */
2497# define TV_OVERSAMPLE_2X (1 << 18)
2498/** Selects no oversampling for 1080p */
2499# define TV_OVERSAMPLE_NONE (2 << 18)
2500/** Selects 8x oversampling */
2501# define TV_OVERSAMPLE_8X (3 << 18)
2502/** Selects progressive mode rather than interlaced */
2503# define TV_PROGRESSIVE (1 << 17)
2504/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2505# define TV_PAL_BURST (1 << 16)
2506/** Field for setting delay of Y compared to C */
2507# define TV_YC_SKEW_MASK (7 << 12)
2508/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2509# define TV_ENC_SDP_FIX (1 << 11)
2510/**
2511 * Enables a fix for the 915GM only.
2512 *
2513 * Not sure what it does.
2514 */
2515# define TV_ENC_C0_FIX (1 << 10)
2516/** Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08002517# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07002518# define TV_FUSE_STATE_MASK (3 << 4)
2519/** Read-only state that reports all features enabled */
2520# define TV_FUSE_STATE_ENABLED (0 << 4)
2521/** Read-only state that reports that Macrovision is disabled in hardware*/
2522# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2523/** Read-only state that reports that TV-out is disabled in hardware. */
2524# define TV_FUSE_STATE_DISABLED (2 << 4)
2525/** Normal operation */
2526# define TV_TEST_MODE_NORMAL (0 << 0)
2527/** Encoder test pattern 1 - combo pattern */
2528# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2529/** Encoder test pattern 2 - full screen vertical 75% color bars */
2530# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2531/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2532# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2533/** Encoder test pattern 4 - random noise */
2534# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2535/** Encoder test pattern 5 - linear color ramps */
2536# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2537/**
2538 * This test mode forces the DACs to 50% of full output.
2539 *
2540 * This is used for load detection in combination with TVDAC_SENSE_MASK
2541 */
2542# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2543# define TV_TEST_MODE_MASK (7 << 0)
2544
2545#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01002546# define TV_DAC_SAVE 0x00ffff00
Jesse Barnes585fb112008-07-29 11:54:06 -07002547/**
2548 * Reports that DAC state change logic has reported change (RO).
2549 *
2550 * This gets cleared when TV_DAC_STATE_EN is cleared
2551*/
2552# define TVDAC_STATE_CHG (1 << 31)
2553# define TVDAC_SENSE_MASK (7 << 28)
2554/** Reports that DAC A voltage is above the detect threshold */
2555# define TVDAC_A_SENSE (1 << 30)
2556/** Reports that DAC B voltage is above the detect threshold */
2557# define TVDAC_B_SENSE (1 << 29)
2558/** Reports that DAC C voltage is above the detect threshold */
2559# define TVDAC_C_SENSE (1 << 28)
2560/**
2561 * Enables DAC state detection logic, for load-based TV detection.
2562 *
2563 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2564 * to off, for load detection to work.
2565 */
2566# define TVDAC_STATE_CHG_EN (1 << 27)
2567/** Sets the DAC A sense value to high */
2568# define TVDAC_A_SENSE_CTL (1 << 26)
2569/** Sets the DAC B sense value to high */
2570# define TVDAC_B_SENSE_CTL (1 << 25)
2571/** Sets the DAC C sense value to high */
2572# define TVDAC_C_SENSE_CTL (1 << 24)
2573/** Overrides the ENC_ENABLE and DAC voltage levels */
2574# define DAC_CTL_OVERRIDE (1 << 7)
2575/** Sets the slew rate. Must be preserved in software */
2576# define ENC_TVDAC_SLEW_FAST (1 << 6)
2577# define DAC_A_1_3_V (0 << 4)
2578# define DAC_A_1_1_V (1 << 4)
2579# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08002580# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002581# define DAC_B_1_3_V (0 << 2)
2582# define DAC_B_1_1_V (1 << 2)
2583# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08002584# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002585# define DAC_C_1_3_V (0 << 0)
2586# define DAC_C_1_1_V (1 << 0)
2587# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08002588# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07002589
2590/**
2591 * CSC coefficients are stored in a floating point format with 9 bits of
2592 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2593 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2594 * -1 (0x3) being the only legal negative value.
2595 */
2596#define TV_CSC_Y 0x68010
2597# define TV_RY_MASK 0x07ff0000
2598# define TV_RY_SHIFT 16
2599# define TV_GY_MASK 0x00000fff
2600# define TV_GY_SHIFT 0
2601
2602#define TV_CSC_Y2 0x68014
2603# define TV_BY_MASK 0x07ff0000
2604# define TV_BY_SHIFT 16
2605/**
2606 * Y attenuation for component video.
2607 *
2608 * Stored in 1.9 fixed point.
2609 */
2610# define TV_AY_MASK 0x000003ff
2611# define TV_AY_SHIFT 0
2612
2613#define TV_CSC_U 0x68018
2614# define TV_RU_MASK 0x07ff0000
2615# define TV_RU_SHIFT 16
2616# define TV_GU_MASK 0x000007ff
2617# define TV_GU_SHIFT 0
2618
2619#define TV_CSC_U2 0x6801c
2620# define TV_BU_MASK 0x07ff0000
2621# define TV_BU_SHIFT 16
2622/**
2623 * U attenuation for component video.
2624 *
2625 * Stored in 1.9 fixed point.
2626 */
2627# define TV_AU_MASK 0x000003ff
2628# define TV_AU_SHIFT 0
2629
2630#define TV_CSC_V 0x68020
2631# define TV_RV_MASK 0x0fff0000
2632# define TV_RV_SHIFT 16
2633# define TV_GV_MASK 0x000007ff
2634# define TV_GV_SHIFT 0
2635
2636#define TV_CSC_V2 0x68024
2637# define TV_BV_MASK 0x07ff0000
2638# define TV_BV_SHIFT 16
2639/**
2640 * V attenuation for component video.
2641 *
2642 * Stored in 1.9 fixed point.
2643 */
2644# define TV_AV_MASK 0x000007ff
2645# define TV_AV_SHIFT 0
2646
2647#define TV_CLR_KNOBS 0x68028
2648/** 2s-complement brightness adjustment */
2649# define TV_BRIGHTNESS_MASK 0xff000000
2650# define TV_BRIGHTNESS_SHIFT 24
2651/** Contrast adjustment, as a 2.6 unsigned floating point number */
2652# define TV_CONTRAST_MASK 0x00ff0000
2653# define TV_CONTRAST_SHIFT 16
2654/** Saturation adjustment, as a 2.6 unsigned floating point number */
2655# define TV_SATURATION_MASK 0x0000ff00
2656# define TV_SATURATION_SHIFT 8
2657/** Hue adjustment, as an integer phase angle in degrees */
2658# define TV_HUE_MASK 0x000000ff
2659# define TV_HUE_SHIFT 0
2660
2661#define TV_CLR_LEVEL 0x6802c
2662/** Controls the DAC level for black */
2663# define TV_BLACK_LEVEL_MASK 0x01ff0000
2664# define TV_BLACK_LEVEL_SHIFT 16
2665/** Controls the DAC level for blanking */
2666# define TV_BLANK_LEVEL_MASK 0x000001ff
2667# define TV_BLANK_LEVEL_SHIFT 0
2668
2669#define TV_H_CTL_1 0x68030
2670/** Number of pixels in the hsync. */
2671# define TV_HSYNC_END_MASK 0x1fff0000
2672# define TV_HSYNC_END_SHIFT 16
2673/** Total number of pixels minus one in the line (display and blanking). */
2674# define TV_HTOTAL_MASK 0x00001fff
2675# define TV_HTOTAL_SHIFT 0
2676
2677#define TV_H_CTL_2 0x68034
2678/** Enables the colorburst (needed for non-component color) */
2679# define TV_BURST_ENA (1 << 31)
2680/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2681# define TV_HBURST_START_SHIFT 16
2682# define TV_HBURST_START_MASK 0x1fff0000
2683/** Length of the colorburst */
2684# define TV_HBURST_LEN_SHIFT 0
2685# define TV_HBURST_LEN_MASK 0x0001fff
2686
2687#define TV_H_CTL_3 0x68038
2688/** End of hblank, measured in pixels minus one from start of hsync */
2689# define TV_HBLANK_END_SHIFT 16
2690# define TV_HBLANK_END_MASK 0x1fff0000
2691/** Start of hblank, measured in pixels minus one from start of hsync */
2692# define TV_HBLANK_START_SHIFT 0
2693# define TV_HBLANK_START_MASK 0x0001fff
2694
2695#define TV_V_CTL_1 0x6803c
2696/** XXX */
2697# define TV_NBR_END_SHIFT 16
2698# define TV_NBR_END_MASK 0x07ff0000
2699/** XXX */
2700# define TV_VI_END_F1_SHIFT 8
2701# define TV_VI_END_F1_MASK 0x00003f00
2702/** XXX */
2703# define TV_VI_END_F2_SHIFT 0
2704# define TV_VI_END_F2_MASK 0x0000003f
2705
2706#define TV_V_CTL_2 0x68040
2707/** Length of vsync, in half lines */
2708# define TV_VSYNC_LEN_MASK 0x07ff0000
2709# define TV_VSYNC_LEN_SHIFT 16
2710/** Offset of the start of vsync in field 1, measured in one less than the
2711 * number of half lines.
2712 */
2713# define TV_VSYNC_START_F1_MASK 0x00007f00
2714# define TV_VSYNC_START_F1_SHIFT 8
2715/**
2716 * Offset of the start of vsync in field 2, measured in one less than the
2717 * number of half lines.
2718 */
2719# define TV_VSYNC_START_F2_MASK 0x0000007f
2720# define TV_VSYNC_START_F2_SHIFT 0
2721
2722#define TV_V_CTL_3 0x68044
2723/** Enables generation of the equalization signal */
2724# define TV_EQUAL_ENA (1 << 31)
2725/** Length of vsync, in half lines */
2726# define TV_VEQ_LEN_MASK 0x007f0000
2727# define TV_VEQ_LEN_SHIFT 16
2728/** Offset of the start of equalization in field 1, measured in one less than
2729 * the number of half lines.
2730 */
2731# define TV_VEQ_START_F1_MASK 0x0007f00
2732# define TV_VEQ_START_F1_SHIFT 8
2733/**
2734 * Offset of the start of equalization in field 2, measured in one less than
2735 * the number of half lines.
2736 */
2737# define TV_VEQ_START_F2_MASK 0x000007f
2738# define TV_VEQ_START_F2_SHIFT 0
2739
2740#define TV_V_CTL_4 0x68048
2741/**
2742 * Offset to start of vertical colorburst, measured in one less than the
2743 * number of lines from vertical start.
2744 */
2745# define TV_VBURST_START_F1_MASK 0x003f0000
2746# define TV_VBURST_START_F1_SHIFT 16
2747/**
2748 * Offset to the end of vertical colorburst, measured in one less than the
2749 * number of lines from the start of NBR.
2750 */
2751# define TV_VBURST_END_F1_MASK 0x000000ff
2752# define TV_VBURST_END_F1_SHIFT 0
2753
2754#define TV_V_CTL_5 0x6804c
2755/**
2756 * Offset to start of vertical colorburst, measured in one less than the
2757 * number of lines from vertical start.
2758 */
2759# define TV_VBURST_START_F2_MASK 0x003f0000
2760# define TV_VBURST_START_F2_SHIFT 16
2761/**
2762 * Offset to the end of vertical colorburst, measured in one less than the
2763 * number of lines from the start of NBR.
2764 */
2765# define TV_VBURST_END_F2_MASK 0x000000ff
2766# define TV_VBURST_END_F2_SHIFT 0
2767
2768#define TV_V_CTL_6 0x68050
2769/**
2770 * Offset to start of vertical colorburst, measured in one less than the
2771 * number of lines from vertical start.
2772 */
2773# define TV_VBURST_START_F3_MASK 0x003f0000
2774# define TV_VBURST_START_F3_SHIFT 16
2775/**
2776 * Offset to the end of vertical colorburst, measured in one less than the
2777 * number of lines from the start of NBR.
2778 */
2779# define TV_VBURST_END_F3_MASK 0x000000ff
2780# define TV_VBURST_END_F3_SHIFT 0
2781
2782#define TV_V_CTL_7 0x68054
2783/**
2784 * Offset to start of vertical colorburst, measured in one less than the
2785 * number of lines from vertical start.
2786 */
2787# define TV_VBURST_START_F4_MASK 0x003f0000
2788# define TV_VBURST_START_F4_SHIFT 16
2789/**
2790 * Offset to the end of vertical colorburst, measured in one less than the
2791 * number of lines from the start of NBR.
2792 */
2793# define TV_VBURST_END_F4_MASK 0x000000ff
2794# define TV_VBURST_END_F4_SHIFT 0
2795
2796#define TV_SC_CTL_1 0x68060
2797/** Turns on the first subcarrier phase generation DDA */
2798# define TV_SC_DDA1_EN (1 << 31)
2799/** Turns on the first subcarrier phase generation DDA */
2800# define TV_SC_DDA2_EN (1 << 30)
2801/** Turns on the first subcarrier phase generation DDA */
2802# define TV_SC_DDA3_EN (1 << 29)
2803/** Sets the subcarrier DDA to reset frequency every other field */
2804# define TV_SC_RESET_EVERY_2 (0 << 24)
2805/** Sets the subcarrier DDA to reset frequency every fourth field */
2806# define TV_SC_RESET_EVERY_4 (1 << 24)
2807/** Sets the subcarrier DDA to reset frequency every eighth field */
2808# define TV_SC_RESET_EVERY_8 (2 << 24)
2809/** Sets the subcarrier DDA to never reset the frequency */
2810# define TV_SC_RESET_NEVER (3 << 24)
2811/** Sets the peak amplitude of the colorburst.*/
2812# define TV_BURST_LEVEL_MASK 0x00ff0000
2813# define TV_BURST_LEVEL_SHIFT 16
2814/** Sets the increment of the first subcarrier phase generation DDA */
2815# define TV_SCDDA1_INC_MASK 0x00000fff
2816# define TV_SCDDA1_INC_SHIFT 0
2817
2818#define TV_SC_CTL_2 0x68064
2819/** Sets the rollover for the second subcarrier phase generation DDA */
2820# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2821# define TV_SCDDA2_SIZE_SHIFT 16
2822/** Sets the increent of the second subcarrier phase generation DDA */
2823# define TV_SCDDA2_INC_MASK 0x00007fff
2824# define TV_SCDDA2_INC_SHIFT 0
2825
2826#define TV_SC_CTL_3 0x68068
2827/** Sets the rollover for the third subcarrier phase generation DDA */
2828# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2829# define TV_SCDDA3_SIZE_SHIFT 16
2830/** Sets the increent of the third subcarrier phase generation DDA */
2831# define TV_SCDDA3_INC_MASK 0x00007fff
2832# define TV_SCDDA3_INC_SHIFT 0
2833
2834#define TV_WIN_POS 0x68070
2835/** X coordinate of the display from the start of horizontal active */
2836# define TV_XPOS_MASK 0x1fff0000
2837# define TV_XPOS_SHIFT 16
2838/** Y coordinate of the display from the start of vertical active (NBR) */
2839# define TV_YPOS_MASK 0x00000fff
2840# define TV_YPOS_SHIFT 0
2841
2842#define TV_WIN_SIZE 0x68074
2843/** Horizontal size of the display window, measured in pixels*/
2844# define TV_XSIZE_MASK 0x1fff0000
2845# define TV_XSIZE_SHIFT 16
2846/**
2847 * Vertical size of the display window, measured in pixels.
2848 *
2849 * Must be even for interlaced modes.
2850 */
2851# define TV_YSIZE_MASK 0x00000fff
2852# define TV_YSIZE_SHIFT 0
2853
2854#define TV_FILTER_CTL_1 0x68080
2855/**
2856 * Enables automatic scaling calculation.
2857 *
2858 * If set, the rest of the registers are ignored, and the calculated values can
2859 * be read back from the register.
2860 */
2861# define TV_AUTO_SCALE (1 << 31)
2862/**
2863 * Disables the vertical filter.
2864 *
2865 * This is required on modes more than 1024 pixels wide */
2866# define TV_V_FILTER_BYPASS (1 << 29)
2867/** Enables adaptive vertical filtering */
2868# define TV_VADAPT (1 << 28)
2869# define TV_VADAPT_MODE_MASK (3 << 26)
2870/** Selects the least adaptive vertical filtering mode */
2871# define TV_VADAPT_MODE_LEAST (0 << 26)
2872/** Selects the moderately adaptive vertical filtering mode */
2873# define TV_VADAPT_MODE_MODERATE (1 << 26)
2874/** Selects the most adaptive vertical filtering mode */
2875# define TV_VADAPT_MODE_MOST (3 << 26)
2876/**
2877 * Sets the horizontal scaling factor.
2878 *
2879 * This should be the fractional part of the horizontal scaling factor divided
2880 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2881 *
2882 * (src width - 1) / ((oversample * dest width) - 1)
2883 */
2884# define TV_HSCALE_FRAC_MASK 0x00003fff
2885# define TV_HSCALE_FRAC_SHIFT 0
2886
2887#define TV_FILTER_CTL_2 0x68084
2888/**
2889 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2890 *
2891 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2892 */
2893# define TV_VSCALE_INT_MASK 0x00038000
2894# define TV_VSCALE_INT_SHIFT 15
2895/**
2896 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2897 *
2898 * \sa TV_VSCALE_INT_MASK
2899 */
2900# define TV_VSCALE_FRAC_MASK 0x00007fff
2901# define TV_VSCALE_FRAC_SHIFT 0
2902
2903#define TV_FILTER_CTL_3 0x68088
2904/**
2905 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2906 *
2907 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2908 *
2909 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2910 */
2911# define TV_VSCALE_IP_INT_MASK 0x00038000
2912# define TV_VSCALE_IP_INT_SHIFT 15
2913/**
2914 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2915 *
2916 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2917 *
2918 * \sa TV_VSCALE_IP_INT_MASK
2919 */
2920# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2921# define TV_VSCALE_IP_FRAC_SHIFT 0
2922
2923#define TV_CC_CONTROL 0x68090
2924# define TV_CC_ENABLE (1 << 31)
2925/**
2926 * Specifies which field to send the CC data in.
2927 *
2928 * CC data is usually sent in field 0.
2929 */
2930# define TV_CC_FID_MASK (1 << 27)
2931# define TV_CC_FID_SHIFT 27
2932/** Sets the horizontal position of the CC data. Usually 135. */
2933# define TV_CC_HOFF_MASK 0x03ff0000
2934# define TV_CC_HOFF_SHIFT 16
2935/** Sets the vertical position of the CC data. Usually 21 */
2936# define TV_CC_LINE_MASK 0x0000003f
2937# define TV_CC_LINE_SHIFT 0
2938
2939#define TV_CC_DATA 0x68094
2940# define TV_CC_RDY (1 << 31)
2941/** Second word of CC data to be transmitted. */
2942# define TV_CC_DATA_2_MASK 0x007f0000
2943# define TV_CC_DATA_2_SHIFT 16
2944/** First word of CC data to be transmitted. */
2945# define TV_CC_DATA_1_MASK 0x0000007f
2946# define TV_CC_DATA_1_SHIFT 0
2947
2948#define TV_H_LUMA_0 0x68100
2949#define TV_H_LUMA_59 0x681ec
2950#define TV_H_CHROMA_0 0x68200
2951#define TV_H_CHROMA_59 0x682ec
2952#define TV_V_LUMA_0 0x68300
2953#define TV_V_LUMA_42 0x683a8
2954#define TV_V_CHROMA_0 0x68400
2955#define TV_V_CHROMA_42 0x684a8
2956
Keith Packard040d87f2009-05-30 20:42:33 -07002957/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002958#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07002959#define DP_B 0x64100
2960#define DP_C 0x64200
2961#define DP_D 0x64300
2962
2963#define DP_PORT_EN (1 << 31)
2964#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002965#define DP_PIPE_MASK (1 << 30)
2966
Keith Packard040d87f2009-05-30 20:42:33 -07002967/* Link training mode - select a suitable mode for each stage */
2968#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2969#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2970#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2971#define DP_LINK_TRAIN_OFF (3 << 28)
2972#define DP_LINK_TRAIN_MASK (3 << 28)
2973#define DP_LINK_TRAIN_SHIFT 28
2974
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002975/* CPT Link training mode */
2976#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2977#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2978#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2979#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2980#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2981#define DP_LINK_TRAIN_SHIFT_CPT 8
2982
Keith Packard040d87f2009-05-30 20:42:33 -07002983/* Signal voltages. These are mostly controlled by the other end */
2984#define DP_VOLTAGE_0_4 (0 << 25)
2985#define DP_VOLTAGE_0_6 (1 << 25)
2986#define DP_VOLTAGE_0_8 (2 << 25)
2987#define DP_VOLTAGE_1_2 (3 << 25)
2988#define DP_VOLTAGE_MASK (7 << 25)
2989#define DP_VOLTAGE_SHIFT 25
2990
2991/* Signal pre-emphasis levels, like voltages, the other end tells us what
2992 * they want
2993 */
2994#define DP_PRE_EMPHASIS_0 (0 << 22)
2995#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2996#define DP_PRE_EMPHASIS_6 (2 << 22)
2997#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2998#define DP_PRE_EMPHASIS_MASK (7 << 22)
2999#define DP_PRE_EMPHASIS_SHIFT 22
3000
3001/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02003002#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07003003#define DP_PORT_WIDTH_MASK (7 << 19)
3004
3005/* Mystic DPCD version 1.1 special mode */
3006#define DP_ENHANCED_FRAMING (1 << 18)
3007
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003008/* eDP */
3009#define DP_PLL_FREQ_270MHZ (0 << 16)
3010#define DP_PLL_FREQ_160MHZ (1 << 16)
3011#define DP_PLL_FREQ_MASK (3 << 16)
3012
Keith Packard040d87f2009-05-30 20:42:33 -07003013/** locked once port is enabled */
3014#define DP_PORT_REVERSAL (1 << 15)
3015
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003016/* eDP */
3017#define DP_PLL_ENABLE (1 << 14)
3018
Keith Packard040d87f2009-05-30 20:42:33 -07003019/** sends the clock on lane 15 of the PEG for debug */
3020#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3021
3022#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003023#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07003024
3025/** limit RGB values to avoid confusing TVs */
3026#define DP_COLOR_RANGE_16_235 (1 << 8)
3027
3028/** Turn on the audio link */
3029#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3030
3031/** vs and hs sync polarity */
3032#define DP_SYNC_VS_HIGH (1 << 4)
3033#define DP_SYNC_HS_HIGH (1 << 3)
3034
3035/** A fantasy */
3036#define DP_DETECTED (1 << 2)
3037
3038/** The aux channel provides a way to talk to the
3039 * signal sink for DDC etc. Max packet size supported
3040 * is 20 bytes in each direction, hence the 5 fixed
3041 * data registers
3042 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003043#define DPA_AUX_CH_CTL 0x64010
3044#define DPA_AUX_CH_DATA1 0x64014
3045#define DPA_AUX_CH_DATA2 0x64018
3046#define DPA_AUX_CH_DATA3 0x6401c
3047#define DPA_AUX_CH_DATA4 0x64020
3048#define DPA_AUX_CH_DATA5 0x64024
3049
Keith Packard040d87f2009-05-30 20:42:33 -07003050#define DPB_AUX_CH_CTL 0x64110
3051#define DPB_AUX_CH_DATA1 0x64114
3052#define DPB_AUX_CH_DATA2 0x64118
3053#define DPB_AUX_CH_DATA3 0x6411c
3054#define DPB_AUX_CH_DATA4 0x64120
3055#define DPB_AUX_CH_DATA5 0x64124
3056
3057#define DPC_AUX_CH_CTL 0x64210
3058#define DPC_AUX_CH_DATA1 0x64214
3059#define DPC_AUX_CH_DATA2 0x64218
3060#define DPC_AUX_CH_DATA3 0x6421c
3061#define DPC_AUX_CH_DATA4 0x64220
3062#define DPC_AUX_CH_DATA5 0x64224
3063
3064#define DPD_AUX_CH_CTL 0x64310
3065#define DPD_AUX_CH_DATA1 0x64314
3066#define DPD_AUX_CH_DATA2 0x64318
3067#define DPD_AUX_CH_DATA3 0x6431c
3068#define DPD_AUX_CH_DATA4 0x64320
3069#define DPD_AUX_CH_DATA5 0x64324
3070
3071#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3072#define DP_AUX_CH_CTL_DONE (1 << 30)
3073#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3074#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3075#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3076#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3077#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3078#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3079#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3080#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3081#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3082#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3083#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3084#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3085#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3086#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3087#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3088#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3089#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3090#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3091#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3092
3093/*
3094 * Computing GMCH M and N values for the Display Port link
3095 *
3096 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3097 *
3098 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3099 *
3100 * The GMCH value is used internally
3101 *
3102 * bytes_per_pixel is the number of bytes coming out of the plane,
3103 * which is after the LUTs, so we want the bytes for our color format.
3104 * For our current usage, this is always 3, one byte for R, G and B.
3105 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02003106#define _PIPEA_DATA_M_G4X 0x70050
3107#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07003108
3109/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003110#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02003111#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003112#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07003113
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003114#define DATA_LINK_M_N_MASK (0xffffff)
3115#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07003116
Daniel Vettere3b95f12013-05-03 11:49:49 +02003117#define _PIPEA_DATA_N_G4X 0x70054
3118#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07003119#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3120
3121/*
3122 * Computing Link M and N values for the Display Port link
3123 *
3124 * Link M / N = pixel_clock / ls_clk
3125 *
3126 * (the DP spec calls pixel_clock the 'strm_clk')
3127 *
3128 * The Link value is transmitted in the Main Stream
3129 * Attributes and VB-ID.
3130 */
3131
Daniel Vettere3b95f12013-05-03 11:49:49 +02003132#define _PIPEA_LINK_M_G4X 0x70060
3133#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07003134#define PIPEA_DP_LINK_M_MASK (0xffffff)
3135
Daniel Vettere3b95f12013-05-03 11:49:49 +02003136#define _PIPEA_LINK_N_G4X 0x70064
3137#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07003138#define PIPEA_DP_LINK_N_MASK (0xffffff)
3139
Daniel Vettere3b95f12013-05-03 11:49:49 +02003140#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3141#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3142#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3143#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003144
Jesse Barnes585fb112008-07-29 11:54:06 -07003145/* Display & cursor control */
3146
3147/* Pipe A */
Ville Syrjälä0c3870e2013-01-24 15:29:36 +02003148#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
Paulo Zanoni837ba002012-05-04 17:18:14 -03003149#define DSL_LINEMASK_GEN2 0x00000fff
3150#define DSL_LINEMASK_GEN3 0x00001fff
Ville Syrjälä0c3870e2013-01-24 15:29:36 +02003151#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
Chris Wilson5eddb702010-09-11 13:48:45 +01003152#define PIPECONF_ENABLE (1<<31)
3153#define PIPECONF_DISABLE 0
3154#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003155#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03003156#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00003157#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01003158#define PIPECONF_SINGLE_WIDE 0
3159#define PIPECONF_PIPE_UNLOCKED 0
3160#define PIPECONF_PIPE_LOCKED (1<<25)
3161#define PIPECONF_PALETTE 0
3162#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07003163#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01003164#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03003165#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01003166/* Note that pre-gen3 does not support interlaced display directly. Panel
3167 * fitting must be disabled on pre-ilk for interlaced. */
3168#define PIPECONF_PROGRESSIVE (0 << 21)
3169#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3170#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3171#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3172#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3173/* Ironlake and later have a complete new set of values for interlaced. PFIT
3174 * means panel fitter required, PF means progressive fetch, DBL means power
3175 * saving pixel doubling. */
3176#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3177#define PIPECONF_INTERLACED_ILK (3 << 21)
3178#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3179#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02003180#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Jesse Barnes652c3932009-08-17 13:31:43 -07003181#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02003182#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003183#define PIPECONF_BPC_MASK (0x7 << 5)
3184#define PIPECONF_8BPC (0<<5)
3185#define PIPECONF_10BPC (1<<5)
3186#define PIPECONF_6BPC (2<<5)
3187#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07003188#define PIPECONF_DITHER_EN (1<<4)
3189#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3190#define PIPECONF_DITHER_TYPE_SP (0<<2)
3191#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3192#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3193#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Ville Syrjälä0c3870e2013-01-24 15:29:36 +02003194#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
Jesse Barnes585fb112008-07-29 11:54:06 -07003195#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003196#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003197#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3198#define PIPE_CRC_DONE_ENABLE (1UL<<28)
3199#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003200#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003201#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3202#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3203#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3204#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02003205#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07003206#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3207#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3208#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3209#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3210#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3211#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003212#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003213#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003214#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02003215#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07003216#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3217#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3218#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003219#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003220#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3221#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3222#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3223#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3224#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3225#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3226#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3227#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3228#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3229#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3230#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3231
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003232#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
Paulo Zanoni702e7a52012-10-23 18:29:59 -02003233#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003234#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
3235#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
3236#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
3237#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01003238
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02003239#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07003240#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003241#define PIPEB_HLINE_INT_EN (1<<28)
3242#define PIPEB_VBLANK_INT_EN (1<<27)
3243#define SPRITED_FLIPDONE_INT_EN (1<<26)
3244#define SPRITEC_FLIPDONE_INT_EN (1<<25)
3245#define PLANEB_FLIPDONE_INT_EN (1<<24)
Jesse Barnes79831172012-06-20 10:53:12 -07003246#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003247#define PIPEA_HLINE_INT_EN (1<<20)
3248#define PIPEA_VBLANK_INT_EN (1<<19)
3249#define SPRITEB_FLIPDONE_INT_EN (1<<18)
3250#define SPRITEA_FLIPDONE_INT_EN (1<<17)
3251#define PLANEA_FLIPDONE_INT_EN (1<<16)
3252
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02003253#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003254#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3255#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3256#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3257#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3258#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3259#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3260#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3261#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3262#define DPINVGTT_EN_MASK 0xff0000
3263#define CURSORB_INVALID_GTT_STATUS (1<<7)
3264#define CURSORA_INVALID_GTT_STATUS (1<<6)
3265#define SPRITED_INVALID_GTT_STATUS (1<<5)
3266#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3267#define PLANEB_INVALID_GTT_STATUS (1<<3)
3268#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3269#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3270#define PLANEA_INVALID_GTT_STATUS (1<<0)
3271#define DPINVGTT_STATUS_MASK 0xff
3272
Jesse Barnes585fb112008-07-29 11:54:06 -07003273#define DSPARB 0x70030
3274#define DSPARB_CSTART_MASK (0x7f << 7)
3275#define DSPARB_CSTART_SHIFT 7
3276#define DSPARB_BSTART_MASK (0x7f)
3277#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08003278#define DSPARB_BEND_SHIFT 9 /* on 855 */
3279#define DSPARB_AEND_SHIFT 0
3280
Ville Syrjälä90f7da32013-01-24 15:29:39 +02003281#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003282#define DSPFW_SR_SHIFT 23
Akshay Joshi0206e352011-08-16 15:34:10 -04003283#define DSPFW_SR_MASK (0x1ff<<23)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003284#define DSPFW_CURSORB_SHIFT 16
Zhao Yakuid4294342010-03-22 22:45:36 +08003285#define DSPFW_CURSORB_MASK (0x3f<<16)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003286#define DSPFW_PLANEB_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08003287#define DSPFW_PLANEB_MASK (0x7f<<8)
3288#define DSPFW_PLANEA_MASK (0x7f)
Ville Syrjälä90f7da32013-01-24 15:29:39 +02003289#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003290#define DSPFW_CURSORA_MASK 0x00003f00
Zhao Yakui21bd7702010-01-13 14:10:50 +00003291#define DSPFW_CURSORA_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08003292#define DSPFW_PLANEC_MASK (0x7f)
Ville Syrjälä90f7da32013-01-24 15:29:39 +02003293#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003294#define DSPFW_HPLL_SR_EN (1<<31)
3295#define DSPFW_CURSOR_SR_SHIFT 24
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003296#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Zhao Yakuid4294342010-03-22 22:45:36 +08003297#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3298#define DSPFW_HPLL_CURSOR_SHIFT 16
3299#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3300#define DSPFW_HPLL_SR_MASK (0x1ff)
Jesse Barnes12569ad2013-03-08 10:45:59 -08003301#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070)
3302#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003303
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003304/* drain latency register values*/
3305#define DRAIN_LATENCY_PRECISION_32 32
3306#define DRAIN_LATENCY_PRECISION_16 16
Ville Syrjälä8f6d8ee2013-01-24 15:29:38 +02003307#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003308#define DDL_CURSORA_PRECISION_32 (1<<31)
3309#define DDL_CURSORA_PRECISION_16 (0<<31)
3310#define DDL_CURSORA_SHIFT 24
3311#define DDL_PLANEA_PRECISION_32 (1<<7)
3312#define DDL_PLANEA_PRECISION_16 (0<<7)
Ville Syrjälä8f6d8ee2013-01-24 15:29:38 +02003313#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003314#define DDL_CURSORB_PRECISION_32 (1<<31)
3315#define DDL_CURSORB_PRECISION_16 (0<<31)
3316#define DDL_CURSORB_SHIFT 24
3317#define DDL_PLANEB_PRECISION_32 (1<<7)
3318#define DDL_PLANEB_PRECISION_16 (0<<7)
3319
Shaohua Li7662c8b2009-06-26 11:23:55 +08003320/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09003321#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08003322#define I915_FIFO_LINE_SIZE 64
3323#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09003324
Jesse Barnesceb04242012-03-28 13:39:22 -07003325#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09003326#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08003327#define I965_FIFO_SIZE 512
3328#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08003329#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003330#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003331#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09003332
Jesse Barnesceb04242012-03-28 13:39:22 -07003333#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09003334#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08003335#define I915_MAX_WM 0x3f
3336
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003337#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3338#define PINEVIEW_FIFO_LINE_SIZE 64
3339#define PINEVIEW_MAX_WM 0x1ff
3340#define PINEVIEW_DFT_WM 0x3f
3341#define PINEVIEW_DFT_HPLLOFF_WM 0
3342#define PINEVIEW_GUARD_WM 10
3343#define PINEVIEW_CURSOR_FIFO 64
3344#define PINEVIEW_CURSOR_MAX_WM 0x3f
3345#define PINEVIEW_CURSOR_DFT_WM 0
3346#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08003347
Jesse Barnesceb04242012-03-28 13:39:22 -07003348#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003349#define I965_CURSOR_FIFO 64
3350#define I965_CURSOR_MAX_WM 32
3351#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003352
3353/* define the Watermark register on Ironlake */
3354#define WM0_PIPEA_ILK 0x45100
Ville Syrjälä1996d622013-10-09 19:18:07 +03003355#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003356#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03003357#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003358#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03003359#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003360
3361#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07003362#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003363#define WM1_LP_ILK 0x45108
3364#define WM1_LP_SR_EN (1<<31)
3365#define WM1_LP_LATENCY_SHIFT 24
3366#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01003367#define WM1_LP_FBC_MASK (0xf<<20)
3368#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä1996d622013-10-09 19:18:07 +03003369#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003370#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03003371#define WM1_LP_CURSOR_MASK (0xff)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07003372#define WM2_LP_ILK 0x4510c
3373#define WM2_LP_EN (1<<31)
3374#define WM3_LP_ILK 0x45110
3375#define WM3_LP_EN (1<<31)
3376#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003377#define WM2S_LP_IVB 0x45124
3378#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07003379#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003380
Paulo Zanonicca32e92013-05-31 11:45:06 -03003381#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3382 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3383 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3384
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003385/* Memory latency timer register */
3386#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08003387#define MLTR_WM1_SHIFT 0
3388#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003389/* the unit of memory self-refresh latency time is 0.5us */
3390#define ILK_SRLT_MASK 0x3f
3391
3392/* define the fifo size on Ironlake */
3393#define ILK_DISPLAY_FIFO 128
3394#define ILK_DISPLAY_MAXWM 64
3395#define ILK_DISPLAY_DFTWM 8
Zhao Yakuic936f442010-06-12 14:32:26 +08003396#define ILK_CURSOR_FIFO 32
3397#define ILK_CURSOR_MAXWM 16
3398#define ILK_CURSOR_DFTWM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003399
3400#define ILK_DISPLAY_SR_FIFO 512
3401#define ILK_DISPLAY_MAX_SRWM 0x1ff
3402#define ILK_DISPLAY_DFT_SRWM 0x3f
3403#define ILK_CURSOR_SR_FIFO 64
3404#define ILK_CURSOR_MAX_SRWM 0x3f
3405#define ILK_CURSOR_DFT_SRWM 8
3406
3407#define ILK_FIFO_LINE_SIZE 64
3408
Yuanhan Liu13982612010-12-15 15:42:31 +08003409/* define the WM info on Sandybridge */
3410#define SNB_DISPLAY_FIFO 128
3411#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
3412#define SNB_DISPLAY_DFTWM 8
3413#define SNB_CURSOR_FIFO 32
3414#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
3415#define SNB_CURSOR_DFTWM 8
3416
3417#define SNB_DISPLAY_SR_FIFO 512
3418#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
3419#define SNB_DISPLAY_DFT_SRWM 0x3f
3420#define SNB_CURSOR_SR_FIFO 64
3421#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
3422#define SNB_CURSOR_DFT_SRWM 8
3423
3424#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
3425
3426#define SNB_FIFO_LINE_SIZE 64
3427
3428
3429/* the address where we get all kinds of latency value */
3430#define SSKPD 0x5d10
3431#define SSKPD_WM_MASK 0x3f
3432#define SSKPD_WM0_SHIFT 0
3433#define SSKPD_WM1_SHIFT 8
3434#define SSKPD_WM2_SHIFT 16
3435#define SSKPD_WM3_SHIFT 24
3436
Jesse Barnes585fb112008-07-29 11:54:06 -07003437/*
3438 * The two pipe frame counter registers are not synchronized, so
3439 * reading a stable value is somewhat tricky. The following code
3440 * should work:
3441 *
3442 * do {
3443 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3444 * PIPE_FRAME_HIGH_SHIFT;
3445 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3446 * PIPE_FRAME_LOW_SHIFT);
3447 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3448 * PIPE_FRAME_HIGH_SHIFT);
3449 * } while (high1 != high2);
3450 * frame = (high1 << 8) | low1;
3451 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003452#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07003453#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3454#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003455#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07003456#define PIPE_FRAME_LOW_MASK 0xff000000
3457#define PIPE_FRAME_LOW_SHIFT 24
3458#define PIPE_PIXEL_MASK 0x00ffffff
3459#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08003460/* GM45+ just has to be different */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003461#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040)
3462#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003463#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07003464
3465/* Cursor A & B regs */
Ville Syrjälä9dc33f32013-01-24 15:29:37 +02003466#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
Jesse Barnes14b603912009-05-20 16:47:08 -04003467/* Old style CUR*CNTR flags (desktop 8xx) */
3468#define CURSOR_ENABLE 0x80000000
3469#define CURSOR_GAMMA_ENABLE 0x40000000
3470#define CURSOR_STRIDE_MASK 0x30000000
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02003471#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b603912009-05-20 16:47:08 -04003472#define CURSOR_FORMAT_SHIFT 24
3473#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3474#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3475#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3476#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3477#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3478#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3479/* New style CUR*CNTR flags */
3480#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07003481#define CURSOR_MODE_DISABLE 0x00
3482#define CURSOR_MODE_64_32B_AX 0x07
3483#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b603912009-05-20 16:47:08 -04003484#define MCURSOR_PIPE_SELECT (1 << 28)
3485#define MCURSOR_PIPE_A 0x00
3486#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07003487#define MCURSOR_GAMMA_ENABLE (1 << 26)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03003488#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä9dc33f32013-01-24 15:29:37 +02003489#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
3490#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
Jesse Barnes585fb112008-07-29 11:54:06 -07003491#define CURSOR_POS_MASK 0x007FF
3492#define CURSOR_POS_SIGN 0x8000
3493#define CURSOR_X_SHIFT 0
3494#define CURSOR_Y_SHIFT 16
Jesse Barnes14b603912009-05-20 16:47:08 -04003495#define CURSIZE 0x700a0
Ville Syrjälä9dc33f32013-01-24 15:29:37 +02003496#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
3497#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
3498#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
Jesse Barnes585fb112008-07-29 11:54:06 -07003499
Jesse Barnes65a21cd2011-10-12 11:10:21 -07003500#define _CURBCNTR_IVB 0x71080
3501#define _CURBBASE_IVB 0x71084
3502#define _CURBPOS_IVB 0x71088
3503
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003504#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3505#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3506#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003507
Jesse Barnes65a21cd2011-10-12 11:10:21 -07003508#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3509#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3510#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3511
Jesse Barnes585fb112008-07-29 11:54:06 -07003512/* Display A control */
Ville Syrjälä895abf02013-01-24 15:29:35 +02003513#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
Jesse Barnes585fb112008-07-29 11:54:06 -07003514#define DISPLAY_PLANE_ENABLE (1<<31)
3515#define DISPLAY_PLANE_DISABLE 0
3516#define DISPPLANE_GAMMA_ENABLE (1<<30)
3517#define DISPPLANE_GAMMA_DISABLE 0
3518#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02003519#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003520#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02003521#define DISPPLANE_BGRA555 (0x3<<26)
3522#define DISPPLANE_BGRX555 (0x4<<26)
3523#define DISPPLANE_BGRX565 (0x5<<26)
3524#define DISPPLANE_BGRX888 (0x6<<26)
3525#define DISPPLANE_BGRA888 (0x7<<26)
3526#define DISPPLANE_RGBX101010 (0x8<<26)
3527#define DISPPLANE_RGBA101010 (0x9<<26)
3528#define DISPPLANE_BGRX101010 (0xa<<26)
3529#define DISPPLANE_RGBX161616 (0xc<<26)
3530#define DISPPLANE_RGBX888 (0xe<<26)
3531#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003532#define DISPPLANE_STEREO_ENABLE (1<<25)
3533#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02003534#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08003535#define DISPPLANE_SEL_PIPE_SHIFT 24
3536#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07003537#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08003538#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07003539#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3540#define DISPPLANE_SRC_KEY_DISABLE 0
3541#define DISPPLANE_LINE_DOUBLE (1<<20)
3542#define DISPPLANE_NO_LINE_DOUBLE 0
3543#define DISPPLANE_STEREO_POLARITY_FIRST 0
3544#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003545#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07003546#define DISPPLANE_TILED (1<<10)
Ville Syrjälä895abf02013-01-24 15:29:35 +02003547#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
3548#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
3549#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3550#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
3551#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3552#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3553#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3554#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07003555
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003556#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3557#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3558#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3559#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3560#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3561#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3562#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
Daniel Vettere506a0c2012-07-05 12:17:29 +02003563#define DSPLINOFF(plane) DSPADDR(plane)
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00003564#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02003565#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01003566
Armin Reese446f2542012-03-30 16:20:16 -07003567/* Display/Sprite base address macros */
3568#define DISP_BASEADDR_MASK (0xfffff000)
3569#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3570#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3571#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
Daniel Vetterc2c75132012-07-05 12:17:30 +02003572 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
Armin Reese446f2542012-03-30 16:20:16 -07003573
Jesse Barnes585fb112008-07-29 11:54:06 -07003574/* VBIOS flags */
Ville Syrjälä80a75f72013-01-24 15:29:33 +02003575#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
3576#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
3577#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
3578#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
3579#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
3580#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
3581#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
3582#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
3583#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
3584#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
3585#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
3586#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
3587#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
Jesse Barnes585fb112008-07-29 11:54:06 -07003588
3589/* Pipe B */
Ville Syrjälä0c3870e2013-01-24 15:29:36 +02003590#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
3591#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
3592#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003593#define _PIPEBFRAMEHIGH 0x71040
3594#define _PIPEBFRAMEPIXEL 0x71044
3595#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040)
3596#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08003597
Jesse Barnes585fb112008-07-29 11:54:06 -07003598
3599/* Display B control */
Ville Syrjälä895abf02013-01-24 15:29:35 +02003600#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07003601#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3602#define DISPPLANE_ALPHA_TRANS_DISABLE 0
3603#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3604#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Ville Syrjälä895abf02013-01-24 15:29:35 +02003605#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
3606#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
3607#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
3608#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
3609#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
3610#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
3611#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
3612#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07003613
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003614/* Sprite A control */
3615#define _DVSACNTR 0x72180
3616#define DVS_ENABLE (1<<31)
3617#define DVS_GAMMA_ENABLE (1<<30)
3618#define DVS_PIXFORMAT_MASK (3<<25)
3619#define DVS_FORMAT_YUV422 (0<<25)
3620#define DVS_FORMAT_RGBX101010 (1<<25)
3621#define DVS_FORMAT_RGBX888 (2<<25)
3622#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02003623#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003624#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08003625#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003626#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3627#define DVS_YUV_ORDER_YUYV (0<<16)
3628#define DVS_YUV_ORDER_UYVY (1<<16)
3629#define DVS_YUV_ORDER_YVYU (2<<16)
3630#define DVS_YUV_ORDER_VYUY (3<<16)
3631#define DVS_DEST_KEY (1<<2)
3632#define DVS_TRICKLE_FEED_DISABLE (1<<14)
3633#define DVS_TILED (1<<10)
3634#define _DVSALINOFF 0x72184
3635#define _DVSASTRIDE 0x72188
3636#define _DVSAPOS 0x7218c
3637#define _DVSASIZE 0x72190
3638#define _DVSAKEYVAL 0x72194
3639#define _DVSAKEYMSK 0x72198
3640#define _DVSASURF 0x7219c
3641#define _DVSAKEYMAXVAL 0x721a0
3642#define _DVSATILEOFF 0x721a4
3643#define _DVSASURFLIVE 0x721ac
3644#define _DVSASCALE 0x72204
3645#define DVS_SCALE_ENABLE (1<<31)
3646#define DVS_FILTER_MASK (3<<29)
3647#define DVS_FILTER_MEDIUM (0<<29)
3648#define DVS_FILTER_ENHANCING (1<<29)
3649#define DVS_FILTER_SOFTENING (2<<29)
3650#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3651#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3652#define _DVSAGAMC 0x72300
3653
3654#define _DVSBCNTR 0x73180
3655#define _DVSBLINOFF 0x73184
3656#define _DVSBSTRIDE 0x73188
3657#define _DVSBPOS 0x7318c
3658#define _DVSBSIZE 0x73190
3659#define _DVSBKEYVAL 0x73194
3660#define _DVSBKEYMSK 0x73198
3661#define _DVSBSURF 0x7319c
3662#define _DVSBKEYMAXVAL 0x731a0
3663#define _DVSBTILEOFF 0x731a4
3664#define _DVSBSURFLIVE 0x731ac
3665#define _DVSBSCALE 0x73204
3666#define _DVSBGAMC 0x73300
3667
3668#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3669#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3670#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3671#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3672#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08003673#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003674#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3675#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3676#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08003677#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3678#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02003679#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003680
3681#define _SPRA_CTL 0x70280
3682#define SPRITE_ENABLE (1<<31)
3683#define SPRITE_GAMMA_ENABLE (1<<30)
3684#define SPRITE_PIXFORMAT_MASK (7<<25)
3685#define SPRITE_FORMAT_YUV422 (0<<25)
3686#define SPRITE_FORMAT_RGBX101010 (1<<25)
3687#define SPRITE_FORMAT_RGBX888 (2<<25)
3688#define SPRITE_FORMAT_RGBX161616 (3<<25)
3689#define SPRITE_FORMAT_YUV444 (4<<25)
3690#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02003691#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003692#define SPRITE_SOURCE_KEY (1<<22)
3693#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3694#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3695#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3696#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3697#define SPRITE_YUV_ORDER_YUYV (0<<16)
3698#define SPRITE_YUV_ORDER_UYVY (1<<16)
3699#define SPRITE_YUV_ORDER_YVYU (2<<16)
3700#define SPRITE_YUV_ORDER_VYUY (3<<16)
3701#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3702#define SPRITE_INT_GAMMA_ENABLE (1<<13)
3703#define SPRITE_TILED (1<<10)
3704#define SPRITE_DEST_KEY (1<<2)
3705#define _SPRA_LINOFF 0x70284
3706#define _SPRA_STRIDE 0x70288
3707#define _SPRA_POS 0x7028c
3708#define _SPRA_SIZE 0x70290
3709#define _SPRA_KEYVAL 0x70294
3710#define _SPRA_KEYMSK 0x70298
3711#define _SPRA_SURF 0x7029c
3712#define _SPRA_KEYMAX 0x702a0
3713#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01003714#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02003715#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003716#define _SPRA_SCALE 0x70304
3717#define SPRITE_SCALE_ENABLE (1<<31)
3718#define SPRITE_FILTER_MASK (3<<29)
3719#define SPRITE_FILTER_MEDIUM (0<<29)
3720#define SPRITE_FILTER_ENHANCING (1<<29)
3721#define SPRITE_FILTER_SOFTENING (2<<29)
3722#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3723#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3724#define _SPRA_GAMC 0x70400
3725
3726#define _SPRB_CTL 0x71280
3727#define _SPRB_LINOFF 0x71284
3728#define _SPRB_STRIDE 0x71288
3729#define _SPRB_POS 0x7128c
3730#define _SPRB_SIZE 0x71290
3731#define _SPRB_KEYVAL 0x71294
3732#define _SPRB_KEYMSK 0x71298
3733#define _SPRB_SURF 0x7129c
3734#define _SPRB_KEYMAX 0x712a0
3735#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01003736#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02003737#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003738#define _SPRB_SCALE 0x71304
3739#define _SPRB_GAMC 0x71400
3740
3741#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3742#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3743#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3744#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3745#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3746#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3747#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3748#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3749#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3750#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
Damien Lespiauc54173a2012-10-26 18:20:11 +01003751#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003752#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3753#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02003754#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003755
Ville Syrjälä921c3b62013-06-25 14:16:35 +03003756#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07003757#define SP_ENABLE (1<<31)
3758#define SP_GEAMMA_ENABLE (1<<30)
3759#define SP_PIXFORMAT_MASK (0xf<<26)
3760#define SP_FORMAT_YUV422 (0<<26)
3761#define SP_FORMAT_BGR565 (5<<26)
3762#define SP_FORMAT_BGRX8888 (6<<26)
3763#define SP_FORMAT_BGRA8888 (7<<26)
3764#define SP_FORMAT_RGBX1010102 (8<<26)
3765#define SP_FORMAT_RGBA1010102 (9<<26)
3766#define SP_FORMAT_RGBX8888 (0xe<<26)
3767#define SP_FORMAT_RGBA8888 (0xf<<26)
3768#define SP_SOURCE_KEY (1<<22)
3769#define SP_YUV_BYTE_ORDER_MASK (3<<16)
3770#define SP_YUV_ORDER_YUYV (0<<16)
3771#define SP_YUV_ORDER_UYVY (1<<16)
3772#define SP_YUV_ORDER_YVYU (2<<16)
3773#define SP_YUV_ORDER_VYUY (3<<16)
3774#define SP_TILED (1<<10)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03003775#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3776#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3777#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3778#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3779#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3780#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3781#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3782#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3783#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3784#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3785#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07003786
Ville Syrjälä921c3b62013-06-25 14:16:35 +03003787#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3788#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3789#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3790#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3791#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3792#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3793#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3794#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3795#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3796#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3797#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3798#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07003799
3800#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3801#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3802#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3803#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3804#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3805#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3806#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3807#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3808#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3809#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3810#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3811#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3812
Jesse Barnes585fb112008-07-29 11:54:06 -07003813/* VBIOS regs */
3814#define VGACNTRL 0x71400
3815# define VGA_DISP_DISABLE (1 << 31)
3816# define VGA_2X_MODE (1 << 30)
3817# define VGA_PIPE_B_SELECT (1 << 29)
3818
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003819#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3820
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003821/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003822
3823#define CPU_VGACNTRL 0x41000
3824
3825#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3826#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3827#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3828#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3829#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3830#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3831#define DIGITAL_PORTA_NO_DETECT (0 << 0)
3832#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3833#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3834
3835/* refresh rate hardware control */
3836#define RR_HW_CTL 0x45300
3837#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3838#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3839
3840#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01003841#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08003842#define FDI_PLL_BIOS_1 0x46004
3843#define FDI_PLL_BIOS_2 0x46008
3844#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3845#define DISPLAY_PORT_PLL_BIOS_1 0x46010
3846#define DISPLAY_PORT_PLL_BIOS_2 0x46014
3847
Eric Anholt8956c8b2010-03-18 13:21:14 -07003848#define PCH_3DCGDIS0 0x46020
3849# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3850# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3851
Eric Anholt06f37752010-12-14 10:06:46 -08003852#define PCH_3DCGDIS1 0x46024
3853# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3854
Zhenyu Wangb9055052009-06-05 15:38:38 +08003855#define FDI_PLL_FREQ_CTL 0x46030
3856#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3857#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3858#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3859
3860
Ville Syrjäläaab171392013-01-24 15:29:32 +02003861#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
Chris Wilson5eddb702010-09-11 13:48:45 +01003862#define PIPE_DATA_M1_OFFSET 0
Ville Syrjäläaab171392013-01-24 15:29:32 +02003863#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
Chris Wilson5eddb702010-09-11 13:48:45 +01003864#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08003865
Ville Syrjäläaab171392013-01-24 15:29:32 +02003866#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
Chris Wilson5eddb702010-09-11 13:48:45 +01003867#define PIPE_DATA_M2_OFFSET 0
Ville Syrjäläaab171392013-01-24 15:29:32 +02003868#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
Chris Wilson5eddb702010-09-11 13:48:45 +01003869#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08003870
Ville Syrjäläaab171392013-01-24 15:29:32 +02003871#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
Chris Wilson5eddb702010-09-11 13:48:45 +01003872#define PIPE_LINK_M1_OFFSET 0
Ville Syrjäläaab171392013-01-24 15:29:32 +02003873#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
Chris Wilson5eddb702010-09-11 13:48:45 +01003874#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08003875
Ville Syrjäläaab171392013-01-24 15:29:32 +02003876#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
Chris Wilson5eddb702010-09-11 13:48:45 +01003877#define PIPE_LINK_M2_OFFSET 0
Ville Syrjäläaab171392013-01-24 15:29:32 +02003878#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
Chris Wilson5eddb702010-09-11 13:48:45 +01003879#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08003880
3881/* PIPEB timing regs are same start from 0x61000 */
3882
Ville Syrjäläaab171392013-01-24 15:29:32 +02003883#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
3884#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003885
Ville Syrjäläaab171392013-01-24 15:29:32 +02003886#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
3887#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003888
Ville Syrjäläaab171392013-01-24 15:29:32 +02003889#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
3890#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003891
Ville Syrjäläaab171392013-01-24 15:29:32 +02003892#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
3893#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
Chris Wilson5eddb702010-09-11 13:48:45 +01003894
Paulo Zanoniafe2fcf2012-10-23 18:30:01 -02003895#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3896#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3897#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3898#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3899#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3900#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3901#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3902#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003903
3904/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003905/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3906#define _PFA_CTL_1 0x68080
3907#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08003908#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02003909#define PF_PIPE_SEL_MASK_IVB (3<<29)
3910#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08003911#define PF_FILTER_MASK (3<<23)
3912#define PF_FILTER_PROGRAMMED (0<<23)
3913#define PF_FILTER_MED_3x3 (1<<23)
3914#define PF_FILTER_EDGE_ENHANCE (2<<23)
3915#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003916#define _PFA_WIN_SZ 0x68074
3917#define _PFB_WIN_SZ 0x68874
3918#define _PFA_WIN_POS 0x68070
3919#define _PFB_WIN_POS 0x68870
3920#define _PFA_VSCALE 0x68084
3921#define _PFB_VSCALE 0x68884
3922#define _PFA_HSCALE 0x68090
3923#define _PFB_HSCALE 0x68890
3924
3925#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3926#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3927#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3928#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3929#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003930
3931/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003932#define _LGC_PALETTE_A 0x4a000
3933#define _LGC_PALETTE_B 0x4a800
3934#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003935
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003936#define _GAMMA_MODE_A 0x4a480
3937#define _GAMMA_MODE_B 0x4ac80
3938#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3939#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02003940#define GAMMA_MODE_MODE_8BIT (0 << 0)
3941#define GAMMA_MODE_MODE_10BIT (1 << 0)
3942#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003943#define GAMMA_MODE_MODE_SPLIT (3 << 0)
3944
Zhenyu Wangb9055052009-06-05 15:38:38 +08003945/* interrupts */
3946#define DE_MASTER_IRQ_CONTROL (1 << 31)
3947#define DE_SPRITEB_FLIP_DONE (1 << 29)
3948#define DE_SPRITEA_FLIP_DONE (1 << 28)
3949#define DE_PLANEB_FLIP_DONE (1 << 27)
3950#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c22013-10-21 18:04:36 +02003951#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08003952#define DE_PCU_EVENT (1 << 25)
3953#define DE_GTT_FAULT (1 << 24)
3954#define DE_POISON (1 << 23)
3955#define DE_PERFORM_COUNTER (1 << 22)
3956#define DE_PCH_EVENT (1 << 21)
3957#define DE_AUX_CHANNEL_A (1 << 20)
3958#define DE_DP_A_HOTPLUG (1 << 19)
3959#define DE_GSE (1 << 18)
3960#define DE_PIPEB_VBLANK (1 << 15)
3961#define DE_PIPEB_EVEN_FIELD (1 << 14)
3962#define DE_PIPEB_ODD_FIELD (1 << 13)
3963#define DE_PIPEB_LINE_COMPARE (1 << 12)
3964#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003965#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003966#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3967#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c22013-10-21 18:04:36 +02003968#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08003969#define DE_PIPEA_EVEN_FIELD (1 << 6)
3970#define DE_PIPEA_ODD_FIELD (1 << 5)
3971#define DE_PIPEA_LINE_COMPARE (1 << 4)
3972#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003973#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c22013-10-21 18:04:36 +02003974#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08003975#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c22013-10-21 18:04:36 +02003976#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08003977
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003978/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03003979#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003980#define DE_GSE_IVB (1<<29)
3981#define DE_PCH_EVENT_IVB (1<<28)
3982#define DE_DP_A_HOTPLUG_IVB (1<<27)
3983#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01003984#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3985#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3986#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003987#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003988#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003989#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01003990#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3991#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c22013-10-21 18:04:36 +02003992#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003993#define DE_PIPEA_VBLANK_IVB (1<<0)
Paulo Zanonib5184212013-07-12 20:00:08 -03003994#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
3995
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07003996#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
3997#define MASTER_INTERRUPT_ENABLE (1<<31)
3998
Zhenyu Wangb9055052009-06-05 15:38:38 +08003999#define DEISR 0x44000
4000#define DEIMR 0x44004
4001#define DEIIR 0x44008
4002#define DEIER 0x4400c
4003
Zhenyu Wangb9055052009-06-05 15:38:38 +08004004#define GTISR 0x44010
4005#define GTIMR 0x44014
4006#define GTIIR 0x44018
4007#define GTIER 0x4401c
4008
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004009#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07004010/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4011#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004012#define ILK_DPARB_GATE (1<<22)
4013#define ILK_VSDPFD_FULL (1<<21)
Chris Wilson4d302442010-12-14 19:21:29 +00004014#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
4015#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
4016#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
4017#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
4018#define ILK_HDCP_DISABLE (1<<25)
4019#define ILK_eDP_A_DISABLE (1<<24)
4020#define ILK_DESKTOP (1<<23)
Yuanhan Liu13982612010-12-15 15:42:31 +08004021
Damien Lespiau231e54f2012-10-19 17:55:41 +01004022#define ILK_DSPCLK_GATE_D 0x42020
4023#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4024#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4025#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4026#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4027#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004028
Eric Anholt116ac8d2011-12-21 10:31:09 -08004029#define IVB_CHICKEN3 0x4200c
4030# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4031# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4032
Paulo Zanoni90a88642013-05-03 17:23:45 -03004033#define CHICKEN_PAR1_1 0x42080
4034#define FORCE_ARB_IDLE_PLANES (1 << 14)
4035
Zhenyu Wang553bd142009-09-02 10:57:52 +08004036#define DISP_ARB_CTL 0x45000
4037#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004038#define DISP_FBC_WM_DIS (1<<15)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07004039#define GEN7_MSG_CTL 0x45010
4040#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4041#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Zhenyu Wang553bd142009-09-02 10:57:52 +08004042
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004043/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08004044#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4045# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
4046
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004047#define GEN7_L3CNTLREG1 0xB01C
4048#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07004049#define GEN7_L3AGDIS (1<<19)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004050
4051#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4052#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4053
Jesse Barnes61939d92012-10-02 17:43:38 -05004054#define GEN7_L3SQCREG4 0xb034
4055#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4056
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08004057/* WaCatErrorRejectionIssue */
4058#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4059#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4060
Francisco Jerezf3fc4882013-10-02 15:53:16 -07004061#define HSW_SCRATCH1 0xb038
4062#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4063
Paulo Zanoni79f689a2012-10-05 12:05:52 -03004064#define HSW_FUSE_STRAP 0x42014
4065#define HSW_CDCLK_LIMIT (1 << 24)
4066
Zhenyu Wangb9055052009-06-05 15:38:38 +08004067/* PCH */
4068
Adam Jackson23e81d62012-06-06 15:45:44 -04004069/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08004070#define SDE_AUDIO_POWER_D (1 << 27)
4071#define SDE_AUDIO_POWER_C (1 << 26)
4072#define SDE_AUDIO_POWER_B (1 << 25)
4073#define SDE_AUDIO_POWER_SHIFT (25)
4074#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4075#define SDE_GMBUS (1 << 24)
4076#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4077#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4078#define SDE_AUDIO_HDCP_MASK (3 << 22)
4079#define SDE_AUDIO_TRANSB (1 << 21)
4080#define SDE_AUDIO_TRANSA (1 << 20)
4081#define SDE_AUDIO_TRANS_MASK (3 << 20)
4082#define SDE_POISON (1 << 19)
4083/* 18 reserved */
4084#define SDE_FDI_RXB (1 << 17)
4085#define SDE_FDI_RXA (1 << 16)
4086#define SDE_FDI_MASK (3 << 16)
4087#define SDE_AUXD (1 << 15)
4088#define SDE_AUXC (1 << 14)
4089#define SDE_AUXB (1 << 13)
4090#define SDE_AUX_MASK (7 << 13)
4091/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004092#define SDE_CRT_HOTPLUG (1 << 11)
4093#define SDE_PORTD_HOTPLUG (1 << 10)
4094#define SDE_PORTC_HOTPLUG (1 << 9)
4095#define SDE_PORTB_HOTPLUG (1 << 8)
4096#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05004097#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4098 SDE_SDVOB_HOTPLUG | \
4099 SDE_PORTB_HOTPLUG | \
4100 SDE_PORTC_HOTPLUG | \
4101 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08004102#define SDE_TRANSB_CRC_DONE (1 << 5)
4103#define SDE_TRANSB_CRC_ERR (1 << 4)
4104#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4105#define SDE_TRANSA_CRC_DONE (1 << 2)
4106#define SDE_TRANSA_CRC_ERR (1 << 1)
4107#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4108#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04004109
4110/* south display engine interrupt: CPT/PPT */
4111#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4112#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4113#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4114#define SDE_AUDIO_POWER_SHIFT_CPT 29
4115#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4116#define SDE_AUXD_CPT (1 << 27)
4117#define SDE_AUXC_CPT (1 << 26)
4118#define SDE_AUXB_CPT (1 << 25)
4119#define SDE_AUX_MASK_CPT (7 << 25)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004120#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4121#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4122#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04004123#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01004124#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004125#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01004126 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004127 SDE_PORTD_HOTPLUG_CPT | \
4128 SDE_PORTC_HOTPLUG_CPT | \
4129 SDE_PORTB_HOTPLUG_CPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04004130#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03004131#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04004132#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4133#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4134#define SDE_FDI_RXC_CPT (1 << 8)
4135#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4136#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4137#define SDE_FDI_RXB_CPT (1 << 4)
4138#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4139#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4140#define SDE_FDI_RXA_CPT (1 << 0)
4141#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4142 SDE_AUDIO_CP_REQ_B_CPT | \
4143 SDE_AUDIO_CP_REQ_A_CPT)
4144#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4145 SDE_AUDIO_CP_CHG_B_CPT | \
4146 SDE_AUDIO_CP_CHG_A_CPT)
4147#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4148 SDE_FDI_RXB_CPT | \
4149 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004150
4151#define SDEISR 0xc4000
4152#define SDEIMR 0xc4004
4153#define SDEIIR 0xc4008
4154#define SDEIER 0xc400c
4155
Paulo Zanoni86642812013-04-12 17:57:57 -03004156#define SERR_INT 0xc4040
Paulo Zanonide032bf2013-04-12 17:57:58 -03004157#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03004158#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4159#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4160#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Daniel Vetter1dd246f2013-07-10 08:30:23 +02004161#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03004162
Zhenyu Wangb9055052009-06-05 15:38:38 +08004163/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07004164#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004165#define PORTD_HOTPLUG_ENABLE (1 << 20)
4166#define PORTD_PULSE_DURATION_2ms (0)
4167#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4168#define PORTD_PULSE_DURATION_6ms (2 << 18)
4169#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07004170#define PORTD_PULSE_DURATION_MASK (3 << 18)
Damien Lespiaub6965192012-12-13 16:08:59 +00004171#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4172#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4173#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4174#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004175#define PORTC_HOTPLUG_ENABLE (1 << 12)
4176#define PORTC_PULSE_DURATION_2ms (0)
4177#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4178#define PORTC_PULSE_DURATION_6ms (2 << 10)
4179#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07004180#define PORTC_PULSE_DURATION_MASK (3 << 10)
Damien Lespiaub6965192012-12-13 16:08:59 +00004181#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4182#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4183#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4184#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004185#define PORTB_HOTPLUG_ENABLE (1 << 4)
4186#define PORTB_PULSE_DURATION_2ms (0)
4187#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4188#define PORTB_PULSE_DURATION_6ms (2 << 2)
4189#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07004190#define PORTB_PULSE_DURATION_MASK (3 << 2)
Damien Lespiaub6965192012-12-13 16:08:59 +00004191#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4192#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4193#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4194#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004195
4196#define PCH_GPIOA 0xc5010
4197#define PCH_GPIOB 0xc5014
4198#define PCH_GPIOC 0xc5018
4199#define PCH_GPIOD 0xc501c
4200#define PCH_GPIOE 0xc5020
4201#define PCH_GPIOF 0xc5024
4202
Eric Anholtf0217c42009-12-01 11:56:30 -08004203#define PCH_GMBUS0 0xc5100
4204#define PCH_GMBUS1 0xc5104
4205#define PCH_GMBUS2 0xc5108
4206#define PCH_GMBUS3 0xc510c
4207#define PCH_GMBUS4 0xc5110
4208#define PCH_GMBUS5 0xc5120
4209
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004210#define _PCH_DPLL_A 0xc6014
4211#define _PCH_DPLL_B 0xc6018
Daniel Vettere9a632a2013-06-05 13:34:13 +02004212#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004213
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004214#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00004215#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004216#define _PCH_FPA1 0xc6044
4217#define _PCH_FPB0 0xc6048
4218#define _PCH_FPB1 0xc604c
Daniel Vettere9a632a2013-06-05 13:34:13 +02004219#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4220#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004221
4222#define PCH_DPLL_TEST 0xc606c
4223
4224#define PCH_DREF_CONTROL 0xC6200
4225#define DREF_CONTROL_MASK 0x7fc3
4226#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4227#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4228#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4229#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4230#define DREF_SSC_SOURCE_DISABLE (0<<11)
4231#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08004232#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004233#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4234#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4235#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08004236#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004237#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4238#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08004239#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004240#define DREF_SSC4_DOWNSPREAD (0<<6)
4241#define DREF_SSC4_CENTERSPREAD (1<<6)
4242#define DREF_SSC1_DISABLE (0<<1)
4243#define DREF_SSC1_ENABLE (1<<1)
4244#define DREF_SSC4_DISABLE (0)
4245#define DREF_SSC4_ENABLE (1)
4246
4247#define PCH_RAWCLK_FREQ 0xc6204
4248#define FDL_TP1_TIMER_SHIFT 12
4249#define FDL_TP1_TIMER_MASK (3<<12)
4250#define FDL_TP2_TIMER_SHIFT 10
4251#define FDL_TP2_TIMER_MASK (3<<10)
4252#define RAWCLK_FREQ_MASK 0x3ff
4253
4254#define PCH_DPLL_TMR_CFG 0xc6208
4255
4256#define PCH_SSC4_PARMS 0xc6210
4257#define PCH_SSC4_AUX_PARMS 0xc6214
4258
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004259#define PCH_DPLL_SEL 0xc7000
Daniel Vetter11887392013-06-05 13:34:09 +02004260#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4261#define TRANS_DPLLA_SEL(pipe) 0
4262#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004263
Zhenyu Wangb9055052009-06-05 15:38:38 +08004264/* transcoder */
4265
Daniel Vetter275f01b22013-05-03 11:49:47 +02004266#define _PCH_TRANS_HTOTAL_A 0xe0000
4267#define TRANS_HTOTAL_SHIFT 16
4268#define TRANS_HACTIVE_SHIFT 0
4269#define _PCH_TRANS_HBLANK_A 0xe0004
4270#define TRANS_HBLANK_END_SHIFT 16
4271#define TRANS_HBLANK_START_SHIFT 0
4272#define _PCH_TRANS_HSYNC_A 0xe0008
4273#define TRANS_HSYNC_END_SHIFT 16
4274#define TRANS_HSYNC_START_SHIFT 0
4275#define _PCH_TRANS_VTOTAL_A 0xe000c
4276#define TRANS_VTOTAL_SHIFT 16
4277#define TRANS_VACTIVE_SHIFT 0
4278#define _PCH_TRANS_VBLANK_A 0xe0010
4279#define TRANS_VBLANK_END_SHIFT 16
4280#define TRANS_VBLANK_START_SHIFT 0
4281#define _PCH_TRANS_VSYNC_A 0xe0014
4282#define TRANS_VSYNC_END_SHIFT 16
4283#define TRANS_VSYNC_START_SHIFT 0
4284#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08004285
Daniel Vettere3b95f12013-05-03 11:49:49 +02004286#define _PCH_TRANSA_DATA_M1 0xe0030
4287#define _PCH_TRANSA_DATA_N1 0xe0034
4288#define _PCH_TRANSA_DATA_M2 0xe0038
4289#define _PCH_TRANSA_DATA_N2 0xe003c
4290#define _PCH_TRANSA_LINK_M1 0xe0040
4291#define _PCH_TRANSA_LINK_N1 0xe0044
4292#define _PCH_TRANSA_LINK_M2 0xe0048
4293#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08004294
Jesse Barnesb055c8f2011-07-08 11:31:57 -07004295/* Per-transcoder DIP controls */
4296
4297#define _VIDEO_DIP_CTL_A 0xe0200
4298#define _VIDEO_DIP_DATA_A 0xe0208
4299#define _VIDEO_DIP_GCP_A 0xe0210
4300
4301#define _VIDEO_DIP_CTL_B 0xe1200
4302#define _VIDEO_DIP_DATA_B 0xe1208
4303#define _VIDEO_DIP_GCP_B 0xe1210
4304
4305#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4306#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4307#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4308
Ville Syrjäläb9064872013-01-24 15:29:31 +02004309#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4310#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4311#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07004312
Ville Syrjäläb9064872013-01-24 15:29:31 +02004313#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4314#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4315#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07004316
4317#define VLV_TVIDEO_DIP_CTL(pipe) \
4318 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4319#define VLV_TVIDEO_DIP_DATA(pipe) \
4320 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4321#define VLV_TVIDEO_DIP_GCP(pipe) \
4322 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4323
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03004324/* Haswell DIP controls */
4325#define HSW_VIDEO_DIP_CTL_A 0x60200
4326#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4327#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4328#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4329#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4330#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4331#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4332#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4333#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4334#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4335#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4336#define HSW_VIDEO_DIP_GCP_A 0x60210
4337
4338#define HSW_VIDEO_DIP_CTL_B 0x61200
4339#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4340#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4341#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4342#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4343#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4344#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4345#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4346#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4347#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4348#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4349#define HSW_VIDEO_DIP_GCP_B 0x61210
4350
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004351#define HSW_TVIDEO_DIP_CTL(trans) \
4352 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
4353#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4354 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +01004355#define HSW_TVIDEO_DIP_VS_DATA(trans) \
4356 _TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004357#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4358 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
4359#define HSW_TVIDEO_DIP_GCP(trans) \
4360 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
4361#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4362 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03004363
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03004364#define HSW_STEREO_3D_CTL_A 0x70020
4365#define S3D_ENABLE (1<<31)
4366#define HSW_STEREO_3D_CTL_B 0x71020
4367
4368#define HSW_STEREO_3D_CTL(trans) \
4369 _TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A)
4370
Daniel Vetter275f01b22013-05-03 11:49:47 +02004371#define _PCH_TRANS_HTOTAL_B 0xe1000
4372#define _PCH_TRANS_HBLANK_B 0xe1004
4373#define _PCH_TRANS_HSYNC_B 0xe1008
4374#define _PCH_TRANS_VTOTAL_B 0xe100c
4375#define _PCH_TRANS_VBLANK_B 0xe1010
4376#define _PCH_TRANS_VSYNC_B 0xe1014
4377#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08004378
Daniel Vetter275f01b22013-05-03 11:49:47 +02004379#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4380#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4381#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4382#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4383#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4384#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4385#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4386 _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01004387
Daniel Vettere3b95f12013-05-03 11:49:49 +02004388#define _PCH_TRANSB_DATA_M1 0xe1030
4389#define _PCH_TRANSB_DATA_N1 0xe1034
4390#define _PCH_TRANSB_DATA_M2 0xe1038
4391#define _PCH_TRANSB_DATA_N2 0xe103c
4392#define _PCH_TRANSB_LINK_M1 0xe1040
4393#define _PCH_TRANSB_LINK_N1 0xe1044
4394#define _PCH_TRANSB_LINK_M2 0xe1048
4395#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08004396
Daniel Vettere3b95f12013-05-03 11:49:49 +02004397#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4398#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4399#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4400#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4401#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4402#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4403#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4404#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004405
Daniel Vetterab9412b2013-05-03 11:49:46 +02004406#define _PCH_TRANSACONF 0xf0008
4407#define _PCH_TRANSBCONF 0xf1008
4408#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4409#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004410#define TRANS_DISABLE (0<<31)
4411#define TRANS_ENABLE (1<<31)
4412#define TRANS_STATE_MASK (1<<30)
4413#define TRANS_STATE_DISABLE (0<<30)
4414#define TRANS_STATE_ENABLE (1<<30)
4415#define TRANS_FSYNC_DELAY_HB1 (0<<27)
4416#define TRANS_FSYNC_DELAY_HB2 (1<<27)
4417#define TRANS_FSYNC_DELAY_HB3 (2<<27)
4418#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02004419#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004420#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02004421#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02004422#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004423#define TRANS_8BPC (0<<5)
4424#define TRANS_10BPC (1<<5)
4425#define TRANS_6BPC (2<<5)
4426#define TRANS_12BPC (3<<5)
4427
Daniel Vetterce401412012-10-31 22:52:30 +01004428#define _TRANSA_CHICKEN1 0xf0060
4429#define _TRANSB_CHICKEN1 0xf1060
4430#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4431#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07004432#define _TRANSA_CHICKEN2 0xf0064
4433#define _TRANSB_CHICKEN2 0xf1064
4434#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03004435#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4436#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4437#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4438#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4439#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07004440
Jesse Barnes291427f2011-07-29 12:42:37 -07004441#define SOUTH_CHICKEN1 0xc2000
4442#define FDIA_PHASE_SYNC_SHIFT_OVR 19
4443#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02004444#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4445#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4446#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jesse Barnes645c62a2011-05-11 09:49:31 -07004447#define SOUTH_CHICKEN2 0xc2004
Paulo Zanonidde86e22012-12-01 12:04:25 -02004448#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4449#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4450#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07004451
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004452#define _FDI_RXA_CHICKEN 0xc200c
4453#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08004454#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4455#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004456#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004457
Jesse Barnes382b0932010-10-07 16:01:25 -07004458#define SOUTH_DSPCLK_GATE_D 0xc2020
Jesse Barnescd664072013-10-02 10:34:19 -07004459#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07004460#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07004461#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02004462#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07004463
Zhenyu Wangb9055052009-06-05 15:38:38 +08004464/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004465#define _FDI_TXA_CTL 0x60100
4466#define _FDI_TXB_CTL 0x61100
4467#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004468#define FDI_TX_DISABLE (0<<31)
4469#define FDI_TX_ENABLE (1<<31)
4470#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4471#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4472#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4473#define FDI_LINK_TRAIN_NONE (3<<28)
4474#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4475#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4476#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4477#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4478#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4479#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4480#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4481#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004482/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4483 SNB has different settings. */
4484/* SNB A-stepping */
4485#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4486#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4487#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4488#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4489/* SNB B-stepping */
4490#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4491#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4492#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4493#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4494#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02004495#define FDI_DP_PORT_WIDTH_SHIFT 19
4496#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4497#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004498#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004499/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004500#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07004501
4502/* Ivybridge has different bits for lolz */
4503#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4504#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4505#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4506#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4507
Zhenyu Wangb9055052009-06-05 15:38:38 +08004508/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07004509#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07004510#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004511#define FDI_SCRAMBLING_ENABLE (0<<7)
4512#define FDI_SCRAMBLING_DISABLE (1<<7)
4513
4514/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004515#define _FDI_RXA_CTL 0xf000c
4516#define _FDI_RXB_CTL 0xf100c
4517#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004518#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004519/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07004520#define FDI_FS_ERRC_ENABLE (1<<27)
4521#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02004522#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004523#define FDI_8BPC (0<<16)
4524#define FDI_10BPC (1<<16)
4525#define FDI_6BPC (2<<16)
4526#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00004527#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004528#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4529#define FDI_RX_PLL_ENABLE (1<<13)
4530#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4531#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4532#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4533#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4534#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01004535#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004536/* CPT */
4537#define FDI_AUTO_TRAINING (1<<10)
4538#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4539#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4540#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4541#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4542#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004543
Paulo Zanoni04945642012-11-01 21:00:59 -02004544#define _FDI_RXA_MISC 0xf0010
4545#define _FDI_RXB_MISC 0xf1010
4546#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4547#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4548#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4549#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4550#define FDI_RX_TP1_TO_TP2_48 (2<<20)
4551#define FDI_RX_TP1_TO_TP2_64 (3<<20)
4552#define FDI_RX_FDI_DELAY_90 (0x90<<0)
4553#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4554
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004555#define _FDI_RXA_TUSIZE1 0xf0030
4556#define _FDI_RXA_TUSIZE2 0xf0038
4557#define _FDI_RXB_TUSIZE1 0xf1030
4558#define _FDI_RXB_TUSIZE2 0xf1038
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004559#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4560#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004561
4562/* FDI_RX interrupt register format */
4563#define FDI_RX_INTER_LANE_ALIGN (1<<10)
4564#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
4565#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
4566#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4567#define FDI_RX_FS_CODE_ERR (1<<6)
4568#define FDI_RX_FE_CODE_ERR (1<<5)
4569#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4570#define FDI_RX_HDCP_LINK_FAIL (1<<3)
4571#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4572#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4573#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4574
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004575#define _FDI_RXA_IIR 0xf0014
4576#define _FDI_RXA_IMR 0xf0018
4577#define _FDI_RXB_IIR 0xf1014
4578#define _FDI_RXB_IMR 0xf1018
4579#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4580#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004581
4582#define FDI_PLL_CTL_1 0xfe000
4583#define FDI_PLL_CTL_2 0xfe004
4584
Zhenyu Wangb9055052009-06-05 15:38:38 +08004585#define PCH_LVDS 0xe1180
4586#define LVDS_DETECTED (1 << 1)
4587
Shobhit Kumar98364372012-06-15 11:55:14 -07004588/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02004589#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4590#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4591#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Jani Nikulaa24c1442013-09-05 16:44:46 +03004592#define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
4593#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02004594#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4595#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07004596
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02004597#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4598#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4599#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4600#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4601#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07004602
Jesse Barnes453c5422013-03-28 09:55:41 -07004603#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4604#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4605#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4606 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4607#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4608 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4609#define VLV_PIPE_PP_DIVISOR(pipe) \
4610 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4611
Zhenyu Wangb9055052009-06-05 15:38:38 +08004612#define PCH_PP_STATUS 0xc7200
4613#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07004614#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07004615#define PANEL_UNLOCK_MASK (0xffff << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004616#define EDP_FORCE_VDD (1 << 3)
4617#define EDP_BLC_ENABLE (1 << 2)
4618#define PANEL_POWER_RESET (1 << 1)
4619#define PANEL_POWER_OFF (0 << 0)
4620#define PANEL_POWER_ON (1 << 0)
4621#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07004622#define PANEL_PORT_SELECT_MASK (3 << 30)
4623#define PANEL_PORT_SELECT_LVDS (0 << 30)
4624#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07004625#define PANEL_PORT_SELECT_DPC (2 << 30)
4626#define PANEL_PORT_SELECT_DPD (3 << 30)
4627#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4628#define PANEL_POWER_UP_DELAY_SHIFT 16
4629#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4630#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4631
Zhenyu Wangb9055052009-06-05 15:38:38 +08004632#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07004633#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4634#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4635#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4636#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4637
Zhenyu Wangb9055052009-06-05 15:38:38 +08004638#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07004639#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4640#define PP_REFERENCE_DIVIDER_SHIFT 8
4641#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4642#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004643
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004644#define PCH_DP_B 0xe4100
4645#define PCH_DPB_AUX_CH_CTL 0xe4110
4646#define PCH_DPB_AUX_CH_DATA1 0xe4114
4647#define PCH_DPB_AUX_CH_DATA2 0xe4118
4648#define PCH_DPB_AUX_CH_DATA3 0xe411c
4649#define PCH_DPB_AUX_CH_DATA4 0xe4120
4650#define PCH_DPB_AUX_CH_DATA5 0xe4124
4651
4652#define PCH_DP_C 0xe4200
4653#define PCH_DPC_AUX_CH_CTL 0xe4210
4654#define PCH_DPC_AUX_CH_DATA1 0xe4214
4655#define PCH_DPC_AUX_CH_DATA2 0xe4218
4656#define PCH_DPC_AUX_CH_DATA3 0xe421c
4657#define PCH_DPC_AUX_CH_DATA4 0xe4220
4658#define PCH_DPC_AUX_CH_DATA5 0xe4224
4659
4660#define PCH_DP_D 0xe4300
4661#define PCH_DPD_AUX_CH_CTL 0xe4310
4662#define PCH_DPD_AUX_CH_DATA1 0xe4314
4663#define PCH_DPD_AUX_CH_DATA2 0xe4318
4664#define PCH_DPD_AUX_CH_DATA3 0xe431c
4665#define PCH_DPD_AUX_CH_DATA4 0xe4320
4666#define PCH_DPD_AUX_CH_DATA5 0xe4324
4667
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004668/* CPT */
4669#define PORT_TRANS_A_SEL_CPT 0
4670#define PORT_TRANS_B_SEL_CPT (1<<29)
4671#define PORT_TRANS_C_SEL_CPT (2<<29)
4672#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07004673#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02004674#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4675#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004676
4677#define TRANS_DP_CTL_A 0xe0300
4678#define TRANS_DP_CTL_B 0xe1300
4679#define TRANS_DP_CTL_C 0xe2300
Daniel Vetter23670b322012-11-01 09:15:30 +01004680#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004681#define TRANS_DP_OUTPUT_ENABLE (1<<31)
4682#define TRANS_DP_PORT_SEL_B (0<<29)
4683#define TRANS_DP_PORT_SEL_C (1<<29)
4684#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08004685#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004686#define TRANS_DP_PORT_SEL_MASK (3<<29)
4687#define TRANS_DP_AUDIO_ONLY (1<<26)
4688#define TRANS_DP_ENH_FRAMING (1<<18)
4689#define TRANS_DP_8BPC (0<<9)
4690#define TRANS_DP_10BPC (1<<9)
4691#define TRANS_DP_6BPC (2<<9)
4692#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08004693#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004694#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4695#define TRANS_DP_VSYNC_ACTIVE_LOW 0
4696#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4697#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01004698#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004699
4700/* SNB eDP training params */
4701/* SNB A-stepping */
4702#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4703#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4704#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4705#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4706/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08004707#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4708#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4709#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4710#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4711#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004712#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4713
Keith Packard1a2eb462011-11-16 16:26:07 -08004714/* IVB */
4715#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4716#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4717#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4718#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4719#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4720#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03004721#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08004722
4723/* legacy values */
4724#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4725#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4726#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4727#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4728#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4729
4730#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4731
Zou Nan haicae58522010-11-09 17:17:32 +08004732#define FORCEWAKE 0xA18C
Jesse Barnes575155a2012-03-28 13:39:37 -07004733#define FORCEWAKE_VLV 0x1300b0
4734#define FORCEWAKE_ACK_VLV 0x1300b4
Jesse Barnesed5de392013-03-08 10:45:57 -08004735#define FORCEWAKE_MEDIA_VLV 0x1300b8
4736#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
Eugeni Dodonove7911c42012-07-02 11:51:04 -03004737#define FORCEWAKE_ACK_HSW 0x130044
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00004738#define FORCEWAKE_ACK 0x130090
Jesse Barnesd62b4892013-03-08 10:45:53 -08004739#define VLV_GTLC_WAKE_CTRL 0x130090
4740#define VLV_GTLC_PW_STATUS 0x130094
Keith Packard8d715f02011-11-18 20:39:01 -08004741#define FORCEWAKE_MT 0xa188 /* multi-threaded */
Chris Wilsonc5836c22012-10-17 12:09:55 +01004742#define FORCEWAKE_KERNEL 0x1
4743#define FORCEWAKE_USER 0x2
Keith Packard8d715f02011-11-18 20:39:01 -08004744#define FORCEWAKE_MT_ACK 0x130040
4745#define ECOBUS 0xa180
4746#define FORCEWAKE_MT_ENABLE (1<<5)
Chris Wilson8fd26852010-12-08 18:40:43 +00004747
Ben Widawskydd202c62012-02-09 10:15:18 +01004748#define GTFIFODBG 0x120000
4749#define GT_FIFO_CPU_ERROR_MASK 7
4750#define GT_FIFO_OVFERR (1<<2)
4751#define GT_FIFO_IAWRERR (1<<1)
4752#define GT_FIFO_IARDERR (1<<0)
4753
Chris Wilson91355832011-03-04 19:22:40 +00004754#define GT_FIFO_FREE_ENTRIES 0x120008
Chris Wilson957367202011-05-12 22:17:09 +01004755#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Chris Wilson91355832011-03-04 19:22:40 +00004756
Ben Widawsky05e21cc2013-07-04 11:02:04 -07004757#define HSW_IDICR 0x9008
4758#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4759#define HSW_EDRAM_PRESENT 0x120010
4760
Daniel Vetter80e829f2012-03-31 11:21:57 +02004761#define GEN6_UCGCTL1 0x9400
4762# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02004763# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02004764
Eric Anholt406478d2011-11-07 16:07:04 -08004765#define GEN6_UCGCTL2 0x9404
Jesse Barnes0f846f82012-06-14 11:04:47 -07004766# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07004767# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08004768# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08004769# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08004770# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08004771
Jesse Barnese3f33d42012-06-14 11:04:50 -07004772#define GEN7_UCGCTL4 0x940c
4773#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4774
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08004775#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00004776#define GEN6_TURBO_DISABLE (1<<31)
4777#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03004778#define HSW_FREQUENCY(x) ((x)<<24)
Chris Wilson8fd26852010-12-08 18:40:43 +00004779#define GEN6_OFFSET(x) ((x)<<19)
4780#define GEN6_AGGRESSIVE_TURBO (0<<15)
4781#define GEN6_RC_VIDEO_FREQ 0xA00C
4782#define GEN6_RC_CONTROL 0xA090
4783#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4784#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4785#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4786#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4787#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes0a073b82013-04-17 15:54:58 -07004788#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00004789#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4790#define GEN6_RC_CTL_HW_ENABLE (1<<31)
4791#define GEN6_RP_DOWN_TIMEOUT 0xA010
4792#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08004793#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08004794#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08004795#define HSW_CAGF_SHIFT 7
Jesse Barnesccab5c82011-01-18 15:49:25 -08004796#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08004797#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00004798#define GEN6_RP_CONTROL 0xA024
4799#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08004800#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4801#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4802#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4803#define GEN6_RP_MEDIA_HW_MODE (1<<9)
4804#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00004805#define GEN6_RP_MEDIA_IS_GFX (1<<8)
4806#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08004807#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4808#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4809#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01004810#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08004811#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00004812#define GEN6_RP_UP_THRESHOLD 0xA02C
4813#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08004814#define GEN6_RP_CUR_UP_EI 0xA050
4815#define GEN6_CURICONT_MASK 0xffffff
4816#define GEN6_RP_CUR_UP 0xA054
4817#define GEN6_CURBSYTAVG_MASK 0xffffff
4818#define GEN6_RP_PREV_UP 0xA058
4819#define GEN6_RP_CUR_DOWN_EI 0xA05C
4820#define GEN6_CURIAVG_MASK 0xffffff
4821#define GEN6_RP_CUR_DOWN 0xA060
4822#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00004823#define GEN6_RP_UP_EI 0xA068
4824#define GEN6_RP_DOWN_EI 0xA06C
4825#define GEN6_RP_IDLE_HYSTERSIS 0xA070
4826#define GEN6_RC_STATE 0xA094
4827#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4828#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4829#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4830#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4831#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4832#define GEN6_RC_SLEEP 0xA0B0
4833#define GEN6_RC1e_THRESHOLD 0xA0B4
4834#define GEN6_RC6_THRESHOLD 0xA0B8
4835#define GEN6_RC6p_THRESHOLD 0xA0BC
4836#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08004837#define GEN6_PMINTRMSK 0xA168
Chris Wilson8fd26852010-12-08 18:40:43 +00004838
4839#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07004840#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00004841#define GEN6_PMIIR 0x44028
4842#define GEN6_PMIER 0x4402C
4843#define GEN6_PM_MBOX_EVENT (1<<25)
4844#define GEN6_PM_THERMAL_EVENT (1<<24)
4845#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4846#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4847#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4848#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4849#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07004850#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07004851 GEN6_PM_RP_DOWN_THRESHOLD | \
4852 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00004853
Ben Widawskycce66a22012-03-27 18:59:38 -07004854#define GEN6_GT_GFX_RC6_LOCKED 0x138104
Jesse Barnes49798eb2013-09-26 17:55:57 -07004855#define VLV_COUNTER_CONTROL 0x138104
4856#define VLV_COUNT_RANGE_HIGH (1<<15)
4857#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
4858#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ben Widawskycce66a22012-03-27 18:59:38 -07004859#define GEN6_GT_GFX_RC6 0x138108
4860#define GEN6_GT_GFX_RC6p 0x13810C
4861#define GEN6_GT_GFX_RC6pp 0x138110
4862
Chris Wilson8fd26852010-12-08 18:40:43 +00004863#define GEN6_PCODE_MAILBOX 0x138124
4864#define GEN6_PCODE_READY (1<<31)
Jesse Barnesa6044e22010-12-20 11:34:20 -08004865#define GEN6_READ_OC_PARAMS 0xc
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07004866#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4867#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
Ben Widawsky31643d52012-09-26 10:34:01 -07004868#define GEN6_PCODE_WRITE_RC6VIDS 0x4
4869#define GEN6_PCODE_READ_RC6VIDS 0x5
Paulo Zanoni515b2392013-09-10 19:36:37 -03004870#define GEN6_PCODE_READ_D_COMP 0x10
4871#define GEN6_PCODE_WRITE_D_COMP 0x11
Ben Widawsky7083e052013-02-01 16:41:14 -08004872#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
4873#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Chris Wilson8fd26852010-12-08 18:40:43 +00004874#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07004875#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01004876#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Chris Wilson8fd26852010-12-08 18:40:43 +00004877
Ben Widawsky4d855292011-12-12 19:34:16 -08004878#define GEN6_GT_CORE_STATUS 0x138060
4879#define GEN6_CORE_CPD_STATE_MASK (7<<4)
4880#define GEN6_RCn_MASK 7
4881#define GEN6_RC0 0
4882#define GEN6_RC3 2
4883#define GEN6_RC6 3
4884#define GEN6_RC7 4
4885
Ben Widawskye3689192012-05-25 16:56:22 -07004886#define GEN7_MISCCPCTL (0x9424)
4887#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4888
4889/* IVYBRIDGE DPF */
4890#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07004891#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07004892#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4893#define GEN7_PARITY_ERROR_VALID (1<<13)
4894#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4895#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4896#define GEN7_PARITY_ERROR_ROW(reg) \
4897 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4898#define GEN7_PARITY_ERROR_BANK(reg) \
4899 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4900#define GEN7_PARITY_ERROR_SUBBANK(reg) \
4901 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4902#define GEN7_L3CDERRST1_ENABLE (1<<7)
4903
Ben Widawskyb9524a12012-05-25 16:56:24 -07004904#define GEN7_L3LOG_BASE 0xB070
Ben Widawsky35a85ac2013-09-19 11:13:41 -07004905#define HSW_L3LOG_BASE_SLICE1 0xB270
Ben Widawskyb9524a12012-05-25 16:56:24 -07004906#define GEN7_L3LOG_SIZE 0x80
4907
Jesse Barnes12f33822012-10-25 12:15:45 -07004908#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
4909#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
4910#define GEN7_MAX_PS_THREAD_DEP (8<<12)
4911#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
4912
Jesse Barnes8ab43972012-10-25 12:15:42 -07004913#define GEN7_ROW_CHICKEN2 0xe4f4
4914#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4915#define DOP_CLOCK_GATING_DISABLE (1<<0)
4916
Francisco Jerezf3fc4882013-10-02 15:53:16 -07004917#define HSW_ROW_CHICKEN3 0xe49c
4918#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
4919
Ville Syrjäläf4ba9f82013-01-24 15:29:29 +02004920#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
Wu Fengguange0dac652011-09-05 14:25:34 +08004921#define INTEL_AUDIO_DEVCL 0x808629FB
4922#define INTEL_AUDIO_DEVBLC 0x80862801
4923#define INTEL_AUDIO_DEVCTG 0x80862802
4924
4925#define G4X_AUD_CNTL_ST 0x620B4
4926#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
4927#define G4X_ELDV_DEVCTG (1 << 14)
4928#define G4X_ELD_ADDR (0xf << 5)
4929#define G4X_ELD_ACK (1 << 4)
4930#define G4X_HDMIW_HDMIEDID 0x6210C
4931
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004932#define IBX_HDMIW_HDMIEDID_A 0xE2050
Wang Xingchao9b138a82012-08-09 16:52:18 +08004933#define IBX_HDMIW_HDMIEDID_B 0xE2150
4934#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4935 IBX_HDMIW_HDMIEDID_A, \
4936 IBX_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004937#define IBX_AUD_CNTL_ST_A 0xE20B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08004938#define IBX_AUD_CNTL_ST_B 0xE21B4
4939#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4940 IBX_AUD_CNTL_ST_A, \
4941 IBX_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004942#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
4943#define IBX_ELD_ADDRESS (0x1f << 5)
4944#define IBX_ELD_ACK (1 << 4)
4945#define IBX_AUD_CNTL_ST2 0xE20C0
4946#define IBX_ELD_VALIDB (1 << 0)
4947#define IBX_CP_READYB (1 << 1)
Wu Fengguange0dac652011-09-05 14:25:34 +08004948
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004949#define CPT_HDMIW_HDMIEDID_A 0xE5050
Wang Xingchao9b138a82012-08-09 16:52:18 +08004950#define CPT_HDMIW_HDMIEDID_B 0xE5150
4951#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4952 CPT_HDMIW_HDMIEDID_A, \
4953 CPT_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004954#define CPT_AUD_CNTL_ST_A 0xE50B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08004955#define CPT_AUD_CNTL_ST_B 0xE51B4
4956#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4957 CPT_AUD_CNTL_ST_A, \
4958 CPT_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08004959#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08004960
Eric Anholtae662d32012-01-03 09:23:29 -08004961/* These are the 4 32-bit write offset registers for each stream
4962 * output buffer. It determines the offset from the
4963 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4964 */
4965#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
4966
Wu Fengguangb6daa022012-01-06 14:41:31 -06004967#define IBX_AUD_CONFIG_A 0xe2000
Wang Xingchao9b138a82012-08-09 16:52:18 +08004968#define IBX_AUD_CONFIG_B 0xe2100
4969#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4970 IBX_AUD_CONFIG_A, \
4971 IBX_AUD_CONFIG_B)
Wu Fengguangb6daa022012-01-06 14:41:31 -06004972#define CPT_AUD_CONFIG_A 0xe5000
Wang Xingchao9b138a82012-08-09 16:52:18 +08004973#define CPT_AUD_CONFIG_B 0xe5100
4974#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4975 CPT_AUD_CONFIG_A, \
4976 CPT_AUD_CONFIG_B)
Wu Fengguangb6daa022012-01-06 14:41:31 -06004977#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
4978#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
4979#define AUD_CONFIG_UPPER_N_SHIFT 20
4980#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
4981#define AUD_CONFIG_LOWER_N_SHIFT 4
4982#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
4983#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03004984#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
4985#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
4986#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
4987#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
4988#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
4989#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
4990#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
4991#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
4992#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
4993#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
4994#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06004995#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
4996
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08004997/* HSW Audio */
4998#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
4999#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5000#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5001 HSW_AUD_CONFIG_A, \
5002 HSW_AUD_CONFIG_B)
5003
5004#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5005#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5006#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5007 HSW_AUD_MISC_CTRL_A, \
5008 HSW_AUD_MISC_CTRL_B)
5009
5010#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5011#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5012#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5013 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5014 HSW_AUD_DIP_ELD_CTRL_ST_B)
5015
5016/* Audio Digital Converter */
5017#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5018#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5019#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5020 HSW_AUD_DIG_CNVT_1, \
5021 HSW_AUD_DIG_CNVT_2)
Wang Xingchao9b138a82012-08-09 16:52:18 +08005022#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08005023
5024#define HSW_AUD_EDID_DATA_A 0x65050
5025#define HSW_AUD_EDID_DATA_B 0x65150
5026#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5027 HSW_AUD_EDID_DATA_A, \
5028 HSW_AUD_EDID_DATA_B)
5029
5030#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5031#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5032#define AUDIO_INACTIVE_C (1<<11)
5033#define AUDIO_INACTIVE_B (1<<7)
5034#define AUDIO_INACTIVE_A (1<<3)
5035#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5036#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5037#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5038#define AUDIO_ELD_VALID_A (1<<0)
5039#define AUDIO_ELD_VALID_B (1<<4)
5040#define AUDIO_ELD_VALID_C (1<<8)
5041#define AUDIO_CP_READY_A (1<<1)
5042#define AUDIO_CP_READY_B (1<<5)
5043#define AUDIO_CP_READY_C (1<<9)
5044
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005045/* HSW Power Wells */
Paulo Zanonifa42e232013-01-25 16:59:11 -02005046#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5047#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5048#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5049#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03005050#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5051#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005052#define HSW_PWR_WELL_CTL5 0x45410
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005053#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5054#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005055#define HSW_PWR_WELL_FORCE_ON (1<<19)
5056#define HSW_PWR_WELL_CTL6 0x45414
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005057
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005058/* Per-pipe DDI Function Control */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005059#define TRANS_DDI_FUNC_CTL_A 0x60400
5060#define TRANS_DDI_FUNC_CTL_B 0x61400
5061#define TRANS_DDI_FUNC_CTL_C 0x62400
5062#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
5063#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
5064 TRANS_DDI_FUNC_CTL_B)
5065#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005066/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005067#define TRANS_DDI_PORT_MASK (7<<28)
5068#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5069#define TRANS_DDI_PORT_NONE (0<<28)
5070#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5071#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5072#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5073#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5074#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5075#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5076#define TRANS_DDI_BPC_MASK (7<<20)
5077#define TRANS_DDI_BPC_8 (0<<20)
5078#define TRANS_DDI_BPC_10 (1<<20)
5079#define TRANS_DDI_BPC_6 (2<<20)
5080#define TRANS_DDI_BPC_12 (3<<20)
5081#define TRANS_DDI_PVSYNC (1<<17)
5082#define TRANS_DDI_PHSYNC (1<<16)
5083#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5084#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5085#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5086#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5087#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5088#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005089
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005090/* DisplayPort Transport Control */
5091#define DP_TP_CTL_A 0x64040
5092#define DP_TP_CTL_B 0x64140
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005093#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5094#define DP_TP_CTL_ENABLE (1<<31)
5095#define DP_TP_CTL_MODE_SST (0<<27)
5096#define DP_TP_CTL_MODE_MST (1<<27)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005097#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005098#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005099#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5100#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5101#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005102#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5103#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005104#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005105#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005106
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005107/* DisplayPort Transport Status */
5108#define DP_TP_STATUS_A 0x64044
5109#define DP_TP_STATUS_B 0x64144
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005110#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005111#define DP_TP_STATUS_IDLE_DONE (1<<25)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005112#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5113
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005114/* DDI Buffer Control */
5115#define DDI_BUF_CTL_A 0x64000
5116#define DDI_BUF_CTL_B 0x64100
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005117#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5118#define DDI_BUF_CTL_ENABLE (1<<31)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005119#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005120#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005121#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005122#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005123#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005124#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005125#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5126#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005127#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
5128#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00005129#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005130#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02005131#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02005132#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005133#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5134
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005135/* DDI Buffer Translations */
5136#define DDI_BUF_TRANS_A 0x64E00
5137#define DDI_BUF_TRANS_B 0x64E60
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005138#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005139
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005140/* Sideband Interface (SBI) is programmed indirectly, via
5141 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5142 * which contains the payload */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005143#define SBI_ADDR 0xC6000
5144#define SBI_DATA 0xC6004
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005145#define SBI_CTL_STAT 0xC6008
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02005146#define SBI_CTL_DEST_ICLK (0x0<<16)
5147#define SBI_CTL_DEST_MPHY (0x1<<16)
5148#define SBI_CTL_OP_IORD (0x2<<8)
5149#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005150#define SBI_CTL_OP_CRRD (0x6<<8)
5151#define SBI_CTL_OP_CRWR (0x7<<8)
5152#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005153#define SBI_RESPONSE_SUCCESS (0x0<<1)
5154#define SBI_BUSY (0x1<<0)
5155#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005156
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005157/* SBI offsets */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005158#define SBI_SSCDIVINTPHASE6 0x0600
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005159#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5160#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5161#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5162#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005163#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005164#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005165#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005166#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02005167#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005168#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005169#define SBI_SSCAUXDIV6 0x0610
5170#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005171#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005172#define SBI_GEN0 0x1f00
5173#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005174
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005175/* LPT PIXCLK_GATE */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005176#define PIXCLK_GATE 0xC6020
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03005177#define PIXCLK_GATE_UNGATE (1<<0)
5178#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005179
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005180/* SPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005181#define SPLL_CTL 0x46020
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005182#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01005183#define SPLL_PLL_SSC (1<<28)
5184#define SPLL_PLL_NON_SSC (2<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005185#define SPLL_PLL_FREQ_810MHz (0<<26)
5186#define SPLL_PLL_FREQ_1350MHz (1<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005187
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005188/* WRPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005189#define WRPLL_CTL1 0x46040
5190#define WRPLL_CTL2 0x46060
5191#define WRPLL_PLL_ENABLE (1<<31)
5192#define WRPLL_PLL_SELECT_SSC (0x01<<28)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01005193#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005194#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03005195/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005196#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
5197#define WRPLL_DIVIDER_POST(x) ((x)<<8)
5198#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005199
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005200/* Port clock selection */
5201#define PORT_CLK_SEL_A 0x46100
5202#define PORT_CLK_SEL_B 0x46104
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005203#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005204#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5205#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5206#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005207#define PORT_CLK_SEL_SPLL (3<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005208#define PORT_CLK_SEL_WRPLL1 (4<<29)
5209#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005210#define PORT_CLK_SEL_NONE (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005211
Paulo Zanonibb523fc2012-10-23 18:29:56 -02005212/* Transcoder clock selection */
5213#define TRANS_CLK_SEL_A 0x46140
5214#define TRANS_CLK_SEL_B 0x46144
5215#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5216/* For each transcoder, we need to select the corresponding port clock */
5217#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5218#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005219
Paulo Zanonic9809792012-10-23 18:30:00 -02005220#define _TRANSA_MSA_MISC 0x60410
5221#define _TRANSB_MSA_MISC 0x61410
5222#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
5223 _TRANSB_MSA_MISC)
5224#define TRANS_MSA_SYNC_CLK (1<<0)
5225#define TRANS_MSA_6_BPC (0<<5)
5226#define TRANS_MSA_8_BPC (1<<5)
5227#define TRANS_MSA_10_BPC (2<<5)
5228#define TRANS_MSA_12_BPC (3<<5)
5229#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03005230
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005231/* LCPLL Control */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005232#define LCPLL_CTL 0x130040
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005233#define LCPLL_PLL_DISABLE (1<<31)
5234#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03005235#define LCPLL_CLK_FREQ_MASK (3<<26)
5236#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005237#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005238#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005239#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03005240#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005241#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5242
5243#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5244#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5245#define D_COMP_COMP_FORCE (1<<8)
5246#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005247
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03005248/* Pipe WM_LINETIME - watermark line time */
5249#define PIPE_WM_LINETIME_A 0x45270
5250#define PIPE_WM_LINETIME_B 0x45274
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005251#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5252 PIPE_WM_LINETIME_B)
5253#define PIPE_WM_LINETIME_MASK (0x1ff)
5254#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03005255#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005256#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03005257
5258/* SFUSE_STRAP */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005259#define SFUSE_STRAP 0xc2014
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03005260#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5261#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5262#define SFUSE_STRAP_DDID_DETECTED (1<<0)
5263
Paulo Zanoni801bcff2013-05-31 10:08:35 -03005264#define WM_MISC 0x45260
5265#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5266
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03005267#define WM_DBG 0x45280
5268#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5269#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5270#define WM_DBG_DISALLOW_SPRITE (1<<2)
5271
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005272/* pipe CSC */
5273#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5274#define _PIPE_A_CSC_COEFF_BY 0x49014
5275#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5276#define _PIPE_A_CSC_COEFF_BU 0x4901c
5277#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5278#define _PIPE_A_CSC_COEFF_BV 0x49024
5279#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03005280#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5281#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5282#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005283#define _PIPE_A_CSC_PREOFF_HI 0x49030
5284#define _PIPE_A_CSC_PREOFF_ME 0x49034
5285#define _PIPE_A_CSC_PREOFF_LO 0x49038
5286#define _PIPE_A_CSC_POSTOFF_HI 0x49040
5287#define _PIPE_A_CSC_POSTOFF_ME 0x49044
5288#define _PIPE_A_CSC_POSTOFF_LO 0x49048
5289
5290#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5291#define _PIPE_B_CSC_COEFF_BY 0x49114
5292#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5293#define _PIPE_B_CSC_COEFF_BU 0x4911c
5294#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5295#define _PIPE_B_CSC_COEFF_BV 0x49124
5296#define _PIPE_B_CSC_MODE 0x49128
5297#define _PIPE_B_CSC_PREOFF_HI 0x49130
5298#define _PIPE_B_CSC_PREOFF_ME 0x49134
5299#define _PIPE_B_CSC_PREOFF_LO 0x49138
5300#define _PIPE_B_CSC_POSTOFF_HI 0x49140
5301#define _PIPE_B_CSC_POSTOFF_ME 0x49144
5302#define _PIPE_B_CSC_POSTOFF_LO 0x49148
5303
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005304#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5305#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5306#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5307#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5308#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5309#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5310#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5311#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5312#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5313#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5314#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5315#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5316#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5317
Jani Nikula3230bf12013-08-27 15:12:16 +03005318/* VLV MIPI registers */
5319
5320#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
5321#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
5322#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
5323#define DPI_ENABLE (1 << 31) /* A + B */
5324#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
5325#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
5326#define DUAL_LINK_MODE_MASK (1 << 26)
5327#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
5328#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
5329#define DITHERING_ENABLE (1 << 25) /* A + B */
5330#define FLOPPED_HSTX (1 << 23)
5331#define DE_INVERT (1 << 19) /* XXX */
5332#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
5333#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
5334#define AFE_LATCHOUT (1 << 17)
5335#define LP_OUTPUT_HOLD (1 << 16)
5336#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
5337#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
5338#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
5339#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
5340#define CSB_SHIFT 9
5341#define CSB_MASK (3 << 9)
5342#define CSB_20MHZ (0 << 9)
5343#define CSB_10MHZ (1 << 9)
5344#define CSB_40MHZ (2 << 9)
5345#define BANDGAP_MASK (1 << 8)
5346#define BANDGAP_PNW_CIRCUIT (0 << 8)
5347#define BANDGAP_LNC_CIRCUIT (1 << 8)
5348#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
5349#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
5350#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
5351#define TEARING_EFFECT_SHIFT 2 /* A + B */
5352#define TEARING_EFFECT_MASK (3 << 2)
5353#define TEARING_EFFECT_OFF (0 << 2)
5354#define TEARING_EFFECT_DSI (1 << 2)
5355#define TEARING_EFFECT_GPIO (2 << 2)
5356#define LANE_CONFIGURATION_SHIFT 0
5357#define LANE_CONFIGURATION_MASK (3 << 0)
5358#define LANE_CONFIGURATION_4LANE (0 << 0)
5359#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
5360#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
5361
5362#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
5363#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
5364#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
5365#define TEARING_EFFECT_DELAY_SHIFT 0
5366#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
5367
5368/* XXX: all bits reserved */
5369#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
5370
5371/* MIPI DSI Controller and D-PHY registers */
5372
5373#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
5374#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
5375#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
5376#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
5377#define ULPS_STATE_MASK (3 << 1)
5378#define ULPS_STATE_ENTER (2 << 1)
5379#define ULPS_STATE_EXIT (1 << 1)
5380#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
5381#define DEVICE_READY (1 << 0)
5382
5383#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
5384#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
5385#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
5386#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
5387#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
5388#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
5389#define TEARING_EFFECT (1 << 31)
5390#define SPL_PKT_SENT_INTERRUPT (1 << 30)
5391#define GEN_READ_DATA_AVAIL (1 << 29)
5392#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
5393#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
5394#define RX_PROT_VIOLATION (1 << 26)
5395#define RX_INVALID_TX_LENGTH (1 << 25)
5396#define ACK_WITH_NO_ERROR (1 << 24)
5397#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
5398#define LP_RX_TIMEOUT (1 << 22)
5399#define HS_TX_TIMEOUT (1 << 21)
5400#define DPI_FIFO_UNDERRUN (1 << 20)
5401#define LOW_CONTENTION (1 << 19)
5402#define HIGH_CONTENTION (1 << 18)
5403#define TXDSI_VC_ID_INVALID (1 << 17)
5404#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
5405#define TXCHECKSUM_ERROR (1 << 15)
5406#define TXECC_MULTIBIT_ERROR (1 << 14)
5407#define TXECC_SINGLE_BIT_ERROR (1 << 13)
5408#define TXFALSE_CONTROL_ERROR (1 << 12)
5409#define RXDSI_VC_ID_INVALID (1 << 11)
5410#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
5411#define RXCHECKSUM_ERROR (1 << 9)
5412#define RXECC_MULTIBIT_ERROR (1 << 8)
5413#define RXECC_SINGLE_BIT_ERROR (1 << 7)
5414#define RXFALSE_CONTROL_ERROR (1 << 6)
5415#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
5416#define RX_LP_TX_SYNC_ERROR (1 << 4)
5417#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
5418#define RXEOT_SYNC_ERROR (1 << 2)
5419#define RXSOT_SYNC_ERROR (1 << 1)
5420#define RXSOT_ERROR (1 << 0)
5421
5422#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
5423#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
5424#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
5425#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
5426#define CMD_MODE_NOT_SUPPORTED (0 << 13)
5427#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
5428#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
5429#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
5430#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
5431#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
5432#define VID_MODE_FORMAT_MASK (0xf << 7)
5433#define VID_MODE_NOT_SUPPORTED (0 << 7)
5434#define VID_MODE_FORMAT_RGB565 (1 << 7)
5435#define VID_MODE_FORMAT_RGB666 (2 << 7)
5436#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
5437#define VID_MODE_FORMAT_RGB888 (4 << 7)
5438#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
5439#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
5440#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
5441#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
5442#define DATA_LANES_PRG_REG_SHIFT 0
5443#define DATA_LANES_PRG_REG_MASK (7 << 0)
5444
5445#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
5446#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
5447#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
5448#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
5449
5450#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
5451#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
5452#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
5453#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
5454
5455#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
5456#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
5457#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
5458#define TURN_AROUND_TIMEOUT_MASK 0x3f
5459
5460#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
5461#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
5462#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
5463#define DEVICE_RESET_TIMER_MASK 0xffff
5464
5465#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
5466#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
5467#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
5468#define VERTICAL_ADDRESS_SHIFT 16
5469#define VERTICAL_ADDRESS_MASK (0xffff << 16)
5470#define HORIZONTAL_ADDRESS_SHIFT 0
5471#define HORIZONTAL_ADDRESS_MASK 0xffff
5472
5473#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
5474#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
5475#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
5476#define DBI_FIFO_EMPTY_HALF (0 << 0)
5477#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
5478#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
5479
5480/* regs below are bits 15:0 */
5481#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
5482#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
5483#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
5484
5485#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
5486#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
5487#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
5488
5489#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
5490#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
5491#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
5492
5493#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
5494#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
5495#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
5496
5497#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
5498#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
5499#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
5500
5501#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
5502#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
5503#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
5504
5505#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
5506#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
5507#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
5508
5509#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
5510#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
5511#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
5512/* regs above are bits 15:0 */
5513
5514#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
5515#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
5516#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
5517#define DPI_LP_MODE (1 << 6)
5518#define BACKLIGHT_OFF (1 << 5)
5519#define BACKLIGHT_ON (1 << 4)
5520#define COLOR_MODE_OFF (1 << 3)
5521#define COLOR_MODE_ON (1 << 2)
5522#define TURN_ON (1 << 1)
5523#define SHUTDOWN (1 << 0)
5524
5525#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
5526#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
5527#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
5528#define COMMAND_BYTE_SHIFT 0
5529#define COMMAND_BYTE_MASK (0x3f << 0)
5530
5531#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
5532#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
5533#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
5534#define MASTER_INIT_TIMER_SHIFT 0
5535#define MASTER_INIT_TIMER_MASK (0xffff << 0)
5536
5537#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
5538#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
5539#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
5540#define MAX_RETURN_PKT_SIZE_SHIFT 0
5541#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
5542
5543#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
5544#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
5545#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
5546#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
5547#define DISABLE_VIDEO_BTA (1 << 3)
5548#define IP_TG_CONFIG (1 << 2)
5549#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
5550#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
5551#define VIDEO_MODE_BURST (3 << 0)
5552
5553#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
5554#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
5555#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
5556#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
5557#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
5558#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
5559#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
5560#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
5561#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
5562#define CLOCKSTOP (1 << 1)
5563#define EOT_DISABLE (1 << 0)
5564
5565#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
5566#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
5567#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
5568#define LP_BYTECLK_SHIFT 0
5569#define LP_BYTECLK_MASK (0xffff << 0)
5570
5571/* bits 31:0 */
5572#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
5573#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
5574#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
5575
5576/* bits 31:0 */
5577#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
5578#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
5579#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
5580
5581#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
5582#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
5583#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
5584#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
5585#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
5586#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
5587#define LONG_PACKET_WORD_COUNT_SHIFT 8
5588#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
5589#define SHORT_PACKET_PARAM_SHIFT 8
5590#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
5591#define VIRTUAL_CHANNEL_SHIFT 6
5592#define VIRTUAL_CHANNEL_MASK (3 << 6)
5593#define DATA_TYPE_SHIFT 0
5594#define DATA_TYPE_MASK (3f << 0)
5595/* data type values, see include/video/mipi_display.h */
5596
5597#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
5598#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
5599#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
5600#define DPI_FIFO_EMPTY (1 << 28)
5601#define DBI_FIFO_EMPTY (1 << 27)
5602#define LP_CTRL_FIFO_EMPTY (1 << 26)
5603#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
5604#define LP_CTRL_FIFO_FULL (1 << 24)
5605#define HS_CTRL_FIFO_EMPTY (1 << 18)
5606#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
5607#define HS_CTRL_FIFO_FULL (1 << 16)
5608#define LP_DATA_FIFO_EMPTY (1 << 10)
5609#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
5610#define LP_DATA_FIFO_FULL (1 << 8)
5611#define HS_DATA_FIFO_EMPTY (1 << 2)
5612#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
5613#define HS_DATA_FIFO_FULL (1 << 0)
5614
5615#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
5616#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
5617#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
5618#define DBI_HS_LP_MODE_MASK (1 << 0)
5619#define DBI_LP_MODE (1 << 0)
5620#define DBI_HS_MODE (0 << 0)
5621
5622#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
5623#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
5624#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
5625#define EXIT_ZERO_COUNT_SHIFT 24
5626#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
5627#define TRAIL_COUNT_SHIFT 16
5628#define TRAIL_COUNT_MASK (0x1f << 16)
5629#define CLK_ZERO_COUNT_SHIFT 8
5630#define CLK_ZERO_COUNT_MASK (0xff << 8)
5631#define PREPARE_COUNT_SHIFT 0
5632#define PREPARE_COUNT_MASK (0x3f << 0)
5633
5634/* bits 31:0 */
5635#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
5636#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
5637#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
5638
5639#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
5640#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
5641#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
5642#define LP_HS_SSW_CNT_SHIFT 16
5643#define LP_HS_SSW_CNT_MASK (0xffff << 16)
5644#define HS_LP_PWR_SW_CNT_SHIFT 0
5645#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
5646
5647#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
5648#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
5649#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
5650#define STOP_STATE_STALL_COUNTER_SHIFT 0
5651#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
5652
5653#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
5654#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
5655#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
5656#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
5657#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
5658#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
5659#define RX_CONTENTION_DETECTED (1 << 0)
5660
5661/* XXX: only pipe A ?!? */
5662#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
5663#define DBI_TYPEC_ENABLE (1 << 31)
5664#define DBI_TYPEC_WIP (1 << 30)
5665#define DBI_TYPEC_OPTION_SHIFT 28
5666#define DBI_TYPEC_OPTION_MASK (3 << 28)
5667#define DBI_TYPEC_FREQ_SHIFT 24
5668#define DBI_TYPEC_FREQ_MASK (0xf << 24)
5669#define DBI_TYPEC_OVERRIDE (1 << 8)
5670#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
5671#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
5672
5673
5674/* MIPI adapter registers */
5675
5676#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
5677#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
5678#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
5679#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
5680#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
5681#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
5682#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
5683#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
5684#define READ_REQUEST_PRIORITY_SHIFT 3
5685#define READ_REQUEST_PRIORITY_MASK (3 << 3)
5686#define READ_REQUEST_PRIORITY_LOW (0 << 3)
5687#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
5688#define RGB_FLIP_TO_BGR (1 << 2)
5689
5690#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
5691#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
5692#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
5693#define DATA_MEM_ADDRESS_SHIFT 5
5694#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
5695#define DATA_VALID (1 << 0)
5696
5697#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
5698#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
5699#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
5700#define DATA_LENGTH_SHIFT 0
5701#define DATA_LENGTH_MASK (0xfffff << 0)
5702
5703#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
5704#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
5705#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
5706#define COMMAND_MEM_ADDRESS_SHIFT 5
5707#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
5708#define AUTO_PWG_ENABLE (1 << 2)
5709#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
5710#define COMMAND_VALID (1 << 0)
5711
5712#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
5713#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
5714#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
5715#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
5716#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
5717
5718#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
5719#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
5720#define MIPI_READ_DATA_RETURN(pipe, n) \
5721 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
5722
5723#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
5724#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
5725#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5726#define READ_DATA_VALID(n) (1 << (n))
5727
Jesse Barnes585fb112008-07-29 11:54:06 -07005728#endif /* _I915_REG_H_ */