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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Jani Nikula1aa920e2017-08-10 15:29:44 +030028/**
29 * DOC: The i915 register macro definition style guide
30 *
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
33 *
34 * Layout
35 * ''''''
36 *
37 * Keep helper macros near the top. For example, _PIPE() and friends.
38 *
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
42 *
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
45 *
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
50 *
51 * For single registers, define the register offset first, followed by register
52 * contents.
53 *
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
57 *
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
61 *
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
66 * register contents.
67 *
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
70 * to the name.
71 *
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
74 *
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
79 *
80 * Naming
81 * ''''''
82 *
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
85 *
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
89 *
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
93 *
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
97 *
98 * Examples
99 * ''''''''
100 *
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
103 * definitions.)::
104 *
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200119typedef struct {
120 uint32_t reg;
121} i915_reg_t;
122
123#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
124
125#define INVALID_MMIO_REG _MMIO(0)
126
127static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
128{
129 return reg.reg;
130}
131
132static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
133{
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
135}
136
137static inline bool i915_mmio_reg_valid(i915_reg_t reg)
138{
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
140}
141
Jani Nikulace646452017-01-27 17:57:06 +0200142#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
143
Chris Wilson5eddb702010-09-11 13:48:45 +0100144#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200145#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
Damien Lespiau70d21f02013-07-03 21:06:04 +0100146#define _PLANE(plane, a, b) _PIPE(plane, a, b)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200147#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
148#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
149#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300150#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200151#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
Rodrigo Vivia1986f42017-06-05 15:12:02 -0700152#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
153#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
Rodrigo Vivia927c922017-06-09 15:26:04 -0700154#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
155#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
Rodrigo Vivi4557c602017-06-09 15:26:05 -0700156#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
157#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
Jani Nikulace646452017-01-27 17:57:06 +0200159#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +0200160#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300161
Damien Lespiau98533252014-12-08 17:33:51 +0000162#define _MASKED_FIELD(mask, value) ({ \
163 if (__builtin_constant_p(mask)) \
164 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
165 if (__builtin_constant_p(value)) \
166 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
167 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
168 BUILD_BUG_ON_MSG((value) & ~(mask), \
169 "Incorrect value for mask"); \
170 (mask) << 16 | (value); })
171#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
172#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
173
Michal Wajdeczko237ae7c2017-03-01 20:26:15 +0000174/* Engine ID */
Damien Lespiau98533252014-12-08 17:33:51 +0000175
Michal Wajdeczko237ae7c2017-03-01 20:26:15 +0000176#define RCS_HW 0
177#define VCS_HW 1
178#define BCS_HW 2
179#define VECS_HW 3
180#define VCS2_HW 4
Daniel Vetter6b26c862012-04-24 14:04:12 +0200181
Daniele Ceraolo Spurio0908180b2017-04-10 07:34:29 -0700182/* Engine class */
183
184#define RENDER_CLASS 0
185#define VIDEO_DECODE_CLASS 1
186#define VIDEO_ENHANCEMENT_CLASS 2
187#define COPY_ENGINE_CLASS 3
188#define OTHER_CLASS 4
Tvrtko Ursulinb46a33e2017-11-21 18:18:45 +0000189#define MAX_ENGINE_CLASS 4
190
191#define MAX_ENGINE_INSTANCE 1
Daniele Ceraolo Spurio0908180b2017-04-10 07:34:29 -0700192
Jesse Barnes585fb112008-07-29 11:54:06 -0700193/* PCI config space */
194
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300195#define MCHBAR_I915 0x44
196#define MCHBAR_I965 0x48
197#define MCHBAR_SIZE (4 * 4096)
198
199#define DEVEN 0x54
200#define DEVEN_MCHBAR_EN (1 << 28)
201
Joonas Lahtinen40006c42016-10-12 10:18:54 +0300202/* BSM in include/drm/i915_drm.h */
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300203
Ville Syrjälä1b1d2712015-05-22 11:22:31 +0300204#define HPLLCC 0xc0 /* 85x only */
205#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700206#define GC_CLOCK_133_200 (0 << 0)
207#define GC_CLOCK_100_200 (1 << 0)
208#define GC_CLOCK_100_133 (2 << 0)
Ville Syrjälä1b1d2712015-05-22 11:22:31 +0300209#define GC_CLOCK_133_266 (3 << 0)
210#define GC_CLOCK_133_200_2 (4 << 0)
211#define GC_CLOCK_133_266_2 (5 << 0)
212#define GC_CLOCK_166_266 (6 << 0)
213#define GC_CLOCK_166_250 (7 << 0)
214
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300215#define I915_GDRST 0xc0 /* PCI config register */
216#define GRDOM_FULL (0 << 2)
217#define GRDOM_RENDER (1 << 2)
218#define GRDOM_MEDIA (3 << 2)
219#define GRDOM_MASK (3 << 2)
220#define GRDOM_RESET_STATUS (1 << 1)
221#define GRDOM_RESET_ENABLE (1 << 0)
222
Ville Syrjälä8fdded82016-12-07 19:28:12 +0200223/* BSpec only has register offset, PCI device and bit found empirically */
224#define I830_CLOCK_GATE 0xc8 /* device 0 */
225#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
226
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300227#define GCDGMBUS 0xcc
228
Jesse Barnesf97108d2010-01-29 11:27:07 -0800229#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -0700230#define GCFGC 0xf0 /* 915+ only */
231#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
232#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
Arthur Heymans62480172017-02-01 00:50:26 +0100233#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +0200234#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
235#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
236#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
237#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
238#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
239#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700240#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -0700241#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
242#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
243#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
244#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
245#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
246#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
247#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
248#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
249#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
250#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
251#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
252#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
253#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
254#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
255#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
256#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
257#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
258#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
259#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +0100260
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300261#define ASLE 0xe4
262#define ASLS 0xfc
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700263
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300264#define SWSCI 0xe8
265#define SWSCI_SCISEL (1 << 15)
266#define SWSCI_GSSCIE (1 << 0)
267
268#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
269
Jesse Barnes585fb112008-07-29 11:54:06 -0700270
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200271#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
Ville Syrjäläb3a3f032014-05-19 19:23:24 +0300272#define ILK_GRDOM_FULL (0<<1)
273#define ILK_GRDOM_RENDER (1<<1)
274#define ILK_GRDOM_MEDIA (3<<1)
275#define ILK_GRDOM_MASK (3<<1)
276#define ILK_GRDOM_RESET_ENABLE (1<<0)
277
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200278#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700279#define GEN6_MBC_SNPCR_SHIFT 21
280#define GEN6_MBC_SNPCR_MASK (3<<21)
281#define GEN6_MBC_SNPCR_MAX (0<<21)
282#define GEN6_MBC_SNPCR_MED (1<<21)
283#define GEN6_MBC_SNPCR_LOW (2<<21)
284#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
285
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200286#define VLV_G3DCTL _MMIO(0x9024)
287#define VLV_GSCKGCTL _MMIO(0x9028)
Imre Deak9e72b462014-05-05 15:13:55 +0300288
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200289#define GEN6_MBCTL _MMIO(0x0907c)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100290#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
291#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
292#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
293#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
294#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
295
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200296#define GEN6_GDRST _MMIO(0x941c)
Eric Anholtcff458c2010-11-18 09:31:14 +0800297#define GEN6_GRDOM_FULL (1 << 0)
298#define GEN6_GRDOM_RENDER (1 << 1)
299#define GEN6_GRDOM_MEDIA (1 << 2)
300#define GEN6_GRDOM_BLT (1 << 3)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200301#define GEN6_GRDOM_VECS (1 << 4)
Arun Siluvery6b332fa2016-04-04 18:50:56 +0100302#define GEN9_GRDOM_GUC (1 << 5)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200303#define GEN8_GRDOM_MEDIA2 (1 << 7)
Eric Anholtcff458c2010-11-18 09:31:14 +0800304
Dave Gordonbbdc070a2016-07-20 18:16:05 +0100305#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
306#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
307#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100308#define PP_DIR_DCLV_2G 0xffffffff
309
Dave Gordonbbdc070a2016-07-20 18:16:05 +0100310#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
311#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800312
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200313#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
Jeff McGee0cea6502015-02-13 10:27:56 -0600314#define GEN8_RPCS_ENABLE (1 << 31)
315#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
316#define GEN8_RPCS_S_CNT_SHIFT 15
317#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
318#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
319#define GEN8_RPCS_SS_CNT_SHIFT 8
320#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
321#define GEN8_RPCS_EU_MAX_SHIFT 4
322#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
323#define GEN8_RPCS_EU_MIN_SHIFT 0
324#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
325
Lionel Landwerlinf89823c2017-08-03 18:05:50 +0100326#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
327/* HSW only */
328#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
329#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
330#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
331#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
332/* HSW+ */
333#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
334#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
335#define HSW_RCS_INHIBIT (1 << 8)
336/* Gen8 */
337#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
338#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
339#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
340#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
341#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
342#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
343#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
344#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
345#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
346#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
347
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200348#define GAM_ECOCHK _MMIO(0x4090)
Damien Lespiau81e231a2015-02-09 19:33:19 +0000349#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100350#define ECOCHK_SNB_BIT (1<<10)
Nick Hoath6381b552015-07-14 14:41:15 +0100351#define ECOCHK_DIS_TLB (1<<8)
Ben Widawskye3dff582013-03-20 14:49:14 -0700352#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100353#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
354#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300355#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
356#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
357#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
358#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
359#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100360
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200361#define GAC_ECO_BITS _MMIO(0x14090)
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300362#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200363#define ECOBITS_PPGTT_CACHE64B (3<<8)
364#define ECOBITS_PPGTT_CACHE4B (0<<8)
365
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200366#define GAB_CTL _MMIO(0x24000)
Daniel Vetterbe901a52012-04-11 20:42:39 +0200367#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
368
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200369#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
Paulo Zanoni3774eb52015-08-10 14:57:32 -0300370#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
371#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
372#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
373#define GEN6_STOLEN_RESERVED_1M (0 << 4)
374#define GEN6_STOLEN_RESERVED_512K (1 << 4)
375#define GEN6_STOLEN_RESERVED_256K (2 << 4)
376#define GEN6_STOLEN_RESERVED_128K (3 << 4)
377#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
378#define GEN7_STOLEN_RESERVED_1M (0 << 5)
379#define GEN7_STOLEN_RESERVED_256K (1 << 5)
380#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
381#define GEN8_STOLEN_RESERVED_1M (0 << 7)
382#define GEN8_STOLEN_RESERVED_2M (1 << 7)
383#define GEN8_STOLEN_RESERVED_4M (2 << 7)
384#define GEN8_STOLEN_RESERVED_8M (3 << 7)
Ville Syrjälädb7fb602017-11-02 17:17:35 +0200385#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
Daniel Vetter40bae732014-09-11 13:28:08 +0200386
Jesse Barnes585fb112008-07-29 11:54:06 -0700387/* VGA stuff */
388
389#define VGA_ST01_MDA 0x3ba
390#define VGA_ST01_CGA 0x3da
391
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200392#define _VGA_MSR_WRITE _MMIO(0x3c2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700393#define VGA_MSR_WRITE 0x3c2
394#define VGA_MSR_READ 0x3cc
395#define VGA_MSR_MEM_EN (1<<1)
396#define VGA_MSR_CGA_MODE (1<<0)
397
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300398#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100399#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300400#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700401
402#define VGA_AR_INDEX 0x3c0
403#define VGA_AR_VID_EN (1<<5)
404#define VGA_AR_DATA_WRITE 0x3c0
405#define VGA_AR_DATA_READ 0x3c1
406
407#define VGA_GR_INDEX 0x3ce
408#define VGA_GR_DATA 0x3cf
409/* GR05 */
410#define VGA_GR_MEM_READ_MODE_SHIFT 3
411#define VGA_GR_MEM_READ_MODE_PLANE 1
412/* GR06 */
413#define VGA_GR_MEM_MODE_MASK 0xc
414#define VGA_GR_MEM_MODE_SHIFT 2
415#define VGA_GR_MEM_A0000_AFFFF 0
416#define VGA_GR_MEM_A0000_BFFFF 1
417#define VGA_GR_MEM_B0000_B7FFF 2
418#define VGA_GR_MEM_B0000_BFFFF 3
419
420#define VGA_DACMASK 0x3c6
421#define VGA_DACRX 0x3c7
422#define VGA_DACWX 0x3c8
423#define VGA_DACDATA 0x3c9
424
425#define VGA_CR_INDEX_MDA 0x3b4
426#define VGA_CR_DATA_MDA 0x3b5
427#define VGA_CR_INDEX_CGA 0x3d4
428#define VGA_CR_DATA_CGA 0x3d5
429
430/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800431 * Instruction field definitions used by the command parser
432 */
433#define INSTR_CLIENT_SHIFT 29
Brad Volkin351e3db2014-02-18 10:15:46 -0800434#define INSTR_MI_CLIENT 0x0
435#define INSTR_BC_CLIENT 0x2
436#define INSTR_RC_CLIENT 0x3
437#define INSTR_SUBCLIENT_SHIFT 27
438#define INSTR_SUBCLIENT_MASK 0x18000000
439#define INSTR_MEDIA_SUBCLIENT 0x2
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800440#define INSTR_26_TO_24_MASK 0x7000000
441#define INSTR_26_TO_24_SHIFT 24
Brad Volkin351e3db2014-02-18 10:15:46 -0800442
443/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700444 * Memory interface instructions used by the kernel
445 */
446#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800447/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
448#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700449
450#define MI_NOOP MI_INSTR(0, 0)
451#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
452#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200453#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700454#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
455#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
456#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
457#define MI_FLUSH MI_INSTR(0x04, 0)
458#define MI_READ_FLUSH (1 << 0)
459#define MI_EXE_FLUSH (1 << 1)
460#define MI_NO_WRITE_FLUSH (1 << 2)
461#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
462#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800463#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800464#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
465#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
466#define MI_ARB_ENABLE (1<<0)
467#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700468#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800469#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
470#define MI_SUSPEND_FLUSH_EN (1<<0)
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800471#define MI_SET_APPID MI_INSTR(0x0e, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400472#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200473#define MI_OVERLAY_CONTINUE (0x0<<21)
474#define MI_OVERLAY_ON (0x1<<21)
475#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700476#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500477#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700478#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500479#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200480/* IVB has funny definitions for which plane to flip. */
481#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
482#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
483#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
484#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
485#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
486#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Damien Lespiau830c81d2014-11-13 17:51:46 +0000487/* SKL ones */
488#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
489#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
490#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
491#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
492#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
493#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
494#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
495#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
496#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700497#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
Ben Widawsky0e792842013-12-16 20:50:37 -0800498#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
499#define MI_SEMAPHORE_UPDATE (1<<21)
500#define MI_SEMAPHORE_COMPARE (1<<20)
501#define MI_SEMAPHORE_REGISTER (1<<18)
502#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
503#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
504#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
505#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
506#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
507#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
508#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
509#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
510#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
511#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
512#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
513#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100514#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
515#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800516#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
517#define MI_MM_SPACE_GTT (1<<8)
518#define MI_MM_SPACE_PHYSICAL (0<<8)
519#define MI_SAVE_EXT_STATE_EN (1<<3)
520#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800521#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800522#define MI_RESTORE_INHIBIT (1<<0)
Abdiel Janulgue4c436d552015-06-16 13:39:41 +0300523#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
524#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
Ben Widawsky3e789982014-06-30 09:53:37 -0700525#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
526#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
Ben Widawsky5ee426c2014-06-30 09:53:38 -0700527#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
528#define MI_SEMAPHORE_POLL (1<<15)
529#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
Jesse Barnes585fb112008-07-29 11:54:06 -0700530#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
Ville Syrjälä8edfbb82014-11-14 18:16:56 +0200531#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
532#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
533#define MI_USE_GGTT (1 << 22) /* g4x+ */
Jesse Barnes585fb112008-07-29 11:54:06 -0700534#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
535#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000536/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
537 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
538 * simply ignores the register load under certain conditions.
539 * - One can actually load arbitrary many arbitrary registers: Simply issue x
540 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
541 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100542#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100543#define MI_LRI_FORCE_POSTED (1<<12)
Arun Siluveryf1afe242015-08-04 16:22:20 +0100544#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
545#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
Ben Widawsky0e792842013-12-16 20:50:37 -0800546#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000547#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700548#define MI_FLUSH_DW_STORE_INDEX (1<<21)
549#define MI_INVALIDATE_TLB (1<<18)
550#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800551#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800552#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700553#define MI_INVALIDATE_BSD (1<<7)
554#define MI_FLUSH_DW_USE_GTT (1<<2)
555#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Arun Siluveryf1afe242015-08-04 16:22:20 +0100556#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
557#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700558#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100559#define MI_BATCH_NON_SECURE (1)
560/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800561#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100562#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800563#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700564#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100565#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700566#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Abdiel Janulgue919032e2015-06-16 13:39:40 +0300567#define MI_BATCH_RESOURCE_STREAMER (1<<10)
Ben Widawsky0e792842013-12-16 20:50:37 -0800568
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200569#define MI_PREDICATE_SRC0 _MMIO(0x2400)
570#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
571#define MI_PREDICATE_SRC1 _MMIO(0x2408)
572#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300573
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200574#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300575#define LOWER_SLICE_ENABLED (1<<0)
576#define LOWER_SLICE_DISABLED (0<<0)
577
Jesse Barnes585fb112008-07-29 11:54:06 -0700578/*
579 * 3D instructions used by the kernel
580 */
581#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
582
arun.siluvery@linux.intel.com33e141e2016-06-03 06:34:33 +0100583#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
584#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
Jesse Barnes585fb112008-07-29 11:54:06 -0700585#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
586#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
587#define SC_UPDATE_SCISSOR (0x1<<1)
588#define SC_ENABLE_MASK (0x1<<0)
589#define SC_ENABLE (0x1<<0)
590#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
591#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
592#define SCI_YMIN_MASK (0xffff<<16)
593#define SCI_XMIN_MASK (0xffff<<0)
594#define SCI_YMAX_MASK (0xffff<<16)
595#define SCI_XMAX_MASK (0xffff<<0)
596#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
597#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
598#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
599#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
600#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
601#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
602#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
603#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
604#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100605
606#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
607#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700608#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
609#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100610#define BLT_WRITE_A (2<<20)
611#define BLT_WRITE_RGB (1<<20)
612#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
Jesse Barnes585fb112008-07-29 11:54:06 -0700613#define BLT_DEPTH_8 (0<<24)
614#define BLT_DEPTH_16_565 (1<<24)
615#define BLT_DEPTH_16_1555 (2<<24)
616#define BLT_DEPTH_32 (3<<24)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100617#define BLT_ROP_SRC_COPY (0xcc<<16)
618#define BLT_ROP_COLOR_COPY (0xf0<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700619#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
620#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
621#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
622#define ASYNC_FLIP (1<<22)
623#define DISPLAY_PLANE_A (0<<20)
624#define DISPLAY_PLANE_B (1<<20)
Ville Syrjälä68d97532015-09-18 20:03:39 +0300625#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
Arun Siluvery0160f052015-06-23 15:46:57 +0100626#define PIPE_CONTROL_FLUSH_L3 (1<<27)
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200627#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800628#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800629#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200630#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700631#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Chris Wilson148b83d2014-12-16 08:44:31 +0000632#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200633#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800634#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200635#define PIPE_CONTROL_DEPTH_STALL (1<<13)
636#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200637#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200638#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
639#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
640#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
641#define PIPE_CONTROL_NOTIFY (1<<8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700642#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
Arun Siluveryc82435b2015-06-19 18:37:13 +0100643#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
Jesse Barnes8d315282011-10-16 10:23:31 +0200644#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
645#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
646#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200647#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200648#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700649#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700650
Brad Volkin3a6fa982014-02-18 10:15:47 -0800651/*
652 * Commands used only by the command parser
653 */
654#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
655#define MI_ARB_CHECK MI_INSTR(0x05, 0)
656#define MI_RS_CONTROL MI_INSTR(0x06, 0)
657#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
658#define MI_PREDICATE MI_INSTR(0x0C, 0)
659#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
660#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800661#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800662#define MI_URB_CLEAR MI_INSTR(0x19, 0)
663#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
664#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800665#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
666#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800667#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
668#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
669#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
670#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
671#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
672
673#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
674#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800675#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
676#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800677#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
678#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
679#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
680 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
681#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
682 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
683#define GFX_OP_3DSTATE_SO_DECL_LIST \
684 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
685
686#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
687 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
688#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
689 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
690#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
691 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
692#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
693 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
694#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
695 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
696
697#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
698
699#define COLOR_BLT ((0x2<<29)|(0x40<<22))
700#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100701
702/*
Brad Volkin5947de92014-02-18 10:15:50 -0800703 * Registers used only by the command parser
704 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200705#define BCS_SWCTRL _MMIO(0x22200)
Brad Volkin5947de92014-02-18 10:15:50 -0800706
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200707#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
708#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
709#define HS_INVOCATION_COUNT _MMIO(0x2300)
710#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
711#define DS_INVOCATION_COUNT _MMIO(0x2308)
712#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
713#define IA_VERTICES_COUNT _MMIO(0x2310)
714#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
715#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
716#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
717#define VS_INVOCATION_COUNT _MMIO(0x2320)
718#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
719#define GS_INVOCATION_COUNT _MMIO(0x2328)
720#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
721#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
722#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
723#define CL_INVOCATION_COUNT _MMIO(0x2338)
724#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
725#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
726#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
727#define PS_INVOCATION_COUNT _MMIO(0x2348)
728#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
729#define PS_DEPTH_COUNT _MMIO(0x2350)
730#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800731
732/* There are the 4 64-bit counter registers, one for each stream output */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200733#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
734#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800735
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200736#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
737#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
Brad Volkin113a0472014-04-08 14:18:58 -0700738
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200739#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
740#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
741#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
742#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
743#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
744#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
Brad Volkin113a0472014-04-08 14:18:58 -0700745
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200746#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
747#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
748#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
Jordan Justen7b9748c2015-10-01 23:09:58 -0700749
Jordan Justen1b850662016-03-06 23:30:29 -0800750/* There are the 16 64-bit CS General Purpose Registers */
751#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
752#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
753
Robert Bragga9417952016-11-07 19:49:48 +0000754#define GEN7_OACONTROL _MMIO(0x2360)
Robert Braggd7965152016-11-07 19:49:52 +0000755#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
756#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
757#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
758#define GEN7_OACONTROL_TIMER_ENABLE (1<<5)
759#define GEN7_OACONTROL_FORMAT_A13 (0<<2)
760#define GEN7_OACONTROL_FORMAT_A29 (1<<2)
761#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2)
762#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2)
763#define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2)
764#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2)
765#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2)
766#define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2)
767#define GEN7_OACONTROL_FORMAT_SHIFT 2
768#define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1)
769#define GEN7_OACONTROL_ENABLE (1<<0)
770
771#define GEN8_OACTXID _MMIO(0x2364)
772
Robert Bragg19f81df2017-06-13 12:23:03 +0100773#define GEN8_OA_DEBUG _MMIO(0x2B04)
774#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5)
775#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6)
776#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2)
777#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1)
778
Robert Braggd7965152016-11-07 19:49:52 +0000779#define GEN8_OACONTROL _MMIO(0x2B00)
780#define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
781#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
782#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2)
783#define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2)
784#define GEN8_OA_REPORT_FORMAT_SHIFT 2
785#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1)
786#define GEN8_OA_COUNTER_ENABLE (1<<0)
787
788#define GEN8_OACTXCONTROL _MMIO(0x2360)
789#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
790#define GEN8_OA_TIMER_PERIOD_SHIFT 2
791#define GEN8_OA_TIMER_ENABLE (1<<1)
792#define GEN8_OA_COUNTER_RESUME (1<<0)
793
794#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
795#define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3)
796#define GEN7_OABUFFER_EDGE_TRIGGER (1<<2)
797#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
798#define GEN7_OABUFFER_RESUME (1<<0)
799
Robert Bragg19f81df2017-06-13 12:23:03 +0100800#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
Robert Braggd7965152016-11-07 19:49:52 +0000801#define GEN8_OABUFFER _MMIO(0x2b14)
802
803#define GEN7_OASTATUS1 _MMIO(0x2364)
804#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
805#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2)
806#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1)
807#define GEN7_OASTATUS1_REPORT_LOST (1<<0)
808
809#define GEN7_OASTATUS2 _MMIO(0x2368)
810#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
811
812#define GEN8_OASTATUS _MMIO(0x2b08)
813#define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
814#define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2)
815#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1)
816#define GEN8_OASTATUS_REPORT_LOST (1<<0)
817
818#define GEN8_OAHEADPTR _MMIO(0x2B0C)
Robert Bragg19f81df2017-06-13 12:23:03 +0100819#define GEN8_OAHEADPTR_MASK 0xffffffc0
Robert Braggd7965152016-11-07 19:49:52 +0000820#define GEN8_OATAILPTR _MMIO(0x2B10)
Robert Bragg19f81df2017-06-13 12:23:03 +0100821#define GEN8_OATAILPTR_MASK 0xffffffc0
Robert Braggd7965152016-11-07 19:49:52 +0000822
823#define OABUFFER_SIZE_128K (0<<3)
824#define OABUFFER_SIZE_256K (1<<3)
825#define OABUFFER_SIZE_512K (2<<3)
826#define OABUFFER_SIZE_1M (3<<3)
827#define OABUFFER_SIZE_2M (4<<3)
828#define OABUFFER_SIZE_4M (5<<3)
829#define OABUFFER_SIZE_8M (6<<3)
830#define OABUFFER_SIZE_16M (7<<3)
831
832#define OA_MEM_SELECT_GGTT (1<<0)
833
Robert Bragg19f81df2017-06-13 12:23:03 +0100834/*
835 * Flexible, Aggregate EU Counter Registers.
836 * Note: these aren't contiguous
837 */
Robert Braggd7965152016-11-07 19:49:52 +0000838#define EU_PERF_CNTL0 _MMIO(0xe458)
Robert Bragg19f81df2017-06-13 12:23:03 +0100839#define EU_PERF_CNTL1 _MMIO(0xe558)
840#define EU_PERF_CNTL2 _MMIO(0xe658)
841#define EU_PERF_CNTL3 _MMIO(0xe758)
842#define EU_PERF_CNTL4 _MMIO(0xe45c)
843#define EU_PERF_CNTL5 _MMIO(0xe55c)
844#define EU_PERF_CNTL6 _MMIO(0xe65c)
Robert Braggd7965152016-11-07 19:49:52 +0000845
Robert Braggd7965152016-11-07 19:49:52 +0000846/*
847 * OA Boolean state
848 */
849
Robert Braggd7965152016-11-07 19:49:52 +0000850#define OASTARTTRIG1 _MMIO(0x2710)
851#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
852#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
853
854#define OASTARTTRIG2 _MMIO(0x2714)
855#define OASTARTTRIG2_INVERT_A_0 (1<<0)
856#define OASTARTTRIG2_INVERT_A_1 (1<<1)
857#define OASTARTTRIG2_INVERT_A_2 (1<<2)
858#define OASTARTTRIG2_INVERT_A_3 (1<<3)
859#define OASTARTTRIG2_INVERT_A_4 (1<<4)
860#define OASTARTTRIG2_INVERT_A_5 (1<<5)
861#define OASTARTTRIG2_INVERT_A_6 (1<<6)
862#define OASTARTTRIG2_INVERT_A_7 (1<<7)
863#define OASTARTTRIG2_INVERT_A_8 (1<<8)
864#define OASTARTTRIG2_INVERT_A_9 (1<<9)
865#define OASTARTTRIG2_INVERT_A_10 (1<<10)
866#define OASTARTTRIG2_INVERT_A_11 (1<<11)
867#define OASTARTTRIG2_INVERT_A_12 (1<<12)
868#define OASTARTTRIG2_INVERT_A_13 (1<<13)
869#define OASTARTTRIG2_INVERT_A_14 (1<<14)
870#define OASTARTTRIG2_INVERT_A_15 (1<<15)
871#define OASTARTTRIG2_INVERT_B_0 (1<<16)
872#define OASTARTTRIG2_INVERT_B_1 (1<<17)
873#define OASTARTTRIG2_INVERT_B_2 (1<<18)
874#define OASTARTTRIG2_INVERT_B_3 (1<<19)
875#define OASTARTTRIG2_INVERT_C_0 (1<<20)
876#define OASTARTTRIG2_INVERT_C_1 (1<<21)
877#define OASTARTTRIG2_INVERT_D_0 (1<<22)
878#define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23)
879#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24)
880#define OASTARTTRIG2_EVENT_SELECT_0 (1<<28)
881#define OASTARTTRIG2_EVENT_SELECT_1 (1<<29)
882#define OASTARTTRIG2_EVENT_SELECT_2 (1<<30)
883#define OASTARTTRIG2_EVENT_SELECT_3 (1<<31)
884
885#define OASTARTTRIG3 _MMIO(0x2718)
886#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
887#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
888#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
889#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
890#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
891#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
892#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
893#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
894#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
895
896#define OASTARTTRIG4 _MMIO(0x271c)
897#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
898#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
899#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
900#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
901#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
902#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
903#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
904#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
905#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
906
907#define OASTARTTRIG5 _MMIO(0x2720)
908#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
909#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
910
911#define OASTARTTRIG6 _MMIO(0x2724)
912#define OASTARTTRIG6_INVERT_A_0 (1<<0)
913#define OASTARTTRIG6_INVERT_A_1 (1<<1)
914#define OASTARTTRIG6_INVERT_A_2 (1<<2)
915#define OASTARTTRIG6_INVERT_A_3 (1<<3)
916#define OASTARTTRIG6_INVERT_A_4 (1<<4)
917#define OASTARTTRIG6_INVERT_A_5 (1<<5)
918#define OASTARTTRIG6_INVERT_A_6 (1<<6)
919#define OASTARTTRIG6_INVERT_A_7 (1<<7)
920#define OASTARTTRIG6_INVERT_A_8 (1<<8)
921#define OASTARTTRIG6_INVERT_A_9 (1<<9)
922#define OASTARTTRIG6_INVERT_A_10 (1<<10)
923#define OASTARTTRIG6_INVERT_A_11 (1<<11)
924#define OASTARTTRIG6_INVERT_A_12 (1<<12)
925#define OASTARTTRIG6_INVERT_A_13 (1<<13)
926#define OASTARTTRIG6_INVERT_A_14 (1<<14)
927#define OASTARTTRIG6_INVERT_A_15 (1<<15)
928#define OASTARTTRIG6_INVERT_B_0 (1<<16)
929#define OASTARTTRIG6_INVERT_B_1 (1<<17)
930#define OASTARTTRIG6_INVERT_B_2 (1<<18)
931#define OASTARTTRIG6_INVERT_B_3 (1<<19)
932#define OASTARTTRIG6_INVERT_C_0 (1<<20)
933#define OASTARTTRIG6_INVERT_C_1 (1<<21)
934#define OASTARTTRIG6_INVERT_D_0 (1<<22)
935#define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23)
936#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24)
937#define OASTARTTRIG6_EVENT_SELECT_4 (1<<28)
938#define OASTARTTRIG6_EVENT_SELECT_5 (1<<29)
939#define OASTARTTRIG6_EVENT_SELECT_6 (1<<30)
940#define OASTARTTRIG6_EVENT_SELECT_7 (1<<31)
941
942#define OASTARTTRIG7 _MMIO(0x2728)
943#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
944#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
945#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
946#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
947#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
948#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
949#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
950#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
951#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
952
953#define OASTARTTRIG8 _MMIO(0x272c)
954#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
955#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
956#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
957#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
958#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
959#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
960#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
961#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
962#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
963
Lionel Landwerlin7853d922017-08-03 17:58:11 +0100964#define OAREPORTTRIG1 _MMIO(0x2740)
965#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
966#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
967
968#define OAREPORTTRIG2 _MMIO(0x2744)
969#define OAREPORTTRIG2_INVERT_A_0 (1<<0)
970#define OAREPORTTRIG2_INVERT_A_1 (1<<1)
971#define OAREPORTTRIG2_INVERT_A_2 (1<<2)
972#define OAREPORTTRIG2_INVERT_A_3 (1<<3)
973#define OAREPORTTRIG2_INVERT_A_4 (1<<4)
974#define OAREPORTTRIG2_INVERT_A_5 (1<<5)
975#define OAREPORTTRIG2_INVERT_A_6 (1<<6)
976#define OAREPORTTRIG2_INVERT_A_7 (1<<7)
977#define OAREPORTTRIG2_INVERT_A_8 (1<<8)
978#define OAREPORTTRIG2_INVERT_A_9 (1<<9)
979#define OAREPORTTRIG2_INVERT_A_10 (1<<10)
980#define OAREPORTTRIG2_INVERT_A_11 (1<<11)
981#define OAREPORTTRIG2_INVERT_A_12 (1<<12)
982#define OAREPORTTRIG2_INVERT_A_13 (1<<13)
983#define OAREPORTTRIG2_INVERT_A_14 (1<<14)
984#define OAREPORTTRIG2_INVERT_A_15 (1<<15)
985#define OAREPORTTRIG2_INVERT_B_0 (1<<16)
986#define OAREPORTTRIG2_INVERT_B_1 (1<<17)
987#define OAREPORTTRIG2_INVERT_B_2 (1<<18)
988#define OAREPORTTRIG2_INVERT_B_3 (1<<19)
989#define OAREPORTTRIG2_INVERT_C_0 (1<<20)
990#define OAREPORTTRIG2_INVERT_C_1 (1<<21)
991#define OAREPORTTRIG2_INVERT_D_0 (1<<22)
992#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23)
993#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)
994
995#define OAREPORTTRIG3 _MMIO(0x2748)
996#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
997#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
998#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
999#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
1000#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
1001#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
1002#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
1003#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
1004#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
1005
1006#define OAREPORTTRIG4 _MMIO(0x274c)
1007#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
1008#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
1009#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
1010#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
1011#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
1012#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
1013#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
1014#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
1015#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
1016
1017#define OAREPORTTRIG5 _MMIO(0x2750)
1018#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
1019#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
1020
1021#define OAREPORTTRIG6 _MMIO(0x2754)
1022#define OAREPORTTRIG6_INVERT_A_0 (1<<0)
1023#define OAREPORTTRIG6_INVERT_A_1 (1<<1)
1024#define OAREPORTTRIG6_INVERT_A_2 (1<<2)
1025#define OAREPORTTRIG6_INVERT_A_3 (1<<3)
1026#define OAREPORTTRIG6_INVERT_A_4 (1<<4)
1027#define OAREPORTTRIG6_INVERT_A_5 (1<<5)
1028#define OAREPORTTRIG6_INVERT_A_6 (1<<6)
1029#define OAREPORTTRIG6_INVERT_A_7 (1<<7)
1030#define OAREPORTTRIG6_INVERT_A_8 (1<<8)
1031#define OAREPORTTRIG6_INVERT_A_9 (1<<9)
1032#define OAREPORTTRIG6_INVERT_A_10 (1<<10)
1033#define OAREPORTTRIG6_INVERT_A_11 (1<<11)
1034#define OAREPORTTRIG6_INVERT_A_12 (1<<12)
1035#define OAREPORTTRIG6_INVERT_A_13 (1<<13)
1036#define OAREPORTTRIG6_INVERT_A_14 (1<<14)
1037#define OAREPORTTRIG6_INVERT_A_15 (1<<15)
1038#define OAREPORTTRIG6_INVERT_B_0 (1<<16)
1039#define OAREPORTTRIG6_INVERT_B_1 (1<<17)
1040#define OAREPORTTRIG6_INVERT_B_2 (1<<18)
1041#define OAREPORTTRIG6_INVERT_B_3 (1<<19)
1042#define OAREPORTTRIG6_INVERT_C_0 (1<<20)
1043#define OAREPORTTRIG6_INVERT_C_1 (1<<21)
1044#define OAREPORTTRIG6_INVERT_D_0 (1<<22)
1045#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23)
1046#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)
1047
1048#define OAREPORTTRIG7 _MMIO(0x2758)
1049#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
1050#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
1051#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1052#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1053#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1054#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1055#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1056#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1057#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1058
1059#define OAREPORTTRIG8 _MMIO(0x275c)
1060#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1061#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1062#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1063#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1064#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1065#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1066#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1067#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1068#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1069
Robert Braggd7965152016-11-07 19:49:52 +00001070/* CECX_0 */
1071#define OACEC_COMPARE_LESS_OR_EQUAL 6
1072#define OACEC_COMPARE_NOT_EQUAL 5
1073#define OACEC_COMPARE_LESS_THAN 4
1074#define OACEC_COMPARE_GREATER_OR_EQUAL 3
1075#define OACEC_COMPARE_EQUAL 2
1076#define OACEC_COMPARE_GREATER_THAN 1
1077#define OACEC_COMPARE_ANY_EQUAL 0
1078
1079#define OACEC_COMPARE_VALUE_MASK 0xffff
1080#define OACEC_COMPARE_VALUE_SHIFT 3
1081
1082#define OACEC_SELECT_NOA (0<<19)
1083#define OACEC_SELECT_PREV (1<<19)
1084#define OACEC_SELECT_BOOLEAN (2<<19)
1085
1086/* CECX_1 */
1087#define OACEC_MASK_MASK 0xffff
1088#define OACEC_CONSIDERATIONS_MASK 0xffff
1089#define OACEC_CONSIDERATIONS_SHIFT 16
1090
1091#define OACEC0_0 _MMIO(0x2770)
1092#define OACEC0_1 _MMIO(0x2774)
1093#define OACEC1_0 _MMIO(0x2778)
1094#define OACEC1_1 _MMIO(0x277c)
1095#define OACEC2_0 _MMIO(0x2780)
1096#define OACEC2_1 _MMIO(0x2784)
1097#define OACEC3_0 _MMIO(0x2788)
1098#define OACEC3_1 _MMIO(0x278c)
1099#define OACEC4_0 _MMIO(0x2790)
1100#define OACEC4_1 _MMIO(0x2794)
1101#define OACEC5_0 _MMIO(0x2798)
1102#define OACEC5_1 _MMIO(0x279c)
1103#define OACEC6_0 _MMIO(0x27a0)
1104#define OACEC6_1 _MMIO(0x27a4)
1105#define OACEC7_0 _MMIO(0x27a8)
1106#define OACEC7_1 _MMIO(0x27ac)
1107
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001108/* OA perf counters */
1109#define OA_PERFCNT1_LO _MMIO(0x91B8)
1110#define OA_PERFCNT1_HI _MMIO(0x91BC)
1111#define OA_PERFCNT2_LO _MMIO(0x91C0)
1112#define OA_PERFCNT2_HI _MMIO(0x91C4)
Lionel Landwerlin95690a02017-11-10 19:08:43 +00001113#define OA_PERFCNT3_LO _MMIO(0x91C8)
1114#define OA_PERFCNT3_HI _MMIO(0x91CC)
1115#define OA_PERFCNT4_LO _MMIO(0x91D8)
1116#define OA_PERFCNT4_HI _MMIO(0x91DC)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001117
1118#define OA_PERFMATRIX_LO _MMIO(0x91C8)
1119#define OA_PERFMATRIX_HI _MMIO(0x91CC)
1120
1121/* RPM unit config (Gen8+) */
1122#define RPM_CONFIG0 _MMIO(0x0D00)
Lionel Landwerlindab91782017-11-10 19:08:44 +00001123#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1124#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1125#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1126#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1127#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1128#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1129
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001130#define RPM_CONFIG1 _MMIO(0x0D04)
Lionel Landwerlin95690a02017-11-10 19:08:43 +00001131#define GEN10_GT_NOA_ENABLE (1 << 9)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001132
Lionel Landwerlindab91782017-11-10 19:08:44 +00001133/* GPM unit config (Gen9+) */
1134#define CTC_MODE _MMIO(0xA26C)
1135#define CTC_SOURCE_PARAMETER_MASK 1
1136#define CTC_SOURCE_CRYSTAL_CLOCK 0
1137#define CTC_SOURCE_DIVIDE_LOGIC 1
1138#define CTC_SHIFT_PARAMETER_SHIFT 1
1139#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1140
Lionel Landwerlin58885762017-11-10 19:08:42 +00001141/* RCP unit config (Gen8+) */
1142#define RCP_CONFIG _MMIO(0x0D08)
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001143
Lionel Landwerlina54b19f2017-11-10 19:08:39 +00001144/* NOA (HSW) */
1145#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1146#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1147#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1148#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1149#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1150#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1151#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1152#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1153#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1154#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1155
1156#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1157
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001158/* NOA (Gen8+) */
1159#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1160
1161#define MICRO_BP0_0 _MMIO(0x9800)
1162#define MICRO_BP0_2 _MMIO(0x9804)
1163#define MICRO_BP0_1 _MMIO(0x9808)
1164
1165#define MICRO_BP1_0 _MMIO(0x980C)
1166#define MICRO_BP1_2 _MMIO(0x9810)
1167#define MICRO_BP1_1 _MMIO(0x9814)
1168
1169#define MICRO_BP2_0 _MMIO(0x9818)
1170#define MICRO_BP2_2 _MMIO(0x981C)
1171#define MICRO_BP2_1 _MMIO(0x9820)
1172
1173#define MICRO_BP3_0 _MMIO(0x9824)
1174#define MICRO_BP3_2 _MMIO(0x9828)
1175#define MICRO_BP3_1 _MMIO(0x982C)
1176
1177#define MICRO_BP_TRIGGER _MMIO(0x9830)
1178#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1179#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1180#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1181
1182#define GDT_CHICKEN_BITS _MMIO(0x9840)
1183#define GT_NOA_ENABLE 0x00000080
1184
1185#define NOA_DATA _MMIO(0x986C)
1186#define NOA_WRITE _MMIO(0x9888)
Kenneth Graunke180b8132014-03-25 22:52:03 -07001187
Brad Volkin220375a2014-02-18 10:15:51 -08001188#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1189#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001190#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
Brad Volkin220375a2014-02-18 10:15:51 -08001191
Brad Volkin5947de92014-02-18 10:15:50 -08001192/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001193 * Reset registers
1194 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001195#define DEBUG_RESET_I830 _MMIO(0x6070)
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001196#define DEBUG_RESET_FULL (1<<7)
1197#define DEBUG_RESET_RENDER (1<<8)
1198#define DEBUG_RESET_DISPLAY (1<<9)
1199
Jesse Barnes57f350b2012-03-28 13:39:25 -07001200/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001201 * IOSF sideband
1202 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001203#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001204#define IOSF_DEVFN_SHIFT 24
1205#define IOSF_OPCODE_SHIFT 16
1206#define IOSF_PORT_SHIFT 8
1207#define IOSF_BYTE_ENABLES_SHIFT 4
1208#define IOSF_BAR_SHIFT 1
1209#define IOSF_SB_BUSY (1<<0)
Jani Nikula4688d452016-02-04 12:50:53 +02001210#define IOSF_PORT_BUNIT 0x03
1211#define IOSF_PORT_PUNIT 0x04
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001212#define IOSF_PORT_NC 0x11
1213#define IOSF_PORT_DPIO 0x12
Jani Nikulae9f882a2013-08-27 15:12:14 +03001214#define IOSF_PORT_GPIO_NC 0x13
1215#define IOSF_PORT_CCK 0x14
Jani Nikula4688d452016-02-04 12:50:53 +02001216#define IOSF_PORT_DPIO_2 0x1a
1217#define IOSF_PORT_FLISDSI 0x1b
Deepak Mdfb19ed2016-02-04 18:55:15 +02001218#define IOSF_PORT_GPIO_SC 0x48
1219#define IOSF_PORT_GPIO_SUS 0xa8
Jani Nikula4688d452016-02-04 12:50:53 +02001220#define IOSF_PORT_CCU 0xa9
Jani Nikula7071af92016-03-18 13:11:15 +02001221#define CHV_IOSF_PORT_GPIO_N 0x13
1222#define CHV_IOSF_PORT_GPIO_SE 0x48
1223#define CHV_IOSF_PORT_GPIO_E 0xa8
1224#define CHV_IOSF_PORT_GPIO_SW 0xb2
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001225#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1226#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001227
Jesse Barnes30a970c2013-11-04 13:48:12 -08001228/* See configdb bunit SB addr map */
1229#define BUNIT_REG_BISOC 0x11
1230
Jesse Barnes30a970c2013-11-04 13:48:12 -08001231#define PUNIT_REG_DSPFREQ 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +03001232#define DSPFREQSTAT_SHIFT_CHV 24
1233#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1234#define DSPFREQGUAR_SHIFT_CHV 8
1235#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -08001236#define DSPFREQSTAT_SHIFT 30
1237#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1238#define DSPFREQGUAR_SHIFT 14
1239#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjäläcfb41412015-03-05 21:19:51 +02001240#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1241#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1242#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
Ville Syrjälä26972b02014-06-28 02:04:11 +03001243#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1244#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1245#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1246#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1247#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1248#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1249#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1250#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1251#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1252#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1253#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1254#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +02001255
Jani Nikulac3fdb9d2017-08-10 15:29:43 +03001256/*
Imre Deak438b8dc2017-07-11 23:42:30 +03001257 * i915_power_well_id:
1258 *
1259 * Platform specific IDs used to look up power wells and - except for custom
1260 * power wells - to define request/status register flag bit positions. As such
1261 * the set of IDs on a given platform must be unique and except for custom
1262 * power wells their value must stay fixed.
1263 */
1264enum i915_power_well_id {
1265 /*
Imre Deak120b56a2017-07-11 23:42:31 +03001266 * I830
1267 * - custom power well
1268 */
1269 I830_DISP_PW_PIPES = 0,
1270
1271 /*
Imre Deak438b8dc2017-07-11 23:42:30 +03001272 * VLV/CHV
1273 * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1274 * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1275 */
Imre Deaka30180a2014-03-04 19:23:02 +02001276 PUNIT_POWER_WELL_RENDER = 0,
1277 PUNIT_POWER_WELL_MEDIA = 1,
1278 PUNIT_POWER_WELL_DISP2D = 3,
1279 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1280 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1281 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1282 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1283 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1284 PUNIT_POWER_WELL_DPIO_RX0 = 10,
1285 PUNIT_POWER_WELL_DPIO_RX1 = 11,
Ville Syrjälä5d6f7ea2014-06-28 02:04:08 +03001286 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
Imre Deakf49193c2017-07-06 17:40:23 +03001287 /* - custom power well */
1288 CHV_DISP_PW_PIPE_A, /* 13 */
Imre Deaka30180a2014-03-04 19:23:02 +02001289
Imre Deak438b8dc2017-07-11 23:42:30 +03001290 /*
Imre Deakfb9248e2017-07-11 23:42:32 +03001291 * HSW/BDW
Imre Deak9c3a16c2017-08-14 18:15:30 +03001292 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
Imre Deakfb9248e2017-07-11 23:42:32 +03001293 */
1294 HSW_DISP_PW_GLOBAL = 15,
1295
1296 /*
Imre Deak438b8dc2017-07-11 23:42:30 +03001297 * GEN9+
Imre Deak9c3a16c2017-08-14 18:15:30 +03001298 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
Imre Deak438b8dc2017-07-11 23:42:30 +03001299 */
1300 SKL_DISP_PW_MISC_IO = 0,
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00001301 SKL_DISP_PW_DDI_A_E,
Ander Conselvan de Oliveira0d039262016-12-02 10:23:50 +02001302 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
Ville Syrjälä8bcd3dd2017-06-06 13:30:39 -07001303 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00001304 SKL_DISP_PW_DDI_B,
1305 SKL_DISP_PW_DDI_C,
1306 SKL_DISP_PW_DDI_D,
Ander Conselvan de Oliveira0d039262016-12-02 10:23:50 +02001307
1308 GLK_DISP_PW_AUX_A = 8,
1309 GLK_DISP_PW_AUX_B,
1310 GLK_DISP_PW_AUX_C,
Ville Syrjälä8bcd3dd2017-06-06 13:30:39 -07001311 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1312 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1313 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1314 CNL_DISP_PW_AUX_D,
Rodrigo Vivia324fca2018-01-29 15:22:15 -08001315 CNL_DISP_PW_AUX_F,
Ander Conselvan de Oliveira0d039262016-12-02 10:23:50 +02001316
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00001317 SKL_DISP_PW_1 = 14,
1318 SKL_DISP_PW_2,
Imre Deak56fcfd62015-11-04 19:24:10 +02001319
Imre Deak438b8dc2017-07-11 23:42:30 +03001320 /* - custom power wells */
Patrik Jakobsson9f836f92015-11-16 16:20:01 +01001321 SKL_DISP_PW_DC_OFF,
Imre Deak9c8d0b82016-06-13 16:44:34 +03001322 BXT_DPIO_CMN_A,
1323 BXT_DPIO_CMN_BC,
Imre Deak438b8dc2017-07-11 23:42:30 +03001324 GLK_DPIO_CMN_C, /* 19 */
1325
1326 /*
1327 * Multiple platforms.
1328 * Must start following the highest ID of any platform.
1329 * - custom power wells
1330 */
1331 I915_DISP_PW_ALWAYS_ON = 20,
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00001332};
1333
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +08001334#define PUNIT_REG_PWRGT_CTRL 0x60
1335#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +02001336#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1337#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1338#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1339#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1340#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +08001341
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001342#define PUNIT_REG_GPU_LFM 0xd3
1343#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1344#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläc8e96272014-11-07 21:33:44 +02001345#define GPLLENABLE (1<<4)
Ville Syrjäläe8474402013-06-26 17:43:24 +03001346#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001347#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -04001348#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001349
1350#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1351#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1352
Deepak S095acd52015-01-17 11:05:59 +05301353#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1354#define FB_GFX_FREQ_FUSE_MASK 0xff
1355#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1356#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1357#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1358
1359#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1360#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1361
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +02001362#define PUNIT_REG_DDR_SETUP2 0x139
1363#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1364#define FORCE_DDR_LOW_FREQ (1 << 1)
1365#define FORCE_DDR_HIGH_FREQ (1 << 0)
1366
Deepak S2b6b3a02014-05-27 15:59:30 +05301367#define PUNIT_GPU_STATUS_REG 0xdb
1368#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1369#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1370#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1371#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1372
1373#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1374#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1375#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1376
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001377#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1378#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1379#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1380#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1381#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1382#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1383#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1384#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1385#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1386#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1387
Deepak S3ef62342015-04-29 08:36:24 +05301388#define VLV_TURBO_SOC_OVERRIDE 0x04
1389#define VLV_OVERRIDE_EN 1
1390#define VLV_SOC_TDP_EN (1 << 1)
1391#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1392#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1393
ymohanmabe4fc042013-08-27 23:40:56 +03001394/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08001395#define CCK_FUSE_REG 0x8
1396#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +03001397#define CCK_REG_DSI_PLL_FUSE 0x44
1398#define CCK_REG_DSI_PLL_CONTROL 0x48
1399#define DSI_PLL_VCO_EN (1 << 31)
1400#define DSI_PLL_LDO_GATE (1 << 30)
1401#define DSI_PLL_P1_POST_DIV_SHIFT 17
1402#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1403#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1404#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1405#define DSI_PLL_MUX_MASK (3 << 9)
1406#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1407#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1408#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1409#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1410#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1411#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1412#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1413#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1414#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1415#define DSI_PLL_LOCK (1 << 0)
1416#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1417#define DSI_PLL_LFSR (1 << 31)
1418#define DSI_PLL_FRACTION_EN (1 << 30)
1419#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1420#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1421#define DSI_PLL_USYNC_CNT_SHIFT 18
1422#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1423#define DSI_PLL_N1_DIV_SHIFT 16
1424#define DSI_PLL_N1_DIV_MASK (3 << 16)
1425#define DSI_PLL_M1_DIV_SHIFT 0
1426#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03001427#define CCK_CZ_CLOCK_CONTROL 0x62
Ville Syrjäläc30fec62016-03-04 21:43:02 +02001428#define CCK_GPLL_CLOCK_CONTROL 0x67
Jesse Barnes30a970c2013-11-04 13:48:12 -08001429#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä35d38d12016-03-02 17:22:16 +02001430#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
Vandana Kannan87d5d252015-09-24 23:29:17 +03001431#define CCK_TRUNK_FORCE_ON (1 << 17)
1432#define CCK_TRUNK_FORCE_OFF (1 << 16)
1433#define CCK_FREQUENCY_STATUS (0x1f << 8)
1434#define CCK_FREQUENCY_STATUS_SHIFT 8
1435#define CCK_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +03001436
Ander Conselvan de Oliveiraf38861b2016-10-06 19:22:18 +03001437/* DPIO registers */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001438#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +03001439
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001440#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001441#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
1442#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
1443#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001444#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001445
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001446#define DPIO_PHY(pipe) ((pipe) >> 1)
1447#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1448
Daniel Vetter598fac62013-04-18 22:01:46 +02001449/*
1450 * Per pipe/PLL DPIO regs
1451 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001452#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -07001453#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +02001454#define DPIO_POST_DIV_DAC 0
1455#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1456#define DPIO_POST_DIV_LVDS1 2
1457#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -07001458#define DPIO_K_SHIFT (24) /* 4 bits */
1459#define DPIO_P1_SHIFT (21) /* 3 bits */
1460#define DPIO_P2_SHIFT (16) /* 5 bits */
1461#define DPIO_N_SHIFT (12) /* 4 bits */
1462#define DPIO_ENABLE_CALIBRATION (1<<11)
1463#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1464#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001465#define _VLV_PLL_DW3_CH1 0x802c
1466#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001467
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001468#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -07001469#define DPIO_REFSEL_OVERRIDE 27
1470#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1471#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1472#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301473#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -07001474#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1475#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001476#define _VLV_PLL_DW5_CH1 0x8034
1477#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001478
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001479#define _VLV_PLL_DW7_CH0 0x801c
1480#define _VLV_PLL_DW7_CH1 0x803c
1481#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001482
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001483#define _VLV_PLL_DW8_CH0 0x8040
1484#define _VLV_PLL_DW8_CH1 0x8060
1485#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001486
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001487#define VLV_PLL_DW9_BCAST 0xc044
1488#define _VLV_PLL_DW9_CH0 0x8044
1489#define _VLV_PLL_DW9_CH1 0x8064
1490#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001491
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001492#define _VLV_PLL_DW10_CH0 0x8048
1493#define _VLV_PLL_DW10_CH1 0x8068
1494#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001495
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001496#define _VLV_PLL_DW11_CH0 0x804c
1497#define _VLV_PLL_DW11_CH1 0x806c
1498#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -07001499
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001500/* Spec for ref block start counts at DW10 */
1501#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +02001502
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001503#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001504
Daniel Vetter598fac62013-04-18 22:01:46 +02001505/*
1506 * Per DDI channel DPIO regs
1507 */
1508
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001509#define _VLV_PCS_DW0_CH0 0x8200
1510#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +02001511#define DPIO_PCS_TX_LANE2_RESET (1<<16)
1512#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001513#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
1514#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001515#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001516
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001517#define _VLV_PCS01_DW0_CH0 0x200
1518#define _VLV_PCS23_DW0_CH0 0x400
1519#define _VLV_PCS01_DW0_CH1 0x2600
1520#define _VLV_PCS23_DW0_CH1 0x2800
1521#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1522#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1523
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001524#define _VLV_PCS_DW1_CH0 0x8204
1525#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +03001526#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +02001527#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1528#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1529#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1530#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001531#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001532
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001533#define _VLV_PCS01_DW1_CH0 0x204
1534#define _VLV_PCS23_DW1_CH0 0x404
1535#define _VLV_PCS01_DW1_CH1 0x2604
1536#define _VLV_PCS23_DW1_CH1 0x2804
1537#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1538#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1539
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001540#define _VLV_PCS_DW8_CH0 0x8220
1541#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +03001542#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1543#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001544#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001545
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001546#define _VLV_PCS01_DW8_CH0 0x0220
1547#define _VLV_PCS23_DW8_CH0 0x0420
1548#define _VLV_PCS01_DW8_CH1 0x2620
1549#define _VLV_PCS23_DW8_CH1 0x2820
1550#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1551#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001552
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001553#define _VLV_PCS_DW9_CH0 0x8224
1554#define _VLV_PCS_DW9_CH1 0x8424
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001555#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1556#define DPIO_PCS_TX2MARGIN_000 (0<<13)
1557#define DPIO_PCS_TX2MARGIN_101 (1<<13)
1558#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1559#define DPIO_PCS_TX1MARGIN_000 (0<<10)
1560#define DPIO_PCS_TX1MARGIN_101 (1<<10)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001561#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001562
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001563#define _VLV_PCS01_DW9_CH0 0x224
1564#define _VLV_PCS23_DW9_CH0 0x424
1565#define _VLV_PCS01_DW9_CH1 0x2624
1566#define _VLV_PCS23_DW9_CH1 0x2824
1567#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1568#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1569
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001570#define _CHV_PCS_DW10_CH0 0x8228
1571#define _CHV_PCS_DW10_CH1 0x8428
1572#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1573#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001574#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1575#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1576#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1577#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1578#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1579#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001580#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1581
Ville Syrjälä1966e592014-04-09 13:29:04 +03001582#define _VLV_PCS01_DW10_CH0 0x0228
1583#define _VLV_PCS23_DW10_CH0 0x0428
1584#define _VLV_PCS01_DW10_CH1 0x2628
1585#define _VLV_PCS23_DW10_CH1 0x2828
1586#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1587#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1588
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001589#define _VLV_PCS_DW11_CH0 0x822c
1590#define _VLV_PCS_DW11_CH1 0x842c
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001591#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001592#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1593#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1594#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001595#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001596
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001597#define _VLV_PCS01_DW11_CH0 0x022c
1598#define _VLV_PCS23_DW11_CH0 0x042c
1599#define _VLV_PCS01_DW11_CH1 0x262c
1600#define _VLV_PCS23_DW11_CH1 0x282c
Ville Syrjälä142d2ec2014-10-16 20:52:32 +03001601#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1602#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001603
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001604#define _VLV_PCS01_DW12_CH0 0x0230
1605#define _VLV_PCS23_DW12_CH0 0x0430
1606#define _VLV_PCS01_DW12_CH1 0x2630
1607#define _VLV_PCS23_DW12_CH1 0x2830
1608#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1609#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1610
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001611#define _VLV_PCS_DW12_CH0 0x8230
1612#define _VLV_PCS_DW12_CH1 0x8430
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001613#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1614#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1615#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1616#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1617#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001618#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001619
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001620#define _VLV_PCS_DW14_CH0 0x8238
1621#define _VLV_PCS_DW14_CH1 0x8438
1622#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001623
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001624#define _VLV_PCS_DW23_CH0 0x825c
1625#define _VLV_PCS_DW23_CH1 0x845c
1626#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001627
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001628#define _VLV_TX_DW2_CH0 0x8288
1629#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001630#define DPIO_SWING_MARGIN000_SHIFT 16
1631#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001632#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001633#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001634
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001635#define _VLV_TX_DW3_CH0 0x828c
1636#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001637/* The following bit for CHV phy */
1638#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001639#define DPIO_SWING_MARGIN101_SHIFT 16
1640#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001641#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1642
1643#define _VLV_TX_DW4_CH0 0x8290
1644#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001645#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1646#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001647#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1648#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001649#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1650
1651#define _VLV_TX3_DW4_CH0 0x690
1652#define _VLV_TX3_DW4_CH1 0x2a90
1653#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1654
1655#define _VLV_TX_DW5_CH0 0x8294
1656#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +02001657#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001658#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001659
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001660#define _VLV_TX_DW11_CH0 0x82ac
1661#define _VLV_TX_DW11_CH1 0x84ac
1662#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001663
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001664#define _VLV_TX_DW14_CH0 0x82b8
1665#define _VLV_TX_DW14_CH1 0x84b8
1666#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301667
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001668/* CHV dpPhy registers */
1669#define _CHV_PLL_DW0_CH0 0x8000
1670#define _CHV_PLL_DW0_CH1 0x8180
1671#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1672
1673#define _CHV_PLL_DW1_CH0 0x8004
1674#define _CHV_PLL_DW1_CH1 0x8184
1675#define DPIO_CHV_N_DIV_SHIFT 8
1676#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1677#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1678
1679#define _CHV_PLL_DW2_CH0 0x8008
1680#define _CHV_PLL_DW2_CH1 0x8188
1681#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1682
1683#define _CHV_PLL_DW3_CH0 0x800c
1684#define _CHV_PLL_DW3_CH1 0x818c
1685#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1686#define DPIO_CHV_FIRST_MOD (0 << 8)
1687#define DPIO_CHV_SECOND_MOD (1 << 8)
1688#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05301689#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001690#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1691
1692#define _CHV_PLL_DW6_CH0 0x8018
1693#define _CHV_PLL_DW6_CH1 0x8198
1694#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1695#define DPIO_CHV_INT_COEFF_SHIFT 8
1696#define DPIO_CHV_PROP_COEFF_SHIFT 0
1697#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1698
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301699#define _CHV_PLL_DW8_CH0 0x8020
1700#define _CHV_PLL_DW8_CH1 0x81A0
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05301701#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1702#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301703#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1704
1705#define _CHV_PLL_DW9_CH0 0x8024
1706#define _CHV_PLL_DW9_CH1 0x81A4
1707#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05301708#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301709#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1710#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1711
Ville Syrjälä6669e392015-07-08 23:46:00 +03001712#define _CHV_CMN_DW0_CH0 0x8100
1713#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1714#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1715#define DPIO_ALLDL_POWERDOWN (1 << 1)
1716#define DPIO_ANYDL_POWERDOWN (1 << 0)
1717
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001718#define _CHV_CMN_DW5_CH0 0x8114
1719#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1720#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1721#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1722#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1723#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1724#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1725#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1726#define CHV_BUFLEFTENA1_MASK (3 << 22)
1727
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001728#define _CHV_CMN_DW13_CH0 0x8134
1729#define _CHV_CMN_DW0_CH1 0x8080
1730#define DPIO_CHV_S1_DIV_SHIFT 21
1731#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1732#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1733#define DPIO_CHV_K_DIV_SHIFT 4
1734#define DPIO_PLL_FREQLOCK (1 << 1)
1735#define DPIO_PLL_LOCK (1 << 0)
1736#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1737
1738#define _CHV_CMN_DW14_CH0 0x8138
1739#define _CHV_CMN_DW1_CH1 0x8084
1740#define DPIO_AFC_RECAL (1 << 14)
1741#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001742#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1743#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1744#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1745#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1746#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1747#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1748#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1749#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001750#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1751
Ville Syrjälä9197c882014-04-09 13:29:05 +03001752#define _CHV_CMN_DW19_CH0 0x814c
1753#define _CHV_CMN_DW6_CH1 0x8098
Ville Syrjälä6669e392015-07-08 23:46:00 +03001754#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1755#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001756#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
Ville Syrjälä9197c882014-04-09 13:29:05 +03001757#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001758
Ville Syrjälä9197c882014-04-09 13:29:05 +03001759#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1760
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001761#define CHV_CMN_DW28 0x8170
1762#define DPIO_CL1POWERDOWNEN (1 << 23)
1763#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
Ville Syrjäläee279212015-07-08 23:45:57 +03001764#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1765#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1766#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1767#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001768
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001769#define CHV_CMN_DW30 0x8178
Ville Syrjälä3e288782015-07-08 23:45:58 +03001770#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001771#define DPIO_LRC_BYPASS (1 << 3)
1772
1773#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1774 (lane) * 0x200 + (offset))
1775
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001776#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1777#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1778#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1779#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1780#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1781#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1782#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1783#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1784#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1785#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1786#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001787#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1788#define DPIO_FRC_LATENCY_SHFIT 8
1789#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1790#define DPIO_UPAR_SHIFT 30
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301791
1792/* BXT PHY registers */
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001793#define _BXT_PHY0_BASE 0x6C000
1794#define _BXT_PHY1_BASE 0x162000
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001795#define _BXT_PHY2_BASE 0x163000
1796#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1797 _BXT_PHY1_BASE, \
1798 _BXT_PHY2_BASE)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001799
1800#define _BXT_PHY(phy, reg) \
1801 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1802
1803#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1804 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1805 (reg_ch1) - _BXT_PHY0_BASE))
1806#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1807 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301808
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001809#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
Uma Shankar1881a422017-01-25 19:43:23 +05301810#define MIPIO_RST_CTRL (1 << 2)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301811
Imre Deake93da0a2016-06-13 16:44:37 +03001812#define _BXT_PHY_CTL_DDI_A 0x64C00
1813#define _BXT_PHY_CTL_DDI_B 0x64C10
1814#define _BXT_PHY_CTL_DDI_C 0x64C20
1815#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1816#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1817#define BXT_PHY_LANE_ENABLED (1 << 8)
1818#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1819 _BXT_PHY_CTL_DDI_B)
1820
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301821#define _PHY_CTL_FAMILY_EDP 0x64C80
1822#define _PHY_CTL_FAMILY_DDI 0x64C90
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001823#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301824#define COMMON_RESET_DIS (1 << 31)
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02001825#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1826 _PHY_CTL_FAMILY_EDP, \
1827 _PHY_CTL_FAMILY_DDI_C)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301828
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301829/* BXT PHY PLL registers */
1830#define _PORT_PLL_A 0x46074
1831#define _PORT_PLL_B 0x46078
1832#define _PORT_PLL_C 0x4607c
1833#define PORT_PLL_ENABLE (1 << 31)
1834#define PORT_PLL_LOCK (1 << 30)
1835#define PORT_PLL_REF_SEL (1 << 27)
Madhav Chauhanf7044dd2016-12-02 10:23:53 +02001836#define PORT_PLL_POWER_ENABLE (1 << 26)
1837#define PORT_PLL_POWER_STATE (1 << 25)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001838#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301839
1840#define _PORT_PLL_EBB_0_A 0x162034
1841#define _PORT_PLL_EBB_0_B 0x6C034
1842#define _PORT_PLL_EBB_0_C 0x6C340
Imre Deakaa610dc2015-06-22 23:35:52 +03001843#define PORT_PLL_P1_SHIFT 13
1844#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1845#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1846#define PORT_PLL_P2_SHIFT 8
1847#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1848#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001849#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1850 _PORT_PLL_EBB_0_B, \
1851 _PORT_PLL_EBB_0_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301852
1853#define _PORT_PLL_EBB_4_A 0x162038
1854#define _PORT_PLL_EBB_4_B 0x6C038
1855#define _PORT_PLL_EBB_4_C 0x6C344
1856#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1857#define PORT_PLL_RECALIBRATE (1 << 14)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001858#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1859 _PORT_PLL_EBB_4_B, \
1860 _PORT_PLL_EBB_4_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301861
1862#define _PORT_PLL_0_A 0x162100
1863#define _PORT_PLL_0_B 0x6C100
1864#define _PORT_PLL_0_C 0x6C380
1865/* PORT_PLL_0_A */
1866#define PORT_PLL_M2_MASK 0xFF
1867/* PORT_PLL_1_A */
Imre Deakaa610dc2015-06-22 23:35:52 +03001868#define PORT_PLL_N_SHIFT 8
1869#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1870#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301871/* PORT_PLL_2_A */
1872#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1873/* PORT_PLL_3_A */
1874#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1875/* PORT_PLL_6_A */
1876#define PORT_PLL_PROP_COEFF_MASK 0xF
1877#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1878#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1879#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1880#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1881/* PORT_PLL_8_A */
1882#define PORT_PLL_TARGET_CNT_MASK 0x3FF
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301883/* PORT_PLL_9_A */
Imre Deak05712c12015-06-18 17:25:54 +03001884#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1885#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301886/* PORT_PLL_10_A */
1887#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
Vandana Kannane6292552015-07-01 17:02:57 +05301888#define PORT_PLL_DCO_AMP_DEFAULT 15
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301889#define PORT_PLL_DCO_AMP_MASK 0x3c00
Ville Syrjälä68d97532015-09-18 20:03:39 +03001890#define PORT_PLL_DCO_AMP(x) ((x)<<10)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001891#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1892 _PORT_PLL_0_B, \
1893 _PORT_PLL_0_C)
1894#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1895 (idx) * 4)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301896
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301897/* BXT PHY common lane registers */
1898#define _PORT_CL1CM_DW0_A 0x162000
1899#define _PORT_CL1CM_DW0_BC 0x6C000
1900#define PHY_POWER_GOOD (1 << 16)
Vandana Kannanb61e7992016-03-31 23:15:54 +05301901#define PHY_RESERVED (1 << 7)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001902#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301903
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07001904#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1905#define CL_POWER_DOWN_ENABLE (1 << 4)
Rodrigo Vivicf54ca82017-06-09 15:26:08 -07001906#define SUS_CLOCK_CONFIG (3 << 0)
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07001907
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301908#define _PORT_CL1CM_DW9_A 0x162024
1909#define _PORT_CL1CM_DW9_BC 0x6C024
1910#define IREF0RC_OFFSET_SHIFT 8
1911#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001912#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301913
1914#define _PORT_CL1CM_DW10_A 0x162028
1915#define _PORT_CL1CM_DW10_BC 0x6C028
1916#define IREF1RC_OFFSET_SHIFT 8
1917#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001918#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301919
1920#define _PORT_CL1CM_DW28_A 0x162070
1921#define _PORT_CL1CM_DW28_BC 0x6C070
1922#define OCL1_POWER_DOWN_EN (1 << 23)
1923#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1924#define SUS_CLK_CONFIG 0x3
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001925#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301926
1927#define _PORT_CL1CM_DW30_A 0x162078
1928#define _PORT_CL1CM_DW30_BC 0x6C078
1929#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03001930#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301931
Rodrigo Vivi04416102017-06-09 15:26:06 -07001932#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1933#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1934#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1935#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1936#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1937#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1938#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1939#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1940#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1941#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1942#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
1943 _CNL_PORT_PCS_DW1_GRP_AE, \
1944 _CNL_PORT_PCS_DW1_GRP_B, \
1945 _CNL_PORT_PCS_DW1_GRP_C, \
1946 _CNL_PORT_PCS_DW1_GRP_D, \
1947 _CNL_PORT_PCS_DW1_GRP_AE, \
1948 _CNL_PORT_PCS_DW1_GRP_F)
1949#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
1950 _CNL_PORT_PCS_DW1_LN0_AE, \
1951 _CNL_PORT_PCS_DW1_LN0_B, \
1952 _CNL_PORT_PCS_DW1_LN0_C, \
1953 _CNL_PORT_PCS_DW1_LN0_D, \
1954 _CNL_PORT_PCS_DW1_LN0_AE, \
1955 _CNL_PORT_PCS_DW1_LN0_F)
1956#define COMMON_KEEPER_EN (1 << 26)
1957
1958#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
1959#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
1960#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
1961#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
1962#define _CNL_PORT_TX_DW2_GRP_F 0x162A48
1963#define _CNL_PORT_TX_DW2_LN0_AE 0x162448
1964#define _CNL_PORT_TX_DW2_LN0_B 0x162648
1965#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
1966#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
Rodrigo Vivi8f942ed2018-01-29 15:22:17 -08001967#define _CNL_PORT_TX_DW2_LN0_F 0x162848
Rodrigo Vivi04416102017-06-09 15:26:06 -07001968#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
1969 _CNL_PORT_TX_DW2_GRP_AE, \
1970 _CNL_PORT_TX_DW2_GRP_B, \
1971 _CNL_PORT_TX_DW2_GRP_C, \
1972 _CNL_PORT_TX_DW2_GRP_D, \
1973 _CNL_PORT_TX_DW2_GRP_AE, \
1974 _CNL_PORT_TX_DW2_GRP_F)
1975#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
1976 _CNL_PORT_TX_DW2_LN0_AE, \
1977 _CNL_PORT_TX_DW2_LN0_B, \
1978 _CNL_PORT_TX_DW2_LN0_C, \
1979 _CNL_PORT_TX_DW2_LN0_D, \
1980 _CNL_PORT_TX_DW2_LN0_AE, \
1981 _CNL_PORT_TX_DW2_LN0_F)
1982#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07001983#define SWING_SEL_UPPER_MASK (1 << 15)
Rodrigo Vivi04416102017-06-09 15:26:06 -07001984#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07001985#define SWING_SEL_LOWER_MASK (0x7 << 11)
Rodrigo Vivi04416102017-06-09 15:26:06 -07001986#define RCOMP_SCALAR(x) ((x) << 0)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07001987#define RCOMP_SCALAR_MASK (0xFF << 0)
Rodrigo Vivi04416102017-06-09 15:26:06 -07001988
1989#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
1990#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
1991#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
1992#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
1993#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
1994#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1995#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1996#define _CNL_PORT_TX_DW4_LN0_B 0x162650
1997#define _CNL_PORT_TX_DW4_LN0_C 0x162C50
1998#define _CNL_PORT_TX_DW4_LN0_D 0x162E50
1999#define _CNL_PORT_TX_DW4_LN0_F 0x162850
2000#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
2001 _CNL_PORT_TX_DW4_GRP_AE, \
2002 _CNL_PORT_TX_DW4_GRP_B, \
2003 _CNL_PORT_TX_DW4_GRP_C, \
2004 _CNL_PORT_TX_DW4_GRP_D, \
2005 _CNL_PORT_TX_DW4_GRP_AE, \
2006 _CNL_PORT_TX_DW4_GRP_F)
2007#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
2008 _CNL_PORT_TX_DW4_LN0_AE, \
2009 _CNL_PORT_TX_DW4_LN1_AE, \
2010 _CNL_PORT_TX_DW4_LN0_B, \
2011 _CNL_PORT_TX_DW4_LN0_C, \
2012 _CNL_PORT_TX_DW4_LN0_D, \
2013 _CNL_PORT_TX_DW4_LN0_AE, \
2014 _CNL_PORT_TX_DW4_LN0_F)
2015#define LOADGEN_SELECT (1 << 31)
2016#define POST_CURSOR_1(x) ((x) << 12)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002017#define POST_CURSOR_1_MASK (0x3F << 12)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002018#define POST_CURSOR_2(x) ((x) << 6)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002019#define POST_CURSOR_2_MASK (0x3F << 6)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002020#define CURSOR_COEFF(x) ((x) << 0)
Navare, Manasi Dfcace3b2017-06-29 18:14:01 -07002021#define CURSOR_COEFF_MASK (0x3F << 0)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002022
2023#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
2024#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
2025#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
2026#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
2027#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
2028#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
2029#define _CNL_PORT_TX_DW5_LN0_B 0x162654
2030#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
2031#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
2032#define _CNL_PORT_TX_DW5_LN0_F 0x162854
2033#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
2034 _CNL_PORT_TX_DW5_GRP_AE, \
2035 _CNL_PORT_TX_DW5_GRP_B, \
2036 _CNL_PORT_TX_DW5_GRP_C, \
2037 _CNL_PORT_TX_DW5_GRP_D, \
2038 _CNL_PORT_TX_DW5_GRP_AE, \
2039 _CNL_PORT_TX_DW5_GRP_F)
2040#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
2041 _CNL_PORT_TX_DW5_LN0_AE, \
2042 _CNL_PORT_TX_DW5_LN0_B, \
2043 _CNL_PORT_TX_DW5_LN0_C, \
2044 _CNL_PORT_TX_DW5_LN0_D, \
2045 _CNL_PORT_TX_DW5_LN0_AE, \
2046 _CNL_PORT_TX_DW5_LN0_F)
2047#define TX_TRAINING_EN (1 << 31)
2048#define TAP3_DISABLE (1 << 29)
2049#define SCALING_MODE_SEL(x) ((x) << 18)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002050#define SCALING_MODE_SEL_MASK (0x7 << 18)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002051#define RTERM_SELECT(x) ((x) << 3)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002052#define RTERM_SELECT_MASK (0x7 << 3)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002053
2054#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
2055#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
2056#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
2057#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
2058#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
2059#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
2060#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
2061#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
2062#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
2063#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
2064#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
2065 _CNL_PORT_TX_DW7_GRP_AE, \
2066 _CNL_PORT_TX_DW7_GRP_B, \
2067 _CNL_PORT_TX_DW7_GRP_C, \
2068 _CNL_PORT_TX_DW7_GRP_D, \
2069 _CNL_PORT_TX_DW7_GRP_AE, \
2070 _CNL_PORT_TX_DW7_GRP_F)
2071#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
2072 _CNL_PORT_TX_DW7_LN0_AE, \
2073 _CNL_PORT_TX_DW7_LN0_B, \
2074 _CNL_PORT_TX_DW7_LN0_C, \
2075 _CNL_PORT_TX_DW7_LN0_D, \
2076 _CNL_PORT_TX_DW7_LN0_AE, \
2077 _CNL_PORT_TX_DW7_LN0_F)
2078#define N_SCALAR(x) ((x) << 24)
Rodrigo Vivi1f588ae2017-06-19 11:39:32 -07002079#define N_SCALAR_MASK (0x7F << 24)
Rodrigo Vivi04416102017-06-09 15:26:06 -07002080
Ander Conselvan de Oliveira842d4162016-10-06 19:22:20 +03002081/* The spec defines this only for BXT PHY0, but lets assume that this
2082 * would exist for PHY1 too if it had a second channel.
2083 */
2084#define _PORT_CL2CM_DW6_A 0x162358
2085#define _PORT_CL2CM_DW6_BC 0x6C358
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002086#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302087#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2088
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07002089#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2090#define COMP_INIT (1 << 31)
2091#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2092#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2093#define PROCESS_INFO_DOT_0 (0 << 26)
2094#define PROCESS_INFO_DOT_1 (1 << 26)
2095#define PROCESS_INFO_DOT_4 (2 << 26)
2096#define PROCESS_INFO_MASK (7 << 26)
2097#define PROCESS_INFO_SHIFT 26
2098#define VOLTAGE_INFO_0_85V (0 << 24)
2099#define VOLTAGE_INFO_0_95V (1 << 24)
2100#define VOLTAGE_INFO_1_05V (2 << 24)
2101#define VOLTAGE_INFO_MASK (3 << 24)
2102#define VOLTAGE_INFO_SHIFT 24
2103#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2104#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2105
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302106/* BXT PHY Ref registers */
2107#define _PORT_REF_DW3_A 0x16218C
2108#define _PORT_REF_DW3_BC 0x6C18C
2109#define GRC_DONE (1 << 22)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002110#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302111
2112#define _PORT_REF_DW6_A 0x162198
2113#define _PORT_REF_DW6_BC 0x6C198
Imre Deakd1e082f2016-04-01 16:02:33 +03002114#define GRC_CODE_SHIFT 24
2115#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302116#define GRC_CODE_FAST_SHIFT 16
Imre Deakd1e082f2016-04-01 16:02:33 +03002117#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302118#define GRC_CODE_SLOW_SHIFT 8
2119#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2120#define GRC_CODE_NOM_MASK 0xFF
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002121#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302122
2123#define _PORT_REF_DW8_A 0x1621A0
2124#define _PORT_REF_DW8_BC 0x6C1A0
2125#define GRC_DIS (1 << 15)
2126#define GRC_RDY_OVRD (1 << 1)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002127#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302128
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302129/* BXT PHY PCS registers */
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302130#define _PORT_PCS_DW10_LN01_A 0x162428
2131#define _PORT_PCS_DW10_LN01_B 0x6C428
2132#define _PORT_PCS_DW10_LN01_C 0x6C828
2133#define _PORT_PCS_DW10_GRP_A 0x162C28
2134#define _PORT_PCS_DW10_GRP_B 0x6CC28
2135#define _PORT_PCS_DW10_GRP_C 0x6CE28
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002136#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2137 _PORT_PCS_DW10_LN01_B, \
2138 _PORT_PCS_DW10_LN01_C)
2139#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2140 _PORT_PCS_DW10_GRP_B, \
2141 _PORT_PCS_DW10_GRP_C)
2142
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302143#define TX2_SWING_CALC_INIT (1 << 31)
2144#define TX1_SWING_CALC_INIT (1 << 30)
2145
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302146#define _PORT_PCS_DW12_LN01_A 0x162430
2147#define _PORT_PCS_DW12_LN01_B 0x6C430
2148#define _PORT_PCS_DW12_LN01_C 0x6C830
2149#define _PORT_PCS_DW12_LN23_A 0x162630
2150#define _PORT_PCS_DW12_LN23_B 0x6C630
2151#define _PORT_PCS_DW12_LN23_C 0x6CA30
2152#define _PORT_PCS_DW12_GRP_A 0x162c30
2153#define _PORT_PCS_DW12_GRP_B 0x6CC30
2154#define _PORT_PCS_DW12_GRP_C 0x6CE30
2155#define LANESTAGGER_STRAP_OVRD (1 << 6)
2156#define LANE_STAGGER_MASK 0x1F
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002157#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2158 _PORT_PCS_DW12_LN01_B, \
2159 _PORT_PCS_DW12_LN01_C)
2160#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2161 _PORT_PCS_DW12_LN23_B, \
2162 _PORT_PCS_DW12_LN23_C)
2163#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2164 _PORT_PCS_DW12_GRP_B, \
2165 _PORT_PCS_DW12_GRP_C)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302166
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302167/* BXT PHY TX registers */
2168#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2169 ((lane) & 1) * 0x80)
2170
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302171#define _PORT_TX_DW2_LN0_A 0x162508
2172#define _PORT_TX_DW2_LN0_B 0x6C508
2173#define _PORT_TX_DW2_LN0_C 0x6C908
2174#define _PORT_TX_DW2_GRP_A 0x162D08
2175#define _PORT_TX_DW2_GRP_B 0x6CD08
2176#define _PORT_TX_DW2_GRP_C 0x6CF08
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002177#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2178 _PORT_TX_DW2_LN0_B, \
2179 _PORT_TX_DW2_LN0_C)
2180#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2181 _PORT_TX_DW2_GRP_B, \
2182 _PORT_TX_DW2_GRP_C)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302183#define MARGIN_000_SHIFT 16
2184#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2185#define UNIQ_TRANS_SCALE_SHIFT 8
2186#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2187
2188#define _PORT_TX_DW3_LN0_A 0x16250C
2189#define _PORT_TX_DW3_LN0_B 0x6C50C
2190#define _PORT_TX_DW3_LN0_C 0x6C90C
2191#define _PORT_TX_DW3_GRP_A 0x162D0C
2192#define _PORT_TX_DW3_GRP_B 0x6CD0C
2193#define _PORT_TX_DW3_GRP_C 0x6CF0C
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002194#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2195 _PORT_TX_DW3_LN0_B, \
2196 _PORT_TX_DW3_LN0_C)
2197#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2198 _PORT_TX_DW3_GRP_B, \
2199 _PORT_TX_DW3_GRP_C)
Sonika Jindal9c58a042015-09-24 10:22:54 +05302200#define SCALE_DCOMP_METHOD (1 << 26)
2201#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302202
2203#define _PORT_TX_DW4_LN0_A 0x162510
2204#define _PORT_TX_DW4_LN0_B 0x6C510
2205#define _PORT_TX_DW4_LN0_C 0x6C910
2206#define _PORT_TX_DW4_GRP_A 0x162D10
2207#define _PORT_TX_DW4_GRP_B 0x6CD10
2208#define _PORT_TX_DW4_GRP_C 0x6CF10
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002209#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2210 _PORT_TX_DW4_LN0_B, \
2211 _PORT_TX_DW4_LN0_C)
2212#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2213 _PORT_TX_DW4_GRP_B, \
2214 _PORT_TX_DW4_GRP_C)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302215#define DEEMPH_SHIFT 24
2216#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2217
Ander Conselvan de Oliveira51b3ee32016-12-02 10:23:52 +02002218#define _PORT_TX_DW5_LN0_A 0x162514
2219#define _PORT_TX_DW5_LN0_B 0x6C514
2220#define _PORT_TX_DW5_LN0_C 0x6C914
2221#define _PORT_TX_DW5_GRP_A 0x162D14
2222#define _PORT_TX_DW5_GRP_B 0x6CD14
2223#define _PORT_TX_DW5_GRP_C 0x6CF14
2224#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2225 _PORT_TX_DW5_LN0_B, \
2226 _PORT_TX_DW5_LN0_C)
2227#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2228 _PORT_TX_DW5_GRP_B, \
2229 _PORT_TX_DW5_GRP_C)
2230#define DCC_DELAY_RANGE_1 (1 << 9)
2231#define DCC_DELAY_RANGE_2 (1 << 8)
2232
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302233#define _PORT_TX_DW14_LN0_A 0x162538
2234#define _PORT_TX_DW14_LN0_B 0x6C538
2235#define _PORT_TX_DW14_LN0_C 0x6C938
2236#define LATENCY_OPTIM_SHIFT 30
2237#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03002238#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2239 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2240 _PORT_TX_DW14_LN0_C) + \
2241 _BXT_LANE_OFFSET(lane))
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302242
David Weinehallf8896f52015-06-25 11:11:03 +03002243/* UAIMI scratch pad register 1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002244#define UAIMI_SPR1 _MMIO(0x4F074)
David Weinehallf8896f52015-06-25 11:11:03 +03002245/* SKL VccIO mask */
2246#define SKL_VCCIO_MASK 0x1
2247/* SKL balance leg register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002248#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
David Weinehallf8896f52015-06-25 11:11:03 +03002249/* I_boost values */
2250#define BALANCE_LEG_SHIFT(port) (8+3*(port))
2251#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
2252/* Balance leg disable bits */
2253#define BALANCE_LEG_DISABLE_SHIFT 23
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03002254#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
David Weinehallf8896f52015-06-25 11:11:03 +03002255
Jesse Barnes585fb112008-07-29 11:54:06 -07002256/*
Jesse Barnesde151cf2008-11-12 10:03:55 -08002257 * Fence registers
Ville Syrjäläeecf6132015-09-21 18:05:14 +03002258 * [0-7] @ 0x2000 gen2,gen3
2259 * [8-15] @ 0x3000 945,g33,pnv
2260 *
2261 * [0-15] @ 0x3000 gen4,gen5
2262 *
2263 * [0-15] @ 0x100000 gen6,vlv,chv
2264 * [0-31] @ 0x100000 gen7+
Jesse Barnesde151cf2008-11-12 10:03:55 -08002265 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002266#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002267#define I830_FENCE_START_MASK 0x07f80000
2268#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -08002269#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002270#define I830_FENCE_PITCH_SHIFT 4
2271#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02002272#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07002273#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002274#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002275
2276#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08002277#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002278
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002279#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2280#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002281#define I965_FENCE_PITCH_SHIFT 2
2282#define I965_FENCE_TILING_Y_SHIFT 1
2283#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002284#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08002285
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002286#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2287#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
Ville Syrjäläeecf6132015-09-21 18:05:14 +03002288#define GEN6_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03002289#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07002290
Deepak S2b6b3a02014-05-27 15:59:30 +05302291
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002292/* control register for cpu gtt access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002293#define TILECTL _MMIO(0x101000)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002294#define TILECTL_SWZCTL (1 << 0)
Robert Beckette3a29052015-03-11 10:28:25 +02002295#define TILECTL_TLBPF (1 << 1)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002296#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2297#define TILECTL_BACKSNOOP_DIS (1 << 3)
2298
Jesse Barnesde151cf2008-11-12 10:03:55 -08002299/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002300 * Instruction and interrupt control regs
2301 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002302#define PGTBL_CTL _MMIO(0x02020)
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03002303#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2304#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002305#define PGTBL_ER _MMIO(0x02024)
2306#define PRB0_BASE (0x2030-0x30)
2307#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
2308#define PRB2_BASE (0x2050-0x30) /* gen3 */
2309#define SRB0_BASE (0x2100-0x30) /* gen2 */
2310#define SRB1_BASE (0x2110-0x30) /* gen2 */
2311#define SRB2_BASE (0x2120-0x30) /* 830 */
2312#define SRB3_BASE (0x2130-0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02002313#define RENDER_RING_BASE 0x02000
2314#define BSD_RING_BASE 0x04000
2315#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08002316#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -07002317#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +01002318#define BLT_RING_BASE 0x22000
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002319#define RING_TAIL(base) _MMIO((base)+0x30)
2320#define RING_HEAD(base) _MMIO((base)+0x34)
2321#define RING_START(base) _MMIO((base)+0x38)
2322#define RING_CTL(base) _MMIO((base)+0x3c)
Chris Wilson62ae14b2016-10-04 21:11:25 +01002323#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002324#define RING_SYNC_0(base) _MMIO((base)+0x40)
2325#define RING_SYNC_1(base) _MMIO((base)+0x44)
2326#define RING_SYNC_2(base) _MMIO((base)+0x48)
Ben Widawsky1950de12013-05-28 19:22:20 -07002327#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2328#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2329#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2330#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2331#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2332#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2333#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2334#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2335#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2336#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2337#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2338#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002339#define GEN6_NOSYNC INVALID_MMIO_REG
2340#define RING_PSMI_CTL(base) _MMIO((base)+0x50)
2341#define RING_MAX_IDLE(base) _MMIO((base)+0x54)
2342#define RING_HWS_PGA(base) _MMIO((base)+0x80)
2343#define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
2344#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
Mika Kuoppala7fd2d262015-06-18 12:51:40 +03002345#define RESET_CTL_REQUEST_RESET (1 << 0)
2346#define RESET_CTL_READY_TO_RESET (1 << 1)
Imre Deak9e72b462014-05-05 15:13:55 +03002347
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002348#define HSW_GTT_CACHE_EN _MMIO(0x4024)
Ville Syrjälä6d50b062015-05-19 20:32:57 +03002349#define GTT_CACHE_EN_ALL 0xF0007FFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002350#define GEN7_WR_WATERMARK _MMIO(0x4028)
2351#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2352#define ARB_MODE _MMIO(0x4030)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002353#define ARB_MODE_SWIZZLE_SNB (1<<4)
2354#define ARB_MODE_SWIZZLE_IVB (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002355#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2356#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
Imre Deak9e72b462014-05-05 15:13:55 +03002357/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002358#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03002359#define GEN7_LRA_LIMITS_REG_NUM 13
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002360#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2361#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
Imre Deak9e72b462014-05-05 15:13:55 +03002362
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002363#define GAMTARBMODE _MMIO(0x04a08)
Ben Widawsky4afe8d32013-11-02 21:07:55 -07002364#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07002365#define ARB_MODE_SWIZZLE_BDW (1<<1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002366#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
Chris Wilson5ac97932016-07-27 19:11:17 +01002367#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
Michel Thierryb03ec3d2017-11-13 09:36:28 -08002368#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2369#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
Ben Widawsky828c7902013-10-16 09:21:30 -07002370#define RING_FAULT_GTTSEL_MASK (1<<11)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002371#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2372#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
Ben Widawsky828c7902013-10-16 09:21:30 -07002373#define RING_FAULT_VALID (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002374#define DONE_REG _MMIO(0x40b0)
2375#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2376#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
Michal Wajdeczko1790625b2017-09-08 16:11:30 +00002377#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index)*4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002378#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2379#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2380#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2381#define RING_ACTHD(base) _MMIO((base)+0x74)
2382#define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
2383#define RING_NOPID(base) _MMIO((base)+0x94)
2384#define RING_IMR(base) _MMIO((base)+0xa8)
2385#define RING_HWSTAM(base) _MMIO((base)+0x98)
2386#define RING_TIMESTAMP(base) _MMIO((base)+0x358)
2387#define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002388#define TAIL_ADDR 0x001FFFF8
2389#define HEAD_WRAP_COUNT 0xFFE00000
2390#define HEAD_WRAP_ONE 0x00200000
2391#define HEAD_ADDR 0x001FFFFC
2392#define RING_NR_PAGES 0x001FF000
2393#define RING_REPORT_MASK 0x00000006
2394#define RING_REPORT_64K 0x00000002
2395#define RING_REPORT_128K 0x00000004
2396#define RING_NO_REPORT 0x00000000
2397#define RING_VALID_MASK 0x00000001
2398#define RING_VALID 0x00000001
2399#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01002400#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
2401#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002402#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03002403
Arun Siluvery33136b02016-01-21 21:43:47 +00002404#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
2405#define RING_MAX_NONPRIV_SLOTS 12
2406
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002407#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
Imre Deak9e72b462014-05-05 15:13:55 +03002408
Mika Kuoppala4ba9c1f2016-07-20 14:26:12 +03002409#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2410#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
2411
Matthew Auld9a6330c2017-10-06 23:18:22 +01002412#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2413#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2414
Mika Kuoppalac0b730d2016-06-07 17:19:06 +03002415#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2416#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
Rodrigo Vivi86ebb012017-08-29 16:07:51 -07002417#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
Mika Kuoppalac0b730d2016-06-07 17:19:06 +03002418
Chris Wilson8168bd42010-11-11 17:54:52 +00002419#if 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002420#define PRB0_TAIL _MMIO(0x2030)
2421#define PRB0_HEAD _MMIO(0x2034)
2422#define PRB0_START _MMIO(0x2038)
2423#define PRB0_CTL _MMIO(0x203c)
2424#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2425#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2426#define PRB1_START _MMIO(0x2048) /* 915+ only */
2427#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00002428#endif
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002429#define IPEIR_I965 _MMIO(0x2064)
2430#define IPEHR_I965 _MMIO(0x2068)
2431#define GEN7_SC_INSTDONE _MMIO(0x7100)
2432#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2433#define GEN7_ROW_INSTDONE _MMIO(0xe164)
Ben Widawskyf9e61372016-09-20 16:54:33 +03002434#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2435#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2436#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2437#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2438#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002439#define RING_IPEIR(base) _MMIO((base)+0x64)
2440#define RING_IPEHR(base) _MMIO((base)+0x68)
Imre Deakf1d54342015-09-30 23:00:42 +03002441/*
2442 * On GEN4, only the render ring INSTDONE exists and has a different
2443 * layout than the GEN7+ version.
Imre Deakbd93a502015-09-30 23:00:43 +03002444 * The GEN2 counterpart of this register is GEN2_INSTDONE.
Imre Deakf1d54342015-09-30 23:00:42 +03002445 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002446#define RING_INSTDONE(base) _MMIO((base)+0x6c)
2447#define RING_INSTPS(base) _MMIO((base)+0x70)
2448#define RING_DMA_FADD(base) _MMIO((base)+0x78)
2449#define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
2450#define RING_INSTPM(base) _MMIO((base)+0xc0)
2451#define RING_MI_MODE(base) _MMIO((base)+0x9c)
2452#define INSTPS _MMIO(0x2070) /* 965+ only */
2453#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2454#define ACTHD_I965 _MMIO(0x2074)
2455#define HWS_PGA _MMIO(0x2080)
Jesse Barnes585fb112008-07-29 11:54:06 -07002456#define HWS_ADDRESS_MASK 0xfffff000
2457#define HWS_START_ADDRESS_SHIFT 4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002458#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
Jesse Barnes97f5ab62009-10-08 10:16:48 -07002459#define PWRCTX_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002460#define IPEIR _MMIO(0x2088)
2461#define IPEHR _MMIO(0x208c)
2462#define GEN2_INSTDONE _MMIO(0x2090)
2463#define NOPID _MMIO(0x2094)
2464#define HWSTAM _MMIO(0x2098)
2465#define DMA_FADD_I8XX _MMIO(0x20d0)
2466#define RING_BBSTATE(base) _MMIO((base)+0x110)
Ville Syrjälä35dc3f92015-11-04 23:20:10 +02002467#define RING_BB_PPGTT (1 << 5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002468#define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
2469#define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
2470#define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
2471#define RING_BBADDR(base) _MMIO((base)+0x140)
2472#define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
2473#define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
2474#define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
2475#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
2476#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08002477
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002478#define ERROR_GEN6 _MMIO(0x40a0)
2479#define GEN7_ERR_INT _MMIO(0x44040)
Paulo Zanonide032bf2013-04-12 17:57:58 -03002480#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03002481#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002482#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03002483#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002484#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03002485#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002486#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002487#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03002488#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002489#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01002490
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002491#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2492#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
Oscar Mateo5a3f58d2017-12-22 14:38:49 -08002493#define FAULT_VA_HIGH_BITS (0xf << 0)
2494#define FAULT_GTT_SEL (1 << 4)
Mika Kuoppala6c826f32015-03-24 14:54:19 +02002495
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002496#define FPGA_DBG _MMIO(0x42300)
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03002497#define FPGA_DBG_RM_NOCLAIM (1<<31)
2498
Mika Kuoppala8ac3e1b2015-12-15 19:45:42 +02002499#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2500#define CLAIM_ER_CLR (1 << 31)
2501#define CLAIM_ER_OVERFLOW (1 << 16)
2502#define CLAIM_ER_CTR_MASK 0xffff
2503
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002504#define DERRMR _MMIO(0x44050)
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07002505/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01002506#define DERRMR_PIPEA_SCANLINE (1<<0)
2507#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
2508#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
2509#define DERRMR_PIPEA_VBLANK (1<<3)
2510#define DERRMR_PIPEA_HBLANK (1<<5)
2511#define DERRMR_PIPEB_SCANLINE (1<<8)
2512#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
2513#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
2514#define DERRMR_PIPEB_VBLANK (1<<11)
2515#define DERRMR_PIPEB_HBLANK (1<<13)
2516/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2517#define DERRMR_PIPEC_SCANLINE (1<<14)
2518#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
2519#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
2520#define DERRMR_PIPEC_VBLANK (1<<21)
2521#define DERRMR_PIPEC_HBLANK (1<<22)
2522
Chris Wilson0f3b6842013-01-15 12:05:55 +00002523
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002524/* GM45+ chicken bits -- debug workaround bits that may be required
2525 * for various sorts of correct behavior. The top 16 bits of each are
2526 * the enables for writing to the corresponding low bit.
2527 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002528#define _3D_CHICKEN _MMIO(0x2084)
Daniel Vetter42839082012-12-14 23:38:28 +01002529#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002530#define _3D_CHICKEN2 _MMIO(0x208c)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002531/* Disables pipelining of read flushes past the SF-WIZ interface.
2532 * Required on all Ironlake steppings according to the B-Spec, but the
2533 * particular danger of not doing so is not specified.
2534 */
2535# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002536#define _3D_CHICKEN3 _MMIO(0x2090)
Jesse Barnes87f80202012-10-02 17:43:41 -05002537#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Rodrigo Vivi1a25db62017-08-15 16:16:51 -07002538#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07002539#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02002540#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
2541#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07002542
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002543#define MI_MODE _MMIO(0x209c)
Eric Anholt71cf39b2010-03-08 23:41:55 -08002544# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08002545# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00002546# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05302547# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01002548# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08002549
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002550#define GEN6_GT_MODE _MMIO(0x20d0)
2551#define GEN7_GT_MODE _MMIO(0x7008)
Ville Syrjälä8d85d272014-02-04 21:59:15 +02002552#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2553#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2554#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2555#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
Damien Lespiau98533252014-12-08 17:33:51 +00002556#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01002557#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ville Syrjälä68d97532015-09-18 20:03:39 +03002558#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2559#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07002560
Tim Gorea8ab5ed2016-06-13 12:15:01 +01002561/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2562#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2563#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2564
Tim Goreb1e429f2016-03-21 14:37:29 +00002565/* WaClearTdlStateAckDirtyBits */
2566#define GEN8_STATE_ACK _MMIO(0x20F0)
2567#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2568#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2569#define GEN9_STATE_ACK_TDL0 (1 << 12)
2570#define GEN9_STATE_ACK_TDL1 (1 << 13)
2571#define GEN9_STATE_ACK_TDL2 (1 << 14)
2572#define GEN9_STATE_ACK_TDL3 (1 << 15)
2573#define GEN9_SUBSLICE_TDL_ACK_BITS \
2574 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2575 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2576
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002577#define GFX_MODE _MMIO(0x2520)
2578#define GFX_MODE_GEN7 _MMIO(0x229c)
Dave Gordonbbdc070a2016-07-20 18:16:05 +01002579#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002580#define GFX_RUN_LIST_ENABLE (1<<15)
Dave Gordon4df001d2015-08-12 15:43:42 +01002581#define GFX_INTERRUPT_STEERING (1<<14)
Chris Wilsonaa83e302014-03-21 17:18:54 +00002582#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002583#define GFX_SURFACE_FAULT_ENABLE (1<<12)
2584#define GFX_REPLAY_MODE (1<<11)
2585#define GFX_PSMI_GRANULARITY (1<<10)
2586#define GFX_PPGTT_ENABLE (1<<9)
Michel Thierry2dba3232015-07-30 11:06:23 +01002587#define GEN8_GFX_PPGTT_48B (1<<7)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002588
Dave Gordon4df001d2015-08-12 15:43:42 +01002589#define GFX_FORWARD_VBLANK_MASK (3<<5)
2590#define GFX_FORWARD_VBLANK_NEVER (0<<5)
2591#define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
2592#define GFX_FORWARD_VBLANK_COND (2<<5)
2593
Daniel Vettera7e806d2012-07-11 16:27:55 +02002594#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05302595#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Shashank Sharmac6c794a2016-03-22 12:01:50 +02002596#define BXT_MIPI_BASE 0x60000
Daniel Vettera7e806d2012-07-11 16:27:55 +02002597
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002598#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2599#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2600#define SCPD0 _MMIO(0x209c) /* 915+ only */
2601#define IER _MMIO(0x20a0)
2602#define IIR _MMIO(0x20a4)
2603#define IMR _MMIO(0x20a8)
2604#define ISR _MMIO(0x20ac)
2605#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03002606#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07002607#define GCFG_DIS (1<<8)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002608#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2609#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2610#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2611#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2612#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2613#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2614#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05302615#define VLV_PCBR_ADDR_SHIFT 12
2616
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002617#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002618#define EIR _MMIO(0x20b0)
2619#define EMR _MMIO(0x20b4)
2620#define ESR _MMIO(0x20b8)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07002621#define GM45_ERROR_PAGE_TABLE (1<<5)
2622#define GM45_ERROR_MEM_PRIV (1<<4)
2623#define I915_ERROR_PAGE_TABLE (1<<4)
2624#define GM45_ERROR_CP_PRIV (1<<3)
2625#define I915_ERROR_MEMORY_REFRESH (1<<1)
2626#define I915_ERROR_INSTRUCTION (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002627#define INSTPM _MMIO(0x20c0)
Li Pengee980b82010-01-27 19:01:11 +08002628#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02002629#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00002630 will not assert AGPBUSY# and will only
2631 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08002632#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01002633#define INSTPM_TLB_INVALIDATE (1<<9)
2634#define INSTPM_SYNC_FLUSH (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002635#define ACTHD _MMIO(0x20c8)
2636#define MEM_MODE _MMIO(0x20cc)
Ville Syrjälä10383922014-08-15 01:21:54 +03002637#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
2638#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
2639#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002640#define FW_BLC _MMIO(0x20d8)
2641#define FW_BLC2 _MMIO(0x20dc)
2642#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08002643#define FW_BLC_SELF_EN_MASK (1<<31)
2644#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
2645#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002646#define MM_BURST_LENGTH 0x00700000
2647#define MM_FIFO_WATERMARK 0x0001F000
2648#define LM_BURST_LENGTH 0x00000700
2649#define LM_FIFO_WATERMARK 0x0000001F
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002650#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07002651
2652/* Make render/texture TLB fetches lower priorty than associated data
2653 * fetches. This is not turned on by default
2654 */
2655#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2656
2657/* Isoch request wait on GTT enable (Display A/B/C streams).
2658 * Make isoch requests stall on the TLB update. May cause
2659 * display underruns (test mode only)
2660 */
2661#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2662
2663/* Block grant count for isoch requests when block count is
2664 * set to a finite value.
2665 */
2666#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2667#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2668#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2669#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2670#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2671
2672/* Enable render writes to complete in C2/C3/C4 power states.
2673 * If this isn't enabled, render writes are prevented in low
2674 * power states. That seems bad to me.
2675 */
2676#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2677
2678/* This acknowledges an async flip immediately instead
2679 * of waiting for 2TLB fetches.
2680 */
2681#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2682
2683/* Enables non-sequential data reads through arbiter
2684 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002685#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07002686
2687/* Disable FSB snooping of cacheable write cycles from binner/render
2688 * command stream
2689 */
2690#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2691
2692/* Arbiter time slice for non-isoch streams */
2693#define MI_ARB_TIME_SLICE_MASK (7 << 5)
2694#define MI_ARB_TIME_SLICE_1 (0 << 5)
2695#define MI_ARB_TIME_SLICE_2 (1 << 5)
2696#define MI_ARB_TIME_SLICE_4 (2 << 5)
2697#define MI_ARB_TIME_SLICE_6 (3 << 5)
2698#define MI_ARB_TIME_SLICE_8 (4 << 5)
2699#define MI_ARB_TIME_SLICE_10 (5 << 5)
2700#define MI_ARB_TIME_SLICE_14 (6 << 5)
2701#define MI_ARB_TIME_SLICE_16 (7 << 5)
2702
2703/* Low priority grace period page size */
2704#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2705#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2706
2707/* Disable display A/B trickle feed */
2708#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2709
2710/* Set display plane priority */
2711#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2712#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2713
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002714#define MI_STATE _MMIO(0x20e4) /* gen2 only */
Ville Syrjälä54e472a2014-02-25 15:13:40 +02002715#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2716#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2717
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002718#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02002719#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07002720#define CM0_IZ_OPT_DISABLE (1<<6)
2721#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02002722#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07002723#define CM0_DEPTH_EVICT_DISABLE (1<<4)
2724#define CM0_COLOR_EVICT_DISABLE (1<<3)
2725#define CM0_DEPTH_WRITE_DISABLE (1<<1)
2726#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002727#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2728#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08002729#define GFX_FLSH_CNTL_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002730#define ECOSKPD _MMIO(0x21d0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07002731#define ECO_GATING_CX_ONLY (1<<3)
2732#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07002733
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002734#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05302735#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08002736#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002737#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00002738#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
2739#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Damien Lespiau9370cd92015-02-09 19:33:17 +00002740#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
Jesse Barnesfb046852012-03-28 13:39:26 -07002741
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002742#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
Jesse Barnes4efe0702011-01-18 11:25:41 -08002743#define GEN6_BLITTER_LOCK_SHIFT 16
2744#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2745
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002746#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
Chris Wilson2c550182014-12-16 10:02:27 +00002747#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02002748#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03002749#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02002750
Robert Bragg19f81df2017-06-13 12:23:03 +01002751#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2752#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2753
Deepak S693d11c2015-01-16 20:42:16 +05302754/* Fuse readout registers for GT */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002755#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
Jeff McGeec93043a2015-02-27 12:12:28 -08002756#define CHV_FGT_DISABLE_SS0 (1 << 10)
2757#define CHV_FGT_DISABLE_SS1 (1 << 11)
Deepak S693d11c2015-01-16 20:42:16 +05302758#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2759#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2760#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2761#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2762#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2763#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2764#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2765#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2766
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002767#define GEN8_FUSE2 _MMIO(0x9120)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002768#define GEN8_F2_SS_DIS_SHIFT 21
2769#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
Jeff McGee38732182015-02-13 10:27:54 -06002770#define GEN8_F2_S_ENA_SHIFT 25
2771#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2772
2773#define GEN9_F2_SS_DIS_SHIFT 20
2774#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2775
Ben Widawsky4e9767b2017-09-20 11:35:24 -07002776#define GEN10_F2_S_ENA_SHIFT 22
2777#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2778#define GEN10_F2_SS_DIS_SHIFT 18
2779#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2780
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002781#define GEN8_EU_DISABLE0 _MMIO(0x9134)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002782#define GEN8_EU_DIS0_S0_MASK 0xffffff
2783#define GEN8_EU_DIS0_S1_SHIFT 24
2784#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2785
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002786#define GEN8_EU_DISABLE1 _MMIO(0x9138)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002787#define GEN8_EU_DIS1_S1_MASK 0xffff
2788#define GEN8_EU_DIS1_S2_SHIFT 16
2789#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2790
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002791#define GEN8_EU_DISABLE2 _MMIO(0x913c)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002792#define GEN8_EU_DIS2_S2_MASK 0xff
2793
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002794#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
Jeff McGee38732182015-02-13 10:27:54 -06002795
Ben Widawsky4e9767b2017-09-20 11:35:24 -07002796#define GEN10_EU_DISABLE3 _MMIO(0x9140)
2797#define GEN10_EU_DIS_SS_MASK 0xff
2798
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002799#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
Chris Wilson12f55812012-07-05 17:14:01 +01002800#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2801#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2802#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2803#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002804
Ben Widawskycc609d52013-05-28 19:22:29 -07002805/* On modern GEN architectures interrupt control consists of two sets
2806 * of registers. The first set pertains to the ring generating the
2807 * interrupt. The second control is for the functional block generating the
2808 * interrupt. These are PM, GT, DE, etc.
2809 *
2810 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2811 * GT interrupt bits, so we don't need to duplicate the defines.
2812 *
2813 * These defines should cover us well from SNB->HSW with minor exceptions
2814 * it can also work on ILK.
2815 */
2816#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2817#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2818#define GT_BLT_USER_INTERRUPT (1 << 22)
2819#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2820#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002821#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Oscar Mateo73d477f2014-07-24 17:04:31 +01002822#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07002823#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2824#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2825#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2826#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2827#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2828#define GT_RENDER_USER_INTERRUPT (1 << 0)
2829
Ben Widawsky12638c52013-05-28 19:22:31 -07002830#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2831#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2832
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01002833#define GT_PARITY_ERROR(dev_priv) \
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002834 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01002835 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002836
Ben Widawskycc609d52013-05-28 19:22:29 -07002837/* These are all the "old" interrupts */
2838#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002839
2840#define I915_PM_INTERRUPT (1<<31)
2841#define I915_ISP_INTERRUPT (1<<22)
2842#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2843#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02002844#define I915_MIPIC_INTERRUPT (1<<19)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002845#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07002846#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2847#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002848#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2849#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07002850#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002851#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07002852#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002853#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07002854#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002855#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07002856#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002857#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07002858#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002859#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07002860#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002861#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07002862#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002863#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07002864#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2865#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2866#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2867#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2868#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002869#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2870#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07002871#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002872#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07002873#define I915_USER_INTERRUPT (1<<1)
2874#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002875#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002876
Jerome Anandeef57322017-01-25 04:27:49 +05302877#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2878#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2879
Pierre-Louis Bossartd5d8c3a2017-01-31 14:16:49 -06002880/* DisplayPort Audio w/ LPE */
Takashi Iwai9db13e52017-02-02 11:03:48 +01002881#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2882#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2883
Pierre-Louis Bossartd5d8c3a2017-01-31 14:16:49 -06002884#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2885#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2886#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2887#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2888 _VLV_AUD_PORT_EN_B_DBG, \
2889 _VLV_AUD_PORT_EN_C_DBG, \
2890 _VLV_AUD_PORT_EN_D_DBG)
2891#define VLV_AMP_MUTE (1 << 1)
2892
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002893#define GEN6_BSD_RNCID _MMIO(0x12198)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002894
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002895#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002896#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08002897#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002898#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2899#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2900#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2901#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08002902#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002903#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2904#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2905#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2906#define GEN7_FF_VS_SCHED_HW (0x0<<12)
2907#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2908#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2909#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2910#define GEN7_FF_DS_SCHED_HW (0x0<<4)
2911
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002912/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002913 * Framebuffer compression (915+ only)
2914 */
2915
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002916#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2917#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2918#define FBC_CONTROL _MMIO(0x3208)
Jesse Barnes585fb112008-07-29 11:54:06 -07002919#define FBC_CTL_EN (1<<31)
2920#define FBC_CTL_PERIODIC (1<<30)
2921#define FBC_CTL_INTERVAL_SHIFT (16)
2922#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02002923#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07002924#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02002925#define FBC_CTL_FENCENO_SHIFT (0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002926#define FBC_COMMAND _MMIO(0x320c)
Jesse Barnes585fb112008-07-29 11:54:06 -07002927#define FBC_CMD_COMPRESS (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002928#define FBC_STATUS _MMIO(0x3210)
Jesse Barnes585fb112008-07-29 11:54:06 -07002929#define FBC_STAT_COMPRESSING (1<<31)
2930#define FBC_STAT_COMPRESSED (1<<30)
2931#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02002932#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002933#define FBC_CONTROL2 _MMIO(0x3214)
Jesse Barnes585fb112008-07-29 11:54:06 -07002934#define FBC_CTL_FENCE_DBL (0<<4)
2935#define FBC_CTL_IDLE_IMM (0<<2)
2936#define FBC_CTL_IDLE_FULL (1<<2)
2937#define FBC_CTL_IDLE_LINE (2<<2)
2938#define FBC_CTL_IDLE_DEBUG (3<<2)
2939#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02002940#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002941#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2942#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002943
2944#define FBC_LL_SIZE (1536)
2945
Mika Kuoppala44fff992016-06-07 17:19:09 +03002946#define FBC_LLC_READ_CTRL _MMIO(0x9044)
2947#define FBC_LLC_FULLY_OPEN (1<<30)
2948
Jesse Barnes74dff282009-09-14 15:39:40 -07002949/* Framebuffer compression for GM45+ */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002950#define DPFC_CB_BASE _MMIO(0x3200)
2951#define DPFC_CONTROL _MMIO(0x3208)
Jesse Barnes74dff282009-09-14 15:39:40 -07002952#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02002953#define DPFC_CTL_PLANE(plane) ((plane)<<30)
2954#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07002955#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002956#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01002957#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07002958#define DPFC_SR_EN (1<<10)
2959#define DPFC_CTL_LIMIT_1X (0<<6)
2960#define DPFC_CTL_LIMIT_2X (1<<6)
2961#define DPFC_CTL_LIMIT_4X (2<<6)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002962#define DPFC_RECOMP_CTL _MMIO(0x320c)
Jesse Barnes74dff282009-09-14 15:39:40 -07002963#define DPFC_RECOMP_STALL_EN (1<<27)
2964#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2965#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2966#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2967#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002968#define DPFC_STATUS _MMIO(0x3210)
Jesse Barnes74dff282009-09-14 15:39:40 -07002969#define DPFC_INVAL_SEG_SHIFT (16)
2970#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2971#define DPFC_COMP_SEG_SHIFT (0)
Ville Syrjälä3fd5d1e2017-06-06 15:43:18 +03002972#define DPFC_COMP_SEG_MASK (0x000007ff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002973#define DPFC_STATUS2 _MMIO(0x3214)
2974#define DPFC_FENCE_YOFF _MMIO(0x3218)
2975#define DPFC_CHICKEN _MMIO(0x3224)
Jesse Barnes74dff282009-09-14 15:39:40 -07002976#define DPFC_HT_MODIFY (1<<31)
2977
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002978/* Framebuffer compression for Ironlake */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002979#define ILK_DPFC_CB_BASE _MMIO(0x43200)
2980#define ILK_DPFC_CONTROL _MMIO(0x43208)
Rodrigo Vivida46f932014-08-01 02:04:45 -07002981#define FBC_CTL_FALSE_COLOR (1<<10)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002982/* The bit 28-8 is reserved */
2983#define DPFC_RESERVED (0x1FFFFF00)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002984#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
2985#define ILK_DPFC_STATUS _MMIO(0x43210)
Ville Syrjälä3fd5d1e2017-06-06 15:43:18 +03002986#define ILK_DPFC_COMP_SEG_MASK 0x7ff
2987#define IVB_FBC_STATUS2 _MMIO(0x43214)
2988#define IVB_FBC_COMP_SEG_MASK 0x7ff
2989#define BDW_FBC_COMP_SEG_MASK 0xfff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002990#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2991#define ILK_DPFC_CHICKEN _MMIO(0x43224)
Mika Kuoppalad1b4eef2016-06-07 17:19:19 +03002992#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03002993#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002994#define ILK_FBC_RT_BASE _MMIO(0x2128)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002995#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002996#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002997
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002998#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002999#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04003000#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08003001
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003002
Jesse Barnes585fb112008-07-29 11:54:06 -07003003/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003004 * Framebuffer compression for Sandybridge
3005 *
3006 * The following two registers are of type GTTMMADR
3007 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003008#define SNB_DPFC_CTL_SA _MMIO(0x100100)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003009#define SNB_CPU_FENCE_ENABLE (1<<29)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003010#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003011
Rodrigo Viviabe959c2013-05-06 19:37:33 -03003012/* Framebuffer compression for Ivybridge */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003013#define IVB_FBC_RT_BASE _MMIO(0x7020)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03003014
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003015#define IPS_CTL _MMIO(0x43408)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003016#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003017
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003018#define MSG_FBC_REND_STATE _MMIO(0x50380)
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03003019#define FBC_REND_NUKE (1<<2)
3020#define FBC_REND_CACHE_CLEAN (1<<1)
3021
Yuanhan Liu9c04f012010-12-15 15:42:32 +08003022/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003023 * GPIO regs
3024 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003025#define GPIOA _MMIO(0x5010)
3026#define GPIOB _MMIO(0x5014)
3027#define GPIOC _MMIO(0x5018)
3028#define GPIOD _MMIO(0x501c)
3029#define GPIOE _MMIO(0x5020)
3030#define GPIOF _MMIO(0x5024)
3031#define GPIOG _MMIO(0x5028)
3032#define GPIOH _MMIO(0x502c)
Jesse Barnes585fb112008-07-29 11:54:06 -07003033# define GPIO_CLOCK_DIR_MASK (1 << 0)
3034# define GPIO_CLOCK_DIR_IN (0 << 1)
3035# define GPIO_CLOCK_DIR_OUT (1 << 1)
3036# define GPIO_CLOCK_VAL_MASK (1 << 2)
3037# define GPIO_CLOCK_VAL_OUT (1 << 3)
3038# define GPIO_CLOCK_VAL_IN (1 << 4)
3039# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3040# define GPIO_DATA_DIR_MASK (1 << 8)
3041# define GPIO_DATA_DIR_IN (0 << 9)
3042# define GPIO_DATA_DIR_OUT (1 << 9)
3043# define GPIO_DATA_VAL_MASK (1 << 10)
3044# define GPIO_DATA_VAL_OUT (1 << 11)
3045# define GPIO_DATA_VAL_IN (1 << 12)
3046# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3047
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003048#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
Chris Wilsonf899fc62010-07-20 15:44:45 -07003049#define GMBUS_RATE_100KHZ (0<<8)
3050#define GMBUS_RATE_50KHZ (1<<8)
3051#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
3052#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
3053#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
Jani Nikula988c7012015-03-27 00:20:19 +02003054#define GMBUS_PIN_DISABLED 0
3055#define GMBUS_PIN_SSC 1
3056#define GMBUS_PIN_VGADDC 2
3057#define GMBUS_PIN_PANEL 3
3058#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3059#define GMBUS_PIN_DPC 4 /* HDMIC */
3060#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3061#define GMBUS_PIN_DPD 6 /* HDMID */
3062#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
Rodrigo Vivi3d023522017-06-02 13:06:43 -07003063#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
Jani Nikula4c272832015-04-01 10:58:05 +03003064#define GMBUS_PIN_2_BXT 2
3065#define GMBUS_PIN_3_BXT 3
Rodrigo Vivi3d023522017-06-02 13:06:43 -07003066#define GMBUS_PIN_4_CNP 4
Anusha Srivatsa5c749c52018-01-11 16:00:09 -02003067#define GMBUS_PIN_9_TC1_ICP 9
3068#define GMBUS_PIN_10_TC2_ICP 10
3069#define GMBUS_PIN_11_TC3_ICP 11
3070#define GMBUS_PIN_12_TC4_ICP 12
3071
3072#define GMBUS_NUM_PINS 13 /* including 0 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003073#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
Chris Wilsonf899fc62010-07-20 15:44:45 -07003074#define GMBUS_SW_CLR_INT (1<<31)
3075#define GMBUS_SW_RDY (1<<30)
3076#define GMBUS_ENT (1<<29) /* enable timeout */
3077#define GMBUS_CYCLE_NONE (0<<25)
3078#define GMBUS_CYCLE_WAIT (1<<25)
3079#define GMBUS_CYCLE_INDEX (2<<25)
3080#define GMBUS_CYCLE_STOP (4<<25)
3081#define GMBUS_BYTE_COUNT_SHIFT 16
Dmitry Torokhov9535c472015-04-21 09:49:11 -07003082#define GMBUS_BYTE_COUNT_MAX 256U
Chris Wilsonf899fc62010-07-20 15:44:45 -07003083#define GMBUS_SLAVE_INDEX_SHIFT 8
3084#define GMBUS_SLAVE_ADDR_SHIFT 1
3085#define GMBUS_SLAVE_READ (1<<0)
3086#define GMBUS_SLAVE_WRITE (0<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003087#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
Chris Wilsonf899fc62010-07-20 15:44:45 -07003088#define GMBUS_INUSE (1<<15)
3089#define GMBUS_HW_WAIT_PHASE (1<<14)
3090#define GMBUS_STALL_TIMEOUT (1<<13)
3091#define GMBUS_INT (1<<12)
3092#define GMBUS_HW_RDY (1<<11)
3093#define GMBUS_SATOER (1<<10)
3094#define GMBUS_ACTIVE (1<<9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003095#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3096#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
Chris Wilsonf899fc62010-07-20 15:44:45 -07003097#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
3098#define GMBUS_NAK_EN (1<<3)
3099#define GMBUS_IDLE_EN (1<<2)
3100#define GMBUS_HW_WAIT_EN (1<<1)
3101#define GMBUS_HW_RDY_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003102#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
Chris Wilsonf899fc62010-07-20 15:44:45 -07003103#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08003104
Jesse Barnes585fb112008-07-29 11:54:06 -07003105/*
3106 * Clock control & power management
3107 */
Ville Syrjälä2d401b12014-04-09 13:29:08 +03003108#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3109#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3110#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003111#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07003112
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003113#define VGA0 _MMIO(0x6000)
3114#define VGA1 _MMIO(0x6004)
3115#define VGA_PD _MMIO(0x6010)
Jesse Barnes585fb112008-07-29 11:54:06 -07003116#define VGA0_PD_P2_DIV_4 (1 << 7)
3117#define VGA0_PD_P1_DIV_2 (1 << 5)
3118#define VGA0_PD_P1_SHIFT 0
3119#define VGA0_PD_P1_MASK (0x1f << 0)
3120#define VGA1_PD_P2_DIV_4 (1 << 15)
3121#define VGA1_PD_P1_DIV_2 (1 << 13)
3122#define VGA1_PD_P1_SHIFT 8
3123#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07003124#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02003125#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3126#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003127#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003128#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03003129#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07003130#define DPLL_VGA_MODE_DIS (1 << 28)
3131#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3132#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3133#define DPLL_MODE_MASK (3 << 26)
3134#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3135#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3136#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3137#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3138#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3139#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003140#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003141#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02003142#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03003143#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
3144#define DPLL_SSC_REF_CLK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02003145#define DPLL_PORTC_READY_MASK (0xf << 4)
3146#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003147
Jesse Barnes585fb112008-07-29 11:54:06 -07003148#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03003149
3150/* Additional CHV pll/phy registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003151#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03003152#define DPLL_PORTD_READY_MASK (0xf)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003153#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003154#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
Ville Syrjäläbc284542015-05-26 20:22:38 +03003155#define PHY_LDO_DELAY_0NS 0x0
3156#define PHY_LDO_DELAY_200NS 0x1
3157#define PHY_LDO_DELAY_600NS 0x2
3158#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003159#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
Ville Syrjälä70722462015-04-10 18:21:28 +03003160#define PHY_CH_SU_PSR 0x1
3161#define PHY_CH_DEEP_PSR 0x7
3162#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
3163#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003164#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03003165#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
Ville Syrjälä30142272015-07-08 23:46:01 +03003166#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
3167#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03003168
Jesse Barnes585fb112008-07-29 11:54:06 -07003169/*
3170 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3171 * this field (only one bit may be set).
3172 */
3173#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3174#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003175#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07003176/* i830, required in DVO non-gang */
3177#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3178#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3179#define PLL_REF_INPUT_DREFCLK (0 << 13)
3180#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3181#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3182#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3183#define PLL_REF_INPUT_MASK (3 << 13)
3184#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003185/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003186# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3187# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3188# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
3189# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3190# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3191
Jesse Barnes585fb112008-07-29 11:54:06 -07003192/*
3193 * Parallel to Serial Load Pulse phase selection.
3194 * Selects the phase for the 10X DPLL clock for the PCIe
3195 * digital display port. The range is 4 to 13; 10 or more
3196 * is just a flip delay. The default is 6
3197 */
3198#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3199#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3200/*
3201 * SDVO multiplier for 945G/GM. Not used on 965.
3202 */
3203#define SDVO_MULTIPLIER_MASK 0x000000ff
3204#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3205#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003206
Ville Syrjälä2d401b12014-04-09 13:29:08 +03003207#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3208#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3209#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003210#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003211
Jesse Barnes585fb112008-07-29 11:54:06 -07003212/*
3213 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3214 *
3215 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3216 */
3217#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3218#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3219/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3220#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3221#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3222/*
3223 * SDVO/UDI pixel multiplier.
3224 *
3225 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3226 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3227 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3228 * dummy bytes in the datastream at an increased clock rate, with both sides of
3229 * the link knowing how many bytes are fill.
3230 *
3231 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3232 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3233 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3234 * through an SDVO command.
3235 *
3236 * This register field has values of multiplication factor minus 1, with
3237 * a maximum multiplier of 5 for SDVO.
3238 */
3239#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3240#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3241/*
3242 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3243 * This best be set to the default value (3) or the CRT won't work. No,
3244 * I don't entirely understand what this does...
3245 */
3246#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3247#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003248
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +03003249#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3250
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003251#define _FPA0 0x6040
3252#define _FPA1 0x6044
3253#define _FPB0 0x6048
3254#define _FPB1 0x604c
3255#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3256#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07003257#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003258#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07003259#define FP_N_DIV_SHIFT 16
3260#define FP_M1_DIV_MASK 0x00003f00
3261#define FP_M1_DIV_SHIFT 8
3262#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003263#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07003264#define FP_M2_DIV_SHIFT 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003265#define DPLL_TEST _MMIO(0x606c)
Jesse Barnes585fb112008-07-29 11:54:06 -07003266#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3267#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3268#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3269#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3270#define DPLLB_TEST_N_BYPASS (1 << 19)
3271#define DPLLB_TEST_M_BYPASS (1 << 18)
3272#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3273#define DPLLA_TEST_N_BYPASS (1 << 3)
3274#define DPLLA_TEST_M_BYPASS (1 << 2)
3275#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003276#define D_STATE _MMIO(0x6104)
Chris Wilsondc96e9b2010-10-01 12:05:06 +01003277#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07003278#define DSTATE_PLL_D3_OFF (1<<3)
3279#define DSTATE_GFX_CLOCK_GATING (1<<1)
3280#define DSTATE_DOT_CLOCK_GATING (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003281#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07003282# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3283# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3284# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3285# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3286# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3287# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3288# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
Ville Syrjäläad8059c2017-12-08 23:37:38 +02003289# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
Jesse Barnes652c3932009-08-17 13:31:43 -07003290# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3291# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3292# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3293# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3294# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3295# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3296# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3297# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3298# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3299# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3300# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3301# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3302# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3303# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3304# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3305# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3306# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3307# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3308# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3309# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3310# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003311/*
Jesse Barnes652c3932009-08-17 13:31:43 -07003312 * This bit must be set on the 830 to prevent hangs when turning off the
3313 * overlay scaler.
3314 */
3315# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3316# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3317# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3318# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3319# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3320
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003321#define RENCLK_GATE_D1 _MMIO(0x6204)
Jesse Barnes652c3932009-08-17 13:31:43 -07003322# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3323# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3324# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3325# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3326# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3327# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3328# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3329# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3330# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003331/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07003332# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3333# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3334# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3335# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003336/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07003337# define SV_CLOCK_GATE_DISABLE (1 << 0)
3338# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3339# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3340# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3341# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3342# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3343# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3344# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3345# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3346# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3347# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3348# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3349# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3350# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3351# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3352# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3353# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3354# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3355
3356# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003357/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07003358# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3359# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3360# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3361# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3362# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3363# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003364/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07003365# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3366# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3367# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3368# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3369# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3370# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3371# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3372# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3373# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3374# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3375# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3376# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3377# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3378# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3379# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3380# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3381# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3382# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3383# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3384
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003385#define RENCLK_GATE_D2 _MMIO(0x6208)
Jesse Barnes652c3932009-08-17 13:31:43 -07003386#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3387#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3388#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03003389
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003390#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03003391#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3392
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003393#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3394#define DEUC _MMIO(0x6214) /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003395
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003396#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07003397#define FW_CSPWRDWNEN (1<<15)
3398
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003399#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03003400
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003401#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08003402#define CDCLK_FREQ_SHIFT 4
3403#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3404#define CZCLK_FREQ_MASK 0xf
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02003405
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003406#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02003407#define PFI_CREDIT_63 (9 << 28) /* chv only */
3408#define PFI_CREDIT_31 (8 << 28) /* chv only */
3409#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3410#define PFI_CREDIT_RESEND (1 << 27)
3411#define VGA_FAST_MODE_DISABLE (1 << 14)
3412
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003413#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08003414
Jesse Barnes585fb112008-07-29 11:54:06 -07003415/*
3416 * Palette regs
3417 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003418#define PALETTE_A_OFFSET 0xa000
3419#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03003420#define CHV_PALETTE_C_OFFSET 0xc000
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003421#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3422 dev_priv->info.display_mmio_offset + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003423
Eric Anholt673a3942008-07-30 12:06:12 -07003424/* MCH MMIO space */
3425
3426/*
3427 * MCHBAR mirror.
3428 *
3429 * This mirrors the MCHBAR MMIO space whose location is determined by
3430 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3431 * every way. It is not accessible from the CP register read instructions.
3432 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03003433 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3434 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07003435 */
3436#define MCHBAR_MIRROR_BASE 0x10000
3437
Yuanhan Liu13982612010-12-15 15:42:31 +08003438#define MCHBAR_MIRROR_BASE_SNB 0x140000
3439
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003440#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3441#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
Ville Syrjälä7d316ae2015-09-16 21:28:50 +03003442#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3443#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
Ville Syrjälädb7fb602017-11-02 17:17:35 +02003444#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
Ville Syrjälä7d316ae2015-09-16 21:28:50 +03003445
Chris Wilson3ebecd02013-04-12 19:10:13 +01003446/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003447#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01003448
Ville Syrjälä646b4262014-04-25 20:14:30 +03003449/* 915-945 and GM965 MCH register controlling DRAM channel access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003450#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
Eric Anholt673a3942008-07-30 12:06:12 -07003451#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3452#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3453#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3454#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3455#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08003456#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003457#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
Daniel Vetter656bfa32014-11-20 09:26:30 +01003458#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
Eric Anholt673a3942008-07-30 12:06:12 -07003459
Ville Syrjälä646b4262014-04-25 20:14:30 +03003460/* Pineview MCH register contains DDR3 setting */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003461#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
Li Peng95534262010-05-18 18:58:44 +08003462#define CSHRDDR3CTL_DDR3 (1 << 2)
3463
Ville Syrjälä646b4262014-04-25 20:14:30 +03003464/* 965 MCH register controlling DRAM channel configuration */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003465#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3466#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
Eric Anholt673a3942008-07-30 12:06:12 -07003467
Ville Syrjälä646b4262014-04-25 20:14:30 +03003468/* snb MCH registers for reading the DRAM channel configuration */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003469#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3470#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3471#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003472#define MAD_DIMM_ECC_MASK (0x3 << 24)
3473#define MAD_DIMM_ECC_OFF (0x0 << 24)
3474#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3475#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3476#define MAD_DIMM_ECC_ON (0x3 << 24)
3477#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3478#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3479#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3480#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3481#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3482#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3483#define MAD_DIMM_A_SELECT (0x1 << 16)
3484/* DIMM sizes are in multiples of 256mb. */
3485#define MAD_DIMM_B_SIZE_SHIFT 8
3486#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3487#define MAD_DIMM_A_SIZE_SHIFT 0
3488#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3489
Ville Syrjälä646b4262014-04-25 20:14:30 +03003490/* snb MCH registers for priority tuning */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003491#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01003492#define MCH_SSKPD_WM0_MASK 0x3f
3493#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003494
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003495#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
Jesse Barnesec013e72013-08-20 10:29:23 +01003496
Keith Packardb11248d2009-06-11 22:28:56 -07003497/* Clocking configuration register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003498#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003499#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07003500#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3501#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3502#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3503#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
Ville Syrjälä6f381232017-05-04 21:15:30 +03003504#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
Keith Packardb11248d2009-06-11 22:28:56 -07003505#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Ville Syrjälä6f381232017-05-04 21:15:30 +03003506/*
3507 * Note that on at least on ELK the below value is reported for both
3508 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3509 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3510 */
3511#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
Keith Packardb11248d2009-06-11 22:28:56 -07003512#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003513#define CLKCFG_MEM_533 (1 << 4)
3514#define CLKCFG_MEM_667 (2 << 4)
3515#define CLKCFG_MEM_800 (3 << 4)
3516#define CLKCFG_MEM_MASK (7 << 4)
3517
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003518#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3519#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
Ville Syrjälä34edce22015-05-22 11:22:33 +03003520
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003521#define TSC1 _MMIO(0x11001)
Jesse Barnesea056c12010-09-10 10:02:13 -07003522#define TSE (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003523#define TR1 _MMIO(0x11006)
3524#define TSFS _MMIO(0x11020)
Jesse Barnes7648fa92010-05-20 14:28:11 -07003525#define TSFS_SLOPE_MASK 0x0000ff00
3526#define TSFS_SLOPE_SHIFT 8
3527#define TSFS_INTR_MASK 0x000000ff
3528
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003529#define CRSTANDVID _MMIO(0x11100)
3530#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003531#define PXVFREQ_PX_MASK 0x7f000000
3532#define PXVFREQ_PX_SHIFT 24
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003533#define VIDFREQ_BASE _MMIO(0x11110)
3534#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3535#define VIDFREQ2 _MMIO(0x11114)
3536#define VIDFREQ3 _MMIO(0x11118)
3537#define VIDFREQ4 _MMIO(0x1111c)
Jesse Barnesf97108d2010-01-29 11:27:07 -08003538#define VIDFREQ_P0_MASK 0x1f000000
3539#define VIDFREQ_P0_SHIFT 24
3540#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3541#define VIDFREQ_P0_CSCLK_SHIFT 20
3542#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3543#define VIDFREQ_P0_CRCLK_SHIFT 16
3544#define VIDFREQ_P1_MASK 0x00001f00
3545#define VIDFREQ_P1_SHIFT 8
3546#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3547#define VIDFREQ_P1_CSCLK_SHIFT 4
3548#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003549#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3550#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003551#define INTTOEXT_MAP3_SHIFT 24
3552#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3553#define INTTOEXT_MAP2_SHIFT 16
3554#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3555#define INTTOEXT_MAP1_SHIFT 8
3556#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3557#define INTTOEXT_MAP0_SHIFT 0
3558#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003559#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003560#define MEMCTL_CMD_MASK 0xe000
3561#define MEMCTL_CMD_SHIFT 13
3562#define MEMCTL_CMD_RCLK_OFF 0
3563#define MEMCTL_CMD_RCLK_ON 1
3564#define MEMCTL_CMD_CHFREQ 2
3565#define MEMCTL_CMD_CHVID 3
3566#define MEMCTL_CMD_VMMOFF 4
3567#define MEMCTL_CMD_VMMON 5
3568#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
3569 when command complete */
3570#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3571#define MEMCTL_FREQ_SHIFT 8
3572#define MEMCTL_SFCAVM (1<<7)
3573#define MEMCTL_TGT_VID_MASK 0x007f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003574#define MEMIHYST _MMIO(0x1117c)
3575#define MEMINTREN _MMIO(0x11180) /* 16 bits */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003576#define MEMINT_RSEXIT_EN (1<<8)
3577#define MEMINT_CX_SUPR_EN (1<<7)
3578#define MEMINT_CONT_BUSY_EN (1<<6)
3579#define MEMINT_AVG_BUSY_EN (1<<5)
3580#define MEMINT_EVAL_CHG_EN (1<<4)
3581#define MEMINT_MON_IDLE_EN (1<<3)
3582#define MEMINT_UP_EVAL_EN (1<<2)
3583#define MEMINT_DOWN_EVAL_EN (1<<1)
3584#define MEMINT_SW_CMD_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003585#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003586#define MEM_RSEXIT_MASK 0xc000
3587#define MEM_RSEXIT_SHIFT 14
3588#define MEM_CONT_BUSY_MASK 0x3000
3589#define MEM_CONT_BUSY_SHIFT 12
3590#define MEM_AVG_BUSY_MASK 0x0c00
3591#define MEM_AVG_BUSY_SHIFT 10
3592#define MEM_EVAL_CHG_MASK 0x0300
3593#define MEM_EVAL_BUSY_SHIFT 8
3594#define MEM_MON_IDLE_MASK 0x00c0
3595#define MEM_MON_IDLE_SHIFT 6
3596#define MEM_UP_EVAL_MASK 0x0030
3597#define MEM_UP_EVAL_SHIFT 4
3598#define MEM_DOWN_EVAL_MASK 0x000c
3599#define MEM_DOWN_EVAL_SHIFT 2
3600#define MEM_SW_CMD_MASK 0x0003
3601#define MEM_INT_STEER_GFX 0
3602#define MEM_INT_STEER_CMR 1
3603#define MEM_INT_STEER_SMI 2
3604#define MEM_INT_STEER_SCI 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003605#define MEMINTRSTS _MMIO(0x11184)
Jesse Barnesf97108d2010-01-29 11:27:07 -08003606#define MEMINT_RSEXIT (1<<7)
3607#define MEMINT_CONT_BUSY (1<<6)
3608#define MEMINT_AVG_BUSY (1<<5)
3609#define MEMINT_EVAL_CHG (1<<4)
3610#define MEMINT_MON_IDLE (1<<3)
3611#define MEMINT_UP_EVAL (1<<2)
3612#define MEMINT_DOWN_EVAL (1<<1)
3613#define MEMINT_SW_CMD (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003614#define MEMMODECTL _MMIO(0x11190)
Jesse Barnesf97108d2010-01-29 11:27:07 -08003615#define MEMMODE_BOOST_EN (1<<31)
3616#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3617#define MEMMODE_BOOST_FREQ_SHIFT 24
3618#define MEMMODE_IDLE_MODE_MASK 0x00030000
3619#define MEMMODE_IDLE_MODE_SHIFT 16
3620#define MEMMODE_IDLE_MODE_EVAL 0
3621#define MEMMODE_IDLE_MODE_CONT 1
3622#define MEMMODE_HWIDLE_EN (1<<15)
3623#define MEMMODE_SWMODE_EN (1<<14)
3624#define MEMMODE_RCLK_GATE (1<<13)
3625#define MEMMODE_HW_UPDATE (1<<12)
3626#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3627#define MEMMODE_FSTART_SHIFT 8
3628#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3629#define MEMMODE_FMAX_SHIFT 4
3630#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003631#define RCBMAXAVG _MMIO(0x1119c)
3632#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08003633#define SWMEMCMD_RENDER_OFF (0 << 13)
3634#define SWMEMCMD_RENDER_ON (1 << 13)
3635#define SWMEMCMD_SWFREQ (2 << 13)
3636#define SWMEMCMD_TARVID (3 << 13)
3637#define SWMEMCMD_VRM_OFF (4 << 13)
3638#define SWMEMCMD_VRM_ON (5 << 13)
3639#define CMDSTS (1<<12)
3640#define SFCAVM (1<<11)
3641#define SWFREQ_MASK 0x0380 /* P0-7 */
3642#define SWFREQ_SHIFT 7
3643#define TARVID_MASK 0x001f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003644#define MEMSTAT_CTG _MMIO(0x111a0)
3645#define RCBMINAVG _MMIO(0x111a0)
3646#define RCUPEI _MMIO(0x111b0)
3647#define RCDNEI _MMIO(0x111b4)
3648#define RSTDBYCTL _MMIO(0x111b8)
Jesse Barnes88271da2011-01-05 12:01:24 -08003649#define RS1EN (1<<31)
3650#define RS2EN (1<<30)
3651#define RS3EN (1<<29)
3652#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
3653#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
3654#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
3655#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
3656#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
3657#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
3658#define RSX_STATUS_MASK (7<<20)
3659#define RSX_STATUS_ON (0<<20)
3660#define RSX_STATUS_RC1 (1<<20)
3661#define RSX_STATUS_RC1E (2<<20)
3662#define RSX_STATUS_RS1 (3<<20)
3663#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
3664#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
3665#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
3666#define RSX_STATUS_RSVD2 (7<<20)
3667#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
3668#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
3669#define JRSC (1<<17) /* rsx coupled to cpu c-state */
3670#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
3671#define RS1CONTSAV_MASK (3<<14)
3672#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
3673#define RS1CONTSAV_RSVD (1<<14)
3674#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
3675#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
3676#define NORMSLEXLAT_MASK (3<<12)
3677#define SLOW_RS123 (0<<12)
3678#define SLOW_RS23 (1<<12)
3679#define SLOW_RS3 (2<<12)
3680#define NORMAL_RS123 (3<<12)
3681#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
3682#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3683#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
3684#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
3685#define RS_CSTATE_MASK (3<<4)
3686#define RS_CSTATE_C367_RS1 (0<<4)
3687#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
3688#define RS_CSTATE_RSVD (2<<4)
3689#define RS_CSTATE_C367_RS2 (3<<4)
3690#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
3691#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003692#define VIDCTL _MMIO(0x111c0)
3693#define VIDSTS _MMIO(0x111c8)
3694#define VIDSTART _MMIO(0x111cc) /* 8 bits */
3695#define MEMSTAT_ILK _MMIO(0x111f8)
Jesse Barnesf97108d2010-01-29 11:27:07 -08003696#define MEMSTAT_VID_MASK 0x7f00
3697#define MEMSTAT_VID_SHIFT 8
3698#define MEMSTAT_PSTATE_MASK 0x00f8
3699#define MEMSTAT_PSTATE_SHIFT 3
3700#define MEMSTAT_MON_ACTV (1<<2)
3701#define MEMSTAT_SRC_CTL_MASK 0x0003
3702#define MEMSTAT_SRC_CTL_CORE 0
3703#define MEMSTAT_SRC_CTL_TRB 1
3704#define MEMSTAT_SRC_CTL_THM 2
3705#define MEMSTAT_SRC_CTL_STDBY 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003706#define RCPREVBSYTUPAVG _MMIO(0x113b8)
3707#define RCPREVBSYTDNAVG _MMIO(0x113bc)
3708#define PMMISC _MMIO(0x11214)
Jesse Barnesea056c12010-09-10 10:02:13 -07003709#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003710#define SDEW _MMIO(0x1124c)
3711#define CSIEW0 _MMIO(0x11250)
3712#define CSIEW1 _MMIO(0x11254)
3713#define CSIEW2 _MMIO(0x11258)
3714#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3715#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3716#define MCHAFE _MMIO(0x112c0)
3717#define CSIEC _MMIO(0x112e0)
3718#define DMIEC _MMIO(0x112e4)
3719#define DDREC _MMIO(0x112e8)
3720#define PEG0EC _MMIO(0x112ec)
3721#define PEG1EC _MMIO(0x112f0)
3722#define GFXEC _MMIO(0x112f4)
3723#define RPPREVBSYTUPAVG _MMIO(0x113b8)
3724#define RPPREVBSYTDNAVG _MMIO(0x113bc)
3725#define ECR _MMIO(0x11600)
Jesse Barnes7648fa92010-05-20 14:28:11 -07003726#define ECR_GPFE (1<<31)
3727#define ECR_IMONE (1<<30)
3728#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003729#define OGW0 _MMIO(0x11608)
3730#define OGW1 _MMIO(0x1160c)
3731#define EG0 _MMIO(0x11610)
3732#define EG1 _MMIO(0x11614)
3733#define EG2 _MMIO(0x11618)
3734#define EG3 _MMIO(0x1161c)
3735#define EG4 _MMIO(0x11620)
3736#define EG5 _MMIO(0x11624)
3737#define EG6 _MMIO(0x11628)
3738#define EG7 _MMIO(0x1162c)
3739#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3740#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3741#define LCFUSE02 _MMIO(0x116c0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07003742#define LCFUSE_HIV_MASK 0x000000ff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003743#define CSIPLL0 _MMIO(0x12c10)
3744#define DDRMPLL1 _MMIO(0X12c20)
3745#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
Eric Anholt7d573822009-01-02 13:33:00 -08003746
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003747#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
Chris Wilsonc4de7b02012-07-02 11:51:03 -03003748#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
Chris Wilsonc4de7b02012-07-02 11:51:03 -03003749
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003750#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3751#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3752#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3753#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3754#define BXT_RP_STATE_CAP _MMIO(0x138170)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08003755
Ville Syrjälä8a292d02016-04-20 16:43:56 +03003756/*
3757 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3758 * 8300) freezing up around GPU hangs. Looks as if even
3759 * scheduling/timer interrupts start misbehaving if the RPS
3760 * EI/thresholds are "bad", leading to a very sluggish or even
3761 * frozen machine.
3762 */
3763#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
Akash Goelde43ae92015-03-06 11:07:14 +05303764#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
Akash Goel26148bd2015-09-18 23:39:51 +05303765#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07003766#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02003767 (IS_GEN9_LP(dev_priv) ? \
Akash Goel26148bd2015-09-18 23:39:51 +05303768 INTERVAL_0_833_US(us) : \
3769 INTERVAL_1_33_US(us)) : \
Akash Goelde43ae92015-03-06 11:07:14 +05303770 INTERVAL_1_28_US(us))
3771
Akash Goel52530cb2016-04-23 00:05:44 +05303772#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3773#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3774#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07003775#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02003776 (IS_GEN9_LP(dev_priv) ? \
Akash Goel52530cb2016-04-23 00:05:44 +05303777 INTERVAL_0_833_TO_US(interval) : \
3778 INTERVAL_1_33_TO_US(interval)) : \
3779 INTERVAL_1_28_TO_US(interval))
3780
Jesse Barnes585fb112008-07-29 11:54:06 -07003781/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08003782 * Logical Context regs
3783 */
Chris Wilsonec62ed32017-02-07 15:24:37 +00003784#define CCID _MMIO(0x2180)
3785#define CCID_EN BIT(0)
3786#define CCID_EXTENDED_STATE_RESTORE BIT(2)
3787#define CCID_EXTENDED_STATE_SAVE BIT(3)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003788/*
3789 * Notes on SNB/IVB/VLV context size:
3790 * - Power context is saved elsewhere (LLC or stolen)
3791 * - Ring/execlist context is saved on SNB, not on IVB
3792 * - Extended context size already includes render context size
3793 * - We always need to follow the extended context size.
3794 * SNB BSpec has comments indicating that we should use the
3795 * render context size instead if execlists are disabled, but
3796 * based on empirical testing that's just nonsense.
3797 * - Pipelined/VF state is saved on SNB/IVB respectively
3798 * - GT1 size just indicates how much of render context
3799 * doesn't need saving on GT1
3800 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003801#define CXT_SIZE _MMIO(0x21a0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03003802#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3803#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3804#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3805#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3806#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003807#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07003808 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3809 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003810#define GEN7_CXT_SIZE _MMIO(0x21a8)
Ville Syrjälä68d97532015-09-18 20:03:39 +03003811#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3812#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3813#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3814#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3815#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3816#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003817#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07003818 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawsky88976442013-11-02 21:07:05 -07003819
Zhi Wangc01fc532016-06-16 08:07:02 -04003820enum {
3821 INTEL_ADVANCED_CONTEXT = 0,
3822 INTEL_LEGACY_32B_CONTEXT,
3823 INTEL_ADVANCED_AD_CONTEXT,
3824 INTEL_LEGACY_64B_CONTEXT
3825};
3826
Mika Kuoppala2355cf02017-01-27 15:03:09 +02003827enum {
3828 FAULT_AND_HANG = 0,
3829 FAULT_AND_HALT, /* Debug only */
3830 FAULT_AND_STREAM,
3831 FAULT_AND_CONTINUE /* Unsupported */
3832};
3833
3834#define GEN8_CTX_VALID (1<<0)
3835#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
3836#define GEN8_CTX_FORCE_RESTORE (1<<2)
3837#define GEN8_CTX_L3LLC_COHERENT (1<<5)
3838#define GEN8_CTX_PRIVILEGE (1<<8)
Zhi Wangc01fc532016-06-16 08:07:02 -04003839#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
Zhi Wangc01fc532016-06-16 08:07:02 -04003840
Mika Kuoppala2355cf02017-01-27 15:03:09 +02003841#define GEN8_CTX_ID_SHIFT 32
3842#define GEN8_CTX_ID_WIDTH 21
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003843
3844#define CHV_CLK_CTL1 _MMIO(0x101100)
3845#define VLV_CLK_CTL2 _MMIO(0x101104)
3846#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3847
3848/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003849 * Overlay regs
3850 */
Imre Deakd965e7ac2015-12-01 10:23:52 +02003851
3852#define OVADD _MMIO(0x30000)
3853#define DOVSTA _MMIO(0x30008)
3854#define OC_BUF (0x3<<20)
3855#define OGAMC5 _MMIO(0x30010)
3856#define OGAMC4 _MMIO(0x30014)
3857#define OGAMC3 _MMIO(0x30018)
Jesse Barnes585fb112008-07-29 11:54:06 -07003858#define OGAMC2 _MMIO(0x3001c)
3859#define OGAMC1 _MMIO(0x30020)
3860#define OGAMC0 _MMIO(0x30024)
Shuang He8bf1e9f2013-10-15 18:55:27 +01003861
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003862/*
Shuang He8bf1e9f2013-10-15 18:55:27 +01003863 * GEN9 clock gating regs
Daniel Vetterb4437a42013-10-16 22:55:54 +02003864 */
Shuang He8bf1e9f2013-10-15 18:55:27 +01003865#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
Rodrigo Vividf49ec82017-11-10 16:03:19 -08003866#define DARBF_GATING_DIS (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003867#define PWM2_GATING_DIS (1 << 14)
Shuang He8bf1e9f2013-10-15 18:55:27 +01003868#define PWM1_GATING_DIS (1 << 13)
3869
Ville Syrjälä6481d5e2017-12-21 22:24:32 +02003870#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3871#define BXT_GMBUS_GATING_DIS (1 << 14)
3872
Imre Deaked69cd42017-10-02 10:55:57 +03003873#define _CLKGATE_DIS_PSL_A 0x46520
3874#define _CLKGATE_DIS_PSL_B 0x46524
3875#define _CLKGATE_DIS_PSL_C 0x46528
3876#define DPF_GATING_DIS (1 << 10)
3877#define DPF_RAM_GATING_DIS (1 << 9)
3878#define DPFR_GATING_DIS (1 << 8)
3879
3880#define CLKGATE_DIS_PSL(pipe) \
3881 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3882
Shuang He8bf1e9f2013-10-15 18:55:27 +01003883/*
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07003884 * GEN10 clock gating regs
3885 */
3886#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3887#define SARBUNIT_CLKGATE_DIS (1 << 5)
Rafael Antognolli0a607972017-11-03 11:30:27 -07003888#define RCCUNIT_CLKGATE_DIS (1 << 7)
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07003889
Rafael Antognolli01ab0f92017-12-15 16:11:16 -08003890#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3891#define VFUNIT_CLKGATE_DIS (1 << 20)
3892
Rodrigo Vivi90007bc2017-08-15 16:16:48 -07003893/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003894 * Display engine regs
3895 */
3896
3897/* Pipe A CRC regs */
Shuang He8bf1e9f2013-10-15 18:55:27 +01003898#define _PIPE_CRC_CTL_A 0x60050
3899#define PIPE_CRC_ENABLE (1 << 31)
3900/* ivb+ source selection */
3901#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3902#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3903#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02003904/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003905#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3906#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3907#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3908/* embedded DP port on the north display block, reserved on ivb */
3909#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3910#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02003911/* vlv source selection */
3912#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3913#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3914#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3915/* with DP port the pipe source is invalid */
3916#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3917#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3918#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3919/* gen3+ source selection */
3920#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3921#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3922#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3923/* with DP/TV port the pipe source is invalid */
3924#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3925#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3926#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3927#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3928#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3929/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02003930#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02003931
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003932#define _PIPE_CRC_RES_1_A_IVB 0x60064
3933#define _PIPE_CRC_RES_2_A_IVB 0x60068
3934#define _PIPE_CRC_RES_3_A_IVB 0x6006c
3935#define _PIPE_CRC_RES_4_A_IVB 0x60070
3936#define _PIPE_CRC_RES_5_A_IVB 0x60074
3937
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003938#define _PIPE_CRC_RES_RED_A 0x60060
3939#define _PIPE_CRC_RES_GREEN_A 0x60064
3940#define _PIPE_CRC_RES_BLUE_A 0x60068
3941#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
3942#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01003943
3944/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003945#define _PIPE_CRC_RES_1_B_IVB 0x61064
3946#define _PIPE_CRC_RES_2_B_IVB 0x61068
3947#define _PIPE_CRC_RES_3_B_IVB 0x6106c
3948#define _PIPE_CRC_RES_4_B_IVB 0x61070
3949#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01003950
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003951#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3952#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3953#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3954#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3955#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3956#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01003957
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003958#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3959#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3960#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3961#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3962#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003963
Jesse Barnes585fb112008-07-29 11:54:06 -07003964/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003965#define _HTOTAL_A 0x60000
3966#define _HBLANK_A 0x60004
3967#define _HSYNC_A 0x60008
3968#define _VTOTAL_A 0x6000c
3969#define _VBLANK_A 0x60010
3970#define _VSYNC_A 0x60014
3971#define _PIPEASRC 0x6001c
3972#define _BCLRPAT_A 0x60020
3973#define _VSYNCSHIFT_A 0x60028
Clint Taylorebb69c92014-09-30 10:30:22 -07003974#define _PIPE_MULT_A 0x6002c
Jesse Barnes585fb112008-07-29 11:54:06 -07003975
3976/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003977#define _HTOTAL_B 0x61000
3978#define _HBLANK_B 0x61004
3979#define _HSYNC_B 0x61008
3980#define _VTOTAL_B 0x6100c
3981#define _VBLANK_B 0x61010
3982#define _VSYNC_B 0x61014
3983#define _PIPEBSRC 0x6101c
3984#define _BCLRPAT_B 0x61020
3985#define _VSYNCSHIFT_B 0x61028
Clint Taylorebb69c92014-09-30 10:30:22 -07003986#define _PIPE_MULT_B 0x6102c
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003987
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003988#define TRANSCODER_A_OFFSET 0x60000
3989#define TRANSCODER_B_OFFSET 0x61000
3990#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03003991#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003992#define TRANSCODER_EDP_OFFSET 0x6f000
3993
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003994#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003995 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3996 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003997
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003998#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
3999#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4000#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4001#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4002#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4003#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4004#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4005#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4006#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4007#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
Chris Wilson5eddb702010-09-11 13:48:45 +01004008
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08004009/* VLV eDP PSR registers */
4010#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4011#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4012#define VLV_EDP_PSR_ENABLE (1<<0)
4013#define VLV_EDP_PSR_RESET (1<<1)
4014#define VLV_EDP_PSR_MODE_MASK (7<<2)
4015#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
4016#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
4017#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
4018#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
4019#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
4020#define VLV_EDP_PSR_DBL_FRAME (1<<10)
4021#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
4022#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004023#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08004024
4025#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4026#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4027#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
4028#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
4029#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004030#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08004031
4032#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4033#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4034#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
4035#define VLV_EDP_PSR_CURR_STATE_MASK 7
4036#define VLV_EDP_PSR_DISABLED (0<<0)
4037#define VLV_EDP_PSR_INACTIVE (1<<0)
4038#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
4039#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
4040#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
4041#define VLV_EDP_PSR_EXIT (5<<0)
4042#define VLV_EDP_PSR_IN_TRANS (1<<7)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004043#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08004044
Ben Widawskyed8546a2013-11-04 22:45:05 -08004045/* HSW+ eDP PSR registers */
Ville Syrjälä443a3892015-11-11 20:34:15 +02004046#define HSW_EDP_PSR_BASE 0x64800
4047#define BDW_EDP_PSR_BASE 0x6f800
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004048#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004049#define EDP_PSR_ENABLE (1<<31)
Rodrigo Vivi82c56252014-06-12 10:16:42 -07004050#define BDW_PSR_SINGLE_FRAME (1<<30)
Jim Bride912d6412017-08-08 14:51:34 -07004051#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004052#define EDP_PSR_LINK_STANDBY (1<<27)
4053#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
4054#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
4055#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
4056#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
4057#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
4058#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4059#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
4060#define EDP_PSR_TP1_TP2_SEL (0<<11)
4061#define EDP_PSR_TP1_TP3_SEL (1<<11)
4062#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
4063#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
4064#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
4065#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
4066#define EDP_PSR_TP1_TIME_500us (0<<4)
4067#define EDP_PSR_TP1_TIME_100us (1<<4)
4068#define EDP_PSR_TP1_TIME_2500us (2<<4)
4069#define EDP_PSR_TP1_TIME_0us (3<<4)
4070#define EDP_PSR_IDLE_FRAME_SHIFT 0
4071
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004072#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4073#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004074
Dhinakaran Pandiyan861023e2017-12-20 12:10:21 -08004075#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004076#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004077#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
4078#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
4079#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
4080#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
4081#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
4082#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
4083#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
4084#define EDP_PSR_STATUS_LINK_MASK (3<<26)
4085#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
4086#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
4087#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
4088#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4089#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4090#define EDP_PSR_STATUS_COUNT_SHIFT 16
4091#define EDP_PSR_STATUS_COUNT_MASK 0xf
4092#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
4093#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
4094#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
4095#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
4096#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
4097#define EDP_PSR_STATUS_IDLE_MASK 0xf
4098
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004099#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004100#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004101
Dhinakaran Pandiyan861023e2017-12-20 12:10:21 -08004102#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
Nagaraju, Vathsala64332262017-01-13 06:01:24 +05304103#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
4104#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
4105#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
4106#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
4107#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16)
4108#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004109
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004110#define EDP_PSR2_CTL _MMIO(0x6f900)
Sonika Jindal474d1ec2015-04-02 11:02:44 +05304111#define EDP_PSR2_ENABLE (1<<31)
4112#define EDP_SU_TRACK_ENABLE (1<<30)
4113#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
4114#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
4115#define EDP_PSR2_TP2_TIME_500 (0<<8)
4116#define EDP_PSR2_TP2_TIME_100 (1<<8)
4117#define EDP_PSR2_TP2_TIME_2500 (2<<8)
4118#define EDP_PSR2_TP2_TIME_50 (3<<8)
4119#define EDP_PSR2_TP2_TIME_MASK (3<<8)
4120#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4121#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
4122#define EDP_PSR2_IDLE_MASK 0xf
vathsala nagaraju977da082017-09-26 15:29:13 +05304123#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
Sonika Jindal474d1ec2015-04-02 11:02:44 +05304124
Dhinakaran Pandiyan861023e2017-12-20 12:10:21 -08004125#define EDP_PSR2_STATUS _MMIO(0x6f940)
Nagaraju, Vathsala3fcb0ca2017-01-12 23:30:59 +05304126#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
Nagaraju, Vathsala6ba1f9e2017-01-06 22:02:32 +05304127#define EDP_PSR2_STATUS_STATE_SHIFT 28
Jesse Barnes585fb112008-07-29 11:54:06 -07004128
4129/* VGA port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004130#define ADPA _MMIO(0x61100)
4131#define PCH_ADPA _MMIO(0xe1100)
4132#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02004133
Jesse Barnes585fb112008-07-29 11:54:06 -07004134#define ADPA_DAC_ENABLE (1<<31)
4135#define ADPA_DAC_DISABLE 0
4136#define ADPA_PIPE_SELECT_MASK (1<<30)
4137#define ADPA_PIPE_A_SELECT 0
4138#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07004139#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02004140/* CPT uses bits 29:30 for pch transcoder select */
4141#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4142#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
4143#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
4144#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
4145#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
4146#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
4147#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
4148#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
4149#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
4150#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
4151#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
4152#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
4153#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
4154#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
4155#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
4156#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
4157#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
4158#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
4159#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07004160#define ADPA_USE_VGA_HVPOLARITY (1<<15)
4161#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01004162#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07004163#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01004164#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07004165#define ADPA_HSYNC_CNTL_ENABLE 0
4166#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
4167#define ADPA_VSYNC_ACTIVE_LOW 0
4168#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
4169#define ADPA_HSYNC_ACTIVE_LOW 0
4170#define ADPA_DPMS_MASK (~(3<<10))
4171#define ADPA_DPMS_ON (0<<10)
4172#define ADPA_DPMS_SUSPEND (1<<10)
4173#define ADPA_DPMS_STANDBY (2<<10)
4174#define ADPA_DPMS_OFF (3<<10)
4175
Chris Wilson939fe4d2010-10-09 10:33:26 +01004176
Jesse Barnes585fb112008-07-29 11:54:06 -07004177/* Hotplug control (945+ only) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004178#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01004179#define PORTB_HOTPLUG_INT_EN (1 << 29)
4180#define PORTC_HOTPLUG_INT_EN (1 << 28)
4181#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07004182#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4183#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4184#define TV_HOTPLUG_INT_EN (1 << 18)
4185#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05004186#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4187 PORTC_HOTPLUG_INT_EN | \
4188 PORTD_HOTPLUG_INT_EN | \
4189 SDVOC_HOTPLUG_INT_EN | \
4190 SDVOB_HOTPLUG_INT_EN | \
4191 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07004192#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08004193#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4194/* must use period 64 on GM45 according to docs */
4195#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4196#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4197#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4198#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4199#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4200#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4201#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4202#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4203#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4204#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4205#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4206#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07004207
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004208#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02004209/*
Ville Syrjälä0780cd32016-02-10 19:59:05 +02004210 * HDMI/DP bits are g4x+
Daniel Vetter0ce99f72013-07-26 11:27:49 +02004211 *
4212 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4213 * Please check the detailed lore in the commit message for for experimental
4214 * evidence.
4215 */
Ville Syrjälä0780cd32016-02-10 19:59:05 +02004216/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4217#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4218#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4219#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4220/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4221#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
Todd Previte232a6ee2014-01-23 00:13:41 -07004222#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
Ville Syrjälä0780cd32016-02-10 19:59:05 +02004223#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01004224#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02004225#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4226#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01004227#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02004228#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4229#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01004230#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02004231#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4232#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01004233/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07004234#define CRT_HOTPLUG_INT_STATUS (1 << 11)
4235#define TV_HOTPLUG_INT_STATUS (1 << 10)
4236#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4237#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4238#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4239#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01004240#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4241#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4242#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02004243#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4244
Chris Wilson084b6122012-05-11 18:01:33 +01004245/* SDVO is different across gen3/4 */
4246#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4247#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02004248/*
4249 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4250 * since reality corrobates that they're the same as on gen3. But keep these
4251 * bits here (and the comment!) to help any other lost wanderers back onto the
4252 * right tracks.
4253 */
Chris Wilson084b6122012-05-11 18:01:33 +01004254#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4255#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4256#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4257#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05004258#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4259 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4260 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4261 PORTB_HOTPLUG_INT_STATUS | \
4262 PORTC_HOTPLUG_INT_STATUS | \
4263 PORTD_HOTPLUG_INT_STATUS)
4264
Egbert Eiche5868a32013-02-28 04:17:12 -05004265#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4266 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4267 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4268 PORTB_HOTPLUG_INT_STATUS | \
4269 PORTC_HOTPLUG_INT_STATUS | \
4270 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07004271
Paulo Zanonic20cd312013-02-19 16:21:45 -03004272/* SDVO and HDMI port control.
4273 * The same register may be used for SDVO or HDMI */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004274#define _GEN3_SDVOB 0x61140
4275#define _GEN3_SDVOC 0x61160
4276#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4277#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004278#define GEN4_HDMIB GEN3_SDVOB
4279#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004280#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4281#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4282#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4283#define PCH_SDVOB _MMIO(0xe1140)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004284#define PCH_HDMIB PCH_SDVOB
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004285#define PCH_HDMIC _MMIO(0xe1150)
4286#define PCH_HDMID _MMIO(0xe1160)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004287
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004288#define PORT_DFT_I9XX _MMIO(0x61150)
Daniel Vetter84093602013-11-01 10:50:21 +01004289#define DC_BALANCE_RESET (1 << 25)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004290#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01004291#define DC_BALANCE_RESET_VLV (1 << 31)
Ville Syrjäläeb736672014-12-09 21:28:28 +02004292#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4293#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
Daniel Vetter84093602013-11-01 10:50:21 +01004294#define PIPE_B_SCRAMBLE_RESET (1 << 1)
4295#define PIPE_A_SCRAMBLE_RESET (1 << 0)
4296
Paulo Zanonic20cd312013-02-19 16:21:45 -03004297/* Gen 3 SDVO bits: */
4298#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03004299#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4300#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004301#define SDVO_PIPE_B_SELECT (1 << 30)
4302#define SDVO_STALL_SELECT (1 << 29)
4303#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004304/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004305 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07004306 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07004307 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4308 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03004309#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07004310#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03004311#define SDVO_PHASE_SELECT_MASK (15 << 19)
4312#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4313#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4314#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4315#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4316#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4317#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07004318/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03004319#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4320 SDVO_INTERRUPT_ENABLE)
4321#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4322
4323/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03004324#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03004325#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004326#define SDVO_ENCODING_SDVO (0 << 10)
4327#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03004328#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4329#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03004330#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03004331#define SDVO_AUDIO_ENABLE (1 << 6)
4332/* VSYNC/HSYNC bits new with 965, default is to be set */
4333#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4334#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4335
4336/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03004337#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03004338#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4339
4340/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03004341#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4342#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03004343
Chon Ming Lee44f37d12014-04-09 13:28:21 +03004344/* CHV SDVO/HDMI bits: */
4345#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4346#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4347
Jesse Barnes585fb112008-07-29 11:54:06 -07004348
4349/* DVO port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004350#define _DVOA 0x61120
4351#define DVOA _MMIO(_DVOA)
4352#define _DVOB 0x61140
4353#define DVOB _MMIO(_DVOB)
4354#define _DVOC 0x61160
4355#define DVOC _MMIO(_DVOC)
Jesse Barnes585fb112008-07-29 11:54:06 -07004356#define DVO_ENABLE (1 << 31)
4357#define DVO_PIPE_B_SELECT (1 << 30)
4358#define DVO_PIPE_STALL_UNUSED (0 << 28)
4359#define DVO_PIPE_STALL (1 << 28)
4360#define DVO_PIPE_STALL_TV (2 << 28)
4361#define DVO_PIPE_STALL_MASK (3 << 28)
4362#define DVO_USE_VGA_SYNC (1 << 15)
4363#define DVO_DATA_ORDER_I740 (0 << 14)
4364#define DVO_DATA_ORDER_FP (1 << 14)
4365#define DVO_VSYNC_DISABLE (1 << 11)
4366#define DVO_HSYNC_DISABLE (1 << 10)
4367#define DVO_VSYNC_TRISTATE (1 << 9)
4368#define DVO_HSYNC_TRISTATE (1 << 8)
4369#define DVO_BORDER_ENABLE (1 << 7)
4370#define DVO_DATA_ORDER_GBRG (1 << 6)
4371#define DVO_DATA_ORDER_RGGB (0 << 6)
4372#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4373#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4374#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4375#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4376#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4377#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4378#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4379#define DVO_PRESERVE_MASK (0x7<<24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004380#define DVOA_SRCDIM _MMIO(0x61124)
4381#define DVOB_SRCDIM _MMIO(0x61144)
4382#define DVOC_SRCDIM _MMIO(0x61164)
Jesse Barnes585fb112008-07-29 11:54:06 -07004383#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4384#define DVO_SRCDIM_VERTICAL_SHIFT 0
4385
4386/* LVDS port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004387#define LVDS _MMIO(0x61180)
Jesse Barnes585fb112008-07-29 11:54:06 -07004388/*
4389 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4390 * the DPLL semantics change when the LVDS is assigned to that pipe.
4391 */
4392#define LVDS_PORT_EN (1 << 31)
4393/* Selects pipe B for LVDS data. Must be set on pre-965. */
4394#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08004395#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07004396#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08004397/* LVDS dithering flag on 965/g4x platform */
4398#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08004399/* LVDS sync polarity flags. Set to invert (i.e. negative) */
4400#define LVDS_VSYNC_POLARITY (1 << 21)
4401#define LVDS_HSYNC_POLARITY (1 << 20)
4402
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004403/* Enable border for unscaled (or aspect-scaled) display */
4404#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07004405/*
4406 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4407 * pixel.
4408 */
4409#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4410#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4411#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4412/*
4413 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4414 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4415 * on.
4416 */
4417#define LVDS_A3_POWER_MASK (3 << 6)
4418#define LVDS_A3_POWER_DOWN (0 << 6)
4419#define LVDS_A3_POWER_UP (3 << 6)
4420/*
4421 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4422 * is set.
4423 */
4424#define LVDS_CLKB_POWER_MASK (3 << 4)
4425#define LVDS_CLKB_POWER_DOWN (0 << 4)
4426#define LVDS_CLKB_POWER_UP (3 << 4)
4427/*
4428 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4429 * setting for whether we are in dual-channel mode. The B3 pair will
4430 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4431 */
4432#define LVDS_B0B3_POWER_MASK (3 << 2)
4433#define LVDS_B0B3_POWER_DOWN (0 << 2)
4434#define LVDS_B0B3_POWER_UP (3 << 2)
4435
David Härdeman3c17fe42010-09-24 21:44:32 +02004436/* Video Data Island Packet control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004437#define VIDEO_DIP_DATA _MMIO(0x61178)
Yannick Guerrinifd0753c2015-02-28 17:20:41 +01004438/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
Paulo Zanoniadf00b22012-09-25 13:23:34 -03004439 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4440 * of the infoframe structure specified by CEA-861. */
4441#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004442#define VIDEO_DIP_VSC_DATA_SIZE 36
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004443#define VIDEO_DIP_CTL _MMIO(0x61170)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03004444/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02004445#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02004446#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03004447#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03004448#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02004449#define VIDEO_DIP_ENABLE_AVI (1 << 21)
4450#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03004451#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02004452#define VIDEO_DIP_ENABLE_SPD (8 << 21)
4453#define VIDEO_DIP_SELECT_AVI (0 << 19)
4454#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4455#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07004456#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02004457#define VIDEO_DIP_FREQ_ONCE (0 << 16)
4458#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4459#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03004460#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03004461/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03004462#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4463#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03004464#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03004465#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4466#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03004467#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02004468
Jesse Barnes585fb112008-07-29 11:54:06 -07004469/* Panel power sequencing */
Imre Deak44cb7342016-08-10 14:07:29 +03004470#define PPS_BASE 0x61200
4471#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4472#define PCH_PPS_BASE 0xC7200
4473
4474#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4475 PPS_BASE + (reg) + \
4476 (pps_idx) * 0x100)
4477
4478#define _PP_STATUS 0x61200
4479#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4480#define PP_ON (1 << 31)
Jesse Barnes585fb112008-07-29 11:54:06 -07004481/*
4482 * Indicates that all dependencies of the panel are on:
4483 *
4484 * - PLL enabled
4485 * - pipe enabled
4486 * - LVDS/DVOB/DVOC on
4487 */
Imre Deak44cb7342016-08-10 14:07:29 +03004488#define PP_READY (1 << 30)
4489#define PP_SEQUENCE_NONE (0 << 28)
4490#define PP_SEQUENCE_POWER_UP (1 << 28)
4491#define PP_SEQUENCE_POWER_DOWN (2 << 28)
4492#define PP_SEQUENCE_MASK (3 << 28)
4493#define PP_SEQUENCE_SHIFT 28
4494#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4495#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07004496#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4497#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4498#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4499#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4500#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4501#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4502#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4503#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4504#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Imre Deak44cb7342016-08-10 14:07:29 +03004505
4506#define _PP_CONTROL 0x61204
4507#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4508#define PANEL_UNLOCK_REGS (0xabcd << 16)
4509#define PANEL_UNLOCK_MASK (0xffff << 16)
4510#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4511#define BXT_POWER_CYCLE_DELAY_SHIFT 4
4512#define EDP_FORCE_VDD (1 << 3)
4513#define EDP_BLC_ENABLE (1 << 2)
4514#define PANEL_POWER_RESET (1 << 1)
4515#define PANEL_POWER_OFF (0 << 0)
4516#define PANEL_POWER_ON (1 << 0)
Imre Deak44cb7342016-08-10 14:07:29 +03004517
4518#define _PP_ON_DELAYS 0x61208
4519#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
Imre Deaked6143b82016-08-10 14:07:31 +03004520#define PANEL_PORT_SELECT_SHIFT 30
Imre Deak44cb7342016-08-10 14:07:29 +03004521#define PANEL_PORT_SELECT_MASK (3 << 30)
4522#define PANEL_PORT_SELECT_LVDS (0 << 30)
4523#define PANEL_PORT_SELECT_DPA (1 << 30)
4524#define PANEL_PORT_SELECT_DPC (2 << 30)
4525#define PANEL_PORT_SELECT_DPD (3 << 30)
4526#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4527#define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4528#define PANEL_POWER_UP_DELAY_SHIFT 16
4529#define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4530#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4531
4532#define _PP_OFF_DELAYS 0x6120C
4533#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4534#define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4535#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4536#define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4537#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4538
4539#define _PP_DIVISOR 0x61210
4540#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4541#define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4542#define PP_REFERENCE_DIVIDER_SHIFT 8
4543#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4544#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Jesse Barnes585fb112008-07-29 11:54:06 -07004545
4546/* Panel fitting */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004547#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07004548#define PFIT_ENABLE (1 << 31)
4549#define PFIT_PIPE_MASK (3 << 29)
4550#define PFIT_PIPE_SHIFT 29
4551#define VERT_INTERP_DISABLE (0 << 10)
4552#define VERT_INTERP_BILINEAR (1 << 10)
4553#define VERT_INTERP_MASK (3 << 10)
4554#define VERT_AUTO_SCALE (1 << 9)
4555#define HORIZ_INTERP_DISABLE (0 << 6)
4556#define HORIZ_INTERP_BILINEAR (1 << 6)
4557#define HORIZ_INTERP_MASK (3 << 6)
4558#define HORIZ_AUTO_SCALE (1 << 5)
4559#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08004560#define PFIT_FILTER_FUZZY (0 << 24)
4561#define PFIT_SCALING_AUTO (0 << 26)
4562#define PFIT_SCALING_PROGRAMMED (1 << 26)
4563#define PFIT_SCALING_PILLAR (2 << 26)
4564#define PFIT_SCALING_LETTER (3 << 26)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004565#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08004566/* Pre-965 */
4567#define PFIT_VERT_SCALE_SHIFT 20
4568#define PFIT_VERT_SCALE_MASK 0xfff00000
4569#define PFIT_HORIZ_SCALE_SHIFT 4
4570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4571/* 965+ */
4572#define PFIT_VERT_SCALE_SHIFT_965 16
4573#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4574#define PFIT_HORIZ_SCALE_SHIFT_965 0
4575#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4576
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004577#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07004578
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004579#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4580#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004581#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4582 _VLV_BLC_PWM_CTL2_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02004583
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004584#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4585#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004586#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4587 _VLV_BLC_PWM_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02004588
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004589#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4590#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004591#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4592 _VLV_BLC_HIST_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02004593
Jesse Barnes585fb112008-07-29 11:54:06 -07004594/* Backlight control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004595#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02004596#define BLM_PWM_ENABLE (1 << 31)
4597#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4598#define BLM_PIPE_SELECT (1 << 29)
4599#define BLM_PIPE_SELECT_IVB (3 << 29)
4600#define BLM_PIPE_A (0 << 29)
4601#define BLM_PIPE_B (1 << 29)
4602#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03004603#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4604#define BLM_TRANSCODER_B BLM_PIPE_B
4605#define BLM_TRANSCODER_C BLM_PIPE_C
4606#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02004607#define BLM_PIPE(pipe) ((pipe) << 29)
4608#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4609#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4610#define BLM_PHASE_IN_ENABLE (1 << 25)
4611#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4612#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4613#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4614#define BLM_PHASE_IN_COUNT_SHIFT (8)
4615#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4616#define BLM_PHASE_IN_INCR_SHIFT (0)
4617#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004618#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01004619/*
4620 * This is the most significant 15 bits of the number of backlight cycles in a
4621 * complete cycle of the modulated backlight control.
4622 *
4623 * The actual value is this field multiplied by two.
4624 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02004625#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4626#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4627#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07004628/*
4629 * This is the number of cycles out of the backlight modulation cycle for which
4630 * the backlight is on.
4631 *
4632 * This field must be no greater than the number of cycles in the complete
4633 * backlight modulation cycle.
4634 */
4635#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4636#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02004637#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4638#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07004639
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004640#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
Jani Nikula2059ac32015-06-26 14:18:56 +03004641#define BLM_HISTOGRAM_ENABLE (1 << 31)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07004642
Daniel Vetter7cf41602012-06-05 10:07:09 +02004643/* New registers for PCH-split platforms. Safe where new bits show up, the
4644 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004645#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4646#define BLC_PWM_CPU_CTL _MMIO(0x48254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02004647
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004648#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03004649
Daniel Vetter7cf41602012-06-05 10:07:09 +02004650/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4651 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004652#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
Daniel Vetter4b4147c2012-07-11 00:31:06 +02004653#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02004654#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4655#define BLM_PCH_POLARITY (1 << 29)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004656#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02004657
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004658#define UTIL_PIN_CTL _MMIO(0x48400)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03004659#define UTIL_PIN_ENABLE (1 << 31)
4660
Sunil Kamath022e4e52015-09-30 22:34:57 +05304661#define UTIL_PIN_PIPE(x) ((x) << 29)
4662#define UTIL_PIN_PIPE_MASK (3 << 29)
4663#define UTIL_PIN_MODE_PWM (1 << 24)
4664#define UTIL_PIN_MODE_MASK (0xf << 24)
4665#define UTIL_PIN_POLARITY (1 << 22)
4666
Vandana Kannan0fb890c2015-05-05 14:51:56 +05304667/* BXT backlight register definition. */
Sunil Kamath022e4e52015-09-30 22:34:57 +05304668#define _BXT_BLC_PWM_CTL1 0xC8250
Vandana Kannan0fb890c2015-05-05 14:51:56 +05304669#define BXT_BLC_PWM_ENABLE (1 << 31)
4670#define BXT_BLC_PWM_POLARITY (1 << 29)
Sunil Kamath022e4e52015-09-30 22:34:57 +05304671#define _BXT_BLC_PWM_FREQ1 0xC8254
4672#define _BXT_BLC_PWM_DUTY1 0xC8258
Vandana Kannan0fb890c2015-05-05 14:51:56 +05304673
Sunil Kamath022e4e52015-09-30 22:34:57 +05304674#define _BXT_BLC_PWM_CTL2 0xC8350
4675#define _BXT_BLC_PWM_FREQ2 0xC8354
4676#define _BXT_BLC_PWM_DUTY2 0xC8358
Vandana Kannan0fb890c2015-05-05 14:51:56 +05304677
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004678#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05304679 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004680#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05304681 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004682#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05304683 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
Vandana Kannan0fb890c2015-05-05 14:51:56 +05304684
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004685#define PCH_GTC_CTL _MMIO(0xe7000)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03004686#define PCH_GTC_ENABLE (1 << 31)
4687
Jesse Barnes585fb112008-07-29 11:54:06 -07004688/* TV port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004689#define TV_CTL _MMIO(0x68000)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004690/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07004691# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004692/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004693# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004694/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004695# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004696/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004697# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004698/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004699# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004700/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004701# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4702# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004703/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004704# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004705/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07004706# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004707/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07004708# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004709/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07004710# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004711/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07004712# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004713/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07004714# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004715/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004716# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004717/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07004718# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004719/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07004720# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004721/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004722 * Enables a fix for the 915GM only.
4723 *
4724 * Not sure what it does.
4725 */
4726# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004727/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08004728# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07004729# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004730/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07004731# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004732/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07004733# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004734/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004735# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004736/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07004737# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004738/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07004739# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004740/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07004741# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004742/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07004743# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004744/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07004745# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004746/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07004747# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004748/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004749 * This test mode forces the DACs to 50% of full output.
4750 *
4751 * This is used for load detection in combination with TVDAC_SENSE_MASK
4752 */
4753# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4754# define TV_TEST_MODE_MASK (7 << 0)
4755
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004756#define TV_DAC _MMIO(0x68004)
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01004757# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03004758/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004759 * Reports that DAC state change logic has reported change (RO).
4760 *
4761 * This gets cleared when TV_DAC_STATE_EN is cleared
4762*/
4763# define TVDAC_STATE_CHG (1 << 31)
4764# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004765/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07004766# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004767/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07004768# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004769/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07004770# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004771/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004772 * Enables DAC state detection logic, for load-based TV detection.
4773 *
4774 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4775 * to off, for load detection to work.
4776 */
4777# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004778/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07004779# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004780/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07004781# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004782/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07004783# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004784/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07004785# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004786/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07004787# define ENC_TVDAC_SLEW_FAST (1 << 6)
4788# define DAC_A_1_3_V (0 << 4)
4789# define DAC_A_1_1_V (1 << 4)
4790# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08004791# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07004792# define DAC_B_1_3_V (0 << 2)
4793# define DAC_B_1_1_V (1 << 2)
4794# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08004795# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07004796# define DAC_C_1_3_V (0 << 0)
4797# define DAC_C_1_1_V (1 << 0)
4798# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08004799# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07004800
Ville Syrjälä646b4262014-04-25 20:14:30 +03004801/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004802 * CSC coefficients are stored in a floating point format with 9 bits of
4803 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4804 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4805 * -1 (0x3) being the only legal negative value.
4806 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004807#define TV_CSC_Y _MMIO(0x68010)
Jesse Barnes585fb112008-07-29 11:54:06 -07004808# define TV_RY_MASK 0x07ff0000
4809# define TV_RY_SHIFT 16
4810# define TV_GY_MASK 0x00000fff
4811# define TV_GY_SHIFT 0
4812
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004813#define TV_CSC_Y2 _MMIO(0x68014)
Jesse Barnes585fb112008-07-29 11:54:06 -07004814# define TV_BY_MASK 0x07ff0000
4815# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004816/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004817 * Y attenuation for component video.
4818 *
4819 * Stored in 1.9 fixed point.
4820 */
4821# define TV_AY_MASK 0x000003ff
4822# define TV_AY_SHIFT 0
4823
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004824#define TV_CSC_U _MMIO(0x68018)
Jesse Barnes585fb112008-07-29 11:54:06 -07004825# define TV_RU_MASK 0x07ff0000
4826# define TV_RU_SHIFT 16
4827# define TV_GU_MASK 0x000007ff
4828# define TV_GU_SHIFT 0
4829
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004830#define TV_CSC_U2 _MMIO(0x6801c)
Jesse Barnes585fb112008-07-29 11:54:06 -07004831# define TV_BU_MASK 0x07ff0000
4832# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004833/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004834 * U attenuation for component video.
4835 *
4836 * Stored in 1.9 fixed point.
4837 */
4838# define TV_AU_MASK 0x000003ff
4839# define TV_AU_SHIFT 0
4840
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004841#define TV_CSC_V _MMIO(0x68020)
Jesse Barnes585fb112008-07-29 11:54:06 -07004842# define TV_RV_MASK 0x0fff0000
4843# define TV_RV_SHIFT 16
4844# define TV_GV_MASK 0x000007ff
4845# define TV_GV_SHIFT 0
4846
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004847#define TV_CSC_V2 _MMIO(0x68024)
Jesse Barnes585fb112008-07-29 11:54:06 -07004848# define TV_BV_MASK 0x07ff0000
4849# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004850/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004851 * V attenuation for component video.
4852 *
4853 * Stored in 1.9 fixed point.
4854 */
4855# define TV_AV_MASK 0x000007ff
4856# define TV_AV_SHIFT 0
4857
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004858#define TV_CLR_KNOBS _MMIO(0x68028)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004859/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07004860# define TV_BRIGHTNESS_MASK 0xff000000
4861# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03004862/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07004863# define TV_CONTRAST_MASK 0x00ff0000
4864# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004865/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07004866# define TV_SATURATION_MASK 0x0000ff00
4867# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03004868/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07004869# define TV_HUE_MASK 0x000000ff
4870# define TV_HUE_SHIFT 0
4871
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004872#define TV_CLR_LEVEL _MMIO(0x6802c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004873/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07004874# define TV_BLACK_LEVEL_MASK 0x01ff0000
4875# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004876/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07004877# define TV_BLANK_LEVEL_MASK 0x000001ff
4878# define TV_BLANK_LEVEL_SHIFT 0
4879
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004880#define TV_H_CTL_1 _MMIO(0x68030)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004881/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004882# define TV_HSYNC_END_MASK 0x1fff0000
4883# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004884/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07004885# define TV_HTOTAL_MASK 0x00001fff
4886# define TV_HTOTAL_SHIFT 0
4887
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004888#define TV_H_CTL_2 _MMIO(0x68034)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004889/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004890# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004891/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004892# define TV_HBURST_START_SHIFT 16
4893# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004894/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07004895# define TV_HBURST_LEN_SHIFT 0
4896# define TV_HBURST_LEN_MASK 0x0001fff
4897
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004898#define TV_H_CTL_3 _MMIO(0x68038)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004899/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07004900# define TV_HBLANK_END_SHIFT 16
4901# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004902/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07004903# define TV_HBLANK_START_SHIFT 0
4904# define TV_HBLANK_START_MASK 0x0001fff
4905
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004906#define TV_V_CTL_1 _MMIO(0x6803c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004907/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004908# define TV_NBR_END_SHIFT 16
4909# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004910/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004911# define TV_VI_END_F1_SHIFT 8
4912# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03004913/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004914# define TV_VI_END_F2_SHIFT 0
4915# define TV_VI_END_F2_MASK 0x0000003f
4916
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004917#define TV_V_CTL_2 _MMIO(0x68040)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004918/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07004919# define TV_VSYNC_LEN_MASK 0x07ff0000
4920# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004921/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07004922 * number of half lines.
4923 */
4924# define TV_VSYNC_START_F1_MASK 0x00007f00
4925# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03004926/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004927 * Offset of the start of vsync in field 2, measured in one less than the
4928 * number of half lines.
4929 */
4930# define TV_VSYNC_START_F2_MASK 0x0000007f
4931# define TV_VSYNC_START_F2_SHIFT 0
4932
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004933#define TV_V_CTL_3 _MMIO(0x68044)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004934/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07004935# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004936/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07004937# define TV_VEQ_LEN_MASK 0x007f0000
4938# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004939/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07004940 * the number of half lines.
4941 */
4942# define TV_VEQ_START_F1_MASK 0x0007f00
4943# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03004944/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004945 * Offset of the start of equalization in field 2, measured in one less than
4946 * the number of half lines.
4947 */
4948# define TV_VEQ_START_F2_MASK 0x000007f
4949# define TV_VEQ_START_F2_SHIFT 0
4950
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004951#define TV_V_CTL_4 _MMIO(0x68048)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004952/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004953 * Offset to start of vertical colorburst, measured in one less than the
4954 * number of lines from vertical start.
4955 */
4956# define TV_VBURST_START_F1_MASK 0x003f0000
4957# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004958/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004959 * Offset to the end of vertical colorburst, measured in one less than the
4960 * number of lines from the start of NBR.
4961 */
4962# define TV_VBURST_END_F1_MASK 0x000000ff
4963# define TV_VBURST_END_F1_SHIFT 0
4964
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004965#define TV_V_CTL_5 _MMIO(0x6804c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004966/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004967 * Offset to start of vertical colorburst, measured in one less than the
4968 * number of lines from vertical start.
4969 */
4970# define TV_VBURST_START_F2_MASK 0x003f0000
4971# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004972/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004973 * Offset to the end of vertical colorburst, measured in one less than the
4974 * number of lines from the start of NBR.
4975 */
4976# define TV_VBURST_END_F2_MASK 0x000000ff
4977# define TV_VBURST_END_F2_SHIFT 0
4978
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004979#define TV_V_CTL_6 _MMIO(0x68050)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004980/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004981 * Offset to start of vertical colorburst, measured in one less than the
4982 * number of lines from vertical start.
4983 */
4984# define TV_VBURST_START_F3_MASK 0x003f0000
4985# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004986/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004987 * Offset to the end of vertical colorburst, measured in one less than the
4988 * number of lines from the start of NBR.
4989 */
4990# define TV_VBURST_END_F3_MASK 0x000000ff
4991# define TV_VBURST_END_F3_SHIFT 0
4992
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004993#define TV_V_CTL_7 _MMIO(0x68054)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004994/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004995 * Offset to start of vertical colorburst, measured in one less than the
4996 * number of lines from vertical start.
4997 */
4998# define TV_VBURST_START_F4_MASK 0x003f0000
4999# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005000/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005001 * Offset to the end of vertical colorburst, measured in one less than the
5002 * number of lines from the start of NBR.
5003 */
5004# define TV_VBURST_END_F4_MASK 0x000000ff
5005# define TV_VBURST_END_F4_SHIFT 0
5006
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005007#define TV_SC_CTL_1 _MMIO(0x68060)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005008/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005009# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005010/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005011# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005012/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005013# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005014/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005015# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005016/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005017# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005018/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07005019# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005020/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07005021# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005022/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07005023# define TV_BURST_LEVEL_MASK 0x00ff0000
5024# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005025/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005026# define TV_SCDDA1_INC_MASK 0x00000fff
5027# define TV_SCDDA1_INC_SHIFT 0
5028
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005029#define TV_SC_CTL_2 _MMIO(0x68064)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005030/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005031# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5032# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005033/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005034# define TV_SCDDA2_INC_MASK 0x00007fff
5035# define TV_SCDDA2_INC_SHIFT 0
5036
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005037#define TV_SC_CTL_3 _MMIO(0x68068)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005038/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005039# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5040# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005041/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07005042# define TV_SCDDA3_INC_MASK 0x00007fff
5043# define TV_SCDDA3_INC_SHIFT 0
5044
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005045#define TV_WIN_POS _MMIO(0x68070)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005046/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07005047# define TV_XPOS_MASK 0x1fff0000
5048# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005049/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07005050# define TV_YPOS_MASK 0x00000fff
5051# define TV_YPOS_SHIFT 0
5052
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005053#define TV_WIN_SIZE _MMIO(0x68074)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005054/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07005055# define TV_XSIZE_MASK 0x1fff0000
5056# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005057/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005058 * Vertical size of the display window, measured in pixels.
5059 *
5060 * Must be even for interlaced modes.
5061 */
5062# define TV_YSIZE_MASK 0x00000fff
5063# define TV_YSIZE_SHIFT 0
5064
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005065#define TV_FILTER_CTL_1 _MMIO(0x68080)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005066/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005067 * Enables automatic scaling calculation.
5068 *
5069 * If set, the rest of the registers are ignored, and the calculated values can
5070 * be read back from the register.
5071 */
5072# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005073/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005074 * Disables the vertical filter.
5075 *
5076 * This is required on modes more than 1024 pixels wide */
5077# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005078/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07005079# define TV_VADAPT (1 << 28)
5080# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005081/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005082# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005083/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005084# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005085/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07005086# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005087/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005088 * Sets the horizontal scaling factor.
5089 *
5090 * This should be the fractional part of the horizontal scaling factor divided
5091 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5092 *
5093 * (src width - 1) / ((oversample * dest width) - 1)
5094 */
5095# define TV_HSCALE_FRAC_MASK 0x00003fff
5096# define TV_HSCALE_FRAC_SHIFT 0
5097
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005098#define TV_FILTER_CTL_2 _MMIO(0x68084)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005099/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005100 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5101 *
5102 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5103 */
5104# define TV_VSCALE_INT_MASK 0x00038000
5105# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03005106/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005107 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5108 *
5109 * \sa TV_VSCALE_INT_MASK
5110 */
5111# define TV_VSCALE_FRAC_MASK 0x00007fff
5112# define TV_VSCALE_FRAC_SHIFT 0
5113
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005114#define TV_FILTER_CTL_3 _MMIO(0x68088)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005115/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005116 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5117 *
5118 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5119 *
5120 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5121 */
5122# define TV_VSCALE_IP_INT_MASK 0x00038000
5123# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03005124/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005125 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5126 *
5127 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5128 *
5129 * \sa TV_VSCALE_IP_INT_MASK
5130 */
5131# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5132# define TV_VSCALE_IP_FRAC_SHIFT 0
5133
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005134#define TV_CC_CONTROL _MMIO(0x68090)
Jesse Barnes585fb112008-07-29 11:54:06 -07005135# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005136/*
Jesse Barnes585fb112008-07-29 11:54:06 -07005137 * Specifies which field to send the CC data in.
5138 *
5139 * CC data is usually sent in field 0.
5140 */
5141# define TV_CC_FID_MASK (1 << 27)
5142# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03005143/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005144# define TV_CC_HOFF_MASK 0x03ff0000
5145# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005146/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07005147# define TV_CC_LINE_MASK 0x0000003f
5148# define TV_CC_LINE_SHIFT 0
5149
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005150#define TV_CC_DATA _MMIO(0x68094)
Jesse Barnes585fb112008-07-29 11:54:06 -07005151# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03005152/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005153# define TV_CC_DATA_2_MASK 0x007f0000
5154# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03005155/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07005156# define TV_CC_DATA_1_MASK 0x0000007f
5157# define TV_CC_DATA_1_SHIFT 0
5158
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005159#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5160#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5161#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5162#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
Jesse Barnes585fb112008-07-29 11:54:06 -07005163
Keith Packard040d87f2009-05-30 20:42:33 -07005164/* Display Port */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005165#define DP_A _MMIO(0x64000) /* eDP */
5166#define DP_B _MMIO(0x64100)
5167#define DP_C _MMIO(0x64200)
5168#define DP_D _MMIO(0x64300)
Keith Packard040d87f2009-05-30 20:42:33 -07005169
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005170#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5171#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5172#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
Ville Syrjäläe66eb812015-09-18 20:03:34 +03005173
Keith Packard040d87f2009-05-30 20:42:33 -07005174#define DP_PORT_EN (1 << 31)
5175#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08005176#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03005177#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
5178#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08005179
Keith Packard040d87f2009-05-30 20:42:33 -07005180/* Link training mode - select a suitable mode for each stage */
5181#define DP_LINK_TRAIN_PAT_1 (0 << 28)
5182#define DP_LINK_TRAIN_PAT_2 (1 << 28)
5183#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5184#define DP_LINK_TRAIN_OFF (3 << 28)
5185#define DP_LINK_TRAIN_MASK (3 << 28)
5186#define DP_LINK_TRAIN_SHIFT 28
Ville Syrjäläaad3d142014-06-28 02:04:25 +03005187#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
5188#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
Keith Packard040d87f2009-05-30 20:42:33 -07005189
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005190/* CPT Link training mode */
5191#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5192#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5193#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5194#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5195#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5196#define DP_LINK_TRAIN_SHIFT_CPT 8
5197
Keith Packard040d87f2009-05-30 20:42:33 -07005198/* Signal voltages. These are mostly controlled by the other end */
5199#define DP_VOLTAGE_0_4 (0 << 25)
5200#define DP_VOLTAGE_0_6 (1 << 25)
5201#define DP_VOLTAGE_0_8 (2 << 25)
5202#define DP_VOLTAGE_1_2 (3 << 25)
5203#define DP_VOLTAGE_MASK (7 << 25)
5204#define DP_VOLTAGE_SHIFT 25
5205
5206/* Signal pre-emphasis levels, like voltages, the other end tells us what
5207 * they want
5208 */
5209#define DP_PRE_EMPHASIS_0 (0 << 22)
5210#define DP_PRE_EMPHASIS_3_5 (1 << 22)
5211#define DP_PRE_EMPHASIS_6 (2 << 22)
5212#define DP_PRE_EMPHASIS_9_5 (3 << 22)
5213#define DP_PRE_EMPHASIS_MASK (7 << 22)
5214#define DP_PRE_EMPHASIS_SHIFT 22
5215
5216/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02005217#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07005218#define DP_PORT_WIDTH_MASK (7 << 19)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03005219#define DP_PORT_WIDTH_SHIFT 19
Keith Packard040d87f2009-05-30 20:42:33 -07005220
5221/* Mystic DPCD version 1.1 special mode */
5222#define DP_ENHANCED_FRAMING (1 << 18)
5223
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005224/* eDP */
5225#define DP_PLL_FREQ_270MHZ (0 << 16)
Ville Syrjäläb377e0d2015-10-29 21:25:59 +02005226#define DP_PLL_FREQ_162MHZ (1 << 16)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005227#define DP_PLL_FREQ_MASK (3 << 16)
5228
Ville Syrjälä646b4262014-04-25 20:14:30 +03005229/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07005230#define DP_PORT_REVERSAL (1 << 15)
5231
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005232/* eDP */
5233#define DP_PLL_ENABLE (1 << 14)
5234
Ville Syrjälä646b4262014-04-25 20:14:30 +03005235/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07005236#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5237
5238#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005239#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07005240
Ville Syrjälä646b4262014-04-25 20:14:30 +03005241/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07005242#define DP_COLOR_RANGE_16_235 (1 << 8)
5243
Ville Syrjälä646b4262014-04-25 20:14:30 +03005244/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07005245#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5246
Ville Syrjälä646b4262014-04-25 20:14:30 +03005247/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07005248#define DP_SYNC_VS_HIGH (1 << 4)
5249#define DP_SYNC_HS_HIGH (1 << 3)
5250
Ville Syrjälä646b4262014-04-25 20:14:30 +03005251/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07005252#define DP_DETECTED (1 << 2)
5253
Ville Syrjälä646b4262014-04-25 20:14:30 +03005254/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07005255 * signal sink for DDC etc. Max packet size supported
5256 * is 20 bytes in each direction, hence the 5 fixed
5257 * data registers
5258 */
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02005259#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5260#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5261#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5262#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5263#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5264#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005265
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02005266#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5267#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5268#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5269#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5270#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5271#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
Keith Packard040d87f2009-05-30 20:42:33 -07005272
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02005273#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5274#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5275#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5276#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5277#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5278#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
Keith Packard040d87f2009-05-30 20:42:33 -07005279
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02005280#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5281#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5282#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5283#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5284#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5285#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
Ville Syrjälä750a9512015-11-11 20:34:12 +02005286
Rodrigo Vivia324fca2018-01-29 15:22:15 -08005287#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5288#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5289#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5290#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5291#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5292#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5293
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005294#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5295#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Keith Packard040d87f2009-05-30 20:42:33 -07005296
5297#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5298#define DP_AUX_CH_CTL_DONE (1 << 30)
5299#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5300#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5301#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5302#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5303#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
James Ausmus6fa228b2017-10-12 14:30:36 -07005304#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
Keith Packard040d87f2009-05-30 20:42:33 -07005305#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5306#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5307#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5308#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5309#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5310#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5311#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5312#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5313#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5314#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5315#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5316#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5317#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
Sonika Jindale3d99842015-01-22 14:30:54 +05305318#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5319#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5320#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
Ville Syrjälä395b2912015-09-18 20:03:40 +03005321#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
Sonika Jindale3d99842015-01-22 14:30:54 +05305322#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00005323#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
Keith Packard040d87f2009-05-30 20:42:33 -07005324
5325/*
5326 * Computing GMCH M and N values for the Display Port link
5327 *
5328 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5329 *
5330 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5331 *
5332 * The GMCH value is used internally
5333 *
5334 * bytes_per_pixel is the number of bytes coming out of the plane,
5335 * which is after the LUTs, so we want the bytes for our color format.
5336 * For our current usage, this is always 3, one byte for R, G and B.
5337 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02005338#define _PIPEA_DATA_M_G4X 0x70050
5339#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07005340
5341/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005342#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02005343#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005344#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07005345
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005346#define DATA_LINK_M_N_MASK (0xffffff)
5347#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07005348
Daniel Vettere3b95f12013-05-03 11:49:49 +02005349#define _PIPEA_DATA_N_G4X 0x70054
5350#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07005351#define PIPE_GMCH_DATA_N_MASK (0xffffff)
5352
5353/*
5354 * Computing Link M and N values for the Display Port link
5355 *
5356 * Link M / N = pixel_clock / ls_clk
5357 *
5358 * (the DP spec calls pixel_clock the 'strm_clk')
5359 *
5360 * The Link value is transmitted in the Main Stream
5361 * Attributes and VB-ID.
5362 */
5363
Daniel Vettere3b95f12013-05-03 11:49:49 +02005364#define _PIPEA_LINK_M_G4X 0x70060
5365#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07005366#define PIPEA_DP_LINK_M_MASK (0xffffff)
5367
Daniel Vettere3b95f12013-05-03 11:49:49 +02005368#define _PIPEA_LINK_N_G4X 0x70064
5369#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07005370#define PIPEA_DP_LINK_N_MASK (0xffffff)
5371
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005372#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5373#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5374#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5375#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005376
Jesse Barnes585fb112008-07-29 11:54:06 -07005377/* Display & cursor control */
5378
5379/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005380#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03005381#define DSL_LINEMASK_GEN2 0x00000fff
5382#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005383#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01005384#define PIPECONF_ENABLE (1<<31)
5385#define PIPECONF_DISABLE 0
5386#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07005387#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03005388#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00005389#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01005390#define PIPECONF_SINGLE_WIDE 0
5391#define PIPECONF_PIPE_UNLOCKED 0
5392#define PIPECONF_PIPE_LOCKED (1<<25)
5393#define PIPECONF_PALETTE 0
5394#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07005395#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01005396#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005397#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01005398/* Note that pre-gen3 does not support interlaced display directly. Panel
5399 * fitting must be disabled on pre-ilk for interlaced. */
5400#define PIPECONF_PROGRESSIVE (0 << 21)
5401#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5402#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5403#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5404#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5405/* Ironlake and later have a complete new set of values for interlaced. PFIT
5406 * means panel fitter required, PF means progressive fetch, DBL means power
5407 * saving pixel doubling. */
5408#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5409#define PIPECONF_INTERLACED_ILK (3 << 21)
5410#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5411#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005412#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305413#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07005414#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05305415#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005416#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005417#define PIPECONF_BPC_MASK (0x7 << 5)
5418#define PIPECONF_8BPC (0<<5)
5419#define PIPECONF_10BPC (1<<5)
5420#define PIPECONF_6BPC (2<<5)
5421#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07005422#define PIPECONF_DITHER_EN (1<<4)
5423#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5424#define PIPECONF_DITHER_TYPE_SP (0<<2)
5425#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
5426#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
5427#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005428#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07005429#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02005430#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07005431#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
5432#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005433#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07005434#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005435#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07005436#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
5437#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
5438#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
5439#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02005440#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07005441#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
5442#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
5443#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02005444#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005445#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07005446#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
5447#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005448#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07005449#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005450#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07005451#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02005452#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
5453#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07005454#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
5455#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005456#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07005457#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02005458#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07005459#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
5460#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
5461#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
5462#define PIPE_DPST_EVENT_STATUS (1UL<<7)
Imre Deak10c59c52014-02-10 18:42:48 +02005463#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005464#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07005465#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
5466#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02005467#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005468#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07005469#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
5470#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005471#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07005472#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03005473#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07005474#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
5475
Imre Deak755e9012014-02-10 18:42:47 +02005476#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5477#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5478
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03005479#define PIPE_A_OFFSET 0x70000
5480#define PIPE_B_OFFSET 0x71000
5481#define PIPE_C_OFFSET 0x72000
5482#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005483/*
5484 * There's actually no pipe EDP. Some pipe registers have
5485 * simply shifted from the pipe to the transcoder, while
5486 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5487 * to access such registers in transcoder EDP.
5488 */
5489#define PIPE_EDP_OFFSET 0x7f000
5490
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005491#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005492 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5493 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005494
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005495#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5496#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5497#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5498#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5499#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01005500
Paulo Zanoni756f85c2013-11-02 21:07:38 -07005501#define _PIPE_MISC_A 0x70030
5502#define _PIPE_MISC_B 0x71030
Shashank Sharmab22ca992017-07-24 19:19:32 +05305503#define PIPEMISC_YUV420_ENABLE (1<<27)
5504#define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26)
5505#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07005506#define PIPEMISC_DITHER_BPC_MASK (7<<5)
5507#define PIPEMISC_DITHER_8_BPC (0<<5)
5508#define PIPEMISC_DITHER_10_BPC (1<<5)
5509#define PIPEMISC_DITHER_6_BPC (2<<5)
5510#define PIPEMISC_DITHER_12_BPC (3<<5)
5511#define PIPEMISC_DITHER_ENABLE (1<<4)
5512#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
5513#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005514#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07005515
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005516#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07005517#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005518#define PIPEB_HLINE_INT_EN (1<<28)
5519#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02005520#define SPRITED_FLIP_DONE_INT_EN (1<<26)
5521#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
5522#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03005523#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07005524#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005525#define PIPEA_HLINE_INT_EN (1<<20)
5526#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02005527#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
5528#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005529#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03005530#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
5531#define PIPEC_HLINE_INT_EN (1<<12)
5532#define PIPEC_VBLANK_INT_EN (1<<11)
5533#define SPRITEF_FLIPDONE_INT_EN (1<<10)
5534#define SPRITEE_FLIPDONE_INT_EN (1<<9)
5535#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005536
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005537#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03005538#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
5539#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
5540#define PLANEC_INVALID_GTT_INT_EN (1<<25)
5541#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005542#define CURSORB_INVALID_GTT_INT_EN (1<<23)
5543#define CURSORA_INVALID_GTT_INT_EN (1<<22)
5544#define SPRITED_INVALID_GTT_INT_EN (1<<21)
5545#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
5546#define PLANEB_INVALID_GTT_INT_EN (1<<19)
5547#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
5548#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
5549#define PLANEA_INVALID_GTT_INT_EN (1<<16)
5550#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03005551#define DPINVGTT_EN_MASK_CHV 0xfff0000
5552#define SPRITEF_INVALID_GTT_STATUS (1<<11)
5553#define SPRITEE_INVALID_GTT_STATUS (1<<10)
5554#define PLANEC_INVALID_GTT_STATUS (1<<9)
5555#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005556#define CURSORB_INVALID_GTT_STATUS (1<<7)
5557#define CURSORA_INVALID_GTT_STATUS (1<<6)
5558#define SPRITED_INVALID_GTT_STATUS (1<<5)
5559#define SPRITEC_INVALID_GTT_STATUS (1<<4)
5560#define PLANEB_INVALID_GTT_STATUS (1<<3)
5561#define SPRITEB_INVALID_GTT_STATUS (1<<2)
5562#define SPRITEA_INVALID_GTT_STATUS (1<<1)
5563#define PLANEA_INVALID_GTT_STATUS (1<<0)
5564#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03005565#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07005566
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005567#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
Jesse Barnes585fb112008-07-29 11:54:06 -07005568#define DSPARB_CSTART_MASK (0x7f << 7)
5569#define DSPARB_CSTART_SHIFT 7
5570#define DSPARB_BSTART_MASK (0x7f)
5571#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08005572#define DSPARB_BEND_SHIFT 9 /* on 855 */
5573#define DSPARB_AEND_SHIFT 0
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03005574#define DSPARB_SPRITEA_SHIFT_VLV 0
5575#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5576#define DSPARB_SPRITEB_SHIFT_VLV 8
5577#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5578#define DSPARB_SPRITEC_SHIFT_VLV 16
5579#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5580#define DSPARB_SPRITED_SHIFT_VLV 24
5581#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005582#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03005583#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5584#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5585#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5586#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5587#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5588#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5589#define DSPARB_SPRITED_HI_SHIFT_VLV 12
5590#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5591#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5592#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5593#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5594#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005595#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03005596#define DSPARB_SPRITEE_SHIFT_VLV 0
5597#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5598#define DSPARB_SPRITEF_SHIFT_VLV 8
5599#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
Ville Syrjäläb5004722015-03-05 21:19:47 +02005600
Ville Syrjälä0a560672014-06-11 16:51:18 +03005601/* pnv/gen4/g4x/vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005602#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005603#define DSPFW_SR_SHIFT 23
5604#define DSPFW_SR_MASK (0x1ff<<23)
5605#define DSPFW_CURSORB_SHIFT 16
5606#define DSPFW_CURSORB_MASK (0x3f<<16)
5607#define DSPFW_PLANEB_SHIFT 8
5608#define DSPFW_PLANEB_MASK (0x7f<<8)
5609#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
5610#define DSPFW_PLANEA_SHIFT 0
5611#define DSPFW_PLANEA_MASK (0x7f<<0)
5612#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005613#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005614#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
5615#define DSPFW_FBC_SR_SHIFT 28
5616#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
5617#define DSPFW_FBC_HPLL_SR_SHIFT 24
5618#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
5619#define DSPFW_SPRITEB_SHIFT (16)
5620#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
5621#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
5622#define DSPFW_CURSORA_SHIFT 8
5623#define DSPFW_CURSORA_MASK (0x3f<<8)
Ville Syrjäläf4998962015-03-10 17:02:21 +02005624#define DSPFW_PLANEC_OLD_SHIFT 0
5625#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
Ville Syrjälä0a560672014-06-11 16:51:18 +03005626#define DSPFW_SPRITEA_SHIFT 0
5627#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
5628#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005629#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005630#define DSPFW_HPLL_SR_EN (1<<31)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005631#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005632#define DSPFW_CURSOR_SR_SHIFT 24
Zhao Yakuid4294342010-03-22 22:45:36 +08005633#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
5634#define DSPFW_HPLL_CURSOR_SHIFT 16
5635#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005636#define DSPFW_HPLL_SR_SHIFT 0
5637#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
5638
5639/* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005640#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005641#define DSPFW_SPRITEB_WM1_SHIFT 16
5642#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
5643#define DSPFW_CURSORA_WM1_SHIFT 8
5644#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
5645#define DSPFW_SPRITEA_WM1_SHIFT 0
5646#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005647#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005648#define DSPFW_PLANEB_WM1_SHIFT 24
5649#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
5650#define DSPFW_PLANEA_WM1_SHIFT 16
5651#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
5652#define DSPFW_CURSORB_WM1_SHIFT 8
5653#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
5654#define DSPFW_CURSOR_SR_WM1_SHIFT 0
5655#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005656#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005657#define DSPFW_SR_WM1_SHIFT 0
5658#define DSPFW_SR_WM1_MASK (0x1ff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005659#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5660#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03005661#define DSPFW_SPRITED_WM1_SHIFT 24
5662#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
5663#define DSPFW_SPRITED_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02005664#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005665#define DSPFW_SPRITEC_WM1_SHIFT 8
5666#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
5667#define DSPFW_SPRITEC_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02005668#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005669#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005670#define DSPFW_SPRITEF_WM1_SHIFT 24
5671#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
5672#define DSPFW_SPRITEF_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02005673#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005674#define DSPFW_SPRITEE_WM1_SHIFT 8
5675#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
5676#define DSPFW_SPRITEE_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02005677#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005678#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03005679#define DSPFW_PLANEC_WM1_SHIFT 24
5680#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
5681#define DSPFW_PLANEC_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02005682#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005683#define DSPFW_CURSORC_WM1_SHIFT 8
5684#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
5685#define DSPFW_CURSORC_SHIFT 0
5686#define DSPFW_CURSORC_MASK (0x3f<<0)
5687
5688/* vlv/chv high order bits */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005689#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005690#define DSPFW_SR_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02005691#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03005692#define DSPFW_SPRITEF_HI_SHIFT 23
5693#define DSPFW_SPRITEF_HI_MASK (1<<23)
5694#define DSPFW_SPRITEE_HI_SHIFT 22
5695#define DSPFW_SPRITEE_HI_MASK (1<<22)
5696#define DSPFW_PLANEC_HI_SHIFT 21
5697#define DSPFW_PLANEC_HI_MASK (1<<21)
5698#define DSPFW_SPRITED_HI_SHIFT 20
5699#define DSPFW_SPRITED_HI_MASK (1<<20)
5700#define DSPFW_SPRITEC_HI_SHIFT 16
5701#define DSPFW_SPRITEC_HI_MASK (1<<16)
5702#define DSPFW_PLANEB_HI_SHIFT 12
5703#define DSPFW_PLANEB_HI_MASK (1<<12)
5704#define DSPFW_SPRITEB_HI_SHIFT 8
5705#define DSPFW_SPRITEB_HI_MASK (1<<8)
5706#define DSPFW_SPRITEA_HI_SHIFT 4
5707#define DSPFW_SPRITEA_HI_MASK (1<<4)
5708#define DSPFW_PLANEA_HI_SHIFT 0
5709#define DSPFW_PLANEA_HI_MASK (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005710#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
Ville Syrjälä0a560672014-06-11 16:51:18 +03005711#define DSPFW_SR_WM1_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02005712#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03005713#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5714#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
5715#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5716#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
5717#define DSPFW_PLANEC_WM1_HI_SHIFT 21
5718#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
5719#define DSPFW_SPRITED_WM1_HI_SHIFT 20
5720#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
5721#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5722#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
5723#define DSPFW_PLANEB_WM1_HI_SHIFT 12
5724#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
5725#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5726#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
5727#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5728#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
5729#define DSPFW_PLANEA_WM1_HI_SHIFT 0
5730#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08005731
Gajanan Bhat12a3c052012-03-28 13:39:30 -07005732/* drain latency register values*/
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005733#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03005734#define DDL_CURSOR_SHIFT 24
Gajanan Bhat01e184c2014-08-07 17:03:30 +05305735#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03005736#define DDL_PLANE_SHIFT 0
Ville Syrjälä341c5262015-03-05 21:19:44 +02005737#define DDL_PRECISION_HIGH (1<<7)
5738#define DDL_PRECISION_LOW (0<<7)
Gajanan Bhat0948c262014-08-07 01:58:24 +05305739#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07005740
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005741#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
Ville Syrjäläc6beb132015-03-05 21:19:48 +02005742#define CBR_PND_DEADLINE_DISABLE (1<<31)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03005743#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
Ville Syrjäläc6beb132015-03-05 21:19:48 +02005744
Ville Syrjäläc2317752016-03-15 16:39:56 +02005745#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
Ville Syrjälädfa311f2017-09-13 17:08:54 +03005746#define CBR_DPLLBMD_PIPE(pipe) (1<<(7+(pipe)*11)) /* pipes B and C */
Ville Syrjäläc2317752016-03-15 16:39:56 +02005747
Shaohua Li7662c8b2009-06-26 11:23:55 +08005748/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09005749#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08005750#define I915_FIFO_LINE_SIZE 64
5751#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09005752
Jesse Barnesceb04242012-03-28 13:39:22 -07005753#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09005754#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08005755#define I965_FIFO_SIZE 512
5756#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08005757#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07005758#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08005759#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09005760
Jesse Barnesceb04242012-03-28 13:39:22 -07005761#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09005762#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08005763#define I915_MAX_WM 0x3f
5764
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005765#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5766#define PINEVIEW_FIFO_LINE_SIZE 64
5767#define PINEVIEW_MAX_WM 0x1ff
5768#define PINEVIEW_DFT_WM 0x3f
5769#define PINEVIEW_DFT_HPLLOFF_WM 0
5770#define PINEVIEW_GUARD_WM 10
5771#define PINEVIEW_CURSOR_FIFO 64
5772#define PINEVIEW_CURSOR_MAX_WM 0x3f
5773#define PINEVIEW_CURSOR_DFT_WM 0
5774#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08005775
Jesse Barnesceb04242012-03-28 13:39:22 -07005776#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08005777#define I965_CURSOR_FIFO 64
5778#define I965_CURSOR_MAX_WM 32
5779#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005780
Pradeep Bhatfae12672014-11-04 17:06:39 +00005781/* Watermark register definitions for SKL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02005782#define _CUR_WM_A_0 0x70140
5783#define _CUR_WM_B_0 0x71140
5784#define _PLANE_WM_1_A_0 0x70240
5785#define _PLANE_WM_1_B_0 0x71240
5786#define _PLANE_WM_2_A_0 0x70340
5787#define _PLANE_WM_2_B_0 0x71340
5788#define _PLANE_WM_TRANS_1_A_0 0x70268
5789#define _PLANE_WM_TRANS_1_B_0 0x71268
5790#define _PLANE_WM_TRANS_2_A_0 0x70368
5791#define _PLANE_WM_TRANS_2_B_0 0x71368
5792#define _CUR_WM_TRANS_A_0 0x70168
5793#define _CUR_WM_TRANS_B_0 0x71168
Pradeep Bhatfae12672014-11-04 17:06:39 +00005794#define PLANE_WM_EN (1 << 31)
5795#define PLANE_WM_LINES_SHIFT 14
5796#define PLANE_WM_LINES_MASK 0x1f
5797#define PLANE_WM_BLOCKS_MASK 0x3ff
5798
Ville Syrjälä086f8e82015-11-04 23:20:01 +02005799#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005800#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5801#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00005802
Ville Syrjälä086f8e82015-11-04 23:20:01 +02005803#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5804#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00005805#define _PLANE_WM_BASE(pipe, plane) \
5806 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5807#define PLANE_WM(pipe, plane, level) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005808 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
Pradeep Bhatfae12672014-11-04 17:06:39 +00005809#define _PLANE_WM_TRANS_1(pipe) \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02005810 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00005811#define _PLANE_WM_TRANS_2(pipe) \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02005812 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00005813#define PLANE_WM_TRANS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005814 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
Pradeep Bhatfae12672014-11-04 17:06:39 +00005815
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005816/* define the Watermark register on Ironlake */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005817#define WM0_PIPEA_ILK _MMIO(0x45100)
Ville Syrjälä1996d622013-10-09 19:18:07 +03005818#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005819#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03005820#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005821#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03005822#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005823
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005824#define WM0_PIPEB_ILK _MMIO(0x45104)
5825#define WM0_PIPEC_IVB _MMIO(0x45200)
5826#define WM1_LP_ILK _MMIO(0x45108)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005827#define WM1_LP_SR_EN (1<<31)
5828#define WM1_LP_LATENCY_SHIFT 24
5829#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01005830#define WM1_LP_FBC_MASK (0xf<<20)
5831#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07005832#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03005833#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005834#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03005835#define WM1_LP_CURSOR_MASK (0xff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005836#define WM2_LP_ILK _MMIO(0x4510c)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07005837#define WM2_LP_EN (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005838#define WM3_LP_ILK _MMIO(0x45110)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07005839#define WM3_LP_EN (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005840#define WM1S_LP_ILK _MMIO(0x45120)
5841#define WM2S_LP_IVB _MMIO(0x45124)
5842#define WM3S_LP_IVB _MMIO(0x45128)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07005843#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005844
Paulo Zanonicca32e92013-05-31 11:45:06 -03005845#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5846 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5847 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5848
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005849/* Memory latency timer register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005850#define MLTR_ILK _MMIO(0x11222)
Jesse Barnesb79d4992010-12-21 13:10:23 -08005851#define MLTR_WM1_SHIFT 0
5852#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005853/* the unit of memory self-refresh latency time is 0.5us */
5854#define ILK_SRLT_MASK 0x3f
5855
Yuanhan Liu13982612010-12-15 15:42:31 +08005856
5857/* the address where we get all kinds of latency value */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005858#define SSKPD _MMIO(0x5d10)
Yuanhan Liu13982612010-12-15 15:42:31 +08005859#define SSKPD_WM_MASK 0x3f
5860#define SSKPD_WM0_SHIFT 0
5861#define SSKPD_WM1_SHIFT 8
5862#define SSKPD_WM2_SHIFT 16
5863#define SSKPD_WM3_SHIFT 24
5864
Jesse Barnes585fb112008-07-29 11:54:06 -07005865/*
5866 * The two pipe frame counter registers are not synchronized, so
5867 * reading a stable value is somewhat tricky. The following code
5868 * should work:
5869 *
5870 * do {
5871 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5872 * PIPE_FRAME_HIGH_SHIFT;
5873 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
5874 * PIPE_FRAME_LOW_SHIFT);
5875 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5876 * PIPE_FRAME_HIGH_SHIFT);
5877 * } while (high1 != high2);
5878 * frame = (high1 << 8) | low1;
5879 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03005880#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07005881#define PIPE_FRAME_HIGH_MASK 0x0000ffff
5882#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03005883#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07005884#define PIPE_FRAME_LOW_MASK 0xff000000
5885#define PIPE_FRAME_LOW_SHIFT 24
5886#define PIPE_PIXEL_MASK 0x00ffffff
5887#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08005888/* GM45+ just has to be different */
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03005889#define _PIPEA_FRMCOUNT_G4X 0x70040
5890#define _PIPEA_FLIPCOUNT_G4X 0x70044
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005891#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5892#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
Jesse Barnes585fb112008-07-29 11:54:06 -07005893
5894/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005895#define _CURACNTR 0x70080
Jesse Barnes14b603912009-05-20 16:47:08 -04005896/* Old style CUR*CNTR flags (desktop 8xx) */
5897#define CURSOR_ENABLE 0x80000000
5898#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03005899#define CURSOR_STRIDE_SHIFT 28
5900#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005901#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b603912009-05-20 16:47:08 -04005902#define CURSOR_FORMAT_SHIFT 24
5903#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5904#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5905#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5906#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5907#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5908#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5909/* New style CUR*CNTR flags */
5910#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07005911#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05305912#define CURSOR_MODE_128_32B_AX 0x02
5913#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07005914#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05305915#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5916#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07005917#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Ville Syrjäläd509e282017-03-27 21:55:32 +03005918#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07005919#define MCURSOR_GAMMA_ENABLE (1 << 26)
Ville Syrjälä4398ad42014-10-23 07:41:34 -07005920#define CURSOR_ROTATE_180 (1<<15)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03005921#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005922#define _CURABASE 0x70084
5923#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07005924#define CURSOR_POS_MASK 0x007FF
5925#define CURSOR_POS_SIGN 0x8000
5926#define CURSOR_X_SHIFT 0
5927#define CURSOR_Y_SHIFT 16
Ville Syrjälä024faac2017-03-27 21:55:42 +03005928#define CURSIZE _MMIO(0x700a0) /* 845/865 */
5929#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
5930#define CUR_FBC_CTL_EN (1 << 31)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005931#define _CURBCNTR 0x700c0
5932#define _CURBBASE 0x700c4
5933#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07005934
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005935#define _CURBCNTR_IVB 0x71080
5936#define _CURBBASE_IVB 0x71084
5937#define _CURBPOS_IVB 0x71088
5938
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005939#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005940 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
5941 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00005942
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005943#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
5944#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
5945#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
Ville Syrjälä024faac2017-03-27 21:55:42 +03005946#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005947
5948#define CURSOR_A_OFFSET 0x70080
5949#define CURSOR_B_OFFSET 0x700c0
5950#define CHV_CURSOR_C_OFFSET 0x700e0
5951#define IVB_CURSOR_B_OFFSET 0x71080
5952#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005953
Jesse Barnes585fb112008-07-29 11:54:06 -07005954/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005955#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07005956#define DISPLAY_PLANE_ENABLE (1<<31)
5957#define DISPLAY_PLANE_DISABLE 0
5958#define DISPPLANE_GAMMA_ENABLE (1<<30)
5959#define DISPPLANE_GAMMA_DISABLE 0
5960#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02005961#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07005962#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02005963#define DISPPLANE_BGRA555 (0x3<<26)
5964#define DISPPLANE_BGRX555 (0x4<<26)
5965#define DISPPLANE_BGRX565 (0x5<<26)
5966#define DISPPLANE_BGRX888 (0x6<<26)
5967#define DISPPLANE_BGRA888 (0x7<<26)
5968#define DISPPLANE_RGBX101010 (0x8<<26)
5969#define DISPPLANE_RGBA101010 (0x9<<26)
5970#define DISPPLANE_BGRX101010 (0xa<<26)
5971#define DISPPLANE_RGBX161616 (0xc<<26)
5972#define DISPPLANE_RGBX888 (0xe<<26)
5973#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07005974#define DISPPLANE_STEREO_ENABLE (1<<25)
5975#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005976#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08005977#define DISPPLANE_SEL_PIPE_SHIFT 24
5978#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Ville Syrjäläd509e282017-03-27 21:55:32 +03005979#define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07005980#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
5981#define DISPPLANE_SRC_KEY_DISABLE 0
5982#define DISPPLANE_LINE_DOUBLE (1<<20)
5983#define DISPPLANE_NO_LINE_DOUBLE 0
5984#define DISPPLANE_STEREO_POLARITY_FIRST 0
5985#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005986#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
5987#define DISPPLANE_ROTATE_180 (1<<15)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005988#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07005989#define DISPPLANE_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005990#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005991#define _DSPAADDR 0x70184
5992#define _DSPASTRIDE 0x70188
5993#define _DSPAPOS 0x7018C /* reserved */
5994#define _DSPASIZE 0x70190
5995#define _DSPASURF 0x7019C /* 965+ only */
5996#define _DSPATILEOFF 0x701A4 /* 965+ only */
5997#define _DSPAOFFSET 0x701A4 /* HSW */
5998#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07005999
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006000#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6001#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6002#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6003#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6004#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6005#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6006#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6007#define DSPLINOFF(plane) DSPADDR(plane)
6008#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6009#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01006010
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006011/* CHV pipe B blender and primary plane */
6012#define _CHV_BLEND_A 0x60a00
6013#define CHV_BLEND_LEGACY (0<<30)
6014#define CHV_BLEND_ANDROID (1<<30)
6015#define CHV_BLEND_MPO (2<<30)
6016#define CHV_BLEND_MASK (3<<30)
6017#define _CHV_CANVAS_A 0x60a04
6018#define _PRIMPOS_A 0x60a08
6019#define _PRIMSIZE_A 0x60a0c
6020#define _PRIMCNSTALPHA_A 0x60a10
6021#define PRIM_CONST_ALPHA_ENABLE (1<<31)
6022
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006023#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6024#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6025#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6026#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6027#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006028
Armin Reese446f2542012-03-30 16:20:16 -07006029/* Display/Sprite base address macros */
6030#define DISP_BASEADDR_MASK (0xfffff000)
6031#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
6032#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07006033
Ville Syrjälä85fa7922015-09-18 20:03:43 +03006034/*
6035 * VBIOS flags
6036 * gen2:
6037 * [00:06] alm,mgm
6038 * [10:16] all
6039 * [30:32] alm,mgm
6040 * gen3+:
6041 * [00:0f] all
6042 * [10:1f] all
6043 * [30:32] all
6044 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006045#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6046#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6047#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6048#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07006049
6050/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006051#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6052#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6053#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03006054#define _PIPEBFRAMEHIGH 0x71040
6055#define _PIPEBFRAMEPIXEL 0x71044
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03006056#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6057#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08006058
Jesse Barnes585fb112008-07-29 11:54:06 -07006059
6060/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006061#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07006062#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
6063#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6064#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6065#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006066#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6067#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6068#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6069#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6070#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6071#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6072#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6073#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07006074
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006075/* Sprite A control */
6076#define _DVSACNTR 0x72180
6077#define DVS_ENABLE (1<<31)
6078#define DVS_GAMMA_ENABLE (1<<30)
6079#define DVS_PIXFORMAT_MASK (3<<25)
6080#define DVS_FORMAT_YUV422 (0<<25)
6081#define DVS_FORMAT_RGBX101010 (1<<25)
6082#define DVS_FORMAT_RGBX888 (2<<25)
6083#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006084#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006085#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08006086#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006087#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
6088#define DVS_YUV_ORDER_YUYV (0<<16)
6089#define DVS_YUV_ORDER_UYVY (1<<16)
6090#define DVS_YUV_ORDER_YVYU (2<<16)
6091#define DVS_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05306092#define DVS_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006093#define DVS_DEST_KEY (1<<2)
6094#define DVS_TRICKLE_FEED_DISABLE (1<<14)
6095#define DVS_TILED (1<<10)
6096#define _DVSALINOFF 0x72184
6097#define _DVSASTRIDE 0x72188
6098#define _DVSAPOS 0x7218c
6099#define _DVSASIZE 0x72190
6100#define _DVSAKEYVAL 0x72194
6101#define _DVSAKEYMSK 0x72198
6102#define _DVSASURF 0x7219c
6103#define _DVSAKEYMAXVAL 0x721a0
6104#define _DVSATILEOFF 0x721a4
6105#define _DVSASURFLIVE 0x721ac
6106#define _DVSASCALE 0x72204
6107#define DVS_SCALE_ENABLE (1<<31)
6108#define DVS_FILTER_MASK (3<<29)
6109#define DVS_FILTER_MEDIUM (0<<29)
6110#define DVS_FILTER_ENHANCING (1<<29)
6111#define DVS_FILTER_SOFTENING (2<<29)
6112#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6113#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
6114#define _DVSAGAMC 0x72300
6115
6116#define _DVSBCNTR 0x73180
6117#define _DVSBLINOFF 0x73184
6118#define _DVSBSTRIDE 0x73188
6119#define _DVSBPOS 0x7318c
6120#define _DVSBSIZE 0x73190
6121#define _DVSBKEYVAL 0x73194
6122#define _DVSBKEYMSK 0x73198
6123#define _DVSBSURF 0x7319c
6124#define _DVSBKEYMAXVAL 0x731a0
6125#define _DVSBTILEOFF 0x731a4
6126#define _DVSBSURFLIVE 0x731ac
6127#define _DVSBSCALE 0x73204
6128#define _DVSBGAMC 0x73300
6129
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006130#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6131#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6132#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6133#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6134#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6135#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6136#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6137#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6138#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6139#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6140#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6141#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006142
6143#define _SPRA_CTL 0x70280
6144#define SPRITE_ENABLE (1<<31)
6145#define SPRITE_GAMMA_ENABLE (1<<30)
6146#define SPRITE_PIXFORMAT_MASK (7<<25)
6147#define SPRITE_FORMAT_YUV422 (0<<25)
6148#define SPRITE_FORMAT_RGBX101010 (1<<25)
6149#define SPRITE_FORMAT_RGBX888 (2<<25)
6150#define SPRITE_FORMAT_RGBX161616 (3<<25)
6151#define SPRITE_FORMAT_YUV444 (4<<25)
6152#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006153#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006154#define SPRITE_SOURCE_KEY (1<<22)
6155#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
6156#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
6157#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
6158#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
6159#define SPRITE_YUV_ORDER_YUYV (0<<16)
6160#define SPRITE_YUV_ORDER_UYVY (1<<16)
6161#define SPRITE_YUV_ORDER_YVYU (2<<16)
6162#define SPRITE_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05306163#define SPRITE_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006164#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
6165#define SPRITE_INT_GAMMA_ENABLE (1<<13)
6166#define SPRITE_TILED (1<<10)
6167#define SPRITE_DEST_KEY (1<<2)
6168#define _SPRA_LINOFF 0x70284
6169#define _SPRA_STRIDE 0x70288
6170#define _SPRA_POS 0x7028c
6171#define _SPRA_SIZE 0x70290
6172#define _SPRA_KEYVAL 0x70294
6173#define _SPRA_KEYMSK 0x70298
6174#define _SPRA_SURF 0x7029c
6175#define _SPRA_KEYMAX 0x702a0
6176#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01006177#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02006178#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006179#define _SPRA_SCALE 0x70304
6180#define SPRITE_SCALE_ENABLE (1<<31)
6181#define SPRITE_FILTER_MASK (3<<29)
6182#define SPRITE_FILTER_MEDIUM (0<<29)
6183#define SPRITE_FILTER_ENHANCING (1<<29)
6184#define SPRITE_FILTER_SOFTENING (2<<29)
6185#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6186#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
6187#define _SPRA_GAMC 0x70400
6188
6189#define _SPRB_CTL 0x71280
6190#define _SPRB_LINOFF 0x71284
6191#define _SPRB_STRIDE 0x71288
6192#define _SPRB_POS 0x7128c
6193#define _SPRB_SIZE 0x71290
6194#define _SPRB_KEYVAL 0x71294
6195#define _SPRB_KEYMSK 0x71298
6196#define _SPRB_SURF 0x7129c
6197#define _SPRB_KEYMAX 0x712a0
6198#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01006199#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02006200#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006201#define _SPRB_SCALE 0x71304
6202#define _SPRB_GAMC 0x71400
6203
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006204#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6205#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6206#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6207#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6208#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6209#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6210#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6211#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6212#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6213#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6214#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6215#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6216#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6217#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08006218
Ville Syrjälä921c3b62013-06-25 14:16:35 +03006219#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006220#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08006221#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006222#define SP_PIXFORMAT_MASK (0xf<<26)
6223#define SP_FORMAT_YUV422 (0<<26)
6224#define SP_FORMAT_BGR565 (5<<26)
6225#define SP_FORMAT_BGRX8888 (6<<26)
6226#define SP_FORMAT_BGRA8888 (7<<26)
6227#define SP_FORMAT_RGBX1010102 (8<<26)
6228#define SP_FORMAT_RGBA1010102 (9<<26)
6229#define SP_FORMAT_RGBX8888 (0xe<<26)
6230#define SP_FORMAT_RGBA8888 (0xf<<26)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006231#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006232#define SP_SOURCE_KEY (1<<22)
6233#define SP_YUV_BYTE_ORDER_MASK (3<<16)
6234#define SP_YUV_ORDER_YUYV (0<<16)
6235#define SP_YUV_ORDER_UYVY (1<<16)
6236#define SP_YUV_ORDER_YVYU (2<<16)
6237#define SP_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05306238#define SP_ROTATE_180 (1<<15)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006239#define SP_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006240#define SP_MIRROR (1<<8) /* CHV pipe B */
Ville Syrjälä921c3b62013-06-25 14:16:35 +03006241#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6242#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6243#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6244#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6245#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6246#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6247#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6248#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6249#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6250#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006251#define SP_CONST_ALPHA_ENABLE (1<<31)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03006252#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006253
Ville Syrjälä921c3b62013-06-25 14:16:35 +03006254#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6255#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6256#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6257#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6258#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6259#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6260#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6261#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6262#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6263#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6264#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6265#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006266
Ville Syrjälä83c04a62016-11-22 18:02:00 +02006267#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6268 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6269
6270#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6271#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6272#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6273#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6274#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6275#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6276#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6277#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6278#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6279#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6280#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6281#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07006282
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03006283/*
6284 * CHV pipe B sprite CSC
6285 *
6286 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6287 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6288 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6289 */
Ville Syrjälä83c04a62016-11-22 18:02:00 +02006290#define _MMIO_CHV_SPCSC(plane_id, reg) \
6291 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6292
6293#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6294#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6295#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03006296#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6297#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6298
Ville Syrjälä83c04a62016-11-22 18:02:00 +02006299#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6300#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6301#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6302#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6303#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03006304#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6305#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6306
Ville Syrjälä83c04a62016-11-22 18:02:00 +02006307#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6308#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6309#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03006310#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6311#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6312
Ville Syrjälä83c04a62016-11-22 18:02:00 +02006313#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6314#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6315#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03006316#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6317#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6318
Damien Lespiau70d21f02013-07-03 21:06:04 +01006319/* Skylake plane registers */
6320
6321#define _PLANE_CTL_1_A 0x70180
6322#define _PLANE_CTL_2_A 0x70280
6323#define _PLANE_CTL_3_A 0x70380
6324#define PLANE_CTL_ENABLE (1 << 31)
James Ausmus4036c782017-11-13 10:11:28 -08006325#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
Damien Lespiau70d21f02013-07-03 21:06:04 +01006326#define PLANE_CTL_FORMAT_MASK (0xf << 24)
6327#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
6328#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
6329#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
6330#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
6331#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
6332#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
6333#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
6334#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
James Ausmus4036c782017-11-13 10:11:28 -08006335#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006336#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6337#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
6338#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
Damien Lespiau70d21f02013-07-03 21:06:04 +01006339#define PLANE_CTL_ORDER_BGRX (0 << 20)
6340#define PLANE_CTL_ORDER_RGBX (1 << 20)
6341#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6342#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
6343#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
6344#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
6345#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
6346#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
6347#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
James Ausmus4036c782017-11-13 10:11:28 -08006348#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
Damien Lespiau70d21f02013-07-03 21:06:04 +01006349#define PLANE_CTL_TILED_MASK (0x7 << 10)
6350#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
6351#define PLANE_CTL_TILED_X ( 1 << 10)
6352#define PLANE_CTL_TILED_Y ( 4 << 10)
6353#define PLANE_CTL_TILED_YF ( 5 << 10)
Joonas Lahtinen5f8e3f52017-12-15 13:38:00 -08006354#define PLANE_CTL_FLIP_HORIZONTAL ( 1 << 8)
James Ausmus4036c782017-11-13 10:11:28 -08006355#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
Damien Lespiau70d21f02013-07-03 21:06:04 +01006356#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
6357#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
6358#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
Sonika Jindal1447dde2014-10-04 10:53:31 +01006359#define PLANE_CTL_ROTATE_MASK 0x3
6360#define PLANE_CTL_ROTATE_0 0x0
Sonika Jindal3b7a5112015-04-10 14:37:29 +05306361#define PLANE_CTL_ROTATE_90 0x1
Sonika Jindal1447dde2014-10-04 10:53:31 +01006362#define PLANE_CTL_ROTATE_180 0x2
Sonika Jindal3b7a5112015-04-10 14:37:29 +05306363#define PLANE_CTL_ROTATE_270 0x3
Damien Lespiau70d21f02013-07-03 21:06:04 +01006364#define _PLANE_STRIDE_1_A 0x70188
6365#define _PLANE_STRIDE_2_A 0x70288
6366#define _PLANE_STRIDE_3_A 0x70388
6367#define _PLANE_POS_1_A 0x7018c
6368#define _PLANE_POS_2_A 0x7028c
6369#define _PLANE_POS_3_A 0x7038c
6370#define _PLANE_SIZE_1_A 0x70190
6371#define _PLANE_SIZE_2_A 0x70290
6372#define _PLANE_SIZE_3_A 0x70390
6373#define _PLANE_SURF_1_A 0x7019c
6374#define _PLANE_SURF_2_A 0x7029c
6375#define _PLANE_SURF_3_A 0x7039c
6376#define _PLANE_OFFSET_1_A 0x701a4
6377#define _PLANE_OFFSET_2_A 0x702a4
6378#define _PLANE_OFFSET_3_A 0x703a4
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006379#define _PLANE_KEYVAL_1_A 0x70194
6380#define _PLANE_KEYVAL_2_A 0x70294
6381#define _PLANE_KEYMSK_1_A 0x70198
6382#define _PLANE_KEYMSK_2_A 0x70298
6383#define _PLANE_KEYMAX_1_A 0x701a0
6384#define _PLANE_KEYMAX_2_A 0x702a0
Ville Syrjälä2e2adb02017-08-01 09:58:13 -07006385#define _PLANE_AUX_DIST_1_A 0x701c0
6386#define _PLANE_AUX_DIST_2_A 0x702c0
6387#define _PLANE_AUX_OFFSET_1_A 0x701c4
6388#define _PLANE_AUX_OFFSET_2_A 0x702c4
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02006389#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6390#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6391#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6392#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
6393#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
6394#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
James Ausmus4036c782017-11-13 10:11:28 -08006395#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6396#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6397#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6398#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
Damien Lespiau8211bd52014-11-04 17:06:44 +00006399#define _PLANE_BUF_CFG_1_A 0x7027c
6400#define _PLANE_BUF_CFG_2_A 0x7037c
Chandra Konduru2cd601c2015-04-27 15:47:37 -07006401#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6402#define _PLANE_NV12_BUF_CFG_2_A 0x70378
Damien Lespiau70d21f02013-07-03 21:06:04 +01006403
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02006404
Damien Lespiau70d21f02013-07-03 21:06:04 +01006405#define _PLANE_CTL_1_B 0x71180
6406#define _PLANE_CTL_2_B 0x71280
6407#define _PLANE_CTL_3_B 0x71380
6408#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6409#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6410#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6411#define PLANE_CTL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006412 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006413
6414#define _PLANE_STRIDE_1_B 0x71188
6415#define _PLANE_STRIDE_2_B 0x71288
6416#define _PLANE_STRIDE_3_B 0x71388
6417#define _PLANE_STRIDE_1(pipe) \
6418 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6419#define _PLANE_STRIDE_2(pipe) \
6420 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6421#define _PLANE_STRIDE_3(pipe) \
6422 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6423#define PLANE_STRIDE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006424 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006425
6426#define _PLANE_POS_1_B 0x7118c
6427#define _PLANE_POS_2_B 0x7128c
6428#define _PLANE_POS_3_B 0x7138c
6429#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6430#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6431#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6432#define PLANE_POS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006433 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006434
6435#define _PLANE_SIZE_1_B 0x71190
6436#define _PLANE_SIZE_2_B 0x71290
6437#define _PLANE_SIZE_3_B 0x71390
6438#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6439#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6440#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6441#define PLANE_SIZE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006442 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006443
6444#define _PLANE_SURF_1_B 0x7119c
6445#define _PLANE_SURF_2_B 0x7129c
6446#define _PLANE_SURF_3_B 0x7139c
6447#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6448#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6449#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6450#define PLANE_SURF(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006451 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006452
6453#define _PLANE_OFFSET_1_B 0x711a4
6454#define _PLANE_OFFSET_2_B 0x712a4
6455#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6456#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6457#define PLANE_OFFSET(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006458 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01006459
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006460#define _PLANE_KEYVAL_1_B 0x71194
6461#define _PLANE_KEYVAL_2_B 0x71294
6462#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6463#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6464#define PLANE_KEYVAL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006465 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006466
6467#define _PLANE_KEYMSK_1_B 0x71198
6468#define _PLANE_KEYMSK_2_B 0x71298
6469#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6470#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6471#define PLANE_KEYMSK(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006472 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006473
6474#define _PLANE_KEYMAX_1_B 0x711a0
6475#define _PLANE_KEYMAX_2_B 0x712a0
6476#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6477#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6478#define PLANE_KEYMAX(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006479 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00006480
Damien Lespiau8211bd52014-11-04 17:06:44 +00006481#define _PLANE_BUF_CFG_1_B 0x7127c
6482#define _PLANE_BUF_CFG_2_B 0x7137c
6483#define _PLANE_BUF_CFG_1(pipe) \
6484 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6485#define _PLANE_BUF_CFG_2(pipe) \
6486 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6487#define PLANE_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006488 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
Damien Lespiau8211bd52014-11-04 17:06:44 +00006489
Chandra Konduru2cd601c2015-04-27 15:47:37 -07006490#define _PLANE_NV12_BUF_CFG_1_B 0x71278
6491#define _PLANE_NV12_BUF_CFG_2_B 0x71378
6492#define _PLANE_NV12_BUF_CFG_1(pipe) \
6493 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6494#define _PLANE_NV12_BUF_CFG_2(pipe) \
6495 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6496#define PLANE_NV12_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006497 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
Chandra Konduru2cd601c2015-04-27 15:47:37 -07006498
Ville Syrjälä2e2adb02017-08-01 09:58:13 -07006499#define _PLANE_AUX_DIST_1_B 0x711c0
6500#define _PLANE_AUX_DIST_2_B 0x712c0
6501#define _PLANE_AUX_DIST_1(pipe) \
6502 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6503#define _PLANE_AUX_DIST_2(pipe) \
6504 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6505#define PLANE_AUX_DIST(pipe, plane) \
6506 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6507
6508#define _PLANE_AUX_OFFSET_1_B 0x711c4
6509#define _PLANE_AUX_OFFSET_2_B 0x712c4
6510#define _PLANE_AUX_OFFSET_1(pipe) \
6511 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6512#define _PLANE_AUX_OFFSET_2(pipe) \
6513 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6514#define PLANE_AUX_OFFSET(pipe, plane) \
6515 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6516
Ander Conselvan de Oliveira47f9ea82017-01-26 13:24:22 +02006517#define _PLANE_COLOR_CTL_1_B 0x711CC
6518#define _PLANE_COLOR_CTL_2_B 0x712CC
6519#define _PLANE_COLOR_CTL_3_B 0x713CC
6520#define _PLANE_COLOR_CTL_1(pipe) \
6521 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6522#define _PLANE_COLOR_CTL_2(pipe) \
6523 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6524#define PLANE_COLOR_CTL(pipe, plane) \
6525 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6526
6527#/* SKL new cursor registers */
Damien Lespiau8211bd52014-11-04 17:06:44 +00006528#define _CUR_BUF_CFG_A 0x7017c
6529#define _CUR_BUF_CFG_B 0x7117c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006530#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
Damien Lespiau8211bd52014-11-04 17:06:44 +00006531
Jesse Barnes585fb112008-07-29 11:54:06 -07006532/* VBIOS regs */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006533#define VGACNTRL _MMIO(0x71400)
Jesse Barnes585fb112008-07-29 11:54:06 -07006534# define VGA_DISP_DISABLE (1 << 31)
6535# define VGA_2X_MODE (1 << 30)
6536# define VGA_PIPE_B_SELECT (1 << 29)
6537
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006538#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02006539
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006540/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006541
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006542#define CPU_VGACNTRL _MMIO(0x41000)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006543
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006544#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006545#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6546#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6547#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6548#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6549#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6550#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6551#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6552#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6553#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6554#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006555
6556/* refresh rate hardware control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006557#define RR_HW_CTL _MMIO(0x45300)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006558#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6559#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6560
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006561#define FDI_PLL_BIOS_0 _MMIO(0x46000)
Chris Wilson021357a2010-09-07 20:54:59 +01006562#define FDI_PLL_FB_CLOCK_MASK 0xff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006563#define FDI_PLL_BIOS_1 _MMIO(0x46004)
6564#define FDI_PLL_BIOS_2 _MMIO(0x46008)
6565#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6566#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6567#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006568
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006569#define PCH_3DCGDIS0 _MMIO(0x46020)
Eric Anholt8956c8b2010-03-18 13:21:14 -07006570# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6571# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6572
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006573#define PCH_3DCGDIS1 _MMIO(0x46024)
Eric Anholt06f37752010-12-14 10:06:46 -08006574# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6575
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006576#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006577#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
6578#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6579#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6580
6581
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006582#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01006583#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006584#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01006585#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006586
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006587#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01006588#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006589#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01006590#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006591
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006592#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01006593#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006594#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01006595#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006596
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006597#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01006598#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006599#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01006600#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006601
6602/* PIPEB timing regs are same start from 0x61000 */
6603
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006604#define _PIPEB_DATA_M1 0x61030
6605#define _PIPEB_DATA_N1 0x61034
6606#define _PIPEB_DATA_M2 0x61038
6607#define _PIPEB_DATA_N2 0x6103c
6608#define _PIPEB_LINK_M1 0x61040
6609#define _PIPEB_LINK_N1 0x61044
6610#define _PIPEB_LINK_M2 0x61048
6611#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08006612
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006613#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6614#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6615#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6616#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6617#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6618#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6619#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6620#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006621
6622/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006623/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6624#define _PFA_CTL_1 0x68080
6625#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08006626#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02006627#define PF_PIPE_SEL_MASK_IVB (3<<29)
6628#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08006629#define PF_FILTER_MASK (3<<23)
6630#define PF_FILTER_PROGRAMMED (0<<23)
6631#define PF_FILTER_MED_3x3 (1<<23)
6632#define PF_FILTER_EDGE_ENHANCE (2<<23)
6633#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006634#define _PFA_WIN_SZ 0x68074
6635#define _PFB_WIN_SZ 0x68874
6636#define _PFA_WIN_POS 0x68070
6637#define _PFB_WIN_POS 0x68870
6638#define _PFA_VSCALE 0x68084
6639#define _PFB_VSCALE 0x68884
6640#define _PFA_HSCALE 0x68090
6641#define _PFB_HSCALE 0x68890
6642
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006643#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6644#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6645#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6646#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6647#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006648
Jesse Barnesbd2e2442014-11-13 17:51:47 +00006649#define _PSA_CTL 0x68180
6650#define _PSB_CTL 0x68980
6651#define PS_ENABLE (1<<31)
6652#define _PSA_WIN_SZ 0x68174
6653#define _PSB_WIN_SZ 0x68974
6654#define _PSA_WIN_POS 0x68170
6655#define _PSB_WIN_POS 0x68970
6656
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006657#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6658#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6659#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00006660
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006661/*
6662 * Skylake scalers
6663 */
6664#define _PS_1A_CTRL 0x68180
6665#define _PS_2A_CTRL 0x68280
6666#define _PS_1B_CTRL 0x68980
6667#define _PS_2B_CTRL 0x68A80
6668#define _PS_1C_CTRL 0x69180
6669#define PS_SCALER_EN (1 << 31)
6670#define PS_SCALER_MODE_MASK (3 << 28)
6671#define PS_SCALER_MODE_DYN (0 << 28)
6672#define PS_SCALER_MODE_HQ (1 << 28)
6673#define PS_PLANE_SEL_MASK (7 << 25)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006674#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006675#define PS_FILTER_MASK (3 << 23)
6676#define PS_FILTER_MEDIUM (0 << 23)
6677#define PS_FILTER_EDGE_ENHANCE (2 << 23)
6678#define PS_FILTER_BILINEAR (3 << 23)
6679#define PS_VERT3TAP (1 << 21)
6680#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6681#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6682#define PS_PWRUP_PROGRESS (1 << 17)
6683#define PS_V_FILTER_BYPASS (1 << 8)
6684#define PS_VADAPT_EN (1 << 7)
6685#define PS_VADAPT_MODE_MASK (3 << 5)
6686#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6687#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6688#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6689
6690#define _PS_PWR_GATE_1A 0x68160
6691#define _PS_PWR_GATE_2A 0x68260
6692#define _PS_PWR_GATE_1B 0x68960
6693#define _PS_PWR_GATE_2B 0x68A60
6694#define _PS_PWR_GATE_1C 0x69160
6695#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6696#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6697#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6698#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6699#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6700#define PS_PWR_GATE_SLPEN_8 0
6701#define PS_PWR_GATE_SLPEN_16 1
6702#define PS_PWR_GATE_SLPEN_24 2
6703#define PS_PWR_GATE_SLPEN_32 3
6704
6705#define _PS_WIN_POS_1A 0x68170
6706#define _PS_WIN_POS_2A 0x68270
6707#define _PS_WIN_POS_1B 0x68970
6708#define _PS_WIN_POS_2B 0x68A70
6709#define _PS_WIN_POS_1C 0x69170
6710
6711#define _PS_WIN_SZ_1A 0x68174
6712#define _PS_WIN_SZ_2A 0x68274
6713#define _PS_WIN_SZ_1B 0x68974
6714#define _PS_WIN_SZ_2B 0x68A74
6715#define _PS_WIN_SZ_1C 0x69174
6716
6717#define _PS_VSCALE_1A 0x68184
6718#define _PS_VSCALE_2A 0x68284
6719#define _PS_VSCALE_1B 0x68984
6720#define _PS_VSCALE_2B 0x68A84
6721#define _PS_VSCALE_1C 0x69184
6722
6723#define _PS_HSCALE_1A 0x68190
6724#define _PS_HSCALE_2A 0x68290
6725#define _PS_HSCALE_1B 0x68990
6726#define _PS_HSCALE_2B 0x68A90
6727#define _PS_HSCALE_1C 0x69190
6728
6729#define _PS_VPHASE_1A 0x68188
6730#define _PS_VPHASE_2A 0x68288
6731#define _PS_VPHASE_1B 0x68988
6732#define _PS_VPHASE_2B 0x68A88
6733#define _PS_VPHASE_1C 0x69188
6734
6735#define _PS_HPHASE_1A 0x68194
6736#define _PS_HPHASE_2A 0x68294
6737#define _PS_HPHASE_1B 0x68994
6738#define _PS_HPHASE_2B 0x68A94
6739#define _PS_HPHASE_1C 0x69194
6740
6741#define _PS_ECC_STAT_1A 0x681D0
6742#define _PS_ECC_STAT_2A 0x682D0
6743#define _PS_ECC_STAT_1B 0x689D0
6744#define _PS_ECC_STAT_2B 0x68AD0
6745#define _PS_ECC_STAT_1C 0x691D0
6746
6747#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006748#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006749 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6750 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006751#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006752 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6753 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006754#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006755 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6756 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006757#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006758 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6759 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006760#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006761 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6762 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006763#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006764 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6765 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006766#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006767 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6768 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006769#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006770 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6771 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006772#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006773 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
Ville Syrjälä9bca5d02015-11-04 23:20:16 +02006774 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07006775
Zhenyu Wangb9055052009-06-05 15:38:38 +08006776/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006777#define _LGC_PALETTE_A 0x4a000
6778#define _LGC_PALETTE_B 0x4a800
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006779#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006780
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006781#define _GAMMA_MODE_A 0x4a480
6782#define _GAMMA_MODE_B 0x4ac80
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006783#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006784#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006785#define GAMMA_MODE_MODE_8BIT (0 << 0)
6786#define GAMMA_MODE_MODE_10BIT (1 << 0)
6787#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006788#define GAMMA_MODE_MODE_SPLIT (3 << 0)
6789
Damien Lespiau83372062015-10-30 17:53:32 +02006790/* DMC/CSR */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006791#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02006792#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6793#define CSR_HTP_ADDR_SKL 0x00500034
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006794#define CSR_SSP_BASE _MMIO(0x8F074)
6795#define CSR_HTP_SKL _MMIO(0x8F004)
6796#define CSR_LAST_WRITE _MMIO(0x8F034)
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02006797#define CSR_LAST_WRITE_VALUE 0xc003b400
6798/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6799#define CSR_MMIO_START_RANGE 0x80000
6800#define CSR_MMIO_END_RANGE 0x8FFFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006801#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6802#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6803#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
Damien Lespiau83372062015-10-30 17:53:32 +02006804
Zhenyu Wangb9055052009-06-05 15:38:38 +08006805/* interrupts */
6806#define DE_MASTER_IRQ_CONTROL (1 << 31)
6807#define DE_SPRITEB_FLIP_DONE (1 << 29)
6808#define DE_SPRITEA_FLIP_DONE (1 << 28)
6809#define DE_PLANEB_FLIP_DONE (1 << 27)
6810#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c22013-10-21 18:04:36 +02006811#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08006812#define DE_PCU_EVENT (1 << 25)
6813#define DE_GTT_FAULT (1 << 24)
6814#define DE_POISON (1 << 23)
6815#define DE_PERFORM_COUNTER (1 << 22)
6816#define DE_PCH_EVENT (1 << 21)
6817#define DE_AUX_CHANNEL_A (1 << 20)
6818#define DE_DP_A_HOTPLUG (1 << 19)
6819#define DE_GSE (1 << 18)
6820#define DE_PIPEB_VBLANK (1 << 15)
6821#define DE_PIPEB_EVEN_FIELD (1 << 14)
6822#define DE_PIPEB_ODD_FIELD (1 << 13)
6823#define DE_PIPEB_LINE_COMPARE (1 << 12)
6824#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02006825#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006826#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
6827#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c22013-10-21 18:04:36 +02006828#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08006829#define DE_PIPEA_EVEN_FIELD (1 << 6)
6830#define DE_PIPEA_ODD_FIELD (1 << 5)
6831#define DE_PIPEA_LINE_COMPARE (1 << 4)
6832#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02006833#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c22013-10-21 18:04:36 +02006834#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08006835#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c22013-10-21 18:04:36 +02006836#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08006837
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006838/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03006839#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006840#define DE_GSE_IVB (1<<29)
6841#define DE_PCH_EVENT_IVB (1<<28)
6842#define DE_DP_A_HOTPLUG_IVB (1<<27)
6843#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01006844#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
6845#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
6846#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006847#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006848#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006849#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01006850#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
6851#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c22013-10-21 18:04:36 +02006852#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07006853#define DE_PIPEA_VBLANK_IVB (1<<0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006854#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
Paulo Zanonib5184212013-07-12 20:00:08 -03006855
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006856#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07006857#define MASTER_INTERRUPT_ENABLE (1<<31)
6858
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006859#define DEISR _MMIO(0x44000)
6860#define DEIMR _MMIO(0x44004)
6861#define DEIIR _MMIO(0x44008)
6862#define DEIER _MMIO(0x4400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006863
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006864#define GTISR _MMIO(0x44010)
6865#define GTIMR _MMIO(0x44014)
6866#define GTIIR _MMIO(0x44018)
6867#define GTIER _MMIO(0x4401c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006868
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006869#define GEN8_MASTER_IRQ _MMIO(0x44200)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006870#define GEN8_MASTER_IRQ_CONTROL (1<<31)
6871#define GEN8_PCU_IRQ (1<<30)
6872#define GEN8_DE_PCH_IRQ (1<<23)
6873#define GEN8_DE_MISC_IRQ (1<<22)
6874#define GEN8_DE_PORT_IRQ (1<<20)
6875#define GEN8_DE_PIPE_C_IRQ (1<<18)
6876#define GEN8_DE_PIPE_B_IRQ (1<<17)
6877#define GEN8_DE_PIPE_A_IRQ (1<<16)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006878#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
Ben Widawskyabd58f02013-11-02 21:07:09 -07006879#define GEN8_GT_VECS_IRQ (1<<6)
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05306880#define GEN8_GT_GUC_IRQ (1<<5)
Ben Widawsky09610212014-05-15 20:58:08 +03006881#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006882#define GEN8_GT_VCS2_IRQ (1<<3)
6883#define GEN8_GT_VCS1_IRQ (1<<2)
6884#define GEN8_GT_BCS_IRQ (1<<1)
6885#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006886
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006887#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
6888#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
6889#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
6890#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
Ben Widawskyabd58f02013-11-02 21:07:09 -07006891
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05306892#define GEN9_GUC_TO_HOST_INT_EVENT (1<<31)
6893#define GEN9_GUC_EXEC_ERROR_EVENT (1<<30)
6894#define GEN9_GUC_DISPLAY_EVENT (1<<29)
6895#define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28)
6896#define GEN9_GUC_IOMMU_MSG_EVENT (1<<27)
6897#define GEN9_GUC_DB_RING_EVENT (1<<26)
6898#define GEN9_GUC_DMA_DONE_EVENT (1<<25)
6899#define GEN9_GUC_FATAL_ERROR_EVENT (1<<24)
6900#define GEN9_GUC_NOTIFICATION_EVENT (1<<23)
6901
Ben Widawskyabd58f02013-11-02 21:07:09 -07006902#define GEN8_RCS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01006903#define GEN8_BCS_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07006904#define GEN8_VCS1_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01006905#define GEN8_VCS2_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07006906#define GEN8_VECS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01006907#define GEN8_WD_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07006908
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006909#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
6910#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
6911#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
6912#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01006913#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006914#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
6915#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
6916#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
6917#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
6918#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
6919#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01006920#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006921#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
6922#define GEN8_PIPE_VSYNC (1 << 1)
6923#define GEN8_PIPE_VBLANK (1 << 0)
Damien Lespiau770de83d2014-03-20 20:45:01 +00006924#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
Damien Lespiaub21249c2015-03-17 11:39:33 +02006925#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
Damien Lespiau770de83d2014-03-20 20:45:01 +00006926#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
6927#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
6928#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
Damien Lespiaub21249c2015-03-17 11:39:33 +02006929#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
Damien Lespiau770de83d2014-03-20 20:45:01 +00006930#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
6931#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
6932#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006933#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
Daniel Vetter30100f22013-11-07 14:49:24 +01006934#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
6935 (GEN8_PIPE_CURSOR_FAULT | \
6936 GEN8_PIPE_SPRITE_FAULT | \
6937 GEN8_PIPE_PRIMARY_FAULT)
Damien Lespiau770de83d2014-03-20 20:45:01 +00006938#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
6939 (GEN9_PIPE_CURSOR_FAULT | \
Damien Lespiaub21249c2015-03-17 11:39:33 +02006940 GEN9_PIPE_PLANE4_FAULT | \
Damien Lespiau770de83d2014-03-20 20:45:01 +00006941 GEN9_PIPE_PLANE3_FAULT | \
6942 GEN9_PIPE_PLANE2_FAULT | \
6943 GEN9_PIPE_PLANE1_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006944
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006945#define GEN8_DE_PORT_ISR _MMIO(0x44440)
6946#define GEN8_DE_PORT_IMR _MMIO(0x44444)
6947#define GEN8_DE_PORT_IIR _MMIO(0x44448)
6948#define GEN8_DE_PORT_IER _MMIO(0x4444c)
Rodrigo Vivia324fca2018-01-29 15:22:15 -08006949#define CNL_AUX_CHANNEL_F (1 << 28)
Jesse Barnes88e04702014-11-13 17:51:48 +00006950#define GEN9_AUX_CHANNEL_D (1 << 27)
6951#define GEN9_AUX_CHANNEL_C (1 << 26)
6952#define GEN9_AUX_CHANNEL_B (1 << 25)
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02006953#define BXT_DE_PORT_HP_DDIC (1 << 5)
6954#define BXT_DE_PORT_HP_DDIB (1 << 4)
6955#define BXT_DE_PORT_HP_DDIA (1 << 3)
6956#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
6957 BXT_DE_PORT_HP_DDIB | \
6958 BXT_DE_PORT_HP_DDIC)
6959#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
Shashank Sharma9e637432014-08-22 17:40:43 +05306960#define BXT_DE_PORT_GMBUS (1 << 1)
Daniel Vetter6d766f02013-11-07 14:49:55 +01006961#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006962
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006963#define GEN8_DE_MISC_ISR _MMIO(0x44460)
6964#define GEN8_DE_MISC_IMR _MMIO(0x44464)
6965#define GEN8_DE_MISC_IIR _MMIO(0x44468)
6966#define GEN8_DE_MISC_IER _MMIO(0x4446c)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006967#define GEN8_DE_MISC_GSE (1 << 27)
6968
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006969#define GEN8_PCU_ISR _MMIO(0x444e0)
6970#define GEN8_PCU_IMR _MMIO(0x444e4)
6971#define GEN8_PCU_IIR _MMIO(0x444e8)
6972#define GEN8_PCU_IER _MMIO(0x444ec)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006973
Tvrtko Ursulina6358dd2018-01-09 21:23:13 -02006974#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
6975#define GEN11_MASTER_IRQ (1 << 31)
6976#define GEN11_PCU_IRQ (1 << 30)
6977#define GEN11_DISPLAY_IRQ (1 << 16)
6978#define GEN11_GT_DW_IRQ(x) (1 << (x))
6979#define GEN11_GT_DW1_IRQ (1 << 1)
6980#define GEN11_GT_DW0_IRQ (1 << 0)
6981
6982#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
6983#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
6984#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
6985#define GEN11_DE_PCH_IRQ (1 << 23)
6986#define GEN11_DE_MISC_IRQ (1 << 22)
6987#define GEN11_DE_PORT_IRQ (1 << 20)
6988#define GEN11_DE_PIPE_C (1 << 18)
6989#define GEN11_DE_PIPE_B (1 << 17)
6990#define GEN11_DE_PIPE_A (1 << 16)
6991
6992#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
6993#define GEN11_CSME (31)
6994#define GEN11_GUNIT (28)
6995#define GEN11_GUC (25)
6996#define GEN11_WDPERF (20)
6997#define GEN11_KCR (19)
6998#define GEN11_GTPM (16)
6999#define GEN11_BCS (15)
7000#define GEN11_RCS0 (0)
7001
7002#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7003#define GEN11_VECS(x) (31 - (x))
7004#define GEN11_VCS(x) (x)
7005
7006#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + (x * 4))
7007
7008#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7009#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7010#define GEN11_INTR_DATA_VALID (1 << 31)
7011#define GEN11_INTR_ENGINE_MASK (0xffff)
7012
7013#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
7014
7015#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7016#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7017
7018#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
7019
7020#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7021#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7022#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7023#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7024#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7025#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7026
7027#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7028#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7029#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7030#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7031#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7032#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7033#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7034#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7035#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7036
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007037#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
Eric Anholt67e92af2010-11-06 14:53:33 -07007038/* Required on all Ironlake and Sandybridge according to the B-Spec. */
7039#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007040#define ILK_DPARB_GATE (1<<22)
7041#define ILK_VSDPFD_FULL (1<<21)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007042#define FUSE_STRAP _MMIO(0x42014)
Damien Lespiaue3589902014-02-07 19:12:50 +00007043#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7044#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7045#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
Gabriel Feceoru8c448ca2016-01-22 13:28:45 +02007046#define IVB_PIPE_C_DISABLE (1 << 28)
Damien Lespiaue3589902014-02-07 19:12:50 +00007047#define ILK_HDCP_DISABLE (1 << 25)
7048#define ILK_eDP_A_DISABLE (1 << 24)
7049#define HSW_CDCLK_LIMIT (1 << 24)
7050#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08007051
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007052#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
Damien Lespiau231e54f2012-10-19 17:55:41 +01007053#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7054#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7055#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7056#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7057#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007058
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007059#define IVB_CHICKEN3 _MMIO(0x4200c)
Eric Anholt116ac8d2011-12-21 10:31:09 -08007060# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7061# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7062
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007063#define CHICKEN_PAR1_1 _MMIO(0x42080)
Ville Syrjälä93564042017-08-24 22:10:51 +03007064#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007065#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03007066#define FORCE_ARB_IDLE_PLANES (1 << 14)
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02007067#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
Paulo Zanoni90a88642013-05-03 17:23:45 -03007068
Mika Kuoppala17e0adf2016-06-07 17:19:02 +03007069#define CHICKEN_PAR2_1 _MMIO(0x42090)
7070#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7071
Ander Conselvan de Oliveiraf4f4b592017-02-22 08:34:29 +02007072#define CHICKEN_MISC_2 _MMIO(0x42084)
Paulo Zanoni746a5172017-07-14 14:52:28 -03007073#define CNL_COMP_PWR_DOWN (1 << 23)
Ander Conselvan de Oliveiraf4f4b592017-02-22 08:34:29 +02007074#define GLK_CL2_PWR_DOWN (1 << 12)
Paulo Zanoni746a5172017-07-14 14:52:28 -03007075#define GLK_CL1_PWR_DOWN (1 << 11)
7076#define GLK_CL0_PWR_DOWN (1 << 10)
Ville Syrjäläd8d4a512017-06-09 15:26:00 -07007077
Praveen Paneri5654a162017-08-11 00:00:33 +05307078#define CHICKEN_MISC_4 _MMIO(0x4208c)
7079#define FBC_STRIDE_OVERRIDE (1 << 13)
7080#define FBC_STRIDE_MASK 0x1FFF
7081
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007082#define _CHICKEN_PIPESL_1_A 0x420b0
7083#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02007084#define HSW_FBCQ_DIS (1 << 22)
7085#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007086#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07007087
Nagaraju, Vathsalad86f0482017-01-13 00:31:31 +05307088#define CHICKEN_TRANS_A 0x420c0
7089#define CHICKEN_TRANS_B 0x420c4
7090#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
Ville Syrjälä0519c102018-01-22 19:41:31 +02007091#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
7092#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
7093#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
7094#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
7095#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
7096#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
Nagaraju, Vathsalad86f0482017-01-13 00:31:31 +05307097
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007098#define DISP_ARB_CTL _MMIO(0x45000)
Mika Kuoppala303d4ea2016-06-07 17:19:17 +03007099#define DISP_FBC_MEMORY_WAKE (1<<31)
Zhenyu Wang553bd142009-09-02 10:57:52 +08007100#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007101#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007102#define DISP_ARB_CTL2 _MMIO(0x45004)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02007103#define DISP_DATA_PARTITION_5_6 (1<<6)
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05307104#define DISP_IPC_ENABLE (1<<3)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007105#define DBUF_CTL _MMIO(0x45008)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307106#define DBUF_POWER_REQUEST (1<<31)
7107#define DBUF_POWER_STATE (1<<30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007108#define GEN7_MSG_CTL _MMIO(0x45010)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07007109#define WAIT_FOR_PCH_RESET_ACK (1<<1)
7110#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007111#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01007112#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08007113
Mika Kuoppala590e8ff2016-06-07 17:19:13 +03007114#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
Lucas De Marchi53421c22017-12-04 15:22:10 -08007115#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
Mika Kuoppala590e8ff2016-06-07 17:19:13 +03007116#define MASK_WAKEMEM (1<<13)
7117
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007118#define SKL_DFSM _MMIO(0x51000)
Damien Lespiaua9419e82015-06-04 18:21:30 +01007119#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7120#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7121#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7122#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7123#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
Patrik Jakobssonbf4f2fb2016-01-20 15:31:20 +01007124#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7125#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7126#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
Damien Lespiaua9419e82015-06-04 18:21:30 +01007127
Ville Syrjälä945f2672017-06-09 15:25:58 -07007128#define SKL_DSSM _MMIO(0x51004)
7129#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7130
Arun Siluverya78536e2016-01-21 21:43:53 +00007131#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7132#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
7133
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007134#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
Damien Lespiau2caa3b22015-02-09 19:33:20 +00007135#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
arun.siluvery@linux.intel.com780f0ae2016-06-03 11:16:10 +01007136#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10)
Damien Lespiau2caa3b22015-02-09 19:33:20 +00007137
Arun Siluvery2c8580e2016-01-21 21:43:50 +00007138#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
arun.siluvery@linux.intel.com6bb628552016-06-06 09:52:49 +01007139#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
Arun Siluverye0f3fa02016-01-21 21:43:48 +00007140#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
Michał Winiarski5152def2017-10-03 21:34:46 +01007141#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
7142#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7143#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7144#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7145#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7146#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
Arun Siluverye0f3fa02016-01-21 21:43:48 +00007147
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08007148/* GEN7 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007149#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
Kenneth Graunked71de142012-02-08 12:53:52 -08007150# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Damien Lespiau183c6da2015-02-09 19:33:11 +00007151# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007152#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
Ville Syrjälä93564042017-08-24 22:10:51 +03007153# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
Mika Kuoppala873e8172016-07-20 14:26:13 +03007154# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
Mika Kuoppalaad2bdb42016-06-07 17:19:07 +03007155# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
Ben Widawskya75f3622013-11-02 21:07:59 -07007156# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08007157
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007158#define HIZ_CHICKEN _MMIO(0x7018)
Damien Lespiaud0bbbc4f2015-02-09 19:33:16 +00007159# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
7160# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
Kenneth Graunked60de812015-01-10 18:02:22 -08007161
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007162#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
Damien Lespiau183c6da2015-02-09 19:33:11 +00007163#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
7164
Kenneth Graunkeab062632018-01-05 00:59:05 -08007165#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7166
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007167#define GEN7_L3SQCREG1 _MMIO(0xB010)
Ville Syrjälä031994e2014-01-22 21:32:46 +02007168#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7169
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007170#define GEN8_L3SQCREG1 _MMIO(0xB100)
Imre Deak450174f2016-05-03 15:54:21 +03007171/*
7172 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7173 * Using the formula in BSpec leads to a hang, while the formula here works
7174 * fine and matches the formulas for all other platforms. A BSpec change
7175 * request has been filed to clarify this.
7176 */
Imre Deak36579cb2016-05-03 15:54:20 +03007177#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7178#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
Oscar Mateo930a7842017-10-17 13:25:45 -07007179#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
Rodrigo Vivi51ce4db2015-03-31 16:03:21 -07007180
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007181#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
Chris Wilson1af84522014-02-14 22:34:43 +00007182#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07007183#define GEN7_L3AGDIS (1<<19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007184#define GEN7_L3CNTLREG2 _MMIO(0xB020)
7185#define GEN7_L3CNTLREG3 _MMIO(0xB024)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08007186
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007187#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08007188#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7189
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007190#define GEN7_L3SQCREG4 _MMIO(0xb034)
Jesse Barnes61939d92012-10-02 17:43:38 -05007191#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
7192
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007193#define GEN8_L3SQCREG4 _MMIO(0xb118)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00007194#define GEN8_LQSC_RO_PERF_DIS (1<<27)
Arun Siluveryc82435b2015-06-19 18:37:13 +01007195#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00007196
Ben Widawsky63801f22013-12-12 17:26:03 -08007197/* GEN8 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007198#define HDC_CHICKEN0 _MMIO(0x7300)
Rodrigo Viviacfb5552017-08-23 13:35:04 -07007199#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
Imre Deak2a0ee942015-05-19 17:05:41 +03007200#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
Rodrigo Vivida096542014-09-19 20:16:27 -04007201#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
Damien Lespiau35cb6f32015-02-10 10:31:00 +00007202#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
7203#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
7204#define HDC_FORCE_NON_COHERENT (1<<4)
Damien Lespiau65ca7512015-02-09 19:33:22 +00007205#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
Ben Widawsky63801f22013-12-12 17:26:03 -08007206
Arun Siluvery3669ab62016-01-21 21:43:49 +00007207#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7208
Ben Widawsky38a39a72015-03-11 10:54:53 +02007209/* GEN9 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007210#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
Ben Widawsky38a39a72015-03-11 10:54:53 +02007211#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7212
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08007213/* WaCatErrorRejectionIssue */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007214#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08007215#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
7216
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007217#define HSW_SCRATCH1 _MMIO(0xb038)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07007218#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
7219
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007220#define BDW_SCRATCH1 _MMIO(0xb11c)
Damien Lespiau77719d22015-02-09 19:33:13 +00007221#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
7222
Zhenyu Wangb9055052009-06-05 15:38:38 +08007223/* PCH */
7224
Adam Jackson23e81d62012-06-06 15:45:44 -04007225/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08007226#define SDE_AUDIO_POWER_D (1 << 27)
7227#define SDE_AUDIO_POWER_C (1 << 26)
7228#define SDE_AUDIO_POWER_B (1 << 25)
7229#define SDE_AUDIO_POWER_SHIFT (25)
7230#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7231#define SDE_GMBUS (1 << 24)
7232#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7233#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7234#define SDE_AUDIO_HDCP_MASK (3 << 22)
7235#define SDE_AUDIO_TRANSB (1 << 21)
7236#define SDE_AUDIO_TRANSA (1 << 20)
7237#define SDE_AUDIO_TRANS_MASK (3 << 20)
7238#define SDE_POISON (1 << 19)
7239/* 18 reserved */
7240#define SDE_FDI_RXB (1 << 17)
7241#define SDE_FDI_RXA (1 << 16)
7242#define SDE_FDI_MASK (3 << 16)
7243#define SDE_AUXD (1 << 15)
7244#define SDE_AUXC (1 << 14)
7245#define SDE_AUXB (1 << 13)
7246#define SDE_AUX_MASK (7 << 13)
7247/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08007248#define SDE_CRT_HOTPLUG (1 << 11)
7249#define SDE_PORTD_HOTPLUG (1 << 10)
7250#define SDE_PORTC_HOTPLUG (1 << 9)
7251#define SDE_PORTB_HOTPLUG (1 << 8)
7252#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05007253#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7254 SDE_SDVOB_HOTPLUG | \
7255 SDE_PORTB_HOTPLUG | \
7256 SDE_PORTC_HOTPLUG | \
7257 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08007258#define SDE_TRANSB_CRC_DONE (1 << 5)
7259#define SDE_TRANSB_CRC_ERR (1 << 4)
7260#define SDE_TRANSB_FIFO_UNDER (1 << 3)
7261#define SDE_TRANSA_CRC_DONE (1 << 2)
7262#define SDE_TRANSA_CRC_ERR (1 << 1)
7263#define SDE_TRANSA_FIFO_UNDER (1 << 0)
7264#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04007265
7266/* south display engine interrupt: CPT/PPT */
7267#define SDE_AUDIO_POWER_D_CPT (1 << 31)
7268#define SDE_AUDIO_POWER_C_CPT (1 << 30)
7269#define SDE_AUDIO_POWER_B_CPT (1 << 29)
7270#define SDE_AUDIO_POWER_SHIFT_CPT 29
7271#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7272#define SDE_AUXD_CPT (1 << 27)
7273#define SDE_AUXC_CPT (1 << 26)
7274#define SDE_AUXB_CPT (1 << 25)
7275#define SDE_AUX_MASK_CPT (7 << 25)
Xiong Zhang26951ca2015-08-17 15:55:50 +08007276#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
Ville Syrjälä74c0b392015-08-27 23:56:07 +03007277#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007278#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7279#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7280#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04007281#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01007282#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01007283#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01007284 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01007285 SDE_PORTD_HOTPLUG_CPT | \
7286 SDE_PORTC_HOTPLUG_CPT | \
7287 SDE_PORTB_HOTPLUG_CPT)
Xiong Zhang26951ca2015-08-17 15:55:50 +08007288#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7289 SDE_PORTD_HOTPLUG_CPT | \
7290 SDE_PORTC_HOTPLUG_CPT | \
Ville Syrjälä74c0b392015-08-27 23:56:07 +03007291 SDE_PORTB_HOTPLUG_CPT | \
7292 SDE_PORTA_HOTPLUG_SPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04007293#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03007294#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04007295#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7296#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7297#define SDE_FDI_RXC_CPT (1 << 8)
7298#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7299#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7300#define SDE_FDI_RXB_CPT (1 << 4)
7301#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7302#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7303#define SDE_FDI_RXA_CPT (1 << 0)
7304#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7305 SDE_AUDIO_CP_REQ_B_CPT | \
7306 SDE_AUDIO_CP_REQ_A_CPT)
7307#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7308 SDE_AUDIO_CP_CHG_B_CPT | \
7309 SDE_AUDIO_CP_CHG_A_CPT)
7310#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7311 SDE_FDI_RXB_CPT | \
7312 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007313
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007314#define SDEISR _MMIO(0xc4000)
7315#define SDEIMR _MMIO(0xc4004)
7316#define SDEIIR _MMIO(0xc4008)
7317#define SDEIER _MMIO(0xc400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007318
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007319#define SERR_INT _MMIO(0xc4040)
Paulo Zanonide032bf2013-04-12 17:57:58 -03007320#define SERR_INT_POISON (1<<31)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007321#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03007322
Zhenyu Wangb9055052009-06-05 15:38:38 +08007323/* digital port hotplug */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007324#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
Ville Syrjälä195baa02015-08-27 23:56:00 +03007325#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05307326#define BXT_DDIA_HPD_INVERT (1 << 27)
Ville Syrjälä195baa02015-08-27 23:56:00 +03007327#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7328#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7329#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7330#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007331#define PORTD_HOTPLUG_ENABLE (1 << 20)
7332#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7333#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7334#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7335#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7336#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7337#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
Damien Lespiaub6965192012-12-13 16:08:59 +00007338#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7339#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7340#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007341#define PORTC_HOTPLUG_ENABLE (1 << 12)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05307342#define BXT_DDIC_HPD_INVERT (1 << 11)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007343#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7344#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7345#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7346#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7347#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7348#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
Damien Lespiaub6965192012-12-13 16:08:59 +00007349#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7350#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7351#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007352#define PORTB_HOTPLUG_ENABLE (1 << 4)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05307353#define BXT_DDIB_HPD_INVERT (1 << 3)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007354#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7355#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7356#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7357#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7358#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7359#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
Damien Lespiaub6965192012-12-13 16:08:59 +00007360#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7361#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7362#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05307363#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7364 BXT_DDIB_HPD_INVERT | \
7365 BXT_DDIC_HPD_INVERT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007366
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007367#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03007368#define PORTE_HOTPLUG_ENABLE (1 << 4)
7369#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
Xiong Zhang26951ca2015-08-17 15:55:50 +08007370#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7371#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7372#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7373
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007374#define PCH_GPIOA _MMIO(0xc5010)
7375#define PCH_GPIOB _MMIO(0xc5014)
7376#define PCH_GPIOC _MMIO(0xc5018)
7377#define PCH_GPIOD _MMIO(0xc501c)
7378#define PCH_GPIOE _MMIO(0xc5020)
7379#define PCH_GPIOF _MMIO(0xc5024)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007380
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007381#define PCH_GMBUS0 _MMIO(0xc5100)
7382#define PCH_GMBUS1 _MMIO(0xc5104)
7383#define PCH_GMBUS2 _MMIO(0xc5108)
7384#define PCH_GMBUS3 _MMIO(0xc510c)
7385#define PCH_GMBUS4 _MMIO(0xc5110)
7386#define PCH_GMBUS5 _MMIO(0xc5120)
Eric Anholtf0217c42009-12-01 11:56:30 -08007387
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007388#define _PCH_DPLL_A 0xc6014
7389#define _PCH_DPLL_B 0xc6018
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007390#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007391
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007392#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00007393#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007394#define _PCH_FPA1 0xc6044
7395#define _PCH_FPB0 0xc6048
7396#define _PCH_FPB1 0xc604c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007397#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
7398#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007399
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007400#define PCH_DPLL_TEST _MMIO(0xc606c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007401
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007402#define PCH_DREF_CONTROL _MMIO(0xC6200)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007403#define DREF_CONTROL_MASK 0x7fc3
7404#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
7405#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
7406#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
7407#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
7408#define DREF_SSC_SOURCE_DISABLE (0<<11)
7409#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08007410#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007411#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
7412#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
7413#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08007414#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007415#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
7416#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08007417#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007418#define DREF_SSC4_DOWNSPREAD (0<<6)
7419#define DREF_SSC4_CENTERSPREAD (1<<6)
7420#define DREF_SSC1_DISABLE (0<<1)
7421#define DREF_SSC1_ENABLE (1<<1)
7422#define DREF_SSC4_DISABLE (0)
7423#define DREF_SSC4_ENABLE (1)
7424
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007425#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007426#define FDL_TP1_TIMER_SHIFT 12
7427#define FDL_TP1_TIMER_MASK (3<<12)
7428#define FDL_TP2_TIMER_SHIFT 10
7429#define FDL_TP2_TIMER_MASK (3<<10)
7430#define RAWCLK_FREQ_MASK 0x3ff
Rodrigo Vivi9d81a992017-06-02 13:06:41 -07007431#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7432#define CNP_RAWCLK_DIV(div) ((div) << 16)
7433#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7434#define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
Anusha Srivatsa4ef99ab2018-01-11 16:00:06 -02007435#define ICP_RAWCLK_DEN(den) ((den) << 26)
7436#define ICP_RAWCLK_NUM(num) ((num) << 11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007437
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007438#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007439
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007440#define PCH_SSC4_PARMS _MMIO(0xc6210)
7441#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007442
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007443#define PCH_DPLL_SEL _MMIO(0xc7000)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007444#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
Daniel Vetter11887392013-06-05 13:34:09 +02007445#define TRANS_DPLLA_SEL(pipe) 0
Ville Syrjälä68d97532015-09-18 20:03:39 +03007446#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007447
Zhenyu Wangb9055052009-06-05 15:38:38 +08007448/* transcoder */
7449
Daniel Vetter275f01b22013-05-03 11:49:47 +02007450#define _PCH_TRANS_HTOTAL_A 0xe0000
7451#define TRANS_HTOTAL_SHIFT 16
7452#define TRANS_HACTIVE_SHIFT 0
7453#define _PCH_TRANS_HBLANK_A 0xe0004
7454#define TRANS_HBLANK_END_SHIFT 16
7455#define TRANS_HBLANK_START_SHIFT 0
7456#define _PCH_TRANS_HSYNC_A 0xe0008
7457#define TRANS_HSYNC_END_SHIFT 16
7458#define TRANS_HSYNC_START_SHIFT 0
7459#define _PCH_TRANS_VTOTAL_A 0xe000c
7460#define TRANS_VTOTAL_SHIFT 16
7461#define TRANS_VACTIVE_SHIFT 0
7462#define _PCH_TRANS_VBLANK_A 0xe0010
7463#define TRANS_VBLANK_END_SHIFT 16
7464#define TRANS_VBLANK_START_SHIFT 0
7465#define _PCH_TRANS_VSYNC_A 0xe0014
7466#define TRANS_VSYNC_END_SHIFT 16
7467#define TRANS_VSYNC_START_SHIFT 0
7468#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08007469
Daniel Vettere3b95f12013-05-03 11:49:49 +02007470#define _PCH_TRANSA_DATA_M1 0xe0030
7471#define _PCH_TRANSA_DATA_N1 0xe0034
7472#define _PCH_TRANSA_DATA_M2 0xe0038
7473#define _PCH_TRANSA_DATA_N2 0xe003c
7474#define _PCH_TRANSA_LINK_M1 0xe0040
7475#define _PCH_TRANSA_LINK_N1 0xe0044
7476#define _PCH_TRANSA_LINK_M2 0xe0048
7477#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08007478
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03007479/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07007480#define _VIDEO_DIP_CTL_A 0xe0200
7481#define _VIDEO_DIP_DATA_A 0xe0208
7482#define _VIDEO_DIP_GCP_A 0xe0210
Ville Syrjälä6d674152015-05-05 17:06:20 +03007483#define GCP_COLOR_INDICATION (1 << 2)
7484#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7485#define GCP_AV_MUTE (1 << 0)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07007486
7487#define _VIDEO_DIP_CTL_B 0xe1200
7488#define _VIDEO_DIP_DATA_B 0xe1208
7489#define _VIDEO_DIP_GCP_B 0xe1210
7490
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007491#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7492#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7493#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07007494
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03007495/* Per-transcoder DIP controls (VLV) */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007496#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7497#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7498#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007499
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007500#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7501#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7502#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007503
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007504#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7505#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7506#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03007507
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007508#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007509 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007510 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007511#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007512 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007513 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007514#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007515 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007516 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07007517
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03007518/* Haswell DIP controls */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007519
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007520#define _HSW_VIDEO_DIP_CTL_A 0x60200
7521#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7522#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7523#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7524#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7525#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7526#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7527#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7528#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7529#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7530#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7531#define _HSW_VIDEO_DIP_GCP_A 0x60210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03007532
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007533#define _HSW_VIDEO_DIP_CTL_B 0x61200
7534#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7535#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7536#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7537#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7538#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7539#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7540#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7541#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7542#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7543#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7544#define _HSW_VIDEO_DIP_GCP_B 0x61210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03007545
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007546#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7547#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7548#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7549#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7550#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7551#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03007552
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007553#define _HSW_STEREO_3D_CTL_A 0x70020
7554#define S3D_ENABLE (1<<31)
7555#define _HSW_STEREO_3D_CTL_B 0x71020
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03007556
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007557#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03007558
Daniel Vetter275f01b22013-05-03 11:49:47 +02007559#define _PCH_TRANS_HTOTAL_B 0xe1000
7560#define _PCH_TRANS_HBLANK_B 0xe1004
7561#define _PCH_TRANS_HSYNC_B 0xe1008
7562#define _PCH_TRANS_VTOTAL_B 0xe100c
7563#define _PCH_TRANS_VBLANK_B 0xe1010
7564#define _PCH_TRANS_VSYNC_B 0xe1014
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007565#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08007566
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007567#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7568#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7569#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7570#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7571#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7572#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7573#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01007574
Daniel Vettere3b95f12013-05-03 11:49:49 +02007575#define _PCH_TRANSB_DATA_M1 0xe1030
7576#define _PCH_TRANSB_DATA_N1 0xe1034
7577#define _PCH_TRANSB_DATA_M2 0xe1038
7578#define _PCH_TRANSB_DATA_N2 0xe103c
7579#define _PCH_TRANSB_LINK_M1 0xe1040
7580#define _PCH_TRANSB_LINK_N1 0xe1044
7581#define _PCH_TRANSB_LINK_M2 0xe1048
7582#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08007583
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007584#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7585#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7586#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
7587#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
7588#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
7589#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
7590#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
7591#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007592
Daniel Vetterab9412b2013-05-03 11:49:46 +02007593#define _PCH_TRANSACONF 0xf0008
7594#define _PCH_TRANSBCONF 0xf1008
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007595#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
7596#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08007597#define TRANS_DISABLE (0<<31)
7598#define TRANS_ENABLE (1<<31)
7599#define TRANS_STATE_MASK (1<<30)
7600#define TRANS_STATE_DISABLE (0<<30)
7601#define TRANS_STATE_ENABLE (1<<30)
7602#define TRANS_FSYNC_DELAY_HB1 (0<<27)
7603#define TRANS_FSYNC_DELAY_HB2 (1<<27)
7604#define TRANS_FSYNC_DELAY_HB3 (2<<27)
7605#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02007606#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007607#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02007608#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02007609#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007610#define TRANS_8BPC (0<<5)
7611#define TRANS_10BPC (1<<5)
7612#define TRANS_6BPC (2<<5)
7613#define TRANS_12BPC (3<<5)
7614
Daniel Vetterce401412012-10-31 22:52:30 +01007615#define _TRANSA_CHICKEN1 0xf0060
7616#define _TRANSB_CHICKEN1 0xf1060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007617#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
Ville Syrjäläd1b15892015-05-05 17:06:19 +03007618#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
Daniel Vetterce401412012-10-31 22:52:30 +01007619#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07007620#define _TRANSA_CHICKEN2 0xf0064
7621#define _TRANSB_CHICKEN2 0xf1064
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007622#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03007623#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
7624#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
7625#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
7626#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
7627#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07007628
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007629#define SOUTH_CHICKEN1 _MMIO(0xc2000)
Jesse Barnes291427f2011-07-29 12:42:37 -07007630#define FDIA_PHASE_SYNC_SHIFT_OVR 19
7631#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02007632#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
7633#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
7634#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Rodrigo Vivi3b92e262017-09-19 14:57:03 -07007635#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
7636#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03007637#define SPT_PWM_GRANULARITY (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007638#define SOUTH_CHICKEN2 _MMIO(0xc2004)
Paulo Zanonidde86e22012-12-01 12:04:25 -02007639#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
7640#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03007641#define LPT_PWM_GRANULARITY (1<<5)
Paulo Zanonidde86e22012-12-01 12:04:25 -02007642#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07007643
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007644#define _FDI_RXA_CHICKEN 0xc200c
7645#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08007646#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
7647#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007648#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007649
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007650#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
Ville Syrjälä6481d5e2017-12-21 22:24:32 +02007651#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
Jesse Barnescd664072013-10-02 10:34:19 -07007652#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07007653#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07007654#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Rodrigo Vivi0a46ddd2017-08-30 21:52:23 -07007655#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02007656#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07007657
Zhenyu Wangb9055052009-06-05 15:38:38 +08007658/* CPU: FDI_TX */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007659#define _FDI_TXA_CTL 0x60100
7660#define _FDI_TXB_CTL 0x61100
7661#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007662#define FDI_TX_DISABLE (0<<31)
7663#define FDI_TX_ENABLE (1<<31)
7664#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
7665#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
7666#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
7667#define FDI_LINK_TRAIN_NONE (3<<28)
7668#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
7669#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
7670#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
7671#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
7672#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
7673#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
7674#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
7675#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007676/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
7677 SNB has different settings. */
7678/* SNB A-stepping */
7679#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7680#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7681#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7682#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7683/* SNB B-stepping */
7684#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
7685#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
7686#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
7687#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
7688#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007689#define FDI_DP_PORT_WIDTH_SHIFT 19
7690#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
7691#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007692#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007693/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08007694#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07007695
7696/* Ivybridge has different bits for lolz */
7697#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
7698#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
7699#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
7700#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
7701
Zhenyu Wangb9055052009-06-05 15:38:38 +08007702/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07007703#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07007704#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007705#define FDI_SCRAMBLING_ENABLE (0<<7)
7706#define FDI_SCRAMBLING_DISABLE (1<<7)
7707
7708/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007709#define _FDI_RXA_CTL 0xf000c
7710#define _FDI_RXB_CTL 0xf100c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007711#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007712#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007713/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07007714#define FDI_FS_ERRC_ENABLE (1<<27)
7715#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02007716#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007717#define FDI_8BPC (0<<16)
7718#define FDI_10BPC (1<<16)
7719#define FDI_6BPC (2<<16)
7720#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00007721#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007722#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
7723#define FDI_RX_PLL_ENABLE (1<<13)
7724#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
7725#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
7726#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
7727#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
7728#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01007729#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007730/* CPT */
7731#define FDI_AUTO_TRAINING (1<<10)
7732#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
7733#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
7734#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
7735#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
7736#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007737
Paulo Zanoni04945642012-11-01 21:00:59 -02007738#define _FDI_RXA_MISC 0xf0010
7739#define _FDI_RXB_MISC 0xf1010
7740#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
7741#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
7742#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
7743#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
7744#define FDI_RX_TP1_TO_TP2_48 (2<<20)
7745#define FDI_RX_TP1_TO_TP2_64 (3<<20)
7746#define FDI_RX_FDI_DELAY_90 (0x90<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007747#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
Paulo Zanoni04945642012-11-01 21:00:59 -02007748
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007749#define _FDI_RXA_TUSIZE1 0xf0030
7750#define _FDI_RXA_TUSIZE2 0xf0038
7751#define _FDI_RXB_TUSIZE1 0xf1030
7752#define _FDI_RXB_TUSIZE2 0xf1038
7753#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
7754#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007755
7756/* FDI_RX interrupt register format */
7757#define FDI_RX_INTER_LANE_ALIGN (1<<10)
7758#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
7759#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
7760#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
7761#define FDI_RX_FS_CODE_ERR (1<<6)
7762#define FDI_RX_FE_CODE_ERR (1<<5)
7763#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
7764#define FDI_RX_HDCP_LINK_FAIL (1<<3)
7765#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
7766#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
7767#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
7768
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007769#define _FDI_RXA_IIR 0xf0014
7770#define _FDI_RXA_IMR 0xf0018
7771#define _FDI_RXB_IIR 0xf1014
7772#define _FDI_RXB_IMR 0xf1018
7773#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
7774#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007775
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007776#define FDI_PLL_CTL_1 _MMIO(0xfe000)
7777#define FDI_PLL_CTL_2 _MMIO(0xfe004)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007778
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007779#define PCH_LVDS _MMIO(0xe1180)
Zhenyu Wangb9055052009-06-05 15:38:38 +08007780#define LVDS_DETECTED (1 << 1)
7781
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007782#define _PCH_DP_B 0xe4100
7783#define PCH_DP_B _MMIO(_PCH_DP_B)
Ville Syrjälä750a9512015-11-11 20:34:12 +02007784#define _PCH_DPB_AUX_CH_CTL 0xe4110
7785#define _PCH_DPB_AUX_CH_DATA1 0xe4114
7786#define _PCH_DPB_AUX_CH_DATA2 0xe4118
7787#define _PCH_DPB_AUX_CH_DATA3 0xe411c
7788#define _PCH_DPB_AUX_CH_DATA4 0xe4120
7789#define _PCH_DPB_AUX_CH_DATA5 0xe4124
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007790
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007791#define _PCH_DP_C 0xe4200
7792#define PCH_DP_C _MMIO(_PCH_DP_C)
Ville Syrjälä750a9512015-11-11 20:34:12 +02007793#define _PCH_DPC_AUX_CH_CTL 0xe4210
7794#define _PCH_DPC_AUX_CH_DATA1 0xe4214
7795#define _PCH_DPC_AUX_CH_DATA2 0xe4218
7796#define _PCH_DPC_AUX_CH_DATA3 0xe421c
7797#define _PCH_DPC_AUX_CH_DATA4 0xe4220
7798#define _PCH_DPC_AUX_CH_DATA5 0xe4224
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007799
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007800#define _PCH_DP_D 0xe4300
7801#define PCH_DP_D _MMIO(_PCH_DP_D)
Ville Syrjälä750a9512015-11-11 20:34:12 +02007802#define _PCH_DPD_AUX_CH_CTL 0xe4310
7803#define _PCH_DPD_AUX_CH_DATA1 0xe4314
7804#define _PCH_DPD_AUX_CH_DATA2 0xe4318
7805#define _PCH_DPD_AUX_CH_DATA3 0xe431c
7806#define _PCH_DPD_AUX_CH_DATA4 0xe4320
7807#define _PCH_DPD_AUX_CH_DATA5 0xe4324
7808
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007809#define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
7810#define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007811
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007812/* CPT */
7813#define PORT_TRANS_A_SEL_CPT 0
7814#define PORT_TRANS_B_SEL_CPT (1<<29)
7815#define PORT_TRANS_C_SEL_CPT (2<<29)
7816#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07007817#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02007818#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
7819#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03007820#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
7821#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007822
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007823#define _TRANS_DP_CTL_A 0xe0300
7824#define _TRANS_DP_CTL_B 0xe1300
7825#define _TRANS_DP_CTL_C 0xe2300
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007826#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007827#define TRANS_DP_OUTPUT_ENABLE (1<<31)
7828#define TRANS_DP_PORT_SEL_B (0<<29)
7829#define TRANS_DP_PORT_SEL_C (1<<29)
7830#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08007831#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007832#define TRANS_DP_PORT_SEL_MASK (3<<29)
Ville Syrjäläadc289d2015-05-05 17:17:30 +03007833#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007834#define TRANS_DP_AUDIO_ONLY (1<<26)
7835#define TRANS_DP_ENH_FRAMING (1<<18)
7836#define TRANS_DP_8BPC (0<<9)
7837#define TRANS_DP_10BPC (1<<9)
7838#define TRANS_DP_6BPC (2<<9)
7839#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08007840#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007841#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
7842#define TRANS_DP_VSYNC_ACTIVE_LOW 0
7843#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
7844#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01007845#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007846
7847/* SNB eDP training params */
7848/* SNB A-stepping */
7849#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7850#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7851#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7852#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7853/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08007854#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
7855#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
7856#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
7857#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
7858#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08007859#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
7860
Keith Packard1a2eb462011-11-16 16:26:07 -08007861/* IVB */
7862#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
7863#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
7864#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
7865#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
7866#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
7867#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03007868#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08007869
7870/* legacy values */
7871#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
7872#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
7873#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
7874#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
7875#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
7876
7877#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
7878
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007879#define VLV_PMWGICZ _MMIO(0x1300a4)
Imre Deak9e72b462014-05-05 15:13:55 +03007880
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05307881#define RC6_LOCATION _MMIO(0xD40)
7882#define RC6_CTX_IN_DRAM (1 << 0)
7883#define RC6_CTX_BASE _MMIO(0xD48)
7884#define RC6_CTX_BASE_MASK 0xFFFFFFF0
7885#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
7886#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
7887#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
7888#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
7889#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
7890#define IDLE_TIME_MASK 0xFFFFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007891#define FORCEWAKE _MMIO(0xA18C)
7892#define FORCEWAKE_VLV _MMIO(0x1300b0)
7893#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
7894#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
7895#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
7896#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
7897#define FORCEWAKE_ACK _MMIO(0x130090)
7898#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
Imre Deak981a5ae2014-04-14 20:24:22 +03007899#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
7900#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
7901#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
7902
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007903#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
Imre Deak981a5ae2014-04-14 20:24:22 +03007904#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
7905#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
7906#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
7907#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007908#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
7909#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
7910#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
7911#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
7912#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
7913#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
7914#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
Mika Kuoppala71306302017-11-02 11:48:36 +02007915#define FORCEWAKE_KERNEL BIT(0)
7916#define FORCEWAKE_USER BIT(1)
7917#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007918#define FORCEWAKE_MT_ACK _MMIO(0x130040)
7919#define ECOBUS _MMIO(0xa180)
Keith Packard8d715f02011-11-18 20:39:01 -08007920#define FORCEWAKE_MT_ENABLE (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007921#define VLV_SPAREG2H _MMIO(0xA194)
Akash Goelf2dd7572016-06-27 20:10:01 +05307922#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
7923#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
7924#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
Chris Wilson8fd26852010-12-08 18:40:43 +00007925
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007926#define GTFIFODBG _MMIO(0x120000)
Ville Syrjälä297b32e2016-04-13 21:09:30 +03007927#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
7928#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
Ville Syrjälä90f256b2013-11-14 01:59:59 +02007929#define GT_FIFO_SBDROPERR (1<<6)
7930#define GT_FIFO_BLOBDROPERR (1<<5)
7931#define GT_FIFO_SB_READ_ABORTERR (1<<4)
7932#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01007933#define GT_FIFO_OVFERR (1<<2)
7934#define GT_FIFO_IAWRERR (1<<1)
7935#define GT_FIFO_IARDERR (1<<0)
7936
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007937#define GTFIFOCTL _MMIO(0x120008)
Ville Syrjälä46520e22013-11-14 02:00:00 +02007938#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01007939#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Deepak Sa04f90a2015-04-16 08:51:28 +05307940#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
7941#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
Chris Wilson91355832011-03-04 19:22:40 +00007942
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007943#define HSW_IDICR _MMIO(0x9008)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07007944#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
Mika Kuoppala3accaf72016-04-13 17:26:43 +03007945#define HSW_EDRAM_CAP _MMIO(0x120010)
Damien Lespiau2db59d52015-02-03 14:25:14 +00007946#define EDRAM_ENABLED 0x1
Mika Kuoppalac02e85a2016-04-13 17:26:44 +03007947#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
7948#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
7949#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07007950
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007951#define GEN6_UCGCTL1 _MMIO(0x9400)
Mika Kuoppala8aeb7f62016-06-07 17:19:05 +03007952# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03007953# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02007954# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02007955# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02007956
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007957#define GEN6_UCGCTL2 _MMIO(0x9404)
Damien Lespiauf9fc42f2015-02-26 18:20:39 +00007958# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
Jesse Barnes0f846f82012-06-14 11:04:47 -07007959# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07007960# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08007961# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08007962# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08007963# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08007964
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007965#define GEN6_UCGCTL3 _MMIO(0x9408)
Robert Braggd7965152016-11-07 19:49:52 +00007966# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
Imre Deak9e72b462014-05-05 15:13:55 +03007967
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007968#define GEN7_UCGCTL4 _MMIO(0x940c)
Jesse Barnese3f33d42012-06-14 11:04:50 -07007969#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
Mika Kuoppalaeee8efb2016-06-07 17:18:53 +03007970#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
Jesse Barnese3f33d42012-06-14 11:04:50 -07007971
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007972#define GEN6_RCGCTL1 _MMIO(0x9410)
7973#define GEN6_RCGCTL2 _MMIO(0x9414)
7974#define GEN6_RSTCTL _MMIO(0x9420)
Imre Deak9e72b462014-05-05 15:13:55 +03007975
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007976#define GEN8_UCGCTL6 _MMIO(0x9430)
Damien Lespiau9253c2e2015-02-09 19:33:10 +00007977#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02007978#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
Ben Widawsky868434c2015-03-11 10:49:32 +02007979#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02007980
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007981#define GEN6_GFXPAUSE _MMIO(0xA000)
7982#define GEN6_RPNSWREQ _MMIO(0xA008)
Chris Wilson8fd26852010-12-08 18:40:43 +00007983#define GEN6_TURBO_DISABLE (1<<31)
7984#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03007985#define HSW_FREQUENCY(x) ((x)<<24)
Akash Goelde43ae92015-03-06 11:07:14 +05307986#define GEN9_FREQUENCY(x) ((x)<<23)
Chris Wilson8fd26852010-12-08 18:40:43 +00007987#define GEN6_OFFSET(x) ((x)<<19)
7988#define GEN6_AGGRESSIVE_TURBO (0<<15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007989#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
7990#define GEN6_RC_CONTROL _MMIO(0xA090)
Chris Wilson8fd26852010-12-08 18:40:43 +00007991#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
7992#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
7993#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
7994#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
7995#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08007996#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07007997#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00007998#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
7999#define GEN6_RC_CTL_HW_ENABLE (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008000#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8001#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8002#define GEN6_RPSTAT1 _MMIO(0xA01C)
Jesse Barnesccab5c82011-01-18 15:49:25 -08008003#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08008004#define HSW_CAGF_SHIFT 7
Akash Goelde43ae92015-03-06 11:07:14 +05308005#define GEN9_CAGF_SHIFT 23
Jesse Barnesccab5c82011-01-18 15:49:25 -08008006#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08008007#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Akash Goelde43ae92015-03-06 11:07:14 +05308008#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008009#define GEN6_RP_CONTROL _MMIO(0xA024)
Chris Wilson8fd26852010-12-08 18:40:43 +00008010#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08008011#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
8012#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
8013#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
8014#define GEN6_RP_MEDIA_HW_MODE (1<<9)
8015#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00008016#define GEN6_RP_MEDIA_IS_GFX (1<<8)
8017#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08008018#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
8019#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
8020#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01008021#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08008022#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008023#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8024#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8025#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
Chris Wilson7466c292016-08-15 09:49:33 +01008026#define GEN6_RP_EI_MASK 0xffffff
8027#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008028#define GEN6_RP_CUR_UP _MMIO(0xA054)
Chris Wilson7466c292016-08-15 09:49:33 +01008029#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008030#define GEN6_RP_PREV_UP _MMIO(0xA058)
8031#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
Chris Wilson7466c292016-08-15 09:49:33 +01008032#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008033#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8034#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8035#define GEN6_RP_UP_EI _MMIO(0xA068)
8036#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8037#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8038#define GEN6_RPDEUHWTC _MMIO(0xA080)
8039#define GEN6_RPDEUC _MMIO(0xA084)
8040#define GEN6_RPDEUCSW _MMIO(0xA088)
8041#define GEN6_RC_STATE _MMIO(0xA094)
Imre Deakfc619842016-06-29 19:13:55 +03008042#define RC_SW_TARGET_STATE_SHIFT 16
8043#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008044#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8045#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8046#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
Rodrigo Vivi0aab2012017-10-23 15:46:12 -07008047#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008048#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8049#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8050#define GEN6_RC_SLEEP _MMIO(0xA0B0)
8051#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8052#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8053#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8054#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8055#define VLV_RCEDATA _MMIO(0xA0BC)
8056#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8057#define GEN6_PMINTRMSK _MMIO(0xA168)
Chris Wilson655d49e2017-03-12 13:27:45 +00008058#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31)
Sagar Arun Kamble9735b042017-03-07 10:22:35 +05308059#define ARAT_EXPIRED_INTRMSK (1<<9)
Imre Deakfc619842016-06-29 19:13:55 +03008060#define GEN8_MISC_CTRL0 _MMIO(0xA180)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008061#define VLV_PWRDWNUPCTL _MMIO(0xA294)
8062#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8063#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8064#define GEN9_PG_ENABLE _MMIO(0xA210)
Sagar Kamblea4104c52015-04-10 14:11:29 +05308065#define GEN9_RENDER_PG_ENABLE (1<<0)
8066#define GEN9_MEDIA_PG_ENABLE (1<<1)
Imre Deakfc619842016-06-29 19:13:55 +03008067#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8068#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8069#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
Chris Wilson8fd26852010-12-08 18:40:43 +00008070
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008071#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
Gaurav K Singha9da9bc2014-12-05 14:13:41 +05308072#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8073#define PIXEL_OVERLAP_CNT_SHIFT 30
8074
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008075#define GEN6_PMISR _MMIO(0x44020)
8076#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8077#define GEN6_PMIIR _MMIO(0x44028)
8078#define GEN6_PMIER _MMIO(0x4402C)
Chris Wilson8fd26852010-12-08 18:40:43 +00008079#define GEN6_PM_MBOX_EVENT (1<<25)
8080#define GEN6_PM_THERMAL_EVENT (1<<24)
8081#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
8082#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
8083#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
8084#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
8085#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07008086#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07008087 GEN6_PM_RP_DOWN_THRESHOLD | \
8088 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00008089
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008090#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03008091#define GEN7_GT_SCRATCH_REG_NUM 8
8092
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008093#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
Deepak S76c3552f2014-01-30 23:08:16 +05308094#define VLV_GFX_CLK_STATUS_BIT (1<<3)
8095#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
8096
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008097#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8098#define VLV_COUNTER_CONTROL _MMIO(0x138104)
Jesse Barnes49798eb2013-09-26 17:55:57 -07008099#define VLV_COUNT_RANGE_HIGH (1<<15)
Deepak S31685c22014-07-03 17:33:01 -04008100#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
8101#define VLV_RENDER_RC0_COUNT_EN (1<<4)
Jesse Barnes49798eb2013-09-26 17:55:57 -07008102#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
8103#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008104#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8105#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8106#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
Imre Deak9cc19be2014-04-14 20:24:24 +03008107
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008108#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8109#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8110#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8111#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
Ben Widawskycce66a22012-03-27 18:59:38 -07008112
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008113#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
Chris Wilson8fd26852010-12-08 18:40:43 +00008114#define GEN6_PCODE_READY (1<<31)
Lyude87660502016-08-17 15:55:53 -04008115#define GEN6_PCODE_ERROR_MASK 0xFF
8116#define GEN6_PCODE_SUCCESS 0x0
8117#define GEN6_PCODE_ILLEGAL_CMD 0x1
8118#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8119#define GEN6_PCODE_TIMEOUT 0x3
8120#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8121#define GEN7_PCODE_TIMEOUT 0x2
8122#define GEN7_PCODE_ILLEGAL_DATA 0x3
8123#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
Ville Syrjälä3e8ddd92017-09-12 18:34:10 +03008124#define GEN6_PCODE_WRITE_RC6VIDS 0x4
8125#define GEN6_PCODE_READ_RC6VIDS 0x5
Damien Lespiau9043ae02015-04-30 16:39:18 +01008126#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8127#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03008128#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
Damien Lespiau57520bc2015-04-30 16:39:19 +01008129#define GEN9_PCODE_READ_MEM_LATENCY 0x6
8130#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8131#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8132#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8133#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01008134#define SKL_PCODE_CDCLK_CONTROL 0x7
8135#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8136#define SKL_CDCLK_READY_FOR_CHANGE 0x1
Damien Lespiau9043ae02015-04-30 16:39:18 +01008137#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8138#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8139#define GEN6_READ_OC_PARAMS 0xc
Paulo Zanoni515b2392013-09-10 19:36:37 -03008140#define GEN6_PCODE_READ_D_COMP 0x10
8141#define GEN6_PCODE_WRITE_D_COMP 0x11
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308142#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
Ben Widawsky2a114cc2013-11-02 21:07:47 -07008143#define DISPLAY_IPS_CONTROL 0x19
Ville Syrjälä61843f02017-09-12 18:34:11 +03008144 /* See also IPS_CTL */
8145#define IPS_PCODE_CONTROL (1 << 30)
Ville Syrjälä3e8ddd92017-09-12 18:34:10 +03008146#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
Lyude656d1b82016-08-17 15:55:54 -04008147#define GEN9_PCODE_SAGV_CONTROL 0x21
8148#define GEN9_SAGV_DISABLE 0x0
8149#define GEN9_SAGV_IS_DISABLED 0x1
8150#define GEN9_SAGV_ENABLE 0x3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008151#define GEN6_PCODE_DATA _MMIO(0x138128)
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07008152#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01008153#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008154#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
Chris Wilson8fd26852010-12-08 18:40:43 +00008155
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008156#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
Ben Widawsky4d855292011-12-12 19:34:16 -08008157#define GEN6_CORE_CPD_STATE_MASK (7<<4)
8158#define GEN6_RCn_MASK 7
8159#define GEN6_RC0 0
8160#define GEN6_RC3 2
8161#define GEN6_RC6 3
8162#define GEN6_RC7 4
8163
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008164#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02008165#define GEN8_LSLICESTAT_MASK 0x7
8166
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008167#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8168#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
Jeff McGee5575f032015-02-27 10:22:32 -08008169#define CHV_SS_PG_ENABLE (1<<1)
8170#define CHV_EU08_PG_ENABLE (1<<9)
8171#define CHV_EU19_PG_ENABLE (1<<17)
8172#define CHV_EU210_PG_ENABLE (1<<25)
8173
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008174#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8175#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
Jeff McGee5575f032015-02-27 10:22:32 -08008176#define CHV_EU311_PG_ENABLE (1<<1)
8177
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008178#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07008179#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8180 ((slice) % 3) * 0x4)
Jeff McGee7f992ab2015-02-13 10:27:55 -06008181#define GEN9_PGCTL_SLICE_ACK (1 << 0)
Jeff McGee1c046bc2015-04-03 18:13:18 -07008182#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07008183#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
Jeff McGee7f992ab2015-02-13 10:27:55 -06008184
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008185#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07008186#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8187 ((slice) % 3) * 0x8)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008188#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07008189#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8190 ((slice) % 3) * 0x8)
Jeff McGee7f992ab2015-02-13 10:27:55 -06008191#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8192#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8193#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8194#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8195#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8196#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8197#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8198#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8199
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008200#define GEN7_MISCCPCTL _MMIO(0x9424)
Alex Dai33a732f2015-08-12 15:43:36 +01008201#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
8202#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
8203#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
Arun Siluvery5b88aba2015-09-08 10:31:49 +01008204#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
Ben Widawskye3689192012-05-25 16:56:22 -07008205
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008206#define GEN8_GARBCNTL _MMIO(0xB004)
Arun Siluvery245d9662015-08-03 20:24:56 +01008207#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
8208
Ben Widawskye3689192012-05-25 16:56:22 -07008209/* IVYBRIDGE DPF */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008210#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07008211#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
8212#define GEN7_PARITY_ERROR_VALID (1<<13)
8213#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
8214#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
8215#define GEN7_PARITY_ERROR_ROW(reg) \
8216 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8217#define GEN7_PARITY_ERROR_BANK(reg) \
8218 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8219#define GEN7_PARITY_ERROR_SUBBANK(reg) \
8220 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8221#define GEN7_L3CDERRST1_ENABLE (1<<7)
8222
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008223#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
Ben Widawskyb9524a12012-05-25 16:56:24 -07008224#define GEN7_L3LOG_SIZE 0x80
8225
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008226#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8227#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
Jesse Barnes12f33822012-10-25 12:15:45 -07008228#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07008229#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Nick Hoath983b4b92015-04-10 13:12:25 +01008230#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
Jesse Barnes12f33822012-10-25 12:15:45 -07008231#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
8232
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008233#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00008234#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
Damien Lespiaue2db7072015-02-09 19:33:21 +00008235#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00008236
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008237#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
Tim Gore950b2aa2016-03-16 16:13:46 +00008238#define FLOW_CONTROL_ENABLE (1<<15)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08008239#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08008240#define STALL_DOP_GATING_DISABLE (1<<5)
Rodrigo Viviaa9f4c42017-09-06 15:03:25 -07008241#define THROTTLE_12_5 (7<<2)
Rafael Antognollia2b16582017-12-15 16:11:17 -08008242#define DISABLE_EARLY_EOT (1<<1)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08008243
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008244#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8245#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
Jesse Barnes8ab43972012-10-25 12:15:42 -07008246#define DOP_CLOCK_GATING_DISABLE (1<<0)
Oscar Mateo2cbecff2017-08-23 12:56:31 -07008247#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
Jesse Barnes8ab43972012-10-25 12:15:42 -07008248
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008249#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07008250#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8251
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008252#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
Robert Beckett6b6d5622015-09-08 10:31:52 +01008253#define GEN8_ST_PO_DISABLE (1<<13)
8254
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008255#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
Kenneth Graunke94411592014-12-31 16:23:00 -08008256#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
Ben Widawskyfd392b62013-11-04 22:52:39 -08008257#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Nick Hoath84241712015-02-05 10:47:20 +00008258#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
Rodrigo Vivi392572f2017-08-29 16:07:23 -07008259#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
Ben Widawskybf663472013-11-02 21:07:57 -07008260#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08008261
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008262#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
Ville Syrjälä93564042017-08-24 22:10:51 +03008263#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1<<8)
Nick Hoathcac23df2015-02-05 10:47:22 +00008264#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
Tim Gorebfd8ad42016-04-19 15:45:52 +01008265#define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
Nick Hoathcac23df2015-02-05 10:47:22 +00008266
Jani Nikulac46f1112014-10-27 16:26:52 +02008267/* Audio */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008268#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
Jani Nikulac46f1112014-10-27 16:26:52 +02008269#define INTEL_AUDIO_DEVCL 0x808629FB
8270#define INTEL_AUDIO_DEVBLC 0x80862801
8271#define INTEL_AUDIO_DEVCTG 0x80862802
Wu Fengguange0dac652011-09-05 14:25:34 +08008272
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008273#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
Jani Nikulac46f1112014-10-27 16:26:52 +02008274#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8275#define G4X_ELDV_DEVCTG (1 << 14)
8276#define G4X_ELD_ADDR_MASK (0xf << 5)
8277#define G4X_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008278#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
Wu Fengguange0dac652011-09-05 14:25:34 +08008279
Jani Nikulac46f1112014-10-27 16:26:52 +02008280#define _IBX_HDMIW_HDMIEDID_A 0xE2050
8281#define _IBX_HDMIW_HDMIEDID_B 0xE2150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008282#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8283 _IBX_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008284#define _IBX_AUD_CNTL_ST_A 0xE20B4
8285#define _IBX_AUD_CNTL_ST_B 0xE21B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008286#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8287 _IBX_AUD_CNTL_ST_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008288#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8289#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8290#define IBX_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008291#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
Jani Nikula82910ac2014-10-27 16:26:59 +02008292#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8293#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
Wu Fengguange0dac652011-09-05 14:25:34 +08008294
Jani Nikulac46f1112014-10-27 16:26:52 +02008295#define _CPT_HDMIW_HDMIEDID_A 0xE5050
8296#define _CPT_HDMIW_HDMIEDID_B 0xE5150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008297#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008298#define _CPT_AUD_CNTL_ST_A 0xE50B4
8299#define _CPT_AUD_CNTL_ST_B 0xE51B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008300#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8301#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
Wu Fengguange0dac652011-09-05 14:25:34 +08008302
Jani Nikulac46f1112014-10-27 16:26:52 +02008303#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8304#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008305#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008306#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8307#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008308#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8309#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04008310
Eric Anholtae662d32012-01-03 09:23:29 -08008311/* These are the 4 32-bit write offset registers for each stream
8312 * output buffer. It determines the offset from the
8313 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8314 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008315#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
Eric Anholtae662d32012-01-03 09:23:29 -08008316
Jani Nikulac46f1112014-10-27 16:26:52 +02008317#define _IBX_AUD_CONFIG_A 0xe2000
8318#define _IBX_AUD_CONFIG_B 0xe2100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008319#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008320#define _CPT_AUD_CONFIG_A 0xe5000
8321#define _CPT_AUD_CONFIG_B 0xe5100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008322#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02008323#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8324#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008325#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04008326
Wu Fengguangb6daa022012-01-06 14:41:31 -06008327#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8328#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8329#define AUD_CONFIG_UPPER_N_SHIFT 20
Jani Nikulac46f1112014-10-27 16:26:52 +02008330#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
Wu Fengguangb6daa022012-01-06 14:41:31 -06008331#define AUD_CONFIG_LOWER_N_SHIFT 4
Jani Nikulac46f1112014-10-27 16:26:52 +02008332#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
Jani Nikula25613892016-10-10 18:04:06 +03008333#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8334#define AUD_CONFIG_N(n) \
8335 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8336 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
Wu Fengguangb6daa022012-01-06 14:41:31 -06008337#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03008338#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8339#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8340#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8341#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8342#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8343#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8344#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8345#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8346#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8347#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8348#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06008349#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8350
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008351/* HSW Audio */
Jani Nikulac46f1112014-10-27 16:26:52 +02008352#define _HSW_AUD_CONFIG_A 0x65000
8353#define _HSW_AUD_CONFIG_B 0x65100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008354#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008355
Jani Nikulac46f1112014-10-27 16:26:52 +02008356#define _HSW_AUD_MISC_CTRL_A 0x65010
8357#define _HSW_AUD_MISC_CTRL_B 0x65110
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008358#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008359
Libin Yang6014ac12016-10-25 17:54:18 +03008360#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8361#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8362#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8363#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8364#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8365#define AUD_CONFIG_M_MASK 0xfffff
8366
Jani Nikulac46f1112014-10-27 16:26:52 +02008367#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8368#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008369#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008370
8371/* Audio Digital Converter */
Jani Nikulac46f1112014-10-27 16:26:52 +02008372#define _HSW_AUD_DIG_CNVT_1 0x65080
8373#define _HSW_AUD_DIG_CNVT_2 0x65180
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008374#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
Jani Nikulac46f1112014-10-27 16:26:52 +02008375#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008376
Jani Nikulac46f1112014-10-27 16:26:52 +02008377#define _HSW_AUD_EDID_DATA_A 0x65050
8378#define _HSW_AUD_EDID_DATA_B 0x65150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008379#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008380
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008381#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8382#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
Jani Nikula82910ac2014-10-27 16:26:59 +02008383#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8384#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8385#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8386#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08008387
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008388#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
Lu, Han632f3ab2015-05-05 09:05:47 +08008389#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8390
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03008391/* HSW Power Wells */
Imre Deak9c3a16c2017-08-14 18:15:30 +03008392#define _HSW_PWR_WELL_CTL1 0x45400
8393#define _HSW_PWR_WELL_CTL2 0x45404
8394#define _HSW_PWR_WELL_CTL3 0x45408
8395#define _HSW_PWR_WELL_CTL4 0x4540C
8396
8397/*
8398 * Each power well control register contains up to 16 (request, status) HW
8399 * flag tuples. The register index and HW flag shift is determined by the
8400 * power well ID (see i915_power_well_id). There are 4 possible sources of
8401 * power well requests each source having its own set of control registers:
8402 * BIOS, DRIVER, KVMR, DEBUG.
8403 */
8404#define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8405#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8406/* TODO: Add all PWR_WELL_CTL registers below for new platforms */
8407#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8408 _HSW_PWR_WELL_CTL1))
8409#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8410 _HSW_PWR_WELL_CTL2))
8411#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8412#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8413 _HSW_PWR_WELL_CTL4))
8414
Imre Deak1af474f2017-07-06 17:40:34 +03008415#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8416#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008417#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03008418#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
8419#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008420#define HSW_PWR_WELL_FORCE_ON (1<<19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008421#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03008422
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00008423/* SKL Fuse Status */
Imre Deakb2891eb2017-07-11 23:42:35 +03008424enum skl_power_gate {
8425 SKL_PG0,
8426 SKL_PG1,
8427 SKL_PG2,
8428};
8429
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008430#define SKL_FUSE_STATUS _MMIO(0x42000)
Imre Deakb2891eb2017-07-11 23:42:35 +03008431#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
8432/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8433#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8434#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00008435
Rodrigo Vivic559c2a2018-01-23 13:52:45 -08008436#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
Lucas De Marchiddd39e42017-11-28 14:05:53 -08008437#define _CNL_AUX_ANAOVRD1_B 0x162250
8438#define _CNL_AUX_ANAOVRD1_C 0x162210
8439#define _CNL_AUX_ANAOVRD1_D 0x1622D0
Rodrigo Vivib1ae6a82018-01-29 15:22:16 -08008440#define _CNL_AUX_ANAOVRD1_F 0x162A90
Lucas De Marchiddd39e42017-11-28 14:05:53 -08008441#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
8442 _CNL_AUX_ANAOVRD1_B, \
8443 _CNL_AUX_ANAOVRD1_C, \
Rodrigo Vivib1ae6a82018-01-29 15:22:16 -08008444 _CNL_AUX_ANAOVRD1_D, \
8445 _CNL_AUX_ANAOVRD1_F))
Lucas De Marchiddd39e42017-11-28 14:05:53 -08008446#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
8447#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
8448
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03008449/* Per-pipe DDI Function Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008450#define _TRANS_DDI_FUNC_CTL_A 0x60400
8451#define _TRANS_DDI_FUNC_CTL_B 0x61400
8452#define _TRANS_DDI_FUNC_CTL_C 0x62400
8453#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008454#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02008455
Paulo Zanoniad80a812012-10-24 16:06:19 -02008456#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03008457/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02008458#define TRANS_DDI_PORT_MASK (7<<28)
Daniel Vetter26804af2014-06-25 22:01:55 +03008459#define TRANS_DDI_PORT_SHIFT 28
Paulo Zanoniad80a812012-10-24 16:06:19 -02008460#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
8461#define TRANS_DDI_PORT_NONE (0<<28)
8462#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
8463#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
8464#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
8465#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
8466#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
8467#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
8468#define TRANS_DDI_BPC_MASK (7<<20)
8469#define TRANS_DDI_BPC_8 (0<<20)
8470#define TRANS_DDI_BPC_10 (1<<20)
8471#define TRANS_DDI_BPC_6 (2<<20)
8472#define TRANS_DDI_BPC_12 (3<<20)
8473#define TRANS_DDI_PVSYNC (1<<17)
8474#define TRANS_DDI_PHSYNC (1<<16)
8475#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
8476#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
8477#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
8478#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
8479#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
Dave Airlie01b887c2014-05-02 11:17:41 +10008480#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
Shashank Sharma15953632017-03-13 16:54:03 +05308481#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
8482#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
Paulo Zanoniad80a812012-10-24 16:06:19 -02008483#define TRANS_DDI_BFI_ENABLE (1<<4)
Shashank Sharma15953632017-03-13 16:54:03 +05308484#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4)
8485#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
8486#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
8487 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
8488 | TRANS_DDI_HDMI_SCRAMBLING)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03008489
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03008490/* DisplayPort Transport Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008491#define _DP_TP_CTL_A 0x64040
8492#define _DP_TP_CTL_B 0x64140
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008493#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008494#define DP_TP_CTL_ENABLE (1<<31)
8495#define DP_TP_CTL_MODE_SST (0<<27)
8496#define DP_TP_CTL_MODE_MST (1<<27)
Dave Airlie01b887c2014-05-02 11:17:41 +10008497#define DP_TP_CTL_FORCE_ACT (1<<25)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03008498#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008499#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03008500#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
8501#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
8502#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03008503#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
8504#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008505#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03008506#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03008507
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03008508/* DisplayPort Transport Status */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008509#define _DP_TP_STATUS_A 0x64044
8510#define _DP_TP_STATUS_B 0x64144
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008511#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
Dave Airlie01b887c2014-05-02 11:17:41 +10008512#define DP_TP_STATUS_IDLE_DONE (1<<25)
8513#define DP_TP_STATUS_ACT_SENT (1<<24)
8514#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
8515#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
8516#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
8517#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
8518#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03008519
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03008520/* DDI Buffer Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008521#define _DDI_BUF_CTL_A 0x64000
8522#define _DDI_BUF_CTL_B 0x64100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008523#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008524#define DDI_BUF_CTL_ENABLE (1<<31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05308525#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008526#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00008527#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008528#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02008529#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02008530#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03008531#define DDI_PORT_WIDTH_MASK (7 << 1)
8532#define DDI_PORT_WIDTH_SHIFT 1
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03008533#define DDI_INIT_DISPLAY_DETECTED (1<<0)
8534
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03008535/* DDI Buffer Translations */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008536#define _DDI_BUF_TRANS_A 0x64E00
8537#define _DDI_BUF_TRANS_B 0x64E60
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008538#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
Ville Syrjäläc110ae62016-07-12 15:59:29 +03008539#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008540#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03008541
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03008542/* Sideband Interface (SBI) is programmed indirectly, via
8543 * SBI_ADDR, which contains the register offset; and SBI_DATA,
8544 * which contains the payload */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008545#define SBI_ADDR _MMIO(0xC6000)
8546#define SBI_DATA _MMIO(0xC6004)
8547#define SBI_CTL_STAT _MMIO(0xC6008)
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02008548#define SBI_CTL_DEST_ICLK (0x0<<16)
8549#define SBI_CTL_DEST_MPHY (0x1<<16)
8550#define SBI_CTL_OP_IORD (0x2<<8)
8551#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03008552#define SBI_CTL_OP_CRRD (0x6<<8)
8553#define SBI_CTL_OP_CRWR (0x7<<8)
8554#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008555#define SBI_RESPONSE_SUCCESS (0x0<<1)
8556#define SBI_BUSY (0x1<<0)
8557#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03008558
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008559/* SBI offsets */
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008560#define SBI_SSCDIVINTPHASE 0x0200
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008561#define SBI_SSCDIVINTPHASE6 0x0600
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02008562#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
8563#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008564#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02008565#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
8566#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008567#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008568#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008569#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008570#define SBI_SSCDITHPHASE 0x0204
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008571#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008572#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02008573#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008574#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008575#define SBI_SSCAUXDIV6 0x0610
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02008576#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
8577#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008578#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008579#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008580#define SBI_GEN0 0x1f00
8581#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03008582
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03008583/* LPT PIXCLK_GATE */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008584#define PIXCLK_GATE _MMIO(0xC6020)
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03008585#define PIXCLK_GATE_UNGATE (1<<0)
8586#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03008587
Eugeni Dodonove93ea062012-03-29 12:32:32 -03008588/* SPLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008589#define SPLL_CTL _MMIO(0x46020)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03008590#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01008591#define SPLL_PLL_SSC (1<<28)
8592#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08008593#define SPLL_PLL_LCPLL (3<<28)
8594#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008595#define SPLL_PLL_FREQ_810MHz (0<<26)
8596#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08008597#define SPLL_PLL_FREQ_2700MHz (2<<26)
8598#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03008599
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03008600/* WRPLL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008601#define _WRPLL_CTL1 0x46040
8602#define _WRPLL_CTL2 0x46060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008603#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008604#define WRPLL_PLL_ENABLE (1<<31)
Daniel Vetter114fe482014-06-25 22:01:48 +03008605#define WRPLL_PLL_SSC (1<<28)
8606#define WRPLL_PLL_NON_SSC (2<<28)
8607#define WRPLL_PLL_LCPLL (3<<28)
8608#define WRPLL_PLL_REF_MASK (3<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03008609/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008610#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08008611#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008612#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08008613#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
8614#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008615#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08008616#define WRPLL_DIVIDER_FB_SHIFT 16
8617#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03008618
Eugeni Dodonovfec91812012-03-29 12:32:33 -03008619/* Port clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008620#define _PORT_CLK_SEL_A 0x46100
8621#define _PORT_CLK_SEL_B 0x46104
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008622#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03008623#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
8624#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
8625#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008626#define PORT_CLK_SEL_SPLL (3<<29)
Daniel Vetter716c2e52014-06-25 22:02:02 +03008627#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03008628#define PORT_CLK_SEL_WRPLL1 (4<<29)
8629#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008630#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08008631#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03008632
Paulo Zanonibb523fc2012-10-23 18:29:56 -02008633/* Transcoder clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008634#define _TRANS_CLK_SEL_A 0x46140
8635#define _TRANS_CLK_SEL_B 0x46144
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008636#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
Paulo Zanonibb523fc2012-10-23 18:29:56 -02008637/* For each transcoder, we need to select the corresponding port clock */
8638#define TRANS_CLK_SEL_DISABLED (0x0<<29)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008639#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03008640
Ville Syrjälä7f1052a2016-04-26 19:46:32 +03008641#define CDCLK_FREQ _MMIO(0x46200)
8642
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008643#define _TRANSA_MSA_MISC 0x60410
8644#define _TRANSB_MSA_MISC 0x61410
8645#define _TRANSC_MSA_MISC 0x62410
8646#define _TRANS_EDP_MSA_MISC 0x6f410
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008647#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02008648
Paulo Zanonic9809792012-10-23 18:30:00 -02008649#define TRANS_MSA_SYNC_CLK (1<<0)
8650#define TRANS_MSA_6_BPC (0<<5)
8651#define TRANS_MSA_8_BPC (1<<5)
8652#define TRANS_MSA_10_BPC (2<<5)
8653#define TRANS_MSA_12_BPC (3<<5)
8654#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03008655
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03008656/* LCPLL Control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008657#define LCPLL_CTL _MMIO(0x130040)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03008658#define LCPLL_PLL_DISABLE (1<<31)
8659#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008660#define LCPLL_CLK_FREQ_MASK (3<<26)
8661#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07008662#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
8663#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
8664#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008665#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03008666#define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03008667#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008668#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008669#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008670#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
8671
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008672/*
8673 * SKL Clocks
8674 */
8675
8676/* CDCLK_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008677#define CDCLK_CTL _MMIO(0x46000)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008678#define CDCLK_FREQ_SEL_MASK (3<<26)
8679#define CDCLK_FREQ_450_432 (0<<26)
8680#define CDCLK_FREQ_540 (1<<26)
8681#define CDCLK_FREQ_337_308 (2<<26)
8682#define CDCLK_FREQ_675_617 (3<<26)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308683#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
8684#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
8685#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
8686#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
8687#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
Ville Syrjälä7fe62752016-05-11 22:44:51 +03008688#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
Lucas De Marchi53421c22017-12-04 15:22:10 -08008689#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
Ville Syrjälä7fe62752016-05-11 22:44:51 +03008690#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308691#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
Ville Syrjälä7fe62752016-05-11 22:44:51 +03008692#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308693
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008694/* LCPLL_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008695#define LCPLL1_CTL _MMIO(0x46010)
8696#define LCPLL2_CTL _MMIO(0x46014)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008697#define LCPLL_PLL_ENABLE (1<<31)
8698
8699/* DPLL control1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008700#define DPLL_CTRL1 _MMIO(0x6C058)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008701#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
8702#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
Damien Lespiau71cd8422015-04-30 16:39:17 +01008703#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
8704#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
8705#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008706#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
Damien Lespiau71cd8422015-04-30 16:39:17 +01008707#define DPLL_CTRL1_LINK_RATE_2700 0
8708#define DPLL_CTRL1_LINK_RATE_1350 1
8709#define DPLL_CTRL1_LINK_RATE_810 2
8710#define DPLL_CTRL1_LINK_RATE_1620 3
8711#define DPLL_CTRL1_LINK_RATE_1080 4
8712#define DPLL_CTRL1_LINK_RATE_2160 5
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008713
8714/* DPLL control2 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008715#define DPLL_CTRL2 _MMIO(0x6C05C)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008716#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008717#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
Satheeshakrishna M540e7322014-11-13 14:55:16 +00008718#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008719#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008720#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
8721
8722/* DPLL Status */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008723#define DPLL_STATUS _MMIO(0x6C060)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008724#define DPLL_LOCK(id) (1<<((id)*8))
8725
8726/* DPLL cfg */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008727#define _DPLL1_CFGCR1 0x6C040
8728#define _DPLL2_CFGCR1 0x6C048
8729#define _DPLL3_CFGCR1 0x6C050
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008730#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
8731#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008732#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008733#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
8734
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008735#define _DPLL1_CFGCR2 0x6C044
8736#define _DPLL2_CFGCR2 0x6C04C
8737#define _DPLL3_CFGCR2 0x6C054
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008738#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008739#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
8740#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008741#define DPLL_CFGCR2_KDIV_MASK (3<<5)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008742#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008743#define DPLL_CFGCR2_KDIV_5 (0<<5)
8744#define DPLL_CFGCR2_KDIV_2 (1<<5)
8745#define DPLL_CFGCR2_KDIV_3 (2<<5)
8746#define DPLL_CFGCR2_KDIV_1 (3<<5)
8747#define DPLL_CFGCR2_PDIV_MASK (7<<2)
Ville Syrjälä68d97532015-09-18 20:03:39 +03008748#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00008749#define DPLL_CFGCR2_PDIV_1 (0<<2)
8750#define DPLL_CFGCR2_PDIV_2 (1<<2)
8751#define DPLL_CFGCR2_PDIV_3 (2<<2)
8752#define DPLL_CFGCR2_PDIV_7 (4<<2)
8753#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
8754
Lyudeda3b8912016-02-04 10:43:21 -05008755#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008756#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
Satheeshakrishna M540e7322014-11-13 14:55:16 +00008757
Rodrigo Vivi555e38d2017-06-09 15:26:02 -07008758/*
8759 * CNL Clocks
8760 */
8761#define DPCLKA_CFGCR0 _MMIO(0x6C200)
8762#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
8763#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
8764#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
8765#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
8766
Rodrigo Vivia927c922017-06-09 15:26:04 -07008767/* CNL PLL */
8768#define DPLL0_ENABLE 0x46010
8769#define DPLL1_ENABLE 0x46014
8770#define PLL_ENABLE (1 << 31)
8771#define PLL_LOCK (1 << 30)
8772#define PLL_POWER_ENABLE (1 << 27)
8773#define PLL_POWER_STATE (1 << 26)
8774#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
8775
8776#define _CNL_DPLL0_CFGCR0 0x6C000
8777#define _CNL_DPLL1_CFGCR0 0x6C080
8778#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
8779#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
8780#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
8781#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
8782#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
8783#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
8784#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
8785#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
8786#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
8787#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
8788#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
8789#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
Manasi Navare442aa272017-09-14 11:31:39 -07008790#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
Rodrigo Vivia927c922017-06-09 15:26:04 -07008791#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
8792#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
8793#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
8794
8795#define _CNL_DPLL0_CFGCR1 0x6C004
8796#define _CNL_DPLL1_CFGCR1 0x6C084
8797#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
Rodrigo Vivia9701a82017-07-06 13:52:01 -07008798#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
Rodrigo Vivia927c922017-06-09 15:26:04 -07008799#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
8800#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
8801#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
8802#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
8803#define DPLL_CFGCR1_KDIV_1 (1 << 6)
8804#define DPLL_CFGCR1_KDIV_2 (2 << 6)
8805#define DPLL_CFGCR1_KDIV_4 (4 << 6)
8806#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
8807#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
8808#define DPLL_CFGCR1_PDIV_2 (1 << 2)
8809#define DPLL_CFGCR1_PDIV_3 (2 << 2)
8810#define DPLL_CFGCR1_PDIV_5 (4 << 2)
8811#define DPLL_CFGCR1_PDIV_7 (8 << 2)
8812#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
8813#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
8814
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308815/* BXT display engine PLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008816#define BXT_DE_PLL_CTL _MMIO(0x6d000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308817#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
8818#define BXT_DE_PLL_RATIO_MASK 0xff
8819
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008820#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308821#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
8822#define BXT_DE_PLL_LOCK (1 << 30)
Ville Syrjälä945f2672017-06-09 15:25:58 -07008823#define CNL_CDCLK_PLL_RATIO(x) (x)
8824#define CNL_CDCLK_PLL_RATIO_MASK 0xff
Vandana Kannanf8437dd12014-11-24 13:37:39 +05308825
A.Sunil Kamath664326f2014-11-24 13:37:44 +05308826/* GEN9 DC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008827#define DC_STATE_EN _MMIO(0x45504)
Imre Deak13ae3a02015-11-04 19:24:16 +02008828#define DC_STATE_DISABLE 0
A.Sunil Kamath664326f2014-11-24 13:37:44 +05308829#define DC_STATE_EN_UPTO_DC5 (1<<0)
8830#define DC_STATE_EN_DC9 (1<<3)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +05308831#define DC_STATE_EN_UPTO_DC6 (2<<0)
8832#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
8833
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008834#define DC_STATE_DEBUG _MMIO(0x45520)
Mika Kuoppala5b076882016-02-19 12:26:04 +02008835#define DC_STATE_DEBUG_MASK_CORES (1<<0)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +05308836#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
8837
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03008838/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
8839 * since on HSW we can't write to it using I915_WRITE. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008840#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
8841#define D_COMP_BDW _MMIO(0x138144)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03008842#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
8843#define D_COMP_COMP_FORCE (1<<8)
8844#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03008845
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03008846/* Pipe WM_LINETIME - watermark line time */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02008847#define _PIPE_WM_LINETIME_A 0x45270
8848#define _PIPE_WM_LINETIME_B 0x45274
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008849#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008850#define PIPE_WM_LINETIME_MASK (0x1ff)
8851#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03008852#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03008853#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03008854
8855/* SFUSE_STRAP */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008856#define SFUSE_STRAP _MMIO(0xc2014)
Damien Lespiau658ac4c2014-02-10 17:19:45 +00008857#define SFUSE_STRAP_FUSE_LOCK (1<<13)
Rodrigo Vivi9d81a992017-06-02 13:06:41 -07008858#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
Damien Lespiau658ac4c2014-02-10 17:19:45 +00008859#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Ville Syrjälä65e472e2015-12-01 23:28:55 +02008860#define SFUSE_STRAP_CRT_DISABLED (1<<6)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03008861#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
8862#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
8863#define SFUSE_STRAP_DDID_DETECTED (1<<0)
8864
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008865#define WM_MISC _MMIO(0x45260)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03008866#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
8867
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008868#define WM_DBG _MMIO(0x45280)
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03008869#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
8870#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
8871#define WM_DBG_DISALLOW_SPRITE (1<<2)
8872
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008873/* pipe CSC */
8874#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
8875#define _PIPE_A_CSC_COEFF_BY 0x49014
8876#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
8877#define _PIPE_A_CSC_COEFF_BU 0x4901c
8878#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
8879#define _PIPE_A_CSC_COEFF_BV 0x49024
8880#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03008881#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
8882#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
8883#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008884#define _PIPE_A_CSC_PREOFF_HI 0x49030
8885#define _PIPE_A_CSC_PREOFF_ME 0x49034
8886#define _PIPE_A_CSC_PREOFF_LO 0x49038
8887#define _PIPE_A_CSC_POSTOFF_HI 0x49040
8888#define _PIPE_A_CSC_POSTOFF_ME 0x49044
8889#define _PIPE_A_CSC_POSTOFF_LO 0x49048
8890
8891#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
8892#define _PIPE_B_CSC_COEFF_BY 0x49114
8893#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
8894#define _PIPE_B_CSC_COEFF_BU 0x4911c
8895#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
8896#define _PIPE_B_CSC_COEFF_BV 0x49124
8897#define _PIPE_B_CSC_MODE 0x49128
8898#define _PIPE_B_CSC_PREOFF_HI 0x49130
8899#define _PIPE_B_CSC_PREOFF_ME 0x49134
8900#define _PIPE_B_CSC_PREOFF_LO 0x49138
8901#define _PIPE_B_CSC_POSTOFF_HI 0x49140
8902#define _PIPE_B_CSC_POSTOFF_ME 0x49144
8903#define _PIPE_B_CSC_POSTOFF_LO 0x49148
8904
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008905#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
8906#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
8907#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
8908#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
8909#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
8910#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
8911#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
8912#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
8913#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
8914#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
8915#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
8916#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
8917#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008918
Lionel Landwerlin82cf4352016-03-16 10:57:16 +00008919/* pipe degamma/gamma LUTs on IVB+ */
8920#define _PAL_PREC_INDEX_A 0x4A400
8921#define _PAL_PREC_INDEX_B 0x4AC00
8922#define _PAL_PREC_INDEX_C 0x4B400
8923#define PAL_PREC_10_12_BIT (0 << 31)
8924#define PAL_PREC_SPLIT_MODE (1 << 31)
8925#define PAL_PREC_AUTO_INCREMENT (1 << 15)
Ander Conselvan de Oliveira2fcb2062017-01-26 13:24:23 +02008926#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
Lionel Landwerlin82cf4352016-03-16 10:57:16 +00008927#define _PAL_PREC_DATA_A 0x4A404
8928#define _PAL_PREC_DATA_B 0x4AC04
8929#define _PAL_PREC_DATA_C 0x4B404
8930#define _PAL_PREC_GC_MAX_A 0x4A410
8931#define _PAL_PREC_GC_MAX_B 0x4AC10
8932#define _PAL_PREC_GC_MAX_C 0x4B410
8933#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
8934#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
8935#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
Ander Conselvan de Oliveira9751baf2017-01-27 11:02:30 +02008936#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
8937#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
8938#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
Lionel Landwerlin82cf4352016-03-16 10:57:16 +00008939
8940#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
8941#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
8942#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
8943#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
8944
Ander Conselvan de Oliveira9751baf2017-01-27 11:02:30 +02008945#define _PRE_CSC_GAMC_INDEX_A 0x4A484
8946#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
8947#define _PRE_CSC_GAMC_INDEX_C 0x4B484
8948#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
8949#define _PRE_CSC_GAMC_DATA_A 0x4A488
8950#define _PRE_CSC_GAMC_DATA_B 0x4AC88
8951#define _PRE_CSC_GAMC_DATA_C 0x4B488
8952
8953#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
8954#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
8955
Lionel Landwerlin29dc3732016-03-16 10:57:17 +00008956/* pipe CSC & degamma/gamma LUTs on CHV */
8957#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
8958#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
8959#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
8960#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
8961#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
8962#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
8963#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
8964#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
8965#define CGM_PIPE_MODE_GAMMA (1 << 2)
8966#define CGM_PIPE_MODE_CSC (1 << 1)
8967#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
8968
8969#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
8970#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
8971#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
8972#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
8973#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
8974#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
8975#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
8976#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
8977
8978#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
8979#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
8980#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
8981#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
8982#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
8983#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
8984#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
8985#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
8986
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008987/* MIPI DSI registers */
8988
Hans de Goede0ad4dc82017-05-18 13:06:44 +02008989#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008990#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
Jani Nikula3230bf12013-08-27 15:12:16 +03008991
Deepak Mbcc65702017-02-17 18:13:34 +05308992#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
8993#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
8994#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
8995#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
8996
Uma Shankaraec02462017-09-25 19:26:01 +05308997/* Gen4+ Timestamp and Pipe Frame time stamp registers */
8998#define GEN4_TIMESTAMP _MMIO(0x2358)
8999#define ILK_TIMESTAMP_HI _MMIO(0x70070)
9000#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9001
Lionel Landwerlindab91782017-11-10 19:08:44 +00009002#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9003#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9004#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9005#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9006#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9007
Uma Shankaraec02462017-09-25 19:26:01 +05309008#define _PIPE_FRMTMSTMP_A 0x70048
9009#define PIPE_FRMTMSTMP(pipe) \
9010 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9011
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309012/* BXT MIPI clock controls */
9013#define BXT_MAX_VAR_OUTPUT_KHZ 39500
9014
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009015#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309016#define BXT_MIPI1_DIV_SHIFT 26
9017#define BXT_MIPI2_DIV_SHIFT 10
9018#define BXT_MIPI_DIV_SHIFT(port) \
9019 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9020 BXT_MIPI2_DIV_SHIFT)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309021
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309022/* TX control divider to select actual TX clock output from (8x/var) */
Deepak M782d25c2016-02-15 22:43:57 +05309023#define BXT_MIPI1_TX_ESCLK_SHIFT 26
9024#define BXT_MIPI2_TX_ESCLK_SHIFT 10
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309025#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9026 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9027 BXT_MIPI2_TX_ESCLK_SHIFT)
Deepak M782d25c2016-02-15 22:43:57 +05309028#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9029#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309030#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9031 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
Deepak M782d25c2016-02-15 22:43:57 +05309032 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9033#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9034 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9035/* RX upper control divider to select actual RX clock output from 8x */
9036#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9037#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9038#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9039 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9040 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9041#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9042#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9043#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9044 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9045 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9046#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9047 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9048/* 8/3X divider to select the actual 8/3X clock output from 8x */
9049#define BXT_MIPI1_8X_BY3_SHIFT 19
9050#define BXT_MIPI2_8X_BY3_SHIFT 3
9051#define BXT_MIPI_8X_BY3_SHIFT(port) \
9052 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9053 BXT_MIPI2_8X_BY3_SHIFT)
9054#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9055#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9056#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9057 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9058 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9059#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9060 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9061/* RX lower control divider to select actual RX clock output from 8x */
9062#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9063#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9064#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9065 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9066 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9067#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9068#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9069#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9070 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9071 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9072#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9073 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9074
9075#define RX_DIVIDER_BIT_1_2 0x3
9076#define RX_DIVIDER_BIT_3_4 0xC
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05309077
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309078/* BXT MIPI mode configure */
9079#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9080#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009081#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309082 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9083
9084#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9085#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009086#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309087 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9088
9089#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9090#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009091#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309092 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9093
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009094#define BXT_DSI_PLL_CTL _MMIO(0x161000)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309095#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9096#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9097#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
Deepak Mf340c2f2017-02-17 18:13:32 +05309098#define BXT_DSIC_16X_BY1 (0 << 10)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309099#define BXT_DSIC_16X_BY2 (1 << 10)
9100#define BXT_DSIC_16X_BY3 (2 << 10)
9101#define BXT_DSIC_16X_BY4 (3 << 10)
Imre Deakdb18b6a2016-03-24 12:41:40 +02009102#define BXT_DSIC_16X_MASK (3 << 10)
Deepak Mf340c2f2017-02-17 18:13:32 +05309103#define BXT_DSIA_16X_BY1 (0 << 8)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309104#define BXT_DSIA_16X_BY2 (1 << 8)
9105#define BXT_DSIA_16X_BY3 (2 << 8)
9106#define BXT_DSIA_16X_BY4 (3 << 8)
Imre Deakdb18b6a2016-03-24 12:41:40 +02009107#define BXT_DSIA_16X_MASK (3 << 8)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309108#define BXT_DSI_FREQ_SEL_SHIFT 8
9109#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9110
9111#define BXT_DSI_PLL_RATIO_MAX 0x7D
9112#define BXT_DSI_PLL_RATIO_MIN 0x22
Deepak Mf340c2f2017-02-17 18:13:32 +05309113#define GLK_DSI_PLL_RATIO_MAX 0x6F
9114#define GLK_DSI_PLL_RATIO_MIN 0x22
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309115#define BXT_DSI_PLL_RATIO_MASK 0xFF
Deepak M61ad9922015-12-04 19:47:38 +05309116#define BXT_REF_CLOCK_KHZ 19200
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309117
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009118#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05309119#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9120#define BXT_DSI_PLL_LOCKED (1 << 30)
9121
Jani Nikula3230bf12013-08-27 15:12:16 +03009122#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009123#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009124#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +05309125
9126 /* BXT port control */
9127#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9128#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009129#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +05309130
Uma Shankar1881a422017-01-25 19:43:23 +05309131#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9132#define STAP_SELECT (1 << 0)
9133
9134#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9135#define HS_IO_CTRL_SELECT (1 << 0)
9136
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009137#define DPI_ENABLE (1 << 31) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03009138#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9139#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
Gaurav K Singh369602d2014-12-05 14:09:28 +05309140#define DUAL_LINK_MODE_SHIFT 26
Jani Nikula3230bf12013-08-27 15:12:16 +03009141#define DUAL_LINK_MODE_MASK (1 << 26)
9142#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9143#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009144#define DITHERING_ENABLE (1 << 25) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03009145#define FLOPPED_HSTX (1 << 23)
9146#define DE_INVERT (1 << 19) /* XXX */
9147#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9148#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9149#define AFE_LATCHOUT (1 << 17)
9150#define LP_OUTPUT_HOLD (1 << 16)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009151#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9152#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9153#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9154#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
Jani Nikula3230bf12013-08-27 15:12:16 +03009155#define CSB_SHIFT 9
9156#define CSB_MASK (3 << 9)
9157#define CSB_20MHZ (0 << 9)
9158#define CSB_10MHZ (1 << 9)
9159#define CSB_40MHZ (2 << 9)
9160#define BANDGAP_MASK (1 << 8)
9161#define BANDGAP_PNW_CIRCUIT (0 << 8)
9162#define BANDGAP_LNC_CIRCUIT (1 << 8)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009163#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9164#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9165#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
9166#define TEARING_EFFECT_SHIFT 2 /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03009167#define TEARING_EFFECT_MASK (3 << 2)
9168#define TEARING_EFFECT_OFF (0 << 2)
9169#define TEARING_EFFECT_DSI (1 << 2)
9170#define TEARING_EFFECT_GPIO (2 << 2)
9171#define LANE_CONFIGURATION_SHIFT 0
9172#define LANE_CONFIGURATION_MASK (3 << 0)
9173#define LANE_CONFIGURATION_4LANE (0 << 0)
9174#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
9175#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
9176
9177#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009178#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009179#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009180#define TEARING_EFFECT_DELAY_SHIFT 0
9181#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
9182
9183/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309184#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +03009185
9186/* MIPI DSI Controller and D-PHY registers */
9187
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309188#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009189#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009190#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +03009191#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
9192#define ULPS_STATE_MASK (3 << 1)
9193#define ULPS_STATE_ENTER (2 << 1)
9194#define ULPS_STATE_EXIT (1 << 1)
9195#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
9196#define DEVICE_READY (1 << 0)
9197
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309198#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009199#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009200#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309201#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009202#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009203#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +03009204#define TEARING_EFFECT (1 << 31)
9205#define SPL_PKT_SENT_INTERRUPT (1 << 30)
9206#define GEN_READ_DATA_AVAIL (1 << 29)
9207#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
9208#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
9209#define RX_PROT_VIOLATION (1 << 26)
9210#define RX_INVALID_TX_LENGTH (1 << 25)
9211#define ACK_WITH_NO_ERROR (1 << 24)
9212#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
9213#define LP_RX_TIMEOUT (1 << 22)
9214#define HS_TX_TIMEOUT (1 << 21)
9215#define DPI_FIFO_UNDERRUN (1 << 20)
9216#define LOW_CONTENTION (1 << 19)
9217#define HIGH_CONTENTION (1 << 18)
9218#define TXDSI_VC_ID_INVALID (1 << 17)
9219#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
9220#define TXCHECKSUM_ERROR (1 << 15)
9221#define TXECC_MULTIBIT_ERROR (1 << 14)
9222#define TXECC_SINGLE_BIT_ERROR (1 << 13)
9223#define TXFALSE_CONTROL_ERROR (1 << 12)
9224#define RXDSI_VC_ID_INVALID (1 << 11)
9225#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
9226#define RXCHECKSUM_ERROR (1 << 9)
9227#define RXECC_MULTIBIT_ERROR (1 << 8)
9228#define RXECC_SINGLE_BIT_ERROR (1 << 7)
9229#define RXFALSE_CONTROL_ERROR (1 << 6)
9230#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
9231#define RX_LP_TX_SYNC_ERROR (1 << 4)
9232#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
9233#define RXEOT_SYNC_ERROR (1 << 2)
9234#define RXSOT_SYNC_ERROR (1 << 1)
9235#define RXSOT_ERROR (1 << 0)
9236
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309237#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009238#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009239#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +03009240#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
9241#define CMD_MODE_NOT_SUPPORTED (0 << 13)
9242#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
9243#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
9244#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
9245#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
9246#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
9247#define VID_MODE_FORMAT_MASK (0xf << 7)
9248#define VID_MODE_NOT_SUPPORTED (0 << 7)
9249#define VID_MODE_FORMAT_RGB565 (1 << 7)
Jani Nikula42c151e2016-03-16 12:21:39 +02009250#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
9251#define VID_MODE_FORMAT_RGB666 (3 << 7)
Jani Nikula3230bf12013-08-27 15:12:16 +03009252#define VID_MODE_FORMAT_RGB888 (4 << 7)
9253#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
9254#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
9255#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
9256#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
9257#define DATA_LANES_PRG_REG_SHIFT 0
9258#define DATA_LANES_PRG_REG_MASK (7 << 0)
9259
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309260#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009261#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009262#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009263#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
9264
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309265#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009266#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009267#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009268#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
9269
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309270#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009271#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009272#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009273#define TURN_AROUND_TIMEOUT_MASK 0x3f
9274
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309275#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009276#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009277#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +03009278#define DEVICE_RESET_TIMER_MASK 0xffff
9279
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309280#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009281#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009282#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +03009283#define VERTICAL_ADDRESS_SHIFT 16
9284#define VERTICAL_ADDRESS_MASK (0xffff << 16)
9285#define HORIZONTAL_ADDRESS_SHIFT 0
9286#define HORIZONTAL_ADDRESS_MASK 0xffff
9287
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309288#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009289#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009290#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03009291#define DBI_FIFO_EMPTY_HALF (0 << 0)
9292#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
9293#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
9294
9295/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309296#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009297#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009298#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009299
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309300#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009301#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009302#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009303
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309304#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009305#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009306#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009307
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309308#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009309#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009310#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009311
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309312#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009313#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009314#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009315
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309316#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009317#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009318#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009319
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309320#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009321#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009322#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009323
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309324#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009325#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009326#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309327
Jani Nikula3230bf12013-08-27 15:12:16 +03009328/* regs above are bits 15:0 */
9329
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309330#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009331#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009332#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009333#define DPI_LP_MODE (1 << 6)
9334#define BACKLIGHT_OFF (1 << 5)
9335#define BACKLIGHT_ON (1 << 4)
9336#define COLOR_MODE_OFF (1 << 3)
9337#define COLOR_MODE_ON (1 << 2)
9338#define TURN_ON (1 << 1)
9339#define SHUTDOWN (1 << 0)
9340
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309341#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009342#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009343#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03009344#define COMMAND_BYTE_SHIFT 0
9345#define COMMAND_BYTE_MASK (0x3f << 0)
9346
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309347#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009348#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009349#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009350#define MASTER_INIT_TIMER_SHIFT 0
9351#define MASTER_INIT_TIMER_MASK (0xffff << 0)
9352
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309353#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009354#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009355#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009356 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +03009357#define MAX_RETURN_PKT_SIZE_SHIFT 0
9358#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
9359
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309360#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009361#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009362#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009363#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
9364#define DISABLE_VIDEO_BTA (1 << 3)
9365#define IP_TG_CONFIG (1 << 2)
9366#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
9367#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
9368#define VIDEO_MODE_BURST (3 << 0)
9369
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309370#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009371#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009372#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
Jani Nikulaf90e8c32016-06-03 17:57:05 +03009373#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
9374#define BXT_DPHY_DEFEATURE_EN (1 << 8)
Jani Nikula3230bf12013-08-27 15:12:16 +03009375#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
9376#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
9377#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
9378#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
9379#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
9380#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
9381#define CLOCKSTOP (1 << 1)
9382#define EOT_DISABLE (1 << 0)
9383
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309384#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009385#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009386#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +03009387#define LP_BYTECLK_SHIFT 0
9388#define LP_BYTECLK_MASK (0xffff << 0)
9389
Deepak Mb426f982017-02-17 18:13:30 +05309390#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
9391#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
9392#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
9393
9394#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
9395#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
9396#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
9397
Jani Nikula3230bf12013-08-27 15:12:16 +03009398/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309399#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009400#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009401#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03009402
9403/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309404#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009405#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009406#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03009407
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309408#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009409#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009410#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309411#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009412#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009413#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009414#define LONG_PACKET_WORD_COUNT_SHIFT 8
9415#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
9416#define SHORT_PACKET_PARAM_SHIFT 8
9417#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
9418#define VIRTUAL_CHANNEL_SHIFT 6
9419#define VIRTUAL_CHANNEL_MASK (3 << 6)
9420#define DATA_TYPE_SHIFT 0
Ville Syrjälä395b2912015-09-18 20:03:40 +03009421#define DATA_TYPE_MASK (0x3f << 0)
Jani Nikula3230bf12013-08-27 15:12:16 +03009422/* data type values, see include/video/mipi_display.h */
9423
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309424#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009425#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009426#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009427#define DPI_FIFO_EMPTY (1 << 28)
9428#define DBI_FIFO_EMPTY (1 << 27)
9429#define LP_CTRL_FIFO_EMPTY (1 << 26)
9430#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
9431#define LP_CTRL_FIFO_FULL (1 << 24)
9432#define HS_CTRL_FIFO_EMPTY (1 << 18)
9433#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
9434#define HS_CTRL_FIFO_FULL (1 << 16)
9435#define LP_DATA_FIFO_EMPTY (1 << 10)
9436#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
9437#define LP_DATA_FIFO_FULL (1 << 8)
9438#define HS_DATA_FIFO_EMPTY (1 << 2)
9439#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
9440#define HS_DATA_FIFO_FULL (1 << 0)
9441
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309442#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009443#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009444#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03009445#define DBI_HS_LP_MODE_MASK (1 << 0)
9446#define DBI_LP_MODE (1 << 0)
9447#define DBI_HS_MODE (0 << 0)
9448
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309449#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009450#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009451#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +03009452#define EXIT_ZERO_COUNT_SHIFT 24
9453#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
9454#define TRAIL_COUNT_SHIFT 16
9455#define TRAIL_COUNT_MASK (0x1f << 16)
9456#define CLK_ZERO_COUNT_SHIFT 8
9457#define CLK_ZERO_COUNT_MASK (0xff << 8)
9458#define PREPARE_COUNT_SHIFT 0
9459#define PREPARE_COUNT_MASK (0x3f << 0)
9460
9461/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309462#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009463#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009464#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009465
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009466#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
9467#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
9468#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03009469#define LP_HS_SSW_CNT_SHIFT 16
9470#define LP_HS_SSW_CNT_MASK (0xffff << 16)
9471#define HS_LP_PWR_SW_CNT_SHIFT 0
9472#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
9473
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309474#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009475#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009476#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009477#define STOP_STATE_STALL_COUNTER_SHIFT 0
9478#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
9479
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309480#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009481#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009482#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309483#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009484#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009485#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +03009486#define RX_CONTENTION_DETECTED (1 << 0)
9487
9488/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309489#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +03009490#define DBI_TYPEC_ENABLE (1 << 31)
9491#define DBI_TYPEC_WIP (1 << 30)
9492#define DBI_TYPEC_OPTION_SHIFT 28
9493#define DBI_TYPEC_OPTION_MASK (3 << 28)
9494#define DBI_TYPEC_FREQ_SHIFT 24
9495#define DBI_TYPEC_FREQ_MASK (0xf << 24)
9496#define DBI_TYPEC_OVERRIDE (1 << 8)
9497#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
9498#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
9499
9500
9501/* MIPI adapter registers */
9502
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309503#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009504#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009505#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03009506#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
9507#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
9508#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
9509#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
9510#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
9511#define READ_REQUEST_PRIORITY_SHIFT 3
9512#define READ_REQUEST_PRIORITY_MASK (3 << 3)
9513#define READ_REQUEST_PRIORITY_LOW (0 << 3)
9514#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
9515#define RGB_FLIP_TO_BGR (1 << 2)
9516
Jani Nikula6b93e9c2016-03-15 21:51:12 +02009517#define BXT_PIPE_SELECT_SHIFT 7
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309518#define BXT_PIPE_SELECT_MASK (7 << 7)
Deepak M56c48972015-12-09 20:14:04 +05309519#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
Deepak M093d6802016-12-15 14:31:32 +05309520#define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
9521#define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
9522#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
9523#define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
9524#define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
9525#define GLK_LP_WAKE (1 << 22)
9526#define GLK_LP11_LOW_PWR_MODE (1 << 21)
9527#define GLK_LP00_LOW_PWR_MODE (1 << 20)
9528#define GLK_FIREWALL_ENABLE (1 << 16)
9529#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
9530#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
9531#define BXT_DSC_ENABLE (1 << 3)
9532#define BXT_RGB_FLIP (1 << 2)
9533#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
9534#define GLK_MIPIIO_ENABLE (1 << 0)
Shashank Sharmad2e08c02015-09-01 19:41:40 +05309535
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309536#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009537#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009538#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03009539#define DATA_MEM_ADDRESS_SHIFT 5
9540#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
9541#define DATA_VALID (1 << 0)
9542
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309543#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009544#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009545#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03009546#define DATA_LENGTH_SHIFT 0
9547#define DATA_LENGTH_MASK (0xfffff << 0)
9548
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309549#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009550#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009551#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03009552#define COMMAND_MEM_ADDRESS_SHIFT 5
9553#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
9554#define AUTO_PWG_ENABLE (1 << 2)
9555#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
9556#define COMMAND_VALID (1 << 0)
9557
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309558#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009559#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009560#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03009561#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
9562#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
9563
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309564#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009565#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009566#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +03009567
Shashank Sharma4ad83e92014-06-02 18:07:47 +05309568#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02009569#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009570#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +03009571#define READ_DATA_VALID(n) (1 << (n))
9572
Antti Koskipaaa57c7742014-02-04 14:22:24 +02009573/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00009574#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
9575#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02009576
Peter Antoine3bbaba02015-07-10 20:13:11 +03009577/* MOCS (Memory Object Control State) registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009578#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
Peter Antoine3bbaba02015-07-10 20:13:11 +03009579
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02009580#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
9581#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
9582#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
9583#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
9584#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
Peter Antoine3bbaba02015-07-10 20:13:11 +03009585
Tim Gored5165eb2016-02-04 11:49:34 +00009586/* gamt regs */
9587#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
9588#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
9589#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
9590#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
9591#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
9592
Ville Syrjälä93564042017-08-24 22:10:51 +03009593#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
9594#define MMCD_PCLA (1 << 31)
9595#define MMCD_HOTSPOT_EN (1 << 27)
9596
Jesse Barnes585fb112008-07-29 11:54:06 -07009597#endif /* _I915_REG_H_ */