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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020028typedef struct {
29 uint32_t reg;
30} i915_reg_t;
31
32#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
33
34#define INVALID_MMIO_REG _MMIO(0)
35
36static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
37{
38 return reg.reg;
39}
40
41static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
42{
43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
44}
45
46static inline bool i915_mmio_reg_valid(i915_reg_t reg)
47{
48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
49}
50
Chris Wilson5eddb702010-09-11 13:48:45 +010051#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020052#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
Damien Lespiau70d21f02013-07-03 21:06:04 +010053#define _PLANE(plane, a, b) _PIPE(plane, a, b)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020054#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
55#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
56#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030057#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020058#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
Ville Syrjälä2d401b12014-04-09 13:29:08 +030059#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
60 (pipe) == PIPE_B ? (b) : (c))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020061#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
Jani Nikulae7d7cad2014-11-14 16:54:21 +020062#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
63 (port) == PORT_B ? (b) : (c))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020064#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030065
Damien Lespiau98533252014-12-08 17:33:51 +000066#define _MASKED_FIELD(mask, value) ({ \
67 if (__builtin_constant_p(mask)) \
68 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
69 if (__builtin_constant_p(value)) \
70 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
71 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
72 BUILD_BUG_ON_MSG((value) & ~(mask), \
73 "Incorrect value for mask"); \
74 (mask) << 16 | (value); })
75#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
76#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
77
78
Daniel Vetter6b26c862012-04-24 14:04:12 +020079
Jesse Barnes585fb112008-07-29 11:54:06 -070080/* PCI config space */
81
Joonas Lahtinene10fa552016-04-15 12:03:39 +030082#define MCHBAR_I915 0x44
83#define MCHBAR_I965 0x48
84#define MCHBAR_SIZE (4 * 4096)
85
86#define DEVEN 0x54
87#define DEVEN_MCHBAR_EN (1 << 28)
88
89#define BSM 0x5c
90#define BSM_MASK (0xFFFF << 20)
91
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030092#define HPLLCC 0xc0 /* 85x only */
93#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070094#define GC_CLOCK_133_200 (0 << 0)
95#define GC_CLOCK_100_200 (1 << 0)
96#define GC_CLOCK_100_133 (2 << 0)
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030097#define GC_CLOCK_133_266 (3 << 0)
98#define GC_CLOCK_133_200_2 (4 << 0)
99#define GC_CLOCK_133_266_2 (5 << 0)
100#define GC_CLOCK_166_266 (6 << 0)
101#define GC_CLOCK_166_250 (7 << 0)
102
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300103#define I915_GDRST 0xc0 /* PCI config register */
104#define GRDOM_FULL (0 << 2)
105#define GRDOM_RENDER (1 << 2)
106#define GRDOM_MEDIA (3 << 2)
107#define GRDOM_MASK (3 << 2)
108#define GRDOM_RESET_STATUS (1 << 1)
109#define GRDOM_RESET_ENABLE (1 << 0)
110
111#define GCDGMBUS 0xcc
112
Jesse Barnesf97108d2010-01-29 11:27:07 -0800113#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -0700114#define GCFGC 0xf0 /* 915+ only */
115#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
116#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
117#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +0200118#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
119#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
120#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
121#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
122#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
123#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700124#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -0700125#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
126#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
127#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
128#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
129#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
130#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
131#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
132#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
133#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
134#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
135#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
136#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
137#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
138#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
139#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
140#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
141#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
142#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
143#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +0100144
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300145#define ASLE 0xe4
146#define ASLS 0xfc
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700147
Joonas Lahtinene10fa552016-04-15 12:03:39 +0300148#define SWSCI 0xe8
149#define SWSCI_SCISEL (1 << 15)
150#define SWSCI_GSSCIE (1 << 0)
151
152#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
153
Jesse Barnes585fb112008-07-29 11:54:06 -0700154
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200155#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
Ville Syrjäläb3a3f032014-05-19 19:23:24 +0300156#define ILK_GRDOM_FULL (0<<1)
157#define ILK_GRDOM_RENDER (1<<1)
158#define ILK_GRDOM_MEDIA (3<<1)
159#define ILK_GRDOM_MASK (3<<1)
160#define ILK_GRDOM_RESET_ENABLE (1<<0)
161
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200162#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700163#define GEN6_MBC_SNPCR_SHIFT 21
164#define GEN6_MBC_SNPCR_MASK (3<<21)
165#define GEN6_MBC_SNPCR_MAX (0<<21)
166#define GEN6_MBC_SNPCR_MED (1<<21)
167#define GEN6_MBC_SNPCR_LOW (2<<21)
168#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
169
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200170#define VLV_G3DCTL _MMIO(0x9024)
171#define VLV_GSCKGCTL _MMIO(0x9028)
Imre Deak9e72b462014-05-05 15:13:55 +0300172
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200173#define GEN6_MBCTL _MMIO(0x0907c)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100174#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
175#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
176#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
177#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
178#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
179
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200180#define GEN6_GDRST _MMIO(0x941c)
Eric Anholtcff458c2010-11-18 09:31:14 +0800181#define GEN6_GRDOM_FULL (1 << 0)
182#define GEN6_GRDOM_RENDER (1 << 1)
183#define GEN6_GRDOM_MEDIA (1 << 2)
184#define GEN6_GRDOM_BLT (1 << 3)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200185#define GEN6_GRDOM_VECS (1 << 4)
Arun Siluvery6b332fa2016-04-04 18:50:56 +0100186#define GEN9_GRDOM_GUC (1 << 5)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200187#define GEN8_GRDOM_MEDIA2 (1 << 7)
Eric Anholtcff458c2010-11-18 09:31:14 +0800188
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200189#define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228)
190#define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518)
191#define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100192#define PP_DIR_DCLV_2G 0xffffffff
193
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200194#define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4)
195#define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800196
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200197#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
Jeff McGee0cea6502015-02-13 10:27:56 -0600198#define GEN8_RPCS_ENABLE (1 << 31)
199#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
200#define GEN8_RPCS_S_CNT_SHIFT 15
201#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
202#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
203#define GEN8_RPCS_SS_CNT_SHIFT 8
204#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
205#define GEN8_RPCS_EU_MAX_SHIFT 4
206#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
207#define GEN8_RPCS_EU_MIN_SHIFT 0
208#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
209
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200210#define GAM_ECOCHK _MMIO(0x4090)
Damien Lespiau81e231a2015-02-09 19:33:19 +0000211#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100212#define ECOCHK_SNB_BIT (1<<10)
Nick Hoath6381b552015-07-14 14:41:15 +0100213#define ECOCHK_DIS_TLB (1<<8)
Ben Widawskye3dff582013-03-20 14:49:14 -0700214#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100215#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
216#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300217#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
218#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
219#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
220#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
221#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100222
Mika Kuoppalab033bb62016-06-07 17:19:04 +0300223#define GEN8_CONFIG0 _MMIO(0xD00)
224#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
225
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200226#define GAC_ECO_BITS _MMIO(0x14090)
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300227#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200228#define ECOBITS_PPGTT_CACHE64B (3<<8)
229#define ECOBITS_PPGTT_CACHE4B (0<<8)
230
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200231#define GAB_CTL _MMIO(0x24000)
Daniel Vetterbe901a52012-04-11 20:42:39 +0200232#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
233
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200234#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
Paulo Zanoni3774eb52015-08-10 14:57:32 -0300235#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
236#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
237#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
238#define GEN6_STOLEN_RESERVED_1M (0 << 4)
239#define GEN6_STOLEN_RESERVED_512K (1 << 4)
240#define GEN6_STOLEN_RESERVED_256K (2 << 4)
241#define GEN6_STOLEN_RESERVED_128K (3 << 4)
242#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
243#define GEN7_STOLEN_RESERVED_1M (0 << 5)
244#define GEN7_STOLEN_RESERVED_256K (1 << 5)
245#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
246#define GEN8_STOLEN_RESERVED_1M (0 << 7)
247#define GEN8_STOLEN_RESERVED_2M (1 << 7)
248#define GEN8_STOLEN_RESERVED_4M (2 << 7)
249#define GEN8_STOLEN_RESERVED_8M (3 << 7)
Daniel Vetter40bae732014-09-11 13:28:08 +0200250
Jesse Barnes585fb112008-07-29 11:54:06 -0700251/* VGA stuff */
252
253#define VGA_ST01_MDA 0x3ba
254#define VGA_ST01_CGA 0x3da
255
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200256#define _VGA_MSR_WRITE _MMIO(0x3c2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700257#define VGA_MSR_WRITE 0x3c2
258#define VGA_MSR_READ 0x3cc
259#define VGA_MSR_MEM_EN (1<<1)
260#define VGA_MSR_CGA_MODE (1<<0)
261
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300262#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100263#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300264#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700265
266#define VGA_AR_INDEX 0x3c0
267#define VGA_AR_VID_EN (1<<5)
268#define VGA_AR_DATA_WRITE 0x3c0
269#define VGA_AR_DATA_READ 0x3c1
270
271#define VGA_GR_INDEX 0x3ce
272#define VGA_GR_DATA 0x3cf
273/* GR05 */
274#define VGA_GR_MEM_READ_MODE_SHIFT 3
275#define VGA_GR_MEM_READ_MODE_PLANE 1
276/* GR06 */
277#define VGA_GR_MEM_MODE_MASK 0xc
278#define VGA_GR_MEM_MODE_SHIFT 2
279#define VGA_GR_MEM_A0000_AFFFF 0
280#define VGA_GR_MEM_A0000_BFFFF 1
281#define VGA_GR_MEM_B0000_B7FFF 2
282#define VGA_GR_MEM_B0000_BFFFF 3
283
284#define VGA_DACMASK 0x3c6
285#define VGA_DACRX 0x3c7
286#define VGA_DACWX 0x3c8
287#define VGA_DACDATA 0x3c9
288
289#define VGA_CR_INDEX_MDA 0x3b4
290#define VGA_CR_DATA_MDA 0x3b5
291#define VGA_CR_INDEX_CGA 0x3d4
292#define VGA_CR_DATA_CGA 0x3d5
293
294/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800295 * Instruction field definitions used by the command parser
296 */
297#define INSTR_CLIENT_SHIFT 29
298#define INSTR_CLIENT_MASK 0xE0000000
299#define INSTR_MI_CLIENT 0x0
300#define INSTR_BC_CLIENT 0x2
301#define INSTR_RC_CLIENT 0x3
302#define INSTR_SUBCLIENT_SHIFT 27
303#define INSTR_SUBCLIENT_MASK 0x18000000
304#define INSTR_MEDIA_SUBCLIENT 0x2
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800305#define INSTR_26_TO_24_MASK 0x7000000
306#define INSTR_26_TO_24_SHIFT 24
Brad Volkin351e3db2014-02-18 10:15:46 -0800307
308/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700309 * Memory interface instructions used by the kernel
310 */
311#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800312/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
313#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700314
315#define MI_NOOP MI_INSTR(0, 0)
316#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
317#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200318#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700319#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
320#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
321#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
322#define MI_FLUSH MI_INSTR(0x04, 0)
323#define MI_READ_FLUSH (1 << 0)
324#define MI_EXE_FLUSH (1 << 1)
325#define MI_NO_WRITE_FLUSH (1 << 2)
326#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
327#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800328#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800329#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
330#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
331#define MI_ARB_ENABLE (1<<0)
332#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700333#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800334#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
335#define MI_SUSPEND_FLUSH_EN (1<<0)
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800336#define MI_SET_APPID MI_INSTR(0x0e, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400337#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200338#define MI_OVERLAY_CONTINUE (0x0<<21)
339#define MI_OVERLAY_ON (0x1<<21)
340#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700341#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500342#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700343#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500344#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200345/* IVB has funny definitions for which plane to flip. */
346#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
347#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
348#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
349#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
350#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
351#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Damien Lespiau830c81d2014-11-13 17:51:46 +0000352/* SKL ones */
353#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
354#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
355#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
356#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
357#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
358#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
359#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
360#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
361#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700362#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
Ben Widawsky0e792842013-12-16 20:50:37 -0800363#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
364#define MI_SEMAPHORE_UPDATE (1<<21)
365#define MI_SEMAPHORE_COMPARE (1<<20)
366#define MI_SEMAPHORE_REGISTER (1<<18)
367#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
368#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
369#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
370#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
371#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
372#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
373#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
374#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
375#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
376#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
377#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
378#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100379#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
380#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800381#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
382#define MI_MM_SPACE_GTT (1<<8)
383#define MI_MM_SPACE_PHYSICAL (0<<8)
384#define MI_SAVE_EXT_STATE_EN (1<<3)
385#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800386#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800387#define MI_RESTORE_INHIBIT (1<<0)
Abdiel Janulgue4c436d552015-06-16 13:39:41 +0300388#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
389#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
Ben Widawsky3e789982014-06-30 09:53:37 -0700390#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
391#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
Ben Widawsky5ee426c2014-06-30 09:53:38 -0700392#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
393#define MI_SEMAPHORE_POLL (1<<15)
394#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
Jesse Barnes585fb112008-07-29 11:54:06 -0700395#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
Ville Syrjälä8edfbb82014-11-14 18:16:56 +0200396#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
397#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
398#define MI_USE_GGTT (1 << 22) /* g4x+ */
Jesse Barnes585fb112008-07-29 11:54:06 -0700399#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
400#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000401/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
402 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
403 * simply ignores the register load under certain conditions.
404 * - One can actually load arbitrary many arbitrary registers: Simply issue x
405 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
406 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100407#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100408#define MI_LRI_FORCE_POSTED (1<<12)
Arun Siluveryf1afe242015-08-04 16:22:20 +0100409#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
410#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
Ben Widawsky0e792842013-12-16 20:50:37 -0800411#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000412#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700413#define MI_FLUSH_DW_STORE_INDEX (1<<21)
414#define MI_INVALIDATE_TLB (1<<18)
415#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800416#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800417#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700418#define MI_INVALIDATE_BSD (1<<7)
419#define MI_FLUSH_DW_USE_GTT (1<<2)
420#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Arun Siluveryf1afe242015-08-04 16:22:20 +0100421#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
422#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700423#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100424#define MI_BATCH_NON_SECURE (1)
425/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800426#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100427#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800428#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700429#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100430#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700431#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Abdiel Janulgue919032e2015-06-16 13:39:40 +0300432#define MI_BATCH_RESOURCE_STREAMER (1<<10)
Ben Widawsky0e792842013-12-16 20:50:37 -0800433
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200434#define MI_PREDICATE_SRC0 _MMIO(0x2400)
435#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
436#define MI_PREDICATE_SRC1 _MMIO(0x2408)
437#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300438
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200439#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300440#define LOWER_SLICE_ENABLED (1<<0)
441#define LOWER_SLICE_DISABLED (0<<0)
442
Jesse Barnes585fb112008-07-29 11:54:06 -0700443/*
444 * 3D instructions used by the kernel
445 */
446#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
447
448#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
449#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
450#define SC_UPDATE_SCISSOR (0x1<<1)
451#define SC_ENABLE_MASK (0x1<<0)
452#define SC_ENABLE (0x1<<0)
453#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
454#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
455#define SCI_YMIN_MASK (0xffff<<16)
456#define SCI_XMIN_MASK (0xffff<<0)
457#define SCI_YMAX_MASK (0xffff<<16)
458#define SCI_XMAX_MASK (0xffff<<0)
459#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
460#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
461#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
462#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
463#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
464#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
465#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
466#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
467#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100468
469#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
470#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700471#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
472#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100473#define BLT_WRITE_A (2<<20)
474#define BLT_WRITE_RGB (1<<20)
475#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
Jesse Barnes585fb112008-07-29 11:54:06 -0700476#define BLT_DEPTH_8 (0<<24)
477#define BLT_DEPTH_16_565 (1<<24)
478#define BLT_DEPTH_16_1555 (2<<24)
479#define BLT_DEPTH_32 (3<<24)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100480#define BLT_ROP_SRC_COPY (0xcc<<16)
481#define BLT_ROP_COLOR_COPY (0xf0<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700482#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
483#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
484#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
485#define ASYNC_FLIP (1<<22)
486#define DISPLAY_PLANE_A (0<<20)
487#define DISPLAY_PLANE_B (1<<20)
Ville Syrjälä68d97532015-09-18 20:03:39 +0300488#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
Arun Siluvery0160f052015-06-23 15:46:57 +0100489#define PIPE_CONTROL_FLUSH_L3 (1<<27)
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200490#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800491#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800492#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200493#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700494#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Chris Wilson148b83d2014-12-16 08:44:31 +0000495#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200496#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800497#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200498#define PIPE_CONTROL_DEPTH_STALL (1<<13)
499#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200500#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200501#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
502#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
503#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
504#define PIPE_CONTROL_NOTIFY (1<<8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700505#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
Arun Siluveryc82435b2015-06-19 18:37:13 +0100506#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
Jesse Barnes8d315282011-10-16 10:23:31 +0200507#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
508#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
509#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200510#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200511#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700512#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700513
Brad Volkin3a6fa982014-02-18 10:15:47 -0800514/*
515 * Commands used only by the command parser
516 */
517#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
518#define MI_ARB_CHECK MI_INSTR(0x05, 0)
519#define MI_RS_CONTROL MI_INSTR(0x06, 0)
520#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
521#define MI_PREDICATE MI_INSTR(0x0C, 0)
522#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
523#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800524#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800525#define MI_URB_CLEAR MI_INSTR(0x19, 0)
526#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
527#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800528#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
529#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800530#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
531#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
532#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
533#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
534#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
535
536#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
537#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800538#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
539#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800540#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
541#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
542#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
543 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
544#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
545 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
546#define GFX_OP_3DSTATE_SO_DECL_LIST \
547 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
548
549#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
550 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
551#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
552 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
553#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
554 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
555#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
556 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
557#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
558 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
559
560#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
561
562#define COLOR_BLT ((0x2<<29)|(0x40<<22))
563#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100564
565/*
Brad Volkin5947de92014-02-18 10:15:50 -0800566 * Registers used only by the command parser
567 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200568#define BCS_SWCTRL _MMIO(0x22200)
Brad Volkin5947de92014-02-18 10:15:50 -0800569
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200570#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
571#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
572#define HS_INVOCATION_COUNT _MMIO(0x2300)
573#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
574#define DS_INVOCATION_COUNT _MMIO(0x2308)
575#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
576#define IA_VERTICES_COUNT _MMIO(0x2310)
577#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
578#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
579#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
580#define VS_INVOCATION_COUNT _MMIO(0x2320)
581#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
582#define GS_INVOCATION_COUNT _MMIO(0x2328)
583#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
584#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
585#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
586#define CL_INVOCATION_COUNT _MMIO(0x2338)
587#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
588#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
589#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
590#define PS_INVOCATION_COUNT _MMIO(0x2348)
591#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
592#define PS_DEPTH_COUNT _MMIO(0x2350)
593#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800594
595/* There are the 4 64-bit counter registers, one for each stream output */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200596#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
597#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
Brad Volkin5947de92014-02-18 10:15:50 -0800598
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200599#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
600#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
Brad Volkin113a0472014-04-08 14:18:58 -0700601
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200602#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
603#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
604#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
605#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
606#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
607#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
Brad Volkin113a0472014-04-08 14:18:58 -0700608
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200609#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
610#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
611#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
Jordan Justen7b9748c2015-10-01 23:09:58 -0700612
Jordan Justen1b850662016-03-06 23:30:29 -0800613/* There are the 16 64-bit CS General Purpose Registers */
614#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
615#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
616
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200617#define OACONTROL _MMIO(0x2360)
Kenneth Graunke180b8132014-03-25 22:52:03 -0700618
Brad Volkin220375a2014-02-18 10:15:51 -0800619#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
620#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200621#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
Brad Volkin220375a2014-02-18 10:15:51 -0800622
Brad Volkin5947de92014-02-18 10:15:50 -0800623/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100624 * Reset registers
625 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200626#define DEBUG_RESET_I830 _MMIO(0x6070)
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100627#define DEBUG_RESET_FULL (1<<7)
628#define DEBUG_RESET_RENDER (1<<8)
629#define DEBUG_RESET_DISPLAY (1<<9)
630
Jesse Barnes57f350b2012-03-28 13:39:25 -0700631/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300632 * IOSF sideband
633 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200634#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300635#define IOSF_DEVFN_SHIFT 24
636#define IOSF_OPCODE_SHIFT 16
637#define IOSF_PORT_SHIFT 8
638#define IOSF_BYTE_ENABLES_SHIFT 4
639#define IOSF_BAR_SHIFT 1
640#define IOSF_SB_BUSY (1<<0)
Jani Nikula4688d452016-02-04 12:50:53 +0200641#define IOSF_PORT_BUNIT 0x03
642#define IOSF_PORT_PUNIT 0x04
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300643#define IOSF_PORT_NC 0x11
644#define IOSF_PORT_DPIO 0x12
Jani Nikulae9f882a2013-08-27 15:12:14 +0300645#define IOSF_PORT_GPIO_NC 0x13
646#define IOSF_PORT_CCK 0x14
Jani Nikula4688d452016-02-04 12:50:53 +0200647#define IOSF_PORT_DPIO_2 0x1a
648#define IOSF_PORT_FLISDSI 0x1b
Deepak Mdfb19ed2016-02-04 18:55:15 +0200649#define IOSF_PORT_GPIO_SC 0x48
650#define IOSF_PORT_GPIO_SUS 0xa8
Jani Nikula4688d452016-02-04 12:50:53 +0200651#define IOSF_PORT_CCU 0xa9
Jani Nikula7071af92016-03-18 13:11:15 +0200652#define CHV_IOSF_PORT_GPIO_N 0x13
653#define CHV_IOSF_PORT_GPIO_SE 0x48
654#define CHV_IOSF_PORT_GPIO_E 0xa8
655#define CHV_IOSF_PORT_GPIO_SW 0xb2
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200656#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
657#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300658
Jesse Barnes30a970c2013-11-04 13:48:12 -0800659/* See configdb bunit SB addr map */
660#define BUNIT_REG_BISOC 0x11
661
Jesse Barnes30a970c2013-11-04 13:48:12 -0800662#define PUNIT_REG_DSPFREQ 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +0300663#define DSPFREQSTAT_SHIFT_CHV 24
664#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
665#define DSPFREQGUAR_SHIFT_CHV 8
666#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800667#define DSPFREQSTAT_SHIFT 30
668#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
669#define DSPFREQGUAR_SHIFT 14
670#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200671#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
672#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
673#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
Ville Syrjälä26972b02014-06-28 02:04:11 +0300674#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
675#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
676#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
677#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
678#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
679#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
680#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
681#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
682#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
683#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
684#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
685#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +0200686
687/* See the PUNIT HAS v0.8 for the below bits */
688enum punit_power_well {
Patrik Jakobssoncd02ac52015-11-16 15:01:05 +0100689 /* These numbers are fixed and must match the position of the pw bits */
Imre Deaka30180a2014-03-04 19:23:02 +0200690 PUNIT_POWER_WELL_RENDER = 0,
691 PUNIT_POWER_WELL_MEDIA = 1,
692 PUNIT_POWER_WELL_DISP2D = 3,
693 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
694 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
695 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
696 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
697 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
698 PUNIT_POWER_WELL_DPIO_RX0 = 10,
699 PUNIT_POWER_WELL_DPIO_RX1 = 11,
Ville Syrjälä5d6f7ea2014-06-28 02:04:08 +0300700 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
Imre Deaka30180a2014-03-04 19:23:02 +0200701
Patrik Jakobssoncd02ac52015-11-16 15:01:05 +0100702 /* Not actual bit groups. Used as IDs for lookup_power_well() */
Imre Deak56fcfd62015-11-04 19:24:10 +0200703 PUNIT_POWER_WELL_ALWAYS_ON,
Imre Deaka30180a2014-03-04 19:23:02 +0200704};
705
Satheeshakrishna M94dd5132015-02-04 13:57:44 +0000706enum skl_disp_power_wells {
Patrik Jakobssoncd02ac52015-11-16 15:01:05 +0100707 /* These numbers are fixed and must match the position of the pw bits */
Satheeshakrishna M94dd5132015-02-04 13:57:44 +0000708 SKL_DISP_PW_MISC_IO,
709 SKL_DISP_PW_DDI_A_E,
710 SKL_DISP_PW_DDI_B,
711 SKL_DISP_PW_DDI_C,
712 SKL_DISP_PW_DDI_D,
713 SKL_DISP_PW_1 = 14,
714 SKL_DISP_PW_2,
Imre Deak56fcfd62015-11-04 19:24:10 +0200715
Patrik Jakobssoncd02ac52015-11-16 15:01:05 +0100716 /* Not actual bit groups. Used as IDs for lookup_power_well() */
Imre Deak56fcfd62015-11-04 19:24:10 +0200717 SKL_DISP_PW_ALWAYS_ON,
Patrik Jakobsson9f836f92015-11-16 16:20:01 +0100718 SKL_DISP_PW_DC_OFF,
Imre Deak9c8d0b82016-06-13 16:44:34 +0300719
720 BXT_DPIO_CMN_A,
721 BXT_DPIO_CMN_BC,
Satheeshakrishna M94dd5132015-02-04 13:57:44 +0000722};
723
724#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
725#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
726
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800727#define PUNIT_REG_PWRGT_CTRL 0x60
728#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +0200729#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
730#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
731#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
732#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
733#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800734
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300735#define PUNIT_REG_GPU_LFM 0xd3
736#define PUNIT_REG_GPU_FREQ_REQ 0xd4
737#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläc8e96272014-11-07 21:33:44 +0200738#define GPLLENABLE (1<<4)
Ville Syrjäläe8474402013-06-26 17:43:24 +0300739#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300740#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -0400741#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300742
743#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
744#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
745
Deepak S095acd52015-01-17 11:05:59 +0530746#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
747#define FB_GFX_FREQ_FUSE_MASK 0xff
748#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
749#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
750#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
751
752#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
753#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
754
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200755#define PUNIT_REG_DDR_SETUP2 0x139
756#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
757#define FORCE_DDR_LOW_FREQ (1 << 1)
758#define FORCE_DDR_HIGH_FREQ (1 << 0)
759
Deepak S2b6b3a02014-05-27 15:59:30 +0530760#define PUNIT_GPU_STATUS_REG 0xdb
761#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
762#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
763#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
764#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
765
766#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
767#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
768#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
769
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300770#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
771#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
772#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
773#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
774#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
775#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
776#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
777#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
778#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
779#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
780
Deepak S3ef62342015-04-29 08:36:24 +0530781#define VLV_TURBO_SOC_OVERRIDE 0x04
782#define VLV_OVERRIDE_EN 1
783#define VLV_SOC_TDP_EN (1 << 1)
784#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
785#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
786
Deepak S31685c22014-07-03 17:33:01 -0400787#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
Deepak S31685c22014-07-03 17:33:01 -0400788
ymohanmabe4fc042013-08-27 23:40:56 +0300789/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800790#define CCK_FUSE_REG 0x8
791#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300792#define CCK_REG_DSI_PLL_FUSE 0x44
793#define CCK_REG_DSI_PLL_CONTROL 0x48
794#define DSI_PLL_VCO_EN (1 << 31)
795#define DSI_PLL_LDO_GATE (1 << 30)
796#define DSI_PLL_P1_POST_DIV_SHIFT 17
797#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
798#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
799#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
800#define DSI_PLL_MUX_MASK (3 << 9)
801#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
802#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
803#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
804#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
805#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
806#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
807#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
808#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
809#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
810#define DSI_PLL_LOCK (1 << 0)
811#define CCK_REG_DSI_PLL_DIVIDER 0x4c
812#define DSI_PLL_LFSR (1 << 31)
813#define DSI_PLL_FRACTION_EN (1 << 30)
814#define DSI_PLL_FRAC_COUNTER_SHIFT 27
815#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
816#define DSI_PLL_USYNC_CNT_SHIFT 18
817#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
818#define DSI_PLL_N1_DIV_SHIFT 16
819#define DSI_PLL_N1_DIV_MASK (3 << 16)
820#define DSI_PLL_M1_DIV_SHIFT 0
821#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300822#define CCK_CZ_CLOCK_CONTROL 0x62
Ville Syrjäläc30fec62016-03-04 21:43:02 +0200823#define CCK_GPLL_CLOCK_CONTROL 0x67
Jesse Barnes30a970c2013-11-04 13:48:12 -0800824#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä35d38d12016-03-02 17:22:16 +0200825#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
Vandana Kannan87d5d252015-09-24 23:29:17 +0300826#define CCK_TRUNK_FORCE_ON (1 << 17)
827#define CCK_TRUNK_FORCE_OFF (1 << 16)
828#define CCK_FREQUENCY_STATUS (0x1f << 8)
829#define CCK_FREQUENCY_STATUS_SHIFT 8
830#define CCK_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +0300831
Ville Syrjälä0e767182014-04-25 20:14:31 +0300832/**
833 * DOC: DPIO
834 *
Imre Deakeee21562015-03-10 21:18:30 +0200835 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
Ville Syrjälä0e767182014-04-25 20:14:31 +0300836 * ports. DPIO is the name given to such a display PHY. These PHYs
837 * don't follow the standard programming model using direct MMIO
838 * registers, and instead their registers must be accessed trough IOSF
839 * sideband. VLV has one such PHY for driving ports B and C, and CHV
840 * adds another PHY for driving port D. Each PHY responds to specific
841 * IOSF-SB port.
842 *
843 * Each display PHY is made up of one or two channels. Each channel
844 * houses a common lane part which contains the PLL and other common
845 * logic. CH0 common lane also contains the IOSF-SB logic for the
846 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
847 * must be running when any DPIO registers are accessed.
848 *
849 * In addition to having their own registers, the PHYs are also
850 * controlled through some dedicated signals from the display
851 * controller. These include PLL reference clock enable, PLL enable,
852 * and CRI clock selection, for example.
853 *
854 * Eeach channel also has two splines (also called data lanes), and
855 * each spline is made up of one Physical Access Coding Sub-Layer
856 * (PCS) block and two TX lanes. So each channel has two PCS blocks
857 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
858 * data/clock pairs depending on the output type.
859 *
860 * Additionally the PHY also contains an AUX lane with AUX blocks
861 * for each channel. This is used for DP AUX communication, but
862 * this fact isn't really relevant for the driver since AUX is
863 * controlled from the display controller side. No DPIO registers
864 * need to be accessed during AUX communication,
865 *
Imre Deakeee21562015-03-10 21:18:30 +0200866 * Generally on VLV/CHV the common lane corresponds to the pipe and
Masanari Iida32197aa2014-10-20 23:53:13 +0900867 * the spline (PCS/TX) corresponds to the port.
Ville Syrjälä0e767182014-04-25 20:14:31 +0300868 *
869 * For dual channel PHY (VLV/CHV):
870 *
871 * pipe A == CMN/PLL/REF CH0
872 *
873 * pipe B == CMN/PLL/REF CH1
874 *
875 * port B == PCS/TX CH0
876 *
877 * port C == PCS/TX CH1
878 *
879 * This is especially important when we cross the streams
880 * ie. drive port B with pipe B, or port C with pipe A.
881 *
882 * For single channel PHY (CHV):
883 *
884 * pipe C == CMN/PLL/REF CH0
885 *
886 * port D == PCS/TX CH0
887 *
Imre Deakeee21562015-03-10 21:18:30 +0200888 * On BXT the entire PHY channel corresponds to the port. That means
889 * the PLL is also now associated with the port rather than the pipe,
890 * and so the clock needs to be routed to the appropriate transcoder.
891 * Port A PLL is directly connected to transcoder EDP and port B/C
892 * PLLs can be routed to any transcoder A/B/C.
893 *
894 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
895 * digital port D (CHV) or port A (BXT).
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200896 *
Danilo Cesar Lemes de Paulaf03d8ed2015-11-25 18:07:55 +0100897 *
898 * Dual channel PHY (VLV/CHV/BXT)
899 * ---------------------------------
900 * | CH0 | CH1 |
901 * | CMN/PLL/REF | CMN/PLL/REF |
902 * |---------------|---------------| Display PHY
903 * | PCS01 | PCS23 | PCS01 | PCS23 |
904 * |-------|-------|-------|-------|
905 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
906 * ---------------------------------
907 * | DDI0 | DDI1 | DP/HDMI ports
908 * ---------------------------------
909 *
910 * Single channel PHY (CHV/BXT)
911 * -----------------
912 * | CH0 |
913 * | CMN/PLL/REF |
914 * |---------------| Display PHY
915 * | PCS01 | PCS23 |
916 * |-------|-------|
917 * |TX0|TX1|TX2|TX3|
918 * -----------------
919 * | DDI2 | DP/HDMI port
920 * -----------------
Jesse Barnes57f350b2012-03-28 13:39:25 -0700921 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300922#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300923
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200924#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700925#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
926#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
927#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700928#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700929
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800930#define DPIO_PHY(pipe) ((pipe) >> 1)
931#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
932
Daniel Vetter598fac62013-04-18 22:01:46 +0200933/*
934 * Per pipe/PLL DPIO regs
935 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800936#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -0700937#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200938#define DPIO_POST_DIV_DAC 0
939#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
940#define DPIO_POST_DIV_LVDS1 2
941#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700942#define DPIO_K_SHIFT (24) /* 4 bits */
943#define DPIO_P1_SHIFT (21) /* 3 bits */
944#define DPIO_P2_SHIFT (16) /* 5 bits */
945#define DPIO_N_SHIFT (12) /* 4 bits */
946#define DPIO_ENABLE_CALIBRATION (1<<11)
947#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
948#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800949#define _VLV_PLL_DW3_CH1 0x802c
950#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700951
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800952#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -0700953#define DPIO_REFSEL_OVERRIDE 27
954#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
955#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
956#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530957#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700958#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
959#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800960#define _VLV_PLL_DW5_CH1 0x8034
961#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700962
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800963#define _VLV_PLL_DW7_CH0 0x801c
964#define _VLV_PLL_DW7_CH1 0x803c
965#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700966
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800967#define _VLV_PLL_DW8_CH0 0x8040
968#define _VLV_PLL_DW8_CH1 0x8060
969#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200970
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800971#define VLV_PLL_DW9_BCAST 0xc044
972#define _VLV_PLL_DW9_CH0 0x8044
973#define _VLV_PLL_DW9_CH1 0x8064
974#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200975
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800976#define _VLV_PLL_DW10_CH0 0x8048
977#define _VLV_PLL_DW10_CH1 0x8068
978#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200979
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800980#define _VLV_PLL_DW11_CH0 0x804c
981#define _VLV_PLL_DW11_CH1 0x806c
982#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700983
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800984/* Spec for ref block start counts at DW10 */
985#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +0200986
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800987#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100988
Daniel Vetter598fac62013-04-18 22:01:46 +0200989/*
990 * Per DDI channel DPIO regs
991 */
992
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800993#define _VLV_PCS_DW0_CH0 0x8200
994#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +0200995#define DPIO_PCS_TX_LANE2_RESET (1<<16)
996#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300997#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
998#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800999#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001000
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001001#define _VLV_PCS01_DW0_CH0 0x200
1002#define _VLV_PCS23_DW0_CH0 0x400
1003#define _VLV_PCS01_DW0_CH1 0x2600
1004#define _VLV_PCS23_DW0_CH1 0x2800
1005#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1006#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1007
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001008#define _VLV_PCS_DW1_CH0 0x8204
1009#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +03001010#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +02001011#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1012#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1013#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1014#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001015#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001016
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03001017#define _VLV_PCS01_DW1_CH0 0x204
1018#define _VLV_PCS23_DW1_CH0 0x404
1019#define _VLV_PCS01_DW1_CH1 0x2604
1020#define _VLV_PCS23_DW1_CH1 0x2804
1021#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1022#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1023
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001024#define _VLV_PCS_DW8_CH0 0x8220
1025#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +03001026#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1027#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001028#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001029
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001030#define _VLV_PCS01_DW8_CH0 0x0220
1031#define _VLV_PCS23_DW8_CH0 0x0420
1032#define _VLV_PCS01_DW8_CH1 0x2620
1033#define _VLV_PCS23_DW8_CH1 0x2820
1034#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1035#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001036
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001037#define _VLV_PCS_DW9_CH0 0x8224
1038#define _VLV_PCS_DW9_CH1 0x8424
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001039#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1040#define DPIO_PCS_TX2MARGIN_000 (0<<13)
1041#define DPIO_PCS_TX2MARGIN_101 (1<<13)
1042#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1043#define DPIO_PCS_TX1MARGIN_000 (0<<10)
1044#define DPIO_PCS_TX1MARGIN_101 (1<<10)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001045#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001046
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001047#define _VLV_PCS01_DW9_CH0 0x224
1048#define _VLV_PCS23_DW9_CH0 0x424
1049#define _VLV_PCS01_DW9_CH1 0x2624
1050#define _VLV_PCS23_DW9_CH1 0x2824
1051#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1052#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1053
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001054#define _CHV_PCS_DW10_CH0 0x8228
1055#define _CHV_PCS_DW10_CH1 0x8428
1056#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1057#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03001058#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1059#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1060#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1061#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1062#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1063#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001064#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1065
Ville Syrjälä1966e592014-04-09 13:29:04 +03001066#define _VLV_PCS01_DW10_CH0 0x0228
1067#define _VLV_PCS23_DW10_CH0 0x0428
1068#define _VLV_PCS01_DW10_CH1 0x2628
1069#define _VLV_PCS23_DW10_CH1 0x2828
1070#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1071#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1072
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001073#define _VLV_PCS_DW11_CH0 0x822c
1074#define _VLV_PCS_DW11_CH1 0x842c
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001075#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001076#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1077#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1078#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001079#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001080
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001081#define _VLV_PCS01_DW11_CH0 0x022c
1082#define _VLV_PCS23_DW11_CH0 0x042c
1083#define _VLV_PCS01_DW11_CH1 0x262c
1084#define _VLV_PCS23_DW11_CH1 0x282c
Ville Syrjälä142d2ec2014-10-16 20:52:32 +03001085#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1086#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
Ville Syrjälä570e2a72014-08-18 14:42:46 +03001087
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001088#define _VLV_PCS01_DW12_CH0 0x0230
1089#define _VLV_PCS23_DW12_CH0 0x0430
1090#define _VLV_PCS01_DW12_CH1 0x2630
1091#define _VLV_PCS23_DW12_CH1 0x2830
1092#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1093#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1094
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001095#define _VLV_PCS_DW12_CH0 0x8230
1096#define _VLV_PCS_DW12_CH1 0x8430
Ville Syrjälä2e523e92015-04-10 18:21:27 +03001097#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1098#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1099#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1100#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1101#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001102#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001103
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001104#define _VLV_PCS_DW14_CH0 0x8238
1105#define _VLV_PCS_DW14_CH1 0x8438
1106#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001107
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001108#define _VLV_PCS_DW23_CH0 0x825c
1109#define _VLV_PCS_DW23_CH1 0x845c
1110#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001111
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001112#define _VLV_TX_DW2_CH0 0x8288
1113#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001114#define DPIO_SWING_MARGIN000_SHIFT 16
1115#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001116#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001117#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001118
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001119#define _VLV_TX_DW3_CH0 0x828c
1120#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001121/* The following bit for CHV phy */
1122#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001123#define DPIO_SWING_MARGIN101_SHIFT 16
1124#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001125#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1126
1127#define _VLV_TX_DW4_CH0 0x8290
1128#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001129#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1130#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001131#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1132#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001133#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1134
1135#define _VLV_TX3_DW4_CH0 0x690
1136#define _VLV_TX3_DW4_CH1 0x2a90
1137#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1138
1139#define _VLV_TX_DW5_CH0 0x8294
1140#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +02001141#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001142#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001143
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001144#define _VLV_TX_DW11_CH0 0x82ac
1145#define _VLV_TX_DW11_CH1 0x84ac
1146#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001147
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001148#define _VLV_TX_DW14_CH0 0x82b8
1149#define _VLV_TX_DW14_CH1 0x84b8
1150#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301151
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001152/* CHV dpPhy registers */
1153#define _CHV_PLL_DW0_CH0 0x8000
1154#define _CHV_PLL_DW0_CH1 0x8180
1155#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1156
1157#define _CHV_PLL_DW1_CH0 0x8004
1158#define _CHV_PLL_DW1_CH1 0x8184
1159#define DPIO_CHV_N_DIV_SHIFT 8
1160#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1161#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1162
1163#define _CHV_PLL_DW2_CH0 0x8008
1164#define _CHV_PLL_DW2_CH1 0x8188
1165#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1166
1167#define _CHV_PLL_DW3_CH0 0x800c
1168#define _CHV_PLL_DW3_CH1 0x818c
1169#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1170#define DPIO_CHV_FIRST_MOD (0 << 8)
1171#define DPIO_CHV_SECOND_MOD (1 << 8)
1172#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05301173#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001174#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1175
1176#define _CHV_PLL_DW6_CH0 0x8018
1177#define _CHV_PLL_DW6_CH1 0x8198
1178#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1179#define DPIO_CHV_INT_COEFF_SHIFT 8
1180#define DPIO_CHV_PROP_COEFF_SHIFT 0
1181#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1182
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301183#define _CHV_PLL_DW8_CH0 0x8020
1184#define _CHV_PLL_DW8_CH1 0x81A0
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05301185#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1186#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301187#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1188
1189#define _CHV_PLL_DW9_CH0 0x8024
1190#define _CHV_PLL_DW9_CH1 0x81A4
1191#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05301192#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301193#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1194#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1195
Ville Syrjälä6669e392015-07-08 23:46:00 +03001196#define _CHV_CMN_DW0_CH0 0x8100
1197#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1198#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1199#define DPIO_ALLDL_POWERDOWN (1 << 1)
1200#define DPIO_ANYDL_POWERDOWN (1 << 0)
1201
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001202#define _CHV_CMN_DW5_CH0 0x8114
1203#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1204#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1205#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1206#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1207#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1208#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1209#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1210#define CHV_BUFLEFTENA1_MASK (3 << 22)
1211
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001212#define _CHV_CMN_DW13_CH0 0x8134
1213#define _CHV_CMN_DW0_CH1 0x8080
1214#define DPIO_CHV_S1_DIV_SHIFT 21
1215#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1216#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1217#define DPIO_CHV_K_DIV_SHIFT 4
1218#define DPIO_PLL_FREQLOCK (1 << 1)
1219#define DPIO_PLL_LOCK (1 << 0)
1220#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1221
1222#define _CHV_CMN_DW14_CH0 0x8138
1223#define _CHV_CMN_DW1_CH1 0x8084
1224#define DPIO_AFC_RECAL (1 << 14)
1225#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001226#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1227#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1228#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1229#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1230#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1231#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1232#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1233#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001234#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1235
Ville Syrjälä9197c882014-04-09 13:29:05 +03001236#define _CHV_CMN_DW19_CH0 0x814c
1237#define _CHV_CMN_DW6_CH1 0x8098
Ville Syrjälä6669e392015-07-08 23:46:00 +03001238#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1239#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001240#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
Ville Syrjälä9197c882014-04-09 13:29:05 +03001241#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001242
Ville Syrjälä9197c882014-04-09 13:29:05 +03001243#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1244
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001245#define CHV_CMN_DW28 0x8170
1246#define DPIO_CL1POWERDOWNEN (1 << 23)
1247#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
Ville Syrjäläee279212015-07-08 23:45:57 +03001248#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1249#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1250#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1251#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001252
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001253#define CHV_CMN_DW30 0x8178
Ville Syrjälä3e288782015-07-08 23:45:58 +03001254#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001255#define DPIO_LRC_BYPASS (1 << 3)
1256
1257#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1258 (lane) * 0x200 + (offset))
1259
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001260#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1261#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1262#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1263#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1264#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1265#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1266#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1267#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1268#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1269#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1270#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001271#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1272#define DPIO_FRC_LATENCY_SHFIT 8
1273#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1274#define DPIO_UPAR_SHIFT 30
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301275
1276/* BXT PHY registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001277#define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b))
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301278
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001279#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301280#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1281
1282#define _PHY_CTL_FAMILY_EDP 0x64C80
1283#define _PHY_CTL_FAMILY_DDI 0x64C90
1284#define COMMON_RESET_DIS (1 << 31)
1285#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1286 _PHY_CTL_FAMILY_EDP)
1287
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301288/* BXT PHY PLL registers */
1289#define _PORT_PLL_A 0x46074
1290#define _PORT_PLL_B 0x46078
1291#define _PORT_PLL_C 0x4607c
1292#define PORT_PLL_ENABLE (1 << 31)
1293#define PORT_PLL_LOCK (1 << 30)
1294#define PORT_PLL_REF_SEL (1 << 27)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001295#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301296
1297#define _PORT_PLL_EBB_0_A 0x162034
1298#define _PORT_PLL_EBB_0_B 0x6C034
1299#define _PORT_PLL_EBB_0_C 0x6C340
Imre Deakaa610dc2015-06-22 23:35:52 +03001300#define PORT_PLL_P1_SHIFT 13
1301#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1302#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1303#define PORT_PLL_P2_SHIFT 8
1304#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1305#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001306#define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301307 _PORT_PLL_EBB_0_B, \
1308 _PORT_PLL_EBB_0_C)
1309
1310#define _PORT_PLL_EBB_4_A 0x162038
1311#define _PORT_PLL_EBB_4_B 0x6C038
1312#define _PORT_PLL_EBB_4_C 0x6C344
1313#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1314#define PORT_PLL_RECALIBRATE (1 << 14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001315#define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301316 _PORT_PLL_EBB_4_B, \
1317 _PORT_PLL_EBB_4_C)
1318
1319#define _PORT_PLL_0_A 0x162100
1320#define _PORT_PLL_0_B 0x6C100
1321#define _PORT_PLL_0_C 0x6C380
1322/* PORT_PLL_0_A */
1323#define PORT_PLL_M2_MASK 0xFF
1324/* PORT_PLL_1_A */
Imre Deakaa610dc2015-06-22 23:35:52 +03001325#define PORT_PLL_N_SHIFT 8
1326#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1327#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301328/* PORT_PLL_2_A */
1329#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1330/* PORT_PLL_3_A */
1331#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1332/* PORT_PLL_6_A */
1333#define PORT_PLL_PROP_COEFF_MASK 0xF
1334#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1335#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1336#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1337#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1338/* PORT_PLL_8_A */
1339#define PORT_PLL_TARGET_CNT_MASK 0x3FF
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301340/* PORT_PLL_9_A */
Imre Deak05712c12015-06-18 17:25:54 +03001341#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1342#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301343/* PORT_PLL_10_A */
1344#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
Vandana Kannane6292552015-07-01 17:02:57 +05301345#define PORT_PLL_DCO_AMP_DEFAULT 15
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301346#define PORT_PLL_DCO_AMP_MASK 0x3c00
Ville Syrjälä68d97532015-09-18 20:03:39 +03001347#define PORT_PLL_DCO_AMP(x) ((x)<<10)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301348#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1349 _PORT_PLL_0_B, \
1350 _PORT_PLL_0_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001351#define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301352
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301353/* BXT PHY common lane registers */
1354#define _PORT_CL1CM_DW0_A 0x162000
1355#define _PORT_CL1CM_DW0_BC 0x6C000
1356#define PHY_POWER_GOOD (1 << 16)
Vandana Kannanb61e7992016-03-31 23:15:54 +05301357#define PHY_RESERVED (1 << 7)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301358#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1359 _PORT_CL1CM_DW0_A)
1360
1361#define _PORT_CL1CM_DW9_A 0x162024
1362#define _PORT_CL1CM_DW9_BC 0x6C024
1363#define IREF0RC_OFFSET_SHIFT 8
1364#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1365#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1366 _PORT_CL1CM_DW9_A)
1367
1368#define _PORT_CL1CM_DW10_A 0x162028
1369#define _PORT_CL1CM_DW10_BC 0x6C028
1370#define IREF1RC_OFFSET_SHIFT 8
1371#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1372#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1373 _PORT_CL1CM_DW10_A)
1374
1375#define _PORT_CL1CM_DW28_A 0x162070
1376#define _PORT_CL1CM_DW28_BC 0x6C070
1377#define OCL1_POWER_DOWN_EN (1 << 23)
1378#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1379#define SUS_CLK_CONFIG 0x3
1380#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1381 _PORT_CL1CM_DW28_A)
1382
1383#define _PORT_CL1CM_DW30_A 0x162078
1384#define _PORT_CL1CM_DW30_BC 0x6C078
1385#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1386#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1387 _PORT_CL1CM_DW30_A)
1388
1389/* Defined for PHY0 only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001390#define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301391#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1392
1393/* BXT PHY Ref registers */
1394#define _PORT_REF_DW3_A 0x16218C
1395#define _PORT_REF_DW3_BC 0x6C18C
1396#define GRC_DONE (1 << 22)
1397#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1398 _PORT_REF_DW3_A)
1399
1400#define _PORT_REF_DW6_A 0x162198
1401#define _PORT_REF_DW6_BC 0x6C198
Imre Deakd1e082f2016-04-01 16:02:33 +03001402#define GRC_CODE_SHIFT 24
1403#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301404#define GRC_CODE_FAST_SHIFT 16
Imre Deakd1e082f2016-04-01 16:02:33 +03001405#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301406#define GRC_CODE_SLOW_SHIFT 8
1407#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1408#define GRC_CODE_NOM_MASK 0xFF
1409#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1410 _PORT_REF_DW6_A)
1411
1412#define _PORT_REF_DW8_A 0x1621A0
1413#define _PORT_REF_DW8_BC 0x6C1A0
1414#define GRC_DIS (1 << 15)
1415#define GRC_RDY_OVRD (1 << 1)
1416#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1417 _PORT_REF_DW8_A)
1418
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301419/* BXT PHY PCS registers */
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301420#define _PORT_PCS_DW10_LN01_A 0x162428
1421#define _PORT_PCS_DW10_LN01_B 0x6C428
1422#define _PORT_PCS_DW10_LN01_C 0x6C828
1423#define _PORT_PCS_DW10_GRP_A 0x162C28
1424#define _PORT_PCS_DW10_GRP_B 0x6CC28
1425#define _PORT_PCS_DW10_GRP_C 0x6CE28
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001426#define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301427 _PORT_PCS_DW10_LN01_B, \
1428 _PORT_PCS_DW10_LN01_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001429#define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301430 _PORT_PCS_DW10_GRP_B, \
1431 _PORT_PCS_DW10_GRP_C)
1432#define TX2_SWING_CALC_INIT (1 << 31)
1433#define TX1_SWING_CALC_INIT (1 << 30)
1434
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301435#define _PORT_PCS_DW12_LN01_A 0x162430
1436#define _PORT_PCS_DW12_LN01_B 0x6C430
1437#define _PORT_PCS_DW12_LN01_C 0x6C830
1438#define _PORT_PCS_DW12_LN23_A 0x162630
1439#define _PORT_PCS_DW12_LN23_B 0x6C630
1440#define _PORT_PCS_DW12_LN23_C 0x6CA30
1441#define _PORT_PCS_DW12_GRP_A 0x162c30
1442#define _PORT_PCS_DW12_GRP_B 0x6CC30
1443#define _PORT_PCS_DW12_GRP_C 0x6CE30
1444#define LANESTAGGER_STRAP_OVRD (1 << 6)
1445#define LANE_STAGGER_MASK 0x1F
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001446#define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301447 _PORT_PCS_DW12_LN01_B, \
1448 _PORT_PCS_DW12_LN01_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001449#define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301450 _PORT_PCS_DW12_LN23_B, \
1451 _PORT_PCS_DW12_LN23_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001452#define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301453 _PORT_PCS_DW12_GRP_B, \
1454 _PORT_PCS_DW12_GRP_C)
1455
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301456/* BXT PHY TX registers */
1457#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1458 ((lane) & 1) * 0x80)
1459
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301460#define _PORT_TX_DW2_LN0_A 0x162508
1461#define _PORT_TX_DW2_LN0_B 0x6C508
1462#define _PORT_TX_DW2_LN0_C 0x6C908
1463#define _PORT_TX_DW2_GRP_A 0x162D08
1464#define _PORT_TX_DW2_GRP_B 0x6CD08
1465#define _PORT_TX_DW2_GRP_C 0x6CF08
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001466#define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301467 _PORT_TX_DW2_GRP_B, \
1468 _PORT_TX_DW2_GRP_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001469#define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301470 _PORT_TX_DW2_LN0_B, \
1471 _PORT_TX_DW2_LN0_C)
1472#define MARGIN_000_SHIFT 16
1473#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1474#define UNIQ_TRANS_SCALE_SHIFT 8
1475#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1476
1477#define _PORT_TX_DW3_LN0_A 0x16250C
1478#define _PORT_TX_DW3_LN0_B 0x6C50C
1479#define _PORT_TX_DW3_LN0_C 0x6C90C
1480#define _PORT_TX_DW3_GRP_A 0x162D0C
1481#define _PORT_TX_DW3_GRP_B 0x6CD0C
1482#define _PORT_TX_DW3_GRP_C 0x6CF0C
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001483#define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301484 _PORT_TX_DW3_GRP_B, \
1485 _PORT_TX_DW3_GRP_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001486#define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301487 _PORT_TX_DW3_LN0_B, \
1488 _PORT_TX_DW3_LN0_C)
Sonika Jindal9c58a042015-09-24 10:22:54 +05301489#define SCALE_DCOMP_METHOD (1 << 26)
1490#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301491
1492#define _PORT_TX_DW4_LN0_A 0x162510
1493#define _PORT_TX_DW4_LN0_B 0x6C510
1494#define _PORT_TX_DW4_LN0_C 0x6C910
1495#define _PORT_TX_DW4_GRP_A 0x162D10
1496#define _PORT_TX_DW4_GRP_B 0x6CD10
1497#define _PORT_TX_DW4_GRP_C 0x6CF10
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001498#define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301499 _PORT_TX_DW4_LN0_B, \
1500 _PORT_TX_DW4_LN0_C)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001501#define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301502 _PORT_TX_DW4_GRP_B, \
1503 _PORT_TX_DW4_GRP_C)
1504#define DEEMPH_SHIFT 24
1505#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1506
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301507#define _PORT_TX_DW14_LN0_A 0x162538
1508#define _PORT_TX_DW14_LN0_B 0x6C538
1509#define _PORT_TX_DW14_LN0_C 0x6C938
1510#define LATENCY_OPTIM_SHIFT 30
1511#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001512#define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301513 _PORT_TX_DW14_LN0_B, \
1514 _PORT_TX_DW14_LN0_C) + \
1515 _BXT_LANE_OFFSET(lane))
1516
David Weinehallf8896f52015-06-25 11:11:03 +03001517/* UAIMI scratch pad register 1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001518#define UAIMI_SPR1 _MMIO(0x4F074)
David Weinehallf8896f52015-06-25 11:11:03 +03001519/* SKL VccIO mask */
1520#define SKL_VCCIO_MASK 0x1
1521/* SKL balance leg register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001522#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
David Weinehallf8896f52015-06-25 11:11:03 +03001523/* I_boost values */
1524#define BALANCE_LEG_SHIFT(port) (8+3*(port))
1525#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1526/* Balance leg disable bits */
1527#define BALANCE_LEG_DISABLE_SHIFT 23
1528
Jesse Barnes585fb112008-07-29 11:54:06 -07001529/*
Jesse Barnesde151cf2008-11-12 10:03:55 -08001530 * Fence registers
Ville Syrjäläeecf6132015-09-21 18:05:14 +03001531 * [0-7] @ 0x2000 gen2,gen3
1532 * [8-15] @ 0x3000 945,g33,pnv
1533 *
1534 * [0-15] @ 0x3000 gen4,gen5
1535 *
1536 * [0-15] @ 0x100000 gen6,vlv,chv
1537 * [0-31] @ 0x100000 gen7+
Jesse Barnesde151cf2008-11-12 10:03:55 -08001538 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001539#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001540#define I830_FENCE_START_MASK 0x07f80000
1541#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -08001542#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001543#define I830_FENCE_PITCH_SHIFT 4
1544#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02001545#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07001546#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001547#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001548
1549#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08001550#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001551
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001552#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
1553#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001554#define I965_FENCE_PITCH_SHIFT 2
1555#define I965_FENCE_TILING_Y_SHIFT 1
1556#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001557#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08001558
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001559#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
1560#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
Ville Syrjäläeecf6132015-09-21 18:05:14 +03001561#define GEN6_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03001562#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07001563
Deepak S2b6b3a02014-05-27 15:59:30 +05301564
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001565/* control register for cpu gtt access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001566#define TILECTL _MMIO(0x101000)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001567#define TILECTL_SWZCTL (1 << 0)
Robert Beckette3a29052015-03-11 10:28:25 +02001568#define TILECTL_TLBPF (1 << 1)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001569#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1570#define TILECTL_BACKSNOOP_DIS (1 << 3)
1571
Jesse Barnesde151cf2008-11-12 10:03:55 -08001572/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001573 * Instruction and interrupt control regs
1574 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001575#define PGTBL_CTL _MMIO(0x02020)
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03001576#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1577#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001578#define PGTBL_ER _MMIO(0x02024)
1579#define PRB0_BASE (0x2030-0x30)
1580#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1581#define PRB2_BASE (0x2050-0x30) /* gen3 */
1582#define SRB0_BASE (0x2100-0x30) /* gen2 */
1583#define SRB1_BASE (0x2110-0x30) /* gen2 */
1584#define SRB2_BASE (0x2120-0x30) /* 830 */
1585#define SRB3_BASE (0x2130-0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02001586#define RENDER_RING_BASE 0x02000
1587#define BSD_RING_BASE 0x04000
1588#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08001589#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -07001590#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +01001591#define BLT_RING_BASE 0x22000
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001592#define RING_TAIL(base) _MMIO((base)+0x30)
1593#define RING_HEAD(base) _MMIO((base)+0x34)
1594#define RING_START(base) _MMIO((base)+0x38)
1595#define RING_CTL(base) _MMIO((base)+0x3c)
1596#define RING_SYNC_0(base) _MMIO((base)+0x40)
1597#define RING_SYNC_1(base) _MMIO((base)+0x44)
1598#define RING_SYNC_2(base) _MMIO((base)+0x48)
Ben Widawsky1950de12013-05-28 19:22:20 -07001599#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1600#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1601#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1602#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1603#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1604#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1605#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1606#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1607#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1608#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1609#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1610#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001611#define GEN6_NOSYNC INVALID_MMIO_REG
1612#define RING_PSMI_CTL(base) _MMIO((base)+0x50)
1613#define RING_MAX_IDLE(base) _MMIO((base)+0x54)
1614#define RING_HWS_PGA(base) _MMIO((base)+0x80)
1615#define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
1616#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
Mika Kuoppala7fd2d262015-06-18 12:51:40 +03001617#define RESET_CTL_REQUEST_RESET (1 << 0)
1618#define RESET_CTL_READY_TO_RESET (1 << 1)
Imre Deak9e72b462014-05-05 15:13:55 +03001619
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001620#define HSW_GTT_CACHE_EN _MMIO(0x4024)
Ville Syrjälä6d50b062015-05-19 20:32:57 +03001621#define GTT_CACHE_EN_ALL 0xF0007FFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001622#define GEN7_WR_WATERMARK _MMIO(0x4028)
1623#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
1624#define ARB_MODE _MMIO(0x4030)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001625#define ARB_MODE_SWIZZLE_SNB (1<<4)
1626#define ARB_MODE_SWIZZLE_IVB (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001627#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
1628#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
Imre Deak9e72b462014-05-05 15:13:55 +03001629/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001630#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03001631#define GEN7_LRA_LIMITS_REG_NUM 13
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001632#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
1633#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
Imre Deak9e72b462014-05-05 15:13:55 +03001634
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001635#define GAMTARBMODE _MMIO(0x04a08)
Ben Widawsky4afe8d32013-11-02 21:07:55 -07001636#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07001637#define ARB_MODE_SWIZZLE_BDW (1<<1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001638#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
1639#define RING_FAULT_REG(ring) _MMIO(0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -07001640#define RING_FAULT_GTTSEL_MASK (1<<11)
Ville Syrjälä68d97532015-09-18 20:03:39 +03001641#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1642#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
Ben Widawsky828c7902013-10-16 09:21:30 -07001643#define RING_FAULT_VALID (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001644#define DONE_REG _MMIO(0x40b0)
1645#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
1646#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
1647#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
1648#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
1649#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
1650#define RING_ACTHD(base) _MMIO((base)+0x74)
1651#define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
1652#define RING_NOPID(base) _MMIO((base)+0x94)
1653#define RING_IMR(base) _MMIO((base)+0xa8)
1654#define RING_HWSTAM(base) _MMIO((base)+0x98)
1655#define RING_TIMESTAMP(base) _MMIO((base)+0x358)
1656#define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07001657#define TAIL_ADDR 0x001FFFF8
1658#define HEAD_WRAP_COUNT 0xFFE00000
1659#define HEAD_WRAP_ONE 0x00200000
1660#define HEAD_ADDR 0x001FFFFC
1661#define RING_NR_PAGES 0x001FF000
1662#define RING_REPORT_MASK 0x00000006
1663#define RING_REPORT_64K 0x00000002
1664#define RING_REPORT_128K 0x00000004
1665#define RING_NO_REPORT 0x00000000
1666#define RING_VALID_MASK 0x00000001
1667#define RING_VALID 0x00000001
1668#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01001669#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1670#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001671#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03001672
Arun Siluvery33136b02016-01-21 21:43:47 +00001673#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
1674#define RING_MAX_NONPRIV_SLOTS 12
1675
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001676#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
Imre Deak9e72b462014-05-05 15:13:55 +03001677
Mika Kuoppalac0b730d2016-06-07 17:19:06 +03001678#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
1679#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
1680
Chris Wilson8168bd42010-11-11 17:54:52 +00001681#if 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001682#define PRB0_TAIL _MMIO(0x2030)
1683#define PRB0_HEAD _MMIO(0x2034)
1684#define PRB0_START _MMIO(0x2038)
1685#define PRB0_CTL _MMIO(0x203c)
1686#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
1687#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
1688#define PRB1_START _MMIO(0x2048) /* 915+ only */
1689#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00001690#endif
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001691#define IPEIR_I965 _MMIO(0x2064)
1692#define IPEHR_I965 _MMIO(0x2068)
1693#define GEN7_SC_INSTDONE _MMIO(0x7100)
1694#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1695#define GEN7_ROW_INSTDONE _MMIO(0xe164)
Ben Widawskyd53bd482012-08-22 11:32:14 -07001696#define I915_NUM_INSTDONE_REG 4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001697#define RING_IPEIR(base) _MMIO((base)+0x64)
1698#define RING_IPEHR(base) _MMIO((base)+0x68)
Imre Deakf1d54342015-09-30 23:00:42 +03001699/*
1700 * On GEN4, only the render ring INSTDONE exists and has a different
1701 * layout than the GEN7+ version.
Imre Deakbd93a502015-09-30 23:00:43 +03001702 * The GEN2 counterpart of this register is GEN2_INSTDONE.
Imre Deakf1d54342015-09-30 23:00:42 +03001703 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001704#define RING_INSTDONE(base) _MMIO((base)+0x6c)
1705#define RING_INSTPS(base) _MMIO((base)+0x70)
1706#define RING_DMA_FADD(base) _MMIO((base)+0x78)
1707#define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
1708#define RING_INSTPM(base) _MMIO((base)+0xc0)
1709#define RING_MI_MODE(base) _MMIO((base)+0x9c)
1710#define INSTPS _MMIO(0x2070) /* 965+ only */
1711#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
1712#define ACTHD_I965 _MMIO(0x2074)
1713#define HWS_PGA _MMIO(0x2080)
Jesse Barnes585fb112008-07-29 11:54:06 -07001714#define HWS_ADDRESS_MASK 0xfffff000
1715#define HWS_START_ADDRESS_SHIFT 4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001716#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
Jesse Barnes97f5ab62009-10-08 10:16:48 -07001717#define PWRCTX_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001718#define IPEIR _MMIO(0x2088)
1719#define IPEHR _MMIO(0x208c)
1720#define GEN2_INSTDONE _MMIO(0x2090)
1721#define NOPID _MMIO(0x2094)
1722#define HWSTAM _MMIO(0x2098)
1723#define DMA_FADD_I8XX _MMIO(0x20d0)
1724#define RING_BBSTATE(base) _MMIO((base)+0x110)
Ville Syrjälä35dc3f92015-11-04 23:20:10 +02001725#define RING_BB_PPGTT (1 << 5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001726#define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
1727#define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
1728#define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
1729#define RING_BBADDR(base) _MMIO((base)+0x140)
1730#define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
1731#define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
1732#define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
1733#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
1734#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08001735
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001736#define ERROR_GEN6 _MMIO(0x40a0)
1737#define GEN7_ERR_INT _MMIO(0x44040)
Paulo Zanonide032bf2013-04-12 17:57:58 -03001738#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03001739#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001740#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03001741#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001742#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03001743#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001744#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Ville Syrjälä68d97532015-09-18 20:03:39 +03001745#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03001746#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03001747#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01001748
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001749#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
1750#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
Mika Kuoppala6c826f32015-03-24 14:54:19 +02001751
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001752#define FPGA_DBG _MMIO(0x42300)
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03001753#define FPGA_DBG_RM_NOCLAIM (1<<31)
1754
Mika Kuoppala8ac3e1b2015-12-15 19:45:42 +02001755#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
1756#define CLAIM_ER_CLR (1 << 31)
1757#define CLAIM_ER_OVERFLOW (1 << 16)
1758#define CLAIM_ER_CTR_MASK 0xffff
1759
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001760#define DERRMR _MMIO(0x44050)
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001761/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01001762#define DERRMR_PIPEA_SCANLINE (1<<0)
1763#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1764#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1765#define DERRMR_PIPEA_VBLANK (1<<3)
1766#define DERRMR_PIPEA_HBLANK (1<<5)
1767#define DERRMR_PIPEB_SCANLINE (1<<8)
1768#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1769#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1770#define DERRMR_PIPEB_VBLANK (1<<11)
1771#define DERRMR_PIPEB_HBLANK (1<<13)
1772/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1773#define DERRMR_PIPEC_SCANLINE (1<<14)
1774#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1775#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1776#define DERRMR_PIPEC_VBLANK (1<<21)
1777#define DERRMR_PIPEC_HBLANK (1<<22)
1778
Chris Wilson0f3b6842013-01-15 12:05:55 +00001779
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001780/* GM45+ chicken bits -- debug workaround bits that may be required
1781 * for various sorts of correct behavior. The top 16 bits of each are
1782 * the enables for writing to the corresponding low bit.
1783 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001784#define _3D_CHICKEN _MMIO(0x2084)
Daniel Vetter42839082012-12-14 23:38:28 +01001785#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001786#define _3D_CHICKEN2 _MMIO(0x208c)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001787/* Disables pipelining of read flushes past the SF-WIZ interface.
1788 * Required on all Ironlake steppings according to the B-Spec, but the
1789 * particular danger of not doing so is not specified.
1790 */
1791# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001792#define _3D_CHICKEN3 _MMIO(0x2090)
Jesse Barnes87f80202012-10-02 17:43:41 -05001793#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07001794#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02001795#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1796#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001797
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001798#define MI_MODE _MMIO(0x209c)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001799# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08001800# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00001801# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301802# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01001803# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001804
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001805#define GEN6_GT_MODE _MMIO(0x20d0)
1806#define GEN7_GT_MODE _MMIO(0x7008)
Ville Syrjälä8d85d272014-02-04 21:59:15 +02001807#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1808#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1809#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1810#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
Damien Lespiau98533252014-12-08 17:33:51 +00001811#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001812#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ville Syrjälä68d97532015-09-18 20:03:39 +03001813#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1814#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001815
Tim Gorea8ab5ed2016-06-13 12:15:01 +01001816/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
1817#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
1818#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
1819
Tim Goreb1e429f2016-03-21 14:37:29 +00001820/* WaClearTdlStateAckDirtyBits */
1821#define GEN8_STATE_ACK _MMIO(0x20F0)
1822#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
1823#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
1824#define GEN9_STATE_ACK_TDL0 (1 << 12)
1825#define GEN9_STATE_ACK_TDL1 (1 << 13)
1826#define GEN9_STATE_ACK_TDL2 (1 << 14)
1827#define GEN9_STATE_ACK_TDL3 (1 << 15)
1828#define GEN9_SUBSLICE_TDL_ACK_BITS \
1829 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
1830 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
1831
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001832#define GFX_MODE _MMIO(0x2520)
1833#define GFX_MODE_GEN7 _MMIO(0x229c)
1834#define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001835#define GFX_RUN_LIST_ENABLE (1<<15)
Dave Gordon4df001d2015-08-12 15:43:42 +01001836#define GFX_INTERRUPT_STEERING (1<<14)
Chris Wilsonaa83e302014-03-21 17:18:54 +00001837#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001838#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1839#define GFX_REPLAY_MODE (1<<11)
1840#define GFX_PSMI_GRANULARITY (1<<10)
1841#define GFX_PPGTT_ENABLE (1<<9)
Michel Thierry2dba3232015-07-30 11:06:23 +01001842#define GEN8_GFX_PPGTT_48B (1<<7)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001843
Dave Gordon4df001d2015-08-12 15:43:42 +01001844#define GFX_FORWARD_VBLANK_MASK (3<<5)
1845#define GFX_FORWARD_VBLANK_NEVER (0<<5)
1846#define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
1847#define GFX_FORWARD_VBLANK_COND (2<<5)
1848
Daniel Vettera7e806d2012-07-11 16:27:55 +02001849#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301850#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Shashank Sharmac6c794a2016-03-22 12:01:50 +02001851#define BXT_MIPI_BASE 0x60000
Daniel Vettera7e806d2012-07-11 16:27:55 +02001852
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001853#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1854#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1855#define SCPD0 _MMIO(0x209c) /* 915+ only */
1856#define IER _MMIO(0x20a0)
1857#define IIR _MMIO(0x20a4)
1858#define IMR _MMIO(0x20a8)
1859#define ISR _MMIO(0x20ac)
1860#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001861#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07001862#define GCFG_DIS (1<<8)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001863#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1864#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1865#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1866#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1867#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1868#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1869#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05301870#define VLV_PCBR_ADDR_SHIFT 12
1871
Ville Syrjälä90a72f82013-02-19 23:16:44 +02001872#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001873#define EIR _MMIO(0x20b0)
1874#define EMR _MMIO(0x20b4)
1875#define ESR _MMIO(0x20b8)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001876#define GM45_ERROR_PAGE_TABLE (1<<5)
1877#define GM45_ERROR_MEM_PRIV (1<<4)
1878#define I915_ERROR_PAGE_TABLE (1<<4)
1879#define GM45_ERROR_CP_PRIV (1<<3)
1880#define I915_ERROR_MEMORY_REFRESH (1<<1)
1881#define I915_ERROR_INSTRUCTION (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001882#define INSTPM _MMIO(0x20c0)
Li Pengee980b82010-01-27 19:01:11 +08001883#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02001884#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00001885 will not assert AGPBUSY# and will only
1886 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08001887#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01001888#define INSTPM_TLB_INVALIDATE (1<<9)
1889#define INSTPM_SYNC_FLUSH (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001890#define ACTHD _MMIO(0x20c8)
1891#define MEM_MODE _MMIO(0x20cc)
Ville Syrjälä10383922014-08-15 01:21:54 +03001892#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1893#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1894#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001895#define FW_BLC _MMIO(0x20d8)
1896#define FW_BLC2 _MMIO(0x20dc)
1897#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08001898#define FW_BLC_SELF_EN_MASK (1<<31)
1899#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1900#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001901#define MM_BURST_LENGTH 0x00700000
1902#define MM_FIFO_WATERMARK 0x0001F000
1903#define LM_BURST_LENGTH 0x00000700
1904#define LM_FIFO_WATERMARK 0x0000001F
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001905#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07001906
1907/* Make render/texture TLB fetches lower priorty than associated data
1908 * fetches. This is not turned on by default
1909 */
1910#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1911
1912/* Isoch request wait on GTT enable (Display A/B/C streams).
1913 * Make isoch requests stall on the TLB update. May cause
1914 * display underruns (test mode only)
1915 */
1916#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1917
1918/* Block grant count for isoch requests when block count is
1919 * set to a finite value.
1920 */
1921#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1922#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1923#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1924#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1925#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1926
1927/* Enable render writes to complete in C2/C3/C4 power states.
1928 * If this isn't enabled, render writes are prevented in low
1929 * power states. That seems bad to me.
1930 */
1931#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1932
1933/* This acknowledges an async flip immediately instead
1934 * of waiting for 2TLB fetches.
1935 */
1936#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1937
1938/* Enables non-sequential data reads through arbiter
1939 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001940#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07001941
1942/* Disable FSB snooping of cacheable write cycles from binner/render
1943 * command stream
1944 */
1945#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1946
1947/* Arbiter time slice for non-isoch streams */
1948#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1949#define MI_ARB_TIME_SLICE_1 (0 << 5)
1950#define MI_ARB_TIME_SLICE_2 (1 << 5)
1951#define MI_ARB_TIME_SLICE_4 (2 << 5)
1952#define MI_ARB_TIME_SLICE_6 (3 << 5)
1953#define MI_ARB_TIME_SLICE_8 (4 << 5)
1954#define MI_ARB_TIME_SLICE_10 (5 << 5)
1955#define MI_ARB_TIME_SLICE_14 (6 << 5)
1956#define MI_ARB_TIME_SLICE_16 (7 << 5)
1957
1958/* Low priority grace period page size */
1959#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1960#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1961
1962/* Disable display A/B trickle feed */
1963#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1964
1965/* Set display plane priority */
1966#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1967#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1968
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001969#define MI_STATE _MMIO(0x20e4) /* gen2 only */
Ville Syrjälä54e472a2014-02-25 15:13:40 +02001970#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1971#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1972
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001973#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02001974#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001975#define CM0_IZ_OPT_DISABLE (1<<6)
1976#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02001977#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001978#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1979#define CM0_COLOR_EVICT_DISABLE (1<<3)
1980#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1981#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001982#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
1983#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001984#define GFX_FLSH_CNTL_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001985#define ECOSKPD _MMIO(0x21d0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07001986#define ECO_GATING_CX_ONLY (1<<3)
1987#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001988
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001989#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05301990#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08001991#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001992#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00001993#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1994#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Damien Lespiau9370cd92015-02-09 19:33:17 +00001995#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
Jesse Barnesfb046852012-03-28 13:39:26 -07001996
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001997#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
Jesse Barnes4efe0702011-01-18 11:25:41 -08001998#define GEN6_BLITTER_LOCK_SHIFT 16
1999#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2000
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002001#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
Chris Wilson2c550182014-12-16 10:02:27 +00002002#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02002003#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03002004#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02002005
Deepak S693d11c2015-01-16 20:42:16 +05302006/* Fuse readout registers for GT */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002007#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
Jeff McGeec93043a2015-02-27 12:12:28 -08002008#define CHV_FGT_DISABLE_SS0 (1 << 10)
2009#define CHV_FGT_DISABLE_SS1 (1 << 11)
Deepak S693d11c2015-01-16 20:42:16 +05302010#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2011#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2012#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2013#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2014#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2015#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2016#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2017#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2018
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002019#define GEN8_FUSE2 _MMIO(0x9120)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002020#define GEN8_F2_SS_DIS_SHIFT 21
2021#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
Jeff McGee38732182015-02-13 10:27:54 -06002022#define GEN8_F2_S_ENA_SHIFT 25
2023#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2024
2025#define GEN9_F2_SS_DIS_SHIFT 20
2026#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2027
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002028#define GEN8_EU_DISABLE0 _MMIO(0x9134)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002029#define GEN8_EU_DIS0_S0_MASK 0xffffff
2030#define GEN8_EU_DIS0_S1_SHIFT 24
2031#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2032
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002033#define GEN8_EU_DISABLE1 _MMIO(0x9138)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002034#define GEN8_EU_DIS1_S1_MASK 0xffff
2035#define GEN8_EU_DIS1_S2_SHIFT 16
2036#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2037
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002038#define GEN8_EU_DISABLE2 _MMIO(0x913c)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02002039#define GEN8_EU_DIS2_S2_MASK 0xff
2040
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002041#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
Jeff McGee38732182015-02-13 10:27:54 -06002042
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002043#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
Chris Wilson12f55812012-07-05 17:14:01 +01002044#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2045#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2046#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2047#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002048
Ben Widawskycc609d52013-05-28 19:22:29 -07002049/* On modern GEN architectures interrupt control consists of two sets
2050 * of registers. The first set pertains to the ring generating the
2051 * interrupt. The second control is for the functional block generating the
2052 * interrupt. These are PM, GT, DE, etc.
2053 *
2054 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2055 * GT interrupt bits, so we don't need to duplicate the defines.
2056 *
2057 * These defines should cover us well from SNB->HSW with minor exceptions
2058 * it can also work on ILK.
2059 */
2060#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2061#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2062#define GT_BLT_USER_INTERRUPT (1 << 22)
2063#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2064#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002065#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Oscar Mateo73d477f2014-07-24 17:04:31 +01002066#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07002067#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2068#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2069#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2070#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2071#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2072#define GT_RENDER_USER_INTERRUPT (1 << 0)
2073
Ben Widawsky12638c52013-05-28 19:22:31 -07002074#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2075#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2076
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002077#define GT_PARITY_ERROR(dev) \
2078 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +03002079 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002080
Ben Widawskycc609d52013-05-28 19:22:29 -07002081/* These are all the "old" interrupts */
2082#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002083
2084#define I915_PM_INTERRUPT (1<<31)
2085#define I915_ISP_INTERRUPT (1<<22)
2086#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2087#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02002088#define I915_MIPIC_INTERRUPT (1<<19)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002089#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07002090#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2091#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002092#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2093#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07002094#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002095#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07002096#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002097#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07002098#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002099#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07002100#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002101#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07002102#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002103#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07002104#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002105#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07002106#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002107#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07002108#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2109#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2110#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2111#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2112#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002113#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2114#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07002115#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002116#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07002117#define I915_USER_INTERRUPT (1<<1)
2118#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03002119#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002120
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002121#define GEN6_BSD_RNCID _MMIO(0x12198)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002122
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002123#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002124#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08002125#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002126#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2127#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2128#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2129#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08002130#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07002131#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2132#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2133#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2134#define GEN7_FF_VS_SCHED_HW (0x0<<12)
2135#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2136#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2137#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2138#define GEN7_FF_DS_SCHED_HW (0x0<<4)
2139
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002140/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002141 * Framebuffer compression (915+ only)
2142 */
2143
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002144#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2145#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2146#define FBC_CONTROL _MMIO(0x3208)
Jesse Barnes585fb112008-07-29 11:54:06 -07002147#define FBC_CTL_EN (1<<31)
2148#define FBC_CTL_PERIODIC (1<<30)
2149#define FBC_CTL_INTERVAL_SHIFT (16)
2150#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02002151#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07002152#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02002153#define FBC_CTL_FENCENO_SHIFT (0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002154#define FBC_COMMAND _MMIO(0x320c)
Jesse Barnes585fb112008-07-29 11:54:06 -07002155#define FBC_CMD_COMPRESS (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002156#define FBC_STATUS _MMIO(0x3210)
Jesse Barnes585fb112008-07-29 11:54:06 -07002157#define FBC_STAT_COMPRESSING (1<<31)
2158#define FBC_STAT_COMPRESSED (1<<30)
2159#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02002160#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002161#define FBC_CONTROL2 _MMIO(0x3214)
Jesse Barnes585fb112008-07-29 11:54:06 -07002162#define FBC_CTL_FENCE_DBL (0<<4)
2163#define FBC_CTL_IDLE_IMM (0<<2)
2164#define FBC_CTL_IDLE_FULL (1<<2)
2165#define FBC_CTL_IDLE_LINE (2<<2)
2166#define FBC_CTL_IDLE_DEBUG (3<<2)
2167#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02002168#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002169#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2170#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002171
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002172#define FBC_STATUS2 _MMIO(0x43214)
Paulo Zanoni31b9df12015-06-12 14:36:18 -03002173#define FBC_COMPRESSION_MASK 0x7ff
2174
Jesse Barnes585fb112008-07-29 11:54:06 -07002175#define FBC_LL_SIZE (1536)
2176
Mika Kuoppala44fff992016-06-07 17:19:09 +03002177#define FBC_LLC_READ_CTRL _MMIO(0x9044)
2178#define FBC_LLC_FULLY_OPEN (1<<30)
2179
Jesse Barnes74dff282009-09-14 15:39:40 -07002180/* Framebuffer compression for GM45+ */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002181#define DPFC_CB_BASE _MMIO(0x3200)
2182#define DPFC_CONTROL _MMIO(0x3208)
Jesse Barnes74dff282009-09-14 15:39:40 -07002183#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02002184#define DPFC_CTL_PLANE(plane) ((plane)<<30)
2185#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07002186#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002187#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01002188#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07002189#define DPFC_SR_EN (1<<10)
2190#define DPFC_CTL_LIMIT_1X (0<<6)
2191#define DPFC_CTL_LIMIT_2X (1<<6)
2192#define DPFC_CTL_LIMIT_4X (2<<6)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002193#define DPFC_RECOMP_CTL _MMIO(0x320c)
Jesse Barnes74dff282009-09-14 15:39:40 -07002194#define DPFC_RECOMP_STALL_EN (1<<27)
2195#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2196#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2197#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2198#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002199#define DPFC_STATUS _MMIO(0x3210)
Jesse Barnes74dff282009-09-14 15:39:40 -07002200#define DPFC_INVAL_SEG_SHIFT (16)
2201#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2202#define DPFC_COMP_SEG_SHIFT (0)
2203#define DPFC_COMP_SEG_MASK (0x000003ff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002204#define DPFC_STATUS2 _MMIO(0x3214)
2205#define DPFC_FENCE_YOFF _MMIO(0x3218)
2206#define DPFC_CHICKEN _MMIO(0x3224)
Jesse Barnes74dff282009-09-14 15:39:40 -07002207#define DPFC_HT_MODIFY (1<<31)
2208
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002209/* Framebuffer compression for Ironlake */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002210#define ILK_DPFC_CB_BASE _MMIO(0x43200)
2211#define ILK_DPFC_CONTROL _MMIO(0x43208)
Rodrigo Vivida46f932014-08-01 02:04:45 -07002212#define FBC_CTL_FALSE_COLOR (1<<10)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002213/* The bit 28-8 is reserved */
2214#define DPFC_RESERVED (0x1FFFFF00)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002215#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
2216#define ILK_DPFC_STATUS _MMIO(0x43210)
2217#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2218#define ILK_DPFC_CHICKEN _MMIO(0x43224)
Mika Kuoppalad1b4eef2016-06-07 17:19:19 +03002219#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
Mika Kuoppala031cd8c2016-06-07 17:19:18 +03002220#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002221#define ILK_FBC_RT_BASE _MMIO(0x2128)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002222#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002223#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002224
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002225#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002226#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04002227#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08002228
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002229
Jesse Barnes585fb112008-07-29 11:54:06 -07002230/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002231 * Framebuffer compression for Sandybridge
2232 *
2233 * The following two registers are of type GTTMMADR
2234 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002235#define SNB_DPFC_CTL_SA _MMIO(0x100100)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002236#define SNB_CPU_FENCE_ENABLE (1<<29)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002237#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002238
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002239/* Framebuffer compression for Ivybridge */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002240#define IVB_FBC_RT_BASE _MMIO(0x7020)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002241
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002242#define IPS_CTL _MMIO(0x43408)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03002243#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002244
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002245#define MSG_FBC_REND_STATE _MMIO(0x50380)
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03002246#define FBC_REND_NUKE (1<<2)
2247#define FBC_REND_CACHE_CLEAN (1<<1)
2248
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002249/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002250 * GPIO regs
2251 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002252#define GPIOA _MMIO(0x5010)
2253#define GPIOB _MMIO(0x5014)
2254#define GPIOC _MMIO(0x5018)
2255#define GPIOD _MMIO(0x501c)
2256#define GPIOE _MMIO(0x5020)
2257#define GPIOF _MMIO(0x5024)
2258#define GPIOG _MMIO(0x5028)
2259#define GPIOH _MMIO(0x502c)
Jesse Barnes585fb112008-07-29 11:54:06 -07002260# define GPIO_CLOCK_DIR_MASK (1 << 0)
2261# define GPIO_CLOCK_DIR_IN (0 << 1)
2262# define GPIO_CLOCK_DIR_OUT (1 << 1)
2263# define GPIO_CLOCK_VAL_MASK (1 << 2)
2264# define GPIO_CLOCK_VAL_OUT (1 << 3)
2265# define GPIO_CLOCK_VAL_IN (1 << 4)
2266# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2267# define GPIO_DATA_DIR_MASK (1 << 8)
2268# define GPIO_DATA_DIR_IN (0 << 9)
2269# define GPIO_DATA_DIR_OUT (1 << 9)
2270# define GPIO_DATA_VAL_MASK (1 << 10)
2271# define GPIO_DATA_VAL_OUT (1 << 11)
2272# define GPIO_DATA_VAL_IN (1 << 12)
2273# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2274
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002275#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002276#define GMBUS_RATE_100KHZ (0<<8)
2277#define GMBUS_RATE_50KHZ (1<<8)
2278#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2279#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2280#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
Jani Nikula988c7012015-03-27 00:20:19 +02002281#define GMBUS_PIN_DISABLED 0
2282#define GMBUS_PIN_SSC 1
2283#define GMBUS_PIN_VGADDC 2
2284#define GMBUS_PIN_PANEL 3
2285#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2286#define GMBUS_PIN_DPC 4 /* HDMIC */
2287#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2288#define GMBUS_PIN_DPD 6 /* HDMID */
2289#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
Jani Nikula4c272832015-04-01 10:58:05 +03002290#define GMBUS_PIN_1_BXT 1
2291#define GMBUS_PIN_2_BXT 2
2292#define GMBUS_PIN_3_BXT 3
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03002293#define GMBUS_NUM_PINS 7 /* including 0 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002294#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002295#define GMBUS_SW_CLR_INT (1<<31)
2296#define GMBUS_SW_RDY (1<<30)
2297#define GMBUS_ENT (1<<29) /* enable timeout */
2298#define GMBUS_CYCLE_NONE (0<<25)
2299#define GMBUS_CYCLE_WAIT (1<<25)
2300#define GMBUS_CYCLE_INDEX (2<<25)
2301#define GMBUS_CYCLE_STOP (4<<25)
2302#define GMBUS_BYTE_COUNT_SHIFT 16
Dmitry Torokhov9535c472015-04-21 09:49:11 -07002303#define GMBUS_BYTE_COUNT_MAX 256U
Chris Wilsonf899fc62010-07-20 15:44:45 -07002304#define GMBUS_SLAVE_INDEX_SHIFT 8
2305#define GMBUS_SLAVE_ADDR_SHIFT 1
2306#define GMBUS_SLAVE_READ (1<<0)
2307#define GMBUS_SLAVE_WRITE (0<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002308#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002309#define GMBUS_INUSE (1<<15)
2310#define GMBUS_HW_WAIT_PHASE (1<<14)
2311#define GMBUS_STALL_TIMEOUT (1<<13)
2312#define GMBUS_INT (1<<12)
2313#define GMBUS_HW_RDY (1<<11)
2314#define GMBUS_SATOER (1<<10)
2315#define GMBUS_ACTIVE (1<<9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002316#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2317#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002318#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2319#define GMBUS_NAK_EN (1<<3)
2320#define GMBUS_IDLE_EN (1<<2)
2321#define GMBUS_HW_WAIT_EN (1<<1)
2322#define GMBUS_HW_RDY_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002323#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002324#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08002325
Jesse Barnes585fb112008-07-29 11:54:06 -07002326/*
2327 * Clock control & power management
2328 */
Ville Syrjälä2d401b12014-04-09 13:29:08 +03002329#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2330#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2331#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002332#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07002333
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002334#define VGA0 _MMIO(0x6000)
2335#define VGA1 _MMIO(0x6004)
2336#define VGA_PD _MMIO(0x6010)
Jesse Barnes585fb112008-07-29 11:54:06 -07002337#define VGA0_PD_P2_DIV_4 (1 << 7)
2338#define VGA0_PD_P1_DIV_2 (1 << 5)
2339#define VGA0_PD_P1_SHIFT 0
2340#define VGA0_PD_P1_MASK (0x1f << 0)
2341#define VGA1_PD_P2_DIV_4 (1 << 15)
2342#define VGA1_PD_P1_DIV_2 (1 << 13)
2343#define VGA1_PD_P1_SHIFT 8
2344#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07002345#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02002346#define DPLL_SDVO_HIGH_SPEED (1 << 30)
2347#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07002348#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07002349#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03002350#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07002351#define DPLL_VGA_MODE_DIS (1 << 28)
2352#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2353#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2354#define DPLL_MODE_MASK (3 << 26)
2355#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2356#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2357#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2358#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2359#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2360#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002361#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07002362#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02002363#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03002364#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2365#define DPLL_SSC_REF_CLK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02002366#define DPLL_PORTC_READY_MASK (0xf << 4)
2367#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07002368
Jesse Barnes585fb112008-07-29 11:54:06 -07002369#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03002370
2371/* Additional CHV pll/phy registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002372#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03002373#define DPLL_PORTD_READY_MASK (0xf)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002374#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002375#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
Ville Syrjäläbc284542015-05-26 20:22:38 +03002376#define PHY_LDO_DELAY_0NS 0x0
2377#define PHY_LDO_DELAY_200NS 0x1
2378#define PHY_LDO_DELAY_600NS 0x2
2379#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002380#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
Ville Syrjälä70722462015-04-10 18:21:28 +03002381#define PHY_CH_SU_PSR 0x1
2382#define PHY_CH_DEEP_PSR 0x7
2383#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2384#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002385#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03002386#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
Ville Syrjälä30142272015-07-08 23:46:01 +03002387#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
2388#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03002389
Jesse Barnes585fb112008-07-29 11:54:06 -07002390/*
2391 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2392 * this field (only one bit may be set).
2393 */
2394#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2395#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002396#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07002397/* i830, required in DVO non-gang */
2398#define PLL_P2_DIVIDE_BY_4 (1 << 23)
2399#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2400#define PLL_REF_INPUT_DREFCLK (0 << 13)
2401#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2402#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2403#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2404#define PLL_REF_INPUT_MASK (3 << 13)
2405#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002406/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08002407# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2408# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2409# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2410# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2411# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2412
Jesse Barnes585fb112008-07-29 11:54:06 -07002413/*
2414 * Parallel to Serial Load Pulse phase selection.
2415 * Selects the phase for the 10X DPLL clock for the PCIe
2416 * digital display port. The range is 4 to 13; 10 or more
2417 * is just a flip delay. The default is 6
2418 */
2419#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2420#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2421/*
2422 * SDVO multiplier for 945G/GM. Not used on 965.
2423 */
2424#define SDVO_MULTIPLIER_MASK 0x000000ff
2425#define SDVO_MULTIPLIER_SHIFT_HIRES 4
2426#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002427
Ville Syrjälä2d401b12014-04-09 13:29:08 +03002428#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2429#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2430#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002431#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002432
Jesse Barnes585fb112008-07-29 11:54:06 -07002433/*
2434 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2435 *
2436 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2437 */
2438#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2439#define DPLL_MD_UDI_DIVIDER_SHIFT 24
2440/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2441#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2442#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2443/*
2444 * SDVO/UDI pixel multiplier.
2445 *
2446 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2447 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2448 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2449 * dummy bytes in the datastream at an increased clock rate, with both sides of
2450 * the link knowing how many bytes are fill.
2451 *
2452 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2453 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2454 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2455 * through an SDVO command.
2456 *
2457 * This register field has values of multiplication factor minus 1, with
2458 * a maximum multiplier of 5 for SDVO.
2459 */
2460#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2461#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2462/*
2463 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2464 * This best be set to the default value (3) or the CRT won't work. No,
2465 * I don't entirely understand what this does...
2466 */
2467#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2468#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07002469
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +03002470#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
2471
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002472#define _FPA0 0x6040
2473#define _FPA1 0x6044
2474#define _FPB0 0x6048
2475#define _FPB1 0x604c
2476#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
2477#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07002478#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002479#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07002480#define FP_N_DIV_SHIFT 16
2481#define FP_M1_DIV_MASK 0x00003f00
2482#define FP_M1_DIV_SHIFT 8
2483#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002484#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07002485#define FP_M2_DIV_SHIFT 0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002486#define DPLL_TEST _MMIO(0x606c)
Jesse Barnes585fb112008-07-29 11:54:06 -07002487#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2488#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2489#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2490#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2491#define DPLLB_TEST_N_BYPASS (1 << 19)
2492#define DPLLB_TEST_M_BYPASS (1 << 18)
2493#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2494#define DPLLA_TEST_N_BYPASS (1 << 3)
2495#define DPLLA_TEST_M_BYPASS (1 << 2)
2496#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002497#define D_STATE _MMIO(0x6104)
Chris Wilsondc96e9b2010-10-01 12:05:06 +01002498#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07002499#define DSTATE_PLL_D3_OFF (1<<3)
2500#define DSTATE_GFX_CLOCK_GATING (1<<1)
2501#define DSTATE_DOT_CLOCK_GATING (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002502#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07002503# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2504# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2505# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2506# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2507# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2508# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2509# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2510# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2511# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2512# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2513# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2514# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2515# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2516# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2517# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2518# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2519# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2520# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2521# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2522# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2523# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2524# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2525# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2526# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2527# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2528# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2529# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2530# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002531/*
Jesse Barnes652c3932009-08-17 13:31:43 -07002532 * This bit must be set on the 830 to prevent hangs when turning off the
2533 * overlay scaler.
2534 */
2535# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2536# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2537# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2538# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2539# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2540
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002541#define RENCLK_GATE_D1 _MMIO(0x6204)
Jesse Barnes652c3932009-08-17 13:31:43 -07002542# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2543# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2544# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2545# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2546# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2547# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2548# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2549# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2550# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002551/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07002552# define MECI_CLOCK_GATE_DISABLE (1 << 4)
2553# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2554# define MEC_CLOCK_GATE_DISABLE (1 << 2)
2555# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002556/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07002557# define SV_CLOCK_GATE_DISABLE (1 << 0)
2558# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2559# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2560# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2561# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2562# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2563# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2564# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2565# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2566# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2567# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2568# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2569# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2570# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2571# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2572# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2573# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2574# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2575
2576# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002577/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07002578# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2579# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2580# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2581# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2582# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2583# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002584/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07002585# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2586# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2587# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2588# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2589# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2590# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2591# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2592# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2593# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2594# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2595# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2596# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2597# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2598# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2599# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2600# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2601# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2602# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2603# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2604
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002605#define RENCLK_GATE_D2 _MMIO(0x6208)
Jesse Barnes652c3932009-08-17 13:31:43 -07002606#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2607#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2608#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03002609
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002610#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03002611#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2612
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002613#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
2614#define DEUC _MMIO(0x6214) /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002615
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002616#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07002617#define FW_CSPWRDWNEN (1<<15)
2618
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002619#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03002620
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002621#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002622#define CDCLK_FREQ_SHIFT 4
2623#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2624#define CZCLK_FREQ_MASK 0xf
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02002625
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002626#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02002627#define PFI_CREDIT_63 (9 << 28) /* chv only */
2628#define PFI_CREDIT_31 (8 << 28) /* chv only */
2629#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2630#define PFI_CREDIT_RESEND (1 << 27)
2631#define VGA_FAST_MODE_DISABLE (1 << 14)
2632
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002633#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002634
Jesse Barnes585fb112008-07-29 11:54:06 -07002635/*
2636 * Palette regs
2637 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002638#define PALETTE_A_OFFSET 0xa000
2639#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002640#define CHV_PALETTE_C_OFFSET 0xc000
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002641#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
2642 dev_priv->info.display_mmio_offset + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07002643
Eric Anholt673a3942008-07-30 12:06:12 -07002644/* MCH MMIO space */
2645
2646/*
2647 * MCHBAR mirror.
2648 *
2649 * This mirrors the MCHBAR MMIO space whose location is determined by
2650 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2651 * every way. It is not accessible from the CP register read instructions.
2652 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03002653 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2654 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07002655 */
2656#define MCHBAR_MIRROR_BASE 0x10000
2657
Yuanhan Liu13982612010-12-15 15:42:31 +08002658#define MCHBAR_MIRROR_BASE_SNB 0x140000
2659
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002660#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
2661#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
Ville Syrjälä7d316ae2015-09-16 21:28:50 +03002662#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
2663#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
2664
Chris Wilson3ebecd02013-04-12 19:10:13 +01002665/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002666#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01002667
Ville Syrjälä646b4262014-04-25 20:14:30 +03002668/* 915-945 and GM965 MCH register controlling DRAM channel access */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002669#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
Eric Anholt673a3942008-07-30 12:06:12 -07002670#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2671#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2672#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2673#define DCC_ADDRESSING_MODE_MASK (3 << 0)
2674#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08002675#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002676#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
Daniel Vetter656bfa32014-11-20 09:26:30 +01002677#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
Eric Anholt673a3942008-07-30 12:06:12 -07002678
Ville Syrjälä646b4262014-04-25 20:14:30 +03002679/* Pineview MCH register contains DDR3 setting */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002680#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
Li Peng95534262010-05-18 18:58:44 +08002681#define CSHRDDR3CTL_DDR3 (1 << 2)
2682
Ville Syrjälä646b4262014-04-25 20:14:30 +03002683/* 965 MCH register controlling DRAM channel configuration */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002684#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
2685#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
Eric Anholt673a3942008-07-30 12:06:12 -07002686
Ville Syrjälä646b4262014-04-25 20:14:30 +03002687/* snb MCH registers for reading the DRAM channel configuration */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002688#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2689#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2690#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002691#define MAD_DIMM_ECC_MASK (0x3 << 24)
2692#define MAD_DIMM_ECC_OFF (0x0 << 24)
2693#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2694#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2695#define MAD_DIMM_ECC_ON (0x3 << 24)
2696#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2697#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2698#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2699#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2700#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2701#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2702#define MAD_DIMM_A_SELECT (0x1 << 16)
2703/* DIMM sizes are in multiples of 256mb. */
2704#define MAD_DIMM_B_SIZE_SHIFT 8
2705#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2706#define MAD_DIMM_A_SIZE_SHIFT 0
2707#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2708
Ville Syrjälä646b4262014-04-25 20:14:30 +03002709/* snb MCH registers for priority tuning */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002710#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01002711#define MCH_SSKPD_WM0_MASK 0x3f
2712#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002713
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002714#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
Jesse Barnesec013e72013-08-20 10:29:23 +01002715
Keith Packardb11248d2009-06-11 22:28:56 -07002716/* Clocking configuration register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002717#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002718#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07002719#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2720#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2721#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2722#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2723#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002724/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07002725#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002726#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07002727#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002728#define CLKCFG_MEM_533 (1 << 4)
2729#define CLKCFG_MEM_667 (2 << 4)
2730#define CLKCFG_MEM_800 (3 << 4)
2731#define CLKCFG_MEM_MASK (7 << 4)
2732
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002733#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
2734#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
Ville Syrjälä34edce22015-05-22 11:22:33 +03002735
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002736#define TSC1 _MMIO(0x11001)
Jesse Barnesea056c12010-09-10 10:02:13 -07002737#define TSE (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002738#define TR1 _MMIO(0x11006)
2739#define TSFS _MMIO(0x11020)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002740#define TSFS_SLOPE_MASK 0x0000ff00
2741#define TSFS_SLOPE_SHIFT 8
2742#define TSFS_INTR_MASK 0x000000ff
2743
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002744#define CRSTANDVID _MMIO(0x11100)
2745#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002746#define PXVFREQ_PX_MASK 0x7f000000
2747#define PXVFREQ_PX_SHIFT 24
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002748#define VIDFREQ_BASE _MMIO(0x11110)
2749#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2750#define VIDFREQ2 _MMIO(0x11114)
2751#define VIDFREQ3 _MMIO(0x11118)
2752#define VIDFREQ4 _MMIO(0x1111c)
Jesse Barnesf97108d2010-01-29 11:27:07 -08002753#define VIDFREQ_P0_MASK 0x1f000000
2754#define VIDFREQ_P0_SHIFT 24
2755#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2756#define VIDFREQ_P0_CSCLK_SHIFT 20
2757#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2758#define VIDFREQ_P0_CRCLK_SHIFT 16
2759#define VIDFREQ_P1_MASK 0x00001f00
2760#define VIDFREQ_P1_SHIFT 8
2761#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2762#define VIDFREQ_P1_CSCLK_SHIFT 4
2763#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002764#define INTTOEXT_BASE_ILK _MMIO(0x11300)
2765#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002766#define INTTOEXT_MAP3_SHIFT 24
2767#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2768#define INTTOEXT_MAP2_SHIFT 16
2769#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2770#define INTTOEXT_MAP1_SHIFT 8
2771#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2772#define INTTOEXT_MAP0_SHIFT 0
2773#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002774#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002775#define MEMCTL_CMD_MASK 0xe000
2776#define MEMCTL_CMD_SHIFT 13
2777#define MEMCTL_CMD_RCLK_OFF 0
2778#define MEMCTL_CMD_RCLK_ON 1
2779#define MEMCTL_CMD_CHFREQ 2
2780#define MEMCTL_CMD_CHVID 3
2781#define MEMCTL_CMD_VMMOFF 4
2782#define MEMCTL_CMD_VMMON 5
2783#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2784 when command complete */
2785#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2786#define MEMCTL_FREQ_SHIFT 8
2787#define MEMCTL_SFCAVM (1<<7)
2788#define MEMCTL_TGT_VID_MASK 0x007f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002789#define MEMIHYST _MMIO(0x1117c)
2790#define MEMINTREN _MMIO(0x11180) /* 16 bits */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002791#define MEMINT_RSEXIT_EN (1<<8)
2792#define MEMINT_CX_SUPR_EN (1<<7)
2793#define MEMINT_CONT_BUSY_EN (1<<6)
2794#define MEMINT_AVG_BUSY_EN (1<<5)
2795#define MEMINT_EVAL_CHG_EN (1<<4)
2796#define MEMINT_MON_IDLE_EN (1<<3)
2797#define MEMINT_UP_EVAL_EN (1<<2)
2798#define MEMINT_DOWN_EVAL_EN (1<<1)
2799#define MEMINT_SW_CMD_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002800#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002801#define MEM_RSEXIT_MASK 0xc000
2802#define MEM_RSEXIT_SHIFT 14
2803#define MEM_CONT_BUSY_MASK 0x3000
2804#define MEM_CONT_BUSY_SHIFT 12
2805#define MEM_AVG_BUSY_MASK 0x0c00
2806#define MEM_AVG_BUSY_SHIFT 10
2807#define MEM_EVAL_CHG_MASK 0x0300
2808#define MEM_EVAL_BUSY_SHIFT 8
2809#define MEM_MON_IDLE_MASK 0x00c0
2810#define MEM_MON_IDLE_SHIFT 6
2811#define MEM_UP_EVAL_MASK 0x0030
2812#define MEM_UP_EVAL_SHIFT 4
2813#define MEM_DOWN_EVAL_MASK 0x000c
2814#define MEM_DOWN_EVAL_SHIFT 2
2815#define MEM_SW_CMD_MASK 0x0003
2816#define MEM_INT_STEER_GFX 0
2817#define MEM_INT_STEER_CMR 1
2818#define MEM_INT_STEER_SMI 2
2819#define MEM_INT_STEER_SCI 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002820#define MEMINTRSTS _MMIO(0x11184)
Jesse Barnesf97108d2010-01-29 11:27:07 -08002821#define MEMINT_RSEXIT (1<<7)
2822#define MEMINT_CONT_BUSY (1<<6)
2823#define MEMINT_AVG_BUSY (1<<5)
2824#define MEMINT_EVAL_CHG (1<<4)
2825#define MEMINT_MON_IDLE (1<<3)
2826#define MEMINT_UP_EVAL (1<<2)
2827#define MEMINT_DOWN_EVAL (1<<1)
2828#define MEMINT_SW_CMD (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002829#define MEMMODECTL _MMIO(0x11190)
Jesse Barnesf97108d2010-01-29 11:27:07 -08002830#define MEMMODE_BOOST_EN (1<<31)
2831#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2832#define MEMMODE_BOOST_FREQ_SHIFT 24
2833#define MEMMODE_IDLE_MODE_MASK 0x00030000
2834#define MEMMODE_IDLE_MODE_SHIFT 16
2835#define MEMMODE_IDLE_MODE_EVAL 0
2836#define MEMMODE_IDLE_MODE_CONT 1
2837#define MEMMODE_HWIDLE_EN (1<<15)
2838#define MEMMODE_SWMODE_EN (1<<14)
2839#define MEMMODE_RCLK_GATE (1<<13)
2840#define MEMMODE_HW_UPDATE (1<<12)
2841#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2842#define MEMMODE_FSTART_SHIFT 8
2843#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2844#define MEMMODE_FMAX_SHIFT 4
2845#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002846#define RCBMAXAVG _MMIO(0x1119c)
2847#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002848#define SWMEMCMD_RENDER_OFF (0 << 13)
2849#define SWMEMCMD_RENDER_ON (1 << 13)
2850#define SWMEMCMD_SWFREQ (2 << 13)
2851#define SWMEMCMD_TARVID (3 << 13)
2852#define SWMEMCMD_VRM_OFF (4 << 13)
2853#define SWMEMCMD_VRM_ON (5 << 13)
2854#define CMDSTS (1<<12)
2855#define SFCAVM (1<<11)
2856#define SWFREQ_MASK 0x0380 /* P0-7 */
2857#define SWFREQ_SHIFT 7
2858#define TARVID_MASK 0x001f
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002859#define MEMSTAT_CTG _MMIO(0x111a0)
2860#define RCBMINAVG _MMIO(0x111a0)
2861#define RCUPEI _MMIO(0x111b0)
2862#define RCDNEI _MMIO(0x111b4)
2863#define RSTDBYCTL _MMIO(0x111b8)
Jesse Barnes88271da2011-01-05 12:01:24 -08002864#define RS1EN (1<<31)
2865#define RS2EN (1<<30)
2866#define RS3EN (1<<29)
2867#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2868#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2869#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2870#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2871#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2872#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2873#define RSX_STATUS_MASK (7<<20)
2874#define RSX_STATUS_ON (0<<20)
2875#define RSX_STATUS_RC1 (1<<20)
2876#define RSX_STATUS_RC1E (2<<20)
2877#define RSX_STATUS_RS1 (3<<20)
2878#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2879#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2880#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2881#define RSX_STATUS_RSVD2 (7<<20)
2882#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2883#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2884#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2885#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2886#define RS1CONTSAV_MASK (3<<14)
2887#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2888#define RS1CONTSAV_RSVD (1<<14)
2889#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2890#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2891#define NORMSLEXLAT_MASK (3<<12)
2892#define SLOW_RS123 (0<<12)
2893#define SLOW_RS23 (1<<12)
2894#define SLOW_RS3 (2<<12)
2895#define NORMAL_RS123 (3<<12)
2896#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2897#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2898#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2899#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2900#define RS_CSTATE_MASK (3<<4)
2901#define RS_CSTATE_C367_RS1 (0<<4)
2902#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2903#define RS_CSTATE_RSVD (2<<4)
2904#define RS_CSTATE_C367_RS2 (3<<4)
2905#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2906#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002907#define VIDCTL _MMIO(0x111c0)
2908#define VIDSTS _MMIO(0x111c8)
2909#define VIDSTART _MMIO(0x111cc) /* 8 bits */
2910#define MEMSTAT_ILK _MMIO(0x111f8)
Jesse Barnesf97108d2010-01-29 11:27:07 -08002911#define MEMSTAT_VID_MASK 0x7f00
2912#define MEMSTAT_VID_SHIFT 8
2913#define MEMSTAT_PSTATE_MASK 0x00f8
2914#define MEMSTAT_PSTATE_SHIFT 3
2915#define MEMSTAT_MON_ACTV (1<<2)
2916#define MEMSTAT_SRC_CTL_MASK 0x0003
2917#define MEMSTAT_SRC_CTL_CORE 0
2918#define MEMSTAT_SRC_CTL_TRB 1
2919#define MEMSTAT_SRC_CTL_THM 2
2920#define MEMSTAT_SRC_CTL_STDBY 3
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002921#define RCPREVBSYTUPAVG _MMIO(0x113b8)
2922#define RCPREVBSYTDNAVG _MMIO(0x113bc)
2923#define PMMISC _MMIO(0x11214)
Jesse Barnesea056c12010-09-10 10:02:13 -07002924#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002925#define SDEW _MMIO(0x1124c)
2926#define CSIEW0 _MMIO(0x11250)
2927#define CSIEW1 _MMIO(0x11254)
2928#define CSIEW2 _MMIO(0x11258)
2929#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
2930#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
2931#define MCHAFE _MMIO(0x112c0)
2932#define CSIEC _MMIO(0x112e0)
2933#define DMIEC _MMIO(0x112e4)
2934#define DDREC _MMIO(0x112e8)
2935#define PEG0EC _MMIO(0x112ec)
2936#define PEG1EC _MMIO(0x112f0)
2937#define GFXEC _MMIO(0x112f4)
2938#define RPPREVBSYTUPAVG _MMIO(0x113b8)
2939#define RPPREVBSYTDNAVG _MMIO(0x113bc)
2940#define ECR _MMIO(0x11600)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002941#define ECR_GPFE (1<<31)
2942#define ECR_IMONE (1<<30)
2943#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002944#define OGW0 _MMIO(0x11608)
2945#define OGW1 _MMIO(0x1160c)
2946#define EG0 _MMIO(0x11610)
2947#define EG1 _MMIO(0x11614)
2948#define EG2 _MMIO(0x11618)
2949#define EG3 _MMIO(0x1161c)
2950#define EG4 _MMIO(0x11620)
2951#define EG5 _MMIO(0x11624)
2952#define EG6 _MMIO(0x11628)
2953#define EG7 _MMIO(0x1162c)
2954#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
2955#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
2956#define LCFUSE02 _MMIO(0x116c0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002957#define LCFUSE_HIV_MASK 0x000000ff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002958#define CSIPLL0 _MMIO(0x12c10)
2959#define DDRMPLL1 _MMIO(0X12c20)
2960#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
Eric Anholt7d573822009-01-02 13:33:00 -08002961
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002962#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002963#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002964
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002965#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2966#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
2967#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2968#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2969#define BXT_RP_STATE_CAP _MMIO(0x138170)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002970
Ville Syrjälä8a292d02016-04-20 16:43:56 +03002971/*
2972 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2973 * 8300) freezing up around GPU hangs. Looks as if even
2974 * scheduling/timer interrupts start misbehaving if the RPS
2975 * EI/thresholds are "bad", leading to a very sluggish or even
2976 * frozen machine.
2977 */
2978#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
Akash Goelde43ae92015-03-06 11:07:14 +05302979#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
Akash Goel26148bd2015-09-18 23:39:51 +05302980#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
Akash Goelde43ae92015-03-06 11:07:14 +05302981#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
Akash Goel26148bd2015-09-18 23:39:51 +05302982 (IS_BROXTON(dev_priv) ? \
2983 INTERVAL_0_833_US(us) : \
2984 INTERVAL_1_33_US(us)) : \
Akash Goelde43ae92015-03-06 11:07:14 +05302985 INTERVAL_1_28_US(us))
2986
Akash Goel52530cb2016-04-23 00:05:44 +05302987#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
2988#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
2989#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
2990#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
2991 (IS_BROXTON(dev_priv) ? \
2992 INTERVAL_0_833_TO_US(interval) : \
2993 INTERVAL_1_33_TO_US(interval)) : \
2994 INTERVAL_1_28_TO_US(interval))
2995
Jesse Barnes585fb112008-07-29 11:54:06 -07002996/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002997 * Logical Context regs
2998 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002999#define CCID _MMIO(0x2180)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08003000#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003001/*
3002 * Notes on SNB/IVB/VLV context size:
3003 * - Power context is saved elsewhere (LLC or stolen)
3004 * - Ring/execlist context is saved on SNB, not on IVB
3005 * - Extended context size already includes render context size
3006 * - We always need to follow the extended context size.
3007 * SNB BSpec has comments indicating that we should use the
3008 * render context size instead if execlists are disabled, but
3009 * based on empirical testing that's just nonsense.
3010 * - Pipelined/VF state is saved on SNB/IVB respectively
3011 * - GT1 size just indicates how much of render context
3012 * doesn't need saving on GT1
3013 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003014#define CXT_SIZE _MMIO(0x21a0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03003015#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3016#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3017#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3018#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3019#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003020#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07003021 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3022 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003023#define GEN7_CXT_SIZE _MMIO(0x21a8)
Ville Syrjälä68d97532015-09-18 20:03:39 +03003024#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3025#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3026#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3027#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3028#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3029#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03003030#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07003031 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07003032/* Haswell does have the CXT_SIZE register however it does not appear to be
3033 * valid. Now, docs explain in dwords what is in the context object. The full
3034 * size is 70720 bytes, however, the power context and execlist context will
3035 * never be saved (power context is stored elsewhere, and execlists don't work
Abdiel Janulgue4c436d552015-06-16 13:39:41 +03003036 * on HSW) - so the final size, including the extra state required for the
3037 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
Ben Widawskya0de80a2013-06-25 21:53:40 -07003038 */
3039#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawsky88976442013-11-02 21:07:05 -07003040/* Same as Haswell, but 72064 bytes now. */
3041#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
3042
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003043#define CHV_CLK_CTL1 _MMIO(0x101100)
3044#define VLV_CLK_CTL2 _MMIO(0x101104)
Jesse Barnese454a052013-09-26 17:55:58 -07003045#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3046
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08003047/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003048 * Overlay regs
3049 */
3050
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003051#define OVADD _MMIO(0x30000)
3052#define DOVSTA _MMIO(0x30008)
Jesse Barnes585fb112008-07-29 11:54:06 -07003053#define OC_BUF (0x3<<20)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003054#define OGAMC5 _MMIO(0x30010)
3055#define OGAMC4 _MMIO(0x30014)
3056#define OGAMC3 _MMIO(0x30018)
3057#define OGAMC2 _MMIO(0x3001c)
3058#define OGAMC1 _MMIO(0x30020)
3059#define OGAMC0 _MMIO(0x30024)
Jesse Barnes585fb112008-07-29 11:54:06 -07003060
3061/*
Imre Deakd965e7ac2015-12-01 10:23:52 +02003062 * GEN9 clock gating regs
3063 */
3064#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3065#define PWM2_GATING_DIS (1 << 14)
3066#define PWM1_GATING_DIS (1 << 13)
3067
3068/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003069 * Display engine regs
3070 */
3071
Shuang He8bf1e9f2013-10-15 18:55:27 +01003072/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003073#define _PIPE_CRC_CTL_A 0x60050
Shuang He8bf1e9f2013-10-15 18:55:27 +01003074#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02003075/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01003076#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3077#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3078#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02003079/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003080#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3081#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3082#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3083/* embedded DP port on the north display block, reserved on ivb */
3084#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3085#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02003086/* vlv source selection */
3087#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3088#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3089#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3090/* with DP port the pipe source is invalid */
3091#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3092#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3093#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3094/* gen3+ source selection */
3095#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3096#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3097#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3098/* with DP/TV port the pipe source is invalid */
3099#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3100#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3101#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3102#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3103#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3104/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02003105#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02003106
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003107#define _PIPE_CRC_RES_1_A_IVB 0x60064
3108#define _PIPE_CRC_RES_2_A_IVB 0x60068
3109#define _PIPE_CRC_RES_3_A_IVB 0x6006c
3110#define _PIPE_CRC_RES_4_A_IVB 0x60070
3111#define _PIPE_CRC_RES_5_A_IVB 0x60074
3112
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003113#define _PIPE_CRC_RES_RED_A 0x60060
3114#define _PIPE_CRC_RES_GREEN_A 0x60064
3115#define _PIPE_CRC_RES_BLUE_A 0x60068
3116#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
3117#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01003118
3119/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003120#define _PIPE_CRC_RES_1_B_IVB 0x61064
3121#define _PIPE_CRC_RES_2_B_IVB 0x61068
3122#define _PIPE_CRC_RES_3_B_IVB 0x6106c
3123#define _PIPE_CRC_RES_4_B_IVB 0x61070
3124#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01003125
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003126#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3127#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3128#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3129#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3130#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3131#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01003132
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003133#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3134#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3135#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3136#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3137#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02003138
Jesse Barnes585fb112008-07-29 11:54:06 -07003139/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003140#define _HTOTAL_A 0x60000
3141#define _HBLANK_A 0x60004
3142#define _HSYNC_A 0x60008
3143#define _VTOTAL_A 0x6000c
3144#define _VBLANK_A 0x60010
3145#define _VSYNC_A 0x60014
3146#define _PIPEASRC 0x6001c
3147#define _BCLRPAT_A 0x60020
3148#define _VSYNCSHIFT_A 0x60028
Clint Taylorebb69c92014-09-30 10:30:22 -07003149#define _PIPE_MULT_A 0x6002c
Jesse Barnes585fb112008-07-29 11:54:06 -07003150
3151/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003152#define _HTOTAL_B 0x61000
3153#define _HBLANK_B 0x61004
3154#define _HSYNC_B 0x61008
3155#define _VTOTAL_B 0x6100c
3156#define _VBLANK_B 0x61010
3157#define _VSYNC_B 0x61014
3158#define _PIPEBSRC 0x6101c
3159#define _BCLRPAT_B 0x61020
3160#define _VSYNCSHIFT_B 0x61028
Clint Taylorebb69c92014-09-30 10:30:22 -07003161#define _PIPE_MULT_B 0x6102c
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003162
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003163#define TRANSCODER_A_OFFSET 0x60000
3164#define TRANSCODER_B_OFFSET 0x61000
3165#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03003166#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003167#define TRANSCODER_EDP_OFFSET 0x6f000
3168
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003169#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003170 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3171 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003172
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003173#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
3174#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
3175#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
3176#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
3177#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
3178#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
3179#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
3180#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
3181#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
3182#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
Chris Wilson5eddb702010-09-11 13:48:45 +01003183
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08003184/* VLV eDP PSR registers */
3185#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
3186#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
3187#define VLV_EDP_PSR_ENABLE (1<<0)
3188#define VLV_EDP_PSR_RESET (1<<1)
3189#define VLV_EDP_PSR_MODE_MASK (7<<2)
3190#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
3191#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
3192#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
3193#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
3194#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
3195#define VLV_EDP_PSR_DBL_FRAME (1<<10)
3196#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
3197#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003198#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08003199
3200#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3201#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3202#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
3203#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
3204#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003205#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08003206
3207#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3208#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
3209#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
3210#define VLV_EDP_PSR_CURR_STATE_MASK 7
3211#define VLV_EDP_PSR_DISABLED (0<<0)
3212#define VLV_EDP_PSR_INACTIVE (1<<0)
3213#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
3214#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
3215#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
3216#define VLV_EDP_PSR_EXIT (5<<0)
3217#define VLV_EDP_PSR_IN_TRANS (1<<7)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003218#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08003219
Ben Widawskyed8546a2013-11-04 22:45:05 -08003220/* HSW+ eDP PSR registers */
Ville Syrjälä443a3892015-11-11 20:34:15 +02003221#define HSW_EDP_PSR_BASE 0x64800
3222#define BDW_EDP_PSR_BASE 0x6f800
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003223#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003224#define EDP_PSR_ENABLE (1<<31)
Rodrigo Vivi82c56252014-06-12 10:16:42 -07003225#define BDW_PSR_SINGLE_FRAME (1<<30)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003226#define EDP_PSR_LINK_STANDBY (1<<27)
3227#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3228#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3229#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3230#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3231#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3232#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3233#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3234#define EDP_PSR_TP1_TP2_SEL (0<<11)
3235#define EDP_PSR_TP1_TP3_SEL (1<<11)
3236#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3237#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3238#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3239#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3240#define EDP_PSR_TP1_TIME_500us (0<<4)
3241#define EDP_PSR_TP1_TIME_100us (1<<4)
3242#define EDP_PSR_TP1_TIME_2500us (2<<4)
3243#define EDP_PSR_TP1_TIME_0us (3<<4)
3244#define EDP_PSR_IDLE_FRAME_SHIFT 0
3245
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003246#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
3247#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003248
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003249#define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003250#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03003251#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3252#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3253#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3254#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3255#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3256#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3257#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3258#define EDP_PSR_STATUS_LINK_MASK (3<<26)
3259#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3260#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3261#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3262#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3263#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3264#define EDP_PSR_STATUS_COUNT_SHIFT 16
3265#define EDP_PSR_STATUS_COUNT_MASK 0xf
3266#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3267#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3268#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3269#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3270#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3271#define EDP_PSR_STATUS_IDLE_MASK 0xf
3272
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003273#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03003274#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003275
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003276#define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003277#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3278#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3279#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3280
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003281#define EDP_PSR2_CTL _MMIO(0x6f900)
Sonika Jindal474d1ec2015-04-02 11:02:44 +05303282#define EDP_PSR2_ENABLE (1<<31)
3283#define EDP_SU_TRACK_ENABLE (1<<30)
3284#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3285#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3286#define EDP_PSR2_TP2_TIME_500 (0<<8)
3287#define EDP_PSR2_TP2_TIME_100 (1<<8)
3288#define EDP_PSR2_TP2_TIME_2500 (2<<8)
3289#define EDP_PSR2_TP2_TIME_50 (3<<8)
3290#define EDP_PSR2_TP2_TIME_MASK (3<<8)
3291#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3292#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3293#define EDP_PSR2_IDLE_MASK 0xf
3294
Jesse Barnes585fb112008-07-29 11:54:06 -07003295/* VGA port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003296#define ADPA _MMIO(0x61100)
3297#define PCH_ADPA _MMIO(0xe1100)
3298#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02003299
Jesse Barnes585fb112008-07-29 11:54:06 -07003300#define ADPA_DAC_ENABLE (1<<31)
3301#define ADPA_DAC_DISABLE 0
3302#define ADPA_PIPE_SELECT_MASK (1<<30)
3303#define ADPA_PIPE_A_SELECT 0
3304#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07003305#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02003306/* CPT uses bits 29:30 for pch transcoder select */
3307#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3308#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3309#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3310#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3311#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3312#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3313#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3314#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3315#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3316#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3317#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3318#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3319#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3320#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3321#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3322#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3323#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3324#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3325#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
3327#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01003328#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003329#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01003330#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07003331#define ADPA_HSYNC_CNTL_ENABLE 0
3332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3333#define ADPA_VSYNC_ACTIVE_LOW 0
3334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3335#define ADPA_HSYNC_ACTIVE_LOW 0
3336#define ADPA_DPMS_MASK (~(3<<10))
3337#define ADPA_DPMS_ON (0<<10)
3338#define ADPA_DPMS_SUSPEND (1<<10)
3339#define ADPA_DPMS_STANDBY (2<<10)
3340#define ADPA_DPMS_OFF (3<<10)
3341
Chris Wilson939fe4d2010-10-09 10:33:26 +01003342
Jesse Barnes585fb112008-07-29 11:54:06 -07003343/* Hotplug control (945+ only) */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003344#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01003345#define PORTB_HOTPLUG_INT_EN (1 << 29)
3346#define PORTC_HOTPLUG_INT_EN (1 << 28)
3347#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003348#define SDVOB_HOTPLUG_INT_EN (1 << 26)
3349#define SDVOC_HOTPLUG_INT_EN (1 << 25)
3350#define TV_HOTPLUG_INT_EN (1 << 18)
3351#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05003352#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3353 PORTC_HOTPLUG_INT_EN | \
3354 PORTD_HOTPLUG_INT_EN | \
3355 SDVOC_HOTPLUG_INT_EN | \
3356 SDVOB_HOTPLUG_INT_EN | \
3357 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07003358#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08003359#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3360/* must use period 64 on GM45 according to docs */
3361#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3362#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3363#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3364#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3365#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3366#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3367#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3368#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3369#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3370#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3371#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3372#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003373
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003374#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02003375/*
Ville Syrjälä0780cd32016-02-10 19:59:05 +02003376 * HDMI/DP bits are g4x+
Daniel Vetter0ce99f72013-07-26 11:27:49 +02003377 *
3378 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3379 * Please check the detailed lore in the commit message for for experimental
3380 * evidence.
3381 */
Ville Syrjälä0780cd32016-02-10 19:59:05 +02003382/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3383#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
3384#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
3385#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
3386/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3387#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
Todd Previte232a6ee2014-01-23 00:13:41 -07003388#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
Ville Syrjälä0780cd32016-02-10 19:59:05 +02003389#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01003390#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02003391#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3392#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01003393#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02003394#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3395#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01003396#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02003397#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3398#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01003399/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07003400#define CRT_HOTPLUG_INT_STATUS (1 << 11)
3401#define TV_HOTPLUG_INT_STATUS (1 << 10)
3402#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3403#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3404#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3405#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01003406#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3407#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3408#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02003409#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3410
Chris Wilson084b6122012-05-11 18:01:33 +01003411/* SDVO is different across gen3/4 */
3412#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3413#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02003414/*
3415 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3416 * since reality corrobates that they're the same as on gen3. But keep these
3417 * bits here (and the comment!) to help any other lost wanderers back onto the
3418 * right tracks.
3419 */
Chris Wilson084b6122012-05-11 18:01:33 +01003420#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3421#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3422#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3423#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05003424#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3425 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3426 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3427 PORTB_HOTPLUG_INT_STATUS | \
3428 PORTC_HOTPLUG_INT_STATUS | \
3429 PORTD_HOTPLUG_INT_STATUS)
3430
Egbert Eiche5868a32013-02-28 04:17:12 -05003431#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3432 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3433 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3434 PORTB_HOTPLUG_INT_STATUS | \
3435 PORTC_HOTPLUG_INT_STATUS | \
3436 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07003437
Paulo Zanonic20cd312013-02-19 16:21:45 -03003438/* SDVO and HDMI port control.
3439 * The same register may be used for SDVO or HDMI */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003440#define _GEN3_SDVOB 0x61140
3441#define _GEN3_SDVOC 0x61160
3442#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
3443#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003444#define GEN4_HDMIB GEN3_SDVOB
3445#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003446#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
3447#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
3448#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
3449#define PCH_SDVOB _MMIO(0xe1140)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003450#define PCH_HDMIB PCH_SDVOB
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003451#define PCH_HDMIC _MMIO(0xe1150)
3452#define PCH_HDMID _MMIO(0xe1160)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003453
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003454#define PORT_DFT_I9XX _MMIO(0x61150)
Daniel Vetter84093602013-11-01 10:50:21 +01003455#define DC_BALANCE_RESET (1 << 25)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003456#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01003457#define DC_BALANCE_RESET_VLV (1 << 31)
Ville Syrjäläeb736672014-12-09 21:28:28 +02003458#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3459#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
Daniel Vetter84093602013-11-01 10:50:21 +01003460#define PIPE_B_SCRAMBLE_RESET (1 << 1)
3461#define PIPE_A_SCRAMBLE_RESET (1 << 0)
3462
Paulo Zanonic20cd312013-02-19 16:21:45 -03003463/* Gen 3 SDVO bits: */
3464#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003465#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3466#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003467#define SDVO_PIPE_B_SELECT (1 << 30)
3468#define SDVO_STALL_SELECT (1 << 29)
3469#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003470/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003471 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07003472 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07003473 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3474 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003475#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07003476#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03003477#define SDVO_PHASE_SELECT_MASK (15 << 19)
3478#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3479#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3480#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3481#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3482#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3483#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003484/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003485#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3486 SDVO_INTERRUPT_ENABLE)
3487#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3488
3489/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003490#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03003491#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003492#define SDVO_ENCODING_SDVO (0 << 10)
3493#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003494#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3495#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003496#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003497#define SDVO_AUDIO_ENABLE (1 << 6)
3498/* VSYNC/HSYNC bits new with 965, default is to be set */
3499#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3500#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3501
3502/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003503#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003504#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3505
3506/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003507#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3508#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003509
Chon Ming Lee44f37d12014-04-09 13:28:21 +03003510/* CHV SDVO/HDMI bits: */
3511#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3512#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3513
Jesse Barnes585fb112008-07-29 11:54:06 -07003514
3515/* DVO port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003516#define _DVOA 0x61120
3517#define DVOA _MMIO(_DVOA)
3518#define _DVOB 0x61140
3519#define DVOB _MMIO(_DVOB)
3520#define _DVOC 0x61160
3521#define DVOC _MMIO(_DVOC)
Jesse Barnes585fb112008-07-29 11:54:06 -07003522#define DVO_ENABLE (1 << 31)
3523#define DVO_PIPE_B_SELECT (1 << 30)
3524#define DVO_PIPE_STALL_UNUSED (0 << 28)
3525#define DVO_PIPE_STALL (1 << 28)
3526#define DVO_PIPE_STALL_TV (2 << 28)
3527#define DVO_PIPE_STALL_MASK (3 << 28)
3528#define DVO_USE_VGA_SYNC (1 << 15)
3529#define DVO_DATA_ORDER_I740 (0 << 14)
3530#define DVO_DATA_ORDER_FP (1 << 14)
3531#define DVO_VSYNC_DISABLE (1 << 11)
3532#define DVO_HSYNC_DISABLE (1 << 10)
3533#define DVO_VSYNC_TRISTATE (1 << 9)
3534#define DVO_HSYNC_TRISTATE (1 << 8)
3535#define DVO_BORDER_ENABLE (1 << 7)
3536#define DVO_DATA_ORDER_GBRG (1 << 6)
3537#define DVO_DATA_ORDER_RGGB (0 << 6)
3538#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3539#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3540#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3541#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3542#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3543#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3544#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3545#define DVO_PRESERVE_MASK (0x7<<24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003546#define DVOA_SRCDIM _MMIO(0x61124)
3547#define DVOB_SRCDIM _MMIO(0x61144)
3548#define DVOC_SRCDIM _MMIO(0x61164)
Jesse Barnes585fb112008-07-29 11:54:06 -07003549#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3550#define DVO_SRCDIM_VERTICAL_SHIFT 0
3551
3552/* LVDS port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003553#define LVDS _MMIO(0x61180)
Jesse Barnes585fb112008-07-29 11:54:06 -07003554/*
3555 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3556 * the DPLL semantics change when the LVDS is assigned to that pipe.
3557 */
3558#define LVDS_PORT_EN (1 << 31)
3559/* Selects pipe B for LVDS data. Must be set on pre-965. */
3560#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003561#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07003562#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08003563/* LVDS dithering flag on 965/g4x platform */
3564#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08003565/* LVDS sync polarity flags. Set to invert (i.e. negative) */
3566#define LVDS_VSYNC_POLARITY (1 << 21)
3567#define LVDS_HSYNC_POLARITY (1 << 20)
3568
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08003569/* Enable border for unscaled (or aspect-scaled) display */
3570#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07003571/*
3572 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3573 * pixel.
3574 */
3575#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3576#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3577#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3578/*
3579 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3580 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3581 * on.
3582 */
3583#define LVDS_A3_POWER_MASK (3 << 6)
3584#define LVDS_A3_POWER_DOWN (0 << 6)
3585#define LVDS_A3_POWER_UP (3 << 6)
3586/*
3587 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3588 * is set.
3589 */
3590#define LVDS_CLKB_POWER_MASK (3 << 4)
3591#define LVDS_CLKB_POWER_DOWN (0 << 4)
3592#define LVDS_CLKB_POWER_UP (3 << 4)
3593/*
3594 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3595 * setting for whether we are in dual-channel mode. The B3 pair will
3596 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3597 */
3598#define LVDS_B0B3_POWER_MASK (3 << 2)
3599#define LVDS_B0B3_POWER_DOWN (0 << 2)
3600#define LVDS_B0B3_POWER_UP (3 << 2)
3601
David Härdeman3c17fe42010-09-24 21:44:32 +02003602/* Video Data Island Packet control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003603#define VIDEO_DIP_DATA _MMIO(0x61178)
Yannick Guerrinifd0753c2015-02-28 17:20:41 +01003604/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
Paulo Zanoniadf00b22012-09-25 13:23:34 -03003605 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3606 * of the infoframe structure specified by CEA-861. */
3607#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003608#define VIDEO_DIP_VSC_DATA_SIZE 36
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003609#define VIDEO_DIP_CTL _MMIO(0x61170)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003610/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02003611#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02003612#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03003613#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003614#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02003615#define VIDEO_DIP_ENABLE_AVI (1 << 21)
3616#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003617#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02003618#define VIDEO_DIP_ENABLE_SPD (8 << 21)
3619#define VIDEO_DIP_SELECT_AVI (0 << 19)
3620#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3621#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07003622#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02003623#define VIDEO_DIP_FREQ_ONCE (0 << 16)
3624#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3625#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03003626#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003627/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003628#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3629#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003630#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003631#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3632#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003633#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02003634
Jesse Barnes585fb112008-07-29 11:54:06 -07003635/* Panel power sequencing */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003636#define PP_STATUS _MMIO(0x61200)
Jesse Barnes585fb112008-07-29 11:54:06 -07003637#define PP_ON (1 << 31)
3638/*
3639 * Indicates that all dependencies of the panel are on:
3640 *
3641 * - PLL enabled
3642 * - pipe enabled
3643 * - LVDS/DVOB/DVOC on
3644 */
3645#define PP_READY (1 << 30)
3646#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07003647#define PP_SEQUENCE_POWER_UP (1 << 28)
3648#define PP_SEQUENCE_POWER_DOWN (2 << 28)
3649#define PP_SEQUENCE_MASK (3 << 28)
3650#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003651#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003652#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07003653#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3654#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3655#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3656#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3657#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3658#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3659#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3660#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3661#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003662#define PP_CONTROL _MMIO(0x61204)
Jesse Barnes585fb112008-07-29 11:54:06 -07003663#define POWER_TARGET_ON (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003664#define PP_ON_DELAYS _MMIO(0x61208)
3665#define PP_OFF_DELAYS _MMIO(0x6120c)
3666#define PP_DIVISOR _MMIO(0x61210)
Jesse Barnes585fb112008-07-29 11:54:06 -07003667
3668/* Panel fitting */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003669#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07003670#define PFIT_ENABLE (1 << 31)
3671#define PFIT_PIPE_MASK (3 << 29)
3672#define PFIT_PIPE_SHIFT 29
3673#define VERT_INTERP_DISABLE (0 << 10)
3674#define VERT_INTERP_BILINEAR (1 << 10)
3675#define VERT_INTERP_MASK (3 << 10)
3676#define VERT_AUTO_SCALE (1 << 9)
3677#define HORIZ_INTERP_DISABLE (0 << 6)
3678#define HORIZ_INTERP_BILINEAR (1 << 6)
3679#define HORIZ_INTERP_MASK (3 << 6)
3680#define HORIZ_AUTO_SCALE (1 << 5)
3681#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003682#define PFIT_FILTER_FUZZY (0 << 24)
3683#define PFIT_SCALING_AUTO (0 << 26)
3684#define PFIT_SCALING_PROGRAMMED (1 << 26)
3685#define PFIT_SCALING_PILLAR (2 << 26)
3686#define PFIT_SCALING_LETTER (3 << 26)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003687#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003688/* Pre-965 */
3689#define PFIT_VERT_SCALE_SHIFT 20
3690#define PFIT_VERT_SCALE_MASK 0xfff00000
3691#define PFIT_HORIZ_SCALE_SHIFT 4
3692#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3693/* 965+ */
3694#define PFIT_VERT_SCALE_SHIFT_965 16
3695#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3696#define PFIT_HORIZ_SCALE_SHIFT_965 0
3697#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3698
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003699#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07003700
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003701#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3702#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003703#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3704 _VLV_BLC_PWM_CTL2_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003705
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003706#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3707#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003708#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3709 _VLV_BLC_PWM_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003710
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003711#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3712#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003713#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3714 _VLV_BLC_HIST_CTL_B)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003715
Jesse Barnes585fb112008-07-29 11:54:06 -07003716/* Backlight control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003717#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003718#define BLM_PWM_ENABLE (1 << 31)
3719#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3720#define BLM_PIPE_SELECT (1 << 29)
3721#define BLM_PIPE_SELECT_IVB (3 << 29)
3722#define BLM_PIPE_A (0 << 29)
3723#define BLM_PIPE_B (1 << 29)
3724#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03003725#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3726#define BLM_TRANSCODER_B BLM_PIPE_B
3727#define BLM_TRANSCODER_C BLM_PIPE_C
3728#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003729#define BLM_PIPE(pipe) ((pipe) << 29)
3730#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3731#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3732#define BLM_PHASE_IN_ENABLE (1 << 25)
3733#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3734#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3735#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3736#define BLM_PHASE_IN_COUNT_SHIFT (8)
3737#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3738#define BLM_PHASE_IN_INCR_SHIFT (0)
3739#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003740#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01003741/*
3742 * This is the most significant 15 bits of the number of backlight cycles in a
3743 * complete cycle of the modulated backlight control.
3744 *
3745 * The actual value is this field multiplied by two.
3746 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003747#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3748#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3749#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003750/*
3751 * This is the number of cycles out of the backlight modulation cycle for which
3752 * the backlight is on.
3753 *
3754 * This field must be no greater than the number of cycles in the complete
3755 * backlight modulation cycle.
3756 */
3757#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3758#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02003759#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3760#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003761
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003762#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
Jani Nikula2059ac32015-06-26 14:18:56 +03003763#define BLM_HISTOGRAM_ENABLE (1 << 31)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07003764
Daniel Vetter7cf41602012-06-05 10:07:09 +02003765/* New registers for PCH-split platforms. Safe where new bits show up, the
3766 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003767#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
3768#define BLC_PWM_CPU_CTL _MMIO(0x48254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003769
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003770#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003771
Daniel Vetter7cf41602012-06-05 10:07:09 +02003772/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3773 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003774#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
Daniel Vetter4b4147c2012-07-11 00:31:06 +02003775#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003776#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3777#define BLM_PCH_POLARITY (1 << 29)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003778#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003779
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003780#define UTIL_PIN_CTL _MMIO(0x48400)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003781#define UTIL_PIN_ENABLE (1 << 31)
3782
Sunil Kamath022e4e52015-09-30 22:34:57 +05303783#define UTIL_PIN_PIPE(x) ((x) << 29)
3784#define UTIL_PIN_PIPE_MASK (3 << 29)
3785#define UTIL_PIN_MODE_PWM (1 << 24)
3786#define UTIL_PIN_MODE_MASK (0xf << 24)
3787#define UTIL_PIN_POLARITY (1 << 22)
3788
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303789/* BXT backlight register definition. */
Sunil Kamath022e4e52015-09-30 22:34:57 +05303790#define _BXT_BLC_PWM_CTL1 0xC8250
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303791#define BXT_BLC_PWM_ENABLE (1 << 31)
3792#define BXT_BLC_PWM_POLARITY (1 << 29)
Sunil Kamath022e4e52015-09-30 22:34:57 +05303793#define _BXT_BLC_PWM_FREQ1 0xC8254
3794#define _BXT_BLC_PWM_DUTY1 0xC8258
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303795
Sunil Kamath022e4e52015-09-30 22:34:57 +05303796#define _BXT_BLC_PWM_CTL2 0xC8350
3797#define _BXT_BLC_PWM_FREQ2 0xC8354
3798#define _BXT_BLC_PWM_DUTY2 0xC8358
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303799
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003800#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05303801 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003802#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05303803 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003804#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
Sunil Kamath022e4e52015-09-30 22:34:57 +05303805 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303806
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003807#define PCH_GTC_CTL _MMIO(0xe7000)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003808#define PCH_GTC_ENABLE (1 << 31)
3809
Jesse Barnes585fb112008-07-29 11:54:06 -07003810/* TV port control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003811#define TV_CTL _MMIO(0x68000)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003812/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07003813# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003814/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003815# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003816/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003817# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003818/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003819# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003820/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003821# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003822/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003823# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3824# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003825/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003826# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003827/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003828# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003829/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07003830# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003831/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003832# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003833/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07003834# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003835/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07003836# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003837/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003838# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003839/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07003840# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003841/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003842# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003843/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003844 * Enables a fix for the 915GM only.
3845 *
3846 * Not sure what it does.
3847 */
3848# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003849/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08003850# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003851# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003852/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07003853# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003854/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003855# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003856/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003857# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003858/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07003859# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003860/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07003861# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003862/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003863# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003864/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003865# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003866/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07003867# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003868/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07003869# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003870/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003871 * This test mode forces the DACs to 50% of full output.
3872 *
3873 * This is used for load detection in combination with TVDAC_SENSE_MASK
3874 */
3875# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3876# define TV_TEST_MODE_MASK (7 << 0)
3877
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003878#define TV_DAC _MMIO(0x68004)
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01003879# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003880/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003881 * Reports that DAC state change logic has reported change (RO).
3882 *
3883 * This gets cleared when TV_DAC_STATE_EN is cleared
3884*/
3885# define TVDAC_STATE_CHG (1 << 31)
3886# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003887/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003888# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003889/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003890# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003891/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003892# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003893/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003894 * Enables DAC state detection logic, for load-based TV detection.
3895 *
3896 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3897 * to off, for load detection to work.
3898 */
3899# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003900/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003901# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003902/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003903# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003904/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003905# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003906/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07003907# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003908/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07003909# define ENC_TVDAC_SLEW_FAST (1 << 6)
3910# define DAC_A_1_3_V (0 << 4)
3911# define DAC_A_1_1_V (1 << 4)
3912# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08003913# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003914# define DAC_B_1_3_V (0 << 2)
3915# define DAC_B_1_1_V (1 << 2)
3916# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08003917# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003918# define DAC_C_1_3_V (0 << 0)
3919# define DAC_C_1_1_V (1 << 0)
3920# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08003921# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003922
Ville Syrjälä646b4262014-04-25 20:14:30 +03003923/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003924 * CSC coefficients are stored in a floating point format with 9 bits of
3925 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3926 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3927 * -1 (0x3) being the only legal negative value.
3928 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003929#define TV_CSC_Y _MMIO(0x68010)
Jesse Barnes585fb112008-07-29 11:54:06 -07003930# define TV_RY_MASK 0x07ff0000
3931# define TV_RY_SHIFT 16
3932# define TV_GY_MASK 0x00000fff
3933# define TV_GY_SHIFT 0
3934
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003935#define TV_CSC_Y2 _MMIO(0x68014)
Jesse Barnes585fb112008-07-29 11:54:06 -07003936# define TV_BY_MASK 0x07ff0000
3937# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003938/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003939 * Y attenuation for component video.
3940 *
3941 * Stored in 1.9 fixed point.
3942 */
3943# define TV_AY_MASK 0x000003ff
3944# define TV_AY_SHIFT 0
3945
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003946#define TV_CSC_U _MMIO(0x68018)
Jesse Barnes585fb112008-07-29 11:54:06 -07003947# define TV_RU_MASK 0x07ff0000
3948# define TV_RU_SHIFT 16
3949# define TV_GU_MASK 0x000007ff
3950# define TV_GU_SHIFT 0
3951
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003952#define TV_CSC_U2 _MMIO(0x6801c)
Jesse Barnes585fb112008-07-29 11:54:06 -07003953# define TV_BU_MASK 0x07ff0000
3954# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003955/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003956 * U attenuation for component video.
3957 *
3958 * Stored in 1.9 fixed point.
3959 */
3960# define TV_AU_MASK 0x000003ff
3961# define TV_AU_SHIFT 0
3962
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003963#define TV_CSC_V _MMIO(0x68020)
Jesse Barnes585fb112008-07-29 11:54:06 -07003964# define TV_RV_MASK 0x0fff0000
3965# define TV_RV_SHIFT 16
3966# define TV_GV_MASK 0x000007ff
3967# define TV_GV_SHIFT 0
3968
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003969#define TV_CSC_V2 _MMIO(0x68024)
Jesse Barnes585fb112008-07-29 11:54:06 -07003970# define TV_BV_MASK 0x07ff0000
3971# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003972/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003973 * V attenuation for component video.
3974 *
3975 * Stored in 1.9 fixed point.
3976 */
3977# define TV_AV_MASK 0x000007ff
3978# define TV_AV_SHIFT 0
3979
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003980#define TV_CLR_KNOBS _MMIO(0x68028)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003981/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07003982# define TV_BRIGHTNESS_MASK 0xff000000
3983# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03003984/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003985# define TV_CONTRAST_MASK 0x00ff0000
3986# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003987/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003988# define TV_SATURATION_MASK 0x0000ff00
3989# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003990/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07003991# define TV_HUE_MASK 0x000000ff
3992# define TV_HUE_SHIFT 0
3993
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003994#define TV_CLR_LEVEL _MMIO(0x6802c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003995/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07003996# define TV_BLACK_LEVEL_MASK 0x01ff0000
3997# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003998/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07003999# define TV_BLANK_LEVEL_MASK 0x000001ff
4000# define TV_BLANK_LEVEL_SHIFT 0
4001
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004002#define TV_H_CTL_1 _MMIO(0x68030)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004003/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004004# define TV_HSYNC_END_MASK 0x1fff0000
4005# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004006/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07004007# define TV_HTOTAL_MASK 0x00001fff
4008# define TV_HTOTAL_SHIFT 0
4009
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004010#define TV_H_CTL_2 _MMIO(0x68034)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004011/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004012# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004013/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004014# define TV_HBURST_START_SHIFT 16
4015# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004016/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07004017# define TV_HBURST_LEN_SHIFT 0
4018# define TV_HBURST_LEN_MASK 0x0001fff
4019
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004020#define TV_H_CTL_3 _MMIO(0x68038)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004021/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07004022# define TV_HBLANK_END_SHIFT 16
4023# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004024/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07004025# define TV_HBLANK_START_SHIFT 0
4026# define TV_HBLANK_START_MASK 0x0001fff
4027
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004028#define TV_V_CTL_1 _MMIO(0x6803c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004029/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004030# define TV_NBR_END_SHIFT 16
4031# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03004032/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004033# define TV_VI_END_F1_SHIFT 8
4034# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03004035/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07004036# define TV_VI_END_F2_SHIFT 0
4037# define TV_VI_END_F2_MASK 0x0000003f
4038
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004039#define TV_V_CTL_2 _MMIO(0x68040)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004040/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07004041# define TV_VSYNC_LEN_MASK 0x07ff0000
4042# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004043/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07004044 * number of half lines.
4045 */
4046# define TV_VSYNC_START_F1_MASK 0x00007f00
4047# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03004048/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004049 * Offset of the start of vsync in field 2, measured in one less than the
4050 * number of half lines.
4051 */
4052# define TV_VSYNC_START_F2_MASK 0x0000007f
4053# define TV_VSYNC_START_F2_SHIFT 0
4054
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004055#define TV_V_CTL_3 _MMIO(0x68044)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004056/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07004057# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004058/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07004059# define TV_VEQ_LEN_MASK 0x007f0000
4060# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004061/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07004062 * the number of half lines.
4063 */
4064# define TV_VEQ_START_F1_MASK 0x0007f00
4065# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03004066/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004067 * Offset of the start of equalization in field 2, measured in one less than
4068 * the number of half lines.
4069 */
4070# define TV_VEQ_START_F2_MASK 0x000007f
4071# define TV_VEQ_START_F2_SHIFT 0
4072
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004073#define TV_V_CTL_4 _MMIO(0x68048)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004074/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004075 * Offset to start of vertical colorburst, measured in one less than the
4076 * number of lines from vertical start.
4077 */
4078# define TV_VBURST_START_F1_MASK 0x003f0000
4079# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004080/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004081 * Offset to the end of vertical colorburst, measured in one less than the
4082 * number of lines from the start of NBR.
4083 */
4084# define TV_VBURST_END_F1_MASK 0x000000ff
4085# define TV_VBURST_END_F1_SHIFT 0
4086
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004087#define TV_V_CTL_5 _MMIO(0x6804c)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004088/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004089 * Offset to start of vertical colorburst, measured in one less than the
4090 * number of lines from vertical start.
4091 */
4092# define TV_VBURST_START_F2_MASK 0x003f0000
4093# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004094/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004095 * Offset to the end of vertical colorburst, measured in one less than the
4096 * number of lines from the start of NBR.
4097 */
4098# define TV_VBURST_END_F2_MASK 0x000000ff
4099# define TV_VBURST_END_F2_SHIFT 0
4100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004101#define TV_V_CTL_6 _MMIO(0x68050)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004102/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004103 * Offset to start of vertical colorburst, measured in one less than the
4104 * number of lines from vertical start.
4105 */
4106# define TV_VBURST_START_F3_MASK 0x003f0000
4107# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004108/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004109 * Offset to the end of vertical colorburst, measured in one less than the
4110 * number of lines from the start of NBR.
4111 */
4112# define TV_VBURST_END_F3_MASK 0x000000ff
4113# define TV_VBURST_END_F3_SHIFT 0
4114
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004115#define TV_V_CTL_7 _MMIO(0x68054)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004116/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004117 * Offset to start of vertical colorburst, measured in one less than the
4118 * number of lines from vertical start.
4119 */
4120# define TV_VBURST_START_F4_MASK 0x003f0000
4121# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004122/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004123 * Offset to the end of vertical colorburst, measured in one less than the
4124 * number of lines from the start of NBR.
4125 */
4126# define TV_VBURST_END_F4_MASK 0x000000ff
4127# define TV_VBURST_END_F4_SHIFT 0
4128
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004129#define TV_SC_CTL_1 _MMIO(0x68060)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004130/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004131# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004132/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004133# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004134/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004135# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004136/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07004137# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004138/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07004139# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004140/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07004141# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004142/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07004143# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004144/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07004145# define TV_BURST_LEVEL_MASK 0x00ff0000
4146# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004147/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004148# define TV_SCDDA1_INC_MASK 0x00000fff
4149# define TV_SCDDA1_INC_SHIFT 0
4150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004151#define TV_SC_CTL_2 _MMIO(0x68064)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004152/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004153# define TV_SCDDA2_SIZE_MASK 0x7fff0000
4154# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004155/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004156# define TV_SCDDA2_INC_MASK 0x00007fff
4157# define TV_SCDDA2_INC_SHIFT 0
4158
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004159#define TV_SC_CTL_3 _MMIO(0x68068)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004160/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004161# define TV_SCDDA3_SIZE_MASK 0x7fff0000
4162# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004163/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07004164# define TV_SCDDA3_INC_MASK 0x00007fff
4165# define TV_SCDDA3_INC_SHIFT 0
4166
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004167#define TV_WIN_POS _MMIO(0x68070)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004168/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07004169# define TV_XPOS_MASK 0x1fff0000
4170# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004171/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07004172# define TV_YPOS_MASK 0x00000fff
4173# define TV_YPOS_SHIFT 0
4174
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004175#define TV_WIN_SIZE _MMIO(0x68074)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004176/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07004177# define TV_XSIZE_MASK 0x1fff0000
4178# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004179/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004180 * Vertical size of the display window, measured in pixels.
4181 *
4182 * Must be even for interlaced modes.
4183 */
4184# define TV_YSIZE_MASK 0x00000fff
4185# define TV_YSIZE_SHIFT 0
4186
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004187#define TV_FILTER_CTL_1 _MMIO(0x68080)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004188/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004189 * Enables automatic scaling calculation.
4190 *
4191 * If set, the rest of the registers are ignored, and the calculated values can
4192 * be read back from the register.
4193 */
4194# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004195/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004196 * Disables the vertical filter.
4197 *
4198 * This is required on modes more than 1024 pixels wide */
4199# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004200/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07004201# define TV_VADAPT (1 << 28)
4202# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004203/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07004204# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004205/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07004206# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004207/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07004208# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004209/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004210 * Sets the horizontal scaling factor.
4211 *
4212 * This should be the fractional part of the horizontal scaling factor divided
4213 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
4214 *
4215 * (src width - 1) / ((oversample * dest width) - 1)
4216 */
4217# define TV_HSCALE_FRAC_MASK 0x00003fff
4218# define TV_HSCALE_FRAC_SHIFT 0
4219
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004220#define TV_FILTER_CTL_2 _MMIO(0x68084)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004221/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004222 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4223 *
4224 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4225 */
4226# define TV_VSCALE_INT_MASK 0x00038000
4227# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03004228/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004229 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4230 *
4231 * \sa TV_VSCALE_INT_MASK
4232 */
4233# define TV_VSCALE_FRAC_MASK 0x00007fff
4234# define TV_VSCALE_FRAC_SHIFT 0
4235
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004236#define TV_FILTER_CTL_3 _MMIO(0x68088)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004237/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004238 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4239 *
4240 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4241 *
4242 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4243 */
4244# define TV_VSCALE_IP_INT_MASK 0x00038000
4245# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03004246/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004247 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4248 *
4249 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4250 *
4251 * \sa TV_VSCALE_IP_INT_MASK
4252 */
4253# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4254# define TV_VSCALE_IP_FRAC_SHIFT 0
4255
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004256#define TV_CC_CONTROL _MMIO(0x68090)
Jesse Barnes585fb112008-07-29 11:54:06 -07004257# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004258/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004259 * Specifies which field to send the CC data in.
4260 *
4261 * CC data is usually sent in field 0.
4262 */
4263# define TV_CC_FID_MASK (1 << 27)
4264# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03004265/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004266# define TV_CC_HOFF_MASK 0x03ff0000
4267# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004268/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07004269# define TV_CC_LINE_MASK 0x0000003f
4270# define TV_CC_LINE_SHIFT 0
4271
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004272#define TV_CC_DATA _MMIO(0x68094)
Jesse Barnes585fb112008-07-29 11:54:06 -07004273# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004274/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004275# define TV_CC_DATA_2_MASK 0x007f0000
4276# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004277/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004278# define TV_CC_DATA_1_MASK 0x0000007f
4279# define TV_CC_DATA_1_SHIFT 0
4280
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004281#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
4282#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
4283#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
4284#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
Jesse Barnes585fb112008-07-29 11:54:06 -07004285
Keith Packard040d87f2009-05-30 20:42:33 -07004286/* Display Port */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004287#define DP_A _MMIO(0x64000) /* eDP */
4288#define DP_B _MMIO(0x64100)
4289#define DP_C _MMIO(0x64200)
4290#define DP_D _MMIO(0x64300)
Keith Packard040d87f2009-05-30 20:42:33 -07004291
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004292#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
4293#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
4294#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
Ville Syrjäläe66eb812015-09-18 20:03:34 +03004295
Keith Packard040d87f2009-05-30 20:42:33 -07004296#define DP_PORT_EN (1 << 31)
4297#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08004298#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03004299#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4300#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08004301
Keith Packard040d87f2009-05-30 20:42:33 -07004302/* Link training mode - select a suitable mode for each stage */
4303#define DP_LINK_TRAIN_PAT_1 (0 << 28)
4304#define DP_LINK_TRAIN_PAT_2 (1 << 28)
4305#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4306#define DP_LINK_TRAIN_OFF (3 << 28)
4307#define DP_LINK_TRAIN_MASK (3 << 28)
4308#define DP_LINK_TRAIN_SHIFT 28
Ville Syrjäläaad3d142014-06-28 02:04:25 +03004309#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4310#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
Keith Packard040d87f2009-05-30 20:42:33 -07004311
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004312/* CPT Link training mode */
4313#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4314#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4315#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4316#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4317#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4318#define DP_LINK_TRAIN_SHIFT_CPT 8
4319
Keith Packard040d87f2009-05-30 20:42:33 -07004320/* Signal voltages. These are mostly controlled by the other end */
4321#define DP_VOLTAGE_0_4 (0 << 25)
4322#define DP_VOLTAGE_0_6 (1 << 25)
4323#define DP_VOLTAGE_0_8 (2 << 25)
4324#define DP_VOLTAGE_1_2 (3 << 25)
4325#define DP_VOLTAGE_MASK (7 << 25)
4326#define DP_VOLTAGE_SHIFT 25
4327
4328/* Signal pre-emphasis levels, like voltages, the other end tells us what
4329 * they want
4330 */
4331#define DP_PRE_EMPHASIS_0 (0 << 22)
4332#define DP_PRE_EMPHASIS_3_5 (1 << 22)
4333#define DP_PRE_EMPHASIS_6 (2 << 22)
4334#define DP_PRE_EMPHASIS_9_5 (3 << 22)
4335#define DP_PRE_EMPHASIS_MASK (7 << 22)
4336#define DP_PRE_EMPHASIS_SHIFT 22
4337
4338/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02004339#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07004340#define DP_PORT_WIDTH_MASK (7 << 19)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03004341#define DP_PORT_WIDTH_SHIFT 19
Keith Packard040d87f2009-05-30 20:42:33 -07004342
4343/* Mystic DPCD version 1.1 special mode */
4344#define DP_ENHANCED_FRAMING (1 << 18)
4345
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004346/* eDP */
4347#define DP_PLL_FREQ_270MHZ (0 << 16)
Ville Syrjäläb377e0d2015-10-29 21:25:59 +02004348#define DP_PLL_FREQ_162MHZ (1 << 16)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004349#define DP_PLL_FREQ_MASK (3 << 16)
4350
Ville Syrjälä646b4262014-04-25 20:14:30 +03004351/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07004352#define DP_PORT_REVERSAL (1 << 15)
4353
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004354/* eDP */
4355#define DP_PLL_ENABLE (1 << 14)
4356
Ville Syrjälä646b4262014-04-25 20:14:30 +03004357/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07004358#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4359
4360#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004361#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07004362
Ville Syrjälä646b4262014-04-25 20:14:30 +03004363/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07004364#define DP_COLOR_RANGE_16_235 (1 << 8)
4365
Ville Syrjälä646b4262014-04-25 20:14:30 +03004366/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07004367#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4368
Ville Syrjälä646b4262014-04-25 20:14:30 +03004369/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07004370#define DP_SYNC_VS_HIGH (1 << 4)
4371#define DP_SYNC_HS_HIGH (1 << 3)
4372
Ville Syrjälä646b4262014-04-25 20:14:30 +03004373/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07004374#define DP_DETECTED (1 << 2)
4375
Ville Syrjälä646b4262014-04-25 20:14:30 +03004376/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07004377 * signal sink for DDC etc. Max packet size supported
4378 * is 20 bytes in each direction, hence the 5 fixed
4379 * data registers
4380 */
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02004381#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
4382#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
4383#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
4384#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
4385#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
4386#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004387
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02004388#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
4389#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
4390#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
4391#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
4392#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
4393#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
Keith Packard040d87f2009-05-30 20:42:33 -07004394
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02004395#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
4396#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
4397#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
4398#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
4399#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
4400#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
Keith Packard040d87f2009-05-30 20:42:33 -07004401
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02004402#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
4403#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
4404#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
4405#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
4406#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
4407#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
Ville Syrjälä750a9512015-11-11 20:34:12 +02004408
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004409#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
4410#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Keith Packard040d87f2009-05-30 20:42:33 -07004411
4412#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4413#define DP_AUX_CH_CTL_DONE (1 << 30)
4414#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4415#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4416#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4417#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4418#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4419#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4420#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4421#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4422#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4423#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4424#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4425#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4426#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4427#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4428#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4429#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4430#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4431#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4432#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
Sonika Jindale3d99842015-01-22 14:30:54 +05304433#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4434#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4435#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
Ville Syrjälä395b2912015-09-18 20:03:40 +03004436#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
Sonika Jindale3d99842015-01-22 14:30:54 +05304437#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00004438#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
Keith Packard040d87f2009-05-30 20:42:33 -07004439
4440/*
4441 * Computing GMCH M and N values for the Display Port link
4442 *
4443 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4444 *
4445 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4446 *
4447 * The GMCH value is used internally
4448 *
4449 * bytes_per_pixel is the number of bytes coming out of the plane,
4450 * which is after the LUTs, so we want the bytes for our color format.
4451 * For our current usage, this is always 3, one byte for R, G and B.
4452 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02004453#define _PIPEA_DATA_M_G4X 0x70050
4454#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07004455
4456/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004457#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02004458#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004459#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07004460
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004461#define DATA_LINK_M_N_MASK (0xffffff)
4462#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07004463
Daniel Vettere3b95f12013-05-03 11:49:49 +02004464#define _PIPEA_DATA_N_G4X 0x70054
4465#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07004466#define PIPE_GMCH_DATA_N_MASK (0xffffff)
4467
4468/*
4469 * Computing Link M and N values for the Display Port link
4470 *
4471 * Link M / N = pixel_clock / ls_clk
4472 *
4473 * (the DP spec calls pixel_clock the 'strm_clk')
4474 *
4475 * The Link value is transmitted in the Main Stream
4476 * Attributes and VB-ID.
4477 */
4478
Daniel Vettere3b95f12013-05-03 11:49:49 +02004479#define _PIPEA_LINK_M_G4X 0x70060
4480#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07004481#define PIPEA_DP_LINK_M_MASK (0xffffff)
4482
Daniel Vettere3b95f12013-05-03 11:49:49 +02004483#define _PIPEA_LINK_N_G4X 0x70064
4484#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07004485#define PIPEA_DP_LINK_N_MASK (0xffffff)
4486
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004487#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4488#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4489#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4490#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004491
Jesse Barnes585fb112008-07-29 11:54:06 -07004492/* Display & cursor control */
4493
4494/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004495#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03004496#define DSL_LINEMASK_GEN2 0x00000fff
4497#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004498#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01004499#define PIPECONF_ENABLE (1<<31)
4500#define PIPECONF_DISABLE 0
4501#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07004502#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03004503#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00004504#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01004505#define PIPECONF_SINGLE_WIDE 0
4506#define PIPECONF_PIPE_UNLOCKED 0
4507#define PIPECONF_PIPE_LOCKED (1<<25)
4508#define PIPECONF_PALETTE 0
4509#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07004510#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01004511#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03004512#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01004513/* Note that pre-gen3 does not support interlaced display directly. Panel
4514 * fitting must be disabled on pre-ilk for interlaced. */
4515#define PIPECONF_PROGRESSIVE (0 << 21)
4516#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4517#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4518#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4519#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4520/* Ironlake and later have a complete new set of values for interlaced. PFIT
4521 * means panel fitter required, PF means progressive fetch, DBL means power
4522 * saving pixel doubling. */
4523#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4524#define PIPECONF_INTERLACED_ILK (3 << 21)
4525#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4526#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004527#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304528#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07004529#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05304530#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02004531#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004532#define PIPECONF_BPC_MASK (0x7 << 5)
4533#define PIPECONF_8BPC (0<<5)
4534#define PIPECONF_10BPC (1<<5)
4535#define PIPECONF_6BPC (2<<5)
4536#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07004537#define PIPECONF_DITHER_EN (1<<4)
4538#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4539#define PIPECONF_DITHER_TYPE_SP (0<<2)
4540#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4541#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4542#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004543#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07004544#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02004545#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07004546#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4547#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004548#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07004549#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004550#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004551#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4552#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4553#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4554#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02004555#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07004556#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4557#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4558#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02004559#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004560#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07004561#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4562#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004563#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07004564#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004565#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07004566#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02004567#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4568#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07004569#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4570#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004571#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07004572#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02004573#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07004574#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4575#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4576#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4577#define PIPE_DPST_EVENT_STATUS (1UL<<7)
Imre Deak10c59c52014-02-10 18:42:48 +02004578#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004579#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07004580#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4581#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02004582#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004583#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07004584#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4585#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004586#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07004587#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004588#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07004589#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4590
Imre Deak755e9012014-02-10 18:42:47 +02004591#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4592#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4593
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03004594#define PIPE_A_OFFSET 0x70000
4595#define PIPE_B_OFFSET 0x71000
4596#define PIPE_C_OFFSET 0x72000
4597#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004598/*
4599 * There's actually no pipe EDP. Some pipe registers have
4600 * simply shifted from the pipe to the transcoder, while
4601 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4602 * to access such registers in transcoder EDP.
4603 */
4604#define PIPE_EDP_OFFSET 0x7f000
4605
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004606#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004607 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4608 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004609
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004610#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
4611#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
4612#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
4613#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
4614#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01004615
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004616#define _PIPE_MISC_A 0x70030
4617#define _PIPE_MISC_B 0x71030
4618#define PIPEMISC_DITHER_BPC_MASK (7<<5)
4619#define PIPEMISC_DITHER_8_BPC (0<<5)
4620#define PIPEMISC_DITHER_10_BPC (1<<5)
4621#define PIPEMISC_DITHER_6_BPC (2<<5)
4622#define PIPEMISC_DITHER_12_BPC (3<<5)
4623#define PIPEMISC_DITHER_ENABLE (1<<4)
4624#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4625#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004626#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004627
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004628#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07004629#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004630#define PIPEB_HLINE_INT_EN (1<<28)
4631#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02004632#define SPRITED_FLIP_DONE_INT_EN (1<<26)
4633#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4634#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004635#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07004636#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004637#define PIPEA_HLINE_INT_EN (1<<20)
4638#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02004639#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4640#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004641#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004642#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4643#define PIPEC_HLINE_INT_EN (1<<12)
4644#define PIPEC_VBLANK_INT_EN (1<<11)
4645#define SPRITEF_FLIPDONE_INT_EN (1<<10)
4646#define SPRITEE_FLIPDONE_INT_EN (1<<9)
4647#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004648
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004649#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004650#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4651#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4652#define PLANEC_INVALID_GTT_INT_EN (1<<25)
4653#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004654#define CURSORB_INVALID_GTT_INT_EN (1<<23)
4655#define CURSORA_INVALID_GTT_INT_EN (1<<22)
4656#define SPRITED_INVALID_GTT_INT_EN (1<<21)
4657#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4658#define PLANEB_INVALID_GTT_INT_EN (1<<19)
4659#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4660#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4661#define PLANEA_INVALID_GTT_INT_EN (1<<16)
4662#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004663#define DPINVGTT_EN_MASK_CHV 0xfff0000
4664#define SPRITEF_INVALID_GTT_STATUS (1<<11)
4665#define SPRITEE_INVALID_GTT_STATUS (1<<10)
4666#define PLANEC_INVALID_GTT_STATUS (1<<9)
4667#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004668#define CURSORB_INVALID_GTT_STATUS (1<<7)
4669#define CURSORA_INVALID_GTT_STATUS (1<<6)
4670#define SPRITED_INVALID_GTT_STATUS (1<<5)
4671#define SPRITEC_INVALID_GTT_STATUS (1<<4)
4672#define PLANEB_INVALID_GTT_STATUS (1<<3)
4673#define SPRITEB_INVALID_GTT_STATUS (1<<2)
4674#define SPRITEA_INVALID_GTT_STATUS (1<<1)
4675#define PLANEA_INVALID_GTT_STATUS (1<<0)
4676#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004677#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004678
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004679#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
Jesse Barnes585fb112008-07-29 11:54:06 -07004680#define DSPARB_CSTART_MASK (0x7f << 7)
4681#define DSPARB_CSTART_SHIFT 7
4682#define DSPARB_BSTART_MASK (0x7f)
4683#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08004684#define DSPARB_BEND_SHIFT 9 /* on 855 */
4685#define DSPARB_AEND_SHIFT 0
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004686#define DSPARB_SPRITEA_SHIFT_VLV 0
4687#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4688#define DSPARB_SPRITEB_SHIFT_VLV 8
4689#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4690#define DSPARB_SPRITEC_SHIFT_VLV 16
4691#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4692#define DSPARB_SPRITED_SHIFT_VLV 24
4693#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004694#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004695#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4696#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4697#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4698#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4699#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4700#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4701#define DSPARB_SPRITED_HI_SHIFT_VLV 12
4702#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4703#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4704#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4705#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4706#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004707#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004708#define DSPARB_SPRITEE_SHIFT_VLV 0
4709#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4710#define DSPARB_SPRITEF_SHIFT_VLV 8
4711#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
Ville Syrjäläb5004722015-03-05 21:19:47 +02004712
Ville Syrjälä0a560672014-06-11 16:51:18 +03004713/* pnv/gen4/g4x/vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004714#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004715#define DSPFW_SR_SHIFT 23
4716#define DSPFW_SR_MASK (0x1ff<<23)
4717#define DSPFW_CURSORB_SHIFT 16
4718#define DSPFW_CURSORB_MASK (0x3f<<16)
4719#define DSPFW_PLANEB_SHIFT 8
4720#define DSPFW_PLANEB_MASK (0x7f<<8)
4721#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4722#define DSPFW_PLANEA_SHIFT 0
4723#define DSPFW_PLANEA_MASK (0x7f<<0)
4724#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004725#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004726#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4727#define DSPFW_FBC_SR_SHIFT 28
4728#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4729#define DSPFW_FBC_HPLL_SR_SHIFT 24
4730#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4731#define DSPFW_SPRITEB_SHIFT (16)
4732#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4733#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4734#define DSPFW_CURSORA_SHIFT 8
4735#define DSPFW_CURSORA_MASK (0x3f<<8)
Ville Syrjäläf4998962015-03-10 17:02:21 +02004736#define DSPFW_PLANEC_OLD_SHIFT 0
4737#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004738#define DSPFW_SPRITEA_SHIFT 0
4739#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4740#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004741#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004742#define DSPFW_HPLL_SR_EN (1<<31)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004743#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004744#define DSPFW_CURSOR_SR_SHIFT 24
Zhao Yakuid4294342010-03-22 22:45:36 +08004745#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4746#define DSPFW_HPLL_CURSOR_SHIFT 16
4747#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004748#define DSPFW_HPLL_SR_SHIFT 0
4749#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4750
4751/* vlv/chv */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004752#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004753#define DSPFW_SPRITEB_WM1_SHIFT 16
4754#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4755#define DSPFW_CURSORA_WM1_SHIFT 8
4756#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4757#define DSPFW_SPRITEA_WM1_SHIFT 0
4758#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004759#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004760#define DSPFW_PLANEB_WM1_SHIFT 24
4761#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4762#define DSPFW_PLANEA_WM1_SHIFT 16
4763#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4764#define DSPFW_CURSORB_WM1_SHIFT 8
4765#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4766#define DSPFW_CURSOR_SR_WM1_SHIFT 0
4767#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004768#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004769#define DSPFW_SR_WM1_SHIFT 0
4770#define DSPFW_SR_WM1_MASK (0x1ff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004771#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
4772#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004773#define DSPFW_SPRITED_WM1_SHIFT 24
4774#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4775#define DSPFW_SPRITED_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004776#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004777#define DSPFW_SPRITEC_WM1_SHIFT 8
4778#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4779#define DSPFW_SPRITEC_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004780#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004781#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004782#define DSPFW_SPRITEF_WM1_SHIFT 24
4783#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4784#define DSPFW_SPRITEF_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004785#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004786#define DSPFW_SPRITEE_WM1_SHIFT 8
4787#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4788#define DSPFW_SPRITEE_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004789#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004790#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004791#define DSPFW_PLANEC_WM1_SHIFT 24
4792#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4793#define DSPFW_PLANEC_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004794#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004795#define DSPFW_CURSORC_WM1_SHIFT 8
4796#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4797#define DSPFW_CURSORC_SHIFT 0
4798#define DSPFW_CURSORC_MASK (0x3f<<0)
4799
4800/* vlv/chv high order bits */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004801#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004802#define DSPFW_SR_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004803#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004804#define DSPFW_SPRITEF_HI_SHIFT 23
4805#define DSPFW_SPRITEF_HI_MASK (1<<23)
4806#define DSPFW_SPRITEE_HI_SHIFT 22
4807#define DSPFW_SPRITEE_HI_MASK (1<<22)
4808#define DSPFW_PLANEC_HI_SHIFT 21
4809#define DSPFW_PLANEC_HI_MASK (1<<21)
4810#define DSPFW_SPRITED_HI_SHIFT 20
4811#define DSPFW_SPRITED_HI_MASK (1<<20)
4812#define DSPFW_SPRITEC_HI_SHIFT 16
4813#define DSPFW_SPRITEC_HI_MASK (1<<16)
4814#define DSPFW_PLANEB_HI_SHIFT 12
4815#define DSPFW_PLANEB_HI_MASK (1<<12)
4816#define DSPFW_SPRITEB_HI_SHIFT 8
4817#define DSPFW_SPRITEB_HI_MASK (1<<8)
4818#define DSPFW_SPRITEA_HI_SHIFT 4
4819#define DSPFW_SPRITEA_HI_MASK (1<<4)
4820#define DSPFW_PLANEA_HI_SHIFT 0
4821#define DSPFW_PLANEA_HI_MASK (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004822#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004823#define DSPFW_SR_WM1_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004824#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004825#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4826#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4827#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4828#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4829#define DSPFW_PLANEC_WM1_HI_SHIFT 21
4830#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4831#define DSPFW_SPRITED_WM1_HI_SHIFT 20
4832#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4833#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4834#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4835#define DSPFW_PLANEB_WM1_HI_SHIFT 12
4836#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4837#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4838#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4839#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4840#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4841#define DSPFW_PLANEA_WM1_HI_SHIFT 0
4842#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004843
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004844/* drain latency register values*/
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004845#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004846#define DDL_CURSOR_SHIFT 24
Gajanan Bhat01e184c2014-08-07 17:03:30 +05304847#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004848#define DDL_PLANE_SHIFT 0
Ville Syrjälä341c5262015-03-05 21:19:44 +02004849#define DDL_PRECISION_HIGH (1<<7)
4850#define DDL_PRECISION_LOW (0<<7)
Gajanan Bhat0948c262014-08-07 01:58:24 +05304851#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004852
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004853#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
Ville Syrjäläc6beb132015-03-05 21:19:48 +02004854#define CBR_PND_DEADLINE_DISABLE (1<<31)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03004855#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
Ville Syrjäläc6beb132015-03-05 21:19:48 +02004856
Ville Syrjäläc2317752016-03-15 16:39:56 +02004857#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
4858#define CBR_DPLLBMD_PIPE_C (1<<29)
4859#define CBR_DPLLBMD_PIPE_B (1<<18)
4860
Shaohua Li7662c8b2009-06-26 11:23:55 +08004861/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09004862#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08004863#define I915_FIFO_LINE_SIZE 64
4864#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09004865
Jesse Barnesceb04242012-03-28 13:39:22 -07004866#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09004867#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08004868#define I965_FIFO_SIZE 512
4869#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08004870#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004871#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004872#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09004873
Jesse Barnesceb04242012-03-28 13:39:22 -07004874#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09004875#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08004876#define I915_MAX_WM 0x3f
4877
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004878#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4879#define PINEVIEW_FIFO_LINE_SIZE 64
4880#define PINEVIEW_MAX_WM 0x1ff
4881#define PINEVIEW_DFT_WM 0x3f
4882#define PINEVIEW_DFT_HPLLOFF_WM 0
4883#define PINEVIEW_GUARD_WM 10
4884#define PINEVIEW_CURSOR_FIFO 64
4885#define PINEVIEW_CURSOR_MAX_WM 0x3f
4886#define PINEVIEW_CURSOR_DFT_WM 0
4887#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08004888
Jesse Barnesceb04242012-03-28 13:39:22 -07004889#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004890#define I965_CURSOR_FIFO 64
4891#define I965_CURSOR_MAX_WM 32
4892#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004893
Pradeep Bhatfae12672014-11-04 17:06:39 +00004894/* Watermark register definitions for SKL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02004895#define _CUR_WM_A_0 0x70140
4896#define _CUR_WM_B_0 0x71140
4897#define _PLANE_WM_1_A_0 0x70240
4898#define _PLANE_WM_1_B_0 0x71240
4899#define _PLANE_WM_2_A_0 0x70340
4900#define _PLANE_WM_2_B_0 0x71340
4901#define _PLANE_WM_TRANS_1_A_0 0x70268
4902#define _PLANE_WM_TRANS_1_B_0 0x71268
4903#define _PLANE_WM_TRANS_2_A_0 0x70368
4904#define _PLANE_WM_TRANS_2_B_0 0x71368
4905#define _CUR_WM_TRANS_A_0 0x70168
4906#define _CUR_WM_TRANS_B_0 0x71168
Pradeep Bhatfae12672014-11-04 17:06:39 +00004907#define PLANE_WM_EN (1 << 31)
4908#define PLANE_WM_LINES_SHIFT 14
4909#define PLANE_WM_LINES_MASK 0x1f
4910#define PLANE_WM_BLOCKS_MASK 0x3ff
4911
Ville Syrjälä086f8e82015-11-04 23:20:01 +02004912#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004913#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4914#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00004915
Ville Syrjälä086f8e82015-11-04 23:20:01 +02004916#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4917#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00004918#define _PLANE_WM_BASE(pipe, plane) \
4919 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4920#define PLANE_WM(pipe, plane, level) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004921 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
Pradeep Bhatfae12672014-11-04 17:06:39 +00004922#define _PLANE_WM_TRANS_1(pipe) \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02004923 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00004924#define _PLANE_WM_TRANS_2(pipe) \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02004925 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
Pradeep Bhatfae12672014-11-04 17:06:39 +00004926#define PLANE_WM_TRANS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004927 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
Pradeep Bhatfae12672014-11-04 17:06:39 +00004928
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004929/* define the Watermark register on Ironlake */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004930#define WM0_PIPEA_ILK _MMIO(0x45100)
Ville Syrjälä1996d622013-10-09 19:18:07 +03004931#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004932#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03004933#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004934#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004935#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004936
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004937#define WM0_PIPEB_ILK _MMIO(0x45104)
4938#define WM0_PIPEC_IVB _MMIO(0x45200)
4939#define WM1_LP_ILK _MMIO(0x45108)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004940#define WM1_LP_SR_EN (1<<31)
4941#define WM1_LP_LATENCY_SHIFT 24
4942#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01004943#define WM1_LP_FBC_MASK (0xf<<20)
4944#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07004945#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03004946#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004947#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004948#define WM1_LP_CURSOR_MASK (0xff)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004949#define WM2_LP_ILK _MMIO(0x4510c)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004950#define WM2_LP_EN (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004951#define WM3_LP_ILK _MMIO(0x45110)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004952#define WM3_LP_EN (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004953#define WM1S_LP_ILK _MMIO(0x45120)
4954#define WM2S_LP_IVB _MMIO(0x45124)
4955#define WM3S_LP_IVB _MMIO(0x45128)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004956#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004957
Paulo Zanonicca32e92013-05-31 11:45:06 -03004958#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4959 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4960 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4961
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004962/* Memory latency timer register */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004963#define MLTR_ILK _MMIO(0x11222)
Jesse Barnesb79d4992010-12-21 13:10:23 -08004964#define MLTR_WM1_SHIFT 0
4965#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004966/* the unit of memory self-refresh latency time is 0.5us */
4967#define ILK_SRLT_MASK 0x3f
4968
Yuanhan Liu13982612010-12-15 15:42:31 +08004969
4970/* the address where we get all kinds of latency value */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004971#define SSKPD _MMIO(0x5d10)
Yuanhan Liu13982612010-12-15 15:42:31 +08004972#define SSKPD_WM_MASK 0x3f
4973#define SSKPD_WM0_SHIFT 0
4974#define SSKPD_WM1_SHIFT 8
4975#define SSKPD_WM2_SHIFT 16
4976#define SSKPD_WM3_SHIFT 24
4977
Jesse Barnes585fb112008-07-29 11:54:06 -07004978/*
4979 * The two pipe frame counter registers are not synchronized, so
4980 * reading a stable value is somewhat tricky. The following code
4981 * should work:
4982 *
4983 * do {
4984 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4985 * PIPE_FRAME_HIGH_SHIFT;
4986 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4987 * PIPE_FRAME_LOW_SHIFT);
4988 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4989 * PIPE_FRAME_HIGH_SHIFT);
4990 * } while (high1 != high2);
4991 * frame = (high1 << 8) | low1;
4992 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004993#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07004994#define PIPE_FRAME_HIGH_MASK 0x0000ffff
4995#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004996#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07004997#define PIPE_FRAME_LOW_MASK 0xff000000
4998#define PIPE_FRAME_LOW_SHIFT 24
4999#define PIPE_PIXEL_MASK 0x00ffffff
5000#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08005001/* GM45+ just has to be different */
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03005002#define _PIPEA_FRMCOUNT_G4X 0x70040
5003#define _PIPEA_FLIPCOUNT_G4X 0x70044
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005004#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5005#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
Jesse Barnes585fb112008-07-29 11:54:06 -07005006
5007/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005008#define _CURACNTR 0x70080
Jesse Barnes14b603912009-05-20 16:47:08 -04005009/* Old style CUR*CNTR flags (desktop 8xx) */
5010#define CURSOR_ENABLE 0x80000000
5011#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03005012#define CURSOR_STRIDE_SHIFT 28
5013#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005014#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b603912009-05-20 16:47:08 -04005015#define CURSOR_FORMAT_SHIFT 24
5016#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5017#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5018#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5019#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5020#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5021#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5022/* New style CUR*CNTR flags */
5023#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07005024#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05305025#define CURSOR_MODE_128_32B_AX 0x02
5026#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07005027#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05305028#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5029#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07005030#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b603912009-05-20 16:47:08 -04005031#define MCURSOR_PIPE_SELECT (1 << 28)
5032#define MCURSOR_PIPE_A 0x00
5033#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07005034#define MCURSOR_GAMMA_ENABLE (1 << 26)
Ville Syrjälä4398ad42014-10-23 07:41:34 -07005035#define CURSOR_ROTATE_180 (1<<15)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03005036#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005037#define _CURABASE 0x70084
5038#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07005039#define CURSOR_POS_MASK 0x007FF
5040#define CURSOR_POS_SIGN 0x8000
5041#define CURSOR_X_SHIFT 0
5042#define CURSOR_Y_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005043#define CURSIZE _MMIO(0x700a0)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005044#define _CURBCNTR 0x700c0
5045#define _CURBBASE 0x700c4
5046#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07005047
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005048#define _CURBCNTR_IVB 0x71080
5049#define _CURBBASE_IVB 0x71084
5050#define _CURBPOS_IVB 0x71088
5051
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005052#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005053 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
5054 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00005055
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03005056#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
5057#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
5058#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
5059
5060#define CURSOR_A_OFFSET 0x70080
5061#define CURSOR_B_OFFSET 0x700c0
5062#define CHV_CURSOR_C_OFFSET 0x700e0
5063#define IVB_CURSOR_B_OFFSET 0x71080
5064#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005065
Jesse Barnes585fb112008-07-29 11:54:06 -07005066/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005067#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07005068#define DISPLAY_PLANE_ENABLE (1<<31)
5069#define DISPLAY_PLANE_DISABLE 0
5070#define DISPPLANE_GAMMA_ENABLE (1<<30)
5071#define DISPPLANE_GAMMA_DISABLE 0
5072#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02005073#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07005074#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02005075#define DISPPLANE_BGRA555 (0x3<<26)
5076#define DISPPLANE_BGRX555 (0x4<<26)
5077#define DISPPLANE_BGRX565 (0x5<<26)
5078#define DISPPLANE_BGRX888 (0x6<<26)
5079#define DISPPLANE_BGRA888 (0x7<<26)
5080#define DISPPLANE_RGBX101010 (0x8<<26)
5081#define DISPPLANE_RGBA101010 (0x9<<26)
5082#define DISPPLANE_BGRX101010 (0xa<<26)
5083#define DISPPLANE_RGBX161616 (0xc<<26)
5084#define DISPPLANE_RGBX888 (0xe<<26)
5085#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07005086#define DISPPLANE_STEREO_ENABLE (1<<25)
5087#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005088#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08005089#define DISPPLANE_SEL_PIPE_SHIFT 24
5090#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07005091#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08005092#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07005093#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
5094#define DISPPLANE_SRC_KEY_DISABLE 0
5095#define DISPPLANE_LINE_DOUBLE (1<<20)
5096#define DISPPLANE_NO_LINE_DOUBLE 0
5097#define DISPPLANE_STEREO_POLARITY_FIRST 0
5098#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005099#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
5100#define DISPPLANE_ROTATE_180 (1<<15)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005101#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07005102#define DISPPLANE_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005103#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005104#define _DSPAADDR 0x70184
5105#define _DSPASTRIDE 0x70188
5106#define _DSPAPOS 0x7018C /* reserved */
5107#define _DSPASIZE 0x70190
5108#define _DSPASURF 0x7019C /* 965+ only */
5109#define _DSPATILEOFF 0x701A4 /* 965+ only */
5110#define _DSPAOFFSET 0x701A4 /* HSW */
5111#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07005112
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005113#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
5114#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
5115#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
5116#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
5117#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
5118#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
5119#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
5120#define DSPLINOFF(plane) DSPADDR(plane)
5121#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
5122#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01005123
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005124/* CHV pipe B blender and primary plane */
5125#define _CHV_BLEND_A 0x60a00
5126#define CHV_BLEND_LEGACY (0<<30)
5127#define CHV_BLEND_ANDROID (1<<30)
5128#define CHV_BLEND_MPO (2<<30)
5129#define CHV_BLEND_MASK (3<<30)
5130#define _CHV_CANVAS_A 0x60a04
5131#define _PRIMPOS_A 0x60a08
5132#define _PRIMSIZE_A 0x60a0c
5133#define _PRIMCNSTALPHA_A 0x60a10
5134#define PRIM_CONST_ALPHA_ENABLE (1<<31)
5135
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005136#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
5137#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
5138#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
5139#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
5140#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005141
Armin Reese446f2542012-03-30 16:20:16 -07005142/* Display/Sprite base address macros */
5143#define DISP_BASEADDR_MASK (0xfffff000)
5144#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
5145#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07005146
Ville Syrjälä85fa7922015-09-18 20:03:43 +03005147/*
5148 * VBIOS flags
5149 * gen2:
5150 * [00:06] alm,mgm
5151 * [10:16] all
5152 * [30:32] alm,mgm
5153 * gen3+:
5154 * [00:0f] all
5155 * [10:1f] all
5156 * [30:32] all
5157 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005158#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5159#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5160#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5161#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07005162
5163/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005164#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
5165#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
5166#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03005167#define _PIPEBFRAMEHIGH 0x71040
5168#define _PIPEBFRAMEPIXEL 0x71044
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03005169#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
5170#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08005171
Jesse Barnes585fb112008-07-29 11:54:06 -07005172
5173/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005174#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07005175#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
5176#define DISPPLANE_ALPHA_TRANS_DISABLE 0
5177#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
5178#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005179#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
5180#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
5181#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
5182#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
5183#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
5184#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
5185#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
5186#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07005187
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005188/* Sprite A control */
5189#define _DVSACNTR 0x72180
5190#define DVS_ENABLE (1<<31)
5191#define DVS_GAMMA_ENABLE (1<<30)
5192#define DVS_PIXFORMAT_MASK (3<<25)
5193#define DVS_FORMAT_YUV422 (0<<25)
5194#define DVS_FORMAT_RGBX101010 (1<<25)
5195#define DVS_FORMAT_RGBX888 (2<<25)
5196#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005197#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005198#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08005199#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005200#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
5201#define DVS_YUV_ORDER_YUYV (0<<16)
5202#define DVS_YUV_ORDER_UYVY (1<<16)
5203#define DVS_YUV_ORDER_YVYU (2<<16)
5204#define DVS_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05305205#define DVS_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005206#define DVS_DEST_KEY (1<<2)
5207#define DVS_TRICKLE_FEED_DISABLE (1<<14)
5208#define DVS_TILED (1<<10)
5209#define _DVSALINOFF 0x72184
5210#define _DVSASTRIDE 0x72188
5211#define _DVSAPOS 0x7218c
5212#define _DVSASIZE 0x72190
5213#define _DVSAKEYVAL 0x72194
5214#define _DVSAKEYMSK 0x72198
5215#define _DVSASURF 0x7219c
5216#define _DVSAKEYMAXVAL 0x721a0
5217#define _DVSATILEOFF 0x721a4
5218#define _DVSASURFLIVE 0x721ac
5219#define _DVSASCALE 0x72204
5220#define DVS_SCALE_ENABLE (1<<31)
5221#define DVS_FILTER_MASK (3<<29)
5222#define DVS_FILTER_MEDIUM (0<<29)
5223#define DVS_FILTER_ENHANCING (1<<29)
5224#define DVS_FILTER_SOFTENING (2<<29)
5225#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5226#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5227#define _DVSAGAMC 0x72300
5228
5229#define _DVSBCNTR 0x73180
5230#define _DVSBLINOFF 0x73184
5231#define _DVSBSTRIDE 0x73188
5232#define _DVSBPOS 0x7318c
5233#define _DVSBSIZE 0x73190
5234#define _DVSBKEYVAL 0x73194
5235#define _DVSBKEYMSK 0x73198
5236#define _DVSBSURF 0x7319c
5237#define _DVSBKEYMAXVAL 0x731a0
5238#define _DVSBTILEOFF 0x731a4
5239#define _DVSBSURFLIVE 0x731ac
5240#define _DVSBSCALE 0x73204
5241#define _DVSBGAMC 0x73300
5242
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005243#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5244#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5245#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5246#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
5247#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
5248#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5249#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5250#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5251#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5252#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5253#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5254#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005255
5256#define _SPRA_CTL 0x70280
5257#define SPRITE_ENABLE (1<<31)
5258#define SPRITE_GAMMA_ENABLE (1<<30)
5259#define SPRITE_PIXFORMAT_MASK (7<<25)
5260#define SPRITE_FORMAT_YUV422 (0<<25)
5261#define SPRITE_FORMAT_RGBX101010 (1<<25)
5262#define SPRITE_FORMAT_RGBX888 (2<<25)
5263#define SPRITE_FORMAT_RGBX161616 (3<<25)
5264#define SPRITE_FORMAT_YUV444 (4<<25)
5265#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005266#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005267#define SPRITE_SOURCE_KEY (1<<22)
5268#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5269#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5270#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5271#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5272#define SPRITE_YUV_ORDER_YUYV (0<<16)
5273#define SPRITE_YUV_ORDER_UYVY (1<<16)
5274#define SPRITE_YUV_ORDER_YVYU (2<<16)
5275#define SPRITE_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05305276#define SPRITE_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005277#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5278#define SPRITE_INT_GAMMA_ENABLE (1<<13)
5279#define SPRITE_TILED (1<<10)
5280#define SPRITE_DEST_KEY (1<<2)
5281#define _SPRA_LINOFF 0x70284
5282#define _SPRA_STRIDE 0x70288
5283#define _SPRA_POS 0x7028c
5284#define _SPRA_SIZE 0x70290
5285#define _SPRA_KEYVAL 0x70294
5286#define _SPRA_KEYMSK 0x70298
5287#define _SPRA_SURF 0x7029c
5288#define _SPRA_KEYMAX 0x702a0
5289#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01005290#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005291#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005292#define _SPRA_SCALE 0x70304
5293#define SPRITE_SCALE_ENABLE (1<<31)
5294#define SPRITE_FILTER_MASK (3<<29)
5295#define SPRITE_FILTER_MEDIUM (0<<29)
5296#define SPRITE_FILTER_ENHANCING (1<<29)
5297#define SPRITE_FILTER_SOFTENING (2<<29)
5298#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5299#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5300#define _SPRA_GAMC 0x70400
5301
5302#define _SPRB_CTL 0x71280
5303#define _SPRB_LINOFF 0x71284
5304#define _SPRB_STRIDE 0x71288
5305#define _SPRB_POS 0x7128c
5306#define _SPRB_SIZE 0x71290
5307#define _SPRB_KEYVAL 0x71294
5308#define _SPRB_KEYMSK 0x71298
5309#define _SPRB_SURF 0x7129c
5310#define _SPRB_KEYMAX 0x712a0
5311#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01005312#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005313#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005314#define _SPRB_SCALE 0x71304
5315#define _SPRB_GAMC 0x71400
5316
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005317#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5318#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5319#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5320#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
5321#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5322#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5323#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5324#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5325#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5326#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5327#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5328#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5329#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5330#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005331
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005332#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005333#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08005334#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005335#define SP_PIXFORMAT_MASK (0xf<<26)
5336#define SP_FORMAT_YUV422 (0<<26)
5337#define SP_FORMAT_BGR565 (5<<26)
5338#define SP_FORMAT_BGRX8888 (6<<26)
5339#define SP_FORMAT_BGRA8888 (7<<26)
5340#define SP_FORMAT_RGBX1010102 (8<<26)
5341#define SP_FORMAT_RGBA1010102 (9<<26)
5342#define SP_FORMAT_RGBX8888 (0xe<<26)
5343#define SP_FORMAT_RGBA8888 (0xf<<26)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005344#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005345#define SP_SOURCE_KEY (1<<22)
5346#define SP_YUV_BYTE_ORDER_MASK (3<<16)
5347#define SP_YUV_ORDER_YUYV (0<<16)
5348#define SP_YUV_ORDER_UYVY (1<<16)
5349#define SP_YUV_ORDER_YVYU (2<<16)
5350#define SP_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05305351#define SP_ROTATE_180 (1<<15)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005352#define SP_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005353#define SP_MIRROR (1<<8) /* CHV pipe B */
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005354#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5355#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5356#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5357#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5358#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5359#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5360#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5361#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5362#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5363#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005364#define SP_CONST_ALPHA_ENABLE (1<<31)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005365#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005366
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005367#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5368#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5369#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5370#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5371#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5372#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5373#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5374#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5375#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5376#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5377#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5378#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005379
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005380#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5381#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5382#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5383#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5384#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5385#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5386#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5387#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5388#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5389#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5390#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5391#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005392
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005393/*
5394 * CHV pipe B sprite CSC
5395 *
5396 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5397 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5398 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5399 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005400#define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5401#define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5402#define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005403#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5404#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5405
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005406#define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5407#define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5408#define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5409#define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5410#define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005411#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5412#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5413
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005414#define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5415#define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5416#define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005417#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5418#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5419
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005420#define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5421#define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5422#define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005423#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5424#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5425
Damien Lespiau70d21f02013-07-03 21:06:04 +01005426/* Skylake plane registers */
5427
5428#define _PLANE_CTL_1_A 0x70180
5429#define _PLANE_CTL_2_A 0x70280
5430#define _PLANE_CTL_3_A 0x70380
5431#define PLANE_CTL_ENABLE (1 << 31)
5432#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5433#define PLANE_CTL_FORMAT_MASK (0xf << 24)
5434#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5435#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5436#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5437#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5438#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5439#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5440#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5441#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5442#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005443#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5444#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5445#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
Damien Lespiau70d21f02013-07-03 21:06:04 +01005446#define PLANE_CTL_ORDER_BGRX (0 << 20)
5447#define PLANE_CTL_ORDER_RGBX (1 << 20)
5448#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5449#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5450#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5451#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5452#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5453#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5454#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5455#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5456#define PLANE_CTL_TILED_MASK (0x7 << 10)
5457#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5458#define PLANE_CTL_TILED_X ( 1 << 10)
5459#define PLANE_CTL_TILED_Y ( 4 << 10)
5460#define PLANE_CTL_TILED_YF ( 5 << 10)
5461#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5462#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5463#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5464#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
Sonika Jindal1447dde2014-10-04 10:53:31 +01005465#define PLANE_CTL_ROTATE_MASK 0x3
5466#define PLANE_CTL_ROTATE_0 0x0
Sonika Jindal3b7a5112015-04-10 14:37:29 +05305467#define PLANE_CTL_ROTATE_90 0x1
Sonika Jindal1447dde2014-10-04 10:53:31 +01005468#define PLANE_CTL_ROTATE_180 0x2
Sonika Jindal3b7a5112015-04-10 14:37:29 +05305469#define PLANE_CTL_ROTATE_270 0x3
Damien Lespiau70d21f02013-07-03 21:06:04 +01005470#define _PLANE_STRIDE_1_A 0x70188
5471#define _PLANE_STRIDE_2_A 0x70288
5472#define _PLANE_STRIDE_3_A 0x70388
5473#define _PLANE_POS_1_A 0x7018c
5474#define _PLANE_POS_2_A 0x7028c
5475#define _PLANE_POS_3_A 0x7038c
5476#define _PLANE_SIZE_1_A 0x70190
5477#define _PLANE_SIZE_2_A 0x70290
5478#define _PLANE_SIZE_3_A 0x70390
5479#define _PLANE_SURF_1_A 0x7019c
5480#define _PLANE_SURF_2_A 0x7029c
5481#define _PLANE_SURF_3_A 0x7039c
5482#define _PLANE_OFFSET_1_A 0x701a4
5483#define _PLANE_OFFSET_2_A 0x702a4
5484#define _PLANE_OFFSET_3_A 0x703a4
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005485#define _PLANE_KEYVAL_1_A 0x70194
5486#define _PLANE_KEYVAL_2_A 0x70294
5487#define _PLANE_KEYMSK_1_A 0x70198
5488#define _PLANE_KEYMSK_2_A 0x70298
5489#define _PLANE_KEYMAX_1_A 0x701a0
5490#define _PLANE_KEYMAX_2_A 0x702a0
Damien Lespiau8211bd52014-11-04 17:06:44 +00005491#define _PLANE_BUF_CFG_1_A 0x7027c
5492#define _PLANE_BUF_CFG_2_A 0x7037c
Chandra Konduru2cd601c2015-04-27 15:47:37 -07005493#define _PLANE_NV12_BUF_CFG_1_A 0x70278
5494#define _PLANE_NV12_BUF_CFG_2_A 0x70378
Damien Lespiau70d21f02013-07-03 21:06:04 +01005495
5496#define _PLANE_CTL_1_B 0x71180
5497#define _PLANE_CTL_2_B 0x71280
5498#define _PLANE_CTL_3_B 0x71380
5499#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5500#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5501#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5502#define PLANE_CTL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005503 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005504
5505#define _PLANE_STRIDE_1_B 0x71188
5506#define _PLANE_STRIDE_2_B 0x71288
5507#define _PLANE_STRIDE_3_B 0x71388
5508#define _PLANE_STRIDE_1(pipe) \
5509 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5510#define _PLANE_STRIDE_2(pipe) \
5511 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5512#define _PLANE_STRIDE_3(pipe) \
5513 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5514#define PLANE_STRIDE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005515 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005516
5517#define _PLANE_POS_1_B 0x7118c
5518#define _PLANE_POS_2_B 0x7128c
5519#define _PLANE_POS_3_B 0x7138c
5520#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5521#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5522#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5523#define PLANE_POS(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005524 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005525
5526#define _PLANE_SIZE_1_B 0x71190
5527#define _PLANE_SIZE_2_B 0x71290
5528#define _PLANE_SIZE_3_B 0x71390
5529#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5530#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5531#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5532#define PLANE_SIZE(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005533 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005534
5535#define _PLANE_SURF_1_B 0x7119c
5536#define _PLANE_SURF_2_B 0x7129c
5537#define _PLANE_SURF_3_B 0x7139c
5538#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5539#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5540#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5541#define PLANE_SURF(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005542 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005543
5544#define _PLANE_OFFSET_1_B 0x711a4
5545#define _PLANE_OFFSET_2_B 0x712a4
5546#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5547#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5548#define PLANE_OFFSET(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005549 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
Damien Lespiau70d21f02013-07-03 21:06:04 +01005550
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005551#define _PLANE_KEYVAL_1_B 0x71194
5552#define _PLANE_KEYVAL_2_B 0x71294
5553#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5554#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5555#define PLANE_KEYVAL(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005556 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005557
5558#define _PLANE_KEYMSK_1_B 0x71198
5559#define _PLANE_KEYMSK_2_B 0x71298
5560#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5561#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5562#define PLANE_KEYMSK(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005563 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005564
5565#define _PLANE_KEYMAX_1_B 0x711a0
5566#define _PLANE_KEYMAX_2_B 0x712a0
5567#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5568#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5569#define PLANE_KEYMAX(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005570 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005571
Damien Lespiau8211bd52014-11-04 17:06:44 +00005572#define _PLANE_BUF_CFG_1_B 0x7127c
5573#define _PLANE_BUF_CFG_2_B 0x7137c
5574#define _PLANE_BUF_CFG_1(pipe) \
5575 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5576#define _PLANE_BUF_CFG_2(pipe) \
5577 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5578#define PLANE_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005579 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
Damien Lespiau8211bd52014-11-04 17:06:44 +00005580
Chandra Konduru2cd601c2015-04-27 15:47:37 -07005581#define _PLANE_NV12_BUF_CFG_1_B 0x71278
5582#define _PLANE_NV12_BUF_CFG_2_B 0x71378
5583#define _PLANE_NV12_BUF_CFG_1(pipe) \
5584 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5585#define _PLANE_NV12_BUF_CFG_2(pipe) \
5586 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5587#define PLANE_NV12_BUF_CFG(pipe, plane) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005588 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
Chandra Konduru2cd601c2015-04-27 15:47:37 -07005589
Damien Lespiau8211bd52014-11-04 17:06:44 +00005590/* SKL new cursor registers */
5591#define _CUR_BUF_CFG_A 0x7017c
5592#define _CUR_BUF_CFG_B 0x7117c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005593#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
Damien Lespiau8211bd52014-11-04 17:06:44 +00005594
Jesse Barnes585fb112008-07-29 11:54:06 -07005595/* VBIOS regs */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005596#define VGACNTRL _MMIO(0x71400)
Jesse Barnes585fb112008-07-29 11:54:06 -07005597# define VGA_DISP_DISABLE (1 << 31)
5598# define VGA_2X_MODE (1 << 30)
5599# define VGA_PIPE_B_SELECT (1 << 29)
5600
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005601#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02005602
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005603/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005604
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005605#define CPU_VGACNTRL _MMIO(0x41000)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005606
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005607#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03005608#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5609#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5610#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5611#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5612#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5613#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5614#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5615#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5616#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5617#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005618
5619/* refresh rate hardware control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005620#define RR_HW_CTL _MMIO(0x45300)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005621#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5622#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5623
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005624#define FDI_PLL_BIOS_0 _MMIO(0x46000)
Chris Wilson021357a2010-09-07 20:54:59 +01005625#define FDI_PLL_FB_CLOCK_MASK 0xff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005626#define FDI_PLL_BIOS_1 _MMIO(0x46004)
5627#define FDI_PLL_BIOS_2 _MMIO(0x46008)
5628#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5629#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5630#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005631
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005632#define PCH_3DCGDIS0 _MMIO(0x46020)
Eric Anholt8956c8b2010-03-18 13:21:14 -07005633# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5634# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5635
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005636#define PCH_3DCGDIS1 _MMIO(0x46024)
Eric Anholt06f37752010-12-14 10:06:46 -08005637# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5638
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005639#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005640#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5641#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5642#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5643
5644
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005645#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01005646#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005647#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01005648#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005649
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005650#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01005651#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005652#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01005653#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005654
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005655#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01005656#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005657#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01005658#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005659
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005660#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01005661#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005662#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01005663#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005664
5665/* PIPEB timing regs are same start from 0x61000 */
5666
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005667#define _PIPEB_DATA_M1 0x61030
5668#define _PIPEB_DATA_N1 0x61034
5669#define _PIPEB_DATA_M2 0x61038
5670#define _PIPEB_DATA_N2 0x6103c
5671#define _PIPEB_LINK_M1 0x61040
5672#define _PIPEB_LINK_N1 0x61044
5673#define _PIPEB_LINK_M2 0x61048
5674#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005675
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005676#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5677#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5678#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5679#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5680#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5681#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5682#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5683#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005684
5685/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005686/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5687#define _PFA_CTL_1 0x68080
5688#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08005689#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02005690#define PF_PIPE_SEL_MASK_IVB (3<<29)
5691#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08005692#define PF_FILTER_MASK (3<<23)
5693#define PF_FILTER_PROGRAMMED (0<<23)
5694#define PF_FILTER_MED_3x3 (1<<23)
5695#define PF_FILTER_EDGE_ENHANCE (2<<23)
5696#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005697#define _PFA_WIN_SZ 0x68074
5698#define _PFB_WIN_SZ 0x68874
5699#define _PFA_WIN_POS 0x68070
5700#define _PFB_WIN_POS 0x68870
5701#define _PFA_VSCALE 0x68084
5702#define _PFB_VSCALE 0x68884
5703#define _PFA_HSCALE 0x68090
5704#define _PFB_HSCALE 0x68890
5705
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005706#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5707#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5708#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5709#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5710#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005711
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005712#define _PSA_CTL 0x68180
5713#define _PSB_CTL 0x68980
5714#define PS_ENABLE (1<<31)
5715#define _PSA_WIN_SZ 0x68174
5716#define _PSB_WIN_SZ 0x68974
5717#define _PSA_WIN_POS 0x68170
5718#define _PSB_WIN_POS 0x68970
5719
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005720#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5721#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5722#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005723
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005724/*
5725 * Skylake scalers
5726 */
5727#define _PS_1A_CTRL 0x68180
5728#define _PS_2A_CTRL 0x68280
5729#define _PS_1B_CTRL 0x68980
5730#define _PS_2B_CTRL 0x68A80
5731#define _PS_1C_CTRL 0x69180
5732#define PS_SCALER_EN (1 << 31)
5733#define PS_SCALER_MODE_MASK (3 << 28)
5734#define PS_SCALER_MODE_DYN (0 << 28)
5735#define PS_SCALER_MODE_HQ (1 << 28)
5736#define PS_PLANE_SEL_MASK (7 << 25)
Ville Syrjälä68d97532015-09-18 20:03:39 +03005737#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005738#define PS_FILTER_MASK (3 << 23)
5739#define PS_FILTER_MEDIUM (0 << 23)
5740#define PS_FILTER_EDGE_ENHANCE (2 << 23)
5741#define PS_FILTER_BILINEAR (3 << 23)
5742#define PS_VERT3TAP (1 << 21)
5743#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5744#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5745#define PS_PWRUP_PROGRESS (1 << 17)
5746#define PS_V_FILTER_BYPASS (1 << 8)
5747#define PS_VADAPT_EN (1 << 7)
5748#define PS_VADAPT_MODE_MASK (3 << 5)
5749#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5750#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5751#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5752
5753#define _PS_PWR_GATE_1A 0x68160
5754#define _PS_PWR_GATE_2A 0x68260
5755#define _PS_PWR_GATE_1B 0x68960
5756#define _PS_PWR_GATE_2B 0x68A60
5757#define _PS_PWR_GATE_1C 0x69160
5758#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5759#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5760#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5761#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5762#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5763#define PS_PWR_GATE_SLPEN_8 0
5764#define PS_PWR_GATE_SLPEN_16 1
5765#define PS_PWR_GATE_SLPEN_24 2
5766#define PS_PWR_GATE_SLPEN_32 3
5767
5768#define _PS_WIN_POS_1A 0x68170
5769#define _PS_WIN_POS_2A 0x68270
5770#define _PS_WIN_POS_1B 0x68970
5771#define _PS_WIN_POS_2B 0x68A70
5772#define _PS_WIN_POS_1C 0x69170
5773
5774#define _PS_WIN_SZ_1A 0x68174
5775#define _PS_WIN_SZ_2A 0x68274
5776#define _PS_WIN_SZ_1B 0x68974
5777#define _PS_WIN_SZ_2B 0x68A74
5778#define _PS_WIN_SZ_1C 0x69174
5779
5780#define _PS_VSCALE_1A 0x68184
5781#define _PS_VSCALE_2A 0x68284
5782#define _PS_VSCALE_1B 0x68984
5783#define _PS_VSCALE_2B 0x68A84
5784#define _PS_VSCALE_1C 0x69184
5785
5786#define _PS_HSCALE_1A 0x68190
5787#define _PS_HSCALE_2A 0x68290
5788#define _PS_HSCALE_1B 0x68990
5789#define _PS_HSCALE_2B 0x68A90
5790#define _PS_HSCALE_1C 0x69190
5791
5792#define _PS_VPHASE_1A 0x68188
5793#define _PS_VPHASE_2A 0x68288
5794#define _PS_VPHASE_1B 0x68988
5795#define _PS_VPHASE_2B 0x68A88
5796#define _PS_VPHASE_1C 0x69188
5797
5798#define _PS_HPHASE_1A 0x68194
5799#define _PS_HPHASE_2A 0x68294
5800#define _PS_HPHASE_1B 0x68994
5801#define _PS_HPHASE_2B 0x68A94
5802#define _PS_HPHASE_1C 0x69194
5803
5804#define _PS_ECC_STAT_1A 0x681D0
5805#define _PS_ECC_STAT_2A 0x682D0
5806#define _PS_ECC_STAT_1B 0x689D0
5807#define _PS_ECC_STAT_2B 0x68AD0
5808#define _PS_ECC_STAT_1C 0x691D0
5809
5810#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005811#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005812 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5813 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005814#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005815 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5816 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005817#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005818 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5819 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005820#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005821 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5822 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005823#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005824 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5825 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005826#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005827 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5828 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005829#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005830 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5831 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005832#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005833 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5834 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005835#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005836 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
Ville Syrjälä9bca5d02015-11-04 23:20:16 +02005837 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
Chandra Konduru1c9a2d4a2015-04-07 15:28:35 -07005838
Zhenyu Wangb9055052009-06-05 15:38:38 +08005839/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005840#define _LGC_PALETTE_A 0x4a000
5841#define _LGC_PALETTE_B 0x4a800
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005842#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005843
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005844#define _GAMMA_MODE_A 0x4a480
5845#define _GAMMA_MODE_B 0x4ac80
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005846#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005847#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005848#define GAMMA_MODE_MODE_8BIT (0 << 0)
5849#define GAMMA_MODE_MODE_10BIT (1 << 0)
5850#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005851#define GAMMA_MODE_MODE_SPLIT (3 << 0)
5852
Damien Lespiau83372062015-10-30 17:53:32 +02005853/* DMC/CSR */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005854#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02005855#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
5856#define CSR_HTP_ADDR_SKL 0x00500034
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005857#define CSR_SSP_BASE _MMIO(0x8F074)
5858#define CSR_HTP_SKL _MMIO(0x8F004)
5859#define CSR_LAST_WRITE _MMIO(0x8F034)
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02005860#define CSR_LAST_WRITE_VALUE 0xc003b400
5861/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
5862#define CSR_MMIO_START_RANGE 0x80000
5863#define CSR_MMIO_END_RANGE 0x8FFFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005864#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
5865#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
5866#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
Damien Lespiau83372062015-10-30 17:53:32 +02005867
Zhenyu Wangb9055052009-06-05 15:38:38 +08005868/* interrupts */
5869#define DE_MASTER_IRQ_CONTROL (1 << 31)
5870#define DE_SPRITEB_FLIP_DONE (1 << 29)
5871#define DE_SPRITEA_FLIP_DONE (1 << 28)
5872#define DE_PLANEB_FLIP_DONE (1 << 27)
5873#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005874#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005875#define DE_PCU_EVENT (1 << 25)
5876#define DE_GTT_FAULT (1 << 24)
5877#define DE_POISON (1 << 23)
5878#define DE_PERFORM_COUNTER (1 << 22)
5879#define DE_PCH_EVENT (1 << 21)
5880#define DE_AUX_CHANNEL_A (1 << 20)
5881#define DE_DP_A_HOTPLUG (1 << 19)
5882#define DE_GSE (1 << 18)
5883#define DE_PIPEB_VBLANK (1 << 15)
5884#define DE_PIPEB_EVEN_FIELD (1 << 14)
5885#define DE_PIPEB_ODD_FIELD (1 << 13)
5886#define DE_PIPEB_LINE_COMPARE (1 << 12)
5887#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005888#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005889#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5890#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005891#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005892#define DE_PIPEA_EVEN_FIELD (1 << 6)
5893#define DE_PIPEA_ODD_FIELD (1 << 5)
5894#define DE_PIPEA_LINE_COMPARE (1 << 4)
5895#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005896#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005897#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005898#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005899#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005900
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005901/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03005902#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005903#define DE_GSE_IVB (1<<29)
5904#define DE_PCH_EVENT_IVB (1<<28)
5905#define DE_DP_A_HOTPLUG_IVB (1<<27)
5906#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01005907#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5908#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5909#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005910#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005911#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005912#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01005913#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5914#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005915#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005916#define DE_PIPEA_VBLANK_IVB (1<<0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03005917#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
Paulo Zanonib5184212013-07-12 20:00:08 -03005918
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005919#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07005920#define MASTER_INTERRUPT_ENABLE (1<<31)
5921
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005922#define DEISR _MMIO(0x44000)
5923#define DEIMR _MMIO(0x44004)
5924#define DEIIR _MMIO(0x44008)
5925#define DEIER _MMIO(0x4400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005926
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005927#define GTISR _MMIO(0x44010)
5928#define GTIMR _MMIO(0x44014)
5929#define GTIIR _MMIO(0x44018)
5930#define GTIER _MMIO(0x4401c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005931
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005932#define GEN8_MASTER_IRQ _MMIO(0x44200)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005933#define GEN8_MASTER_IRQ_CONTROL (1<<31)
5934#define GEN8_PCU_IRQ (1<<30)
5935#define GEN8_DE_PCH_IRQ (1<<23)
5936#define GEN8_DE_MISC_IRQ (1<<22)
5937#define GEN8_DE_PORT_IRQ (1<<20)
5938#define GEN8_DE_PIPE_C_IRQ (1<<18)
5939#define GEN8_DE_PIPE_B_IRQ (1<<17)
5940#define GEN8_DE_PIPE_A_IRQ (1<<16)
Ville Syrjälä68d97532015-09-18 20:03:39 +03005941#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
Ben Widawskyabd58f02013-11-02 21:07:09 -07005942#define GEN8_GT_VECS_IRQ (1<<6)
Ben Widawsky09610212014-05-15 20:58:08 +03005943#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005944#define GEN8_GT_VCS2_IRQ (1<<3)
5945#define GEN8_GT_VCS1_IRQ (1<<2)
5946#define GEN8_GT_BCS_IRQ (1<<1)
5947#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005948
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005949#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5950#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5951#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5952#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
Ben Widawskyabd58f02013-11-02 21:07:09 -07005953
Ben Widawskyabd58f02013-11-02 21:07:09 -07005954#define GEN8_RCS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01005955#define GEN8_BCS_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07005956#define GEN8_VCS1_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01005957#define GEN8_VCS2_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07005958#define GEN8_VECS_IRQ_SHIFT 0
Dave Gordon4df001d2015-08-12 15:43:42 +01005959#define GEN8_WD_IRQ_SHIFT 16
Ben Widawskyabd58f02013-11-02 21:07:09 -07005960
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005961#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5962#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5963#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5964#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01005965#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005966#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5967#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5968#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5969#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5970#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5971#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01005972#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005973#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5974#define GEN8_PIPE_VSYNC (1 << 1)
5975#define GEN8_PIPE_VBLANK (1 << 0)
Damien Lespiau770de83d2014-03-20 20:45:01 +00005976#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
Damien Lespiaub21249c2015-03-17 11:39:33 +02005977#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
Damien Lespiau770de83d2014-03-20 20:45:01 +00005978#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5979#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5980#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
Damien Lespiaub21249c2015-03-17 11:39:33 +02005981#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
Damien Lespiau770de83d2014-03-20 20:45:01 +00005982#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5983#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5984#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
Ville Syrjälä68d97532015-09-18 20:03:39 +03005985#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
Daniel Vetter30100f22013-11-07 14:49:24 +01005986#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5987 (GEN8_PIPE_CURSOR_FAULT | \
5988 GEN8_PIPE_SPRITE_FAULT | \
5989 GEN8_PIPE_PRIMARY_FAULT)
Damien Lespiau770de83d2014-03-20 20:45:01 +00005990#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5991 (GEN9_PIPE_CURSOR_FAULT | \
Damien Lespiaub21249c2015-03-17 11:39:33 +02005992 GEN9_PIPE_PLANE4_FAULT | \
Damien Lespiau770de83d2014-03-20 20:45:01 +00005993 GEN9_PIPE_PLANE3_FAULT | \
5994 GEN9_PIPE_PLANE2_FAULT | \
5995 GEN9_PIPE_PLANE1_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005996
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005997#define GEN8_DE_PORT_ISR _MMIO(0x44440)
5998#define GEN8_DE_PORT_IMR _MMIO(0x44444)
5999#define GEN8_DE_PORT_IIR _MMIO(0x44448)
6000#define GEN8_DE_PORT_IER _MMIO(0x4444c)
Jesse Barnes88e04702014-11-13 17:51:48 +00006001#define GEN9_AUX_CHANNEL_D (1 << 27)
6002#define GEN9_AUX_CHANNEL_C (1 << 26)
6003#define GEN9_AUX_CHANNEL_B (1 << 25)
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02006004#define BXT_DE_PORT_HP_DDIC (1 << 5)
6005#define BXT_DE_PORT_HP_DDIB (1 << 4)
6006#define BXT_DE_PORT_HP_DDIA (1 << 3)
6007#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
6008 BXT_DE_PORT_HP_DDIB | \
6009 BXT_DE_PORT_HP_DDIC)
6010#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
Shashank Sharma9e637432014-08-22 17:40:43 +05306011#define BXT_DE_PORT_GMBUS (1 << 1)
Daniel Vetter6d766f02013-11-07 14:49:55 +01006012#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006013
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006014#define GEN8_DE_MISC_ISR _MMIO(0x44460)
6015#define GEN8_DE_MISC_IMR _MMIO(0x44464)
6016#define GEN8_DE_MISC_IIR _MMIO(0x44468)
6017#define GEN8_DE_MISC_IER _MMIO(0x4446c)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006018#define GEN8_DE_MISC_GSE (1 << 27)
6019
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006020#define GEN8_PCU_ISR _MMIO(0x444e0)
6021#define GEN8_PCU_IMR _MMIO(0x444e4)
6022#define GEN8_PCU_IIR _MMIO(0x444e8)
6023#define GEN8_PCU_IER _MMIO(0x444ec)
Ben Widawskyabd58f02013-11-02 21:07:09 -07006024
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006025#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
Eric Anholt67e92af2010-11-06 14:53:33 -07006026/* Required on all Ironlake and Sandybridge according to the B-Spec. */
6027#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006028#define ILK_DPARB_GATE (1<<22)
6029#define ILK_VSDPFD_FULL (1<<21)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006030#define FUSE_STRAP _MMIO(0x42014)
Damien Lespiaue3589902014-02-07 19:12:50 +00006031#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
6032#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
6033#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
Gabriel Feceoru8c448ca2016-01-22 13:28:45 +02006034#define IVB_PIPE_C_DISABLE (1 << 28)
Damien Lespiaue3589902014-02-07 19:12:50 +00006035#define ILK_HDCP_DISABLE (1 << 25)
6036#define ILK_eDP_A_DISABLE (1 << 24)
6037#define HSW_CDCLK_LIMIT (1 << 24)
6038#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08006039
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006040#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
Damien Lespiau231e54f2012-10-19 17:55:41 +01006041#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
6042#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
6043#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
6044#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
6045#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006046
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006047#define IVB_CHICKEN3 _MMIO(0x4200c)
Eric Anholt116ac8d2011-12-21 10:31:09 -08006048# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
6049# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
6050
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006051#define CHICKEN_PAR1_1 _MMIO(0x42080)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006052#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03006053#define FORCE_ARB_IDLE_PLANES (1 << 14)
Daniel Vetterdc00b6a2016-05-19 09:14:20 +02006054#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
Paulo Zanoni90a88642013-05-03 17:23:45 -03006055
Mika Kuoppala17e0adf2016-06-07 17:19:02 +03006056#define CHICKEN_PAR2_1 _MMIO(0x42090)
6057#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
6058
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006059#define _CHICKEN_PIPESL_1_A 0x420b0
6060#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02006061#define HSW_FBCQ_DIS (1 << 22)
6062#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006063#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07006064
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006065#define DISP_ARB_CTL _MMIO(0x45000)
Mika Kuoppala303d4ea2016-06-07 17:19:17 +03006066#define DISP_FBC_MEMORY_WAKE (1<<31)
Zhenyu Wang553bd142009-09-02 10:57:52 +08006067#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006068#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006069#define DISP_ARB_CTL2 _MMIO(0x45004)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02006070#define DISP_DATA_PARTITION_5_6 (1<<6)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006071#define DBUF_CTL _MMIO(0x45008)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306072#define DBUF_POWER_REQUEST (1<<31)
6073#define DBUF_POWER_STATE (1<<30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006074#define GEN7_MSG_CTL _MMIO(0x45010)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07006075#define WAIT_FOR_PCH_RESET_ACK (1<<1)
6076#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006077#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01006078#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08006079
Mika Kuoppala590e8ff2016-06-07 17:19:13 +03006080#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6081#define MASK_WAKEMEM (1<<13)
6082
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006083#define SKL_DFSM _MMIO(0x51000)
Damien Lespiaua9419e82015-06-04 18:21:30 +01006084#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
6085#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
6086#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
6087#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
6088#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
Patrik Jakobssonbf4f2fb2016-01-20 15:31:20 +01006089#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
6090#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
6091#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
Damien Lespiaua9419e82015-06-04 18:21:30 +01006092
Arun Siluverya78536e2016-01-21 21:43:53 +00006093#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
6094#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
6095
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006096#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
Damien Lespiau2caa3b22015-02-09 19:33:20 +00006097#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
6098
Arun Siluvery2c8580e2016-01-21 21:43:50 +00006099#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
arun.siluvery@linux.intel.com6bb628552016-06-06 09:52:49 +01006100#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
Arun Siluverye0f3fa02016-01-21 21:43:48 +00006101#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
6102
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08006103/* GEN7 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006104#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
Kenneth Graunked71de142012-02-08 12:53:52 -08006105# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Damien Lespiau183c6da2015-02-09 19:33:11 +00006106# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006107#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
Mika Kuoppalaad2bdb42016-06-07 17:19:07 +03006108# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
Ben Widawskya75f3622013-11-02 21:07:59 -07006109# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08006110
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006111#define HIZ_CHICKEN _MMIO(0x7018)
Damien Lespiaud0bbbc4f2015-02-09 19:33:16 +00006112# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
6113# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
Kenneth Graunked60de812015-01-10 18:02:22 -08006114
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006115#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
Damien Lespiau183c6da2015-02-09 19:33:11 +00006116#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
6117
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006118#define GEN7_L3SQCREG1 _MMIO(0xB010)
Ville Syrjälä031994e2014-01-22 21:32:46 +02006119#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
6120
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006121#define GEN8_L3SQCREG1 _MMIO(0xB100)
Imre Deak450174f2016-05-03 15:54:21 +03006122/*
6123 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
6124 * Using the formula in BSpec leads to a hang, while the formula here works
6125 * fine and matches the formulas for all other platforms. A BSpec change
6126 * request has been filed to clarify this.
6127 */
Imre Deak36579cb2016-05-03 15:54:20 +03006128#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
6129#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
Rodrigo Vivi51ce4db2015-03-31 16:03:21 -07006130
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006131#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
Chris Wilson1af84522014-02-14 22:34:43 +00006132#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07006133#define GEN7_L3AGDIS (1<<19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006134#define GEN7_L3CNTLREG2 _MMIO(0xB020)
6135#define GEN7_L3CNTLREG3 _MMIO(0xB024)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08006136
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006137#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08006138#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
6139
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006140#define GEN7_L3SQCREG4 _MMIO(0xb034)
Jesse Barnes61939d92012-10-02 17:43:38 -05006141#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
6142
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006143#define GEN8_L3SQCREG4 _MMIO(0xb118)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00006144#define GEN8_LQSC_RO_PERF_DIS (1<<27)
Arun Siluveryc82435b2015-06-19 18:37:13 +01006145#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00006146
Ben Widawsky63801f22013-12-12 17:26:03 -08006147/* GEN8 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006148#define HDC_CHICKEN0 _MMIO(0x7300)
Imre Deak2a0ee942015-05-19 17:05:41 +03006149#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
Rodrigo Vivida096542014-09-19 20:16:27 -04006150#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
Damien Lespiau35cb6f32015-02-10 10:31:00 +00006151#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
6152#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
6153#define HDC_FORCE_NON_COHERENT (1<<4)
Damien Lespiau65ca7512015-02-09 19:33:22 +00006154#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
Ben Widawsky63801f22013-12-12 17:26:03 -08006155
Arun Siluvery3669ab62016-01-21 21:43:49 +00006156#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
6157
Ben Widawsky38a39a72015-03-11 10:54:53 +02006158/* GEN9 chicken */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006159#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
Ben Widawsky38a39a72015-03-11 10:54:53 +02006160#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
6161
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08006162/* WaCatErrorRejectionIssue */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006163#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08006164#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
6165
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006166#define HSW_SCRATCH1 _MMIO(0xb038)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07006167#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
6168
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006169#define BDW_SCRATCH1 _MMIO(0xb11c)
Damien Lespiau77719d22015-02-09 19:33:13 +00006170#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
6171
Zhenyu Wangb9055052009-06-05 15:38:38 +08006172/* PCH */
6173
Adam Jackson23e81d62012-06-06 15:45:44 -04006174/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08006175#define SDE_AUDIO_POWER_D (1 << 27)
6176#define SDE_AUDIO_POWER_C (1 << 26)
6177#define SDE_AUDIO_POWER_B (1 << 25)
6178#define SDE_AUDIO_POWER_SHIFT (25)
6179#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
6180#define SDE_GMBUS (1 << 24)
6181#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
6182#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
6183#define SDE_AUDIO_HDCP_MASK (3 << 22)
6184#define SDE_AUDIO_TRANSB (1 << 21)
6185#define SDE_AUDIO_TRANSA (1 << 20)
6186#define SDE_AUDIO_TRANS_MASK (3 << 20)
6187#define SDE_POISON (1 << 19)
6188/* 18 reserved */
6189#define SDE_FDI_RXB (1 << 17)
6190#define SDE_FDI_RXA (1 << 16)
6191#define SDE_FDI_MASK (3 << 16)
6192#define SDE_AUXD (1 << 15)
6193#define SDE_AUXC (1 << 14)
6194#define SDE_AUXB (1 << 13)
6195#define SDE_AUX_MASK (7 << 13)
6196/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006197#define SDE_CRT_HOTPLUG (1 << 11)
6198#define SDE_PORTD_HOTPLUG (1 << 10)
6199#define SDE_PORTC_HOTPLUG (1 << 9)
6200#define SDE_PORTB_HOTPLUG (1 << 8)
6201#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05006202#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
6203 SDE_SDVOB_HOTPLUG | \
6204 SDE_PORTB_HOTPLUG | \
6205 SDE_PORTC_HOTPLUG | \
6206 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08006207#define SDE_TRANSB_CRC_DONE (1 << 5)
6208#define SDE_TRANSB_CRC_ERR (1 << 4)
6209#define SDE_TRANSB_FIFO_UNDER (1 << 3)
6210#define SDE_TRANSA_CRC_DONE (1 << 2)
6211#define SDE_TRANSA_CRC_ERR (1 << 1)
6212#define SDE_TRANSA_FIFO_UNDER (1 << 0)
6213#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04006214
6215/* south display engine interrupt: CPT/PPT */
6216#define SDE_AUDIO_POWER_D_CPT (1 << 31)
6217#define SDE_AUDIO_POWER_C_CPT (1 << 30)
6218#define SDE_AUDIO_POWER_B_CPT (1 << 29)
6219#define SDE_AUDIO_POWER_SHIFT_CPT 29
6220#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
6221#define SDE_AUXD_CPT (1 << 27)
6222#define SDE_AUXC_CPT (1 << 26)
6223#define SDE_AUXB_CPT (1 << 25)
6224#define SDE_AUX_MASK_CPT (7 << 25)
Xiong Zhang26951ca2015-08-17 15:55:50 +08006225#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
Ville Syrjälä74c0b392015-08-27 23:56:07 +03006226#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006227#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
6228#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
6229#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04006230#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01006231#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01006232#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01006233 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01006234 SDE_PORTD_HOTPLUG_CPT | \
6235 SDE_PORTC_HOTPLUG_CPT | \
6236 SDE_PORTB_HOTPLUG_CPT)
Xiong Zhang26951ca2015-08-17 15:55:50 +08006237#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
6238 SDE_PORTD_HOTPLUG_CPT | \
6239 SDE_PORTC_HOTPLUG_CPT | \
Ville Syrjälä74c0b392015-08-27 23:56:07 +03006240 SDE_PORTB_HOTPLUG_CPT | \
6241 SDE_PORTA_HOTPLUG_SPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04006242#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03006243#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04006244#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
6245#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
6246#define SDE_FDI_RXC_CPT (1 << 8)
6247#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
6248#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
6249#define SDE_FDI_RXB_CPT (1 << 4)
6250#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
6251#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
6252#define SDE_FDI_RXA_CPT (1 << 0)
6253#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
6254 SDE_AUDIO_CP_REQ_B_CPT | \
6255 SDE_AUDIO_CP_REQ_A_CPT)
6256#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
6257 SDE_AUDIO_CP_CHG_B_CPT | \
6258 SDE_AUDIO_CP_CHG_A_CPT)
6259#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
6260 SDE_FDI_RXB_CPT | \
6261 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006262
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006263#define SDEISR _MMIO(0xc4000)
6264#define SDEIMR _MMIO(0xc4004)
6265#define SDEIIR _MMIO(0xc4008)
6266#define SDEIER _MMIO(0xc400c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006267
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006268#define SERR_INT _MMIO(0xc4040)
Paulo Zanonide032bf2013-04-12 17:57:58 -03006269#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03006270#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
6271#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
6272#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006273#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03006274
Zhenyu Wangb9055052009-06-05 15:38:38 +08006275/* digital port hotplug */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006276#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
Ville Syrjälä195baa02015-08-27 23:56:00 +03006277#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05306278#define BXT_DDIA_HPD_INVERT (1 << 27)
Ville Syrjälä195baa02015-08-27 23:56:00 +03006279#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
6280#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
6281#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
6282#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006283#define PORTD_HOTPLUG_ENABLE (1 << 20)
6284#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
6285#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
6286#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
6287#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
6288#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
6289#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
Damien Lespiaub6965192012-12-13 16:08:59 +00006290#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
6291#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
6292#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006293#define PORTC_HOTPLUG_ENABLE (1 << 12)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05306294#define BXT_DDIC_HPD_INVERT (1 << 11)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006295#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
6296#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
6297#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
6298#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
6299#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
6300#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
Damien Lespiaub6965192012-12-13 16:08:59 +00006301#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6302#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6303#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006304#define PORTB_HOTPLUG_ENABLE (1 << 4)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05306305#define BXT_DDIB_HPD_INVERT (1 << 3)
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006306#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
6307#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
6308#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
6309#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
6310#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
6311#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
Damien Lespiaub6965192012-12-13 16:08:59 +00006312#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6313#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6314#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05306315#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
6316 BXT_DDIB_HPD_INVERT | \
6317 BXT_DDIC_HPD_INVERT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006318
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006319#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
Ville Syrjälä40bfd7a2015-08-27 23:55:56 +03006320#define PORTE_HOTPLUG_ENABLE (1 << 4)
6321#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
Xiong Zhang26951ca2015-08-17 15:55:50 +08006322#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
6323#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
6324#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
6325
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006326#define PCH_GPIOA _MMIO(0xc5010)
6327#define PCH_GPIOB _MMIO(0xc5014)
6328#define PCH_GPIOC _MMIO(0xc5018)
6329#define PCH_GPIOD _MMIO(0xc501c)
6330#define PCH_GPIOE _MMIO(0xc5020)
6331#define PCH_GPIOF _MMIO(0xc5024)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006332
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006333#define PCH_GMBUS0 _MMIO(0xc5100)
6334#define PCH_GMBUS1 _MMIO(0xc5104)
6335#define PCH_GMBUS2 _MMIO(0xc5108)
6336#define PCH_GMBUS3 _MMIO(0xc510c)
6337#define PCH_GMBUS4 _MMIO(0xc5110)
6338#define PCH_GMBUS5 _MMIO(0xc5120)
Eric Anholtf0217c42009-12-01 11:56:30 -08006339
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006340#define _PCH_DPLL_A 0xc6014
6341#define _PCH_DPLL_B 0xc6018
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006342#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006343
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006344#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00006345#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006346#define _PCH_FPA1 0xc6044
6347#define _PCH_FPB0 0xc6048
6348#define _PCH_FPB1 0xc604c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006349#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6350#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006351
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006352#define PCH_DPLL_TEST _MMIO(0xc606c)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006353
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006354#define PCH_DREF_CONTROL _MMIO(0xC6200)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006355#define DREF_CONTROL_MASK 0x7fc3
6356#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6357#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6358#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6359#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6360#define DREF_SSC_SOURCE_DISABLE (0<<11)
6361#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08006362#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006363#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6364#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6365#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08006366#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006367#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6368#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08006369#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006370#define DREF_SSC4_DOWNSPREAD (0<<6)
6371#define DREF_SSC4_CENTERSPREAD (1<<6)
6372#define DREF_SSC1_DISABLE (0<<1)
6373#define DREF_SSC1_ENABLE (1<<1)
6374#define DREF_SSC4_DISABLE (0)
6375#define DREF_SSC4_ENABLE (1)
6376
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006377#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006378#define FDL_TP1_TIMER_SHIFT 12
6379#define FDL_TP1_TIMER_MASK (3<<12)
6380#define FDL_TP2_TIMER_SHIFT 10
6381#define FDL_TP2_TIMER_MASK (3<<10)
6382#define RAWCLK_FREQ_MASK 0x3ff
6383
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006384#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006385
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006386#define PCH_SSC4_PARMS _MMIO(0xc6210)
6387#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006388
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006389#define PCH_DPLL_SEL _MMIO(0xc7000)
Ville Syrjälä68d97532015-09-18 20:03:39 +03006390#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
Daniel Vetter11887392013-06-05 13:34:09 +02006391#define TRANS_DPLLA_SEL(pipe) 0
Ville Syrjälä68d97532015-09-18 20:03:39 +03006392#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006393
Zhenyu Wangb9055052009-06-05 15:38:38 +08006394/* transcoder */
6395
Daniel Vetter275f01b22013-05-03 11:49:47 +02006396#define _PCH_TRANS_HTOTAL_A 0xe0000
6397#define TRANS_HTOTAL_SHIFT 16
6398#define TRANS_HACTIVE_SHIFT 0
6399#define _PCH_TRANS_HBLANK_A 0xe0004
6400#define TRANS_HBLANK_END_SHIFT 16
6401#define TRANS_HBLANK_START_SHIFT 0
6402#define _PCH_TRANS_HSYNC_A 0xe0008
6403#define TRANS_HSYNC_END_SHIFT 16
6404#define TRANS_HSYNC_START_SHIFT 0
6405#define _PCH_TRANS_VTOTAL_A 0xe000c
6406#define TRANS_VTOTAL_SHIFT 16
6407#define TRANS_VACTIVE_SHIFT 0
6408#define _PCH_TRANS_VBLANK_A 0xe0010
6409#define TRANS_VBLANK_END_SHIFT 16
6410#define TRANS_VBLANK_START_SHIFT 0
6411#define _PCH_TRANS_VSYNC_A 0xe0014
6412#define TRANS_VSYNC_END_SHIFT 16
6413#define TRANS_VSYNC_START_SHIFT 0
6414#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08006415
Daniel Vettere3b95f12013-05-03 11:49:49 +02006416#define _PCH_TRANSA_DATA_M1 0xe0030
6417#define _PCH_TRANSA_DATA_N1 0xe0034
6418#define _PCH_TRANSA_DATA_M2 0xe0038
6419#define _PCH_TRANSA_DATA_N2 0xe003c
6420#define _PCH_TRANSA_LINK_M1 0xe0040
6421#define _PCH_TRANSA_LINK_N1 0xe0044
6422#define _PCH_TRANSA_LINK_M2 0xe0048
6423#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08006424
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006425/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07006426#define _VIDEO_DIP_CTL_A 0xe0200
6427#define _VIDEO_DIP_DATA_A 0xe0208
6428#define _VIDEO_DIP_GCP_A 0xe0210
Ville Syrjälä6d674152015-05-05 17:06:20 +03006429#define GCP_COLOR_INDICATION (1 << 2)
6430#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6431#define GCP_AV_MUTE (1 << 0)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07006432
6433#define _VIDEO_DIP_CTL_B 0xe1200
6434#define _VIDEO_DIP_DATA_B 0xe1208
6435#define _VIDEO_DIP_GCP_B 0xe1210
6436
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006437#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6438#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6439#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07006440
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006441/* Per-transcoder DIP controls (VLV) */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006442#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6443#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6444#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006445
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006446#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6447#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6448#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006449
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006450#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6451#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6452#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006453
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006454#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006455 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006456 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006457#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006458 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006459 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006460#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006461 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006462 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006463
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006464/* Haswell DIP controls */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006465
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006466#define _HSW_VIDEO_DIP_CTL_A 0x60200
6467#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6468#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6469#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6470#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6471#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6472#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6473#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6474#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6475#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6476#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6477#define _HSW_VIDEO_DIP_GCP_A 0x60210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006478
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006479#define _HSW_VIDEO_DIP_CTL_B 0x61200
6480#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6481#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6482#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6483#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6484#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6485#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6486#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6487#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6488#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6489#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6490#define _HSW_VIDEO_DIP_GCP_B 0x61210
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006491
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006492#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6493#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6494#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6495#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6496#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6497#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006498
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006499#define _HSW_STEREO_3D_CTL_A 0x70020
6500#define S3D_ENABLE (1<<31)
6501#define _HSW_STEREO_3D_CTL_B 0x71020
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03006502
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006503#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03006504
Daniel Vetter275f01b22013-05-03 11:49:47 +02006505#define _PCH_TRANS_HTOTAL_B 0xe1000
6506#define _PCH_TRANS_HBLANK_B 0xe1004
6507#define _PCH_TRANS_HSYNC_B 0xe1008
6508#define _PCH_TRANS_VTOTAL_B 0xe100c
6509#define _PCH_TRANS_VBLANK_B 0xe1010
6510#define _PCH_TRANS_VSYNC_B 0xe1014
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006511#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08006512
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006513#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6514#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6515#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6516#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6517#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6518#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6519#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01006520
Daniel Vettere3b95f12013-05-03 11:49:49 +02006521#define _PCH_TRANSB_DATA_M1 0xe1030
6522#define _PCH_TRANSB_DATA_N1 0xe1034
6523#define _PCH_TRANSB_DATA_M2 0xe1038
6524#define _PCH_TRANSB_DATA_N2 0xe103c
6525#define _PCH_TRANSB_LINK_M1 0xe1040
6526#define _PCH_TRANSB_LINK_N1 0xe1044
6527#define _PCH_TRANSB_LINK_M2 0xe1048
6528#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08006529
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006530#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6531#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6532#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6533#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6534#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6535#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6536#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6537#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006538
Daniel Vetterab9412b2013-05-03 11:49:46 +02006539#define _PCH_TRANSACONF 0xf0008
6540#define _PCH_TRANSBCONF 0xf1008
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006541#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6542#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006543#define TRANS_DISABLE (0<<31)
6544#define TRANS_ENABLE (1<<31)
6545#define TRANS_STATE_MASK (1<<30)
6546#define TRANS_STATE_DISABLE (0<<30)
6547#define TRANS_STATE_ENABLE (1<<30)
6548#define TRANS_FSYNC_DELAY_HB1 (0<<27)
6549#define TRANS_FSYNC_DELAY_HB2 (1<<27)
6550#define TRANS_FSYNC_DELAY_HB3 (2<<27)
6551#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02006552#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006553#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02006554#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02006555#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006556#define TRANS_8BPC (0<<5)
6557#define TRANS_10BPC (1<<5)
6558#define TRANS_6BPC (2<<5)
6559#define TRANS_12BPC (3<<5)
6560
Daniel Vetterce401412012-10-31 22:52:30 +01006561#define _TRANSA_CHICKEN1 0xf0060
6562#define _TRANSB_CHICKEN1 0xf1060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006563#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
Ville Syrjäläd1b15892015-05-05 17:06:19 +03006564#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
Daniel Vetterce401412012-10-31 22:52:30 +01006565#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07006566#define _TRANSA_CHICKEN2 0xf0064
6567#define _TRANSB_CHICKEN2 0xf1064
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006568#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006569#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6570#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6571#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6572#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6573#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07006574
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006575#define SOUTH_CHICKEN1 _MMIO(0xc2000)
Jesse Barnes291427f2011-07-29 12:42:37 -07006576#define FDIA_PHASE_SYNC_SHIFT_OVR 19
6577#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02006578#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6579#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6580#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03006581#define SPT_PWM_GRANULARITY (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006582#define SOUTH_CHICKEN2 _MMIO(0xc2004)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006583#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6584#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
Jani Nikulaaa17cdb2015-09-04 16:55:14 +03006585#define LPT_PWM_GRANULARITY (1<<5)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006586#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07006587
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006588#define _FDI_RXA_CHICKEN 0xc200c
6589#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08006590#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6591#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006592#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006593
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006594#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
Jesse Barnescd664072013-10-02 10:34:19 -07006595#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07006596#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07006597#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006598#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07006599
Zhenyu Wangb9055052009-06-05 15:38:38 +08006600/* CPU: FDI_TX */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006601#define _FDI_TXA_CTL 0x60100
6602#define _FDI_TXB_CTL 0x61100
6603#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006604#define FDI_TX_DISABLE (0<<31)
6605#define FDI_TX_ENABLE (1<<31)
6606#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6607#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6608#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6609#define FDI_LINK_TRAIN_NONE (3<<28)
6610#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6611#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6612#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6613#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6614#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6615#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6616#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6617#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006618/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6619 SNB has different settings. */
6620/* SNB A-stepping */
6621#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6622#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6623#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6624#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6625/* SNB B-stepping */
6626#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6627#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6628#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6629#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6630#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006631#define FDI_DP_PORT_WIDTH_SHIFT 19
6632#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6633#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006634#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006635/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006636#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07006637
6638/* Ivybridge has different bits for lolz */
6639#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6640#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6641#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6642#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6643
Zhenyu Wangb9055052009-06-05 15:38:38 +08006644/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07006645#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07006646#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006647#define FDI_SCRAMBLING_ENABLE (0<<7)
6648#define FDI_SCRAMBLING_DISABLE (1<<7)
6649
6650/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006651#define _FDI_RXA_CTL 0xf000c
6652#define _FDI_RXB_CTL 0xf100c
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006653#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006654#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006655/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07006656#define FDI_FS_ERRC_ENABLE (1<<27)
6657#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02006658#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006659#define FDI_8BPC (0<<16)
6660#define FDI_10BPC (1<<16)
6661#define FDI_6BPC (2<<16)
6662#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00006663#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006664#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6665#define FDI_RX_PLL_ENABLE (1<<13)
6666#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6667#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6668#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6669#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6670#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01006671#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006672/* CPT */
6673#define FDI_AUTO_TRAINING (1<<10)
6674#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6675#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6676#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6677#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6678#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006679
Paulo Zanoni04945642012-11-01 21:00:59 -02006680#define _FDI_RXA_MISC 0xf0010
6681#define _FDI_RXB_MISC 0xf1010
6682#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6683#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6684#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6685#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6686#define FDI_RX_TP1_TO_TP2_48 (2<<20)
6687#define FDI_RX_TP1_TO_TP2_64 (3<<20)
6688#define FDI_RX_FDI_DELAY_90 (0x90<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006689#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
Paulo Zanoni04945642012-11-01 21:00:59 -02006690
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006691#define _FDI_RXA_TUSIZE1 0xf0030
6692#define _FDI_RXA_TUSIZE2 0xf0038
6693#define _FDI_RXB_TUSIZE1 0xf1030
6694#define _FDI_RXB_TUSIZE2 0xf1038
6695#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6696#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006697
6698/* FDI_RX interrupt register format */
6699#define FDI_RX_INTER_LANE_ALIGN (1<<10)
6700#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6701#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6702#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6703#define FDI_RX_FS_CODE_ERR (1<<6)
6704#define FDI_RX_FE_CODE_ERR (1<<5)
6705#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6706#define FDI_RX_HDCP_LINK_FAIL (1<<3)
6707#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6708#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6709#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6710
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006711#define _FDI_RXA_IIR 0xf0014
6712#define _FDI_RXA_IMR 0xf0018
6713#define _FDI_RXB_IIR 0xf1014
6714#define _FDI_RXB_IMR 0xf1018
6715#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6716#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006717
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006718#define FDI_PLL_CTL_1 _MMIO(0xfe000)
6719#define FDI_PLL_CTL_2 _MMIO(0xfe004)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006720
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006721#define PCH_LVDS _MMIO(0xe1180)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006722#define LVDS_DETECTED (1 << 1)
6723
Shobhit Kumar98364372012-06-15 11:55:14 -07006724/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006725#define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6726#define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6727#define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Ville Syrjäläad933b52014-08-18 22:15:56 +03006728#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006729#define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6730#define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07006731
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006732#define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6733#define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6734#define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6735#define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6736#define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07006737
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006738#define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
6739#define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
6740#define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
6741#define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
6742#define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
Jesse Barnes453c5422013-03-28 09:55:41 -07006743
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006744#define _PCH_PP_STATUS 0xc7200
6745#define _PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07006746#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07006747#define PANEL_UNLOCK_MASK (0xffff << 16)
Vandana Kannanb0a08be2015-06-18 11:00:55 +05306748#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
6749#define BXT_POWER_CYCLE_DELAY_SHIFT 4
Zhenyu Wangb9055052009-06-05 15:38:38 +08006750#define EDP_FORCE_VDD (1 << 3)
6751#define EDP_BLC_ENABLE (1 << 2)
6752#define PANEL_POWER_RESET (1 << 1)
6753#define PANEL_POWER_OFF (0 << 0)
6754#define PANEL_POWER_ON (1 << 0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006755#define _PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07006756#define PANEL_PORT_SELECT_MASK (3 << 30)
6757#define PANEL_PORT_SELECT_LVDS (0 << 30)
6758#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07006759#define PANEL_PORT_SELECT_DPC (2 << 30)
6760#define PANEL_PORT_SELECT_DPD (3 << 30)
6761#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
6762#define PANEL_POWER_UP_DELAY_SHIFT 16
6763#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6764#define PANEL_LIGHT_ON_DELAY_SHIFT 0
6765
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006766#define _PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07006767#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6768#define PANEL_POWER_DOWN_DELAY_SHIFT 16
6769#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6770#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6771
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006772#define _PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07006773#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6774#define PP_REFERENCE_DIVIDER_SHIFT 8
6775#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6776#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006777
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006778#define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS)
6779#define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL)
6780#define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS)
6781#define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS)
6782#define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR)
6783
Vandana Kannanb0a08be2015-06-18 11:00:55 +05306784/* BXT PPS changes - 2nd set of PPS registers */
6785#define _BXT_PP_STATUS2 0xc7300
6786#define _BXT_PP_CONTROL2 0xc7304
6787#define _BXT_PP_ON_DELAYS2 0xc7308
6788#define _BXT_PP_OFF_DELAYS2 0xc730c
6789
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006790#define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
6791#define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6792#define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6793#define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
Vandana Kannanb0a08be2015-06-18 11:00:55 +05306794
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006795#define _PCH_DP_B 0xe4100
6796#define PCH_DP_B _MMIO(_PCH_DP_B)
Ville Syrjälä750a9512015-11-11 20:34:12 +02006797#define _PCH_DPB_AUX_CH_CTL 0xe4110
6798#define _PCH_DPB_AUX_CH_DATA1 0xe4114
6799#define _PCH_DPB_AUX_CH_DATA2 0xe4118
6800#define _PCH_DPB_AUX_CH_DATA3 0xe411c
6801#define _PCH_DPB_AUX_CH_DATA4 0xe4120
6802#define _PCH_DPB_AUX_CH_DATA5 0xe4124
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006803
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006804#define _PCH_DP_C 0xe4200
6805#define PCH_DP_C _MMIO(_PCH_DP_C)
Ville Syrjälä750a9512015-11-11 20:34:12 +02006806#define _PCH_DPC_AUX_CH_CTL 0xe4210
6807#define _PCH_DPC_AUX_CH_DATA1 0xe4214
6808#define _PCH_DPC_AUX_CH_DATA2 0xe4218
6809#define _PCH_DPC_AUX_CH_DATA3 0xe421c
6810#define _PCH_DPC_AUX_CH_DATA4 0xe4220
6811#define _PCH_DPC_AUX_CH_DATA5 0xe4224
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006812
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006813#define _PCH_DP_D 0xe4300
6814#define PCH_DP_D _MMIO(_PCH_DP_D)
Ville Syrjälä750a9512015-11-11 20:34:12 +02006815#define _PCH_DPD_AUX_CH_CTL 0xe4310
6816#define _PCH_DPD_AUX_CH_DATA1 0xe4314
6817#define _PCH_DPD_AUX_CH_DATA2 0xe4318
6818#define _PCH_DPD_AUX_CH_DATA3 0xe431c
6819#define _PCH_DPD_AUX_CH_DATA4 0xe4320
6820#define _PCH_DPD_AUX_CH_DATA5 0xe4324
6821
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006822#define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6823#define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006824
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006825/* CPT */
6826#define PORT_TRANS_A_SEL_CPT 0
6827#define PORT_TRANS_B_SEL_CPT (1<<29)
6828#define PORT_TRANS_C_SEL_CPT (2<<29)
6829#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07006830#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02006831#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6832#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03006833#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6834#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006835
Ville Syrjälä086f8e82015-11-04 23:20:01 +02006836#define _TRANS_DP_CTL_A 0xe0300
6837#define _TRANS_DP_CTL_B 0xe1300
6838#define _TRANS_DP_CTL_C 0xe2300
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006839#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006840#define TRANS_DP_OUTPUT_ENABLE (1<<31)
6841#define TRANS_DP_PORT_SEL_B (0<<29)
6842#define TRANS_DP_PORT_SEL_C (1<<29)
6843#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08006844#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006845#define TRANS_DP_PORT_SEL_MASK (3<<29)
Ville Syrjäläadc289d2015-05-05 17:17:30 +03006846#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006847#define TRANS_DP_AUDIO_ONLY (1<<26)
6848#define TRANS_DP_ENH_FRAMING (1<<18)
6849#define TRANS_DP_8BPC (0<<9)
6850#define TRANS_DP_10BPC (1<<9)
6851#define TRANS_DP_6BPC (2<<9)
6852#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08006853#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006854#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6855#define TRANS_DP_VSYNC_ACTIVE_LOW 0
6856#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6857#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01006858#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006859
6860/* SNB eDP training params */
6861/* SNB A-stepping */
6862#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6863#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6864#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6865#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6866/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08006867#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6868#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6869#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6870#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6871#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006872#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6873
Keith Packard1a2eb462011-11-16 16:26:07 -08006874/* IVB */
6875#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6876#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6877#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6878#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6879#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6880#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03006881#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08006882
6883/* legacy values */
6884#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6885#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6886#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6887#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6888#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6889
6890#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6891
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006892#define VLV_PMWGICZ _MMIO(0x1300a4)
Imre Deak9e72b462014-05-05 15:13:55 +03006893
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05306894#define RC6_LOCATION _MMIO(0xD40)
6895#define RC6_CTX_IN_DRAM (1 << 0)
6896#define RC6_CTX_BASE _MMIO(0xD48)
6897#define RC6_CTX_BASE_MASK 0xFFFFFFF0
6898#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
6899#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
6900#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
6901#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
6902#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
6903#define IDLE_TIME_MASK 0xFFFFF
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006904#define FORCEWAKE _MMIO(0xA18C)
6905#define FORCEWAKE_VLV _MMIO(0x1300b0)
6906#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
6907#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
6908#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
6909#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
6910#define FORCEWAKE_ACK _MMIO(0x130090)
6911#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
Imre Deak981a5ae2014-04-14 20:24:22 +03006912#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6913#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6914#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6915
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006916#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
Imre Deak981a5ae2014-04-14 20:24:22 +03006917#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6918#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6919#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6920#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006921#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
6922#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
6923#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
6924#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
6925#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
6926#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
6927#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
Chris Wilsonc5836c22012-10-17 12:09:55 +01006928#define FORCEWAKE_KERNEL 0x1
6929#define FORCEWAKE_USER 0x2
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006930#define FORCEWAKE_MT_ACK _MMIO(0x130040)
6931#define ECOBUS _MMIO(0xa180)
Keith Packard8d715f02011-11-18 20:39:01 -08006932#define FORCEWAKE_MT_ENABLE (1<<5)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006933#define VLV_SPAREG2H _MMIO(0xA194)
Chris Wilson8fd26852010-12-08 18:40:43 +00006934
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006935#define GTFIFODBG _MMIO(0x120000)
Ville Syrjälä297b32e2016-04-13 21:09:30 +03006936#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
6937#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
Ville Syrjälä90f256b2013-11-14 01:59:59 +02006938#define GT_FIFO_SBDROPERR (1<<6)
6939#define GT_FIFO_BLOBDROPERR (1<<5)
6940#define GT_FIFO_SB_READ_ABORTERR (1<<4)
6941#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01006942#define GT_FIFO_OVFERR (1<<2)
6943#define GT_FIFO_IAWRERR (1<<1)
6944#define GT_FIFO_IARDERR (1<<0)
6945
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006946#define GTFIFOCTL _MMIO(0x120008)
Ville Syrjälä46520e22013-11-14 02:00:00 +02006947#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01006948#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Deepak Sa04f90a2015-04-16 08:51:28 +05306949#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6950#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
Chris Wilson91355832011-03-04 19:22:40 +00006951
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006952#define HSW_IDICR _MMIO(0x9008)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006953#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
Mika Kuoppala3accaf72016-04-13 17:26:43 +03006954#define HSW_EDRAM_CAP _MMIO(0x120010)
Damien Lespiau2db59d52015-02-03 14:25:14 +00006955#define EDRAM_ENABLED 0x1
Mika Kuoppalac02e85a2016-04-13 17:26:44 +03006956#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
6957#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
6958#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006959
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006960#define GEN6_UCGCTL1 _MMIO(0x9400)
Mika Kuoppala8aeb7f62016-06-07 17:19:05 +03006961# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03006962# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006963# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02006964# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006965
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006966#define GEN6_UCGCTL2 _MMIO(0x9404)
Damien Lespiauf9fc42f2015-02-26 18:20:39 +00006967# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
Jesse Barnes0f846f82012-06-14 11:04:47 -07006968# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07006969# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08006970# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08006971# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08006972# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08006973
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006974#define GEN6_UCGCTL3 _MMIO(0x9408)
Imre Deak9e72b462014-05-05 15:13:55 +03006975
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006976#define GEN7_UCGCTL4 _MMIO(0x940c)
Jesse Barnese3f33d42012-06-14 11:04:50 -07006977#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
Mika Kuoppalaeee8efb2016-06-07 17:18:53 +03006978#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
Jesse Barnese3f33d42012-06-14 11:04:50 -07006979
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006980#define GEN6_RCGCTL1 _MMIO(0x9410)
6981#define GEN6_RCGCTL2 _MMIO(0x9414)
6982#define GEN6_RSTCTL _MMIO(0x9420)
Imre Deak9e72b462014-05-05 15:13:55 +03006983
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006984#define GEN8_UCGCTL6 _MMIO(0x9430)
Damien Lespiau9253c2e2015-02-09 19:33:10 +00006985#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006986#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
Ben Widawsky868434c2015-03-11 10:49:32 +02006987#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006988
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006989#define GEN6_GFXPAUSE _MMIO(0xA000)
6990#define GEN6_RPNSWREQ _MMIO(0xA008)
Chris Wilson8fd26852010-12-08 18:40:43 +00006991#define GEN6_TURBO_DISABLE (1<<31)
6992#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03006993#define HSW_FREQUENCY(x) ((x)<<24)
Akash Goelde43ae92015-03-06 11:07:14 +05306994#define GEN9_FREQUENCY(x) ((x)<<23)
Chris Wilson8fd26852010-12-08 18:40:43 +00006995#define GEN6_OFFSET(x) ((x)<<19)
6996#define GEN6_AGGRESSIVE_TURBO (0<<15)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02006997#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
6998#define GEN6_RC_CONTROL _MMIO(0xA090)
Chris Wilson8fd26852010-12-08 18:40:43 +00006999#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
7000#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
7001#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
7002#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
7003#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08007004#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07007005#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00007006#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
7007#define GEN6_RC_CTL_HW_ENABLE (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007008#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
7009#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
7010#define GEN6_RPSTAT1 _MMIO(0xA01C)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007011#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08007012#define HSW_CAGF_SHIFT 7
Akash Goelde43ae92015-03-06 11:07:14 +05307013#define GEN9_CAGF_SHIFT 23
Jesse Barnesccab5c82011-01-18 15:49:25 -08007014#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08007015#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Akash Goelde43ae92015-03-06 11:07:14 +05307016#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007017#define GEN6_RP_CONTROL _MMIO(0xA024)
Chris Wilson8fd26852010-12-08 18:40:43 +00007018#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08007019#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
7020#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
7021#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
7022#define GEN6_RP_MEDIA_HW_MODE (1<<9)
7023#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00007024#define GEN6_RP_MEDIA_IS_GFX (1<<8)
7025#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007026#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
7027#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
7028#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01007029#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007030#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007031#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
7032#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
7033#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007034#define GEN6_CURICONT_MASK 0xffffff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007035#define GEN6_RP_CUR_UP _MMIO(0xA054)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007036#define GEN6_CURBSYTAVG_MASK 0xffffff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007037#define GEN6_RP_PREV_UP _MMIO(0xA058)
7038#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
Jesse Barnesccab5c82011-01-18 15:49:25 -08007039#define GEN6_CURIAVG_MASK 0xffffff
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007040#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
7041#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
7042#define GEN6_RP_UP_EI _MMIO(0xA068)
7043#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
7044#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
7045#define GEN6_RPDEUHWTC _MMIO(0xA080)
7046#define GEN6_RPDEUC _MMIO(0xA084)
7047#define GEN6_RPDEUCSW _MMIO(0xA088)
7048#define GEN6_RC_STATE _MMIO(0xA094)
Sagar Arun Kamble274008e2016-02-06 00:13:29 +05307049#define RC6_STATE (1 << 18)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007050#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
7051#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
7052#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
7053#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
7054#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
7055#define GEN6_RC_SLEEP _MMIO(0xA0B0)
7056#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
7057#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
7058#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
7059#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
7060#define VLV_RCEDATA _MMIO(0xA0BC)
7061#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
7062#define GEN6_PMINTRMSK _MMIO(0xA168)
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05307063#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007064#define VLV_PWRDWNUPCTL _MMIO(0xA294)
7065#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
7066#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
7067#define GEN9_PG_ENABLE _MMIO(0xA210)
Sagar Kamblea4104c52015-04-10 14:11:29 +05307068#define GEN9_RENDER_PG_ENABLE (1<<0)
7069#define GEN9_MEDIA_PG_ENABLE (1<<1)
Chris Wilson8fd26852010-12-08 18:40:43 +00007070
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007071#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
Gaurav K Singha9da9bc2014-12-05 14:13:41 +05307072#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
7073#define PIXEL_OVERLAP_CNT_SHIFT 30
7074
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007075#define GEN6_PMISR _MMIO(0x44020)
7076#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
7077#define GEN6_PMIIR _MMIO(0x44028)
7078#define GEN6_PMIER _MMIO(0x4402C)
Chris Wilson8fd26852010-12-08 18:40:43 +00007079#define GEN6_PM_MBOX_EVENT (1<<25)
7080#define GEN6_PM_THERMAL_EVENT (1<<24)
7081#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
7082#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
7083#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
7084#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
7085#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07007086#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07007087 GEN6_PM_RP_DOWN_THRESHOLD | \
7088 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00007089
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007090#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
Imre Deak9e72b462014-05-05 15:13:55 +03007091#define GEN7_GT_SCRATCH_REG_NUM 8
7092
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007093#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
Deepak S76c3552f2014-01-30 23:08:16 +05307094#define VLV_GFX_CLK_STATUS_BIT (1<<3)
7095#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
7096
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007097#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
7098#define VLV_COUNTER_CONTROL _MMIO(0x138104)
Jesse Barnes49798eb2013-09-26 17:55:57 -07007099#define VLV_COUNT_RANGE_HIGH (1<<15)
Deepak S31685c22014-07-03 17:33:01 -04007100#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
7101#define VLV_RENDER_RC0_COUNT_EN (1<<4)
Jesse Barnes49798eb2013-09-26 17:55:57 -07007102#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
7103#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007104#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
7105#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
7106#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
Imre Deak9cc19be2014-04-14 20:24:24 +03007107
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007108#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
7109#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
7110#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
7111#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
Ben Widawskycce66a22012-03-27 18:59:38 -07007112
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007113#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
Chris Wilson8fd26852010-12-08 18:40:43 +00007114#define GEN6_PCODE_READY (1<<31)
Ben Widawsky31643d52012-09-26 10:34:01 -07007115#define GEN6_PCODE_WRITE_RC6VIDS 0x4
7116#define GEN6_PCODE_READ_RC6VIDS 0x5
Damien Lespiau9043ae02015-04-30 16:39:18 +01007117#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
7118#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03007119#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
Damien Lespiau57520bc2015-04-30 16:39:19 +01007120#define GEN9_PCODE_READ_MEM_LATENCY 0x6
7121#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
7122#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
7123#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
7124#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01007125#define SKL_PCODE_CDCLK_CONTROL 0x7
7126#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
7127#define SKL_CDCLK_READY_FOR_CHANGE 0x1
Damien Lespiau9043ae02015-04-30 16:39:18 +01007128#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
7129#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
7130#define GEN6_READ_OC_PARAMS 0xc
Paulo Zanoni515b2392013-09-10 19:36:37 -03007131#define GEN6_PCODE_READ_D_COMP 0x10
7132#define GEN6_PCODE_WRITE_D_COMP 0x11
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307133#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
Ben Widawsky2a114cc2013-11-02 21:07:47 -07007134#define DISPLAY_IPS_CONTROL 0x19
Tom O'Rourke93ee2922014-11-19 14:21:52 -08007135#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007136#define GEN6_PCODE_DATA _MMIO(0x138128)
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07007137#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01007138#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007139#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
Chris Wilson8fd26852010-12-08 18:40:43 +00007140
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007141#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
Ben Widawsky4d855292011-12-12 19:34:16 -08007142#define GEN6_CORE_CPD_STATE_MASK (7<<4)
7143#define GEN6_RCn_MASK 7
7144#define GEN6_RC0 0
7145#define GEN6_RC3 2
7146#define GEN6_RC6 3
7147#define GEN6_RC7 4
7148
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007149#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02007150#define GEN8_LSLICESTAT_MASK 0x7
7151
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007152#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
7153#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
Jeff McGee5575f032015-02-27 10:22:32 -08007154#define CHV_SS_PG_ENABLE (1<<1)
7155#define CHV_EU08_PG_ENABLE (1<<9)
7156#define CHV_EU19_PG_ENABLE (1<<17)
7157#define CHV_EU210_PG_ENABLE (1<<25)
7158
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007159#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
7160#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
Jeff McGee5575f032015-02-27 10:22:32 -08007161#define CHV_EU311_PG_ENABLE (1<<1)
7162
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007163#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
Jeff McGee7f992ab2015-02-13 10:27:55 -06007164#define GEN9_PGCTL_SLICE_ACK (1 << 0)
Jeff McGee1c046bc2015-04-03 18:13:18 -07007165#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
Jeff McGee7f992ab2015-02-13 10:27:55 -06007166
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007167#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
7168#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
Jeff McGee7f992ab2015-02-13 10:27:55 -06007169#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
7170#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
7171#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
7172#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
7173#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
7174#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
7175#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
7176#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
7177
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007178#define GEN7_MISCCPCTL _MMIO(0x9424)
Alex Dai33a732f2015-08-12 15:43:36 +01007179#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
7180#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
7181#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
Arun Siluvery5b88aba2015-09-08 10:31:49 +01007182#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
Ben Widawskye3689192012-05-25 16:56:22 -07007183
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007184#define GEN8_GARBCNTL _MMIO(0xB004)
Arun Siluvery245d9662015-08-03 20:24:56 +01007185#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
7186
Ben Widawskye3689192012-05-25 16:56:22 -07007187/* IVYBRIDGE DPF */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007188#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07007189#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
7190#define GEN7_PARITY_ERROR_VALID (1<<13)
7191#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
7192#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
7193#define GEN7_PARITY_ERROR_ROW(reg) \
7194 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
7195#define GEN7_PARITY_ERROR_BANK(reg) \
7196 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
7197#define GEN7_PARITY_ERROR_SUBBANK(reg) \
7198 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
7199#define GEN7_L3CDERRST1_ENABLE (1<<7)
7200
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007201#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
Ben Widawskyb9524a12012-05-25 16:56:24 -07007202#define GEN7_L3LOG_SIZE 0x80
7203
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007204#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
7205#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
Jesse Barnes12f33822012-10-25 12:15:45 -07007206#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07007207#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Nick Hoath983b4b92015-04-10 13:12:25 +01007208#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
Jesse Barnes12f33822012-10-25 12:15:45 -07007209#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
7210
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007211#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00007212#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
Damien Lespiaue2db7072015-02-09 19:33:21 +00007213#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00007214
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007215#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
Tim Gore950b2aa2016-03-16 16:13:46 +00007216#define FLOW_CONTROL_ENABLE (1<<15)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08007217#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08007218#define STALL_DOP_GATING_DISABLE (1<<5)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08007219
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007220#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
7221#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
Jesse Barnes8ab43972012-10-25 12:15:42 -07007222#define DOP_CLOCK_GATING_DISABLE (1<<0)
7223
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007224#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
Francisco Jerezf3fc4882013-10-02 15:53:16 -07007225#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
7226
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007227#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
Robert Beckett6b6d5622015-09-08 10:31:52 +01007228#define GEN8_ST_PO_DISABLE (1<<13)
7229
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007230#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
Kenneth Graunke94411592014-12-31 16:23:00 -08007231#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
Ben Widawskyfd392b62013-11-04 22:52:39 -08007232#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Nick Hoath84241712015-02-05 10:47:20 +00007233#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
Ben Widawskybf663472013-11-02 21:07:57 -07007234#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08007235
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007236#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
Nick Hoathcac23df2015-02-05 10:47:22 +00007237#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
Tim Gorebfd8ad42016-04-19 15:45:52 +01007238#define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
Nick Hoathcac23df2015-02-05 10:47:22 +00007239
Jani Nikulac46f1112014-10-27 16:26:52 +02007240/* Audio */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007241#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
Jani Nikulac46f1112014-10-27 16:26:52 +02007242#define INTEL_AUDIO_DEVCL 0x808629FB
7243#define INTEL_AUDIO_DEVBLC 0x80862801
7244#define INTEL_AUDIO_DEVCTG 0x80862802
Wu Fengguange0dac652011-09-05 14:25:34 +08007245
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007246#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
Jani Nikulac46f1112014-10-27 16:26:52 +02007247#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
7248#define G4X_ELDV_DEVCTG (1 << 14)
7249#define G4X_ELD_ADDR_MASK (0xf << 5)
7250#define G4X_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007251#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
Wu Fengguange0dac652011-09-05 14:25:34 +08007252
Jani Nikulac46f1112014-10-27 16:26:52 +02007253#define _IBX_HDMIW_HDMIEDID_A 0xE2050
7254#define _IBX_HDMIW_HDMIEDID_B 0xE2150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007255#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
7256 _IBX_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007257#define _IBX_AUD_CNTL_ST_A 0xE20B4
7258#define _IBX_AUD_CNTL_ST_B 0xE21B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007259#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
7260 _IBX_AUD_CNTL_ST_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007261#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
7262#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
7263#define IBX_ELD_ACK (1 << 4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007264#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
Jani Nikula82910ac2014-10-27 16:26:59 +02007265#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
7266#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
Wu Fengguange0dac652011-09-05 14:25:34 +08007267
Jani Nikulac46f1112014-10-27 16:26:52 +02007268#define _CPT_HDMIW_HDMIEDID_A 0xE5050
7269#define _CPT_HDMIW_HDMIEDID_B 0xE5150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007270#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007271#define _CPT_AUD_CNTL_ST_A 0xE50B4
7272#define _CPT_AUD_CNTL_ST_B 0xE51B4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007273#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
7274#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
Wu Fengguange0dac652011-09-05 14:25:34 +08007275
Jani Nikulac46f1112014-10-27 16:26:52 +02007276#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7277#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007278#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007279#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7280#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007281#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
7282#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007283
Eric Anholtae662d32012-01-03 09:23:29 -08007284/* These are the 4 32-bit write offset registers for each stream
7285 * output buffer. It determines the offset from the
7286 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7287 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007288#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
Eric Anholtae662d32012-01-03 09:23:29 -08007289
Jani Nikulac46f1112014-10-27 16:26:52 +02007290#define _IBX_AUD_CONFIG_A 0xe2000
7291#define _IBX_AUD_CONFIG_B 0xe2100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007292#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007293#define _CPT_AUD_CONFIG_A 0xe5000
7294#define _CPT_AUD_CONFIG_B 0xe5100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007295#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
Jani Nikulac46f1112014-10-27 16:26:52 +02007296#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7297#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007298#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007299
Wu Fengguangb6daa022012-01-06 14:41:31 -06007300#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
7301#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
7302#define AUD_CONFIG_UPPER_N_SHIFT 20
Jani Nikulac46f1112014-10-27 16:26:52 +02007303#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
Wu Fengguangb6daa022012-01-06 14:41:31 -06007304#define AUD_CONFIG_LOWER_N_SHIFT 4
Jani Nikulac46f1112014-10-27 16:26:52 +02007305#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
Wu Fengguangb6daa022012-01-06 14:41:31 -06007306#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03007307#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
7308#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
7309#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
7310#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
7311#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
7312#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
7313#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
7314#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
7315#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
7316#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
7317#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06007318#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
7319
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007320/* HSW Audio */
Jani Nikulac46f1112014-10-27 16:26:52 +02007321#define _HSW_AUD_CONFIG_A 0x65000
7322#define _HSW_AUD_CONFIG_B 0x65100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007323#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007324
Jani Nikulac46f1112014-10-27 16:26:52 +02007325#define _HSW_AUD_MISC_CTRL_A 0x65010
7326#define _HSW_AUD_MISC_CTRL_B 0x65110
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007327#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007328
Jani Nikulac46f1112014-10-27 16:26:52 +02007329#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7330#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007331#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007332
7333/* Audio Digital Converter */
Jani Nikulac46f1112014-10-27 16:26:52 +02007334#define _HSW_AUD_DIG_CNVT_1 0x65080
7335#define _HSW_AUD_DIG_CNVT_2 0x65180
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007336#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
Jani Nikulac46f1112014-10-27 16:26:52 +02007337#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007338
Jani Nikulac46f1112014-10-27 16:26:52 +02007339#define _HSW_AUD_EDID_DATA_A 0x65050
7340#define _HSW_AUD_EDID_DATA_B 0x65150
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007341#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007342
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007343#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
7344#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
Jani Nikula82910ac2014-10-27 16:26:59 +02007345#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7346#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7347#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7348#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007349
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007350#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
Lu, Han632f3ab2015-05-05 09:05:47 +08007351#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7352
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007353/* HSW Power Wells */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007354#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */
7355#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */
7356#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */
7357#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03007358#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7359#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007360#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007361#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7362#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007363#define HSW_PWR_WELL_FORCE_ON (1<<19)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007364#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007365
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00007366/* SKL Fuse Status */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007367#define SKL_FUSE_STATUS _MMIO(0x42000)
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00007368#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7369#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7370#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7371#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7372
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007373/* Per-pipe DDI Function Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007374#define _TRANS_DDI_FUNC_CTL_A 0x60400
7375#define _TRANS_DDI_FUNC_CTL_B 0x61400
7376#define _TRANS_DDI_FUNC_CTL_C 0x62400
7377#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007378#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007379
Paulo Zanoniad80a812012-10-24 16:06:19 -02007380#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007381/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02007382#define TRANS_DDI_PORT_MASK (7<<28)
Daniel Vetter26804af2014-06-25 22:01:55 +03007383#define TRANS_DDI_PORT_SHIFT 28
Paulo Zanoniad80a812012-10-24 16:06:19 -02007384#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7385#define TRANS_DDI_PORT_NONE (0<<28)
7386#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7387#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7388#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7389#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7390#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7391#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7392#define TRANS_DDI_BPC_MASK (7<<20)
7393#define TRANS_DDI_BPC_8 (0<<20)
7394#define TRANS_DDI_BPC_10 (1<<20)
7395#define TRANS_DDI_BPC_6 (2<<20)
7396#define TRANS_DDI_BPC_12 (3<<20)
7397#define TRANS_DDI_PVSYNC (1<<17)
7398#define TRANS_DDI_PHSYNC (1<<16)
7399#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7400#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7401#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7402#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7403#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
Dave Airlie01b887c2014-05-02 11:17:41 +10007404#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
Paulo Zanoniad80a812012-10-24 16:06:19 -02007405#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007406
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007407/* DisplayPort Transport Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007408#define _DP_TP_CTL_A 0x64040
7409#define _DP_TP_CTL_B 0x64140
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007410#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007411#define DP_TP_CTL_ENABLE (1<<31)
7412#define DP_TP_CTL_MODE_SST (0<<27)
7413#define DP_TP_CTL_MODE_MST (1<<27)
Dave Airlie01b887c2014-05-02 11:17:41 +10007414#define DP_TP_CTL_FORCE_ACT (1<<25)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007415#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007416#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007417#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7418#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7419#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03007420#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7421#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007422#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03007423#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007424
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03007425/* DisplayPort Transport Status */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007426#define _DP_TP_STATUS_A 0x64044
7427#define _DP_TP_STATUS_B 0x64144
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007428#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
Dave Airlie01b887c2014-05-02 11:17:41 +10007429#define DP_TP_STATUS_IDLE_DONE (1<<25)
7430#define DP_TP_STATUS_ACT_SENT (1<<24)
7431#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7432#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7433#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7434#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7435#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03007436
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03007437/* DDI Buffer Control */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007438#define _DDI_BUF_CTL_A 0x64000
7439#define _DDI_BUF_CTL_B 0x64100
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007440#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007441#define DDI_BUF_CTL_ENABLE (1<<31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05307442#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007443#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00007444#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007445#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02007446#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02007447#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03007448#define DDI_PORT_WIDTH_MASK (7 << 1)
7449#define DDI_PORT_WIDTH_SHIFT 1
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03007450#define DDI_INIT_DISPLAY_DETECTED (1<<0)
7451
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03007452/* DDI Buffer Translations */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007453#define _DDI_BUF_TRANS_A 0x64E00
7454#define _DDI_BUF_TRANS_B 0x64E60
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007455#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
7456#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03007457
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03007458/* Sideband Interface (SBI) is programmed indirectly, via
7459 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7460 * which contains the payload */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007461#define SBI_ADDR _MMIO(0xC6000)
7462#define SBI_DATA _MMIO(0xC6004)
7463#define SBI_CTL_STAT _MMIO(0xC6008)
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02007464#define SBI_CTL_DEST_ICLK (0x0<<16)
7465#define SBI_CTL_DEST_MPHY (0x1<<16)
7466#define SBI_CTL_OP_IORD (0x2<<8)
7467#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03007468#define SBI_CTL_OP_CRRD (0x6<<8)
7469#define SBI_CTL_OP_CRWR (0x7<<8)
7470#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007471#define SBI_RESPONSE_SUCCESS (0x0<<1)
7472#define SBI_BUSY (0x1<<0)
7473#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007474
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007475/* SBI offsets */
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02007476#define SBI_SSCDIVINTPHASE 0x0200
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007477#define SBI_SSCDIVINTPHASE6 0x0600
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02007478#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
7479#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007480#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02007481#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
7482#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007483#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007484#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007485#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02007486#define SBI_SSCDITHPHASE 0x0204
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007487#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007488#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02007489#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007490#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007491#define SBI_SSCAUXDIV6 0x0610
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02007492#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
7493#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007494#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007495#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007496#define SBI_GEN0 0x1f00
7497#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007498
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007499/* LPT PIXCLK_GATE */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007500#define PIXCLK_GATE _MMIO(0xC6020)
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03007501#define PIXCLK_GATE_UNGATE (1<<0)
7502#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007503
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007504/* SPLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007505#define SPLL_CTL _MMIO(0x46020)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007506#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01007507#define SPLL_PLL_SSC (1<<28)
7508#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08007509#define SPLL_PLL_LCPLL (3<<28)
7510#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007511#define SPLL_PLL_FREQ_810MHz (0<<26)
7512#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08007513#define SPLL_PLL_FREQ_2700MHz (2<<26)
7514#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007515
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03007516/* WRPLL */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007517#define _WRPLL_CTL1 0x46040
7518#define _WRPLL_CTL2 0x46060
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007519#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007520#define WRPLL_PLL_ENABLE (1<<31)
Daniel Vetter114fe482014-06-25 22:01:48 +03007521#define WRPLL_PLL_SSC (1<<28)
7522#define WRPLL_PLL_NON_SSC (2<<28)
7523#define WRPLL_PLL_LCPLL (3<<28)
7524#define WRPLL_PLL_REF_MASK (3<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03007525/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007526#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08007527#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007528#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08007529#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7530#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007531#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08007532#define WRPLL_DIVIDER_FB_SHIFT 16
7533#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03007534
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007535/* Port clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007536#define _PORT_CLK_SEL_A 0x46100
7537#define _PORT_CLK_SEL_B 0x46104
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007538#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007539#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7540#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7541#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007542#define PORT_CLK_SEL_SPLL (3<<29)
Daniel Vetter716c2e52014-06-25 22:02:02 +03007543#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007544#define PORT_CLK_SEL_WRPLL1 (4<<29)
7545#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007546#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08007547#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007548
Paulo Zanonibb523fc2012-10-23 18:29:56 -02007549/* Transcoder clock selection */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007550#define _TRANS_CLK_SEL_A 0x46140
7551#define _TRANS_CLK_SEL_B 0x46144
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007552#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
Paulo Zanonibb523fc2012-10-23 18:29:56 -02007553/* For each transcoder, we need to select the corresponding port clock */
7554#define TRANS_CLK_SEL_DISABLED (0x0<<29)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007555#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007556
Ville Syrjälä7f1052a2016-04-26 19:46:32 +03007557#define CDCLK_FREQ _MMIO(0x46200)
7558
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007559#define _TRANSA_MSA_MISC 0x60410
7560#define _TRANSB_MSA_MISC 0x61410
7561#define _TRANSC_MSA_MISC 0x62410
7562#define _TRANS_EDP_MSA_MISC 0x6f410
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007563#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007564
Paulo Zanonic9809792012-10-23 18:30:00 -02007565#define TRANS_MSA_SYNC_CLK (1<<0)
7566#define TRANS_MSA_6_BPC (0<<5)
7567#define TRANS_MSA_8_BPC (1<<5)
7568#define TRANS_MSA_10_BPC (2<<5)
7569#define TRANS_MSA_12_BPC (3<<5)
7570#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03007571
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007572/* LCPLL Control */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007573#define LCPLL_CTL _MMIO(0x130040)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007574#define LCPLL_PLL_DISABLE (1<<31)
7575#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03007576#define LCPLL_CLK_FREQ_MASK (3<<26)
7577#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07007578#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7579#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7580#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007581#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03007582#define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007583#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007584#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03007585#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007586#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7587
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007588/*
7589 * SKL Clocks
7590 */
7591
7592/* CDCLK_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007593#define CDCLK_CTL _MMIO(0x46000)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007594#define CDCLK_FREQ_SEL_MASK (3<<26)
7595#define CDCLK_FREQ_450_432 (0<<26)
7596#define CDCLK_FREQ_540 (1<<26)
7597#define CDCLK_FREQ_337_308 (2<<26)
7598#define CDCLK_FREQ_675_617 (3<<26)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307599#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7600#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7601#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7602#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7603#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
Ville Syrjälä7fe62752016-05-11 22:44:51 +03007604#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
7605#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307606#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
Ville Syrjälä7fe62752016-05-11 22:44:51 +03007607#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307608
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007609/* LCPLL_CTL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007610#define LCPLL1_CTL _MMIO(0x46010)
7611#define LCPLL2_CTL _MMIO(0x46014)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007612#define LCPLL_PLL_ENABLE (1<<31)
7613
7614/* DPLL control1 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007615#define DPLL_CTRL1 _MMIO(0x6C058)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007616#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7617#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
Damien Lespiau71cd8422015-04-30 16:39:17 +01007618#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7619#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7620#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007621#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
Damien Lespiau71cd8422015-04-30 16:39:17 +01007622#define DPLL_CTRL1_LINK_RATE_2700 0
7623#define DPLL_CTRL1_LINK_RATE_1350 1
7624#define DPLL_CTRL1_LINK_RATE_810 2
7625#define DPLL_CTRL1_LINK_RATE_1620 3
7626#define DPLL_CTRL1_LINK_RATE_1080 4
7627#define DPLL_CTRL1_LINK_RATE_2160 5
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007628
7629/* DPLL control2 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007630#define DPLL_CTRL2 _MMIO(0x6C05C)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007631#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007632#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
Satheeshakrishna M540e7322014-11-13 14:55:16 +00007633#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007634#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007635#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7636
7637/* DPLL Status */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007638#define DPLL_STATUS _MMIO(0x6C060)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007639#define DPLL_LOCK(id) (1<<((id)*8))
7640
7641/* DPLL cfg */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007642#define _DPLL1_CFGCR1 0x6C040
7643#define _DPLL2_CFGCR1 0x6C048
7644#define _DPLL3_CFGCR1 0x6C050
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007645#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7646#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007647#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007648#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7649
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007650#define _DPLL1_CFGCR2 0x6C044
7651#define _DPLL2_CFGCR2 0x6C04C
7652#define _DPLL3_CFGCR2 0x6C054
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007653#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007654#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
7655#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007656#define DPLL_CFGCR2_KDIV_MASK (3<<5)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007657#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007658#define DPLL_CFGCR2_KDIV_5 (0<<5)
7659#define DPLL_CFGCR2_KDIV_2 (1<<5)
7660#define DPLL_CFGCR2_KDIV_3 (2<<5)
7661#define DPLL_CFGCR2_KDIV_1 (3<<5)
7662#define DPLL_CFGCR2_PDIV_MASK (7<<2)
Ville Syrjälä68d97532015-09-18 20:03:39 +03007663#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007664#define DPLL_CFGCR2_PDIV_1 (0<<2)
7665#define DPLL_CFGCR2_PDIV_2 (1<<2)
7666#define DPLL_CFGCR2_PDIV_3 (2<<2)
7667#define DPLL_CFGCR2_PDIV_7 (4<<2)
7668#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7669
Lyudeda3b8912016-02-04 10:43:21 -05007670#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007671#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
Satheeshakrishna M540e7322014-11-13 14:55:16 +00007672
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307673/* BXT display engine PLL */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007674#define BXT_DE_PLL_CTL _MMIO(0x6d000)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307675#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7676#define BXT_DE_PLL_RATIO_MASK 0xff
7677
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007678#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307679#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7680#define BXT_DE_PLL_LOCK (1 << 30)
7681
A.Sunil Kamath664326f2014-11-24 13:37:44 +05307682/* GEN9 DC */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007683#define DC_STATE_EN _MMIO(0x45504)
Imre Deak13ae3a02015-11-04 19:24:16 +02007684#define DC_STATE_DISABLE 0
A.Sunil Kamath664326f2014-11-24 13:37:44 +05307685#define DC_STATE_EN_UPTO_DC5 (1<<0)
7686#define DC_STATE_EN_DC9 (1<<3)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +05307687#define DC_STATE_EN_UPTO_DC6 (2<<0)
7688#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7689
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007690#define DC_STATE_DEBUG _MMIO(0x45520)
Mika Kuoppala5b076882016-02-19 12:26:04 +02007691#define DC_STATE_DEBUG_MASK_CORES (1<<0)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +05307692#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7693
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007694/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7695 * since on HSW we can't write to it using I915_WRITE. */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007696#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7697#define D_COMP_BDW _MMIO(0x138144)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007698#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7699#define D_COMP_COMP_FORCE (1<<8)
7700#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007701
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03007702/* Pipe WM_LINETIME - watermark line time */
Ville Syrjälä086f8e82015-11-04 23:20:01 +02007703#define _PIPE_WM_LINETIME_A 0x45270
7704#define _PIPE_WM_LINETIME_B 0x45274
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007705#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007706#define PIPE_WM_LINETIME_MASK (0x1ff)
7707#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03007708#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007709#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03007710
7711/* SFUSE_STRAP */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007712#define SFUSE_STRAP _MMIO(0xc2014)
Damien Lespiau658ac4c2014-02-10 17:19:45 +00007713#define SFUSE_STRAP_FUSE_LOCK (1<<13)
7714#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Ville Syrjälä65e472e2015-12-01 23:28:55 +02007715#define SFUSE_STRAP_CRT_DISABLED (1<<6)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03007716#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7717#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7718#define SFUSE_STRAP_DDID_DETECTED (1<<0)
7719
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007720#define WM_MISC _MMIO(0x45260)
Paulo Zanoni801bcff2013-05-31 10:08:35 -03007721#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7722
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007723#define WM_DBG _MMIO(0x45280)
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03007724#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7725#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7726#define WM_DBG_DISALLOW_SPRITE (1<<2)
7727
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007728/* pipe CSC */
7729#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7730#define _PIPE_A_CSC_COEFF_BY 0x49014
7731#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7732#define _PIPE_A_CSC_COEFF_BU 0x4901c
7733#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7734#define _PIPE_A_CSC_COEFF_BV 0x49024
7735#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03007736#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7737#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7738#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007739#define _PIPE_A_CSC_PREOFF_HI 0x49030
7740#define _PIPE_A_CSC_PREOFF_ME 0x49034
7741#define _PIPE_A_CSC_PREOFF_LO 0x49038
7742#define _PIPE_A_CSC_POSTOFF_HI 0x49040
7743#define _PIPE_A_CSC_POSTOFF_ME 0x49044
7744#define _PIPE_A_CSC_POSTOFF_LO 0x49048
7745
7746#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7747#define _PIPE_B_CSC_COEFF_BY 0x49114
7748#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7749#define _PIPE_B_CSC_COEFF_BU 0x4911c
7750#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7751#define _PIPE_B_CSC_COEFF_BV 0x49124
7752#define _PIPE_B_CSC_MODE 0x49128
7753#define _PIPE_B_CSC_PREOFF_HI 0x49130
7754#define _PIPE_B_CSC_PREOFF_ME 0x49134
7755#define _PIPE_B_CSC_PREOFF_LO 0x49138
7756#define _PIPE_B_CSC_POSTOFF_HI 0x49140
7757#define _PIPE_B_CSC_POSTOFF_ME 0x49144
7758#define _PIPE_B_CSC_POSTOFF_LO 0x49148
7759
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007760#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7761#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7762#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7763#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7764#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7765#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7766#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7767#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7768#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7769#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7770#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7771#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7772#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007773
Lionel Landwerlin82cf4352016-03-16 10:57:16 +00007774/* pipe degamma/gamma LUTs on IVB+ */
7775#define _PAL_PREC_INDEX_A 0x4A400
7776#define _PAL_PREC_INDEX_B 0x4AC00
7777#define _PAL_PREC_INDEX_C 0x4B400
7778#define PAL_PREC_10_12_BIT (0 << 31)
7779#define PAL_PREC_SPLIT_MODE (1 << 31)
7780#define PAL_PREC_AUTO_INCREMENT (1 << 15)
7781#define _PAL_PREC_DATA_A 0x4A404
7782#define _PAL_PREC_DATA_B 0x4AC04
7783#define _PAL_PREC_DATA_C 0x4B404
7784#define _PAL_PREC_GC_MAX_A 0x4A410
7785#define _PAL_PREC_GC_MAX_B 0x4AC10
7786#define _PAL_PREC_GC_MAX_C 0x4B410
7787#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
7788#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
7789#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
7790
7791#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
7792#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
7793#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
7794#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
7795
Lionel Landwerlin29dc3732016-03-16 10:57:17 +00007796/* pipe CSC & degamma/gamma LUTs on CHV */
7797#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
7798#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
7799#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
7800#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
7801#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
7802#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
7803#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
7804#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
7805#define CGM_PIPE_MODE_GAMMA (1 << 2)
7806#define CGM_PIPE_MODE_CSC (1 << 1)
7807#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
7808
7809#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
7810#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
7811#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
7812#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
7813#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
7814#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
7815#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
7816#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
7817
7818#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
7819#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
7820#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
7821#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
7822#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
7823#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
7824#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
7825#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
7826
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007827/* MIPI DSI registers */
7828
7829#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007830#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
Jani Nikula3230bf12013-08-27 15:12:16 +03007831
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307832/* BXT MIPI clock controls */
7833#define BXT_MAX_VAR_OUTPUT_KHZ 39500
7834
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007835#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307836#define BXT_MIPI1_DIV_SHIFT 26
7837#define BXT_MIPI2_DIV_SHIFT 10
7838#define BXT_MIPI_DIV_SHIFT(port) \
7839 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7840 BXT_MIPI2_DIV_SHIFT)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307841
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307842/* TX control divider to select actual TX clock output from (8x/var) */
Deepak M782d25c2016-02-15 22:43:57 +05307843#define BXT_MIPI1_TX_ESCLK_SHIFT 26
7844#define BXT_MIPI2_TX_ESCLK_SHIFT 10
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307845#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
7846 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7847 BXT_MIPI2_TX_ESCLK_SHIFT)
Deepak M782d25c2016-02-15 22:43:57 +05307848#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
7849#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307850#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
7851 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
Deepak M782d25c2016-02-15 22:43:57 +05307852 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7853#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
7854 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
7855/* RX upper control divider to select actual RX clock output from 8x */
7856#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
7857#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
7858#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
7859 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
7860 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
7861#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
7862#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
7863#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
7864 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
7865 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
7866#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
7867 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
7868/* 8/3X divider to select the actual 8/3X clock output from 8x */
7869#define BXT_MIPI1_8X_BY3_SHIFT 19
7870#define BXT_MIPI2_8X_BY3_SHIFT 3
7871#define BXT_MIPI_8X_BY3_SHIFT(port) \
7872 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
7873 BXT_MIPI2_8X_BY3_SHIFT)
7874#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
7875#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
7876#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
7877 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
7878 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
7879#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
7880 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
7881/* RX lower control divider to select actual RX clock output from 8x */
7882#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
7883#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
7884#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
7885 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
7886 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
7887#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
7888#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
7889#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
7890 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
7891 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
7892#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
7893 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
7894
7895#define RX_DIVIDER_BIT_1_2 0x3
7896#define RX_DIVIDER_BIT_3_4 0xC
Shashank Sharma11b8e4f2015-09-23 23:27:17 +05307897
Shashank Sharmad2e08c02015-09-01 19:41:40 +05307898/* BXT MIPI mode configure */
7899#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
7900#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007901#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05307902 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7903
7904#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
7905#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007906#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05307907 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7908
7909#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
7910#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007911#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
Shashank Sharmad2e08c02015-09-01 19:41:40 +05307912 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7913
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007914#define BXT_DSI_PLL_CTL _MMIO(0x161000)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05307915#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
7916#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7917#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7918#define BXT_DSIC_16X_BY2 (1 << 10)
7919#define BXT_DSIC_16X_BY3 (2 << 10)
7920#define BXT_DSIC_16X_BY4 (3 << 10)
Imre Deakdb18b6a2016-03-24 12:41:40 +02007921#define BXT_DSIC_16X_MASK (3 << 10)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05307922#define BXT_DSIA_16X_BY2 (1 << 8)
7923#define BXT_DSIA_16X_BY3 (2 << 8)
7924#define BXT_DSIA_16X_BY4 (3 << 8)
Imre Deakdb18b6a2016-03-24 12:41:40 +02007925#define BXT_DSIA_16X_MASK (3 << 8)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05307926#define BXT_DSI_FREQ_SEL_SHIFT 8
7927#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
7928
7929#define BXT_DSI_PLL_RATIO_MAX 0x7D
7930#define BXT_DSI_PLL_RATIO_MIN 0x22
7931#define BXT_DSI_PLL_RATIO_MASK 0xFF
Deepak M61ad9922015-12-04 19:47:38 +05307932#define BXT_REF_CLOCK_KHZ 19200
Shashank Sharmacfe01a52015-09-01 19:41:38 +05307933
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007934#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
Shashank Sharmacfe01a52015-09-01 19:41:38 +05307935#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
7936#define BXT_DSI_PLL_LOCKED (1 << 30)
7937
Jani Nikula3230bf12013-08-27 15:12:16 +03007938#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007939#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007940#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +05307941
7942 /* BXT port control */
7943#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
7944#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007945#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
Shashank Sharma37ab0812015-09-01 19:41:42 +05307946
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007947#define DPI_ENABLE (1 << 31) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007948#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7949#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
Gaurav K Singh369602d2014-12-05 14:09:28 +05307950#define DUAL_LINK_MODE_SHIFT 26
Jani Nikula3230bf12013-08-27 15:12:16 +03007951#define DUAL_LINK_MODE_MASK (1 << 26)
7952#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7953#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007954#define DITHERING_ENABLE (1 << 25) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007955#define FLOPPED_HSTX (1 << 23)
7956#define DE_INVERT (1 << 19) /* XXX */
7957#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7958#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7959#define AFE_LATCHOUT (1 << 17)
7960#define LP_OUTPUT_HOLD (1 << 16)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007961#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7962#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7963#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7964#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
Jani Nikula3230bf12013-08-27 15:12:16 +03007965#define CSB_SHIFT 9
7966#define CSB_MASK (3 << 9)
7967#define CSB_20MHZ (0 << 9)
7968#define CSB_10MHZ (1 << 9)
7969#define CSB_40MHZ (2 << 9)
7970#define BANDGAP_MASK (1 << 8)
7971#define BANDGAP_PNW_CIRCUIT (0 << 8)
7972#define BANDGAP_LNC_CIRCUIT (1 << 8)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007973#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7974#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
7975#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
7976#define TEARING_EFFECT_SHIFT 2 /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007977#define TEARING_EFFECT_MASK (3 << 2)
7978#define TEARING_EFFECT_OFF (0 << 2)
7979#define TEARING_EFFECT_DSI (1 << 2)
7980#define TEARING_EFFECT_GPIO (2 << 2)
7981#define LANE_CONFIGURATION_SHIFT 0
7982#define LANE_CONFIGURATION_MASK (3 << 0)
7983#define LANE_CONFIGURATION_4LANE (0 << 0)
7984#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
7985#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
7986
7987#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007988#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007989#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007990#define TEARING_EFFECT_DELAY_SHIFT 0
7991#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
7992
7993/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307994#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +03007995
7996/* MIPI DSI Controller and D-PHY registers */
7997
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307998#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007999#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008000#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +03008001#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
8002#define ULPS_STATE_MASK (3 << 1)
8003#define ULPS_STATE_ENTER (2 << 1)
8004#define ULPS_STATE_EXIT (1 << 1)
8005#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
8006#define DEVICE_READY (1 << 0)
8007
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308008#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008009#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008010#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308011#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008012#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008013#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +03008014#define TEARING_EFFECT (1 << 31)
8015#define SPL_PKT_SENT_INTERRUPT (1 << 30)
8016#define GEN_READ_DATA_AVAIL (1 << 29)
8017#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
8018#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
8019#define RX_PROT_VIOLATION (1 << 26)
8020#define RX_INVALID_TX_LENGTH (1 << 25)
8021#define ACK_WITH_NO_ERROR (1 << 24)
8022#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
8023#define LP_RX_TIMEOUT (1 << 22)
8024#define HS_TX_TIMEOUT (1 << 21)
8025#define DPI_FIFO_UNDERRUN (1 << 20)
8026#define LOW_CONTENTION (1 << 19)
8027#define HIGH_CONTENTION (1 << 18)
8028#define TXDSI_VC_ID_INVALID (1 << 17)
8029#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
8030#define TXCHECKSUM_ERROR (1 << 15)
8031#define TXECC_MULTIBIT_ERROR (1 << 14)
8032#define TXECC_SINGLE_BIT_ERROR (1 << 13)
8033#define TXFALSE_CONTROL_ERROR (1 << 12)
8034#define RXDSI_VC_ID_INVALID (1 << 11)
8035#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
8036#define RXCHECKSUM_ERROR (1 << 9)
8037#define RXECC_MULTIBIT_ERROR (1 << 8)
8038#define RXECC_SINGLE_BIT_ERROR (1 << 7)
8039#define RXFALSE_CONTROL_ERROR (1 << 6)
8040#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
8041#define RX_LP_TX_SYNC_ERROR (1 << 4)
8042#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
8043#define RXEOT_SYNC_ERROR (1 << 2)
8044#define RXSOT_SYNC_ERROR (1 << 1)
8045#define RXSOT_ERROR (1 << 0)
8046
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308047#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008048#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008049#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +03008050#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
8051#define CMD_MODE_NOT_SUPPORTED (0 << 13)
8052#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
8053#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
8054#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
8055#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
8056#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
8057#define VID_MODE_FORMAT_MASK (0xf << 7)
8058#define VID_MODE_NOT_SUPPORTED (0 << 7)
8059#define VID_MODE_FORMAT_RGB565 (1 << 7)
Jani Nikula42c151e2016-03-16 12:21:39 +02008060#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
8061#define VID_MODE_FORMAT_RGB666 (3 << 7)
Jani Nikula3230bf12013-08-27 15:12:16 +03008062#define VID_MODE_FORMAT_RGB888 (4 << 7)
8063#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
8064#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
8065#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
8066#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
8067#define DATA_LANES_PRG_REG_SHIFT 0
8068#define DATA_LANES_PRG_REG_MASK (7 << 0)
8069
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308070#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008071#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008072#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008073#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
8074
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308075#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008076#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008077#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008078#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
8079
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308080#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008081#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008082#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008083#define TURN_AROUND_TIMEOUT_MASK 0x3f
8084
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308085#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008086#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008087#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +03008088#define DEVICE_RESET_TIMER_MASK 0xffff
8089
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308090#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008091#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008092#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +03008093#define VERTICAL_ADDRESS_SHIFT 16
8094#define VERTICAL_ADDRESS_MASK (0xffff << 16)
8095#define HORIZONTAL_ADDRESS_SHIFT 0
8096#define HORIZONTAL_ADDRESS_MASK 0xffff
8097
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308098#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008099#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008100#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03008101#define DBI_FIFO_EMPTY_HALF (0 << 0)
8102#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
8103#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
8104
8105/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308106#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008107#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008108#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008109
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308110#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008111#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008112#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008113
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308114#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008115#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008116#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008117
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308118#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008119#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008120#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008121
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308122#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008123#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008124#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008125
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308126#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008127#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008128#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008129
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308130#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008131#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008132#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008133
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308134#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008135#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008136#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308137
Jani Nikula3230bf12013-08-27 15:12:16 +03008138/* regs above are bits 15:0 */
8139
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308140#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008141#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008142#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +03008143#define DPI_LP_MODE (1 << 6)
8144#define BACKLIGHT_OFF (1 << 5)
8145#define BACKLIGHT_ON (1 << 4)
8146#define COLOR_MODE_OFF (1 << 3)
8147#define COLOR_MODE_ON (1 << 2)
8148#define TURN_ON (1 << 1)
8149#define SHUTDOWN (1 << 0)
8150
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308151#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008152#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008153#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03008154#define COMMAND_BYTE_SHIFT 0
8155#define COMMAND_BYTE_MASK (0x3f << 0)
8156
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308157#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008158#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008159#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008160#define MASTER_INIT_TIMER_SHIFT 0
8161#define MASTER_INIT_TIMER_MASK (0xffff << 0)
8162
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308163#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008164#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008165#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008166 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +03008167#define MAX_RETURN_PKT_SIZE_SHIFT 0
8168#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
8169
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308170#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008171#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008172#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008173#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
8174#define DISABLE_VIDEO_BTA (1 << 3)
8175#define IP_TG_CONFIG (1 << 2)
8176#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
8177#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
8178#define VIDEO_MODE_BURST (3 << 0)
8179
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308180#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008181#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008182#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
Jani Nikulaf90e8c32016-06-03 17:57:05 +03008183#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
8184#define BXT_DPHY_DEFEATURE_EN (1 << 8)
Jani Nikula3230bf12013-08-27 15:12:16 +03008185#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
8186#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
8187#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
8188#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
8189#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
8190#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
8191#define CLOCKSTOP (1 << 1)
8192#define EOT_DISABLE (1 << 0)
8193
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308194#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008195#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008196#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +03008197#define LP_BYTECLK_SHIFT 0
8198#define LP_BYTECLK_MASK (0xffff << 0)
8199
8200/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308201#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008202#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008203#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03008204
8205/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308206#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008207#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008208#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03008209
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308210#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008211#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008212#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308213#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008214#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008215#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03008216#define LONG_PACKET_WORD_COUNT_SHIFT 8
8217#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
8218#define SHORT_PACKET_PARAM_SHIFT 8
8219#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
8220#define VIRTUAL_CHANNEL_SHIFT 6
8221#define VIRTUAL_CHANNEL_MASK (3 << 6)
8222#define DATA_TYPE_SHIFT 0
Ville Syrjälä395b2912015-09-18 20:03:40 +03008223#define DATA_TYPE_MASK (0x3f << 0)
Jani Nikula3230bf12013-08-27 15:12:16 +03008224/* data type values, see include/video/mipi_display.h */
8225
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308226#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008227#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008228#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008229#define DPI_FIFO_EMPTY (1 << 28)
8230#define DBI_FIFO_EMPTY (1 << 27)
8231#define LP_CTRL_FIFO_EMPTY (1 << 26)
8232#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
8233#define LP_CTRL_FIFO_FULL (1 << 24)
8234#define HS_CTRL_FIFO_EMPTY (1 << 18)
8235#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
8236#define HS_CTRL_FIFO_FULL (1 << 16)
8237#define LP_DATA_FIFO_EMPTY (1 << 10)
8238#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
8239#define LP_DATA_FIFO_FULL (1 << 8)
8240#define HS_DATA_FIFO_EMPTY (1 << 2)
8241#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
8242#define HS_DATA_FIFO_FULL (1 << 0)
8243
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308244#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008245#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008246#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03008247#define DBI_HS_LP_MODE_MASK (1 << 0)
8248#define DBI_LP_MODE (1 << 0)
8249#define DBI_HS_MODE (0 << 0)
8250
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308251#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008252#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008253#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +03008254#define EXIT_ZERO_COUNT_SHIFT 24
8255#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
8256#define TRAIL_COUNT_SHIFT 16
8257#define TRAIL_COUNT_MASK (0x1f << 16)
8258#define CLK_ZERO_COUNT_SHIFT 8
8259#define CLK_ZERO_COUNT_MASK (0xff << 8)
8260#define PREPARE_COUNT_SHIFT 0
8261#define PREPARE_COUNT_MASK (0x3f << 0)
8262
8263/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308264#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008265#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008266#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03008267
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008268#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
8269#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
8270#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03008271#define LP_HS_SSW_CNT_SHIFT 16
8272#define LP_HS_SSW_CNT_MASK (0xffff << 16)
8273#define HS_LP_PWR_SW_CNT_SHIFT 0
8274#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
8275
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308276#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008277#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008278#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +03008279#define STOP_STATE_STALL_COUNTER_SHIFT 0
8280#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
8281
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308282#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008283#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008284#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308285#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008286#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008287#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +03008288#define RX_CONTENTION_DETECTED (1 << 0)
8289
8290/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308291#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +03008292#define DBI_TYPEC_ENABLE (1 << 31)
8293#define DBI_TYPEC_WIP (1 << 30)
8294#define DBI_TYPEC_OPTION_SHIFT 28
8295#define DBI_TYPEC_OPTION_MASK (3 << 28)
8296#define DBI_TYPEC_FREQ_SHIFT 24
8297#define DBI_TYPEC_FREQ_MASK (0xf << 24)
8298#define DBI_TYPEC_OVERRIDE (1 << 8)
8299#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
8300#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
8301
8302
8303/* MIPI adapter registers */
8304
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308305#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008306#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008307#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03008308#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
8309#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
8310#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
8311#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
8312#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
8313#define READ_REQUEST_PRIORITY_SHIFT 3
8314#define READ_REQUEST_PRIORITY_MASK (3 << 3)
8315#define READ_REQUEST_PRIORITY_LOW (0 << 3)
8316#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
8317#define RGB_FLIP_TO_BGR (1 << 2)
8318
Jani Nikula6b93e9c2016-03-15 21:51:12 +02008319#define BXT_PIPE_SELECT_SHIFT 7
Shashank Sharmad2e08c02015-09-01 19:41:40 +05308320#define BXT_PIPE_SELECT_MASK (7 << 7)
Deepak M56c48972015-12-09 20:14:04 +05308321#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
Shashank Sharmad2e08c02015-09-01 19:41:40 +05308322
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308323#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008324#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008325#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03008326#define DATA_MEM_ADDRESS_SHIFT 5
8327#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
8328#define DATA_VALID (1 << 0)
8329
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308330#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008331#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008332#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03008333#define DATA_LENGTH_SHIFT 0
8334#define DATA_LENGTH_MASK (0xfffff << 0)
8335
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308336#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008337#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008338#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03008339#define COMMAND_MEM_ADDRESS_SHIFT 5
8340#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
8341#define AUTO_PWG_ENABLE (1 << 2)
8342#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
8343#define COMMAND_VALID (1 << 0)
8344
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308345#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008346#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008347#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03008348#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
8349#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
8350
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308351#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008352#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008353#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +03008354
Shashank Sharma4ad83e92014-06-02 18:07:47 +05308355#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02008356#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008357#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +03008358#define READ_DATA_VALID(n) (1 << (n))
8359
Antti Koskipaaa57c7742014-02-04 14:22:24 +02008360/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00008361#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8362#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02008363
Peter Antoine3bbaba02015-07-10 20:13:11 +03008364/* MOCS (Memory Object Control State) registers */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008365#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
Peter Antoine3bbaba02015-07-10 20:13:11 +03008366
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02008367#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
8368#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
8369#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
8370#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
8371#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
Peter Antoine3bbaba02015-07-10 20:13:11 +03008372
Tim Gored5165eb2016-02-04 11:49:34 +00008373/* gamt regs */
8374#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
8375#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
8376#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
8377#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
8378#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
8379
Jesse Barnes585fb112008-07-29 11:54:06 -07008380#endif /* _I915_REG_H_ */