Thomas Gleixner | 50acfb2 | 2019-05-29 07:18:00 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Regents of the University of California |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 4 | * Copyright (C) 2019 Western Digital Corporation or its affiliates. |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 5 | * Copyright (C) 2020 FORTH-ICS/CARV |
| 6 | * Nick Kossifidis <mick@ics.forth.gr> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/mm.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 11 | #include <linux/memblock.h> |
Mike Rapoport | 57c8a66 | 2018-10-30 15:09:49 -0700 | [diff] [blame] | 12 | #include <linux/initrd.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 13 | #include <linux/swap.h> |
Kefeng Wang | ce3aca0 | 2021-06-02 16:55:16 +0800 | [diff] [blame] | 14 | #include <linux/swiotlb.h> |
Christoph Hellwig | 5ec9c4f | 2018-01-16 09:37:50 +0100 | [diff] [blame] | 15 | #include <linux/sizes.h> |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 16 | #include <linux/of_fdt.h> |
Nick Kossifidis | 5640975 | 2021-04-19 03:55:39 +0300 | [diff] [blame] | 17 | #include <linux/of_reserved_mem.h> |
Albert Ou | 922b037 | 2019-09-27 16:14:18 -0700 | [diff] [blame] | 18 | #include <linux/libfdt.h> |
Zong Li | d27c3c9 | 2020-03-10 00:55:41 +0800 | [diff] [blame] | 19 | #include <linux/set_memory.h> |
Kefeng Wang | da81558 | 2020-10-31 14:01:12 +0800 | [diff] [blame] | 20 | #include <linux/dma-map-ops.h> |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 21 | #include <linux/crash_dump.h> |
Kefeng Wang | 8ba1a8b | 2021-07-30 20:48:41 +0800 | [diff] [blame] | 22 | #include <linux/hugetlb.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 23 | |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 24 | #include <asm/fixmap.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 25 | #include <asm/tlbflush.h> |
| 26 | #include <asm/sections.h> |
Palmer Dabbelt | 2d26825 | 2020-04-14 13:43:24 +0900 | [diff] [blame] | 27 | #include <asm/soc.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 28 | #include <asm/io.h> |
Zong Li | b422d28 | 2020-06-03 16:03:55 -0700 | [diff] [blame] | 29 | #include <asm/ptdump.h> |
Atish Patra | 4f0e8ee | 2020-11-18 16:38:29 -0800 | [diff] [blame] | 30 | #include <asm/numa.h> |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 31 | |
Paul Walmsley | ffaee27 | 2019-10-17 15:00:17 -0700 | [diff] [blame] | 32 | #include "../kernel/head.h" |
| 33 | |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 34 | struct kernel_mapping kernel_map __ro_after_init; |
| 35 | EXPORT_SYMBOL(kernel_map); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 36 | #ifdef CONFIG_XIP_KERNEL |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 37 | #define kernel_map (*(struct kernel_mapping *)XIP_FIXUP(&kernel_map)) |
| 38 | #endif |
| 39 | |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 40 | #ifdef CONFIG_64BIT |
| 41 | u64 satp_mode = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_48 : SATP_MODE_39; |
| 42 | #else |
| 43 | u64 satp_mode = SATP_MODE_32; |
| 44 | #endif |
| 45 | EXPORT_SYMBOL(satp_mode); |
| 46 | |
kernel test robot | 20aa495 | 2022-01-19 11:38:36 +0800 | [diff] [blame] | 47 | bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL); |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 48 | EXPORT_SYMBOL(pgtable_l4_enabled); |
| 49 | |
Alexandre Ghiti | 6d7f91d | 2021-07-21 09:59:35 +0200 | [diff] [blame] | 50 | phys_addr_t phys_ram_base __ro_after_init; |
| 51 | EXPORT_SYMBOL(phys_ram_base); |
| 52 | |
Anup Patel | 387181d | 2019-03-26 08:03:47 +0000 | [diff] [blame] | 53 | unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] |
| 54 | __page_aligned_bss; |
| 55 | EXPORT_SYMBOL(empty_zero_page); |
| 56 | |
Anup Patel | d90d45d | 2019-06-07 06:01:29 +0000 | [diff] [blame] | 57 | extern char _start[]; |
Anup Patel | 8f3a2b4 | 2020-09-17 15:37:10 -0700 | [diff] [blame] | 58 | #define DTB_EARLY_BASE_VA PGDIR_SIZE |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 59 | void *_dtb_early_va __initdata; |
| 60 | uintptr_t _dtb_early_pa __initdata; |
Anup Patel | d90d45d | 2019-06-07 06:01:29 +0000 | [diff] [blame] | 61 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 62 | static phys_addr_t dma32_phys_limit __initdata; |
Kefeng Wang | da81558 | 2020-10-31 14:01:12 +0800 | [diff] [blame] | 63 | |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 64 | static void __init zone_sizes_init(void) |
| 65 | { |
Christoph Hellwig | 5ec9c4f | 2018-01-16 09:37:50 +0100 | [diff] [blame] | 66 | unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, }; |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 67 | |
Zong Li | d5fad48 | 2018-06-25 16:49:37 +0800 | [diff] [blame] | 68 | #ifdef CONFIG_ZONE_DMA32 |
Kefeng Wang | da81558 | 2020-10-31 14:01:12 +0800 | [diff] [blame] | 69 | max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit); |
Zong Li | d5fad48 | 2018-06-25 16:49:37 +0800 | [diff] [blame] | 70 | #endif |
Christoph Hellwig | 5ec9c4f | 2018-01-16 09:37:50 +0100 | [diff] [blame] | 71 | max_zone_pfns[ZONE_NORMAL] = max_low_pfn; |
| 72 | |
Mike Rapoport | 9691a07 | 2020-06-03 15:57:10 -0700 | [diff] [blame] | 73 | free_area_init(max_zone_pfns); |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 74 | } |
| 75 | |
Kefeng Wang | 8fa3cdf | 2020-05-14 19:53:35 +0800 | [diff] [blame] | 76 | #if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM) |
Yash Shah | 2cc6c4a | 2019-11-18 05:58:34 +0000 | [diff] [blame] | 77 | static inline void print_mlk(char *name, unsigned long b, unsigned long t) |
| 78 | { |
| 79 | pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld kB)\n", name, b, t, |
| 80 | (((t) - (b)) >> 10)); |
| 81 | } |
| 82 | |
| 83 | static inline void print_mlm(char *name, unsigned long b, unsigned long t) |
| 84 | { |
| 85 | pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld MB)\n", name, b, t, |
| 86 | (((t) - (b)) >> 20)); |
| 87 | } |
| 88 | |
Jisheng Zhang | 1987501 | 2021-03-30 02:22:21 +0800 | [diff] [blame] | 89 | static void __init print_vm_layout(void) |
Yash Shah | 2cc6c4a | 2019-11-18 05:58:34 +0000 | [diff] [blame] | 90 | { |
| 91 | pr_notice("Virtual kernel memory layout:\n"); |
| 92 | print_mlk("fixmap", (unsigned long)FIXADDR_START, |
| 93 | (unsigned long)FIXADDR_TOP); |
| 94 | print_mlm("pci io", (unsigned long)PCI_IO_START, |
| 95 | (unsigned long)PCI_IO_END); |
| 96 | print_mlm("vmemmap", (unsigned long)VMEMMAP_START, |
| 97 | (unsigned long)VMEMMAP_END); |
| 98 | print_mlm("vmalloc", (unsigned long)VMALLOC_START, |
| 99 | (unsigned long)VMALLOC_END); |
| 100 | print_mlm("lowmem", (unsigned long)PAGE_OFFSET, |
| 101 | (unsigned long)high_memory); |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 102 | if (IS_ENABLED(CONFIG_64BIT)) { |
Alexandre Ghiti | f7ae023 | 2021-12-06 11:46:45 +0100 | [diff] [blame] | 103 | #ifdef CONFIG_KASAN |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 104 | print_mlm("kasan", KASAN_SHADOW_START, KASAN_SHADOW_END); |
Alexandre Ghiti | f7ae023 | 2021-12-06 11:46:45 +0100 | [diff] [blame] | 105 | #endif |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 106 | |
Jisheng Zhang | 07aabe8 | 2021-12-06 23:03:50 +0800 | [diff] [blame] | 107 | print_mlm("kernel", (unsigned long)KERNEL_LINK_ADDR, |
| 108 | (unsigned long)ADDRESS_SPACE_END); |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 109 | } |
Yash Shah | 2cc6c4a | 2019-11-18 05:58:34 +0000 | [diff] [blame] | 110 | } |
| 111 | #else |
| 112 | static void print_vm_layout(void) { } |
| 113 | #endif /* CONFIG_DEBUG_VM */ |
| 114 | |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 115 | void __init mem_init(void) |
| 116 | { |
| 117 | #ifdef CONFIG_FLATMEM |
| 118 | BUG_ON(!mem_map); |
| 119 | #endif /* CONFIG_FLATMEM */ |
| 120 | |
Kefeng Wang | ce3aca0 | 2021-06-02 16:55:16 +0800 | [diff] [blame] | 121 | #ifdef CONFIG_SWIOTLB |
| 122 | if (swiotlb_force == SWIOTLB_FORCE || |
| 123 | max_pfn > PFN_DOWN(dma32_phys_limit)) |
| 124 | swiotlb_init(1); |
| 125 | else |
| 126 | swiotlb_force = SWIOTLB_NO_FORCE; |
| 127 | #endif |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 128 | high_memory = (void *)(__va(PFN_PHYS(max_low_pfn))); |
Mike Rapoport | c6ffc5c | 2018-10-30 15:09:30 -0700 | [diff] [blame] | 129 | memblock_free_all(); |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 130 | |
Yash Shah | 2cc6c4a | 2019-11-18 05:58:34 +0000 | [diff] [blame] | 131 | print_vm_layout(); |
Palmer Dabbelt | 76d2a04 | 2017-07-10 18:00:26 -0700 | [diff] [blame] | 132 | } |
| 133 | |
Alexandre Ghiti | f7ae023 | 2021-12-06 11:46:45 +0100 | [diff] [blame] | 134 | /* Limit the memory size via mem. */ |
| 135 | static phys_addr_t memory_limit; |
Kefeng Wang | c9811e3 | 2021-06-02 16:55:17 +0800 | [diff] [blame] | 136 | |
| 137 | static int __init early_mem(char *p) |
| 138 | { |
| 139 | u64 size; |
| 140 | |
| 141 | if (!p) |
| 142 | return 1; |
| 143 | |
| 144 | size = memparse(p, &p) & PAGE_MASK; |
| 145 | memory_limit = min_t(u64, size, memory_limit); |
| 146 | |
| 147 | pr_notice("Memory limited to %lldMB\n", (u64)memory_limit >> 20); |
| 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | early_param("mem", early_mem); |
| 152 | |
Kefeng Wang | f842f5f | 2021-05-10 19:42:22 +0800 | [diff] [blame] | 153 | static void __init setup_bootmem(void) |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 154 | { |
Zong Li | ac51e00 | 2020-01-02 11:12:40 +0800 | [diff] [blame] | 155 | phys_addr_t vmlinux_end = __pa_symbol(&_end); |
Jisheng Zhang | 07aabe8 | 2021-12-06 23:03:50 +0800 | [diff] [blame] | 156 | phys_addr_t max_mapped_addr; |
Jisheng Zhang | fe036db | 2021-12-06 23:03:52 +0800 | [diff] [blame] | 157 | phys_addr_t phys_ram_end, vmlinux_start; |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 158 | |
Jisheng Zhang | fe036db | 2021-12-06 23:03:52 +0800 | [diff] [blame] | 159 | if (IS_ENABLED(CONFIG_XIP_KERNEL)) |
| 160 | vmlinux_start = __pa_symbol(&_sdata); |
| 161 | else |
| 162 | vmlinux_start = __pa_symbol(&_start); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 163 | |
Kefeng Wang | c9811e3 | 2021-06-02 16:55:17 +0800 | [diff] [blame] | 164 | memblock_enforce_memory_limit(memory_limit); |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 165 | |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 166 | /* |
Geert Uytterhoeven | 8db6f93 | 2021-04-29 17:05:00 +0200 | [diff] [blame] | 167 | * Make sure we align the reservation on PMD_SIZE since we will |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 168 | * map the kernel in the linear mapping as read-only: we do not want |
| 169 | * any allocation to happen between _end and the next pmd aligned page. |
| 170 | */ |
Jisheng Zhang | 07aabe8 | 2021-12-06 23:03:50 +0800 | [diff] [blame] | 171 | if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_STRICT_KERNEL_RWX)) |
| 172 | vmlinux_end = (vmlinux_end + PMD_SIZE - 1) & PMD_MASK; |
| 173 | /* |
| 174 | * Reserve from the start of the kernel to the end of the kernel |
| 175 | */ |
Geert Uytterhoeven | 8db6f93 | 2021-04-29 17:05:00 +0200 | [diff] [blame] | 176 | memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start); |
Anup Patel | d90d45d | 2019-06-07 06:01:29 +0000 | [diff] [blame] | 177 | |
Alexandre Ghiti | 6d7f91d | 2021-07-21 09:59:35 +0200 | [diff] [blame] | 178 | phys_ram_end = memblock_end_of_DRAM(); |
Jisheng Zhang | fe036db | 2021-12-06 23:03:52 +0800 | [diff] [blame] | 179 | if (!IS_ENABLED(CONFIG_XIP_KERNEL)) |
| 180 | phys_ram_base = memblock_start_of_DRAM(); |
Atish Patra | abb8e86 | 2021-01-11 15:45:02 -0800 | [diff] [blame] | 181 | /* |
| 182 | * memblock allocator is not aware of the fact that last 4K bytes of |
| 183 | * the addressable memory can not be mapped because of IS_ERR_VALUE |
| 184 | * macro. Make sure that last 4k bytes are not usable by memblock |
Alexandre Ghiti | db6b84a | 2021-06-29 11:13:48 +0200 | [diff] [blame] | 185 | * if end of dram is equal to maximum addressable memory. For 64-bit |
| 186 | * kernel, this problem can't happen here as the end of the virtual |
| 187 | * address space is occupied by the kernel mapping then this check must |
Alexandre Ghiti | fdf3a7a | 2021-07-26 07:42:54 +0200 | [diff] [blame] | 188 | * be done as soon as the kernel mapping base address is determined. |
Atish Patra | abb8e86 | 2021-01-11 15:45:02 -0800 | [diff] [blame] | 189 | */ |
Jisheng Zhang | 07aabe8 | 2021-12-06 23:03:50 +0800 | [diff] [blame] | 190 | if (!IS_ENABLED(CONFIG_64BIT)) { |
| 191 | max_mapped_addr = __pa(~(ulong)0); |
| 192 | if (max_mapped_addr == (phys_ram_end - 1)) |
| 193 | memblock_set_current_limit(max_mapped_addr - 4096); |
| 194 | } |
Atish Patra | abb8e86 | 2021-01-11 15:45:02 -0800 | [diff] [blame] | 195 | |
Alexandre Ghiti | 6d7f91d | 2021-07-21 09:59:35 +0200 | [diff] [blame] | 196 | min_low_pfn = PFN_UP(phys_ram_base); |
| 197 | max_low_pfn = max_pfn = PFN_DOWN(phys_ram_end); |
Kefeng Wang | f6e5aed | 2021-02-25 14:54:17 +0800 | [diff] [blame] | 198 | |
Kefeng Wang | da81558 | 2020-10-31 14:01:12 +0800 | [diff] [blame] | 199 | dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn)); |
Guo Ren | 336e8eb | 2021-01-21 14:31:17 +0800 | [diff] [blame] | 200 | set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET); |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 201 | |
Kefeng Wang | aec33b5 | 2021-01-15 13:46:06 +0800 | [diff] [blame] | 202 | reserve_initrd_mem(); |
Albert Ou | 922b037 | 2019-09-27 16:14:18 -0700 | [diff] [blame] | 203 | /* |
Vitaly Wool | f105aa9 | 2021-01-16 01:49:48 +0200 | [diff] [blame] | 204 | * If DTB is built in, no need to reserve its memblock. |
| 205 | * Otherwise, do reserve it but avoid using |
| 206 | * early_init_fdt_reserve_self() since __pa() does |
Albert Ou | 922b037 | 2019-09-27 16:14:18 -0700 | [diff] [blame] | 207 | * not work for DTB pointers that are fixmap addresses |
| 208 | */ |
Vitaly Wool | f105aa9 | 2021-01-16 01:49:48 +0200 | [diff] [blame] | 209 | if (!IS_ENABLED(CONFIG_BUILTIN_DTB)) |
| 210 | memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va)); |
Albert Ou | 922b037 | 2019-09-27 16:14:18 -0700 | [diff] [blame] | 211 | |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 212 | early_init_fdt_scan_reserved_mem(); |
Kefeng Wang | da81558 | 2020-10-31 14:01:12 +0800 | [diff] [blame] | 213 | dma_contiguous_reserve(dma32_phys_limit); |
Kefeng Wang | 8ba1a8b | 2021-07-30 20:48:41 +0800 | [diff] [blame] | 214 | if (IS_ENABLED(CONFIG_64BIT)) |
| 215 | hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT); |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 216 | memblock_allow_resize(); |
Anup Patel | 0651c26 | 2019-02-21 11:25:49 +0530 | [diff] [blame] | 217 | } |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 218 | |
Christoph Hellwig | 6bd33e1 | 2019-10-28 13:10:41 +0100 | [diff] [blame] | 219 | #ifdef CONFIG_MMU |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 220 | struct pt_alloc_ops pt_ops __initdata; |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 221 | |
Kenneth Lee | fb31f0a | 2021-07-28 15:15:57 +0800 | [diff] [blame] | 222 | unsigned long riscv_pfn_base __ro_after_init; |
| 223 | EXPORT_SYMBOL(riscv_pfn_base); |
Anup Patel | 387181d | 2019-03-26 08:03:47 +0000 | [diff] [blame] | 224 | |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 225 | pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 226 | pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 227 | static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 228 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 229 | pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 230 | static pud_t __maybe_unused early_dtb_pud[PTRS_PER_PUD] __initdata __aligned(PAGE_SIZE); |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 231 | static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 232 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 233 | #ifdef CONFIG_XIP_KERNEL |
Jisheng Zhang | 805a3eb | 2021-12-06 23:03:53 +0800 | [diff] [blame] | 234 | #define pt_ops (*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops)) |
Palmer Dabbelt | ca0cb9a | 2022-02-04 13:14:08 -0800 | [diff] [blame] | 235 | #define riscv_pfn_base (*(unsigned long *)XIP_FIXUP(&riscv_pfn_base)) |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 236 | #define trampoline_pg_dir ((pgd_t *)XIP_FIXUP(trampoline_pg_dir)) |
| 237 | #define fixmap_pte ((pte_t *)XIP_FIXUP(fixmap_pte)) |
| 238 | #define early_pg_dir ((pgd_t *)XIP_FIXUP(early_pg_dir)) |
| 239 | #endif /* CONFIG_XIP_KERNEL */ |
| 240 | |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 241 | void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) |
| 242 | { |
| 243 | unsigned long addr = __fix_to_virt(idx); |
| 244 | pte_t *ptep; |
| 245 | |
| 246 | BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses); |
| 247 | |
| 248 | ptep = &fixmap_pte[pte_index(addr)]; |
| 249 | |
Greentime Hu | 21190b7 | 2020-08-04 11:02:05 +0800 | [diff] [blame] | 250 | if (pgprot_val(prot)) |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 251 | set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); |
Greentime Hu | 21190b7 | 2020-08-04 11:02:05 +0800 | [diff] [blame] | 252 | else |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 253 | pte_clear(&init_mm, addr, ptep); |
Greentime Hu | 21190b7 | 2020-08-04 11:02:05 +0800 | [diff] [blame] | 254 | local_flush_tlb_page(addr); |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 255 | } |
| 256 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 257 | static inline pte_t *__init get_pte_virt_early(phys_addr_t pa) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 258 | { |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 259 | return (pte_t *)((uintptr_t)pa); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 260 | } |
| 261 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 262 | static inline pte_t *__init get_pte_virt_fixmap(phys_addr_t pa) |
| 263 | { |
| 264 | clear_fixmap(FIX_PTE); |
| 265 | return (pte_t *)set_fixmap_offset(FIX_PTE, pa); |
| 266 | } |
| 267 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 268 | static inline pte_t *__init get_pte_virt_late(phys_addr_t pa) |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 269 | { |
| 270 | return (pte_t *) __va(pa); |
| 271 | } |
| 272 | |
| 273 | static inline phys_addr_t __init alloc_pte_early(uintptr_t va) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 274 | { |
| 275 | /* |
| 276 | * We only create PMD or PGD early mappings so we |
| 277 | * should never reach here with MMU disabled. |
| 278 | */ |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 279 | BUG(); |
| 280 | } |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 281 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 282 | static inline phys_addr_t __init alloc_pte_fixmap(uintptr_t va) |
| 283 | { |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 284 | return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); |
| 285 | } |
| 286 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 287 | static phys_addr_t __init alloc_pte_late(uintptr_t va) |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 288 | { |
| 289 | unsigned long vaddr; |
| 290 | |
| 291 | vaddr = __get_free_page(GFP_KERNEL); |
zhouchuangao | e75e6bf | 2021-03-30 06:56:26 -0700 | [diff] [blame] | 292 | BUG_ON(!vaddr || !pgtable_pte_page_ctor(virt_to_page(vaddr))); |
| 293 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 294 | return __pa(vaddr); |
| 295 | } |
| 296 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 297 | static void __init create_pte_mapping(pte_t *ptep, |
| 298 | uintptr_t va, phys_addr_t pa, |
| 299 | phys_addr_t sz, pgprot_t prot) |
| 300 | { |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 301 | uintptr_t pte_idx = pte_index(va); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 302 | |
| 303 | BUG_ON(sz != PAGE_SIZE); |
| 304 | |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 305 | if (pte_none(ptep[pte_idx])) |
| 306 | ptep[pte_idx] = pfn_pte(PFN_DOWN(pa), prot); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | #ifndef __PAGETABLE_PMD_FOLDED |
| 310 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 311 | static pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; |
| 312 | static pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss; |
| 313 | static pmd_t early_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 314 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 315 | #ifdef CONFIG_XIP_KERNEL |
| 316 | #define trampoline_pmd ((pmd_t *)XIP_FIXUP(trampoline_pmd)) |
| 317 | #define fixmap_pmd ((pmd_t *)XIP_FIXUP(fixmap_pmd)) |
| 318 | #define early_pmd ((pmd_t *)XIP_FIXUP(early_pmd)) |
| 319 | #endif /* CONFIG_XIP_KERNEL */ |
| 320 | |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 321 | static pud_t trampoline_pud[PTRS_PER_PUD] __page_aligned_bss; |
| 322 | static pud_t fixmap_pud[PTRS_PER_PUD] __page_aligned_bss; |
| 323 | static pud_t early_pud[PTRS_PER_PUD] __initdata __aligned(PAGE_SIZE); |
| 324 | |
| 325 | #ifdef CONFIG_XIP_KERNEL |
| 326 | #define trampoline_pud ((pud_t *)XIP_FIXUP(trampoline_pud)) |
| 327 | #define fixmap_pud ((pud_t *)XIP_FIXUP(fixmap_pud)) |
| 328 | #define early_pud ((pud_t *)XIP_FIXUP(early_pud)) |
| 329 | #endif /* CONFIG_XIP_KERNEL */ |
| 330 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 331 | static pmd_t *__init get_pmd_virt_early(phys_addr_t pa) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 332 | { |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 333 | /* Before MMU is enabled */ |
| 334 | return (pmd_t *)((uintptr_t)pa); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 335 | } |
| 336 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 337 | static pmd_t *__init get_pmd_virt_fixmap(phys_addr_t pa) |
| 338 | { |
| 339 | clear_fixmap(FIX_PMD); |
| 340 | return (pmd_t *)set_fixmap_offset(FIX_PMD, pa); |
| 341 | } |
| 342 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 343 | static pmd_t *__init get_pmd_virt_late(phys_addr_t pa) |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 344 | { |
| 345 | return (pmd_t *) __va(pa); |
| 346 | } |
| 347 | |
| 348 | static phys_addr_t __init alloc_pmd_early(uintptr_t va) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 349 | { |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 350 | BUG_ON((va - kernel_map.virt_addr) >> PUD_SHIFT); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 351 | |
Alexandre Ghiti | 0f02de4 | 2021-02-21 09:22:33 -0500 | [diff] [blame] | 352 | return (uintptr_t)early_pmd; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 353 | } |
| 354 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 355 | static phys_addr_t __init alloc_pmd_fixmap(uintptr_t va) |
| 356 | { |
| 357 | return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); |
| 358 | } |
| 359 | |
Jisheng Zhang | 0106235 | 2021-05-16 21:15:56 +0800 | [diff] [blame] | 360 | static phys_addr_t __init alloc_pmd_late(uintptr_t va) |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 361 | { |
| 362 | unsigned long vaddr; |
| 363 | |
| 364 | vaddr = __get_free_page(GFP_KERNEL); |
Kefeng Wang | 5a7ac59 | 2021-09-27 11:03:25 +0800 | [diff] [blame] | 365 | BUG_ON(!vaddr || !pgtable_pmd_page_ctor(virt_to_page(vaddr))); |
| 366 | |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 367 | return __pa(vaddr); |
| 368 | } |
| 369 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 370 | static void __init create_pmd_mapping(pmd_t *pmdp, |
| 371 | uintptr_t va, phys_addr_t pa, |
| 372 | phys_addr_t sz, pgprot_t prot) |
| 373 | { |
| 374 | pte_t *ptep; |
| 375 | phys_addr_t pte_phys; |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 376 | uintptr_t pmd_idx = pmd_index(va); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 377 | |
| 378 | if (sz == PMD_SIZE) { |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 379 | if (pmd_none(pmdp[pmd_idx])) |
| 380 | pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pa), prot); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 381 | return; |
| 382 | } |
| 383 | |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 384 | if (pmd_none(pmdp[pmd_idx])) { |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 385 | pte_phys = pt_ops.alloc_pte(va); |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 386 | pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pte_phys), PAGE_TABLE); |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 387 | ptep = pt_ops.get_pte_virt(pte_phys); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 388 | memset(ptep, 0, PAGE_SIZE); |
| 389 | } else { |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 390 | pte_phys = PFN_PHYS(_pmd_pfn(pmdp[pmd_idx])); |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 391 | ptep = pt_ops.get_pte_virt(pte_phys); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | create_pte_mapping(ptep, va, pa, sz, prot); |
| 395 | } |
| 396 | |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 397 | static pud_t *__init get_pud_virt_early(phys_addr_t pa) |
| 398 | { |
| 399 | return (pud_t *)((uintptr_t)pa); |
| 400 | } |
| 401 | |
| 402 | static pud_t *__init get_pud_virt_fixmap(phys_addr_t pa) |
| 403 | { |
| 404 | clear_fixmap(FIX_PUD); |
| 405 | return (pud_t *)set_fixmap_offset(FIX_PUD, pa); |
| 406 | } |
| 407 | |
| 408 | static pud_t *__init get_pud_virt_late(phys_addr_t pa) |
| 409 | { |
| 410 | return (pud_t *)__va(pa); |
| 411 | } |
| 412 | |
| 413 | static phys_addr_t __init alloc_pud_early(uintptr_t va) |
| 414 | { |
| 415 | /* Only one PUD is available for early mapping */ |
| 416 | BUG_ON((va - kernel_map.virt_addr) >> PGDIR_SHIFT); |
| 417 | |
| 418 | return (uintptr_t)early_pud; |
| 419 | } |
| 420 | |
| 421 | static phys_addr_t __init alloc_pud_fixmap(uintptr_t va) |
| 422 | { |
| 423 | return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); |
| 424 | } |
| 425 | |
| 426 | static phys_addr_t alloc_pud_late(uintptr_t va) |
| 427 | { |
| 428 | unsigned long vaddr; |
| 429 | |
| 430 | vaddr = __get_free_page(GFP_KERNEL); |
| 431 | BUG_ON(!vaddr); |
| 432 | return __pa(vaddr); |
| 433 | } |
| 434 | |
| 435 | static void __init create_pud_mapping(pud_t *pudp, |
| 436 | uintptr_t va, phys_addr_t pa, |
| 437 | phys_addr_t sz, pgprot_t prot) |
| 438 | { |
| 439 | pmd_t *nextp; |
| 440 | phys_addr_t next_phys; |
| 441 | uintptr_t pud_index = pud_index(va); |
| 442 | |
| 443 | if (sz == PUD_SIZE) { |
| 444 | if (pud_val(pudp[pud_index]) == 0) |
| 445 | pudp[pud_index] = pfn_pud(PFN_DOWN(pa), prot); |
| 446 | return; |
| 447 | } |
| 448 | |
| 449 | if (pud_val(pudp[pud_index]) == 0) { |
| 450 | next_phys = pt_ops.alloc_pmd(va); |
| 451 | pudp[pud_index] = pfn_pud(PFN_DOWN(next_phys), PAGE_TABLE); |
| 452 | nextp = pt_ops.get_pmd_virt(next_phys); |
| 453 | memset(nextp, 0, PAGE_SIZE); |
| 454 | } else { |
| 455 | next_phys = PFN_PHYS(_pud_pfn(pudp[pud_index])); |
| 456 | nextp = pt_ops.get_pmd_virt(next_phys); |
| 457 | } |
| 458 | |
| 459 | create_pmd_mapping(nextp, va, pa, sz, prot); |
| 460 | } |
| 461 | |
| 462 | #define pgd_next_t pud_t |
| 463 | #define alloc_pgd_next(__va) (pgtable_l4_enabled ? \ |
| 464 | pt_ops.alloc_pud(__va) : pt_ops.alloc_pmd(__va)) |
| 465 | #define get_pgd_next_virt(__pa) (pgtable_l4_enabled ? \ |
| 466 | pt_ops.get_pud_virt(__pa) : (pgd_next_t *)pt_ops.get_pmd_virt(__pa)) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 467 | #define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \ |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 468 | (pgtable_l4_enabled ? \ |
| 469 | create_pud_mapping(__nextp, __va, __pa, __sz, __prot) : \ |
| 470 | create_pmd_mapping((pmd_t *)__nextp, __va, __pa, __sz, __prot)) |
| 471 | #define fixmap_pgd_next (pgtable_l4_enabled ? \ |
| 472 | (uintptr_t)fixmap_pud : (uintptr_t)fixmap_pmd) |
| 473 | #define trampoline_pgd_next (pgtable_l4_enabled ? \ |
| 474 | (uintptr_t)trampoline_pud : (uintptr_t)trampoline_pmd) |
| 475 | #define early_dtb_pgd_next (pgtable_l4_enabled ? \ |
| 476 | (uintptr_t)early_dtb_pud : (uintptr_t)early_dtb_pmd) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 477 | #else |
| 478 | #define pgd_next_t pte_t |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 479 | #define alloc_pgd_next(__va) pt_ops.alloc_pte(__va) |
| 480 | #define get_pgd_next_virt(__pa) pt_ops.get_pte_virt(__pa) |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 481 | #define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \ |
| 482 | create_pte_mapping(__nextp, __va, __pa, __sz, __prot) |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 483 | #define fixmap_pgd_next ((uintptr_t)fixmap_pte) |
| 484 | #define early_dtb_pgd_next ((uintptr_t)early_dtb_pmd) |
| 485 | #define create_pud_mapping(__pmdp, __va, __pa, __sz, __prot) |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 486 | #define create_pmd_mapping(__pmdp, __va, __pa, __sz, __prot) |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 487 | #endif /* __PAGETABLE_PMD_FOLDED */ |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 488 | |
Atish Patra | b91540d | 2020-09-17 15:37:15 -0700 | [diff] [blame] | 489 | void __init create_pgd_mapping(pgd_t *pgdp, |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 490 | uintptr_t va, phys_addr_t pa, |
| 491 | phys_addr_t sz, pgprot_t prot) |
| 492 | { |
| 493 | pgd_next_t *nextp; |
| 494 | phys_addr_t next_phys; |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 495 | uintptr_t pgd_idx = pgd_index(va); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 496 | |
| 497 | if (sz == PGDIR_SIZE) { |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 498 | if (pgd_val(pgdp[pgd_idx]) == 0) |
| 499 | pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(pa), prot); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 500 | return; |
| 501 | } |
| 502 | |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 503 | if (pgd_val(pgdp[pgd_idx]) == 0) { |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 504 | next_phys = alloc_pgd_next(va); |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 505 | pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 506 | nextp = get_pgd_next_virt(next_phys); |
| 507 | memset(nextp, 0, PAGE_SIZE); |
| 508 | } else { |
Mike Rapoport | 974b9b2 | 2020-06-08 21:33:10 -0700 | [diff] [blame] | 509 | next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 510 | nextp = get_pgd_next_virt(next_phys); |
| 511 | } |
| 512 | |
| 513 | create_pgd_next_mapping(nextp, va, pa, sz, prot); |
| 514 | } |
| 515 | |
| 516 | static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) |
| 517 | { |
Zong Li | 0fdc636 | 2019-11-08 01:00:40 -0800 | [diff] [blame] | 518 | /* Upgrade to PMD_SIZE mappings whenever possible */ |
| 519 | if ((base & (PMD_SIZE - 1)) || (size & (PMD_SIZE - 1))) |
| 520 | return PAGE_SIZE; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 521 | |
Zong Li | 0fdc636 | 2019-11-08 01:00:40 -0800 | [diff] [blame] | 522 | return PMD_SIZE; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 523 | } |
| 524 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 525 | #ifdef CONFIG_XIP_KERNEL |
Palmer Dabbelt | 4b1c70a | 2022-02-04 13:13:37 -0800 | [diff] [blame] | 526 | #define phys_ram_base (*(phys_addr_t *)XIP_FIXUP(&phys_ram_base)) |
Jisheng Zhang | 805a3eb | 2021-12-06 23:03:53 +0800 | [diff] [blame] | 527 | extern char _xiprom[], _exiprom[], __data_loc; |
| 528 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 529 | /* called from head.S with MMU off */ |
| 530 | asmlinkage void __init __copy_data(void) |
| 531 | { |
Vitaly Wool | f9ace4e | 2021-10-11 11:14:14 +0200 | [diff] [blame] | 532 | void *from = (void *)(&__data_loc); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 533 | void *to = (void *)CONFIG_PHYS_RAM_BASE; |
Vitaly Wool | f9ace4e | 2021-10-11 11:14:14 +0200 | [diff] [blame] | 534 | size_t sz = (size_t)((uintptr_t)(&_end) - (uintptr_t)(&_sdata)); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 535 | |
| 536 | memcpy(to, from, sz); |
| 537 | } |
| 538 | #endif |
| 539 | |
Alexandre Ghiti | e5c35fa0 | 2021-06-24 14:00:41 +0200 | [diff] [blame] | 540 | #ifdef CONFIG_STRICT_KERNEL_RWX |
| 541 | static __init pgprot_t pgprot_from_va(uintptr_t va) |
| 542 | { |
| 543 | if (is_va_kernel_text(va)) |
| 544 | return PAGE_KERNEL_READ_EXEC; |
| 545 | |
| 546 | /* |
| 547 | * In 64-bit kernel, the kernel mapping is outside the linear mapping so |
| 548 | * we must protect its linear mapping alias from being executed and |
| 549 | * written. |
| 550 | * And rodata section is marked readonly in mark_rodata_ro. |
| 551 | */ |
| 552 | if (IS_ENABLED(CONFIG_64BIT) && is_va_kernel_lm_alias_text(va)) |
| 553 | return PAGE_KERNEL_READ; |
| 554 | |
| 555 | return PAGE_KERNEL; |
| 556 | } |
| 557 | |
| 558 | void mark_rodata_ro(void) |
| 559 | { |
| 560 | set_kernel_memory(__start_rodata, _data, set_memory_ro); |
| 561 | if (IS_ENABLED(CONFIG_64BIT)) |
| 562 | set_kernel_memory(lm_alias(__start_rodata), lm_alias(_data), |
| 563 | set_memory_ro); |
| 564 | |
| 565 | debug_checkwx(); |
| 566 | } |
| 567 | #else |
| 568 | static __init pgprot_t pgprot_from_va(uintptr_t va) |
| 569 | { |
| 570 | if (IS_ENABLED(CONFIG_64BIT) && !is_kernel_mapping(va)) |
| 571 | return PAGE_KERNEL; |
| 572 | |
| 573 | return PAGE_KERNEL_EXEC; |
| 574 | } |
| 575 | #endif /* CONFIG_STRICT_KERNEL_RWX */ |
| 576 | |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 577 | #ifdef CONFIG_64BIT |
| 578 | static void __init disable_pgtable_l4(void) |
| 579 | { |
| 580 | pgtable_l4_enabled = false; |
| 581 | kernel_map.page_offset = PAGE_OFFSET_L3; |
| 582 | satp_mode = SATP_MODE_39; |
| 583 | } |
| 584 | |
| 585 | /* |
| 586 | * There is a simple way to determine if 4-level is supported by the |
| 587 | * underlying hardware: establish 1:1 mapping in 4-level page table mode |
| 588 | * then read SATP to see if the configuration was taken into account |
| 589 | * meaning sv48 is supported. |
| 590 | */ |
| 591 | static __init void set_satp_mode(void) |
| 592 | { |
| 593 | u64 identity_satp, hw_satp; |
| 594 | uintptr_t set_satp_mode_pmd; |
| 595 | |
| 596 | set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; |
| 597 | create_pgd_mapping(early_pg_dir, |
| 598 | set_satp_mode_pmd, (uintptr_t)early_pud, |
| 599 | PGDIR_SIZE, PAGE_TABLE); |
| 600 | create_pud_mapping(early_pud, |
| 601 | set_satp_mode_pmd, (uintptr_t)early_pmd, |
| 602 | PUD_SIZE, PAGE_TABLE); |
| 603 | /* Handle the case where set_satp_mode straddles 2 PMDs */ |
| 604 | create_pmd_mapping(early_pmd, |
| 605 | set_satp_mode_pmd, set_satp_mode_pmd, |
| 606 | PMD_SIZE, PAGE_KERNEL_EXEC); |
| 607 | create_pmd_mapping(early_pmd, |
| 608 | set_satp_mode_pmd + PMD_SIZE, |
| 609 | set_satp_mode_pmd + PMD_SIZE, |
| 610 | PMD_SIZE, PAGE_KERNEL_EXEC); |
| 611 | |
| 612 | identity_satp = PFN_DOWN((uintptr_t)&early_pg_dir) | satp_mode; |
| 613 | |
| 614 | local_flush_tlb_all(); |
| 615 | csr_write(CSR_SATP, identity_satp); |
| 616 | hw_satp = csr_swap(CSR_SATP, 0ULL); |
| 617 | local_flush_tlb_all(); |
| 618 | |
| 619 | if (hw_satp != identity_satp) |
| 620 | disable_pgtable_l4(); |
| 621 | |
| 622 | memset(early_pg_dir, 0, PAGE_SIZE); |
| 623 | memset(early_pud, 0, PAGE_SIZE); |
| 624 | memset(early_pmd, 0, PAGE_SIZE); |
| 625 | } |
| 626 | #endif |
| 627 | |
Anup Patel | 387181d | 2019-03-26 08:03:47 +0000 | [diff] [blame] | 628 | /* |
| 629 | * setup_vm() is called from head.S with MMU-off. |
| 630 | * |
| 631 | * Following requirements should be honoured for setup_vm() to work |
| 632 | * correctly: |
| 633 | * 1) It should use PC-relative addressing for accessing kernel symbols. |
| 634 | * To achieve this we always use GCC cmodel=medany. |
| 635 | * 2) The compiler instrumentation for FTRACE will not work for setup_vm() |
| 636 | * so disable compiler instrumentation when FTRACE is enabled. |
| 637 | * |
| 638 | * Currently, the above requirements are honoured by using custom CFLAGS |
| 639 | * for init.o in mm/Makefile. |
| 640 | */ |
| 641 | |
| 642 | #ifndef __riscv_cmodel_medany |
Paul Walmsley | 6a527b6 | 2019-10-17 14:45:58 -0700 | [diff] [blame] | 643 | #error "setup_vm() is called from head.S before relocate so it should not use absolute addressing." |
Anup Patel | 387181d | 2019-03-26 08:03:47 +0000 | [diff] [blame] | 644 | #endif |
| 645 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 646 | #ifdef CONFIG_XIP_KERNEL |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 647 | static void __init create_kernel_page_table(pgd_t *pgdir, |
Alexandre Ghiti | e5c35fa0 | 2021-06-24 14:00:41 +0200 | [diff] [blame] | 648 | __always_unused bool early) |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 649 | { |
| 650 | uintptr_t va, end_va; |
| 651 | |
| 652 | /* Map the flash resident part */ |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 653 | end_va = kernel_map.virt_addr + kernel_map.xiprom_sz; |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 654 | for (va = kernel_map.virt_addr; va < end_va; va += PMD_SIZE) |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 655 | create_pgd_mapping(pgdir, va, |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 656 | kernel_map.xiprom + (va - kernel_map.virt_addr), |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 657 | PMD_SIZE, PAGE_KERNEL_EXEC); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 658 | |
| 659 | /* Map the data in RAM */ |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 660 | end_va = kernel_map.virt_addr + XIP_OFFSET + kernel_map.size; |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 661 | for (va = kernel_map.virt_addr + XIP_OFFSET; va < end_va; va += PMD_SIZE) |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 662 | create_pgd_mapping(pgdir, va, |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 663 | kernel_map.phys_addr + (va - (kernel_map.virt_addr + XIP_OFFSET)), |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 664 | PMD_SIZE, PAGE_KERNEL); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 665 | } |
| 666 | #else |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 667 | static void __init create_kernel_page_table(pgd_t *pgdir, bool early) |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 668 | { |
| 669 | uintptr_t va, end_va; |
| 670 | |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 671 | end_va = kernel_map.virt_addr + kernel_map.size; |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 672 | for (va = kernel_map.virt_addr; va < end_va; va += PMD_SIZE) |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 673 | create_pgd_mapping(pgdir, va, |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 674 | kernel_map.phys_addr + (va - kernel_map.virt_addr), |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 675 | PMD_SIZE, |
Alexandre Ghiti | e5c35fa0 | 2021-06-24 14:00:41 +0200 | [diff] [blame] | 676 | early ? |
| 677 | PAGE_KERNEL_EXEC : pgprot_from_va(va)); |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 678 | } |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 679 | #endif |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 680 | |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 681 | /* |
| 682 | * Setup a 4MB mapping that encompasses the device tree: for 64-bit kernel, |
| 683 | * this means 2 PMD entries whereas for 32-bit kernel, this is only 1 PGDIR |
| 684 | * entry. |
| 685 | */ |
| 686 | static void __init create_fdt_early_page_table(pgd_t *pgdir, uintptr_t dtb_pa) |
| 687 | { |
| 688 | #ifndef CONFIG_BUILTIN_DTB |
| 689 | uintptr_t pa = dtb_pa & ~(PMD_SIZE - 1); |
| 690 | |
| 691 | create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA, |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 692 | IS_ENABLED(CONFIG_64BIT) ? early_dtb_pgd_next : pa, |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 693 | PGDIR_SIZE, |
| 694 | IS_ENABLED(CONFIG_64BIT) ? PAGE_TABLE : PAGE_KERNEL); |
| 695 | |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 696 | if (pgtable_l4_enabled) { |
| 697 | create_pud_mapping(early_dtb_pud, DTB_EARLY_BASE_VA, |
| 698 | (uintptr_t)early_dtb_pmd, PUD_SIZE, PAGE_TABLE); |
| 699 | } |
| 700 | |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 701 | if (IS_ENABLED(CONFIG_64BIT)) { |
| 702 | create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA, |
| 703 | pa, PMD_SIZE, PAGE_KERNEL); |
| 704 | create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA + PMD_SIZE, |
| 705 | pa + PMD_SIZE, PMD_SIZE, PAGE_KERNEL); |
| 706 | } |
| 707 | |
| 708 | dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PMD_SIZE - 1)); |
| 709 | #else |
| 710 | /* |
| 711 | * For 64-bit kernel, __va can't be used since it would return a linear |
| 712 | * mapping address whereas dtb_early_va will be used before |
| 713 | * setup_vm_final installs the linear mapping. For 32-bit kernel, as the |
| 714 | * kernel is mapped in the linear mapping, that makes no difference. |
| 715 | */ |
| 716 | dtb_early_va = kernel_mapping_pa_to_va(XIP_FIXUP(dtb_pa)); |
| 717 | #endif |
| 718 | |
| 719 | dtb_early_pa = dtb_pa; |
| 720 | } |
| 721 | |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 722 | /* |
| 723 | * MMU is not enabled, the page tables are allocated directly using |
| 724 | * early_pmd/pud/p4d and the address returned is the physical one. |
| 725 | */ |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 726 | void __init pt_ops_set_early(void) |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 727 | { |
| 728 | pt_ops.alloc_pte = alloc_pte_early; |
| 729 | pt_ops.get_pte_virt = get_pte_virt_early; |
| 730 | #ifndef __PAGETABLE_PMD_FOLDED |
| 731 | pt_ops.alloc_pmd = alloc_pmd_early; |
| 732 | pt_ops.get_pmd_virt = get_pmd_virt_early; |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 733 | pt_ops.alloc_pud = alloc_pud_early; |
| 734 | pt_ops.get_pud_virt = get_pud_virt_early; |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 735 | #endif |
| 736 | } |
| 737 | |
| 738 | /* |
| 739 | * MMU is enabled but page table setup is not complete yet. |
| 740 | * fixmap page table alloc functions must be used as a means to temporarily |
| 741 | * map the allocated physical pages since the linear mapping does not exist yet. |
| 742 | * |
| 743 | * Note that this is called with MMU disabled, hence kernel_mapping_pa_to_va, |
| 744 | * but it will be used as described above. |
| 745 | */ |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 746 | void __init pt_ops_set_fixmap(void) |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 747 | { |
| 748 | pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap); |
| 749 | pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap); |
| 750 | #ifndef __PAGETABLE_PMD_FOLDED |
| 751 | pt_ops.alloc_pmd = kernel_mapping_pa_to_va((uintptr_t)alloc_pmd_fixmap); |
| 752 | pt_ops.get_pmd_virt = kernel_mapping_pa_to_va((uintptr_t)get_pmd_virt_fixmap); |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 753 | pt_ops.alloc_pud = kernel_mapping_pa_to_va((uintptr_t)alloc_pud_fixmap); |
| 754 | pt_ops.get_pud_virt = kernel_mapping_pa_to_va((uintptr_t)get_pud_virt_fixmap); |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 755 | #endif |
| 756 | } |
| 757 | |
| 758 | /* |
| 759 | * MMU is enabled and page table setup is complete, so from now, we can use |
| 760 | * generic page allocation functions to setup page table. |
| 761 | */ |
Palmer Dabbelt | 0c34e79 | 2022-01-19 19:23:41 -0800 | [diff] [blame] | 762 | void __init pt_ops_set_late(void) |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 763 | { |
| 764 | pt_ops.alloc_pte = alloc_pte_late; |
| 765 | pt_ops.get_pte_virt = get_pte_virt_late; |
| 766 | #ifndef __PAGETABLE_PMD_FOLDED |
| 767 | pt_ops.alloc_pmd = alloc_pmd_late; |
| 768 | pt_ops.get_pmd_virt = get_pmd_virt_late; |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 769 | pt_ops.alloc_pud = alloc_pud_late; |
| 770 | pt_ops.get_pud_virt = get_pud_virt_late; |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 771 | #endif |
| 772 | } |
| 773 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 774 | asmlinkage void __init setup_vm(uintptr_t dtb_pa) |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 775 | { |
Alexandre Ghiti | 6f3e5fd | 2021-07-23 15:01:26 +0200 | [diff] [blame] | 776 | pmd_t __maybe_unused fix_bmap_spmd, fix_bmap_epmd; |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 777 | |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 778 | kernel_map.virt_addr = KERNEL_LINK_ADDR; |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 779 | kernel_map.page_offset = _AC(CONFIG_PAGE_OFFSET, UL); |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 780 | |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 781 | #ifdef CONFIG_XIP_KERNEL |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 782 | kernel_map.xiprom = (uintptr_t)CONFIG_XIP_PHYS_ADDR; |
| 783 | kernel_map.xiprom_sz = (uintptr_t)(&_exiprom) - (uintptr_t)(&_xiprom); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 784 | |
Alexandre Ghiti | 6d7f91d | 2021-07-21 09:59:35 +0200 | [diff] [blame] | 785 | phys_ram_base = CONFIG_PHYS_RAM_BASE; |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 786 | kernel_map.phys_addr = (uintptr_t)CONFIG_PHYS_RAM_BASE; |
| 787 | kernel_map.size = (uintptr_t)(&_end) - (uintptr_t)(&_sdata); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 788 | |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 789 | kernel_map.va_kernel_xip_pa_offset = kernel_map.virt_addr - kernel_map.xiprom; |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 790 | #else |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 791 | kernel_map.phys_addr = (uintptr_t)(&_start); |
| 792 | kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr; |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 793 | #endif |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 794 | |
| 795 | #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) |
| 796 | set_satp_mode(); |
| 797 | #endif |
| 798 | |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 799 | kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 800 | kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 801 | |
Kenneth Lee | fb31f0a | 2021-07-28 15:15:57 +0800 | [diff] [blame] | 802 | riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr); |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 803 | |
Alexandre Ghiti | f7ae023 | 2021-12-06 11:46:45 +0100 | [diff] [blame] | 804 | /* |
| 805 | * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit |
| 806 | * kernel, whereas for 64-bit kernel, the end of the virtual address |
| 807 | * space is occupied by the modules/BPF/kernel mappings which reduces |
| 808 | * the available size of the linear mapping. |
| 809 | */ |
| 810 | memory_limit = KERN_VIRT_SIZE - (IS_ENABLED(CONFIG_64BIT) ? SZ_4G : 0); |
| 811 | |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 812 | /* Sanity check alignment and size */ |
| 813 | BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0); |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 814 | BUG_ON((kernel_map.phys_addr % PMD_SIZE) != 0); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 815 | |
Alexandre Ghiti | db6b84a | 2021-06-29 11:13:48 +0200 | [diff] [blame] | 816 | #ifdef CONFIG_64BIT |
| 817 | /* |
| 818 | * The last 4K bytes of the addressable memory can not be mapped because |
| 819 | * of IS_ERR_VALUE macro. |
| 820 | */ |
| 821 | BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K); |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 822 | #endif |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 823 | |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 824 | pt_ops_set_early(); |
| 825 | |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 826 | /* Setup early PGD for fixmap */ |
| 827 | create_pgd_mapping(early_pg_dir, FIXADDR_START, |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 828 | fixmap_pgd_next, PGDIR_SIZE, PAGE_TABLE); |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 829 | |
| 830 | #ifndef __PAGETABLE_PMD_FOLDED |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 831 | /* Setup fixmap PUD and PMD */ |
| 832 | if (pgtable_l4_enabled) |
| 833 | create_pud_mapping(fixmap_pud, FIXADDR_START, |
| 834 | (uintptr_t)fixmap_pmd, PUD_SIZE, PAGE_TABLE); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 835 | create_pmd_mapping(fixmap_pmd, FIXADDR_START, |
| 836 | (uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE); |
| 837 | /* Setup trampoline PGD and PMD */ |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 838 | create_pgd_mapping(trampoline_pg_dir, kernel_map.virt_addr, |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 839 | trampoline_pgd_next, PGDIR_SIZE, PAGE_TABLE); |
| 840 | if (pgtable_l4_enabled) |
| 841 | create_pud_mapping(trampoline_pud, kernel_map.virt_addr, |
| 842 | (uintptr_t)trampoline_pmd, PUD_SIZE, PAGE_TABLE); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 843 | #ifdef CONFIG_XIP_KERNEL |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 844 | create_pmd_mapping(trampoline_pmd, kernel_map.virt_addr, |
| 845 | kernel_map.xiprom, PMD_SIZE, PAGE_KERNEL_EXEC); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 846 | #else |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 847 | create_pmd_mapping(trampoline_pmd, kernel_map.virt_addr, |
| 848 | kernel_map.phys_addr, PMD_SIZE, PAGE_KERNEL_EXEC); |
Vitaly Wool | 44c9225 | 2021-04-13 02:35:14 -0400 | [diff] [blame] | 849 | #endif |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 850 | #else |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 851 | /* Setup trampoline PGD */ |
Alexandre Ghiti | 658e2c5 | 2021-06-17 15:53:07 +0200 | [diff] [blame] | 852 | create_pgd_mapping(trampoline_pg_dir, kernel_map.virt_addr, |
| 853 | kernel_map.phys_addr, PGDIR_SIZE, PAGE_KERNEL_EXEC); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 854 | #endif |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 855 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 856 | /* |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 857 | * Setup early PGD covering entire kernel which will allow |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 858 | * us to reach paging_init(). We map all memory banks later |
| 859 | * in setup_vm_final() below. |
| 860 | */ |
Alexandre Ghiti | 526f83d | 2021-07-23 15:01:25 +0200 | [diff] [blame] | 861 | create_kernel_page_table(early_pg_dir, true); |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 862 | |
Alexandre Ghiti | fe45ffa | 2021-07-23 15:01:28 +0200 | [diff] [blame] | 863 | /* Setup early mapping for FDT early scan */ |
| 864 | create_fdt_early_page_table(early_pg_dir, dtb_pa); |
Atish Patra | 6262f66 | 2020-09-17 15:37:11 -0700 | [diff] [blame] | 865 | |
| 866 | /* |
| 867 | * Bootime fixmap only can handle PMD_SIZE mapping. Thus, boot-ioremap |
| 868 | * range can not span multiple pmds. |
| 869 | */ |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 870 | BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT) |
Atish Patra | 6262f66 | 2020-09-17 15:37:11 -0700 | [diff] [blame] | 871 | != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT)); |
| 872 | |
| 873 | #ifndef __PAGETABLE_PMD_FOLDED |
| 874 | /* |
| 875 | * Early ioremap fixmap is already created as it lies within first 2MB |
| 876 | * of fixmap region. We always map PMD_SIZE. Thus, both FIX_BTMAP_END |
| 877 | * FIX_BTMAP_BEGIN should lie in the same pmd. Verify that and warn |
| 878 | * the user if not. |
| 879 | */ |
| 880 | fix_bmap_spmd = fixmap_pmd[pmd_index(__fix_to_virt(FIX_BTMAP_BEGIN))]; |
| 881 | fix_bmap_epmd = fixmap_pmd[pmd_index(__fix_to_virt(FIX_BTMAP_END))]; |
| 882 | if (pmd_val(fix_bmap_spmd) != pmd_val(fix_bmap_epmd)) { |
| 883 | WARN_ON(1); |
| 884 | pr_warn("fixmap btmap start [%08lx] != end [%08lx]\n", |
| 885 | pmd_val(fix_bmap_spmd), pmd_val(fix_bmap_epmd)); |
| 886 | pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n", |
| 887 | fix_to_virt(FIX_BTMAP_BEGIN)); |
| 888 | pr_warn("fix_to_virt(FIX_BTMAP_END): %08lx\n", |
| 889 | fix_to_virt(FIX_BTMAP_END)); |
| 890 | |
| 891 | pr_warn("FIX_BTMAP_END: %d\n", FIX_BTMAP_END); |
| 892 | pr_warn("FIX_BTMAP_BEGIN: %d\n", FIX_BTMAP_BEGIN); |
| 893 | } |
| 894 | #endif |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 895 | |
| 896 | pt_ops_set_fixmap(); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 897 | } |
| 898 | |
| 899 | static void __init setup_vm_final(void) |
| 900 | { |
| 901 | uintptr_t va, map_size; |
| 902 | phys_addr_t pa, start, end; |
Mike Rapoport | b10d6bc | 2020-10-13 16:58:08 -0700 | [diff] [blame] | 903 | u64 i; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 904 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 905 | /* Setup swapper PGD for fixmap */ |
| 906 | create_pgd_mapping(swapper_pg_dir, FIXADDR_START, |
Zong Li | ac51e00 | 2020-01-02 11:12:40 +0800 | [diff] [blame] | 907 | __pa_symbol(fixmap_pgd_next), |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 908 | PGDIR_SIZE, PAGE_TABLE); |
| 909 | |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 910 | /* Map all memory banks in the linear mapping */ |
Mike Rapoport | b10d6bc | 2020-10-13 16:58:08 -0700 | [diff] [blame] | 911 | for_each_mem_range(i, &start, &end) { |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 912 | if (start >= end) |
| 913 | break; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 914 | if (start <= __pa(PAGE_OFFSET) && |
| 915 | __pa(PAGE_OFFSET) < end) |
| 916 | start = __pa(PAGE_OFFSET); |
Alexandre Ghiti | c99127c | 2021-06-29 11:13:47 +0200 | [diff] [blame] | 917 | if (end >= __pa(PAGE_OFFSET) + memory_limit) |
| 918 | end = __pa(PAGE_OFFSET) + memory_limit; |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 919 | |
| 920 | map_size = best_map_size(start, end - start); |
| 921 | for (pa = start; pa < end; pa += map_size) { |
| 922 | va = (uintptr_t)__va(pa); |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 923 | |
Alexandre Ghiti | e5c35fa0 | 2021-06-24 14:00:41 +0200 | [diff] [blame] | 924 | create_pgd_mapping(swapper_pg_dir, va, pa, map_size, |
| 925 | pgprot_from_va(va)); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 926 | } |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 927 | } |
Anup Patel | f2c17aa | 2019-01-07 20:57:01 +0530 | [diff] [blame] | 928 | |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 929 | /* Map the kernel */ |
Jisheng Zhang | 07aabe8 | 2021-12-06 23:03:50 +0800 | [diff] [blame] | 930 | if (IS_ENABLED(CONFIG_64BIT)) |
| 931 | create_kernel_page_table(swapper_pg_dir, false); |
Alexandre Ghiti | 2bfc6cd | 2021-04-11 12:41:44 -0400 | [diff] [blame] | 932 | |
Alexandre Ghiti | 2efad17 | 2021-12-06 11:46:46 +0100 | [diff] [blame] | 933 | #ifdef CONFIG_KASAN |
| 934 | kasan_swapper_init(); |
| 935 | #endif |
| 936 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 937 | /* Clear fixmap PTE and PMD mappings */ |
| 938 | clear_fixmap(FIX_PTE); |
| 939 | clear_fixmap(FIX_PMD); |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 940 | clear_fixmap(FIX_PUD); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 941 | |
| 942 | /* Move to swapper page table */ |
Alexandre Ghiti | e8a62cc | 2021-12-06 11:46:51 +0100 | [diff] [blame] | 943 | csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | satp_mode); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 944 | local_flush_tlb_all(); |
Atish Patra | e8dcb61 | 2020-09-17 15:37:12 -0700 | [diff] [blame] | 945 | |
Alexandre Ghiti | 840125a | 2021-12-06 11:46:47 +0100 | [diff] [blame] | 946 | pt_ops_set_late(); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 947 | } |
Christoph Hellwig | 6bd33e1 | 2019-10-28 13:10:41 +0100 | [diff] [blame] | 948 | #else |
| 949 | asmlinkage void __init setup_vm(uintptr_t dtb_pa) |
| 950 | { |
| 951 | dtb_early_va = (void *)dtb_pa; |
Atish Patra | a78c6f5 | 2020-10-01 12:04:56 -0700 | [diff] [blame] | 952 | dtb_early_pa = dtb_pa; |
Christoph Hellwig | 6bd33e1 | 2019-10-28 13:10:41 +0100 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | static inline void setup_vm_final(void) |
| 956 | { |
| 957 | } |
| 958 | #endif /* CONFIG_MMU */ |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 959 | |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 960 | #ifdef CONFIG_KEXEC_CORE |
| 961 | /* |
| 962 | * reserve_crashkernel() - reserves memory for crash kernel |
| 963 | * |
| 964 | * This function reserves memory area given in "crashkernel=" kernel command |
| 965 | * line parameter. The memory reserved is used by dump capture kernel when |
| 966 | * primary kernel is crashing. |
| 967 | */ |
| 968 | static void __init reserve_crashkernel(void) |
| 969 | { |
| 970 | unsigned long long crash_base = 0; |
| 971 | unsigned long long crash_size = 0; |
| 972 | unsigned long search_start = memblock_start_of_DRAM(); |
| 973 | unsigned long search_end = memblock_end_of_DRAM(); |
| 974 | |
| 975 | int ret = 0; |
| 976 | |
Nick Kossifidis | 5640975 | 2021-04-19 03:55:39 +0300 | [diff] [blame] | 977 | /* |
| 978 | * Don't reserve a region for a crash kernel on a crash kernel |
| 979 | * since it doesn't make much sense and we have limited memory |
| 980 | * resources. |
| 981 | */ |
Nick Kossifidis | 5640975 | 2021-04-19 03:55:39 +0300 | [diff] [blame] | 982 | if (is_kdump_kernel()) { |
| 983 | pr_info("crashkernel: ignoring reservation request\n"); |
| 984 | return; |
| 985 | } |
Nick Kossifidis | 5640975 | 2021-04-19 03:55:39 +0300 | [diff] [blame] | 986 | |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 987 | ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(), |
| 988 | &crash_size, &crash_base); |
| 989 | if (ret || !crash_size) |
| 990 | return; |
| 991 | |
| 992 | crash_size = PAGE_ALIGN(crash_size); |
| 993 | |
Mike Rapoport | a7259df | 2021-09-02 15:00:26 -0700 | [diff] [blame] | 994 | if (crash_base) { |
| 995 | search_start = crash_base; |
| 996 | search_end = crash_base + crash_size; |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 997 | } |
Mike Rapoport | a7259df | 2021-09-02 15:00:26 -0700 | [diff] [blame] | 998 | |
| 999 | /* |
| 1000 | * Current riscv boot protocol requires 2MB alignment for |
| 1001 | * RV64 and 4MB alignment for RV32 (hugepage size) |
Nick Kossifidis | decf89f | 2021-11-26 20:04:11 +0200 | [diff] [blame] | 1002 | * |
| 1003 | * Try to alloc from 32bit addressible physical memory so that |
| 1004 | * swiotlb can work on the crash kernel. |
Mike Rapoport | a7259df | 2021-09-02 15:00:26 -0700 | [diff] [blame] | 1005 | */ |
| 1006 | crash_base = memblock_phys_alloc_range(crash_size, PMD_SIZE, |
Nick Kossifidis | decf89f | 2021-11-26 20:04:11 +0200 | [diff] [blame] | 1007 | search_start, |
| 1008 | min(search_end, (unsigned long) SZ_4G)); |
Mike Rapoport | a7259df | 2021-09-02 15:00:26 -0700 | [diff] [blame] | 1009 | if (crash_base == 0) { |
Nick Kossifidis | decf89f | 2021-11-26 20:04:11 +0200 | [diff] [blame] | 1010 | /* Try again without restricting region to 32bit addressible memory */ |
| 1011 | crash_base = memblock_phys_alloc_range(crash_size, PMD_SIZE, |
| 1012 | search_start, search_end); |
| 1013 | if (crash_base == 0) { |
| 1014 | pr_warn("crashkernel: couldn't allocate %lldKB\n", |
| 1015 | crash_size >> 10); |
| 1016 | return; |
| 1017 | } |
Mike Rapoport | a7259df | 2021-09-02 15:00:26 -0700 | [diff] [blame] | 1018 | } |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 1019 | |
| 1020 | pr_info("crashkernel: reserved 0x%016llx - 0x%016llx (%lld MB)\n", |
| 1021 | crash_base, crash_base + crash_size, crash_size >> 20); |
| 1022 | |
| 1023 | crashk_res.start = crash_base; |
| 1024 | crashk_res.end = crash_base + crash_size - 1; |
| 1025 | } |
| 1026 | #endif /* CONFIG_KEXEC_CORE */ |
| 1027 | |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 1028 | void __init paging_init(void) |
| 1029 | { |
Kefeng Wang | f842f5f | 2021-05-10 19:42:22 +0800 | [diff] [blame] | 1030 | setup_bootmem(); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 1031 | setup_vm_final(); |
Atish Patra | cbd34f4 | 2020-11-18 16:38:27 -0800 | [diff] [blame] | 1032 | } |
| 1033 | |
| 1034 | void __init misc_mem_init(void) |
| 1035 | { |
Kefeng Wang | f6e5aed | 2021-02-25 14:54:17 +0800 | [diff] [blame] | 1036 | early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT); |
Atish Patra | 4f0e8ee | 2020-11-18 16:38:29 -0800 | [diff] [blame] | 1037 | arch_numa_init(); |
Atish Patra | cbd34f4 | 2020-11-18 16:38:27 -0800 | [diff] [blame] | 1038 | sparse_init(); |
Anup Patel | 671f9a3 | 2019-06-28 13:36:21 -0700 | [diff] [blame] | 1039 | zone_sizes_init(); |
Nick Kossifidis | e53d281 | 2021-04-19 03:55:38 +0300 | [diff] [blame] | 1040 | #ifdef CONFIG_KEXEC_CORE |
| 1041 | reserve_crashkernel(); |
| 1042 | #endif |
Atish Patra | 4f0e8ee | 2020-11-18 16:38:29 -0800 | [diff] [blame] | 1043 | memblock_dump_all(); |
Anup Patel | 6f1e9e9 | 2019-02-13 16:38:36 +0530 | [diff] [blame] | 1044 | } |
Logan Gunthorpe | d95f1a5 | 2019-08-28 15:40:54 -0600 | [diff] [blame] | 1045 | |
Kefeng Wang | 9fe57d8 | 2019-10-23 11:23:02 +0800 | [diff] [blame] | 1046 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
Logan Gunthorpe | d95f1a5 | 2019-08-28 15:40:54 -0600 | [diff] [blame] | 1047 | int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, |
| 1048 | struct vmem_altmap *altmap) |
| 1049 | { |
Anshuman Khandual | 1d9cfee | 2020-08-06 23:23:19 -0700 | [diff] [blame] | 1050 | return vmemmap_populate_basepages(start, end, node, NULL); |
Logan Gunthorpe | d95f1a5 | 2019-08-28 15:40:54 -0600 | [diff] [blame] | 1051 | } |
| 1052 | #endif |