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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnese5747e32014-06-12 08:35:47 -070030#include <linux/acpi.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010031#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/vt.h>
42#include <acpi/video.h>
43
David Howells760285e2012-10-02 18:01:07 +010044#include <drm/drmP.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010045#include <drm/drm_crtc_helper.h>
Maarten Lankhorsta667fb42016-12-15 15:29:44 +010046#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010047#include <drm/i915_drm.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010048
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030050#include "i915_trace.h"
Chris Wilson0673ad42016-06-24 14:00:22 +010051#include "i915_vgpu.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070052#include "intel_drv.h"
Anusha Srivatsa5464cd62017-01-18 08:05:58 -080053#include "intel_uc.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
Kristian Høgsberg112b7152009-01-04 16:55:33 -050055static struct drm_driver driver;
56
Chris Wilson0673ad42016-06-24 14:00:22 +010057static unsigned int i915_load_fail_count;
58
59bool __i915_inject_load_failure(const char *func, int line)
60{
Michal Wajdeczko4f044a82017-09-19 19:38:44 +000061 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
Chris Wilson0673ad42016-06-24 14:00:22 +010062 return false;
63
Michal Wajdeczko4f044a82017-09-19 19:38:44 +000064 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
Chris Wilson0673ad42016-06-24 14:00:22 +010065 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
Michal Wajdeczko4f044a82017-09-19 19:38:44 +000066 i915_modparams.inject_load_failure, func, line);
Chris Wilson0673ad42016-06-24 14:00:22 +010067 return true;
68 }
69
70 return false;
71}
72
73#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
76
77void
78__i915_printk(struct drm_i915_private *dev_priv, const char *level,
79 const char *fmt, ...)
80{
81 static bool shown_bug_once;
David Weinehallc49d13e2016-08-22 13:32:42 +030082 struct device *kdev = dev_priv->drm.dev;
Chris Wilson0673ad42016-06-24 14:00:22 +010083 bool is_error = level[1] <= KERN_ERR[1];
84 bool is_debug = level[1] == KERN_DEBUG[1];
85 struct va_format vaf;
86 va_list args;
87
88 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
89 return;
90
91 va_start(args, fmt);
92
93 vaf.fmt = fmt;
94 vaf.va = &args;
95
David Weinehallc49d13e2016-08-22 13:32:42 +030096 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
Chris Wilson0673ad42016-06-24 14:00:22 +010097 __builtin_return_address(0), &vaf);
98
99 if (is_error && !shown_bug_once) {
David Weinehallc49d13e2016-08-22 13:32:42 +0300100 dev_notice(kdev, "%s", FDO_BUG_MSG);
Chris Wilson0673ad42016-06-24 14:00:22 +0100101 shown_bug_once = true;
102 }
103
104 va_end(args);
105}
106
107static bool i915_error_injected(struct drm_i915_private *dev_priv)
108{
Michal Wajdeczko4f044a82017-09-19 19:38:44 +0000109 return i915_modparams.inject_load_failure &&
110 i915_load_fail_count == i915_modparams.inject_load_failure;
Chris Wilson0673ad42016-06-24 14:00:22 +0100111}
112
113#define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
116 fmt, ##__VA_ARGS__)
117
118
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100119static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
Robert Beckett30c964a2015-08-28 13:10:22 +0100120{
121 enum intel_pch ret = PCH_NOP;
122
123 /*
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
128 */
129
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100130 if (IS_GEN5(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100131 ret = PCH_IBX;
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100133 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100134 ret = PCH_CPT;
Ville Syrjäläaa032132017-06-20 16:03:07 +0300135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100136 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100137 ret = PCH_LPT;
Xiong Zhang817aef52017-06-15 11:11:45 +0800138 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
139 dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
140 else
141 dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
Robert Beckett30c964a2015-08-28 13:10:22 +0100142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100143 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100144 ret = PCH_SPT;
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
Rodrigo Vivi80937812017-06-08 08:49:59 -0700146 } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
Rodrigo Viviacf1dba2017-06-06 13:30:31 -0700147 ret = PCH_CNP;
Rodrigo Vivi80937812017-06-08 08:49:59 -0700148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
Robert Beckett30c964a2015-08-28 13:10:22 +0100149 }
150
151 return ret;
152}
153
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000154static void intel_detect_pch(struct drm_i915_private *dev_priv)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800155{
Imre Deakbcdb72a2014-02-14 20:23:54 +0200156 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800157
Ben Widawskyce1bb322013-04-05 13:12:44 -0700158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
160 */
Tvrtko Ursulinb7f05d42016-11-09 11:30:45 +0000161 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
Ben Widawskyce1bb322013-04-05 13:12:44 -0700162 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700163 return;
164 }
165
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800166 /*
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800171 *
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800176 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200177 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800178 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200179 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Ville Syrjäläc5e855d2017-06-21 20:49:44 +0300180
181 dev_priv->pch_id = id;
Dhinakaran Pandiyanec7e0bb2017-06-02 13:06:40 -0700182
Jesse Barnes90711d52011-04-28 14:48:02 -0700183 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
184 dev_priv->pch_type = PCH_IBX;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Tvrtko Ursulin5db94012016-10-13 11:03:10 +0100186 WARN_ON(!IS_GEN5(dev_priv));
Jesse Barnes90711d52011-04-28 14:48:02 -0700187 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800188 dev_priv->pch_type = PCH_CPT;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Ville Syrjäläd4cdbf02017-06-20 16:03:09 +0300190 WARN_ON(!IS_GEN6(dev_priv) &&
191 !IS_IVYBRIDGE(dev_priv));
Jesse Barnesc7925132011-04-07 12:33:56 -0700192 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
193 /* PantherPoint is CPT compatible */
194 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Ville Syrjäläd4cdbf02017-06-20 16:03:09 +0300196 WARN_ON(!IS_GEN6(dev_priv) &&
197 !IS_IVYBRIDGE(dev_priv));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300198 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
199 dev_priv->pch_type = PCH_LPT;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100201 WARN_ON(!IS_HASWELL(dev_priv) &&
202 !IS_BROADWELL(dev_priv));
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100203 WARN_ON(IS_HSW_ULT(dev_priv) ||
204 IS_BDW_ULT(dev_priv));
Ben Widawskye76e0632013-11-07 21:40:41 -0800205 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
206 dev_priv->pch_type = PCH_LPT;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100208 WARN_ON(!IS_HASWELL(dev_priv) &&
209 !IS_BROADWELL(dev_priv));
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100210 WARN_ON(!IS_HSW_ULT(dev_priv) &&
211 !IS_BDW_ULT(dev_priv));
Ville Syrjäläc5e855d2017-06-21 20:49:44 +0300212 } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv->pch_type = PCH_LPT;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv) &&
217 !IS_BROADWELL(dev_priv));
218 WARN_ON(IS_HSW_ULT(dev_priv) ||
219 IS_BDW_ULT(dev_priv));
220 } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv->pch_type = PCH_LPT;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv) &&
225 !IS_BROADWELL(dev_priv));
226 WARN_ON(!IS_HSW_ULT(dev_priv) &&
227 !IS_BDW_ULT(dev_priv));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530228 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
229 dev_priv->pch_type = PCH_SPT;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
Tvrtko Ursulin08537232016-10-13 11:03:02 +0100231 WARN_ON(!IS_SKYLAKE(dev_priv) &&
232 !IS_KABYLAKE(dev_priv));
Ville Syrjäläc5e855d2017-06-21 20:49:44 +0300233 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530234 dev_priv->pch_type = PCH_SPT;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
Tvrtko Ursulin08537232016-10-13 11:03:02 +0100236 WARN_ON(!IS_SKYLAKE(dev_priv) &&
237 !IS_KABYLAKE(dev_priv));
Rodrigo Vivi22dea0b2016-07-01 17:07:12 -0700238 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
239 dev_priv->pch_type = PCH_KBP;
Rodrigo Vivi23247d72017-07-31 11:52:20 -0700240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
Jani Nikula85327742017-02-01 15:46:09 +0200241 WARN_ON(!IS_SKYLAKE(dev_priv) &&
Rodrigo Vivieb371932017-08-21 16:50:56 -0700242 !IS_KABYLAKE(dev_priv) &&
243 !IS_COFFEELAKE(dev_priv));
Rodrigo Vivi7b22b8c2017-06-02 13:06:39 -0700244 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
245 dev_priv->pch_type = PCH_CNP;
Rodrigo Vivi23247d72017-07-31 11:52:20 -0700246 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
Rodrigo Vivi80937812017-06-08 08:49:59 -0700247 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
248 !IS_COFFEELAKE(dev_priv));
Ville Syrjäläc5e855d2017-06-21 20:49:44 +0300249 } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
Dhinakaran Pandiyanec7e0bb2017-06-02 13:06:40 -0700250 dev_priv->pch_type = PCH_CNP;
Rodrigo Vivi23247d72017-07-31 11:52:20 -0700251 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
Rodrigo Vivi80937812017-06-08 08:49:59 -0700252 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
253 !IS_COFFEELAKE(dev_priv));
Ville Syrjäläd4cdbf02017-06-20 16:03:09 +0300254 } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
255 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
256 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
Gerd Hoffmann94bb4892016-06-13 14:38:56 +0200257 pch->subsystem_vendor ==
258 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
259 pch->subsystem_device ==
260 PCI_SUBDEVICE_ID_QEMU)) {
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100261 dev_priv->pch_type =
262 intel_virt_detect_pch(dev_priv);
Imre Deakbcdb72a2014-02-14 20:23:54 +0200263 } else
264 continue;
265
Rui Guo6a9c4b32013-06-19 21:10:23 +0800266 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800267 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800268 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800269 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200270 DRM_DEBUG_KMS("No PCH found.\n");
271
272 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800273}
274
Chris Wilson0673ad42016-06-24 14:00:22 +0100275static int i915_getparam(struct drm_device *dev, void *data,
276 struct drm_file *file_priv)
277{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100278 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +0300279 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100280 drm_i915_getparam_t *param = data;
281 int value;
282
283 switch (param->param) {
284 case I915_PARAM_IRQ_ACTIVE:
285 case I915_PARAM_ALLOW_BATCHBUFFER:
286 case I915_PARAM_LAST_DISPATCH:
Kenneth Graunkeef0f4112017-02-15 01:34:46 -0800287 case I915_PARAM_HAS_EXEC_CONSTANTS:
Chris Wilson0673ad42016-06-24 14:00:22 +0100288 /* Reject all old ums/dri params. */
289 return -ENODEV;
290 case I915_PARAM_CHIPSET_ID:
David Weinehall52a05c32016-08-22 13:32:44 +0300291 value = pdev->device;
Chris Wilson0673ad42016-06-24 14:00:22 +0100292 break;
293 case I915_PARAM_REVISION:
David Weinehall52a05c32016-08-22 13:32:44 +0300294 value = pdev->revision;
Chris Wilson0673ad42016-06-24 14:00:22 +0100295 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100296 case I915_PARAM_NUM_FENCES_AVAIL:
297 value = dev_priv->num_fence_regs;
298 break;
299 case I915_PARAM_HAS_OVERLAY:
300 value = dev_priv->overlay ? 1 : 0;
301 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100302 case I915_PARAM_HAS_BSD:
Akash Goel3b3f1652016-10-13 22:44:48 +0530303 value = !!dev_priv->engine[VCS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100304 break;
305 case I915_PARAM_HAS_BLT:
Akash Goel3b3f1652016-10-13 22:44:48 +0530306 value = !!dev_priv->engine[BCS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100307 break;
308 case I915_PARAM_HAS_VEBOX:
Akash Goel3b3f1652016-10-13 22:44:48 +0530309 value = !!dev_priv->engine[VECS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100310 break;
311 case I915_PARAM_HAS_BSD2:
Akash Goel3b3f1652016-10-13 22:44:48 +0530312 value = !!dev_priv->engine[VCS2];
Chris Wilson0673ad42016-06-24 14:00:22 +0100313 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100314 case I915_PARAM_HAS_LLC:
David Weinehall16162472016-09-02 13:46:17 +0300315 value = HAS_LLC(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100316 break;
317 case I915_PARAM_HAS_WT:
David Weinehall16162472016-09-02 13:46:17 +0300318 value = HAS_WT(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100319 break;
320 case I915_PARAM_HAS_ALIASING_PPGTT:
David Weinehall16162472016-09-02 13:46:17 +0300321 value = USES_PPGTT(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100322 break;
323 case I915_PARAM_HAS_SEMAPHORES:
Michal Wajdeczko4f044a82017-09-19 19:38:44 +0000324 value = i915_modparams.semaphores;
Chris Wilson0673ad42016-06-24 14:00:22 +0100325 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100326 case I915_PARAM_HAS_SECURE_BATCHES:
327 value = capable(CAP_SYS_ADMIN);
328 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100329 case I915_PARAM_CMD_PARSER_VERSION:
330 value = i915_cmd_parser_get_version(dev_priv);
331 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100332 case I915_PARAM_SUBSLICE_TOTAL:
Imre Deak57ec1712016-08-31 19:13:05 +0300333 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
Chris Wilson0673ad42016-06-24 14:00:22 +0100334 if (!value)
335 return -ENODEV;
336 break;
337 case I915_PARAM_EU_TOTAL:
Imre Deak43b67992016-08-31 19:13:02 +0300338 value = INTEL_INFO(dev_priv)->sseu.eu_total;
Chris Wilson0673ad42016-06-24 14:00:22 +0100339 if (!value)
340 return -ENODEV;
341 break;
342 case I915_PARAM_HAS_GPU_RESET:
Michal Wajdeczko4f044a82017-09-19 19:38:44 +0000343 value = i915_modparams.enable_hangcheck &&
344 intel_has_gpu_reset(dev_priv);
Michel Thierry142bc7d2017-06-20 10:57:46 +0100345 if (value && intel_has_reset_engine(dev_priv))
346 value = 2;
Chris Wilson0673ad42016-06-24 14:00:22 +0100347 break;
348 case I915_PARAM_HAS_RESOURCE_STREAMER:
David Weinehall16162472016-09-02 13:46:17 +0300349 value = HAS_RESOURCE_STREAMER(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100350 break;
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100351 case I915_PARAM_HAS_POOLED_EU:
David Weinehall16162472016-09-02 13:46:17 +0300352 value = HAS_POOLED_EU(dev_priv);
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100353 break;
354 case I915_PARAM_MIN_EU_IN_POOL:
Imre Deak43b67992016-08-31 19:13:02 +0300355 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100356 break;
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800357 case I915_PARAM_HUC_STATUS:
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +0530358 intel_runtime_pm_get(dev_priv);
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800359 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +0530360 intel_runtime_pm_put(dev_priv);
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800361 break;
Chris Wilson4cc69072016-08-25 19:05:19 +0100362 case I915_PARAM_MMAP_GTT_VERSION:
363 /* Though we've started our numbering from 1, and so class all
364 * earlier versions as 0, in effect their value is undefined as
365 * the ioctl will report EINVAL for the unknown param!
366 */
367 value = i915_gem_mmap_gtt_version();
368 break;
Chris Wilson0de91362016-11-14 20:41:01 +0000369 case I915_PARAM_HAS_SCHEDULER:
Chris Wilsonbf64e0b2017-10-03 21:34:51 +0100370 value = 0;
Chris Wilsonbeecec92017-10-03 21:34:52 +0100371 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
Chris Wilsonbf64e0b2017-10-03 21:34:51 +0100372 value |= I915_SCHEDULER_CAP_ENABLED;
Chris Wilsonac14fbd2017-10-03 21:34:53 +0100373 value |= I915_SCHEDULER_CAP_PRIORITY;
Chris Wilsonbeecec92017-10-03 21:34:52 +0100374
Michał Winiarskia4598d12017-10-25 22:00:18 +0200375 if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
Michał Winiarskic41937fd2017-10-26 15:35:58 +0200376 i915_modparams.enable_execlists)
Chris Wilsonbeecec92017-10-03 21:34:52 +0100377 value |= I915_SCHEDULER_CAP_PREEMPTION;
378 }
Chris Wilson0de91362016-11-14 20:41:01 +0000379 break;
Chris Wilsonbeecec92017-10-03 21:34:52 +0100380
David Weinehall16162472016-09-02 13:46:17 +0300381 case I915_PARAM_MMAP_VERSION:
382 /* Remember to bump this if the version changes! */
383 case I915_PARAM_HAS_GEM:
384 case I915_PARAM_HAS_PAGEFLIPPING:
385 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
386 case I915_PARAM_HAS_RELAXED_FENCING:
387 case I915_PARAM_HAS_COHERENT_RINGS:
388 case I915_PARAM_HAS_RELAXED_DELTA:
389 case I915_PARAM_HAS_GEN7_SOL_RESET:
390 case I915_PARAM_HAS_WAIT_TIMEOUT:
391 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
392 case I915_PARAM_HAS_PINNED_BATCHES:
393 case I915_PARAM_HAS_EXEC_NO_RELOC:
394 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
395 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
396 case I915_PARAM_HAS_EXEC_SOFTPIN:
Chris Wilson77ae9952017-01-27 09:40:07 +0000397 case I915_PARAM_HAS_EXEC_ASYNC:
Chris Wilsonfec04452017-01-27 09:40:08 +0000398 case I915_PARAM_HAS_EXEC_FENCE:
Chris Wilsonb0fd47a2017-04-15 10:39:02 +0100399 case I915_PARAM_HAS_EXEC_CAPTURE:
Chris Wilson1a71cf22017-06-16 15:05:23 +0100400 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
Jason Ekstrandcf6e7ba2017-08-15 15:57:33 +0100401 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
David Weinehall16162472016-09-02 13:46:17 +0300402 /* For the time being all of these are always true;
403 * if some supported hardware does not have one of these
404 * features this value needs to be provided from
405 * INTEL_INFO(), a feature macro, or similar.
406 */
407 value = 1;
408 break;
Chris Wilsond2b4b972017-11-10 14:26:33 +0000409 case I915_PARAM_HAS_CONTEXT_ISOLATION:
410 value = intel_engines_has_context_isolation(dev_priv);
411 break;
Robert Bragg7fed5552017-06-13 12:22:59 +0100412 case I915_PARAM_SLICE_MASK:
413 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
414 if (!value)
415 return -ENODEV;
416 break;
Robert Braggf5320232017-06-13 12:23:00 +0100417 case I915_PARAM_SUBSLICE_MASK:
418 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
419 if (!value)
420 return -ENODEV;
421 break;
Lionel Landwerlindab91782017-11-10 19:08:44 +0000422 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
423 value = INTEL_INFO(dev_priv)->cs_timestamp_frequency;
424 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100425 default:
426 DRM_DEBUG("Unknown parameter %d\n", param->param);
427 return -EINVAL;
428 }
429
Chris Wilsondda33002016-06-24 14:00:23 +0100430 if (put_user(value, param->value))
Chris Wilson0673ad42016-06-24 14:00:22 +0100431 return -EFAULT;
Chris Wilson0673ad42016-06-24 14:00:22 +0100432
433 return 0;
434}
435
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000436static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100437{
Chris Wilson0673ad42016-06-24 14:00:22 +0100438 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
439 if (!dev_priv->bridge_dev) {
440 DRM_ERROR("bridge device not found\n");
441 return -1;
442 }
443 return 0;
444}
445
446/* Allocate space for the MCH regs if needed, return nonzero on error */
447static int
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000448intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100449{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000450 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100451 u32 temp_lo, temp_hi = 0;
452 u64 mchbar_addr;
453 int ret;
454
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000455 if (INTEL_GEN(dev_priv) >= 4)
Chris Wilson0673ad42016-06-24 14:00:22 +0100456 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
457 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
458 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
459
460 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
461#ifdef CONFIG_PNP
462 if (mchbar_addr &&
463 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
464 return 0;
465#endif
466
467 /* Get some space for it */
468 dev_priv->mch_res.name = "i915 MCHBAR";
469 dev_priv->mch_res.flags = IORESOURCE_MEM;
470 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
471 &dev_priv->mch_res,
472 MCHBAR_SIZE, MCHBAR_SIZE,
473 PCIBIOS_MIN_MEM,
474 0, pcibios_align_resource,
475 dev_priv->bridge_dev);
476 if (ret) {
477 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
478 dev_priv->mch_res.start = 0;
479 return ret;
480 }
481
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000482 if (INTEL_GEN(dev_priv) >= 4)
Chris Wilson0673ad42016-06-24 14:00:22 +0100483 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
484 upper_32_bits(dev_priv->mch_res.start));
485
486 pci_write_config_dword(dev_priv->bridge_dev, reg,
487 lower_32_bits(dev_priv->mch_res.start));
488 return 0;
489}
490
491/* Setup MCHBAR if possible, return true if we should disable it again */
492static void
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000493intel_setup_mchbar(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100494{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000495 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100496 u32 temp;
497 bool enabled;
498
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100499 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +0100500 return;
501
502 dev_priv->mchbar_need_disable = false;
503
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100504 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100505 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
506 enabled = !!(temp & DEVEN_MCHBAR_EN);
507 } else {
508 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
509 enabled = temp & 1;
510 }
511
512 /* If it's already enabled, don't have to do anything */
513 if (enabled)
514 return;
515
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000516 if (intel_alloc_mchbar_resource(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +0100517 return;
518
519 dev_priv->mchbar_need_disable = true;
520
521 /* Space is allocated or reserved, so enable it. */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100522 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100523 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
524 temp | DEVEN_MCHBAR_EN);
525 } else {
526 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
527 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
528 }
529}
530
531static void
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000532intel_teardown_mchbar(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100533{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000534 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100535
536 if (dev_priv->mchbar_need_disable) {
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100537 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100538 u32 deven_val;
539
540 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
541 &deven_val);
542 deven_val &= ~DEVEN_MCHBAR_EN;
543 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
544 deven_val);
545 } else {
546 u32 mchbar_val;
547
548 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
549 &mchbar_val);
550 mchbar_val &= ~1;
551 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
552 mchbar_val);
553 }
554 }
555
556 if (dev_priv->mch_res.start)
557 release_resource(&dev_priv->mch_res);
558}
559
560/* true = enable decode, false = disable decoder */
561static unsigned int i915_vga_set_decode(void *cookie, bool state)
562{
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000563 struct drm_i915_private *dev_priv = cookie;
Chris Wilson0673ad42016-06-24 14:00:22 +0100564
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000565 intel_modeset_vga_set_state(dev_priv, state);
Chris Wilson0673ad42016-06-24 14:00:22 +0100566 if (state)
567 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
568 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
569 else
570 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
571}
572
Tvrtko Ursulin7f26cb82016-12-01 14:16:41 +0000573static int i915_resume_switcheroo(struct drm_device *dev);
574static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
575
Chris Wilson0673ad42016-06-24 14:00:22 +0100576static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
577{
578 struct drm_device *dev = pci_get_drvdata(pdev);
579 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
580
581 if (state == VGA_SWITCHEROO_ON) {
582 pr_info("switched on\n");
583 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
584 /* i915 resume handler doesn't set to D0 */
David Weinehall52a05c32016-08-22 13:32:44 +0300585 pci_set_power_state(pdev, PCI_D0);
Chris Wilson0673ad42016-06-24 14:00:22 +0100586 i915_resume_switcheroo(dev);
587 dev->switch_power_state = DRM_SWITCH_POWER_ON;
588 } else {
589 pr_info("switched off\n");
590 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
591 i915_suspend_switcheroo(dev, pmm);
592 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
593 }
594}
595
596static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
597{
598 struct drm_device *dev = pci_get_drvdata(pdev);
599
600 /*
601 * FIXME: open_count is protected by drm_global_mutex but that would lead to
602 * locking inversion with the driver load path. And the access here is
603 * completely racy anyway. So don't bother with locking for now.
604 */
605 return dev->open_count == 0;
606}
607
608static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
609 .set_gpu_state = i915_switcheroo_set_state,
610 .reprobe = NULL,
611 .can_switch = i915_switcheroo_can_switch,
612};
613
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100614static void i915_gem_fini(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100615{
Chris Wilson3b19f162017-07-18 14:41:24 +0100616 /* Flush any outstanding unpin_work. */
617 i915_gem_drain_workqueue(dev_priv);
Chris Wilson5f09a9c2017-06-20 12:05:46 +0100618
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100619 mutex_lock(&dev_priv->drm.struct_mutex);
Oscar Mateob8991402017-03-28 09:53:47 -0700620 intel_uc_fini_hw(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000621 i915_gem_cleanup_engines(dev_priv);
Chris Wilson829a0af2017-06-20 12:05:45 +0100622 i915_gem_contexts_fini(dev_priv);
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100623 mutex_unlock(&dev_priv->drm.struct_mutex);
Chris Wilson0673ad42016-06-24 14:00:22 +0100624
Chris Wilson7c781422017-10-11 15:18:57 +0100625 i915_gem_cleanup_userptr(dev_priv);
626
Chris Wilsonbdeb9782016-12-23 14:57:56 +0000627 i915_gem_drain_freed_objects(dev_priv);
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100628
Chris Wilson829a0af2017-06-20 12:05:45 +0100629 WARN_ON(!list_empty(&dev_priv->contexts.list));
Chris Wilson0673ad42016-06-24 14:00:22 +0100630}
631
632static int i915_load_modeset_init(struct drm_device *dev)
633{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100634 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +0300635 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100636 int ret;
637
638 if (i915_inject_load_failure())
639 return -ENODEV;
640
Jani Nikula66578852017-03-10 15:27:57 +0200641 intel_bios_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100642
643 /* If we have > 1 VGA cards, then we need to arbitrate access
644 * to the common VGA resources.
645 *
646 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
647 * then we do not take part in VGA arbitration and the
648 * vga_client_register() fails with -ENODEV.
649 */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000650 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
Chris Wilson0673ad42016-06-24 14:00:22 +0100651 if (ret && ret != -ENODEV)
652 goto out;
653
654 intel_register_dsm_handler();
655
David Weinehall52a05c32016-08-22 13:32:44 +0300656 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
Chris Wilson0673ad42016-06-24 14:00:22 +0100657 if (ret)
658 goto cleanup_vga_client;
659
660 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
661 intel_update_rawclk(dev_priv);
662
663 intel_power_domains_init_hw(dev_priv, false);
664
665 intel_csr_ucode_init(dev_priv);
666
667 ret = intel_irq_install(dev_priv);
668 if (ret)
669 goto cleanup_csr;
670
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000671 intel_setup_gmbus(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100672
673 /* Important: The output setup functions called by modeset_init need
674 * working irqs for e.g. gmbus and dp aux transfers. */
Ville Syrjäläb079bd172016-10-25 18:58:02 +0300675 ret = intel_modeset_init(dev);
676 if (ret)
677 goto cleanup_irq;
Chris Wilson0673ad42016-06-24 14:00:22 +0100678
Arkadiusz Hiler29ad6a32017-03-14 15:28:09 +0100679 intel_uc_init_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100680
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +0000681 ret = i915_gem_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100682 if (ret)
Oscar Mateo3950bf32017-03-22 10:39:46 -0700683 goto cleanup_uc;
Chris Wilson0673ad42016-06-24 14:00:22 +0100684
Chris Wilsond378a3e2017-11-10 14:26:31 +0000685 intel_setup_overlay(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100686
Tvrtko Ursulinb7f05d42016-11-09 11:30:45 +0000687 if (INTEL_INFO(dev_priv)->num_pipes == 0)
Chris Wilson0673ad42016-06-24 14:00:22 +0100688 return 0;
689
690 ret = intel_fbdev_init(dev);
691 if (ret)
692 goto cleanup_gem;
693
694 /* Only enable hotplug handling once the fbdev is fully set up. */
695 intel_hpd_init(dev_priv);
696
697 drm_kms_helper_poll_init(dev);
698
699 return 0;
700
701cleanup_gem:
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +0000702 if (i915_gem_suspend(dev_priv))
Imre Deak1c777c52016-10-12 17:46:37 +0300703 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100704 i915_gem_fini(dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -0700705cleanup_uc:
706 intel_uc_fini_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100707cleanup_irq:
Chris Wilson0673ad42016-06-24 14:00:22 +0100708 drm_irq_uninstall(dev);
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000709 intel_teardown_gmbus(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100710cleanup_csr:
711 intel_csr_ucode_fini(dev_priv);
712 intel_power_domains_fini(dev_priv);
David Weinehall52a05c32016-08-22 13:32:44 +0300713 vga_switcheroo_unregister_client(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +0100714cleanup_vga_client:
David Weinehall52a05c32016-08-22 13:32:44 +0300715 vga_client_register(pdev, NULL, NULL, NULL);
Chris Wilson0673ad42016-06-24 14:00:22 +0100716out:
717 return ret;
718}
719
Chris Wilson0673ad42016-06-24 14:00:22 +0100720static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
721{
722 struct apertures_struct *ap;
Chris Wilson91c8a322016-07-05 10:40:23 +0100723 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100724 struct i915_ggtt *ggtt = &dev_priv->ggtt;
725 bool primary;
726 int ret;
727
728 ap = alloc_apertures(1);
729 if (!ap)
730 return -ENOMEM;
731
732 ap->ranges[0].base = ggtt->mappable_base;
733 ap->ranges[0].size = ggtt->mappable_end;
734
735 primary =
736 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
737
Daniel Vetter44adece2016-08-10 18:52:34 +0200738 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
Chris Wilson0673ad42016-06-24 14:00:22 +0100739
740 kfree(ap);
741
742 return ret;
743}
Chris Wilson0673ad42016-06-24 14:00:22 +0100744
745#if !defined(CONFIG_VGA_CONSOLE)
746static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
747{
748 return 0;
749}
750#elif !defined(CONFIG_DUMMY_CONSOLE)
751static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
752{
753 return -ENODEV;
754}
755#else
756static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
757{
758 int ret = 0;
759
760 DRM_INFO("Replacing VGA console driver\n");
761
762 console_lock();
763 if (con_is_bound(&vga_con))
764 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
765 if (ret == 0) {
766 ret = do_unregister_con_driver(&vga_con);
767
768 /* Ignore "already unregistered". */
769 if (ret == -ENODEV)
770 ret = 0;
771 }
772 console_unlock();
773
774 return ret;
775}
776#endif
777
Chris Wilson0673ad42016-06-24 14:00:22 +0100778static void intel_init_dpio(struct drm_i915_private *dev_priv)
779{
780 /*
781 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
782 * CHV x1 PHY (DP/HDMI D)
783 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
784 */
785 if (IS_CHERRYVIEW(dev_priv)) {
786 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
787 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
788 } else if (IS_VALLEYVIEW(dev_priv)) {
789 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
790 }
791}
792
793static int i915_workqueues_init(struct drm_i915_private *dev_priv)
794{
795 /*
796 * The i915 workqueue is primarily used for batched retirement of
797 * requests (and thus managing bo) once the task has been completed
798 * by the GPU. i915_gem_retire_requests() is called directly when we
799 * need high-priority retirement, such as waiting for an explicit
800 * bo.
801 *
802 * It is also used for periodic low-priority events, such as
803 * idle-timers and recording error state.
804 *
805 * All tasks on the workqueue are expected to acquire the dev mutex
806 * so there is no point in running more than one instance of the
807 * workqueue at any time. Use an ordered one.
808 */
809 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
810 if (dev_priv->wq == NULL)
811 goto out_err;
812
813 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
814 if (dev_priv->hotplug.dp_wq == NULL)
815 goto out_free_wq;
816
Chris Wilson0673ad42016-06-24 14:00:22 +0100817 return 0;
818
Chris Wilson0673ad42016-06-24 14:00:22 +0100819out_free_wq:
820 destroy_workqueue(dev_priv->wq);
821out_err:
822 DRM_ERROR("Failed to allocate workqueues.\n");
823
824 return -ENOMEM;
825}
826
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000827static void i915_engines_cleanup(struct drm_i915_private *i915)
828{
829 struct intel_engine_cs *engine;
830 enum intel_engine_id id;
831
832 for_each_engine(engine, i915, id)
833 kfree(engine);
834}
835
Chris Wilson0673ad42016-06-24 14:00:22 +0100836static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
837{
Chris Wilson0673ad42016-06-24 14:00:22 +0100838 destroy_workqueue(dev_priv->hotplug.dp_wq);
839 destroy_workqueue(dev_priv->wq);
840}
841
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300842/*
843 * We don't keep the workarounds for pre-production hardware, so we expect our
844 * driver to fail on these machines in one way or another. A little warning on
845 * dmesg may help both the user and the bug triagers.
846 */
847static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
848{
Chris Wilson248a1242017-01-30 10:44:56 +0000849 bool pre = false;
850
851 pre |= IS_HSW_EARLY_SDV(dev_priv);
852 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
Chris Wilson0102ba12017-01-30 10:44:58 +0000853 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
Chris Wilson248a1242017-01-30 10:44:56 +0000854
Chris Wilson7c5ff4a2017-01-30 10:44:57 +0000855 if (pre) {
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300856 DRM_ERROR("This is a pre-production stepping. "
857 "It may not be fully functional.\n");
Chris Wilson7c5ff4a2017-01-30 10:44:57 +0000858 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
859 }
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300860}
861
Chris Wilson0673ad42016-06-24 14:00:22 +0100862/**
863 * i915_driver_init_early - setup state not requiring device access
864 * @dev_priv: device private
865 *
866 * Initialize everything that is a "SW-only" state, that is state not
867 * requiring accessing the device or exposing the driver via kernel internal
868 * or userspace interfaces. Example steps belonging here: lock initialization,
869 * system memory allocation, setting up device specific attributes and
870 * function hooks not requiring accessing the device.
871 */
872static int i915_driver_init_early(struct drm_i915_private *dev_priv,
873 const struct pci_device_id *ent)
874{
875 const struct intel_device_info *match_info =
876 (struct intel_device_info *)ent->driver_data;
877 struct intel_device_info *device_info;
878 int ret = 0;
879
880 if (i915_inject_load_failure())
881 return -ENODEV;
882
883 /* Setup the write-once "constant" device info */
Chris Wilson94b4f3b2016-07-05 10:40:20 +0100884 device_info = mkwrite_device_info(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100885 memcpy(device_info, match_info, sizeof(*device_info));
886 device_info->device_id = dev_priv->drm.pdev->device;
887
Tvrtko Ursulinae7617f2017-09-27 17:41:38 +0100888 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
889 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
890 device_info->platform_mask = BIT(device_info->platform);
891
Chris Wilson0673ad42016-06-24 14:00:22 +0100892 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
893 device_info->gen_mask = BIT(device_info->gen - 1);
894
895 spin_lock_init(&dev_priv->irq_lock);
896 spin_lock_init(&dev_priv->gpu_error.lock);
897 mutex_init(&dev_priv->backlight_lock);
898 spin_lock_init(&dev_priv->uncore.lock);
Lyude317eaa92017-02-03 21:18:25 -0500899
Chris Wilson0673ad42016-06-24 14:00:22 +0100900 mutex_init(&dev_priv->sb_lock);
901 mutex_init(&dev_priv->modeset_restore_lock);
902 mutex_init(&dev_priv->av_mutex);
903 mutex_init(&dev_priv->wm.wm_mutex);
904 mutex_init(&dev_priv->pps_mutex);
905
Arkadiusz Hiler413e8fd2016-11-25 18:59:36 +0100906 intel_uc_init_early(dev_priv);
Chris Wilson0b1de5d2016-08-12 12:39:59 +0100907 i915_memcpy_init_early(dev_priv);
908
Chris Wilson0673ad42016-06-24 14:00:22 +0100909 ret = i915_workqueues_init(dev_priv);
910 if (ret < 0)
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000911 goto err_engines;
Chris Wilson0673ad42016-06-24 14:00:22 +0100912
Chris Wilson0673ad42016-06-24 14:00:22 +0100913 /* This must be called before any calls to HAS_PCH_* */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000914 intel_detect_pch(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100915
Tvrtko Ursulin192aa182016-12-01 14:16:45 +0000916 intel_pm_setup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100917 intel_init_dpio(dev_priv);
918 intel_power_domains_init(dev_priv);
919 intel_irq_init(dev_priv);
Mika Kuoppala3ac168a2016-11-01 18:43:03 +0200920 intel_hangcheck_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100921 intel_init_display_hooks(dev_priv);
922 intel_init_clock_gating_hooks(dev_priv);
923 intel_init_audio_hooks(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000924 ret = i915_gem_load_init(dev_priv);
Chris Wilson73cb9702016-10-28 13:58:46 +0100925 if (ret < 0)
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300926 goto err_irq;
Chris Wilson0673ad42016-06-24 14:00:22 +0100927
David Weinehall36cdd012016-08-22 13:59:31 +0300928 intel_display_crc_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100929
Chris Wilson94b4f3b2016-07-05 10:40:20 +0100930 intel_device_info_dump(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100931
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300932 intel_detect_preproduction_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100933
Robert Braggeec688e2016-11-07 19:49:47 +0000934 i915_perf_init(dev_priv);
935
Chris Wilson0673ad42016-06-24 14:00:22 +0100936 return 0;
937
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300938err_irq:
939 intel_irq_fini(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100940 i915_workqueues_cleanup(dev_priv);
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000941err_engines:
942 i915_engines_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100943 return ret;
944}
945
946/**
947 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
948 * @dev_priv: device private
949 */
950static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
951{
Robert Braggeec688e2016-11-07 19:49:47 +0000952 i915_perf_fini(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000953 i915_gem_load_cleanup(dev_priv);
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300954 intel_irq_fini(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100955 i915_workqueues_cleanup(dev_priv);
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000956 i915_engines_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100957}
958
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000959static int i915_mmio_setup(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100960{
David Weinehall52a05c32016-08-22 13:32:44 +0300961 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100962 int mmio_bar;
963 int mmio_size;
964
Tvrtko Ursulin5db94012016-10-13 11:03:10 +0100965 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
Chris Wilson0673ad42016-06-24 14:00:22 +0100966 /*
967 * Before gen4, the registers and the GTT are behind different BARs.
968 * However, from gen4 onwards, the registers and the GTT are shared
969 * in the same BAR, so we want to restrict this ioremap from
970 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
971 * the register BAR remains the same size for all the earlier
972 * generations up to Ironlake.
973 */
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000974 if (INTEL_GEN(dev_priv) < 5)
Chris Wilson0673ad42016-06-24 14:00:22 +0100975 mmio_size = 512 * 1024;
976 else
977 mmio_size = 2 * 1024 * 1024;
David Weinehall52a05c32016-08-22 13:32:44 +0300978 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
Chris Wilson0673ad42016-06-24 14:00:22 +0100979 if (dev_priv->regs == NULL) {
980 DRM_ERROR("failed to map registers\n");
981
982 return -EIO;
983 }
984
985 /* Try to make sure MCHBAR is enabled before poking at it */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000986 intel_setup_mchbar(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100987
988 return 0;
989}
990
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000991static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100992{
David Weinehall52a05c32016-08-22 13:32:44 +0300993 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100994
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000995 intel_teardown_mchbar(dev_priv);
David Weinehall52a05c32016-08-22 13:32:44 +0300996 pci_iounmap(pdev, dev_priv->regs);
Chris Wilson0673ad42016-06-24 14:00:22 +0100997}
998
999/**
1000 * i915_driver_init_mmio - setup device MMIO
1001 * @dev_priv: device private
1002 *
1003 * Setup minimal device state necessary for MMIO accesses later in the
1004 * initialization sequence. The setup here should avoid any other device-wide
1005 * side effects or exposing the driver via kernel internal or user space
1006 * interfaces.
1007 */
1008static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1009{
Chris Wilson0673ad42016-06-24 14:00:22 +01001010 int ret;
1011
1012 if (i915_inject_load_failure())
1013 return -ENODEV;
1014
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +00001015 if (i915_get_bridge_dev(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +01001016 return -EIO;
1017
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +00001018 ret = i915_mmio_setup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001019 if (ret < 0)
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03001020 goto err_bridge;
Chris Wilson0673ad42016-06-24 14:00:22 +01001021
1022 intel_uncore_init(dev_priv);
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03001023
Sagar Arun Kamble1fc556f2017-10-04 15:33:24 +00001024 intel_uc_init_mmio(dev_priv);
1025
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03001026 ret = intel_engines_init_mmio(dev_priv);
1027 if (ret)
1028 goto err_uncore;
1029
Chris Wilson24145512017-01-24 11:01:35 +00001030 i915_gem_init_mmio(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001031
1032 return 0;
1033
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03001034err_uncore:
1035 intel_uncore_fini(dev_priv);
1036err_bridge:
Chris Wilson0673ad42016-06-24 14:00:22 +01001037 pci_dev_put(dev_priv->bridge_dev);
1038
1039 return ret;
1040}
1041
1042/**
1043 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1044 * @dev_priv: device private
1045 */
1046static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1047{
Chris Wilson0673ad42016-06-24 14:00:22 +01001048 intel_uncore_fini(dev_priv);
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +00001049 i915_mmio_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001050 pci_dev_put(dev_priv->bridge_dev);
1051}
1052
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001053static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1054{
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001055 i915_modparams.enable_execlists =
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001056 intel_sanitize_enable_execlists(dev_priv,
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001057 i915_modparams.enable_execlists);
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001058
1059 /*
1060 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1061 * user's requested state against the hardware/driver capabilities. We
1062 * do this now so that we can print out any log messages once rather
1063 * than every time we check intel_enable_ppgtt().
1064 */
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001065 i915_modparams.enable_ppgtt =
1066 intel_sanitize_enable_ppgtt(dev_priv,
1067 i915_modparams.enable_ppgtt);
1068 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
Chris Wilson39df9192016-07-20 13:31:57 +01001069
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001070 i915_modparams.semaphores =
1071 intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
1072 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1073 yesno(i915_modparams.semaphores));
Arkadiusz Hilerd2be9f22017-03-14 15:28:10 +01001074
1075 intel_uc_sanitize_options(dev_priv);
Chuanxiao Dong67b7f332017-05-27 17:44:17 +08001076
1077 intel_gvt_sanitize_options(dev_priv);
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001078}
1079
Chris Wilson0673ad42016-06-24 14:00:22 +01001080/**
1081 * i915_driver_init_hw - setup state requiring device access
1082 * @dev_priv: device private
1083 *
1084 * Setup state that requires accessing the device, but doesn't require
1085 * exposing the driver via kernel internal or userspace interfaces.
1086 */
1087static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1088{
David Weinehall52a05c32016-08-22 13:32:44 +03001089 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001090 int ret;
1091
1092 if (i915_inject_load_failure())
1093 return -ENODEV;
1094
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001095 intel_device_info_runtime_init(dev_priv);
1096
1097 intel_sanitize_options(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001098
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001099 ret = i915_ggtt_probe_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001100 if (ret)
1101 return ret;
1102
Chris Wilson0673ad42016-06-24 14:00:22 +01001103 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1104 * otherwise the vga fbdev driver falls over. */
1105 ret = i915_kick_out_firmware_fb(dev_priv);
1106 if (ret) {
1107 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1108 goto out_ggtt;
1109 }
1110
1111 ret = i915_kick_out_vgacon(dev_priv);
1112 if (ret) {
1113 DRM_ERROR("failed to remove conflicting VGA console\n");
1114 goto out_ggtt;
1115 }
1116
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001117 ret = i915_ggtt_init_hw(dev_priv);
Chris Wilson0088e522016-08-04 07:52:21 +01001118 if (ret)
1119 return ret;
1120
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001121 ret = i915_ggtt_enable_hw(dev_priv);
Chris Wilson0088e522016-08-04 07:52:21 +01001122 if (ret) {
1123 DRM_ERROR("failed to enable GGTT\n");
1124 goto out_ggtt;
1125 }
1126
David Weinehall52a05c32016-08-22 13:32:44 +03001127 pci_set_master(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001128
1129 /* overlay on gen2 is broken and can't address above 1G */
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01001130 if (IS_GEN2(dev_priv)) {
David Weinehall52a05c32016-08-22 13:32:44 +03001131 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
Chris Wilson0673ad42016-06-24 14:00:22 +01001132 if (ret) {
1133 DRM_ERROR("failed to set DMA mask\n");
1134
1135 goto out_ggtt;
1136 }
1137 }
1138
Chris Wilson0673ad42016-06-24 14:00:22 +01001139 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1140 * using 32bit addressing, overwriting memory if HWS is located
1141 * above 4GB.
1142 *
1143 * The documentation also mentions an issue with undefined
1144 * behaviour if any general state is accessed within a page above 4GB,
1145 * which also needs to be handled carefully.
1146 */
Jani Nikulac0f86832016-12-07 12:13:04 +02001147 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
David Weinehall52a05c32016-08-22 13:32:44 +03001148 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
Chris Wilson0673ad42016-06-24 14:00:22 +01001149
1150 if (ret) {
1151 DRM_ERROR("failed to set DMA mask\n");
1152
1153 goto out_ggtt;
1154 }
1155 }
1156
Chris Wilson0673ad42016-06-24 14:00:22 +01001157 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1158 PM_QOS_DEFAULT_VALUE);
1159
1160 intel_uncore_sanitize(dev_priv);
1161
1162 intel_opregion_setup(dev_priv);
1163
1164 i915_gem_load_init_fences(dev_priv);
1165
1166 /* On the 945G/GM, the chipset reports the MSI capability on the
1167 * integrated graphics even though the support isn't actually there
1168 * according to the published specs. It doesn't appear to function
1169 * correctly in testing on 945G.
1170 * This may be a side effect of MSI having been made available for PEG
1171 * and the registers being closely associated.
1172 *
1173 * According to chipset errata, on the 965GM, MSI interrupts may
Ville Syrjäläe38c2da2017-06-26 23:30:51 +03001174 * be lost or delayed, and was defeatured. MSI interrupts seem to
1175 * get lost on g4x as well, and interrupt delivery seems to stay
1176 * properly dead afterwards. So we'll just disable them for all
1177 * pre-gen5 chipsets.
Chris Wilson0673ad42016-06-24 14:00:22 +01001178 */
Ville Syrjäläe38c2da2017-06-26 23:30:51 +03001179 if (INTEL_GEN(dev_priv) >= 5) {
David Weinehall52a05c32016-08-22 13:32:44 +03001180 if (pci_enable_msi(pdev) < 0)
Chris Wilson0673ad42016-06-24 14:00:22 +01001181 DRM_DEBUG_DRIVER("can't enable MSI");
1182 }
1183
Zhenyu Wang26f837e2017-01-13 10:46:09 +08001184 ret = intel_gvt_init(dev_priv);
1185 if (ret)
1186 goto out_ggtt;
1187
Chris Wilson0673ad42016-06-24 14:00:22 +01001188 return 0;
1189
1190out_ggtt:
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001191 i915_ggtt_cleanup_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001192
1193 return ret;
1194}
1195
1196/**
1197 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1198 * @dev_priv: device private
1199 */
1200static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1201{
David Weinehall52a05c32016-08-22 13:32:44 +03001202 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001203
David Weinehall52a05c32016-08-22 13:32:44 +03001204 if (pdev->msi_enabled)
1205 pci_disable_msi(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001206
1207 pm_qos_remove_request(&dev_priv->pm_qos);
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001208 i915_ggtt_cleanup_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001209}
1210
1211/**
1212 * i915_driver_register - register the driver with the rest of the system
1213 * @dev_priv: device private
1214 *
1215 * Perform any steps necessary to make the driver available via kernel
1216 * internal or userspace interfaces.
1217 */
1218static void i915_driver_register(struct drm_i915_private *dev_priv)
1219{
Chris Wilson91c8a322016-07-05 10:40:23 +01001220 struct drm_device *dev = &dev_priv->drm;
Chris Wilson0673ad42016-06-24 14:00:22 +01001221
1222 i915_gem_shrinker_init(dev_priv);
1223
1224 /*
1225 * Notify a valid surface after modesetting,
1226 * when running inside a VM.
1227 */
1228 if (intel_vgpu_active(dev_priv))
1229 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1230
1231 /* Reveal our presence to userspace */
1232 if (drm_dev_register(dev, 0) == 0) {
1233 i915_debugfs_register(dev_priv);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +00001234 i915_guc_log_register(dev_priv);
David Weinehall694c2822016-08-22 13:32:43 +03001235 i915_setup_sysfs(dev_priv);
Robert Bragg442b8c02016-11-07 19:49:53 +00001236
1237 /* Depends on sysfs having been initialized */
1238 i915_perf_register(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001239 } else
1240 DRM_ERROR("Failed to register driver for userspace access!\n");
1241
1242 if (INTEL_INFO(dev_priv)->num_pipes) {
1243 /* Must be done after probing outputs */
1244 intel_opregion_register(dev_priv);
1245 acpi_video_register();
1246 }
1247
1248 if (IS_GEN5(dev_priv))
1249 intel_gpu_ips_init(dev_priv);
1250
Jerome Anandeef57322017-01-25 04:27:49 +05301251 intel_audio_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001252
1253 /*
1254 * Some ports require correctly set-up hpd registers for detection to
1255 * work properly (leading to ghost connected connector status), e.g. VGA
1256 * on gm45. Hence we can only set up the initial fbdev config after hpd
1257 * irqs are fully enabled. We do it last so that the async config
1258 * cannot run before the connectors are registered.
1259 */
1260 intel_fbdev_initial_config_async(dev);
1261}
1262
1263/**
1264 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1265 * @dev_priv: device private
1266 */
1267static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1268{
Daniel Vetter4f256d82017-07-15 00:46:55 +02001269 intel_fbdev_unregister(dev_priv);
Jerome Anandeef57322017-01-25 04:27:49 +05301270 intel_audio_deinit(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001271
1272 intel_gpu_ips_teardown();
1273 acpi_video_unregister();
1274 intel_opregion_unregister(dev_priv);
1275
Robert Bragg442b8c02016-11-07 19:49:53 +00001276 i915_perf_unregister(dev_priv);
1277
David Weinehall694c2822016-08-22 13:32:43 +03001278 i915_teardown_sysfs(dev_priv);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +00001279 i915_guc_log_unregister(dev_priv);
Chris Wilson91c8a322016-07-05 10:40:23 +01001280 drm_dev_unregister(&dev_priv->drm);
Chris Wilson0673ad42016-06-24 14:00:22 +01001281
1282 i915_gem_shrinker_cleanup(dev_priv);
1283}
1284
1285/**
1286 * i915_driver_load - setup chip and create an initial config
Joonas Lahtinend2ad3ae2016-11-10 15:36:34 +02001287 * @pdev: PCI device
1288 * @ent: matching PCI ID entry
Chris Wilson0673ad42016-06-24 14:00:22 +01001289 *
1290 * The driver load routine has to do several things:
1291 * - drive output discovery via intel_modeset_init()
1292 * - initialize the memory manager
1293 * - allocate initial config memory
1294 * - setup the DRM framebuffer with the allocated memory
1295 */
Chris Wilson42f55512016-06-24 14:00:26 +01001296int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
Chris Wilson0673ad42016-06-24 14:00:22 +01001297{
Maarten Lankhorst8d2b47d2017-02-02 08:41:42 +01001298 const struct intel_device_info *match_info =
1299 (struct intel_device_info *)ent->driver_data;
Chris Wilson0673ad42016-06-24 14:00:22 +01001300 struct drm_i915_private *dev_priv;
1301 int ret;
1302
Ville Syrjäläff4c3b72017-03-03 17:19:28 +02001303 /* Enable nuclear pageflip on ILK+ */
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001304 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
Maarten Lankhorst8d2b47d2017-02-02 08:41:42 +01001305 driver.driver_features &= ~DRIVER_ATOMIC;
Chris Wilsona09d0ba2016-06-24 14:00:27 +01001306
Chris Wilson0673ad42016-06-24 14:00:22 +01001307 ret = -ENOMEM;
1308 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1309 if (dev_priv)
1310 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1311 if (ret) {
Tvrtko Ursulin87a67522016-12-06 19:04:13 +00001312 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
Chris Wilsoncad36882017-02-10 16:35:21 +00001313 goto out_free;
Chris Wilson0673ad42016-06-24 14:00:22 +01001314 }
1315
Chris Wilson0673ad42016-06-24 14:00:22 +01001316 dev_priv->drm.pdev = pdev;
1317 dev_priv->drm.dev_private = dev_priv;
Chris Wilson0673ad42016-06-24 14:00:22 +01001318
1319 ret = pci_enable_device(pdev);
1320 if (ret)
Chris Wilsoncad36882017-02-10 16:35:21 +00001321 goto out_fini;
Chris Wilson0673ad42016-06-24 14:00:22 +01001322
1323 pci_set_drvdata(pdev, &dev_priv->drm);
Imre Deakadfdf852017-05-02 15:04:09 +03001324 /*
1325 * Disable the system suspend direct complete optimization, which can
1326 * leave the device suspended skipping the driver's suspend handlers
1327 * if the device was already runtime suspended. This is needed due to
1328 * the difference in our runtime and system suspend sequence and
1329 * becaue the HDA driver may require us to enable the audio power
1330 * domain during system suspend.
1331 */
1332 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
Chris Wilson0673ad42016-06-24 14:00:22 +01001333
1334 ret = i915_driver_init_early(dev_priv, ent);
1335 if (ret < 0)
1336 goto out_pci_disable;
1337
1338 intel_runtime_pm_get(dev_priv);
1339
1340 ret = i915_driver_init_mmio(dev_priv);
1341 if (ret < 0)
1342 goto out_runtime_pm_put;
1343
1344 ret = i915_driver_init_hw(dev_priv);
1345 if (ret < 0)
1346 goto out_cleanup_mmio;
1347
1348 /*
1349 * TODO: move the vblank init and parts of modeset init steps into one
1350 * of the i915_driver_init_/i915_driver_register functions according
1351 * to the role/effect of the given init step.
1352 */
1353 if (INTEL_INFO(dev_priv)->num_pipes) {
Chris Wilson91c8a322016-07-05 10:40:23 +01001354 ret = drm_vblank_init(&dev_priv->drm,
Chris Wilson0673ad42016-06-24 14:00:22 +01001355 INTEL_INFO(dev_priv)->num_pipes);
1356 if (ret)
1357 goto out_cleanup_hw;
1358 }
1359
Chris Wilson91c8a322016-07-05 10:40:23 +01001360 ret = i915_load_modeset_init(&dev_priv->drm);
Chris Wilson0673ad42016-06-24 14:00:22 +01001361 if (ret < 0)
Daniel Vetterbaf54382017-06-21 10:28:41 +02001362 goto out_cleanup_hw;
Chris Wilson0673ad42016-06-24 14:00:22 +01001363
1364 i915_driver_register(dev_priv);
1365
1366 intel_runtime_pm_enable(dev_priv);
1367
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05301368 intel_init_ipc(dev_priv);
Mahesh Kumara3a89862016-12-01 21:19:34 +05301369
Chris Wilson0525a062016-10-14 14:27:07 +01001370 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1371 DRM_INFO("DRM_I915_DEBUG enabled\n");
1372 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1373 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
Chris Wilsonbc5ca472016-08-25 08:23:14 +01001374
Chris Wilson0673ad42016-06-24 14:00:22 +01001375 intel_runtime_pm_put(dev_priv);
1376
1377 return 0;
1378
Chris Wilson0673ad42016-06-24 14:00:22 +01001379out_cleanup_hw:
1380 i915_driver_cleanup_hw(dev_priv);
1381out_cleanup_mmio:
1382 i915_driver_cleanup_mmio(dev_priv);
1383out_runtime_pm_put:
1384 intel_runtime_pm_put(dev_priv);
1385 i915_driver_cleanup_early(dev_priv);
1386out_pci_disable:
1387 pci_disable_device(pdev);
Chris Wilsoncad36882017-02-10 16:35:21 +00001388out_fini:
Chris Wilson0673ad42016-06-24 14:00:22 +01001389 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
Chris Wilsoncad36882017-02-10 16:35:21 +00001390 drm_dev_fini(&dev_priv->drm);
1391out_free:
1392 kfree(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001393 return ret;
1394}
1395
Chris Wilson42f55512016-06-24 14:00:26 +01001396void i915_driver_unload(struct drm_device *dev)
Chris Wilson0673ad42016-06-24 14:00:22 +01001397{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001398 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001399 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001400
Daniel Vetter99c539b2017-07-15 00:46:56 +02001401 i915_driver_unregister(dev_priv);
1402
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001403 if (i915_gem_suspend(dev_priv))
Chris Wilson42f55512016-06-24 14:00:26 +01001404 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
Chris Wilson0673ad42016-06-24 14:00:22 +01001405
1406 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1407
Daniel Vetter18dddad2017-03-21 17:41:49 +01001408 drm_atomic_helper_shutdown(dev);
Maarten Lankhorsta667fb42016-12-15 15:29:44 +01001409
Zhenyu Wang26f837e2017-01-13 10:46:09 +08001410 intel_gvt_cleanup(dev_priv);
1411
Chris Wilson0673ad42016-06-24 14:00:22 +01001412 intel_modeset_cleanup(dev);
1413
1414 /*
1415 * free the memory space allocated for the child device
1416 * config parsed from VBT
1417 */
1418 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1419 kfree(dev_priv->vbt.child_dev);
1420 dev_priv->vbt.child_dev = NULL;
1421 dev_priv->vbt.child_dev_num = 0;
1422 }
1423 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1424 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1425 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1426 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1427
David Weinehall52a05c32016-08-22 13:32:44 +03001428 vga_switcheroo_unregister_client(pdev);
1429 vga_client_register(pdev, NULL, NULL, NULL);
Chris Wilson0673ad42016-06-24 14:00:22 +01001430
1431 intel_csr_ucode_fini(dev_priv);
1432
1433 /* Free error state after interrupts are fully disabled. */
1434 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
Chris Wilson5a4c6f12017-02-14 16:46:11 +00001435 i915_reset_error_state(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001436
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01001437 i915_gem_fini(dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -07001438 intel_uc_fini_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001439 intel_fbc_cleanup_cfb(dev_priv);
1440
1441 intel_power_domains_fini(dev_priv);
1442
1443 i915_driver_cleanup_hw(dev_priv);
1444 i915_driver_cleanup_mmio(dev_priv);
1445
1446 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
Chris Wilsoncad36882017-02-10 16:35:21 +00001447}
1448
1449static void i915_driver_release(struct drm_device *dev)
1450{
1451 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001452
1453 i915_driver_cleanup_early(dev_priv);
Chris Wilsoncad36882017-02-10 16:35:21 +00001454 drm_dev_fini(&dev_priv->drm);
1455
1456 kfree(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001457}
1458
1459static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1460{
Chris Wilson829a0af2017-06-20 12:05:45 +01001461 struct drm_i915_private *i915 = to_i915(dev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001462 int ret;
1463
Chris Wilson829a0af2017-06-20 12:05:45 +01001464 ret = i915_gem_open(i915, file);
Chris Wilson0673ad42016-06-24 14:00:22 +01001465 if (ret)
1466 return ret;
1467
1468 return 0;
1469}
1470
1471/**
1472 * i915_driver_lastclose - clean up after all DRM clients have exited
1473 * @dev: DRM device
1474 *
1475 * Take care of cleaning up after all DRM clients have exited. In the
1476 * mode setting case, we want to restore the kernel's initial mode (just
1477 * in case the last client left us in a bad state).
1478 *
1479 * Additionally, in the non-mode setting case, we'll tear down the GTT
1480 * and DMA structures, since the kernel won't be using them, and clea
1481 * up any GEM state.
1482 */
1483static void i915_driver_lastclose(struct drm_device *dev)
1484{
1485 intel_fbdev_restore_mode(dev);
1486 vga_switcheroo_process_delayed_switch();
1487}
1488
Daniel Vetter7d2ec882017-03-08 15:12:45 +01001489static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
Chris Wilson0673ad42016-06-24 14:00:22 +01001490{
Daniel Vetter7d2ec882017-03-08 15:12:45 +01001491 struct drm_i915_file_private *file_priv = file->driver_priv;
1492
Chris Wilson0673ad42016-06-24 14:00:22 +01001493 mutex_lock(&dev->struct_mutex);
Chris Wilson829a0af2017-06-20 12:05:45 +01001494 i915_gem_context_close(file);
Chris Wilson0673ad42016-06-24 14:00:22 +01001495 i915_gem_release(dev, file);
1496 mutex_unlock(&dev->struct_mutex);
Chris Wilson0673ad42016-06-24 14:00:22 +01001497
1498 kfree(file_priv);
1499}
1500
Imre Deak07f9cd02014-08-18 14:42:45 +03001501static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1502{
Chris Wilson91c8a322016-07-05 10:40:23 +01001503 struct drm_device *dev = &dev_priv->drm;
Jani Nikula19c80542015-12-16 12:48:16 +02001504 struct intel_encoder *encoder;
Imre Deak07f9cd02014-08-18 14:42:45 +03001505
1506 drm_modeset_lock_all(dev);
Jani Nikula19c80542015-12-16 12:48:16 +02001507 for_each_intel_encoder(dev, encoder)
1508 if (encoder->suspend)
1509 encoder->suspend(encoder);
Imre Deak07f9cd02014-08-18 14:42:45 +03001510 drm_modeset_unlock_all(dev);
1511}
1512
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001513static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1514 bool rpm_resume);
Imre Deak507e1262016-04-20 20:27:54 +03001515static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +05301516
Imre Deakbc872292015-11-18 17:32:30 +02001517static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1518{
1519#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1520 if (acpi_target_system_state() < ACPI_STATE_S3)
1521 return true;
1522#endif
1523 return false;
1524}
Sagar Kambleebc32822014-08-13 23:07:05 +05301525
Imre Deak5e365c32014-10-23 19:23:25 +03001526static int i915_drm_suspend(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001527{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001528 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001529 struct pci_dev *pdev = dev_priv->drm.pdev;
Jesse Barnese5747e32014-06-12 08:35:47 -07001530 pci_power_t opregion_target_state;
Daniel Vetterd5818932015-02-23 12:03:26 +01001531 int error;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +01001532
Zhang Ruib8efb172013-02-05 15:41:53 +08001533 /* ignore lid events during suspend */
1534 mutex_lock(&dev_priv->modeset_restore_lock);
1535 dev_priv->modeset_restore = MODESET_SUSPENDED;
1536 mutex_unlock(&dev_priv->modeset_restore_lock);
1537
Imre Deak1f814da2015-12-16 02:52:19 +02001538 disable_rpm_wakeref_asserts(dev_priv);
1539
Paulo Zanonic67a4702013-08-19 13:18:09 -03001540 /* We do a lot of poking in a lot of registers, make sure they work
1541 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +02001542 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -02001543
Dave Airlie5bcf7192010-12-07 09:20:40 +10001544 drm_kms_helper_poll_disable(dev);
1545
David Weinehall52a05c32016-08-22 13:32:44 +03001546 pci_save_state(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001547
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001548 error = i915_gem_suspend(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001549 if (error) {
David Weinehall52a05c32016-08-22 13:32:44 +03001550 dev_err(&pdev->dev,
Daniel Vetterd5818932015-02-23 12:03:26 +01001551 "GEM idle failed, resume might fail\n");
Imre Deak1f814da2015-12-16 02:52:19 +02001552 goto out;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001553 }
1554
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02001555 intel_display_suspend(dev);
Daniel Vetterd5818932015-02-23 12:03:26 +01001556
1557 intel_dp_mst_suspend(dev);
1558
1559 intel_runtime_pm_disable_interrupts(dev_priv);
1560 intel_hpd_cancel_work(dev_priv);
1561
1562 intel_suspend_encoders(dev_priv);
1563
Ville Syrjälä712bf362016-10-31 22:37:23 +02001564 intel_suspend_hw(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001565
Tvrtko Ursulin275a9912016-11-16 08:55:34 +00001566 i915_gem_suspend_gtt_mappings(dev_priv);
Ben Widawsky828c7902013-10-16 09:21:30 -07001567
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00001568 i915_save_state(dev_priv);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001569
Imre Deakbc872292015-11-18 17:32:30 +02001570 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001571 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
Jesse Barnese5747e32014-06-12 08:35:47 -07001572
Hans de Goede68f60942017-02-10 11:28:01 +01001573 intel_uncore_suspend(dev_priv);
Chris Wilson03d92e42016-05-23 15:08:10 +01001574 intel_opregion_unregister(dev_priv);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001575
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001576 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +01001577
Mika Kuoppala62d5d692014-02-25 17:11:28 +02001578 dev_priv->suspend_count++;
1579
Imre Deakf74ed082016-04-18 14:48:21 +03001580 intel_csr_ucode_suspend(dev_priv);
Imre Deakf514c2d2015-10-28 23:59:06 +02001581
Imre Deak1f814da2015-12-16 02:52:19 +02001582out:
1583 enable_rpm_wakeref_asserts(dev_priv);
1584
1585 return error;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001586}
1587
David Weinehallc49d13e2016-08-22 13:32:42 +03001588static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
Imre Deakc3c09c92014-10-23 19:23:15 +03001589{
David Weinehallc49d13e2016-08-22 13:32:42 +03001590 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001591 struct pci_dev *pdev = dev_priv->drm.pdev;
Imre Deakbc872292015-11-18 17:32:30 +02001592 bool fw_csr;
Imre Deakc3c09c92014-10-23 19:23:15 +03001593 int ret;
1594
Imre Deak1f814da2015-12-16 02:52:19 +02001595 disable_rpm_wakeref_asserts(dev_priv);
1596
Imre Deak4c494a52016-10-13 14:34:06 +03001597 intel_display_set_init_power(dev_priv, false);
1598
Imre Deakdd9f31c2017-08-16 17:46:07 +03001599 fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
Imre Deaka7c81252016-04-01 16:02:38 +03001600 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
Imre Deakbc872292015-11-18 17:32:30 +02001601 /*
1602 * In case of firmware assisted context save/restore don't manually
1603 * deinit the power domains. This also means the CSR/DMC firmware will
1604 * stay active, it will power down any HW resources as required and
1605 * also enable deeper system power states that would be blocked if the
1606 * firmware was inactive.
1607 */
1608 if (!fw_csr)
1609 intel_power_domains_suspend(dev_priv);
Imre Deak73dfc222015-11-17 17:33:53 +02001610
Imre Deak507e1262016-04-20 20:27:54 +03001611 ret = 0;
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001612 if (IS_GEN9_LP(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +03001613 bxt_enable_dc9(dev_priv);
Imre Deakb8aea3d12016-04-20 20:27:55 +03001614 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +03001615 hsw_enable_pc8(dev_priv);
1616 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1617 ret = vlv_suspend_complete(dev_priv);
Imre Deakc3c09c92014-10-23 19:23:15 +03001618
1619 if (ret) {
1620 DRM_ERROR("Suspend complete failed: %d\n", ret);
Imre Deakbc872292015-11-18 17:32:30 +02001621 if (!fw_csr)
1622 intel_power_domains_init_hw(dev_priv, true);
Imre Deakc3c09c92014-10-23 19:23:15 +03001623
Imre Deak1f814da2015-12-16 02:52:19 +02001624 goto out;
Imre Deakc3c09c92014-10-23 19:23:15 +03001625 }
1626
David Weinehall52a05c32016-08-22 13:32:44 +03001627 pci_disable_device(pdev);
Imre Deakab3be732015-03-02 13:04:41 +02001628 /*
Imre Deak54875572015-06-30 17:06:47 +03001629 * During hibernation on some platforms the BIOS may try to access
Imre Deakab3be732015-03-02 13:04:41 +02001630 * the device even though it's already in D3 and hang the machine. So
1631 * leave the device in D0 on those platforms and hope the BIOS will
Imre Deak54875572015-06-30 17:06:47 +03001632 * power down the device properly. The issue was seen on multiple old
1633 * GENs with different BIOS vendors, so having an explicit blacklist
1634 * is inpractical; apply the workaround on everything pre GEN6. The
1635 * platforms where the issue was seen:
1636 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1637 * Fujitsu FSC S7110
1638 * Acer Aspire 1830T
Imre Deakab3be732015-03-02 13:04:41 +02001639 */
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +00001640 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
David Weinehall52a05c32016-08-22 13:32:44 +03001641 pci_set_power_state(pdev, PCI_D3hot);
Imre Deakc3c09c92014-10-23 19:23:15 +03001642
Imre Deakbc872292015-11-18 17:32:30 +02001643 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1644
Imre Deak1f814da2015-12-16 02:52:19 +02001645out:
1646 enable_rpm_wakeref_asserts(dev_priv);
1647
1648 return ret;
Imre Deakc3c09c92014-10-23 19:23:15 +03001649}
1650
Matthew Aulda9a251c2016-12-02 10:24:11 +00001651static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001652{
1653 int error;
1654
Chris Wilsonded8b072016-07-05 10:40:22 +01001655 if (!dev) {
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001656 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -07001657 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001658 return -ENODEV;
1659 }
1660
Imre Deak0b14cbd2014-09-10 18:16:55 +03001661 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1662 state.event != PM_EVENT_FREEZE))
1663 return -EINVAL;
Dave Airlie5bcf7192010-12-07 09:20:40 +10001664
1665 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1666 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +01001667
Imre Deak5e365c32014-10-23 19:23:25 +03001668 error = i915_drm_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001669 if (error)
1670 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001671
Imre Deakab3be732015-03-02 13:04:41 +02001672 return i915_drm_suspend_late(dev, false);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001673}
1674
Imre Deak5e365c32014-10-23 19:23:25 +03001675static int i915_drm_resume(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001676{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001677 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläac840ae2016-05-06 21:35:55 +03001678 int ret;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001679
Imre Deak1f814da2015-12-16 02:52:19 +02001680 disable_rpm_wakeref_asserts(dev_priv);
Chris Wilsonabc80ab2016-08-24 10:27:01 +01001681 intel_sanitize_gt_powersave(dev_priv);
Imre Deak1f814da2015-12-16 02:52:19 +02001682
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001683 ret = i915_ggtt_enable_hw(dev_priv);
Ville Syrjäläac840ae2016-05-06 21:35:55 +03001684 if (ret)
1685 DRM_ERROR("failed to re-enable GGTT\n");
1686
Imre Deakf74ed082016-04-18 14:48:21 +03001687 intel_csr_ucode_resume(dev_priv);
1688
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00001689 i915_restore_state(dev_priv);
Imre Deak8090ba82016-08-10 14:07:33 +03001690 intel_pps_unlock_regs_wa(dev_priv);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001691 intel_opregion_setup(dev_priv);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +01001692
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02001693 intel_init_pch_refclk(dev_priv);
Chris Wilson1833b132012-05-09 11:56:28 +01001694
Peter Antoine364aece2015-05-11 08:50:45 +01001695 /*
1696 * Interrupts have to be enabled before any batches are run. If not the
1697 * GPU will hang. i915_gem_init_hw() will initiate batches to
1698 * update/restore the context.
1699 *
Imre Deak908764f2016-11-29 21:40:29 +02001700 * drm_mode_config_reset() needs AUX interrupts.
1701 *
Peter Antoine364aece2015-05-11 08:50:45 +01001702 * Modeset enabling in intel_modeset_init_hw() also needs working
1703 * interrupts.
1704 */
1705 intel_runtime_pm_enable_interrupts(dev_priv);
1706
Imre Deak908764f2016-11-29 21:40:29 +02001707 drm_mode_config_reset(dev);
1708
Chris Wilson37cd3302017-11-12 11:27:38 +00001709 i915_gem_resume(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001710
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001711 intel_guc_resume(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07001712
Daniel Vetterd5818932015-02-23 12:03:26 +01001713 intel_modeset_init_hw(dev);
1714
1715 spin_lock_irq(&dev_priv->irq_lock);
1716 if (dev_priv->display.hpd_irq_setup)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001717 dev_priv->display.hpd_irq_setup(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001718 spin_unlock_irq(&dev_priv->irq_lock);
1719
Daniel Vetterd5818932015-02-23 12:03:26 +01001720 intel_dp_mst_resume(dev);
1721
Lyudea16b7652016-03-11 10:57:01 -05001722 intel_display_resume(dev);
1723
Lyudee0b70062016-11-01 21:06:30 -04001724 drm_kms_helper_poll_enable(dev);
1725
Daniel Vetterd5818932015-02-23 12:03:26 +01001726 /*
1727 * ... but also need to make sure that hotplug processing
1728 * doesn't cause havoc. Like in the driver load code we don't
1729 * bother with the tiny race here where we might loose hotplug
1730 * notifications.
1731 * */
1732 intel_hpd_init(dev_priv);
Jesse Barnes1daed3f2011-01-05 12:01:25 -08001733
Chris Wilson03d92e42016-05-23 15:08:10 +01001734 intel_opregion_register(dev_priv);
Chris Wilson44834a62010-08-19 16:09:23 +01001735
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001736 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -07001737
Zhang Ruib8efb172013-02-05 15:41:53 +08001738 mutex_lock(&dev_priv->modeset_restore_lock);
1739 dev_priv->modeset_restore = MODESET_DONE;
1740 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001741
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001742 intel_opregion_notify_adapter(dev_priv, PCI_D0);
Jesse Barnese5747e32014-06-12 08:35:47 -07001743
Imre Deak1f814da2015-12-16 02:52:19 +02001744 enable_rpm_wakeref_asserts(dev_priv);
1745
Chris Wilson074c6ad2014-04-09 09:19:43 +01001746 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001747}
1748
Imre Deak5e365c32014-10-23 19:23:25 +03001749static int i915_drm_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001750{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001751 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001752 struct pci_dev *pdev = dev_priv->drm.pdev;
Imre Deak44410cd2016-04-18 14:45:54 +03001753 int ret;
Imre Deak36d61e62014-10-23 19:23:24 +03001754
Imre Deak76c4b252014-04-01 19:55:22 +03001755 /*
1756 * We have a resume ordering issue with the snd-hda driver also
1757 * requiring our device to be power up. Due to the lack of a
1758 * parent/child relationship we currently solve this with an early
1759 * resume hook.
1760 *
1761 * FIXME: This should be solved with a special hdmi sink device or
1762 * similar so that power domains can be employed.
1763 */
Imre Deak44410cd2016-04-18 14:45:54 +03001764
1765 /*
1766 * Note that we need to set the power state explicitly, since we
1767 * powered off the device during freeze and the PCI core won't power
1768 * it back up for us during thaw. Powering off the device during
1769 * freeze is not a hard requirement though, and during the
1770 * suspend/resume phases the PCI core makes sure we get here with the
1771 * device powered on. So in case we change our freeze logic and keep
1772 * the device powered we can also remove the following set power state
1773 * call.
1774 */
David Weinehall52a05c32016-08-22 13:32:44 +03001775 ret = pci_set_power_state(pdev, PCI_D0);
Imre Deak44410cd2016-04-18 14:45:54 +03001776 if (ret) {
1777 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1778 goto out;
1779 }
1780
1781 /*
1782 * Note that pci_enable_device() first enables any parent bridge
1783 * device and only then sets the power state for this device. The
1784 * bridge enabling is a nop though, since bridge devices are resumed
1785 * first. The order of enabling power and enabling the device is
1786 * imposed by the PCI core as described above, so here we preserve the
1787 * same order for the freeze/thaw phases.
1788 *
1789 * TODO: eventually we should remove pci_disable_device() /
1790 * pci_enable_enable_device() from suspend/resume. Due to how they
1791 * depend on the device enable refcount we can't anyway depend on them
1792 * disabling/enabling the device.
1793 */
David Weinehall52a05c32016-08-22 13:32:44 +03001794 if (pci_enable_device(pdev)) {
Imre Deakbc872292015-11-18 17:32:30 +02001795 ret = -EIO;
1796 goto out;
1797 }
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001798
David Weinehall52a05c32016-08-22 13:32:44 +03001799 pci_set_master(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001800
Imre Deak1f814da2015-12-16 02:52:19 +02001801 disable_rpm_wakeref_asserts(dev_priv);
1802
Wayne Boyer666a4532015-12-09 12:29:35 -08001803 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001804 ret = vlv_resume_prepare(dev_priv, false);
Imre Deak36d61e62014-10-23 19:23:24 +03001805 if (ret)
Damien Lespiauff0b1872015-05-20 14:45:15 +01001806 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1807 ret);
Imre Deak36d61e62014-10-23 19:23:24 +03001808
Hans de Goede68f60942017-02-10 11:28:01 +01001809 intel_uncore_resume_early(dev_priv);
Paulo Zanoniefee8332014-10-27 17:54:33 -02001810
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001811 if (IS_GEN9_LP(dev_priv)) {
Imre Deakda2f41d2016-04-20 20:27:56 +03001812 if (!dev_priv->suspended_to_idle)
1813 gen9_sanitize_dc_state(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03001814 bxt_disable_dc9(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +03001815 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Damien Lespiaua9a6b732015-05-20 14:45:14 +01001816 hsw_disable_pc8(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +03001817 }
Paulo Zanoniefee8332014-10-27 17:54:33 -02001818
Chris Wilsondc979972016-05-10 14:10:04 +01001819 intel_uncore_sanitize(dev_priv);
Imre Deakbc872292015-11-18 17:32:30 +02001820
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001821 if (IS_GEN9_LP(dev_priv) ||
Imre Deaka7c81252016-04-01 16:02:38 +03001822 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
Imre Deakbc872292015-11-18 17:32:30 +02001823 intel_power_domains_init_hw(dev_priv, true);
1824
Chris Wilson24145512017-01-24 11:01:35 +00001825 i915_gem_sanitize(dev_priv);
1826
Imre Deak6e35e8a2016-04-18 10:04:19 +03001827 enable_rpm_wakeref_asserts(dev_priv);
1828
Imre Deakbc872292015-11-18 17:32:30 +02001829out:
1830 dev_priv->suspended_to_idle = false;
Imre Deak36d61e62014-10-23 19:23:24 +03001831
1832 return ret;
Imre Deak76c4b252014-04-01 19:55:22 +03001833}
1834
Tvrtko Ursulin7f26cb82016-12-01 14:16:41 +00001835static int i915_resume_switcheroo(struct drm_device *dev)
Imre Deak76c4b252014-04-01 19:55:22 +03001836{
Imre Deak50a00722014-10-23 19:23:17 +03001837 int ret;
Imre Deak76c4b252014-04-01 19:55:22 +03001838
Imre Deak097dd832014-10-23 19:23:19 +03001839 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1840 return 0;
1841
Imre Deak5e365c32014-10-23 19:23:25 +03001842 ret = i915_drm_resume_early(dev);
Imre Deak50a00722014-10-23 19:23:17 +03001843 if (ret)
1844 return ret;
1845
Imre Deak5a175142014-10-23 19:23:18 +03001846 return i915_drm_resume(dev);
1847}
1848
Ben Gamari11ed50e2009-09-14 17:48:45 -04001849/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -02001850 * i915_reset - reset chip after a hang
Chris Wilson535275d2017-07-21 13:32:37 +01001851 * @i915: #drm_i915_private to reset
1852 * @flags: Instructions
Ben Gamari11ed50e2009-09-14 17:48:45 -04001853 *
Chris Wilson780f2622016-09-09 14:11:52 +01001854 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1855 * on failure.
Ben Gamari11ed50e2009-09-14 17:48:45 -04001856 *
Chris Wilson221fe792016-09-09 14:11:51 +01001857 * Caller must hold the struct_mutex.
1858 *
Ben Gamari11ed50e2009-09-14 17:48:45 -04001859 * Procedure is fairly simple:
1860 * - reset the chip using the reset reg
1861 * - re-init context state
1862 * - re-init hardware status page
1863 * - re-init ring buffer
1864 * - re-init interrupt state
1865 * - re-init display
1866 */
Chris Wilson535275d2017-07-21 13:32:37 +01001867void i915_reset(struct drm_i915_private *i915, unsigned int flags)
Ben Gamari11ed50e2009-09-14 17:48:45 -04001868{
Chris Wilson535275d2017-07-21 13:32:37 +01001869 struct i915_gpu_error *error = &i915->gpu_error;
Kenneth Graunke0573ed42010-09-11 03:17:19 -07001870 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001871
Chris Wilson535275d2017-07-21 13:32:37 +01001872 lockdep_assert_held(&i915->drm.struct_mutex);
Chris Wilson8c185ec2017-03-16 17:13:02 +00001873 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
Chris Wilson221fe792016-09-09 14:11:51 +01001874
Chris Wilson8c185ec2017-03-16 17:13:02 +00001875 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
Chris Wilson780f2622016-09-09 14:11:52 +01001876 return;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001877
Chris Wilsond98c52c2016-04-13 17:35:05 +01001878 /* Clear any previous failed attempts at recovery. Time to try again. */
Chris Wilson535275d2017-07-21 13:32:37 +01001879 if (!i915_gem_unset_wedged(i915))
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001880 goto wakeup;
1881
Chris Wilson535275d2017-07-21 13:32:37 +01001882 if (!(flags & I915_RESET_QUIET))
1883 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
Chris Wilson8af29b02016-09-09 14:11:47 +01001884 error->reset_count++;
Chris Wilsond98c52c2016-04-13 17:35:05 +01001885
Chris Wilson535275d2017-07-21 13:32:37 +01001886 disable_irq(i915->drm.irq);
1887 ret = i915_gem_reset_prepare(i915);
Chris Wilson0e178ae2017-01-17 17:59:06 +02001888 if (ret) {
1889 DRM_ERROR("GPU recovery failed\n");
Chris Wilson535275d2017-07-21 13:32:37 +01001890 intel_gpu_reset(i915, ALL_ENGINES);
Chris Wilson0e178ae2017-01-17 17:59:06 +02001891 goto error;
1892 }
Chris Wilson9e60ab02016-10-04 21:11:28 +01001893
Chris Wilson535275d2017-07-21 13:32:37 +01001894 ret = intel_gpu_reset(i915, ALL_ENGINES);
Kenneth Graunke0573ed42010-09-11 03:17:19 -07001895 if (ret) {
Chris Wilson804e59a2016-04-13 17:35:09 +01001896 if (ret != -ENODEV)
1897 DRM_ERROR("Failed to reset chip: %i\n", ret);
1898 else
1899 DRM_DEBUG_DRIVER("GPU reset disabled\n");
Chris Wilsond98c52c2016-04-13 17:35:05 +01001900 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001901 }
1902
Chris Wilson535275d2017-07-21 13:32:37 +01001903 i915_gem_reset(i915);
1904 intel_overlay_reset(i915);
Ville Syrjälä1362b772014-11-26 17:07:29 +02001905
Ben Gamari11ed50e2009-09-14 17:48:45 -04001906 /* Ok, now get things going again... */
1907
1908 /*
1909 * Everything depends on having the GTT running, so we need to start
Chris Wilson0db8c962017-09-06 12:14:05 +01001910 * there.
1911 */
1912 ret = i915_ggtt_enable_hw(i915);
1913 if (ret) {
1914 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1915 goto error;
1916 }
1917
1918 /*
Ben Gamari11ed50e2009-09-14 17:48:45 -04001919 * Next we need to restore the context, but we don't use those
1920 * yet either...
1921 *
1922 * Ring buffer needs to be re-initialized in the KMS case, or if X
1923 * was running at the time of the reset (i.e. we weren't VT
1924 * switched away).
1925 */
Chris Wilson535275d2017-07-21 13:32:37 +01001926 ret = i915_gem_init_hw(i915);
Daniel Vetter33d30a92015-02-23 12:03:27 +01001927 if (ret) {
1928 DRM_ERROR("Failed hw init on reset %d\n", ret);
Chris Wilsond98c52c2016-04-13 17:35:05 +01001929 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001930 }
1931
Chris Wilson535275d2017-07-21 13:32:37 +01001932 i915_queue_hangcheck(i915);
Chris Wilsonc2a126a2016-11-22 14:41:19 +00001933
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001934finish:
Chris Wilson535275d2017-07-21 13:32:37 +01001935 i915_gem_reset_finish(i915);
1936 enable_irq(i915->drm.irq);
Chris Wilson8c185ec2017-03-16 17:13:02 +00001937
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001938wakeup:
Chris Wilson8c185ec2017-03-16 17:13:02 +00001939 clear_bit(I915_RESET_HANDOFF, &error->flags);
1940 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
Chris Wilson780f2622016-09-09 14:11:52 +01001941 return;
Chris Wilsond98c52c2016-04-13 17:35:05 +01001942
1943error:
Chris Wilson535275d2017-07-21 13:32:37 +01001944 i915_gem_set_wedged(i915);
1945 i915_gem_retire_requests(i915);
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001946 goto finish;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001947}
1948
Michel Thierry6acbea82017-10-31 15:53:09 -07001949static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
1950 struct intel_engine_cs *engine)
1951{
1952 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
1953}
1954
Michel Thierry142bc7d2017-06-20 10:57:46 +01001955/**
1956 * i915_reset_engine - reset GPU engine to recover from a hang
1957 * @engine: engine to reset
Chris Wilson535275d2017-07-21 13:32:37 +01001958 * @flags: options
Michel Thierry142bc7d2017-06-20 10:57:46 +01001959 *
1960 * Reset a specific GPU engine. Useful if a hang is detected.
1961 * Returns zero on successful reset or otherwise an error code.
Michel Thierrya1ef70e2017-06-20 10:57:47 +01001962 *
1963 * Procedure is:
1964 * - identifies the request that caused the hang and it is dropped
1965 * - reset engine (which will force the engine to idle)
1966 * - re-init/configure engine
Michel Thierry142bc7d2017-06-20 10:57:46 +01001967 */
Chris Wilson535275d2017-07-21 13:32:37 +01001968int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
Michel Thierry142bc7d2017-06-20 10:57:46 +01001969{
Michel Thierrya1ef70e2017-06-20 10:57:47 +01001970 struct i915_gpu_error *error = &engine->i915->gpu_error;
1971 struct drm_i915_gem_request *active_request;
1972 int ret;
1973
1974 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1975
Chris Wilson535275d2017-07-21 13:32:37 +01001976 if (!(flags & I915_RESET_QUIET)) {
1977 dev_notice(engine->i915->drm.dev,
1978 "Resetting %s after gpu hang\n", engine->name);
1979 }
Chris Wilson73676122017-07-21 13:32:31 +01001980 error->reset_engine_count[engine->id]++;
Michel Thierrya1ef70e2017-06-20 10:57:47 +01001981
1982 active_request = i915_gem_reset_prepare_engine(engine);
1983 if (IS_ERR(active_request)) {
1984 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1985 ret = PTR_ERR(active_request);
1986 goto out;
1987 }
1988
Michel Thierry6acbea82017-10-31 15:53:09 -07001989 if (!engine->i915->guc.execbuf_client)
1990 ret = intel_gt_reset_engine(engine->i915, engine);
1991 else
1992 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
Chris Wilson0364cd12017-07-21 13:32:21 +01001993 if (ret) {
1994 /* If we fail here, we expect to fallback to a global reset */
Michel Thierry6acbea82017-10-31 15:53:09 -07001995 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1996 engine->i915->guc.execbuf_client ? "GuC " : "",
Chris Wilson0364cd12017-07-21 13:32:21 +01001997 engine->name, ret);
1998 goto out;
1999 }
Chris Wilsonb4f3e162017-07-21 13:32:20 +01002000
Michel Thierrya1ef70e2017-06-20 10:57:47 +01002001 /*
2002 * The request that caused the hang is stuck on elsp, we know the
2003 * active request and can drop it, adjust head to skip the offending
2004 * request to resume executing remaining requests in the queue.
2005 */
2006 i915_gem_reset_engine(engine, active_request);
2007
Michel Thierrya1ef70e2017-06-20 10:57:47 +01002008 /*
2009 * The engine and its registers (and workarounds in case of render)
2010 * have been reset to their default values. Follow the init_ring
2011 * process to program RING_MODE, HWSP and re-enable submission.
2012 */
2013 ret = engine->init_hw(engine);
Michel Thierry702c8f82017-06-20 10:57:48 +01002014 if (ret)
2015 goto out;
Michel Thierrya1ef70e2017-06-20 10:57:47 +01002016
2017out:
Chris Wilson0364cd12017-07-21 13:32:21 +01002018 i915_gem_reset_finish_engine(engine);
Michel Thierrya1ef70e2017-06-20 10:57:47 +01002019 return ret;
Michel Thierry142bc7d2017-06-20 10:57:46 +01002020}
2021
David Weinehallc49d13e2016-08-22 13:32:42 +03002022static int i915_pm_suspend(struct device *kdev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -05002023{
David Weinehallc49d13e2016-08-22 13:32:42 +03002024 struct pci_dev *pdev = to_pci_dev(kdev);
2025 struct drm_device *dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05002026
David Weinehallc49d13e2016-08-22 13:32:42 +03002027 if (!dev) {
2028 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01002029 return -ENODEV;
2030 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -05002031
David Weinehallc49d13e2016-08-22 13:32:42 +03002032 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Dave Airlie5bcf7192010-12-07 09:20:40 +10002033 return 0;
2034
David Weinehallc49d13e2016-08-22 13:32:42 +03002035 return i915_drm_suspend(dev);
Imre Deak76c4b252014-04-01 19:55:22 +03002036}
2037
David Weinehallc49d13e2016-08-22 13:32:42 +03002038static int i915_pm_suspend_late(struct device *kdev)
Imre Deak76c4b252014-04-01 19:55:22 +03002039{
David Weinehallc49d13e2016-08-22 13:32:42 +03002040 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deak76c4b252014-04-01 19:55:22 +03002041
2042 /*
Damien Lespiauc965d9952015-05-18 19:53:48 +01002043 * We have a suspend ordering issue with the snd-hda driver also
Imre Deak76c4b252014-04-01 19:55:22 +03002044 * requiring our device to be power up. Due to the lack of a
2045 * parent/child relationship we currently solve this with an late
2046 * suspend hook.
2047 *
2048 * FIXME: This should be solved with a special hdmi sink device or
2049 * similar so that power domains can be employed.
2050 */
David Weinehallc49d13e2016-08-22 13:32:42 +03002051 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak76c4b252014-04-01 19:55:22 +03002052 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -05002053
David Weinehallc49d13e2016-08-22 13:32:42 +03002054 return i915_drm_suspend_late(dev, false);
Imre Deakab3be732015-03-02 13:04:41 +02002055}
2056
David Weinehallc49d13e2016-08-22 13:32:42 +03002057static int i915_pm_poweroff_late(struct device *kdev)
Imre Deakab3be732015-03-02 13:04:41 +02002058{
David Weinehallc49d13e2016-08-22 13:32:42 +03002059 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deakab3be732015-03-02 13:04:41 +02002060
David Weinehallc49d13e2016-08-22 13:32:42 +03002061 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deakab3be732015-03-02 13:04:41 +02002062 return 0;
2063
David Weinehallc49d13e2016-08-22 13:32:42 +03002064 return i915_drm_suspend_late(dev, true);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08002065}
2066
David Weinehallc49d13e2016-08-22 13:32:42 +03002067static int i915_pm_resume_early(struct device *kdev)
Imre Deak76c4b252014-04-01 19:55:22 +03002068{
David Weinehallc49d13e2016-08-22 13:32:42 +03002069 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deak76c4b252014-04-01 19:55:22 +03002070
David Weinehallc49d13e2016-08-22 13:32:42 +03002071 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak097dd832014-10-23 19:23:19 +03002072 return 0;
2073
David Weinehallc49d13e2016-08-22 13:32:42 +03002074 return i915_drm_resume_early(dev);
Imre Deak76c4b252014-04-01 19:55:22 +03002075}
2076
David Weinehallc49d13e2016-08-22 13:32:42 +03002077static int i915_pm_resume(struct device *kdev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08002078{
David Weinehallc49d13e2016-08-22 13:32:42 +03002079 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01002080
David Weinehallc49d13e2016-08-22 13:32:42 +03002081 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak097dd832014-10-23 19:23:19 +03002082 return 0;
2083
David Weinehallc49d13e2016-08-22 13:32:42 +03002084 return i915_drm_resume(dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08002085}
2086
Chris Wilson1f19ac22016-05-14 07:26:32 +01002087/* freeze: before creating the hibernation_image */
David Weinehallc49d13e2016-08-22 13:32:42 +03002088static int i915_pm_freeze(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002089{
Imre Deakdd9f31c2017-08-16 17:46:07 +03002090 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Chris Wilson6a800ea2016-09-21 14:51:07 +01002091 int ret;
2092
Imre Deakdd9f31c2017-08-16 17:46:07 +03002093 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2094 ret = i915_drm_suspend(dev);
2095 if (ret)
2096 return ret;
2097 }
Chris Wilson6a800ea2016-09-21 14:51:07 +01002098
2099 ret = i915_gem_freeze(kdev_to_i915(kdev));
2100 if (ret)
2101 return ret;
2102
2103 return 0;
Chris Wilson1f19ac22016-05-14 07:26:32 +01002104}
2105
David Weinehallc49d13e2016-08-22 13:32:42 +03002106static int i915_pm_freeze_late(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002107{
Imre Deakdd9f31c2017-08-16 17:46:07 +03002108 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Chris Wilson461fb992016-05-14 07:26:33 +01002109 int ret;
2110
Imre Deakdd9f31c2017-08-16 17:46:07 +03002111 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2112 ret = i915_drm_suspend_late(dev, true);
2113 if (ret)
2114 return ret;
2115 }
Chris Wilson461fb992016-05-14 07:26:33 +01002116
David Weinehallc49d13e2016-08-22 13:32:42 +03002117 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
Chris Wilson461fb992016-05-14 07:26:33 +01002118 if (ret)
2119 return ret;
2120
2121 return 0;
Chris Wilson1f19ac22016-05-14 07:26:32 +01002122}
2123
2124/* thaw: called after creating the hibernation image, but before turning off. */
David Weinehallc49d13e2016-08-22 13:32:42 +03002125static int i915_pm_thaw_early(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002126{
David Weinehallc49d13e2016-08-22 13:32:42 +03002127 return i915_pm_resume_early(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01002128}
2129
David Weinehallc49d13e2016-08-22 13:32:42 +03002130static int i915_pm_thaw(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002131{
David Weinehallc49d13e2016-08-22 13:32:42 +03002132 return i915_pm_resume(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01002133}
2134
2135/* restore: called after loading the hibernation image. */
David Weinehallc49d13e2016-08-22 13:32:42 +03002136static int i915_pm_restore_early(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002137{
David Weinehallc49d13e2016-08-22 13:32:42 +03002138 return i915_pm_resume_early(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01002139}
2140
David Weinehallc49d13e2016-08-22 13:32:42 +03002141static int i915_pm_restore(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01002142{
David Weinehallc49d13e2016-08-22 13:32:42 +03002143 return i915_pm_resume(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01002144}
2145
Imre Deakddeea5b2014-05-05 15:19:56 +03002146/*
2147 * Save all Gunit registers that may be lost after a D3 and a subsequent
2148 * S0i[R123] transition. The list of registers needing a save/restore is
2149 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2150 * registers in the following way:
2151 * - Driver: saved/restored by the driver
2152 * - Punit : saved/restored by the Punit firmware
2153 * - No, w/o marking: no need to save/restore, since the register is R/O or
2154 * used internally by the HW in a way that doesn't depend
2155 * keeping the content across a suspend/resume.
2156 * - Debug : used for debugging
2157 *
2158 * We save/restore all registers marked with 'Driver', with the following
2159 * exceptions:
2160 * - Registers out of use, including also registers marked with 'Debug'.
2161 * These have no effect on the driver's operation, so we don't save/restore
2162 * them to reduce the overhead.
2163 * - Registers that are fully setup by an initialization function called from
2164 * the resume path. For example many clock gating and RPS/RC6 registers.
2165 * - Registers that provide the right functionality with their reset defaults.
2166 *
2167 * TODO: Except for registers that based on the above 3 criteria can be safely
2168 * ignored, we save/restore all others, practically treating the HW context as
2169 * a black-box for the driver. Further investigation is needed to reduce the
2170 * saved/restored registers even further, by following the same 3 criteria.
2171 */
2172static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2173{
2174 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2175 int i;
2176
2177 /* GAM 0x4000-0x4770 */
2178 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2179 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2180 s->arb_mode = I915_READ(ARB_MODE);
2181 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2182 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2183
2184 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002185 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03002186
2187 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
Imre Deakb5f1c972015-04-15 16:52:30 -07002188 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
Imre Deakddeea5b2014-05-05 15:19:56 +03002189
2190 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2191 s->ecochk = I915_READ(GAM_ECOCHK);
2192 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2193 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2194
2195 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2196
2197 /* MBC 0x9024-0x91D0, 0x8500 */
2198 s->g3dctl = I915_READ(VLV_G3DCTL);
2199 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2200 s->mbctl = I915_READ(GEN6_MBCTL);
2201
2202 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2203 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2204 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2205 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2206 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2207 s->rstctl = I915_READ(GEN6_RSTCTL);
2208 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2209
2210 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2211 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2212 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2213 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2214 s->ecobus = I915_READ(ECOBUS);
2215 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2216 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2217 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2218 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2219 s->rcedata = I915_READ(VLV_RCEDATA);
2220 s->spare2gh = I915_READ(VLV_SPAREG2H);
2221
2222 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2223 s->gt_imr = I915_READ(GTIMR);
2224 s->gt_ier = I915_READ(GTIER);
2225 s->pm_imr = I915_READ(GEN6_PMIMR);
2226 s->pm_ier = I915_READ(GEN6_PMIER);
2227
2228 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002229 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03002230
2231 /* GT SA CZ domain, 0x100000-0x138124 */
2232 s->tilectl = I915_READ(TILECTL);
2233 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2234 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2235 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2236 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2237
2238 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2239 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2240 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
Jesse Barnes9c252102015-04-01 14:22:57 -07002241 s->pcbr = I915_READ(VLV_PCBR);
Imre Deakddeea5b2014-05-05 15:19:56 +03002242 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2243
2244 /*
2245 * Not saving any of:
2246 * DFT, 0x9800-0x9EC0
2247 * SARB, 0xB000-0xB1FC
2248 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2249 * PCI CFG
2250 */
2251}
2252
2253static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2254{
2255 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2256 u32 val;
2257 int i;
2258
2259 /* GAM 0x4000-0x4770 */
2260 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2261 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2262 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2263 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2264 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2265
2266 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002267 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03002268
2269 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
Imre Deakb5f1c972015-04-15 16:52:30 -07002270 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
Imre Deakddeea5b2014-05-05 15:19:56 +03002271
2272 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2273 I915_WRITE(GAM_ECOCHK, s->ecochk);
2274 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2275 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2276
2277 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2278
2279 /* MBC 0x9024-0x91D0, 0x8500 */
2280 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2281 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2282 I915_WRITE(GEN6_MBCTL, s->mbctl);
2283
2284 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2285 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2286 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2287 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2288 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2289 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2290 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2291
2292 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2293 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2294 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2295 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2296 I915_WRITE(ECOBUS, s->ecobus);
2297 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2298 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2299 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2300 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2301 I915_WRITE(VLV_RCEDATA, s->rcedata);
2302 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2303
2304 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2305 I915_WRITE(GTIMR, s->gt_imr);
2306 I915_WRITE(GTIER, s->gt_ier);
2307 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2308 I915_WRITE(GEN6_PMIER, s->pm_ier);
2309
2310 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002311 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03002312
2313 /* GT SA CZ domain, 0x100000-0x138124 */
2314 I915_WRITE(TILECTL, s->tilectl);
2315 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2316 /*
2317 * Preserve the GT allow wake and GFX force clock bit, they are not
2318 * be restored, as they are used to control the s0ix suspend/resume
2319 * sequence by the caller.
2320 */
2321 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2322 val &= VLV_GTLC_ALLOWWAKEREQ;
2323 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2324 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2325
2326 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2327 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2328 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2329 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2330
2331 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2332
2333 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2334 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2335 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
Jesse Barnes9c252102015-04-01 14:22:57 -07002336 I915_WRITE(VLV_PCBR, s->pcbr);
Imre Deakddeea5b2014-05-05 15:19:56 +03002337 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2338}
2339
Chris Wilson3dd14c02017-04-21 14:58:15 +01002340static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2341 u32 mask, u32 val)
2342{
2343 /* The HW does not like us polling for PW_STATUS frequently, so
2344 * use the sleeping loop rather than risk the busy spin within
2345 * intel_wait_for_register().
2346 *
2347 * Transitioning between RC6 states should be at most 2ms (see
2348 * valleyview_enable_rps) so use a 3ms timeout.
2349 */
2350 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2351 3);
2352}
2353
Imre Deak650ad972014-04-18 16:35:02 +03002354int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2355{
2356 u32 val;
2357 int err;
2358
Imre Deak650ad972014-04-18 16:35:02 +03002359 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2360 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2361 if (force_on)
2362 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2363 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2364
2365 if (!force_on)
2366 return 0;
2367
Chris Wilsonc6ddc5f2016-06-30 15:32:46 +01002368 err = intel_wait_for_register(dev_priv,
2369 VLV_GTLC_SURVIVABILITY_REG,
2370 VLV_GFX_CLK_STATUS_BIT,
2371 VLV_GFX_CLK_STATUS_BIT,
2372 20);
Imre Deak650ad972014-04-18 16:35:02 +03002373 if (err)
2374 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2375 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2376
2377 return err;
Imre Deak650ad972014-04-18 16:35:02 +03002378}
2379
Imre Deakddeea5b2014-05-05 15:19:56 +03002380static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2381{
Chris Wilson3dd14c02017-04-21 14:58:15 +01002382 u32 mask;
Imre Deakddeea5b2014-05-05 15:19:56 +03002383 u32 val;
Chris Wilson3dd14c02017-04-21 14:58:15 +01002384 int err;
Imre Deakddeea5b2014-05-05 15:19:56 +03002385
2386 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2387 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2388 if (allow)
2389 val |= VLV_GTLC_ALLOWWAKEREQ;
2390 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2391 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2392
Chris Wilson3dd14c02017-04-21 14:58:15 +01002393 mask = VLV_GTLC_ALLOWWAKEACK;
2394 val = allow ? mask : 0;
2395
2396 err = vlv_wait_for_pw_status(dev_priv, mask, val);
Imre Deakddeea5b2014-05-05 15:19:56 +03002397 if (err)
2398 DRM_ERROR("timeout disabling GT waking\n");
Chris Wilsonb2736692016-06-30 15:32:47 +01002399
Imre Deakddeea5b2014-05-05 15:19:56 +03002400 return err;
Imre Deakddeea5b2014-05-05 15:19:56 +03002401}
2402
Chris Wilson3dd14c02017-04-21 14:58:15 +01002403static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2404 bool wait_for_on)
Imre Deakddeea5b2014-05-05 15:19:56 +03002405{
2406 u32 mask;
2407 u32 val;
Imre Deakddeea5b2014-05-05 15:19:56 +03002408
2409 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2410 val = wait_for_on ? mask : 0;
Imre Deakddeea5b2014-05-05 15:19:56 +03002411
2412 /*
2413 * RC6 transitioning can be delayed up to 2 msec (see
2414 * valleyview_enable_rps), use 3 msec for safety.
2415 */
Chris Wilson3dd14c02017-04-21 14:58:15 +01002416 if (vlv_wait_for_pw_status(dev_priv, mask, val))
Imre Deakddeea5b2014-05-05 15:19:56 +03002417 DRM_ERROR("timeout waiting for GT wells to go %s\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02002418 onoff(wait_for_on));
Imre Deakddeea5b2014-05-05 15:19:56 +03002419}
2420
2421static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2422{
2423 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2424 return;
2425
Daniel Vetter6fa283b2016-01-19 21:00:56 +01002426 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
Imre Deakddeea5b2014-05-05 15:19:56 +03002427 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2428}
2429
Sagar Kambleebc32822014-08-13 23:07:05 +05302430static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03002431{
2432 u32 mask;
2433 int err;
2434
2435 /*
2436 * Bspec defines the following GT well on flags as debug only, so
2437 * don't treat them as hard failures.
2438 */
Chris Wilson3dd14c02017-04-21 14:58:15 +01002439 vlv_wait_for_gt_wells(dev_priv, false);
Imre Deakddeea5b2014-05-05 15:19:56 +03002440
2441 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2442 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2443
2444 vlv_check_no_gt_access(dev_priv);
2445
2446 err = vlv_force_gfx_clock(dev_priv, true);
2447 if (err)
2448 goto err1;
2449
2450 err = vlv_allow_gt_wake(dev_priv, false);
2451 if (err)
2452 goto err2;
Deepak S98711162014-12-12 14:18:16 +05302453
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03002454 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05302455 vlv_save_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002456
2457 err = vlv_force_gfx_clock(dev_priv, false);
2458 if (err)
2459 goto err2;
2460
2461 return 0;
2462
2463err2:
2464 /* For safety always re-enable waking and disable gfx clock forcing */
2465 vlv_allow_gt_wake(dev_priv, true);
2466err1:
2467 vlv_force_gfx_clock(dev_priv, false);
2468
2469 return err;
2470}
2471
Sagar Kamble016970b2014-08-13 23:07:06 +05302472static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2473 bool rpm_resume)
Imre Deakddeea5b2014-05-05 15:19:56 +03002474{
Imre Deakddeea5b2014-05-05 15:19:56 +03002475 int err;
2476 int ret;
2477
2478 /*
2479 * If any of the steps fail just try to continue, that's the best we
2480 * can do at this point. Return the first error code (which will also
2481 * leave RPM permanently disabled).
2482 */
2483 ret = vlv_force_gfx_clock(dev_priv, true);
2484
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03002485 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05302486 vlv_restore_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002487
2488 err = vlv_allow_gt_wake(dev_priv, true);
2489 if (!ret)
2490 ret = err;
2491
2492 err = vlv_force_gfx_clock(dev_priv, false);
2493 if (!ret)
2494 ret = err;
2495
2496 vlv_check_no_gt_access(dev_priv);
2497
Chris Wilson7c108fd2016-10-24 13:42:18 +01002498 if (rpm_resume)
Ville Syrjälä46f16e62016-10-31 22:37:22 +02002499 intel_init_clock_gating(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002500
2501 return ret;
2502}
2503
David Weinehallc49d13e2016-08-22 13:32:42 +03002504static int intel_runtime_suspend(struct device *kdev)
Paulo Zanoni8a187452013-12-06 20:32:13 -02002505{
David Weinehallc49d13e2016-08-22 13:32:42 +03002506 struct pci_dev *pdev = to_pci_dev(kdev);
Paulo Zanoni8a187452013-12-06 20:32:13 -02002507 struct drm_device *dev = pci_get_drvdata(pdev);
Chris Wilsonfac5e232016-07-04 11:34:36 +01002508 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002509 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002510
Sagar Arun Kamble37d933f2017-10-10 22:30:10 +01002511 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
Imre Deakc6df39b2014-04-14 20:24:29 +03002512 return -ENODEV;
2513
Tvrtko Ursulin6772ffe2016-10-13 11:02:55 +01002514 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
Imre Deak604effb2014-08-26 13:26:56 +03002515 return -ENODEV;
2516
Paulo Zanoni8a187452013-12-06 20:32:13 -02002517 DRM_DEBUG_KMS("Suspending device\n");
2518
Imre Deak1f814da2015-12-16 02:52:19 +02002519 disable_rpm_wakeref_asserts(dev_priv);
2520
Imre Deakd6102972014-05-07 19:57:49 +03002521 /*
2522 * We are safe here against re-faults, since the fault handler takes
2523 * an RPM reference.
2524 */
Chris Wilson7c108fd2016-10-24 13:42:18 +01002525 i915_gem_runtime_suspend(dev_priv);
Imre Deakd6102972014-05-07 19:57:49 +03002526
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00002527 intel_guc_suspend(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07002528
Imre Deak2eb52522014-11-19 15:30:05 +02002529 intel_runtime_pm_disable_interrupts(dev_priv);
Imre Deakb5478bc2014-04-14 20:24:37 +03002530
Imre Deak507e1262016-04-20 20:27:54 +03002531 ret = 0;
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02002532 if (IS_GEN9_LP(dev_priv)) {
Imre Deak507e1262016-04-20 20:27:54 +03002533 bxt_display_core_uninit(dev_priv);
2534 bxt_enable_dc9(dev_priv);
2535 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2536 hsw_enable_pc8(dev_priv);
2537 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2538 ret = vlv_suspend_complete(dev_priv);
2539 }
2540
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002541 if (ret) {
2542 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
Daniel Vetterb9632912014-09-30 10:56:44 +02002543 intel_runtime_pm_enable_interrupts(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002544
Imre Deak1f814da2015-12-16 02:52:19 +02002545 enable_rpm_wakeref_asserts(dev_priv);
2546
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002547 return ret;
2548 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03002549
Hans de Goede68f60942017-02-10 11:28:01 +01002550 intel_uncore_suspend(dev_priv);
Imre Deak1f814da2015-12-16 02:52:19 +02002551
2552 enable_rpm_wakeref_asserts(dev_priv);
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01002553 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002554
Mika Kuoppalabc3b9342016-01-08 15:51:20 +02002555 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002556 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2557
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01002558 dev_priv->runtime_pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08002559
2560 /*
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002561 * FIXME: We really should find a document that references the arguments
2562 * used below!
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08002563 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002564 if (IS_BROADWELL(dev_priv)) {
Paulo Zanonid37ae192015-07-30 18:20:29 -03002565 /*
2566 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2567 * being detected, and the call we do at intel_runtime_resume()
2568 * won't be able to restore them. Since PCI_D3hot matches the
2569 * actual specification and appears to be working, use it.
2570 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002571 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
Paulo Zanonid37ae192015-07-30 18:20:29 -03002572 } else {
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002573 /*
2574 * current versions of firmware which depend on this opregion
2575 * notification have repurposed the D1 definition to mean
2576 * "runtime suspended" vs. what you would normally expect (D3)
2577 * to distinguish it from notifications that might be sent via
2578 * the suspend path.
2579 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002580 intel_opregion_notify_adapter(dev_priv, PCI_D1);
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002581 }
Paulo Zanoni8a187452013-12-06 20:32:13 -02002582
Mika Kuoppala59bad942015-01-16 11:34:40 +02002583 assert_forcewakes_inactive(dev_priv);
Chris Wilsondc9fb092015-01-16 11:34:34 +02002584
Ander Conselvan de Oliveira21d6e0b2017-01-20 16:28:43 +02002585 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Lyude19625e82016-06-21 17:03:44 -04002586 intel_hpd_poll_init(dev_priv);
2587
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03002588 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02002589 return 0;
2590}
2591
David Weinehallc49d13e2016-08-22 13:32:42 +03002592static int intel_runtime_resume(struct device *kdev)
Paulo Zanoni8a187452013-12-06 20:32:13 -02002593{
David Weinehallc49d13e2016-08-22 13:32:42 +03002594 struct pci_dev *pdev = to_pci_dev(kdev);
Paulo Zanoni8a187452013-12-06 20:32:13 -02002595 struct drm_device *dev = pci_get_drvdata(pdev);
Chris Wilsonfac5e232016-07-04 11:34:36 +01002596 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002597 int ret = 0;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002598
Tvrtko Ursulin6772ffe2016-10-13 11:02:55 +01002599 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
Imre Deak604effb2014-08-26 13:26:56 +03002600 return -ENODEV;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002601
2602 DRM_DEBUG_KMS("Resuming device\n");
2603
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01002604 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
Imre Deak1f814da2015-12-16 02:52:19 +02002605 disable_rpm_wakeref_asserts(dev_priv);
2606
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002607 intel_opregion_notify_adapter(dev_priv, PCI_D0);
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01002608 dev_priv->runtime_pm.suspended = false;
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002609 if (intel_uncore_unclaimed_mmio(dev_priv))
2610 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02002611
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00002612 intel_guc_resume(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07002613
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02002614 if (IS_GEN9_LP(dev_priv)) {
Imre Deak507e1262016-04-20 20:27:54 +03002615 bxt_disable_dc9(dev_priv);
2616 bxt_display_core_init(dev_priv, true);
Imre Deakf62c79b2016-04-20 20:27:57 +03002617 if (dev_priv->csr.dmc_payload &&
2618 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2619 gen9_enable_dc5(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03002620 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002621 hsw_disable_pc8(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03002622 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002623 ret = vlv_resume_prepare(dev_priv, true);
Imre Deak507e1262016-04-20 20:27:54 +03002624 }
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002625
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002626 /*
2627 * No point of rolling back things in case of an error, as the best
2628 * we can do is to hope that things will still work (and disable RPM).
2629 */
Tvrtko Ursulinc6be6072016-11-16 08:55:31 +00002630 i915_gem_init_swizzling(dev_priv);
Chris Wilson83bf6d52017-02-03 12:57:17 +00002631 i915_gem_restore_fences(dev_priv);
Imre Deak92b806d2014-04-14 20:24:39 +03002632
Daniel Vetterb9632912014-09-30 10:56:44 +02002633 intel_runtime_pm_enable_interrupts(dev_priv);
Ville Syrjälä08d8a232015-08-27 23:56:08 +03002634
2635 /*
2636 * On VLV/CHV display interrupts are part of the display
2637 * power well, so hpd is reinitialized from there. For
2638 * everyone else do it here.
2639 */
Wayne Boyer666a4532015-12-09 12:29:35 -08002640 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä08d8a232015-08-27 23:56:08 +03002641 intel_hpd_init(dev_priv);
2642
Kumar, Mahesh2503a0f2017-08-17 19:15:28 +05302643 intel_enable_ipc(dev_priv);
2644
Imre Deak1f814da2015-12-16 02:52:19 +02002645 enable_rpm_wakeref_asserts(dev_priv);
2646
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002647 if (ret)
2648 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2649 else
2650 DRM_DEBUG_KMS("Device resumed\n");
2651
2652 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002653}
2654
Chris Wilson42f55512016-06-24 14:00:26 +01002655const struct dev_pm_ops i915_pm_ops = {
Imre Deak5545dbb2014-10-23 19:23:28 +03002656 /*
2657 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2658 * PMSG_RESUME]
2659 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002660 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03002661 .suspend_late = i915_pm_suspend_late,
2662 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04002663 .resume = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03002664
2665 /*
2666 * S4 event handlers
2667 * @freeze, @freeze_late : called (1) before creating the
2668 * hibernation image [PMSG_FREEZE] and
2669 * (2) after rebooting, before restoring
2670 * the image [PMSG_QUIESCE]
2671 * @thaw, @thaw_early : called (1) after creating the hibernation
2672 * image, before writing it [PMSG_THAW]
2673 * and (2) after failing to create or
2674 * restore the image [PMSG_RECOVER]
2675 * @poweroff, @poweroff_late: called after writing the hibernation
2676 * image, before rebooting [PMSG_HIBERNATE]
2677 * @restore, @restore_early : called after rebooting and restoring the
2678 * hibernation image [PMSG_RESTORE]
2679 */
Chris Wilson1f19ac22016-05-14 07:26:32 +01002680 .freeze = i915_pm_freeze,
2681 .freeze_late = i915_pm_freeze_late,
2682 .thaw_early = i915_pm_thaw_early,
2683 .thaw = i915_pm_thaw,
Imre Deak36d61e62014-10-23 19:23:24 +03002684 .poweroff = i915_pm_suspend,
Imre Deakab3be732015-03-02 13:04:41 +02002685 .poweroff_late = i915_pm_poweroff_late,
Chris Wilson1f19ac22016-05-14 07:26:32 +01002686 .restore_early = i915_pm_restore_early,
2687 .restore = i915_pm_restore,
Imre Deak5545dbb2014-10-23 19:23:28 +03002688
2689 /* S0ix (via runtime suspend) event handlers */
Paulo Zanoni97bea202014-03-07 20:12:33 -03002690 .runtime_suspend = intel_runtime_suspend,
2691 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08002692};
2693
Laurent Pinchart78b68552012-05-17 13:27:22 +02002694static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08002695 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08002696 .open = drm_gem_vm_open,
2697 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08002698};
2699
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002700static const struct file_operations i915_driver_fops = {
2701 .owner = THIS_MODULE,
2702 .open = drm_open,
2703 .release = drm_release,
2704 .unlocked_ioctl = drm_ioctl,
2705 .mmap = drm_gem_mmap,
2706 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002707 .read = drm_read,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002708 .compat_ioctl = i915_compat_ioctl,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002709 .llseek = noop_llseek,
2710};
2711
Chris Wilson0673ad42016-06-24 14:00:22 +01002712static int
2713i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2714 struct drm_file *file)
2715{
2716 return -ENODEV;
2717}
2718
2719static const struct drm_ioctl_desc i915_ioctls[] = {
2720 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2721 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2722 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2723 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2724 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2725 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2726 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2727 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2728 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2729 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2730 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2731 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2732 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2733 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2734 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2735 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2736 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2737 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2738 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
Chris Wilsonfec04452017-01-27 09:40:08 +00002739 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002740 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2741 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2742 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2743 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2744 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2745 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2746 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2747 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2748 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2749 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2750 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2751 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2752 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2753 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2754 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
Chris Wilson111dbca2017-01-10 12:10:44 +00002755 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2756 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002757 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2758 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2759 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2760 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2761 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2762 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2763 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2764 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2765 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2766 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2767 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2768 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2769 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2770 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2771 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
Robert Braggeec688e2016-11-07 19:49:47 +00002772 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01002773 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2774 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002775};
2776
Linus Torvalds1da177e2005-04-16 15:20:36 -07002777static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00002778 /* Don't use MTRRs here; the Xserver or userspace app should
2779 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11002780 */
Eric Anholt673a3942008-07-30 12:06:12 -07002781 .driver_features =
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02002782 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
Jason Ekstrandcf6e7ba2017-08-15 15:57:33 +01002783 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
Chris Wilsoncad36882017-02-10 16:35:21 +00002784 .release = i915_driver_release,
Eric Anholt673a3942008-07-30 12:06:12 -07002785 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11002786 .lastclose = i915_driver_lastclose,
Eric Anholt673a3942008-07-30 12:06:12 -07002787 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01002788
Chris Wilsonb1f788c2016-08-04 07:52:45 +01002789 .gem_close_object = i915_gem_close_object,
Chris Wilsonf0cd5182016-10-28 13:58:43 +01002790 .gem_free_object_unlocked = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08002791 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02002792
2793 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2794 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2795 .gem_prime_export = i915_gem_prime_export,
2796 .gem_prime_import = i915_gem_prime_import,
2797
Dave Airlieff72145b2011-02-07 12:16:14 +10002798 .dumb_create = i915_gem_dumb_create,
Dave Airlieda6b51d2014-12-24 13:11:17 +10002799 .dumb_map_offset = i915_gem_mmap_gtt,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002800 .ioctls = i915_ioctls,
Chris Wilson0673ad42016-06-24 14:00:22 +01002801 .num_ioctls = ARRAY_SIZE(i915_ioctls),
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002802 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11002803 .name = DRIVER_NAME,
2804 .desc = DRIVER_DESC,
2805 .date = DRIVER_DATE,
2806 .major = DRIVER_MAJOR,
2807 .minor = DRIVER_MINOR,
2808 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002809};
Chris Wilson66d9cb52017-02-13 17:15:17 +00002810
2811#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2812#include "selftests/mock_drm.c"
2813#endif