blob: 1eaedaaba09441cc5086d424463e1fae0014d226 [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
Pierre-Louis Bossart45505692020-07-01 02:43:53 +080016#include <sound/soc.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053017#include "bus.h"
18
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053019/*
20 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
21 *
22 * The rows are arranged as per the array index value programmed
23 * in register. The index 15 has dummy value 0 in order to fill hole.
24 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050025int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053026 96, 100, 120, 128, 150, 160, 250, 0,
27 192, 200, 240, 256, 72, 144, 90, 180};
Bard Liao90261182020-09-08 21:15:20 +080028EXPORT_SYMBOL(sdw_rows);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053029
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050030int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Bard Liao90261182020-09-08 21:15:20 +080031EXPORT_SYMBOL(sdw_cols);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053032
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050033int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053034{
35 int i;
36
37 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050038 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053039 return i;
40 }
41
42 pr_warn("Requested column not found, selecting lowest column no: 2\n");
43 return 0;
44}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050045EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053046
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050047int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053048{
49 int i;
50
51 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050052 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053053 return i;
54 }
55
56 pr_warn("Requested row not found, selecting lowest row no: 48\n");
57 return 0;
58}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050059EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053060
Sanyog Kalef8101c72018-04-26 18:38:17 +053061static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050062 struct sdw_slave *slave,
63 struct sdw_transport_params *t_params,
64 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053065{
66 u32 addr1, addr2, addr3, addr4;
67 int ret;
68 u16 wbuf;
69
70 if (bus->params.next_bank) {
71 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
72 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
73 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
74 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
75 } else {
76 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
77 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
78 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
79 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
80 }
81
82 /* Program DPN_OffsetCtrl2 registers */
83 ret = sdw_write(slave, addr1, t_params->offset2);
84 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050085 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053086 return ret;
87 }
88
89 /* Program DPN_BlockCtrl3 register */
90 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
91 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050092 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053093 return ret;
94 }
95
96 /*
97 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053098 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053099 * handled, so bail out if we are not FULL data port type
100 */
101 if (type != SDW_DPN_FULL)
102 return ret;
103
104 /* Program DPN_SampleCtrl2 register */
Vinod Koul41ff9172020-09-03 17:14:59 +0530105 wbuf = FIELD_GET(SDW_DPN_SAMPLECTRL_HIGH, t_params->sample_interval - 1);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530106
107 ret = sdw_write(slave, addr3, wbuf);
108 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500109 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530110 return ret;
111 }
112
113 /* Program DPN_HCtrl register */
Vinod Koul41ff9172020-09-03 17:14:59 +0530114 wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart);
115 wbuf |= FIELD_PREP(SDW_DPN_HCTRL_HSTOP, t_params->hstop);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530116
117 ret = sdw_write(slave, addr4, wbuf);
118 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500119 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530120
121 return ret;
122}
123
124static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500125 struct sdw_slave_runtime *s_rt,
126 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530127{
128 struct sdw_transport_params *t_params = &p_rt->transport_params;
129 struct sdw_port_params *p_params = &p_rt->port_params;
130 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
131 u32 addr1, addr2, addr3, addr4, addr5, addr6;
132 struct sdw_dpn_prop *dpn_prop;
133 int ret;
134 u8 wbuf;
135
136 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500137 s_rt->direction,
138 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530139 if (!dpn_prop)
140 return -EINVAL;
141
142 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
143 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
144
145 if (bus->params.next_bank) {
146 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
147 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
148 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
149 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
150
151 } else {
152 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
153 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
154 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
155 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
156 }
157
158 /* Program DPN_PortCtrl register */
Vinod Koul41ff9172020-09-03 17:14:59 +0530159 wbuf = FIELD_PREP(SDW_DPN_PORTCTRL_DATAMODE, p_params->data_mode);
160 wbuf |= FIELD_PREP(SDW_DPN_PORTCTRL_FLOWMODE, p_params->flow_mode);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530161
162 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
163 if (ret < 0) {
164 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500165 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530166 t_params->port_num);
167 return ret;
168 }
169
Srinivas Kandagatlaa9107de2020-03-11 11:35:44 +0000170 if (!dpn_prop->read_only_wordlength) {
171 /* Program DPN_BlockCtrl1 register */
172 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
173 if (ret < 0) {
174 dev_err(&s_rt->slave->dev,
175 "DPN_BlockCtrl1 register write failed for port %d\n",
176 t_params->port_num);
177 return ret;
178 }
Sanyog Kalef8101c72018-04-26 18:38:17 +0530179 }
180
181 /* Program DPN_SampleCtrl1 register */
182 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
183 ret = sdw_write(s_rt->slave, addr3, wbuf);
184 if (ret < 0) {
185 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500186 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530187 t_params->port_num);
188 return ret;
189 }
190
191 /* Program DPN_OffsetCtrl1 registers */
192 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
193 if (ret < 0) {
194 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500195 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530196 t_params->port_num);
197 return ret;
198 }
199
200 /* Program DPN_BlockCtrl2 register*/
201 if (t_params->blk_grp_ctrl_valid) {
202 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
203 if (ret < 0) {
204 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500205 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530206 t_params->port_num);
207 return ret;
208 }
209 }
210
211 /* program DPN_LaneCtrl register */
212 if (slave_prop->lane_control_support) {
213 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
214 if (ret < 0) {
215 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500216 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530217 t_params->port_num);
218 return ret;
219 }
220 }
221
222 if (dpn_prop->type != SDW_DPN_SIMPLE) {
223 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500224 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530225 if (ret < 0)
226 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500227 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530228 t_params->port_num);
229 }
230
231 return ret;
232}
233
234static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500235 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530236{
237 int ret;
238
239 /*
240 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530241 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530242 * hstart/stop etc of the data. Port parameters refers to word
243 * length, flow mode etc of the port
244 */
245 ret = bus->port_ops->dpn_set_port_transport_params(bus,
246 &p_rt->transport_params,
247 bus->params.next_bank);
248 if (ret < 0)
249 return ret;
250
251 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500252 &p_rt->port_params,
253 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530254}
255
256/**
257 * sdw_program_port_params() - Programs transport parameters of Master(s)
258 * and Slave(s)
259 *
260 * @m_rt: Master stream runtime
261 */
262static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
263{
Pierre-Louis Bossart5920a292021-03-02 17:11:21 +0800264 struct sdw_slave_runtime *s_rt;
Sanyog Kalef8101c72018-04-26 18:38:17 +0530265 struct sdw_bus *bus = m_rt->bus;
266 struct sdw_port_runtime *p_rt;
267 int ret = 0;
268
269 /* Program transport & port parameters for Slave(s) */
270 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
271 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
272 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
273 if (ret < 0)
274 return ret;
275 }
276 }
277
278 /* Program transport & port parameters for Master(s) */
279 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
280 ret = sdw_program_master_port_params(bus, p_rt);
281 if (ret < 0)
282 return ret;
283 }
284
285 return 0;
286}
287
Sanyog Kale89e59052018-04-26 18:38:08 +0530288/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530289 * sdw_enable_disable_slave_ports: Enable/disable slave data port
290 *
291 * @bus: bus instance
292 * @s_rt: slave runtime
293 * @p_rt: port runtime
294 * @en: enable or disable operation
295 *
296 * This function only sets the enable/disable bits in the relevant bank, the
297 * actual enable/disable is done with a bank switch
298 */
299static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500300 struct sdw_slave_runtime *s_rt,
301 struct sdw_port_runtime *p_rt,
302 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530303{
304 struct sdw_transport_params *t_params = &p_rt->transport_params;
305 u32 addr;
306 int ret;
307
308 if (bus->params.next_bank)
309 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
310 else
311 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
312
313 /*
314 * Since bus doesn't support sharing a port across two streams,
315 * it is safe to reset this register
316 */
317 if (en)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000318 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530319 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000320 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530321
322 if (ret < 0)
323 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500324 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530325 ret, t_params->port_num);
326
327 return ret;
328}
329
330static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500331 struct sdw_port_runtime *p_rt,
332 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530333{
334 struct sdw_transport_params *t_params = &p_rt->transport_params;
335 struct sdw_bus *bus = m_rt->bus;
336 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500337 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530338
339 enable_ch.port_num = p_rt->num;
340 enable_ch.ch_mask = p_rt->ch_mask;
341 enable_ch.enable = en;
342
343 /* Perform Master port channel(s) enable/disable */
344 if (bus->port_ops->dpn_port_enable_ch) {
345 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500346 &enable_ch,
347 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530348 if (ret < 0) {
349 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500350 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530351 ret, t_params->port_num);
352 return ret;
353 }
354 } else {
355 dev_err(bus->dev,
356 "dpn_port_enable_ch not supported, %s failed\n",
357 en ? "enable" : "disable");
358 return -EINVAL;
359 }
360
361 return 0;
362}
363
364/**
365 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
366 * Slave(s)
367 *
368 * @m_rt: Master stream runtime
369 * @en: mode (enable/disable)
370 */
371static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
372{
373 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500374 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530375 int ret = 0;
376
377 /* Enable/Disable Slave port(s) */
378 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
379 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
380 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500381 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530382 if (ret < 0)
383 return ret;
384 }
385 }
386
387 /* Enable/Disable Master port(s) */
388 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
389 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
390 if (ret < 0)
391 return ret;
392 }
393
394 return 0;
395}
396
397static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500398 struct sdw_prepare_ch prep_ch,
399 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530400{
401 const struct sdw_slave_ops *ops = s_rt->slave->ops;
402 int ret;
403
404 if (ops->port_prep) {
405 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
406 if (ret < 0) {
407 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530408 "Slave Port Prep cmd %d failed: %d\n",
409 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530410 return ret;
411 }
412 }
413
414 return 0;
415}
416
417static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500418 struct sdw_slave_runtime *s_rt,
419 struct sdw_port_runtime *p_rt,
420 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530421{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500422 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530423 struct sdw_dpn_prop *dpn_prop;
424 struct sdw_prepare_ch prep_ch;
425 unsigned int time_left;
426 bool intr = false;
427 int ret = 0, val;
428 u32 addr;
429
430 prep_ch.num = p_rt->num;
431 prep_ch.ch_mask = p_rt->ch_mask;
432
433 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500434 s_rt->direction,
435 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530436 if (!dpn_prop) {
437 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500438 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530439 return -EINVAL;
440 }
441
442 prep_ch.prepare = prep;
443
444 prep_ch.bank = bus->params.next_bank;
445
Pierre-Louis Bossartdd87a722020-09-21 03:32:05 +0800446 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm ||
447 bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530448 intr = true;
449
450 /*
451 * Enable interrupt before Port prepare.
452 * For Port de-prepare, it is assumed that port
453 * was prepared earlier
454 */
455 if (prep && intr) {
456 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500457 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530458 if (ret < 0)
459 return ret;
460 }
461
462 /* Inform slave about the impending port prepare */
463 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
464
465 /* Prepare Slave port implementing CP_SM */
466 if (!dpn_prop->simple_ch_prep_sm) {
467 addr = SDW_DPN_PREPARECTRL(p_rt->num);
468
469 if (prep)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000470 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530471 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000472 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530473
474 if (ret < 0) {
475 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500476 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530477 return ret;
478 }
479
480 /* Wait for completion on port ready */
481 port_ready = &s_rt->slave->port_ready[prep_ch.num];
482 time_left = wait_for_completion_timeout(port_ready,
483 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
484
485 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
486 val &= p_rt->ch_mask;
487 if (!time_left || val) {
488 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500489 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530490 return -ETIMEDOUT;
491 }
492 }
493
494 /* Inform slaves about ports prepared */
495 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
496
497 /* Disable interrupt after Port de-prepare */
498 if (!prep && intr)
499 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500500 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530501
502 return ret;
503}
504
505static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500506 struct sdw_port_runtime *p_rt,
507 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530508{
509 struct sdw_transport_params *t_params = &p_rt->transport_params;
510 struct sdw_bus *bus = m_rt->bus;
511 const struct sdw_master_port_ops *ops = bus->port_ops;
512 struct sdw_prepare_ch prep_ch;
513 int ret = 0;
514
515 prep_ch.num = p_rt->num;
516 prep_ch.ch_mask = p_rt->ch_mask;
517 prep_ch.prepare = prep; /* Prepare/De-prepare */
518 prep_ch.bank = bus->params.next_bank;
519
520 /* Pre-prepare/Pre-deprepare port(s) */
521 if (ops->dpn_port_prep) {
522 ret = ops->dpn_port_prep(bus, &prep_ch);
523 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500524 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500525 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530526 return ret;
527 }
528 }
529
530 return ret;
531}
532
533/**
534 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
535 * Slave(s)
536 *
537 * @m_rt: Master runtime handle
538 * @prep: Prepare or De-prepare
539 */
540static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
541{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500542 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530543 struct sdw_port_runtime *p_rt;
544 int ret = 0;
545
546 /* Prepare/De-prepare Slave port(s) */
547 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
548 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
549 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500550 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530551 if (ret < 0)
552 return ret;
553 }
554 }
555
556 /* Prepare/De-prepare Master port(s) */
557 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
558 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
559 if (ret < 0)
560 return ret;
561 }
562
563 return ret;
564}
565
566/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530567 * sdw_notify_config() - Notify bus configuration
568 *
569 * @m_rt: Master runtime handle
570 *
571 * This function notifies the Master(s) and Slave(s) of the
572 * new bus configuration.
573 */
574static int sdw_notify_config(struct sdw_master_runtime *m_rt)
575{
576 struct sdw_slave_runtime *s_rt;
577 struct sdw_bus *bus = m_rt->bus;
578 struct sdw_slave *slave;
579 int ret = 0;
580
581 if (bus->ops->set_bus_conf) {
582 ret = bus->ops->set_bus_conf(bus, &bus->params);
583 if (ret < 0)
584 return ret;
585 }
586
587 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
588 slave = s_rt->slave;
589
590 if (slave->ops->bus_config) {
591 ret = slave->ops->bus_config(slave, &bus->params);
Rander Wang60835022020-01-14 17:52:26 -0600592 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500593 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500594 slave->dev_num);
Rander Wang60835022020-01-14 17:52:26 -0600595 return ret;
596 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530597 }
598 }
599
600 return ret;
601}
602
603/**
604 * sdw_program_params() - Program transport and port parameters for Master(s)
605 * and Slave(s)
606 *
607 * @bus: SDW bus instance
Rander Wangbfaa3542020-01-14 17:52:27 -0600608 * @prepare: true if sdw_program_params() is called by _prepare.
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530609 */
Rander Wangbfaa3542020-01-14 17:52:27 -0600610static int sdw_program_params(struct sdw_bus *bus, bool prepare)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530611{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500612 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530613 int ret = 0;
614
615 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
Rander Wangbfaa3542020-01-14 17:52:27 -0600616
617 /*
618 * this loop walks through all master runtimes for a
619 * bus, but the ports can only be configured while
620 * explicitly preparing a stream or handling an
621 * already-prepared stream otherwise.
622 */
623 if (!prepare &&
624 m_rt->stream->state == SDW_STREAM_CONFIGURED)
625 continue;
626
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530627 ret = sdw_program_port_params(m_rt);
628 if (ret < 0) {
629 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500630 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530631 return ret;
632 }
633
634 ret = sdw_notify_config(m_rt);
635 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530636 dev_err(bus->dev,
637 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530638 return ret;
639 }
640
641 /* Enable port(s) on alternate bank for all active streams */
642 if (m_rt->stream->state != SDW_STREAM_ENABLED)
643 continue;
644
645 ret = sdw_enable_disable_ports(m_rt, true);
646 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500647 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530648 return ret;
649 }
650 }
651
652 return ret;
653}
654
Shreyas NCce6e74d2018-07-27 14:44:16 +0530655static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530656{
657 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530658 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530659 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500660 u8 *wbuf;
661 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530662 u16 addr;
663
664 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
665 if (!wr_msg)
666 return -ENOMEM;
667
Shreyas NCce6e74d2018-07-27 14:44:16 +0530668 bus->defer_msg.msg = wr_msg;
669
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530670 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
671 if (!wbuf) {
672 ret = -ENOMEM;
673 goto error_1;
674 }
675
676 /* Get row and column index to program register */
677 col_index = sdw_find_col_index(bus->params.col);
678 row_index = sdw_find_row_index(bus->params.row);
679 wbuf[0] = col_index | (row_index << 3);
680
681 if (bus->params.next_bank)
682 addr = SDW_SCP_FRAMECTRL_B1;
683 else
684 addr = SDW_SCP_FRAMECTRL_B0;
685
686 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500687 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530688 wr_msg->ssp_sync = true;
689
Shreyas NCce6e74d2018-07-27 14:44:16 +0530690 /*
691 * Set the multi_link flag only when both the hardware supports
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800692 * and hardware-based sync is required
Shreyas NCce6e74d2018-07-27 14:44:16 +0530693 */
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800694 multi_link = bus->multi_link && (m_rt_count >= bus->hw_sync_min_links);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530695
696 if (multi_link)
697 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
698 else
699 ret = sdw_transfer(bus, wr_msg);
700
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530701 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500702 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530703 goto error;
704 }
705
Shreyas NCce6e74d2018-07-27 14:44:16 +0530706 if (!multi_link) {
707 kfree(wr_msg);
708 kfree(wbuf);
709 bus->defer_msg.msg = NULL;
710 bus->params.curr_bank = !bus->params.curr_bank;
711 bus->params.next_bank = !bus->params.next_bank;
712 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530713
714 return 0;
715
716error:
717 kfree(wbuf);
718error_1:
719 kfree(wr_msg);
Tom Rix3fbbf212020-09-02 13:26:50 -0700720 bus->defer_msg.msg = NULL;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530721 return ret;
722}
723
Shreyas NCce6e74d2018-07-27 14:44:16 +0530724/**
725 * sdw_ml_sync_bank_switch: Multilink register bank switch
726 *
727 * @bus: SDW bus instance
728 *
729 * Caller function should free the buffers on error
730 */
731static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
732{
733 unsigned long time_left;
734
735 if (!bus->multi_link)
736 return 0;
737
738 /* Wait for completion of transfer */
739 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
740 bus->bank_switch_timeout);
741
742 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500743 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530744 return -ETIMEDOUT;
745 }
746
747 bus->params.curr_bank = !bus->params.curr_bank;
748 bus->params.next_bank = !bus->params.next_bank;
749
750 if (bus->defer_msg.msg) {
751 kfree(bus->defer_msg.msg->buf);
752 kfree(bus->defer_msg.msg);
753 }
754
755 return 0;
756}
757
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530758static int do_bank_switch(struct sdw_stream_runtime *stream)
759{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500760 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530761 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500762 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530763 bool multi_link = false;
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800764 int m_rt_count;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530765 int ret = 0;
766
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800767 m_rt_count = stream->m_rt_count;
768
Vinod Koul48949722018-07-27 14:44:14 +0530769 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
770 bus = m_rt->bus;
771 ops = bus->ops;
772
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800773 if (bus->multi_link && m_rt_count >= bus->hw_sync_min_links) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530774 multi_link = true;
775 mutex_lock(&bus->msg_lock);
776 }
777
Vinod Koul48949722018-07-27 14:44:14 +0530778 /* Pre-bank switch */
779 if (ops->pre_bank_switch) {
780 ret = ops->pre_bank_switch(bus);
781 if (ret < 0) {
782 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500783 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530784 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530785 }
786 }
787
Shreyas NCce6e74d2018-07-27 14:44:16 +0530788 /*
789 * Perform Bank switch operation.
790 * For multi link cases, the actual bank switch is
791 * synchronized across all Masters and happens later as a
792 * part of post_bank_switch ops.
793 */
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800794 ret = sdw_bank_switch(bus, m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530795 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500796 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530797 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530798 }
799 }
800
Shreyas NCce6e74d2018-07-27 14:44:16 +0530801 /*
802 * For multi link cases, it is expected that the bank switch is
803 * triggered by the post_bank_switch for the first Master in the list
804 * and for the other Masters the post_bank_switch() should return doing
805 * nothing.
806 */
Vinod Koul48949722018-07-27 14:44:14 +0530807 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
808 bus = m_rt->bus;
809 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530810
Vinod Koul48949722018-07-27 14:44:14 +0530811 /* Post-bank switch */
812 if (ops->post_bank_switch) {
813 ret = ops->post_bank_switch(bus);
814 if (ret < 0) {
815 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530816 "Post bank switch op failed: %d\n",
817 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530818 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530819 }
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800820 } else if (multi_link) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530821 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500822 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530823 goto error;
824 }
825
826 /* Set the bank switch timeout to default, if not set */
827 if (!bus->bank_switch_timeout)
828 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
829
830 /* Check if bank switch was successful */
831 ret = sdw_ml_sync_bank_switch(bus);
832 if (ret < 0) {
833 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500834 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530835 goto error;
836 }
837
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800838 if (multi_link)
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100839 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530840 }
841
842 return ret;
843
844error:
845 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530846 bus = m_rt->bus;
Tom Rix3fbbf212020-09-02 13:26:50 -0700847 if (bus->defer_msg.msg) {
848 kfree(bus->defer_msg.msg->buf);
849 kfree(bus->defer_msg.msg);
850 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530851 }
852
853msg_unlock:
854
855 if (multi_link) {
856 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
857 bus = m_rt->bus;
858 if (mutex_is_locked(&bus->msg_lock))
859 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530860 }
861 }
862
863 return ret;
864}
865
866/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530867 * sdw_release_stream() - Free the assigned stream runtime
868 *
869 * @stream: SoundWire stream runtime
870 *
871 * sdw_release_stream should be called only once per stream
872 */
873void sdw_release_stream(struct sdw_stream_runtime *stream)
874{
875 kfree(stream);
876}
877EXPORT_SYMBOL(sdw_release_stream);
878
879/**
880 * sdw_alloc_stream() - Allocate and return stream runtime
881 *
882 * @stream_name: SoundWire stream name
883 *
884 * Allocates a SoundWire stream runtime instance.
885 * sdw_alloc_stream should be called only once per stream. Typically
886 * invoked from ALSA/ASoC machine/platform driver.
887 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100888struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530889{
890 struct sdw_stream_runtime *stream;
891
892 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
893 if (!stream)
894 return NULL;
895
896 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530897 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530898 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530899 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530900
901 return stream;
902}
903EXPORT_SYMBOL(sdw_alloc_stream);
904
Vinod Koul48949722018-07-27 14:44:14 +0530905static struct sdw_master_runtime
906*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500907 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530908{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500909 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530910
911 /* Retrieve Bus handle if already available */
912 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
913 if (m_rt->bus == bus)
914 return m_rt;
915 }
916
917 return NULL;
918}
919
Sanyog Kale89e59052018-04-26 18:38:08 +0530920/**
921 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
922 *
923 * @bus: SDW bus instance
924 * @stream_config: Stream configuration
925 * @stream: Stream runtime handle.
926 *
927 * This function is to be called with bus_lock held.
928 */
929static struct sdw_master_runtime
930*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500931 struct sdw_stream_config *stream_config,
932 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530933{
934 struct sdw_master_runtime *m_rt;
935
Sanyog Kale89e59052018-04-26 18:38:08 +0530936 /*
937 * check if Master is already allocated (as a result of Slave adding
938 * it first), if so skip allocation and go to configure
939 */
Vinod Koul48949722018-07-27 14:44:14 +0530940 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530941 if (m_rt)
942 goto stream_config;
943
944 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
945 if (!m_rt)
946 return NULL;
947
948 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530949 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530950 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530951 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530952
953 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
954
955stream_config:
956 m_rt->ch_count = stream_config->ch_count;
957 m_rt->bus = bus;
958 m_rt->stream = stream;
959 m_rt->direction = stream_config->direction;
960
961 return m_rt;
962}
963
964/**
965 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
966 *
967 * @slave: Slave handle
968 * @stream_config: Stream configuration
969 * @stream: Stream runtime handle
970 *
971 * This function is to be called with bus_lock held.
972 */
973static struct sdw_slave_runtime
974*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500975 struct sdw_stream_config *stream_config,
976 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530977{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500978 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530979
980 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
981 if (!s_rt)
982 return NULL;
983
Sanyog Kalebbe73792018-04-26 18:38:13 +0530984 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530985 s_rt->ch_count = stream_config->ch_count;
986 s_rt->direction = stream_config->direction;
987 s_rt->slave = slave;
988
989 return s_rt;
990}
991
Sanyog Kalebbe73792018-04-26 18:38:13 +0530992static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500993 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530994{
995 struct sdw_port_runtime *p_rt, *_p_rt;
996
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500997 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530998 list_del(&p_rt->port_node);
999 kfree(p_rt);
1000 }
1001}
1002
1003static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001004 struct sdw_slave *slave,
1005 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301006{
1007 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301008 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +05301009 struct sdw_slave_runtime *s_rt;
1010
Vinod Koul48949722018-07-27 14:44:14 +05301011 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1012 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301013 if (s_rt->slave != slave)
1014 continue;
1015
1016 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001017 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301018 list_del(&p_rt->port_node);
1019 kfree(p_rt);
1020 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301021 }
1022 }
1023}
1024
Sanyog Kale89e59052018-04-26 18:38:08 +05301025/**
1026 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1027 *
1028 * @slave: Slave handle.
1029 * @stream: Stream runtime handle.
1030 *
1031 * This function is to be called with bus_lock held.
1032 */
1033static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001034 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301035{
1036 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301037 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301038
Vinod Koul48949722018-07-27 14:44:14 +05301039 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1040 /* Retrieve Slave runtime handle */
1041 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001042 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301043 if (s_rt->slave == slave) {
1044 list_del(&s_rt->m_rt_node);
1045 kfree(s_rt);
1046 return;
1047 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301048 }
1049 }
1050}
1051
1052/**
1053 * sdw_release_master_stream() - Free Master runtime handle
1054 *
Vinod Koul48949722018-07-27 14:44:14 +05301055 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301056 * @stream: Stream runtime handle.
1057 *
1058 * This function is to be called with bus_lock held
1059 * It frees the Master runtime handle and associated Slave(s) runtime
1060 * handle. If this is called first then sdw_release_slave_stream() will have
1061 * no effect as Slave(s) runtime handle would already be freed up.
1062 */
Vinod Koul48949722018-07-27 14:44:14 +05301063static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001064 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301065{
Sanyog Kale89e59052018-04-26 18:38:08 +05301066 struct sdw_slave_runtime *s_rt, *_s_rt;
1067
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301068 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1069 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1070 sdw_release_slave_stream(s_rt->slave, stream);
1071 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301072
Vinod Koul48949722018-07-27 14:44:14 +05301073 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301074 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301075 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301076}
1077
1078/**
1079 * sdw_stream_remove_master() - Remove master from sdw_stream
1080 *
1081 * @bus: SDW Bus instance
1082 * @stream: SoundWire stream
1083 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301084 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301085 */
1086int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001087 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301088{
Vinod Koul48949722018-07-27 14:44:14 +05301089 struct sdw_master_runtime *m_rt, *_m_rt;
1090
Sanyog Kale89e59052018-04-26 18:38:08 +05301091 mutex_lock(&bus->bus_lock);
1092
Vinod Koul48949722018-07-27 14:44:14 +05301093 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001094 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301095 if (m_rt->bus != bus)
1096 continue;
1097
1098 sdw_master_port_release(bus, m_rt);
1099 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301100 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301101 }
1102
1103 if (list_empty(&stream->master_list))
1104 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301105
1106 mutex_unlock(&bus->bus_lock);
1107
1108 return 0;
1109}
1110EXPORT_SYMBOL(sdw_stream_remove_master);
1111
1112/**
1113 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1114 *
1115 * @slave: SDW Slave instance
1116 * @stream: SoundWire stream
1117 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301118 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301119 */
1120int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001121 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301122{
1123 mutex_lock(&slave->bus->bus_lock);
1124
Sanyog Kalebbe73792018-04-26 18:38:13 +05301125 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301126 sdw_release_slave_stream(slave, stream);
1127
1128 mutex_unlock(&slave->bus->bus_lock);
1129
1130 return 0;
1131}
1132EXPORT_SYMBOL(sdw_stream_remove_slave);
1133
1134/**
1135 * sdw_config_stream() - Configure the allocated stream
1136 *
1137 * @dev: SDW device
1138 * @stream: SoundWire stream
1139 * @stream_config: Stream configuration for audio stream
1140 * @is_slave: is API called from Slave or Master
1141 *
1142 * This function is to be called with bus_lock held.
1143 */
1144static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001145 struct sdw_stream_runtime *stream,
1146 struct sdw_stream_config *stream_config,
1147 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301148{
1149 /*
1150 * Update the stream rate, channel and bps based on data
1151 * source. For more than one data source (multilink),
1152 * match the rate, bps, stream type and increment number of channels.
1153 *
1154 * If rate/bps is zero, it means the values are not set, so skip
1155 * comparison and allow the value to be set and stored in stream
1156 */
1157 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001158 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001159 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301160 return -EINVAL;
1161 }
1162
1163 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001164 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001165 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301166 return -EINVAL;
1167 }
1168
1169 stream->type = stream_config->type;
1170 stream->params.rate = stream_config->frame_rate;
1171 stream->params.bps = stream_config->bps;
1172
1173 /* TODO: Update this check during Device-device support */
1174 if (is_slave)
1175 stream->params.ch_count += stream_config->ch_count;
1176
1177 return 0;
1178}
1179
Sanyog Kalebbe73792018-04-26 18:38:13 +05301180static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001181 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301182{
1183 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1184 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001185 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301186 return -EINVAL;
1187 }
1188
1189 return 0;
1190}
1191
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001192static struct sdw_port_runtime
1193*sdw_port_alloc(struct device *dev,
1194 struct sdw_port_config *port_config,
1195 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301196{
1197 struct sdw_port_runtime *p_rt;
1198
1199 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1200 if (!p_rt)
1201 return NULL;
1202
1203 p_rt->ch_mask = port_config[port_index].ch_mask;
1204 p_rt->num = port_config[port_index].num;
1205
1206 return p_rt;
1207}
1208
1209static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001210 struct sdw_master_runtime *m_rt,
1211 struct sdw_port_config *port_config,
1212 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301213{
1214 struct sdw_port_runtime *p_rt;
1215 int i;
1216
1217 /* Iterate for number of ports to perform initialization */
1218 for (i = 0; i < num_ports; i++) {
1219 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1220 if (!p_rt)
1221 return -ENOMEM;
1222
1223 /*
1224 * TODO: Check port capabilities for requested
1225 * configuration (audio mode support)
1226 */
1227
1228 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1229 }
1230
1231 return 0;
1232}
1233
1234static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001235 struct sdw_slave_runtime *s_rt,
1236 struct sdw_port_config *port_config,
1237 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301238{
1239 struct sdw_port_runtime *p_rt;
1240 int i, ret;
1241
1242 /* Iterate for number of ports to perform initialization */
1243 for (i = 0; i < num_config; i++) {
1244 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1245 if (!p_rt)
1246 return -ENOMEM;
1247
1248 /*
1249 * TODO: Check valid port range as defined by DisCo/
1250 * slave
1251 */
1252 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1253 if (ret < 0) {
1254 kfree(p_rt);
1255 return ret;
1256 }
1257
1258 /*
1259 * TODO: Check port capabilities for requested
1260 * configuration (audio mode support)
1261 */
1262
1263 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1264 }
1265
1266 return 0;
1267}
1268
Sanyog Kale89e59052018-04-26 18:38:08 +05301269/**
1270 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1271 *
1272 * @bus: SDW Bus instance
1273 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301274 * @port_config: Port configuration for audio stream
1275 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301276 * @stream: SoundWire stream
1277 */
1278int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001279 struct sdw_stream_config *stream_config,
1280 struct sdw_port_config *port_config,
1281 unsigned int num_ports,
1282 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301283{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001284 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301285 int ret;
1286
1287 mutex_lock(&bus->bus_lock);
1288
Shreyas NCce6e74d2018-07-27 14:44:16 +05301289 /*
1290 * For multi link streams, add the second master only if
1291 * the bus supports it.
1292 * Check if bus->multi_link is set
1293 */
1294 if (!bus->multi_link && stream->m_rt_count > 0) {
1295 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001296 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301297 ret = -EINVAL;
1298 goto unlock;
1299 }
1300
Sanyog Kale89e59052018-04-26 18:38:08 +05301301 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1302 if (!m_rt) {
1303 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001304 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001305 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301306 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301307 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301308 }
1309
1310 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1311 if (ret)
1312 goto stream_error;
1313
Sanyog Kalebbe73792018-04-26 18:38:13 +05301314 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1315 if (ret)
1316 goto stream_error;
1317
Shreyas NCce6e74d2018-07-27 14:44:16 +05301318 stream->m_rt_count++;
1319
Shreyas NC3fef1a22018-07-27 14:44:09 +05301320 goto unlock;
1321
Sanyog Kale89e59052018-04-26 18:38:08 +05301322stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301323 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301324unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301325 mutex_unlock(&bus->bus_lock);
1326 return ret;
1327}
1328EXPORT_SYMBOL(sdw_stream_add_master);
1329
1330/**
1331 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1332 *
1333 * @slave: SDW Slave instance
1334 * @stream_config: Stream configuration for audio stream
1335 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301336 * @port_config: Port configuration for audio stream
1337 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301338 *
1339 * It is expected that Slave is added before adding Master
1340 * to the Stream.
1341 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301342 */
1343int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001344 struct sdw_stream_config *stream_config,
1345 struct sdw_port_config *port_config,
1346 unsigned int num_ports,
1347 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301348{
1349 struct sdw_slave_runtime *s_rt;
1350 struct sdw_master_runtime *m_rt;
1351 int ret;
1352
1353 mutex_lock(&slave->bus->bus_lock);
1354
1355 /*
1356 * If this API is invoked by Slave first then m_rt is not valid.
1357 * So, allocate m_rt and add Slave to it.
1358 */
1359 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1360 if (!m_rt) {
1361 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001362 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001363 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301364 ret = -ENOMEM;
1365 goto error;
1366 }
1367
1368 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1369 if (!s_rt) {
1370 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001371 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001372 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301373 ret = -ENOMEM;
1374 goto stream_error;
1375 }
1376
1377 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
Rander Wang48f17f92021-03-31 08:46:10 +08001378 if (ret) {
1379 /*
1380 * sdw_release_master_stream will release s_rt in slave_rt_list in
1381 * stream_error case, but s_rt is only added to slave_rt_list
1382 * when sdw_config_stream is successful, so free s_rt explicitly
1383 * when sdw_config_stream is failed.
1384 */
1385 kfree(s_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301386 goto stream_error;
Rander Wang48f17f92021-03-31 08:46:10 +08001387 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301388
1389 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1390
Sanyog Kalebbe73792018-04-26 18:38:13 +05301391 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1392 if (ret)
1393 goto stream_error;
1394
Shreyas NC0aebe402018-07-27 14:44:08 +05301395 /*
1396 * Change stream state to CONFIGURED on first Slave add.
1397 * Bus is not aware of number of Slave(s) in a stream at this
1398 * point so cannot depend on all Slave(s) to be added in order to
1399 * change stream state to CONFIGURED.
1400 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301401 stream->state = SDW_STREAM_CONFIGURED;
1402 goto error;
1403
1404stream_error:
1405 /*
1406 * we hit error so cleanup the stream, release all Slave(s) and
1407 * Master runtime
1408 */
Vinod Koul48949722018-07-27 14:44:14 +05301409 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301410error:
1411 mutex_unlock(&slave->bus->bus_lock);
1412 return ret;
1413}
1414EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301415
1416/**
1417 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1418 *
1419 * @slave: Slave handle
1420 * @direction: Data direction.
1421 * @port_num: Port number
1422 */
1423struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001424 enum sdw_data_direction direction,
1425 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301426{
1427 struct sdw_dpn_prop *dpn_prop;
1428 u8 num_ports;
1429 int i;
1430
1431 if (direction == SDW_DATA_DIR_TX) {
1432 num_ports = hweight32(slave->prop.source_ports);
1433 dpn_prop = slave->prop.src_dpn_prop;
1434 } else {
1435 num_ports = hweight32(slave->prop.sink_ports);
1436 dpn_prop = slave->prop.sink_dpn_prop;
1437 }
1438
1439 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001440 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301441 return &dpn_prop[i];
1442 }
1443
1444 return NULL;
1445}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301446
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301447/**
1448 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1449 *
1450 * @stream: SoundWire stream
1451 *
1452 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1453 * stream to reconfigure the bus.
1454 * NOTE: This function is called from SoundWire stream ops and is
1455 * expected that a global lock is held before acquiring bus_lock.
1456 */
1457static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1458{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001459 struct sdw_master_runtime *m_rt;
Pierre-Louis Bossart53e0a302021-03-02 17:11:22 +08001460 struct sdw_bus *bus;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301461
1462 /* Iterate for all Master(s) in Master list */
1463 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1464 bus = m_rt->bus;
1465
1466 mutex_lock(&bus->bus_lock);
1467 }
1468}
1469
1470/**
1471 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1472 *
1473 * @stream: SoundWire stream
1474 *
1475 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301476 * NOTE: This function is called from SoundWire stream ops and is
1477 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301478 */
1479static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1480{
Pierre-Louis Bossart5920a292021-03-02 17:11:21 +08001481 struct sdw_master_runtime *m_rt;
Pierre-Louis Bossart53e0a302021-03-02 17:11:22 +08001482 struct sdw_bus *bus;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301483
1484 /* Iterate for all Master(s) in Master list */
1485 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1486 bus = m_rt->bus;
1487 mutex_unlock(&bus->bus_lock);
1488 }
1489}
1490
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001491static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1492 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301493{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001494 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301495 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001496 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301497 struct sdw_bus_params params;
1498 int ret;
1499
Vinod Koul48949722018-07-27 14:44:14 +05301500 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1501 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1502 bus = m_rt->bus;
1503 prop = &bus->prop;
1504 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301505
Vinod Koul48949722018-07-27 14:44:14 +05301506 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001507 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001508 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301509 return -EINVAL;
1510 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301511
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001512 if (!update_params)
1513 goto program_params;
1514
Vinod Koul48949722018-07-27 14:44:14 +05301515 /* Increment cumulative bus bandwidth */
1516 /* TODO: Update this during Device-Device support */
1517 bus->params.bandwidth += m_rt->stream->params.rate *
1518 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301519
Vinod Koulc7578c12019-08-13 09:35:46 +01001520 /* Compute params */
1521 if (bus->compute_params) {
1522 ret = bus->compute_params(bus);
1523 if (ret < 0) {
Pierre-Louis Bossart6122d3b2021-03-23 08:58:54 +08001524 dev_err(bus->dev, "Compute params failed: %d\n",
Vinod Koulc7578c12019-08-13 09:35:46 +01001525 ret);
1526 return ret;
1527 }
1528 }
1529
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001530program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301531 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001532 ret = sdw_program_params(bus, true);
Vinod Koul48949722018-07-27 14:44:14 +05301533 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001534 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301535 goto restore_params;
1536 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301537 }
1538
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001539 if (!bus) {
1540 pr_err("Configuration error in %s\n", __func__);
1541 return -EINVAL;
1542 }
1543
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301544 ret = do_bank_switch(stream);
1545 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001546 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301547 goto restore_params;
1548 }
1549
Vinod Koul48949722018-07-27 14:44:14 +05301550 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1551 bus = m_rt->bus;
1552
1553 /* Prepare port(s) on the new clock configuration */
1554 ret = sdw_prep_deprep_ports(m_rt, true);
1555 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001556 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001557 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301558 return ret;
1559 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301560 }
1561
1562 stream->state = SDW_STREAM_PREPARED;
1563
1564 return ret;
1565
1566restore_params:
1567 memcpy(&bus->params, &params, sizeof(params));
1568 return ret;
1569}
1570
1571/**
1572 * sdw_prepare_stream() - Prepare SoundWire stream
1573 *
1574 * @stream: Soundwire stream
1575 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001576 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301577 */
1578int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1579{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001580 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001581 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301582
1583 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001584 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301585 return -EINVAL;
1586 }
1587
Vinod Koul48949722018-07-27 14:44:14 +05301588 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301589
Bard Liaoc32464c2020-01-14 17:52:24 -06001590 if (stream->state == SDW_STREAM_PREPARED) {
1591 ret = 0;
1592 goto state_err;
1593 }
1594
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001595 if (stream->state != SDW_STREAM_CONFIGURED &&
1596 stream->state != SDW_STREAM_DEPREPARED &&
1597 stream->state != SDW_STREAM_DISABLED) {
1598 pr_err("%s: %s: inconsistent state state %d\n",
1599 __func__, stream->name, stream->state);
1600 ret = -EINVAL;
1601 goto state_err;
1602 }
1603
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001604 /*
1605 * when the stream is DISABLED, this means sdw_prepare_stream()
1606 * is called as a result of an underflow or a resume operation.
1607 * In this case, the bus parameters shall not be recomputed, but
1608 * still need to be re-applied
1609 */
1610 if (stream->state == SDW_STREAM_DISABLED)
1611 update_params = false;
1612
1613 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301614
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001615state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301616 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301617 return ret;
1618}
1619EXPORT_SYMBOL(sdw_prepare_stream);
1620
1621static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1622{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001623 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301624 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301625 int ret;
1626
Vinod Koul48949722018-07-27 14:44:14 +05301627 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1628 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1629 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301630
Vinod Koul48949722018-07-27 14:44:14 +05301631 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001632 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301633 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001634 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301635 return ret;
1636 }
1637
1638 /* Enable port(s) */
1639 ret = sdw_enable_disable_ports(m_rt, true);
1640 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301641 dev_err(bus->dev,
1642 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301643 return ret;
1644 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301645 }
1646
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001647 if (!bus) {
1648 pr_err("Configuration error in %s\n", __func__);
1649 return -EINVAL;
1650 }
1651
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301652 ret = do_bank_switch(stream);
1653 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001654 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301655 return ret;
1656 }
1657
1658 stream->state = SDW_STREAM_ENABLED;
1659 return 0;
1660}
1661
1662/**
1663 * sdw_enable_stream() - Enable SoundWire stream
1664 *
1665 * @stream: Soundwire stream
1666 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001667 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301668 */
1669int sdw_enable_stream(struct sdw_stream_runtime *stream)
1670{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001671 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301672
1673 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001674 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301675 return -EINVAL;
1676 }
1677
Vinod Koul48949722018-07-27 14:44:14 +05301678 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301679
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001680 if (stream->state != SDW_STREAM_PREPARED &&
1681 stream->state != SDW_STREAM_DISABLED) {
1682 pr_err("%s: %s: inconsistent state state %d\n",
1683 __func__, stream->name, stream->state);
1684 ret = -EINVAL;
1685 goto state_err;
1686 }
1687
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301688 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301689
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001690state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301691 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301692 return ret;
1693}
1694EXPORT_SYMBOL(sdw_enable_stream);
1695
1696static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1697{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001698 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301699 int ret;
1700
Vinod Koul48949722018-07-27 14:44:14 +05301701 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001702 struct sdw_bus *bus = m_rt->bus;
1703
Vinod Koul48949722018-07-27 14:44:14 +05301704 /* Disable port(s) */
1705 ret = sdw_enable_disable_ports(m_rt, false);
1706 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001707 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301708 return ret;
1709 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301710 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301711 stream->state = SDW_STREAM_DISABLED;
1712
Vinod Koul48949722018-07-27 14:44:14 +05301713 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001714 struct sdw_bus *bus = m_rt->bus;
1715
Vinod Koul48949722018-07-27 14:44:14 +05301716 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001717 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301718 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001719 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301720 return ret;
1721 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301722 }
1723
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001724 ret = do_bank_switch(stream);
1725 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001726 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001727 return ret;
1728 }
1729
1730 /* make sure alternate bank (previous current) is also disabled */
1731 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001732 struct sdw_bus *bus = m_rt->bus;
1733
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001734 /* Disable port(s) */
1735 ret = sdw_enable_disable_ports(m_rt, false);
1736 if (ret < 0) {
1737 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1738 return ret;
1739 }
1740 }
1741
1742 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301743}
1744
1745/**
1746 * sdw_disable_stream() - Disable SoundWire stream
1747 *
1748 * @stream: Soundwire stream
1749 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001750 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301751 */
1752int sdw_disable_stream(struct sdw_stream_runtime *stream)
1753{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001754 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301755
1756 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001757 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301758 return -EINVAL;
1759 }
1760
Vinod Koul48949722018-07-27 14:44:14 +05301761 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301762
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001763 if (stream->state != SDW_STREAM_ENABLED) {
1764 pr_err("%s: %s: inconsistent state state %d\n",
1765 __func__, stream->name, stream->state);
1766 ret = -EINVAL;
1767 goto state_err;
1768 }
1769
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301770 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301771
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001772state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301773 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301774 return ret;
1775}
1776EXPORT_SYMBOL(sdw_disable_stream);
1777
1778static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1779{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001780 struct sdw_master_runtime *m_rt;
1781 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301782 int ret = 0;
1783
Vinod Koul48949722018-07-27 14:44:14 +05301784 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1785 bus = m_rt->bus;
1786 /* De-prepare port(s) */
1787 ret = sdw_prep_deprep_ports(m_rt, false);
1788 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301789 dev_err(bus->dev,
1790 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301791 return ret;
1792 }
1793
1794 /* TODO: Update this during Device-Device support */
1795 bus->params.bandwidth -= m_rt->stream->params.rate *
1796 m_rt->ch_count * m_rt->stream->params.bps;
1797
Bard Liao90261182020-09-08 21:15:20 +08001798 /* Compute params */
1799 if (bus->compute_params) {
1800 ret = bus->compute_params(bus);
1801 if (ret < 0) {
Pierre-Louis Bossart6122d3b2021-03-23 08:58:54 +08001802 dev_err(bus->dev, "Compute params failed: %d\n",
Bard Liao90261182020-09-08 21:15:20 +08001803 ret);
1804 return ret;
1805 }
1806 }
1807
Vinod Koul48949722018-07-27 14:44:14 +05301808 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001809 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301810 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001811 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301812 return ret;
1813 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301814 }
1815
1816 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301817 return do_bank_switch(stream);
1818}
1819
1820/**
1821 * sdw_deprepare_stream() - Deprepare SoundWire stream
1822 *
1823 * @stream: Soundwire stream
1824 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001825 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301826 */
1827int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1828{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001829 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301830
1831 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001832 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301833 return -EINVAL;
1834 }
1835
Vinod Koul48949722018-07-27 14:44:14 +05301836 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001837
1838 if (stream->state != SDW_STREAM_PREPARED &&
1839 stream->state != SDW_STREAM_DISABLED) {
1840 pr_err("%s: %s: inconsistent state state %d\n",
1841 __func__, stream->name, stream->state);
1842 ret = -EINVAL;
1843 goto state_err;
1844 }
1845
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301846 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301847
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001848state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301849 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301850 return ret;
1851}
1852EXPORT_SYMBOL(sdw_deprepare_stream);
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001853
1854static int set_stream(struct snd_pcm_substream *substream,
1855 struct sdw_stream_runtime *sdw_stream)
1856{
1857 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1858 struct snd_soc_dai *dai;
1859 int ret = 0;
1860 int i;
1861
1862 /* Set stream pointer on all DAIs */
1863 for_each_rtd_dais(rtd, i, dai) {
1864 ret = snd_soc_dai_set_sdw_stream(dai, sdw_stream, substream->stream);
1865 if (ret < 0) {
Pierre-Louis Bossart6122d3b2021-03-23 08:58:54 +08001866 dev_err(rtd->dev, "failed to set stream pointer on dai %s\n", dai->name);
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001867 break;
1868 }
1869 }
1870
1871 return ret;
1872}
1873
1874/**
1875 * sdw_startup_stream() - Startup SoundWire stream
1876 *
Vinod Koul3b71c692020-07-15 15:27:02 +05301877 * @sdw_substream: Soundwire stream
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001878 *
1879 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1880 */
1881int sdw_startup_stream(void *sdw_substream)
1882{
1883 struct snd_pcm_substream *substream = sdw_substream;
1884 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1885 struct sdw_stream_runtime *sdw_stream;
1886 char *name;
1887 int ret;
1888
1889 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1890 name = kasprintf(GFP_KERNEL, "%s-Playback", substream->name);
1891 else
1892 name = kasprintf(GFP_KERNEL, "%s-Capture", substream->name);
1893
1894 if (!name)
1895 return -ENOMEM;
1896
1897 sdw_stream = sdw_alloc_stream(name);
1898 if (!sdw_stream) {
Pierre-Louis Bossart6122d3b2021-03-23 08:58:54 +08001899 dev_err(rtd->dev, "alloc stream failed for substream DAI %s\n", substream->name);
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001900 ret = -ENOMEM;
1901 goto error;
1902 }
1903
1904 ret = set_stream(substream, sdw_stream);
1905 if (ret < 0)
1906 goto release_stream;
1907 return 0;
1908
1909release_stream:
1910 sdw_release_stream(sdw_stream);
1911 set_stream(substream, NULL);
1912error:
1913 kfree(name);
1914 return ret;
1915}
1916EXPORT_SYMBOL(sdw_startup_stream);
1917
1918/**
1919 * sdw_shutdown_stream() - Shutdown SoundWire stream
1920 *
Vinod Koul3b71c692020-07-15 15:27:02 +05301921 * @sdw_substream: Soundwire stream
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001922 *
1923 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1924 */
1925void sdw_shutdown_stream(void *sdw_substream)
1926{
1927 struct snd_pcm_substream *substream = sdw_substream;
1928 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1929 struct sdw_stream_runtime *sdw_stream;
1930 struct snd_soc_dai *dai;
1931
1932 /* Find stream from first CPU DAI */
1933 dai = asoc_rtd_to_cpu(rtd, 0);
1934
1935 sdw_stream = snd_soc_dai_get_sdw_stream(dai, substream->stream);
1936
Pierre-Louis Bossart3471d2a2020-09-04 04:47:36 +08001937 if (IS_ERR(sdw_stream)) {
Pierre-Louis Bossart6122d3b2021-03-23 08:58:54 +08001938 dev_err(rtd->dev, "no stream found for DAI %s\n", dai->name);
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001939 return;
1940 }
1941
1942 /* release memory */
1943 kfree(sdw_stream->name);
1944 sdw_release_stream(sdw_stream);
1945
1946 /* clear DAI data */
1947 set_stream(substream, NULL);
1948}
1949EXPORT_SYMBOL(sdw_shutdown_stream);