blob: c28ce7f0d7424f06729a6326e770ce7044900abe [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050024int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053025 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050028int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053029
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050030int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053031{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050035 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053036 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050042EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053043
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050044int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053045{
46 int i;
47
48 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050049 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053050 return i;
51 }
52
53 pr_warn("Requested row not found, selecting lowest row no: 48\n");
54 return 0;
55}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050056EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053057
Sanyog Kalef8101c72018-04-26 18:38:17 +053058static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050059 struct sdw_slave *slave,
60 struct sdw_transport_params *t_params,
61 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053062{
63 u32 addr1, addr2, addr3, addr4;
64 int ret;
65 u16 wbuf;
66
67 if (bus->params.next_bank) {
68 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
69 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
70 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
71 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
72 } else {
73 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
74 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
75 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
76 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
77 }
78
79 /* Program DPN_OffsetCtrl2 registers */
80 ret = sdw_write(slave, addr1, t_params->offset2);
81 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050082 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053083 return ret;
84 }
85
86 /* Program DPN_BlockCtrl3 register */
87 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
88 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050089 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053090 return ret;
91 }
92
93 /*
94 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053095 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053096 * handled, so bail out if we are not FULL data port type
97 */
98 if (type != SDW_DPN_FULL)
99 return ret;
100
101 /* Program DPN_SampleCtrl2 register */
102 wbuf = (t_params->sample_interval - 1);
103 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
104 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
105
106 ret = sdw_write(slave, addr3, wbuf);
107 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500108 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530109 return ret;
110 }
111
112 /* Program DPN_HCtrl register */
113 wbuf = t_params->hstart;
114 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
115 wbuf |= t_params->hstop;
116
117 ret = sdw_write(slave, addr4, wbuf);
118 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500119 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530120
121 return ret;
122}
123
124static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500125 struct sdw_slave_runtime *s_rt,
126 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530127{
128 struct sdw_transport_params *t_params = &p_rt->transport_params;
129 struct sdw_port_params *p_params = &p_rt->port_params;
130 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
131 u32 addr1, addr2, addr3, addr4, addr5, addr6;
132 struct sdw_dpn_prop *dpn_prop;
133 int ret;
134 u8 wbuf;
135
136 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500137 s_rt->direction,
138 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530139 if (!dpn_prop)
140 return -EINVAL;
141
142 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
143 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
144
145 if (bus->params.next_bank) {
146 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
147 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
148 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
149 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
150
151 } else {
152 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
153 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
154 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
155 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
156 }
157
158 /* Program DPN_PortCtrl register */
159 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
160 wbuf |= p_params->flow_mode;
161
162 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
163 if (ret < 0) {
164 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500165 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530166 t_params->port_num);
167 return ret;
168 }
169
170 /* Program DPN_BlockCtrl1 register */
171 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
172 if (ret < 0) {
173 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500174 "DPN_BlockCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530175 t_params->port_num);
176 return ret;
177 }
178
179 /* Program DPN_SampleCtrl1 register */
180 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
181 ret = sdw_write(s_rt->slave, addr3, wbuf);
182 if (ret < 0) {
183 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500184 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530185 t_params->port_num);
186 return ret;
187 }
188
189 /* Program DPN_OffsetCtrl1 registers */
190 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
191 if (ret < 0) {
192 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500193 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530194 t_params->port_num);
195 return ret;
196 }
197
198 /* Program DPN_BlockCtrl2 register*/
199 if (t_params->blk_grp_ctrl_valid) {
200 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
201 if (ret < 0) {
202 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500203 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530204 t_params->port_num);
205 return ret;
206 }
207 }
208
209 /* program DPN_LaneCtrl register */
210 if (slave_prop->lane_control_support) {
211 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
212 if (ret < 0) {
213 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500214 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530215 t_params->port_num);
216 return ret;
217 }
218 }
219
220 if (dpn_prop->type != SDW_DPN_SIMPLE) {
221 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500222 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530223 if (ret < 0)
224 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500225 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530226 t_params->port_num);
227 }
228
229 return ret;
230}
231
232static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500233 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530234{
235 int ret;
236
237 /*
238 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530239 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530240 * hstart/stop etc of the data. Port parameters refers to word
241 * length, flow mode etc of the port
242 */
243 ret = bus->port_ops->dpn_set_port_transport_params(bus,
244 &p_rt->transport_params,
245 bus->params.next_bank);
246 if (ret < 0)
247 return ret;
248
249 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500250 &p_rt->port_params,
251 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530252}
253
254/**
255 * sdw_program_port_params() - Programs transport parameters of Master(s)
256 * and Slave(s)
257 *
258 * @m_rt: Master stream runtime
259 */
260static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
261{
262 struct sdw_slave_runtime *s_rt = NULL;
263 struct sdw_bus *bus = m_rt->bus;
264 struct sdw_port_runtime *p_rt;
265 int ret = 0;
266
267 /* Program transport & port parameters for Slave(s) */
268 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
269 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
270 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
271 if (ret < 0)
272 return ret;
273 }
274 }
275
276 /* Program transport & port parameters for Master(s) */
277 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
278 ret = sdw_program_master_port_params(bus, p_rt);
279 if (ret < 0)
280 return ret;
281 }
282
283 return 0;
284}
285
Sanyog Kale89e59052018-04-26 18:38:08 +0530286/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530287 * sdw_enable_disable_slave_ports: Enable/disable slave data port
288 *
289 * @bus: bus instance
290 * @s_rt: slave runtime
291 * @p_rt: port runtime
292 * @en: enable or disable operation
293 *
294 * This function only sets the enable/disable bits in the relevant bank, the
295 * actual enable/disable is done with a bank switch
296 */
297static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500298 struct sdw_slave_runtime *s_rt,
299 struct sdw_port_runtime *p_rt,
300 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530301{
302 struct sdw_transport_params *t_params = &p_rt->transport_params;
303 u32 addr;
304 int ret;
305
306 if (bus->params.next_bank)
307 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
308 else
309 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
310
311 /*
312 * Since bus doesn't support sharing a port across two streams,
313 * it is safe to reset this register
314 */
315 if (en)
316 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
317 else
318 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
319
320 if (ret < 0)
321 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500322 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530323 ret, t_params->port_num);
324
325 return ret;
326}
327
328static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500329 struct sdw_port_runtime *p_rt,
330 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530331{
332 struct sdw_transport_params *t_params = &p_rt->transport_params;
333 struct sdw_bus *bus = m_rt->bus;
334 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500335 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530336
337 enable_ch.port_num = p_rt->num;
338 enable_ch.ch_mask = p_rt->ch_mask;
339 enable_ch.enable = en;
340
341 /* Perform Master port channel(s) enable/disable */
342 if (bus->port_ops->dpn_port_enable_ch) {
343 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500344 &enable_ch,
345 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530346 if (ret < 0) {
347 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500348 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530349 ret, t_params->port_num);
350 return ret;
351 }
352 } else {
353 dev_err(bus->dev,
354 "dpn_port_enable_ch not supported, %s failed\n",
355 en ? "enable" : "disable");
356 return -EINVAL;
357 }
358
359 return 0;
360}
361
362/**
363 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
364 * Slave(s)
365 *
366 * @m_rt: Master stream runtime
367 * @en: mode (enable/disable)
368 */
369static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
370{
371 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500372 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530373 int ret = 0;
374
375 /* Enable/Disable Slave port(s) */
376 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
377 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
378 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500379 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530380 if (ret < 0)
381 return ret;
382 }
383 }
384
385 /* Enable/Disable Master port(s) */
386 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
387 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
388 if (ret < 0)
389 return ret;
390 }
391
392 return 0;
393}
394
395static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500396 struct sdw_prepare_ch prep_ch,
397 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530398{
399 const struct sdw_slave_ops *ops = s_rt->slave->ops;
400 int ret;
401
402 if (ops->port_prep) {
403 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
404 if (ret < 0) {
405 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530406 "Slave Port Prep cmd %d failed: %d\n",
407 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530408 return ret;
409 }
410 }
411
412 return 0;
413}
414
415static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500416 struct sdw_slave_runtime *s_rt,
417 struct sdw_port_runtime *p_rt,
418 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530419{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500420 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530421 struct sdw_dpn_prop *dpn_prop;
422 struct sdw_prepare_ch prep_ch;
423 unsigned int time_left;
424 bool intr = false;
425 int ret = 0, val;
426 u32 addr;
427
428 prep_ch.num = p_rt->num;
429 prep_ch.ch_mask = p_rt->ch_mask;
430
431 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500432 s_rt->direction,
433 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530434 if (!dpn_prop) {
435 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500436 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530437 return -EINVAL;
438 }
439
440 prep_ch.prepare = prep;
441
442 prep_ch.bank = bus->params.next_bank;
443
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500444 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530445 intr = true;
446
447 /*
448 * Enable interrupt before Port prepare.
449 * For Port de-prepare, it is assumed that port
450 * was prepared earlier
451 */
452 if (prep && intr) {
453 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500454 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530455 if (ret < 0)
456 return ret;
457 }
458
459 /* Inform slave about the impending port prepare */
460 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
461
462 /* Prepare Slave port implementing CP_SM */
463 if (!dpn_prop->simple_ch_prep_sm) {
464 addr = SDW_DPN_PREPARECTRL(p_rt->num);
465
466 if (prep)
467 ret = sdw_update(s_rt->slave, addr,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500468 0xFF, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530469 else
470 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
471
472 if (ret < 0) {
473 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500474 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530475 return ret;
476 }
477
478 /* Wait for completion on port ready */
479 port_ready = &s_rt->slave->port_ready[prep_ch.num];
480 time_left = wait_for_completion_timeout(port_ready,
481 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
482
483 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
484 val &= p_rt->ch_mask;
485 if (!time_left || val) {
486 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500487 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530488 return -ETIMEDOUT;
489 }
490 }
491
492 /* Inform slaves about ports prepared */
493 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
494
495 /* Disable interrupt after Port de-prepare */
496 if (!prep && intr)
497 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500498 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530499
500 return ret;
501}
502
503static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500504 struct sdw_port_runtime *p_rt,
505 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530506{
507 struct sdw_transport_params *t_params = &p_rt->transport_params;
508 struct sdw_bus *bus = m_rt->bus;
509 const struct sdw_master_port_ops *ops = bus->port_ops;
510 struct sdw_prepare_ch prep_ch;
511 int ret = 0;
512
513 prep_ch.num = p_rt->num;
514 prep_ch.ch_mask = p_rt->ch_mask;
515 prep_ch.prepare = prep; /* Prepare/De-prepare */
516 prep_ch.bank = bus->params.next_bank;
517
518 /* Pre-prepare/Pre-deprepare port(s) */
519 if (ops->dpn_port_prep) {
520 ret = ops->dpn_port_prep(bus, &prep_ch);
521 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500522 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500523 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530524 return ret;
525 }
526 }
527
528 return ret;
529}
530
531/**
532 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
533 * Slave(s)
534 *
535 * @m_rt: Master runtime handle
536 * @prep: Prepare or De-prepare
537 */
538static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
539{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500540 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530541 struct sdw_port_runtime *p_rt;
542 int ret = 0;
543
544 /* Prepare/De-prepare Slave port(s) */
545 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
546 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
547 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500548 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530549 if (ret < 0)
550 return ret;
551 }
552 }
553
554 /* Prepare/De-prepare Master port(s) */
555 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
556 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
557 if (ret < 0)
558 return ret;
559 }
560
561 return ret;
562}
563
564/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530565 * sdw_notify_config() - Notify bus configuration
566 *
567 * @m_rt: Master runtime handle
568 *
569 * This function notifies the Master(s) and Slave(s) of the
570 * new bus configuration.
571 */
572static int sdw_notify_config(struct sdw_master_runtime *m_rt)
573{
574 struct sdw_slave_runtime *s_rt;
575 struct sdw_bus *bus = m_rt->bus;
576 struct sdw_slave *slave;
577 int ret = 0;
578
579 if (bus->ops->set_bus_conf) {
580 ret = bus->ops->set_bus_conf(bus, &bus->params);
581 if (ret < 0)
582 return ret;
583 }
584
585 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
586 slave = s_rt->slave;
587
588 if (slave->ops->bus_config) {
589 ret = slave->ops->bus_config(slave, &bus->params);
590 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500591 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500592 slave->dev_num);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530593 return ret;
594 }
595 }
596
597 return ret;
598}
599
600/**
601 * sdw_program_params() - Program transport and port parameters for Master(s)
602 * and Slave(s)
603 *
604 * @bus: SDW bus instance
605 */
606static int sdw_program_params(struct sdw_bus *bus)
607{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500608 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530609 int ret = 0;
610
611 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
612 ret = sdw_program_port_params(m_rt);
613 if (ret < 0) {
614 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500615 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530616 return ret;
617 }
618
619 ret = sdw_notify_config(m_rt);
620 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530621 dev_err(bus->dev,
622 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530623 return ret;
624 }
625
626 /* Enable port(s) on alternate bank for all active streams */
627 if (m_rt->stream->state != SDW_STREAM_ENABLED)
628 continue;
629
630 ret = sdw_enable_disable_ports(m_rt, true);
631 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500632 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530633 return ret;
634 }
635 }
636
637 return ret;
638}
639
Shreyas NCce6e74d2018-07-27 14:44:16 +0530640static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530641{
642 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530643 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530644 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500645 u8 *wbuf;
646 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530647 u16 addr;
648
649 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
650 if (!wr_msg)
651 return -ENOMEM;
652
Shreyas NCce6e74d2018-07-27 14:44:16 +0530653 bus->defer_msg.msg = wr_msg;
654
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530655 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
656 if (!wbuf) {
657 ret = -ENOMEM;
658 goto error_1;
659 }
660
661 /* Get row and column index to program register */
662 col_index = sdw_find_col_index(bus->params.col);
663 row_index = sdw_find_row_index(bus->params.row);
664 wbuf[0] = col_index | (row_index << 3);
665
666 if (bus->params.next_bank)
667 addr = SDW_SCP_FRAMECTRL_B1;
668 else
669 addr = SDW_SCP_FRAMECTRL_B0;
670
671 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500672 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530673 wr_msg->ssp_sync = true;
674
Shreyas NCce6e74d2018-07-27 14:44:16 +0530675 /*
676 * Set the multi_link flag only when both the hardware supports
677 * and there is a stream handled by multiple masters
678 */
679 multi_link = bus->multi_link && (m_rt_count > 1);
680
681 if (multi_link)
682 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
683 else
684 ret = sdw_transfer(bus, wr_msg);
685
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530686 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500687 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530688 goto error;
689 }
690
Shreyas NCce6e74d2018-07-27 14:44:16 +0530691 if (!multi_link) {
692 kfree(wr_msg);
693 kfree(wbuf);
694 bus->defer_msg.msg = NULL;
695 bus->params.curr_bank = !bus->params.curr_bank;
696 bus->params.next_bank = !bus->params.next_bank;
697 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530698
699 return 0;
700
701error:
702 kfree(wbuf);
703error_1:
704 kfree(wr_msg);
705 return ret;
706}
707
Shreyas NCce6e74d2018-07-27 14:44:16 +0530708/**
709 * sdw_ml_sync_bank_switch: Multilink register bank switch
710 *
711 * @bus: SDW bus instance
712 *
713 * Caller function should free the buffers on error
714 */
715static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
716{
717 unsigned long time_left;
718
719 if (!bus->multi_link)
720 return 0;
721
722 /* Wait for completion of transfer */
723 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
724 bus->bank_switch_timeout);
725
726 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500727 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530728 return -ETIMEDOUT;
729 }
730
731 bus->params.curr_bank = !bus->params.curr_bank;
732 bus->params.next_bank = !bus->params.next_bank;
733
734 if (bus->defer_msg.msg) {
735 kfree(bus->defer_msg.msg->buf);
736 kfree(bus->defer_msg.msg);
737 }
738
739 return 0;
740}
741
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530742static int do_bank_switch(struct sdw_stream_runtime *stream)
743{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500744 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530745 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500746 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530747 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530748 int ret = 0;
749
Vinod Koul48949722018-07-27 14:44:14 +0530750 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
751 bus = m_rt->bus;
752 ops = bus->ops;
753
Shreyas NCce6e74d2018-07-27 14:44:16 +0530754 if (bus->multi_link) {
755 multi_link = true;
756 mutex_lock(&bus->msg_lock);
757 }
758
Vinod Koul48949722018-07-27 14:44:14 +0530759 /* Pre-bank switch */
760 if (ops->pre_bank_switch) {
761 ret = ops->pre_bank_switch(bus);
762 if (ret < 0) {
763 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500764 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530765 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530766 }
767 }
768
Shreyas NCce6e74d2018-07-27 14:44:16 +0530769 /*
770 * Perform Bank switch operation.
771 * For multi link cases, the actual bank switch is
772 * synchronized across all Masters and happens later as a
773 * part of post_bank_switch ops.
774 */
775 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530776 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500777 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530778 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530779 }
780 }
781
Shreyas NCce6e74d2018-07-27 14:44:16 +0530782 /*
783 * For multi link cases, it is expected that the bank switch is
784 * triggered by the post_bank_switch for the first Master in the list
785 * and for the other Masters the post_bank_switch() should return doing
786 * nothing.
787 */
Vinod Koul48949722018-07-27 14:44:14 +0530788 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
789 bus = m_rt->bus;
790 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530791
Vinod Koul48949722018-07-27 14:44:14 +0530792 /* Post-bank switch */
793 if (ops->post_bank_switch) {
794 ret = ops->post_bank_switch(bus);
795 if (ret < 0) {
796 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530797 "Post bank switch op failed: %d\n",
798 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530799 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530800 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530801 } else if (bus->multi_link && stream->m_rt_count > 1) {
802 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500803 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530804 goto error;
805 }
806
807 /* Set the bank switch timeout to default, if not set */
808 if (!bus->bank_switch_timeout)
809 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
810
811 /* Check if bank switch was successful */
812 ret = sdw_ml_sync_bank_switch(bus);
813 if (ret < 0) {
814 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500815 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530816 goto error;
817 }
818
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100819 if (bus->multi_link)
820 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530821 }
822
823 return ret;
824
825error:
826 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530827 bus = m_rt->bus;
828
829 kfree(bus->defer_msg.msg->buf);
830 kfree(bus->defer_msg.msg);
831 }
832
833msg_unlock:
834
835 if (multi_link) {
836 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
837 bus = m_rt->bus;
838 if (mutex_is_locked(&bus->msg_lock))
839 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530840 }
841 }
842
843 return ret;
844}
845
846/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530847 * sdw_release_stream() - Free the assigned stream runtime
848 *
849 * @stream: SoundWire stream runtime
850 *
851 * sdw_release_stream should be called only once per stream
852 */
853void sdw_release_stream(struct sdw_stream_runtime *stream)
854{
855 kfree(stream);
856}
857EXPORT_SYMBOL(sdw_release_stream);
858
859/**
860 * sdw_alloc_stream() - Allocate and return stream runtime
861 *
862 * @stream_name: SoundWire stream name
863 *
864 * Allocates a SoundWire stream runtime instance.
865 * sdw_alloc_stream should be called only once per stream. Typically
866 * invoked from ALSA/ASoC machine/platform driver.
867 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100868struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530869{
870 struct sdw_stream_runtime *stream;
871
872 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
873 if (!stream)
874 return NULL;
875
876 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530877 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530878 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530879 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530880
881 return stream;
882}
883EXPORT_SYMBOL(sdw_alloc_stream);
884
Vinod Koul48949722018-07-27 14:44:14 +0530885static struct sdw_master_runtime
886*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500887 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530888{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500889 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530890
891 /* Retrieve Bus handle if already available */
892 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
893 if (m_rt->bus == bus)
894 return m_rt;
895 }
896
897 return NULL;
898}
899
Sanyog Kale89e59052018-04-26 18:38:08 +0530900/**
901 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
902 *
903 * @bus: SDW bus instance
904 * @stream_config: Stream configuration
905 * @stream: Stream runtime handle.
906 *
907 * This function is to be called with bus_lock held.
908 */
909static struct sdw_master_runtime
910*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500911 struct sdw_stream_config *stream_config,
912 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530913{
914 struct sdw_master_runtime *m_rt;
915
Sanyog Kale89e59052018-04-26 18:38:08 +0530916 /*
917 * check if Master is already allocated (as a result of Slave adding
918 * it first), if so skip allocation and go to configure
919 */
Vinod Koul48949722018-07-27 14:44:14 +0530920 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530921 if (m_rt)
922 goto stream_config;
923
924 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
925 if (!m_rt)
926 return NULL;
927
928 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530929 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530930 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530931 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530932
933 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
934
935stream_config:
936 m_rt->ch_count = stream_config->ch_count;
937 m_rt->bus = bus;
938 m_rt->stream = stream;
939 m_rt->direction = stream_config->direction;
940
941 return m_rt;
942}
943
944/**
945 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
946 *
947 * @slave: Slave handle
948 * @stream_config: Stream configuration
949 * @stream: Stream runtime handle
950 *
951 * This function is to be called with bus_lock held.
952 */
953static struct sdw_slave_runtime
954*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500955 struct sdw_stream_config *stream_config,
956 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530957{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500958 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530959
960 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
961 if (!s_rt)
962 return NULL;
963
Sanyog Kalebbe73792018-04-26 18:38:13 +0530964 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530965 s_rt->ch_count = stream_config->ch_count;
966 s_rt->direction = stream_config->direction;
967 s_rt->slave = slave;
968
969 return s_rt;
970}
971
Sanyog Kalebbe73792018-04-26 18:38:13 +0530972static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500973 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530974{
975 struct sdw_port_runtime *p_rt, *_p_rt;
976
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500977 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530978 list_del(&p_rt->port_node);
979 kfree(p_rt);
980 }
981}
982
983static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500984 struct sdw_slave *slave,
985 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530986{
987 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530988 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +0530989 struct sdw_slave_runtime *s_rt;
990
Vinod Koul48949722018-07-27 14:44:14 +0530991 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
992 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530993 if (s_rt->slave != slave)
994 continue;
995
996 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500997 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530998 list_del(&p_rt->port_node);
999 kfree(p_rt);
1000 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301001 }
1002 }
1003}
1004
Sanyog Kale89e59052018-04-26 18:38:08 +05301005/**
1006 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1007 *
1008 * @slave: Slave handle.
1009 * @stream: Stream runtime handle.
1010 *
1011 * This function is to be called with bus_lock held.
1012 */
1013static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001014 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301015{
1016 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301017 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301018
Vinod Koul48949722018-07-27 14:44:14 +05301019 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1020 /* Retrieve Slave runtime handle */
1021 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001022 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301023 if (s_rt->slave == slave) {
1024 list_del(&s_rt->m_rt_node);
1025 kfree(s_rt);
1026 return;
1027 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301028 }
1029 }
1030}
1031
1032/**
1033 * sdw_release_master_stream() - Free Master runtime handle
1034 *
Vinod Koul48949722018-07-27 14:44:14 +05301035 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301036 * @stream: Stream runtime handle.
1037 *
1038 * This function is to be called with bus_lock held
1039 * It frees the Master runtime handle and associated Slave(s) runtime
1040 * handle. If this is called first then sdw_release_slave_stream() will have
1041 * no effect as Slave(s) runtime handle would already be freed up.
1042 */
Vinod Koul48949722018-07-27 14:44:14 +05301043static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001044 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301045{
Sanyog Kale89e59052018-04-26 18:38:08 +05301046 struct sdw_slave_runtime *s_rt, *_s_rt;
1047
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301048 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1049 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1050 sdw_release_slave_stream(s_rt->slave, stream);
1051 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301052
Vinod Koul48949722018-07-27 14:44:14 +05301053 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301054 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301055 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301056}
1057
1058/**
1059 * sdw_stream_remove_master() - Remove master from sdw_stream
1060 *
1061 * @bus: SDW Bus instance
1062 * @stream: SoundWire stream
1063 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301064 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301065 */
1066int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001067 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301068{
Vinod Koul48949722018-07-27 14:44:14 +05301069 struct sdw_master_runtime *m_rt, *_m_rt;
1070
Sanyog Kale89e59052018-04-26 18:38:08 +05301071 mutex_lock(&bus->bus_lock);
1072
Vinod Koul48949722018-07-27 14:44:14 +05301073 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001074 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301075 if (m_rt->bus != bus)
1076 continue;
1077
1078 sdw_master_port_release(bus, m_rt);
1079 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301080 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301081 }
1082
1083 if (list_empty(&stream->master_list))
1084 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301085
1086 mutex_unlock(&bus->bus_lock);
1087
1088 return 0;
1089}
1090EXPORT_SYMBOL(sdw_stream_remove_master);
1091
1092/**
1093 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1094 *
1095 * @slave: SDW Slave instance
1096 * @stream: SoundWire stream
1097 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301098 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301099 */
1100int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001101 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301102{
1103 mutex_lock(&slave->bus->bus_lock);
1104
Sanyog Kalebbe73792018-04-26 18:38:13 +05301105 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301106 sdw_release_slave_stream(slave, stream);
1107
1108 mutex_unlock(&slave->bus->bus_lock);
1109
1110 return 0;
1111}
1112EXPORT_SYMBOL(sdw_stream_remove_slave);
1113
1114/**
1115 * sdw_config_stream() - Configure the allocated stream
1116 *
1117 * @dev: SDW device
1118 * @stream: SoundWire stream
1119 * @stream_config: Stream configuration for audio stream
1120 * @is_slave: is API called from Slave or Master
1121 *
1122 * This function is to be called with bus_lock held.
1123 */
1124static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001125 struct sdw_stream_runtime *stream,
1126 struct sdw_stream_config *stream_config,
1127 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301128{
1129 /*
1130 * Update the stream rate, channel and bps based on data
1131 * source. For more than one data source (multilink),
1132 * match the rate, bps, stream type and increment number of channels.
1133 *
1134 * If rate/bps is zero, it means the values are not set, so skip
1135 * comparison and allow the value to be set and stored in stream
1136 */
1137 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001138 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001139 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301140 return -EINVAL;
1141 }
1142
1143 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001144 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001145 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301146 return -EINVAL;
1147 }
1148
1149 stream->type = stream_config->type;
1150 stream->params.rate = stream_config->frame_rate;
1151 stream->params.bps = stream_config->bps;
1152
1153 /* TODO: Update this check during Device-device support */
1154 if (is_slave)
1155 stream->params.ch_count += stream_config->ch_count;
1156
1157 return 0;
1158}
1159
Sanyog Kalebbe73792018-04-26 18:38:13 +05301160static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001161 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301162{
1163 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1164 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001165 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301166 return -EINVAL;
1167 }
1168
1169 return 0;
1170}
1171
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001172static struct sdw_port_runtime
1173*sdw_port_alloc(struct device *dev,
1174 struct sdw_port_config *port_config,
1175 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301176{
1177 struct sdw_port_runtime *p_rt;
1178
1179 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1180 if (!p_rt)
1181 return NULL;
1182
1183 p_rt->ch_mask = port_config[port_index].ch_mask;
1184 p_rt->num = port_config[port_index].num;
1185
1186 return p_rt;
1187}
1188
1189static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001190 struct sdw_master_runtime *m_rt,
1191 struct sdw_port_config *port_config,
1192 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301193{
1194 struct sdw_port_runtime *p_rt;
1195 int i;
1196
1197 /* Iterate for number of ports to perform initialization */
1198 for (i = 0; i < num_ports; i++) {
1199 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1200 if (!p_rt)
1201 return -ENOMEM;
1202
1203 /*
1204 * TODO: Check port capabilities for requested
1205 * configuration (audio mode support)
1206 */
1207
1208 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1209 }
1210
1211 return 0;
1212}
1213
1214static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001215 struct sdw_slave_runtime *s_rt,
1216 struct sdw_port_config *port_config,
1217 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301218{
1219 struct sdw_port_runtime *p_rt;
1220 int i, ret;
1221
1222 /* Iterate for number of ports to perform initialization */
1223 for (i = 0; i < num_config; i++) {
1224 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1225 if (!p_rt)
1226 return -ENOMEM;
1227
1228 /*
1229 * TODO: Check valid port range as defined by DisCo/
1230 * slave
1231 */
1232 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1233 if (ret < 0) {
1234 kfree(p_rt);
1235 return ret;
1236 }
1237
1238 /*
1239 * TODO: Check port capabilities for requested
1240 * configuration (audio mode support)
1241 */
1242
1243 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1244 }
1245
1246 return 0;
1247}
1248
Sanyog Kale89e59052018-04-26 18:38:08 +05301249/**
1250 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1251 *
1252 * @bus: SDW Bus instance
1253 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301254 * @port_config: Port configuration for audio stream
1255 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301256 * @stream: SoundWire stream
1257 */
1258int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001259 struct sdw_stream_config *stream_config,
1260 struct sdw_port_config *port_config,
1261 unsigned int num_ports,
1262 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301263{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001264 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301265 int ret;
1266
1267 mutex_lock(&bus->bus_lock);
1268
Shreyas NCce6e74d2018-07-27 14:44:16 +05301269 /*
1270 * For multi link streams, add the second master only if
1271 * the bus supports it.
1272 * Check if bus->multi_link is set
1273 */
1274 if (!bus->multi_link && stream->m_rt_count > 0) {
1275 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001276 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301277 ret = -EINVAL;
1278 goto unlock;
1279 }
1280
Sanyog Kale89e59052018-04-26 18:38:08 +05301281 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1282 if (!m_rt) {
1283 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001284 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001285 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301286 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301287 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301288 }
1289
1290 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1291 if (ret)
1292 goto stream_error;
1293
Sanyog Kalebbe73792018-04-26 18:38:13 +05301294 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1295 if (ret)
1296 goto stream_error;
1297
Shreyas NCce6e74d2018-07-27 14:44:16 +05301298 stream->m_rt_count++;
1299
Shreyas NC3fef1a22018-07-27 14:44:09 +05301300 goto unlock;
1301
Sanyog Kale89e59052018-04-26 18:38:08 +05301302stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301303 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301304unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301305 mutex_unlock(&bus->bus_lock);
1306 return ret;
1307}
1308EXPORT_SYMBOL(sdw_stream_add_master);
1309
1310/**
1311 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1312 *
1313 * @slave: SDW Slave instance
1314 * @stream_config: Stream configuration for audio stream
1315 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301316 * @port_config: Port configuration for audio stream
1317 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301318 *
1319 * It is expected that Slave is added before adding Master
1320 * to the Stream.
1321 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301322 */
1323int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001324 struct sdw_stream_config *stream_config,
1325 struct sdw_port_config *port_config,
1326 unsigned int num_ports,
1327 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301328{
1329 struct sdw_slave_runtime *s_rt;
1330 struct sdw_master_runtime *m_rt;
1331 int ret;
1332
1333 mutex_lock(&slave->bus->bus_lock);
1334
1335 /*
1336 * If this API is invoked by Slave first then m_rt is not valid.
1337 * So, allocate m_rt and add Slave to it.
1338 */
1339 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1340 if (!m_rt) {
1341 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001342 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001343 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301344 ret = -ENOMEM;
1345 goto error;
1346 }
1347
1348 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1349 if (!s_rt) {
1350 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001351 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001352 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301353 ret = -ENOMEM;
1354 goto stream_error;
1355 }
1356
1357 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1358 if (ret)
1359 goto stream_error;
1360
1361 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1362
Sanyog Kalebbe73792018-04-26 18:38:13 +05301363 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1364 if (ret)
1365 goto stream_error;
1366
Shreyas NC0aebe402018-07-27 14:44:08 +05301367 /*
1368 * Change stream state to CONFIGURED on first Slave add.
1369 * Bus is not aware of number of Slave(s) in a stream at this
1370 * point so cannot depend on all Slave(s) to be added in order to
1371 * change stream state to CONFIGURED.
1372 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301373 stream->state = SDW_STREAM_CONFIGURED;
1374 goto error;
1375
1376stream_error:
1377 /*
1378 * we hit error so cleanup the stream, release all Slave(s) and
1379 * Master runtime
1380 */
Vinod Koul48949722018-07-27 14:44:14 +05301381 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301382error:
1383 mutex_unlock(&slave->bus->bus_lock);
1384 return ret;
1385}
1386EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301387
1388/**
1389 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1390 *
1391 * @slave: Slave handle
1392 * @direction: Data direction.
1393 * @port_num: Port number
1394 */
1395struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001396 enum sdw_data_direction direction,
1397 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301398{
1399 struct sdw_dpn_prop *dpn_prop;
1400 u8 num_ports;
1401 int i;
1402
1403 if (direction == SDW_DATA_DIR_TX) {
1404 num_ports = hweight32(slave->prop.source_ports);
1405 dpn_prop = slave->prop.src_dpn_prop;
1406 } else {
1407 num_ports = hweight32(slave->prop.sink_ports);
1408 dpn_prop = slave->prop.sink_dpn_prop;
1409 }
1410
1411 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001412 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301413 return &dpn_prop[i];
1414 }
1415
1416 return NULL;
1417}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301418
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301419/**
1420 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1421 *
1422 * @stream: SoundWire stream
1423 *
1424 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1425 * stream to reconfigure the bus.
1426 * NOTE: This function is called from SoundWire stream ops and is
1427 * expected that a global lock is held before acquiring bus_lock.
1428 */
1429static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1430{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001431 struct sdw_master_runtime *m_rt;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301432 struct sdw_bus *bus = NULL;
1433
1434 /* Iterate for all Master(s) in Master list */
1435 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1436 bus = m_rt->bus;
1437
1438 mutex_lock(&bus->bus_lock);
1439 }
1440}
1441
1442/**
1443 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1444 *
1445 * @stream: SoundWire stream
1446 *
1447 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301448 * NOTE: This function is called from SoundWire stream ops and is
1449 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301450 */
1451static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1452{
1453 struct sdw_master_runtime *m_rt = NULL;
1454 struct sdw_bus *bus = NULL;
1455
1456 /* Iterate for all Master(s) in Master list */
1457 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1458 bus = m_rt->bus;
1459 mutex_unlock(&bus->bus_lock);
1460 }
1461}
1462
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001463static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1464 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301465{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001466 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301467 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001468 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301469 struct sdw_bus_params params;
1470 int ret;
1471
Vinod Koul48949722018-07-27 14:44:14 +05301472 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1473 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1474 bus = m_rt->bus;
1475 prop = &bus->prop;
1476 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301477
Vinod Koul48949722018-07-27 14:44:14 +05301478 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001479 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001480 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301481 return -EINVAL;
1482 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301483
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001484 if (!update_params)
1485 goto program_params;
1486
Vinod Koul48949722018-07-27 14:44:14 +05301487 /* Increment cumulative bus bandwidth */
1488 /* TODO: Update this during Device-Device support */
1489 bus->params.bandwidth += m_rt->stream->params.rate *
1490 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301491
Vinod Koulc7578c12019-08-13 09:35:46 +01001492 /* Compute params */
1493 if (bus->compute_params) {
1494 ret = bus->compute_params(bus);
1495 if (ret < 0) {
1496 dev_err(bus->dev, "Compute params failed: %d",
1497 ret);
1498 return ret;
1499 }
1500 }
1501
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001502program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301503 /* Program params */
1504 ret = sdw_program_params(bus);
1505 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001506 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301507 goto restore_params;
1508 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301509 }
1510
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001511 if (!bus) {
1512 pr_err("Configuration error in %s\n", __func__);
1513 return -EINVAL;
1514 }
1515
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301516 ret = do_bank_switch(stream);
1517 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001518 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301519 goto restore_params;
1520 }
1521
Vinod Koul48949722018-07-27 14:44:14 +05301522 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1523 bus = m_rt->bus;
1524
1525 /* Prepare port(s) on the new clock configuration */
1526 ret = sdw_prep_deprep_ports(m_rt, true);
1527 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001528 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001529 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301530 return ret;
1531 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301532 }
1533
1534 stream->state = SDW_STREAM_PREPARED;
1535
1536 return ret;
1537
1538restore_params:
1539 memcpy(&bus->params, &params, sizeof(params));
1540 return ret;
1541}
1542
1543/**
1544 * sdw_prepare_stream() - Prepare SoundWire stream
1545 *
1546 * @stream: Soundwire stream
1547 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001548 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301549 */
1550int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1551{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001552 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001553 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301554
1555 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001556 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301557 return -EINVAL;
1558 }
1559
Vinod Koul48949722018-07-27 14:44:14 +05301560 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301561
Bard Liaoc32464c2020-01-14 17:52:24 -06001562 if (stream->state == SDW_STREAM_PREPARED) {
1563 ret = 0;
1564 goto state_err;
1565 }
1566
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001567 if (stream->state != SDW_STREAM_CONFIGURED &&
1568 stream->state != SDW_STREAM_DEPREPARED &&
1569 stream->state != SDW_STREAM_DISABLED) {
1570 pr_err("%s: %s: inconsistent state state %d\n",
1571 __func__, stream->name, stream->state);
1572 ret = -EINVAL;
1573 goto state_err;
1574 }
1575
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001576 /*
1577 * when the stream is DISABLED, this means sdw_prepare_stream()
1578 * is called as a result of an underflow or a resume operation.
1579 * In this case, the bus parameters shall not be recomputed, but
1580 * still need to be re-applied
1581 */
1582 if (stream->state == SDW_STREAM_DISABLED)
1583 update_params = false;
1584
1585 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301586
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001587state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301588 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301589 return ret;
1590}
1591EXPORT_SYMBOL(sdw_prepare_stream);
1592
1593static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1594{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001595 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301596 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301597 int ret;
1598
Vinod Koul48949722018-07-27 14:44:14 +05301599 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1600 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1601 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301602
Vinod Koul48949722018-07-27 14:44:14 +05301603 /* Program params */
1604 ret = sdw_program_params(bus);
1605 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001606 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301607 return ret;
1608 }
1609
1610 /* Enable port(s) */
1611 ret = sdw_enable_disable_ports(m_rt, true);
1612 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301613 dev_err(bus->dev,
1614 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301615 return ret;
1616 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301617 }
1618
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001619 if (!bus) {
1620 pr_err("Configuration error in %s\n", __func__);
1621 return -EINVAL;
1622 }
1623
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301624 ret = do_bank_switch(stream);
1625 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001626 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301627 return ret;
1628 }
1629
1630 stream->state = SDW_STREAM_ENABLED;
1631 return 0;
1632}
1633
1634/**
1635 * sdw_enable_stream() - Enable SoundWire stream
1636 *
1637 * @stream: Soundwire stream
1638 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001639 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301640 */
1641int sdw_enable_stream(struct sdw_stream_runtime *stream)
1642{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001643 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301644
1645 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001646 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301647 return -EINVAL;
1648 }
1649
Vinod Koul48949722018-07-27 14:44:14 +05301650 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301651
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001652 if (stream->state != SDW_STREAM_PREPARED &&
1653 stream->state != SDW_STREAM_DISABLED) {
1654 pr_err("%s: %s: inconsistent state state %d\n",
1655 __func__, stream->name, stream->state);
1656 ret = -EINVAL;
1657 goto state_err;
1658 }
1659
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301660 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301661
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001662state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301663 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301664 return ret;
1665}
1666EXPORT_SYMBOL(sdw_enable_stream);
1667
1668static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1669{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001670 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301671 int ret;
1672
Vinod Koul48949722018-07-27 14:44:14 +05301673 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001674 struct sdw_bus *bus = m_rt->bus;
1675
Vinod Koul48949722018-07-27 14:44:14 +05301676 /* Disable port(s) */
1677 ret = sdw_enable_disable_ports(m_rt, false);
1678 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001679 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301680 return ret;
1681 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301682 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301683 stream->state = SDW_STREAM_DISABLED;
1684
Vinod Koul48949722018-07-27 14:44:14 +05301685 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001686 struct sdw_bus *bus = m_rt->bus;
1687
Vinod Koul48949722018-07-27 14:44:14 +05301688 /* Program params */
1689 ret = sdw_program_params(bus);
1690 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001691 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301692 return ret;
1693 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301694 }
1695
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001696 ret = do_bank_switch(stream);
1697 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001698 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001699 return ret;
1700 }
1701
1702 /* make sure alternate bank (previous current) is also disabled */
1703 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001704 struct sdw_bus *bus = m_rt->bus;
1705
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001706 /* Disable port(s) */
1707 ret = sdw_enable_disable_ports(m_rt, false);
1708 if (ret < 0) {
1709 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1710 return ret;
1711 }
1712 }
1713
1714 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301715}
1716
1717/**
1718 * sdw_disable_stream() - Disable SoundWire stream
1719 *
1720 * @stream: Soundwire stream
1721 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001722 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301723 */
1724int sdw_disable_stream(struct sdw_stream_runtime *stream)
1725{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001726 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301727
1728 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001729 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301730 return -EINVAL;
1731 }
1732
Vinod Koul48949722018-07-27 14:44:14 +05301733 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301734
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001735 if (stream->state != SDW_STREAM_ENABLED) {
1736 pr_err("%s: %s: inconsistent state state %d\n",
1737 __func__, stream->name, stream->state);
1738 ret = -EINVAL;
1739 goto state_err;
1740 }
1741
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301742 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301743
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001744state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301745 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301746 return ret;
1747}
1748EXPORT_SYMBOL(sdw_disable_stream);
1749
1750static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1751{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001752 struct sdw_master_runtime *m_rt;
1753 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301754 int ret = 0;
1755
Vinod Koul48949722018-07-27 14:44:14 +05301756 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1757 bus = m_rt->bus;
1758 /* De-prepare port(s) */
1759 ret = sdw_prep_deprep_ports(m_rt, false);
1760 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301761 dev_err(bus->dev,
1762 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301763 return ret;
1764 }
1765
1766 /* TODO: Update this during Device-Device support */
1767 bus->params.bandwidth -= m_rt->stream->params.rate *
1768 m_rt->ch_count * m_rt->stream->params.bps;
1769
1770 /* Program params */
1771 ret = sdw_program_params(bus);
1772 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001773 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301774 return ret;
1775 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301776 }
1777
1778 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301779 return do_bank_switch(stream);
1780}
1781
1782/**
1783 * sdw_deprepare_stream() - Deprepare SoundWire stream
1784 *
1785 * @stream: Soundwire stream
1786 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001787 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301788 */
1789int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1790{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001791 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301792
1793 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001794 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301795 return -EINVAL;
1796 }
1797
Vinod Koul48949722018-07-27 14:44:14 +05301798 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001799
1800 if (stream->state != SDW_STREAM_PREPARED &&
1801 stream->state != SDW_STREAM_DISABLED) {
1802 pr_err("%s: %s: inconsistent state state %d\n",
1803 __func__, stream->name, stream->state);
1804 ret = -EINVAL;
1805 goto state_err;
1806 }
1807
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301808 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301809
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001810state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301811 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301812 return ret;
1813}
1814EXPORT_SYMBOL(sdw_deprepare_stream);