blob: 166b0c16003f500206b52fcd42177f7a7bcfe474 [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
24int rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
25 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
28int cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
29
30static int sdw_find_col_index(int col)
31{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
35 if (cols[i] == col)
36 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
42
43static int sdw_find_row_index(int row)
44{
45 int i;
46
47 for (i = 0; i < SDW_FRAME_ROWS; i++) {
48 if (rows[i] == row)
49 return i;
50 }
51
52 pr_warn("Requested row not found, selecting lowest row no: 48\n");
53 return 0;
54}
Sanyog Kalef8101c72018-04-26 18:38:17 +053055static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050056 struct sdw_slave *slave,
57 struct sdw_transport_params *t_params,
58 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053059{
60 u32 addr1, addr2, addr3, addr4;
61 int ret;
62 u16 wbuf;
63
64 if (bus->params.next_bank) {
65 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
66 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
67 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
68 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
69 } else {
70 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
71 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
72 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
73 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
74 }
75
76 /* Program DPN_OffsetCtrl2 registers */
77 ret = sdw_write(slave, addr1, t_params->offset2);
78 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050079 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053080 return ret;
81 }
82
83 /* Program DPN_BlockCtrl3 register */
84 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
85 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050086 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053087 return ret;
88 }
89
90 /*
91 * Data ports are FULL, SIMPLE and REDUCED. This function handles
92 * FULL and REDUCED only and and beyond this point only FULL is
93 * handled, so bail out if we are not FULL data port type
94 */
95 if (type != SDW_DPN_FULL)
96 return ret;
97
98 /* Program DPN_SampleCtrl2 register */
99 wbuf = (t_params->sample_interval - 1);
100 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
101 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
102
103 ret = sdw_write(slave, addr3, wbuf);
104 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500105 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530106 return ret;
107 }
108
109 /* Program DPN_HCtrl register */
110 wbuf = t_params->hstart;
111 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
112 wbuf |= t_params->hstop;
113
114 ret = sdw_write(slave, addr4, wbuf);
115 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500116 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530117
118 return ret;
119}
120
121static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500122 struct sdw_slave_runtime *s_rt,
123 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530124{
125 struct sdw_transport_params *t_params = &p_rt->transport_params;
126 struct sdw_port_params *p_params = &p_rt->port_params;
127 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
128 u32 addr1, addr2, addr3, addr4, addr5, addr6;
129 struct sdw_dpn_prop *dpn_prop;
130 int ret;
131 u8 wbuf;
132
133 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500134 s_rt->direction,
135 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530136 if (!dpn_prop)
137 return -EINVAL;
138
139 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
140 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
141
142 if (bus->params.next_bank) {
143 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
144 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
145 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
146 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
147
148 } else {
149 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
150 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
151 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
152 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
153 }
154
155 /* Program DPN_PortCtrl register */
156 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
157 wbuf |= p_params->flow_mode;
158
159 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
160 if (ret < 0) {
161 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500162 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530163 t_params->port_num);
164 return ret;
165 }
166
167 /* Program DPN_BlockCtrl1 register */
168 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
169 if (ret < 0) {
170 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500171 "DPN_BlockCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530172 t_params->port_num);
173 return ret;
174 }
175
176 /* Program DPN_SampleCtrl1 register */
177 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
178 ret = sdw_write(s_rt->slave, addr3, wbuf);
179 if (ret < 0) {
180 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500181 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530182 t_params->port_num);
183 return ret;
184 }
185
186 /* Program DPN_OffsetCtrl1 registers */
187 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
188 if (ret < 0) {
189 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500190 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530191 t_params->port_num);
192 return ret;
193 }
194
195 /* Program DPN_BlockCtrl2 register*/
196 if (t_params->blk_grp_ctrl_valid) {
197 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
198 if (ret < 0) {
199 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500200 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530201 t_params->port_num);
202 return ret;
203 }
204 }
205
206 /* program DPN_LaneCtrl register */
207 if (slave_prop->lane_control_support) {
208 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
209 if (ret < 0) {
210 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500211 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530212 t_params->port_num);
213 return ret;
214 }
215 }
216
217 if (dpn_prop->type != SDW_DPN_SIMPLE) {
218 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500219 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530220 if (ret < 0)
221 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500222 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530223 t_params->port_num);
224 }
225
226 return ret;
227}
228
229static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500230 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530231{
232 int ret;
233
234 /*
235 * we need to set transport and port parameters for the port.
236 * Transport parameters refers to the smaple interval, offsets and
237 * hstart/stop etc of the data. Port parameters refers to word
238 * length, flow mode etc of the port
239 */
240 ret = bus->port_ops->dpn_set_port_transport_params(bus,
241 &p_rt->transport_params,
242 bus->params.next_bank);
243 if (ret < 0)
244 return ret;
245
246 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500247 &p_rt->port_params,
248 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530249}
250
251/**
252 * sdw_program_port_params() - Programs transport parameters of Master(s)
253 * and Slave(s)
254 *
255 * @m_rt: Master stream runtime
256 */
257static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
258{
259 struct sdw_slave_runtime *s_rt = NULL;
260 struct sdw_bus *bus = m_rt->bus;
261 struct sdw_port_runtime *p_rt;
262 int ret = 0;
263
264 /* Program transport & port parameters for Slave(s) */
265 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
266 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
267 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
268 if (ret < 0)
269 return ret;
270 }
271 }
272
273 /* Program transport & port parameters for Master(s) */
274 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
275 ret = sdw_program_master_port_params(bus, p_rt);
276 if (ret < 0)
277 return ret;
278 }
279
280 return 0;
281}
282
Sanyog Kale89e59052018-04-26 18:38:08 +0530283/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530284 * sdw_enable_disable_slave_ports: Enable/disable slave data port
285 *
286 * @bus: bus instance
287 * @s_rt: slave runtime
288 * @p_rt: port runtime
289 * @en: enable or disable operation
290 *
291 * This function only sets the enable/disable bits in the relevant bank, the
292 * actual enable/disable is done with a bank switch
293 */
294static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500295 struct sdw_slave_runtime *s_rt,
296 struct sdw_port_runtime *p_rt,
297 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530298{
299 struct sdw_transport_params *t_params = &p_rt->transport_params;
300 u32 addr;
301 int ret;
302
303 if (bus->params.next_bank)
304 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
305 else
306 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
307
308 /*
309 * Since bus doesn't support sharing a port across two streams,
310 * it is safe to reset this register
311 */
312 if (en)
313 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
314 else
315 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
316
317 if (ret < 0)
318 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500319 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530320 ret, t_params->port_num);
321
322 return ret;
323}
324
325static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500326 struct sdw_port_runtime *p_rt,
327 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530328{
329 struct sdw_transport_params *t_params = &p_rt->transport_params;
330 struct sdw_bus *bus = m_rt->bus;
331 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500332 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530333
334 enable_ch.port_num = p_rt->num;
335 enable_ch.ch_mask = p_rt->ch_mask;
336 enable_ch.enable = en;
337
338 /* Perform Master port channel(s) enable/disable */
339 if (bus->port_ops->dpn_port_enable_ch) {
340 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500341 &enable_ch,
342 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530343 if (ret < 0) {
344 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500345 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530346 ret, t_params->port_num);
347 return ret;
348 }
349 } else {
350 dev_err(bus->dev,
351 "dpn_port_enable_ch not supported, %s failed\n",
352 en ? "enable" : "disable");
353 return -EINVAL;
354 }
355
356 return 0;
357}
358
359/**
360 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
361 * Slave(s)
362 *
363 * @m_rt: Master stream runtime
364 * @en: mode (enable/disable)
365 */
366static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
367{
368 struct sdw_port_runtime *s_port, *m_port;
369 struct sdw_slave_runtime *s_rt = NULL;
370 int ret = 0;
371
372 /* Enable/Disable Slave port(s) */
373 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
374 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
375 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500376 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530377 if (ret < 0)
378 return ret;
379 }
380 }
381
382 /* Enable/Disable Master port(s) */
383 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
384 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
385 if (ret < 0)
386 return ret;
387 }
388
389 return 0;
390}
391
392static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500393 struct sdw_prepare_ch prep_ch,
394 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530395{
396 const struct sdw_slave_ops *ops = s_rt->slave->ops;
397 int ret;
398
399 if (ops->port_prep) {
400 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
401 if (ret < 0) {
402 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500403 "Slave Port Prep cmd %d failed: %d\n", cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530404 return ret;
405 }
406 }
407
408 return 0;
409}
410
411static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500412 struct sdw_slave_runtime *s_rt,
413 struct sdw_port_runtime *p_rt,
414 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530415{
416 struct completion *port_ready = NULL;
417 struct sdw_dpn_prop *dpn_prop;
418 struct sdw_prepare_ch prep_ch;
419 unsigned int time_left;
420 bool intr = false;
421 int ret = 0, val;
422 u32 addr;
423
424 prep_ch.num = p_rt->num;
425 prep_ch.ch_mask = p_rt->ch_mask;
426
427 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500428 s_rt->direction,
429 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530430 if (!dpn_prop) {
431 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500432 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530433 return -EINVAL;
434 }
435
436 prep_ch.prepare = prep;
437
438 prep_ch.bank = bus->params.next_bank;
439
440 if (dpn_prop->device_interrupts || !dpn_prop->simple_ch_prep_sm)
441 intr = true;
442
443 /*
444 * Enable interrupt before Port prepare.
445 * For Port de-prepare, it is assumed that port
446 * was prepared earlier
447 */
448 if (prep && intr) {
449 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500450 dpn_prop->device_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530451 if (ret < 0)
452 return ret;
453 }
454
455 /* Inform slave about the impending port prepare */
456 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
457
458 /* Prepare Slave port implementing CP_SM */
459 if (!dpn_prop->simple_ch_prep_sm) {
460 addr = SDW_DPN_PREPARECTRL(p_rt->num);
461
462 if (prep)
463 ret = sdw_update(s_rt->slave, addr,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500464 0xFF, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530465 else
466 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
467
468 if (ret < 0) {
469 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500470 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530471 return ret;
472 }
473
474 /* Wait for completion on port ready */
475 port_ready = &s_rt->slave->port_ready[prep_ch.num];
476 time_left = wait_for_completion_timeout(port_ready,
477 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
478
479 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
480 val &= p_rt->ch_mask;
481 if (!time_left || val) {
482 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500483 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530484 return -ETIMEDOUT;
485 }
486 }
487
488 /* Inform slaves about ports prepared */
489 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
490
491 /* Disable interrupt after Port de-prepare */
492 if (!prep && intr)
493 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500494 dpn_prop->device_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530495
496 return ret;
497}
498
499static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500500 struct sdw_port_runtime *p_rt,
501 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530502{
503 struct sdw_transport_params *t_params = &p_rt->transport_params;
504 struct sdw_bus *bus = m_rt->bus;
505 const struct sdw_master_port_ops *ops = bus->port_ops;
506 struct sdw_prepare_ch prep_ch;
507 int ret = 0;
508
509 prep_ch.num = p_rt->num;
510 prep_ch.ch_mask = p_rt->ch_mask;
511 prep_ch.prepare = prep; /* Prepare/De-prepare */
512 prep_ch.bank = bus->params.next_bank;
513
514 /* Pre-prepare/Pre-deprepare port(s) */
515 if (ops->dpn_port_prep) {
516 ret = ops->dpn_port_prep(bus, &prep_ch);
517 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500518 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500519 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530520 return ret;
521 }
522 }
523
524 return ret;
525}
526
527/**
528 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
529 * Slave(s)
530 *
531 * @m_rt: Master runtime handle
532 * @prep: Prepare or De-prepare
533 */
534static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
535{
536 struct sdw_slave_runtime *s_rt = NULL;
537 struct sdw_port_runtime *p_rt;
538 int ret = 0;
539
540 /* Prepare/De-prepare Slave port(s) */
541 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
542 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
543 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500544 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530545 if (ret < 0)
546 return ret;
547 }
548 }
549
550 /* Prepare/De-prepare Master port(s) */
551 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
552 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
553 if (ret < 0)
554 return ret;
555 }
556
557 return ret;
558}
559
560/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530561 * sdw_notify_config() - Notify bus configuration
562 *
563 * @m_rt: Master runtime handle
564 *
565 * This function notifies the Master(s) and Slave(s) of the
566 * new bus configuration.
567 */
568static int sdw_notify_config(struct sdw_master_runtime *m_rt)
569{
570 struct sdw_slave_runtime *s_rt;
571 struct sdw_bus *bus = m_rt->bus;
572 struct sdw_slave *slave;
573 int ret = 0;
574
575 if (bus->ops->set_bus_conf) {
576 ret = bus->ops->set_bus_conf(bus, &bus->params);
577 if (ret < 0)
578 return ret;
579 }
580
581 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
582 slave = s_rt->slave;
583
584 if (slave->ops->bus_config) {
585 ret = slave->ops->bus_config(slave, &bus->params);
586 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500587 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500588 slave->dev_num);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530589 return ret;
590 }
591 }
592
593 return ret;
594}
595
596/**
597 * sdw_program_params() - Program transport and port parameters for Master(s)
598 * and Slave(s)
599 *
600 * @bus: SDW bus instance
601 */
602static int sdw_program_params(struct sdw_bus *bus)
603{
604 struct sdw_master_runtime *m_rt = NULL;
605 int ret = 0;
606
607 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
608 ret = sdw_program_port_params(m_rt);
609 if (ret < 0) {
610 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500611 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530612 return ret;
613 }
614
615 ret = sdw_notify_config(m_rt);
616 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500617 dev_err(bus->dev, "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530618 return ret;
619 }
620
621 /* Enable port(s) on alternate bank for all active streams */
622 if (m_rt->stream->state != SDW_STREAM_ENABLED)
623 continue;
624
625 ret = sdw_enable_disable_ports(m_rt, true);
626 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500627 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530628 return ret;
629 }
630 }
631
632 return ret;
633}
634
Shreyas NCce6e74d2018-07-27 14:44:16 +0530635static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530636{
637 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530638 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530639 struct sdw_msg *wr_msg;
640 u8 *wbuf = NULL;
641 int ret = 0;
642 u16 addr;
643
644 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
645 if (!wr_msg)
646 return -ENOMEM;
647
Shreyas NCce6e74d2018-07-27 14:44:16 +0530648 bus->defer_msg.msg = wr_msg;
649
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530650 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
651 if (!wbuf) {
652 ret = -ENOMEM;
653 goto error_1;
654 }
655
656 /* Get row and column index to program register */
657 col_index = sdw_find_col_index(bus->params.col);
658 row_index = sdw_find_row_index(bus->params.row);
659 wbuf[0] = col_index | (row_index << 3);
660
661 if (bus->params.next_bank)
662 addr = SDW_SCP_FRAMECTRL_B1;
663 else
664 addr = SDW_SCP_FRAMECTRL_B0;
665
666 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500667 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530668 wr_msg->ssp_sync = true;
669
Shreyas NCce6e74d2018-07-27 14:44:16 +0530670 /*
671 * Set the multi_link flag only when both the hardware supports
672 * and there is a stream handled by multiple masters
673 */
674 multi_link = bus->multi_link && (m_rt_count > 1);
675
676 if (multi_link)
677 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
678 else
679 ret = sdw_transfer(bus, wr_msg);
680
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530681 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500682 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530683 goto error;
684 }
685
Shreyas NCce6e74d2018-07-27 14:44:16 +0530686 if (!multi_link) {
687 kfree(wr_msg);
688 kfree(wbuf);
689 bus->defer_msg.msg = NULL;
690 bus->params.curr_bank = !bus->params.curr_bank;
691 bus->params.next_bank = !bus->params.next_bank;
692 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530693
694 return 0;
695
696error:
697 kfree(wbuf);
698error_1:
699 kfree(wr_msg);
700 return ret;
701}
702
Shreyas NCce6e74d2018-07-27 14:44:16 +0530703/**
704 * sdw_ml_sync_bank_switch: Multilink register bank switch
705 *
706 * @bus: SDW bus instance
707 *
708 * Caller function should free the buffers on error
709 */
710static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
711{
712 unsigned long time_left;
713
714 if (!bus->multi_link)
715 return 0;
716
717 /* Wait for completion of transfer */
718 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
719 bus->bank_switch_timeout);
720
721 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500722 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530723 return -ETIMEDOUT;
724 }
725
726 bus->params.curr_bank = !bus->params.curr_bank;
727 bus->params.next_bank = !bus->params.next_bank;
728
729 if (bus->defer_msg.msg) {
730 kfree(bus->defer_msg.msg->buf);
731 kfree(bus->defer_msg.msg);
732 }
733
734 return 0;
735}
736
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530737static int do_bank_switch(struct sdw_stream_runtime *stream)
738{
Vinod Koul48949722018-07-27 14:44:14 +0530739 struct sdw_master_runtime *m_rt = NULL;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530740 const struct sdw_master_ops *ops;
Vinod Koul48949722018-07-27 14:44:14 +0530741 struct sdw_bus *bus = NULL;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530742 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530743 int ret = 0;
744
Vinod Koul48949722018-07-27 14:44:14 +0530745 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
746 bus = m_rt->bus;
747 ops = bus->ops;
748
Shreyas NCce6e74d2018-07-27 14:44:16 +0530749 if (bus->multi_link) {
750 multi_link = true;
751 mutex_lock(&bus->msg_lock);
752 }
753
Vinod Koul48949722018-07-27 14:44:14 +0530754 /* Pre-bank switch */
755 if (ops->pre_bank_switch) {
756 ret = ops->pre_bank_switch(bus);
757 if (ret < 0) {
758 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500759 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530760 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530761 }
762 }
763
Shreyas NCce6e74d2018-07-27 14:44:16 +0530764 /*
765 * Perform Bank switch operation.
766 * For multi link cases, the actual bank switch is
767 * synchronized across all Masters and happens later as a
768 * part of post_bank_switch ops.
769 */
770 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530771 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500772 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530773 goto error;
774
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530775 }
776 }
777
Shreyas NCce6e74d2018-07-27 14:44:16 +0530778 /*
779 * For multi link cases, it is expected that the bank switch is
780 * triggered by the post_bank_switch for the first Master in the list
781 * and for the other Masters the post_bank_switch() should return doing
782 * nothing.
783 */
Vinod Koul48949722018-07-27 14:44:14 +0530784 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
785 bus = m_rt->bus;
786 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530787
Vinod Koul48949722018-07-27 14:44:14 +0530788 /* Post-bank switch */
789 if (ops->post_bank_switch) {
790 ret = ops->post_bank_switch(bus);
791 if (ret < 0) {
792 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500793 "Post bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530794 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530795 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530796 } else if (bus->multi_link && stream->m_rt_count > 1) {
797 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500798 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530799 goto error;
800 }
801
802 /* Set the bank switch timeout to default, if not set */
803 if (!bus->bank_switch_timeout)
804 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
805
806 /* Check if bank switch was successful */
807 ret = sdw_ml_sync_bank_switch(bus);
808 if (ret < 0) {
809 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500810 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530811 goto error;
812 }
813
814 mutex_unlock(&bus->msg_lock);
815 }
816
817 return ret;
818
819error:
820 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
821
822 bus = m_rt->bus;
823
824 kfree(bus->defer_msg.msg->buf);
825 kfree(bus->defer_msg.msg);
826 }
827
828msg_unlock:
829
830 if (multi_link) {
831 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
832 bus = m_rt->bus;
833 if (mutex_is_locked(&bus->msg_lock))
834 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530835 }
836 }
837
838 return ret;
839}
840
841/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530842 * sdw_release_stream() - Free the assigned stream runtime
843 *
844 * @stream: SoundWire stream runtime
845 *
846 * sdw_release_stream should be called only once per stream
847 */
848void sdw_release_stream(struct sdw_stream_runtime *stream)
849{
850 kfree(stream);
851}
852EXPORT_SYMBOL(sdw_release_stream);
853
854/**
855 * sdw_alloc_stream() - Allocate and return stream runtime
856 *
857 * @stream_name: SoundWire stream name
858 *
859 * Allocates a SoundWire stream runtime instance.
860 * sdw_alloc_stream should be called only once per stream. Typically
861 * invoked from ALSA/ASoC machine/platform driver.
862 */
863struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name)
864{
865 struct sdw_stream_runtime *stream;
866
867 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
868 if (!stream)
869 return NULL;
870
871 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530872 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530873 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530874 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530875
876 return stream;
877}
878EXPORT_SYMBOL(sdw_alloc_stream);
879
Vinod Koul48949722018-07-27 14:44:14 +0530880static struct sdw_master_runtime
881*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500882 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530883{
884 struct sdw_master_runtime *m_rt = NULL;
885
886 /* Retrieve Bus handle if already available */
887 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
888 if (m_rt->bus == bus)
889 return m_rt;
890 }
891
892 return NULL;
893}
894
Sanyog Kale89e59052018-04-26 18:38:08 +0530895/**
896 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
897 *
898 * @bus: SDW bus instance
899 * @stream_config: Stream configuration
900 * @stream: Stream runtime handle.
901 *
902 * This function is to be called with bus_lock held.
903 */
904static struct sdw_master_runtime
905*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500906 struct sdw_stream_config *stream_config,
907 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530908{
909 struct sdw_master_runtime *m_rt;
910
Sanyog Kale89e59052018-04-26 18:38:08 +0530911 /*
912 * check if Master is already allocated (as a result of Slave adding
913 * it first), if so skip allocation and go to configure
914 */
Vinod Koul48949722018-07-27 14:44:14 +0530915 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530916 if (m_rt)
917 goto stream_config;
918
919 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
920 if (!m_rt)
921 return NULL;
922
923 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530924 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530925 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530926 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530927
928 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
929
930stream_config:
931 m_rt->ch_count = stream_config->ch_count;
932 m_rt->bus = bus;
933 m_rt->stream = stream;
934 m_rt->direction = stream_config->direction;
935
936 return m_rt;
937}
938
939/**
940 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
941 *
942 * @slave: Slave handle
943 * @stream_config: Stream configuration
944 * @stream: Stream runtime handle
945 *
946 * This function is to be called with bus_lock held.
947 */
948static struct sdw_slave_runtime
949*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500950 struct sdw_stream_config *stream_config,
951 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530952{
953 struct sdw_slave_runtime *s_rt = NULL;
954
955 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
956 if (!s_rt)
957 return NULL;
958
Sanyog Kalebbe73792018-04-26 18:38:13 +0530959 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530960 s_rt->ch_count = stream_config->ch_count;
961 s_rt->direction = stream_config->direction;
962 s_rt->slave = slave;
963
964 return s_rt;
965}
966
Sanyog Kalebbe73792018-04-26 18:38:13 +0530967static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500968 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530969{
970 struct sdw_port_runtime *p_rt, *_p_rt;
971
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500972 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530973 list_del(&p_rt->port_node);
974 kfree(p_rt);
975 }
976}
977
978static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500979 struct sdw_slave *slave,
980 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530981{
982 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530983 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +0530984 struct sdw_slave_runtime *s_rt;
985
Vinod Koul48949722018-07-27 14:44:14 +0530986 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
987 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530988
Vinod Koul48949722018-07-27 14:44:14 +0530989 if (s_rt->slave != slave)
990 continue;
991
992 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500993 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530994
995 list_del(&p_rt->port_node);
996 kfree(p_rt);
997 }
Sanyog Kalebbe73792018-04-26 18:38:13 +0530998 }
999 }
1000}
1001
Sanyog Kale89e59052018-04-26 18:38:08 +05301002/**
1003 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1004 *
1005 * @slave: Slave handle.
1006 * @stream: Stream runtime handle.
1007 *
1008 * This function is to be called with bus_lock held.
1009 */
1010static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001011 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301012{
1013 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301014 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301015
Vinod Koul48949722018-07-27 14:44:14 +05301016 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1017 /* Retrieve Slave runtime handle */
1018 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001019 &m_rt->slave_rt_list, m_rt_node) {
Sanyog Kale89e59052018-04-26 18:38:08 +05301020
Vinod Koul48949722018-07-27 14:44:14 +05301021 if (s_rt->slave == slave) {
1022 list_del(&s_rt->m_rt_node);
1023 kfree(s_rt);
1024 return;
1025 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301026 }
1027 }
1028}
1029
1030/**
1031 * sdw_release_master_stream() - Free Master runtime handle
1032 *
Vinod Koul48949722018-07-27 14:44:14 +05301033 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301034 * @stream: Stream runtime handle.
1035 *
1036 * This function is to be called with bus_lock held
1037 * It frees the Master runtime handle and associated Slave(s) runtime
1038 * handle. If this is called first then sdw_release_slave_stream() will have
1039 * no effect as Slave(s) runtime handle would already be freed up.
1040 */
Vinod Koul48949722018-07-27 14:44:14 +05301041static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001042 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301043{
Sanyog Kale89e59052018-04-26 18:38:08 +05301044 struct sdw_slave_runtime *s_rt, *_s_rt;
1045
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301046 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1047 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1048 sdw_release_slave_stream(s_rt->slave, stream);
1049 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301050
Vinod Koul48949722018-07-27 14:44:14 +05301051 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301052 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301053 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301054}
1055
1056/**
1057 * sdw_stream_remove_master() - Remove master from sdw_stream
1058 *
1059 * @bus: SDW Bus instance
1060 * @stream: SoundWire stream
1061 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301062 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301063 */
1064int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001065 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301066{
Vinod Koul48949722018-07-27 14:44:14 +05301067 struct sdw_master_runtime *m_rt, *_m_rt;
1068
Sanyog Kale89e59052018-04-26 18:38:08 +05301069 mutex_lock(&bus->bus_lock);
1070
Vinod Koul48949722018-07-27 14:44:14 +05301071 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001072 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301073
1074 if (m_rt->bus != bus)
1075 continue;
1076
1077 sdw_master_port_release(bus, m_rt);
1078 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301079 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301080 }
1081
1082 if (list_empty(&stream->master_list))
1083 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301084
1085 mutex_unlock(&bus->bus_lock);
1086
1087 return 0;
1088}
1089EXPORT_SYMBOL(sdw_stream_remove_master);
1090
1091/**
1092 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1093 *
1094 * @slave: SDW Slave instance
1095 * @stream: SoundWire stream
1096 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301097 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301098 */
1099int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001100 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301101{
1102 mutex_lock(&slave->bus->bus_lock);
1103
Sanyog Kalebbe73792018-04-26 18:38:13 +05301104 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301105 sdw_release_slave_stream(slave, stream);
1106
1107 mutex_unlock(&slave->bus->bus_lock);
1108
1109 return 0;
1110}
1111EXPORT_SYMBOL(sdw_stream_remove_slave);
1112
1113/**
1114 * sdw_config_stream() - Configure the allocated stream
1115 *
1116 * @dev: SDW device
1117 * @stream: SoundWire stream
1118 * @stream_config: Stream configuration for audio stream
1119 * @is_slave: is API called from Slave or Master
1120 *
1121 * This function is to be called with bus_lock held.
1122 */
1123static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001124 struct sdw_stream_runtime *stream,
1125 struct sdw_stream_config *stream_config,
1126 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301127{
1128 /*
1129 * Update the stream rate, channel and bps based on data
1130 * source. For more than one data source (multilink),
1131 * match the rate, bps, stream type and increment number of channels.
1132 *
1133 * If rate/bps is zero, it means the values are not set, so skip
1134 * comparison and allow the value to be set and stored in stream
1135 */
1136 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001137 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001138 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301139 return -EINVAL;
1140 }
1141
1142 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001143 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001144 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301145 return -EINVAL;
1146 }
1147
1148 stream->type = stream_config->type;
1149 stream->params.rate = stream_config->frame_rate;
1150 stream->params.bps = stream_config->bps;
1151
1152 /* TODO: Update this check during Device-device support */
1153 if (is_slave)
1154 stream->params.ch_count += stream_config->ch_count;
1155
1156 return 0;
1157}
1158
Sanyog Kalebbe73792018-04-26 18:38:13 +05301159static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001160 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301161{
1162 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1163 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001164 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301165 return -EINVAL;
1166 }
1167
1168 return 0;
1169}
1170
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001171static struct sdw_port_runtime
1172*sdw_port_alloc(struct device *dev,
1173 struct sdw_port_config *port_config,
1174 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301175{
1176 struct sdw_port_runtime *p_rt;
1177
1178 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1179 if (!p_rt)
1180 return NULL;
1181
1182 p_rt->ch_mask = port_config[port_index].ch_mask;
1183 p_rt->num = port_config[port_index].num;
1184
1185 return p_rt;
1186}
1187
1188static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001189 struct sdw_master_runtime *m_rt,
1190 struct sdw_port_config *port_config,
1191 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301192{
1193 struct sdw_port_runtime *p_rt;
1194 int i;
1195
1196 /* Iterate for number of ports to perform initialization */
1197 for (i = 0; i < num_ports; i++) {
1198 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1199 if (!p_rt)
1200 return -ENOMEM;
1201
1202 /*
1203 * TODO: Check port capabilities for requested
1204 * configuration (audio mode support)
1205 */
1206
1207 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1208 }
1209
1210 return 0;
1211}
1212
1213static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001214 struct sdw_slave_runtime *s_rt,
1215 struct sdw_port_config *port_config,
1216 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301217{
1218 struct sdw_port_runtime *p_rt;
1219 int i, ret;
1220
1221 /* Iterate for number of ports to perform initialization */
1222 for (i = 0; i < num_config; i++) {
1223 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1224 if (!p_rt)
1225 return -ENOMEM;
1226
1227 /*
1228 * TODO: Check valid port range as defined by DisCo/
1229 * slave
1230 */
1231 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1232 if (ret < 0) {
1233 kfree(p_rt);
1234 return ret;
1235 }
1236
1237 /*
1238 * TODO: Check port capabilities for requested
1239 * configuration (audio mode support)
1240 */
1241
1242 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1243 }
1244
1245 return 0;
1246}
1247
Sanyog Kale89e59052018-04-26 18:38:08 +05301248/**
1249 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1250 *
1251 * @bus: SDW Bus instance
1252 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301253 * @port_config: Port configuration for audio stream
1254 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301255 * @stream: SoundWire stream
1256 */
1257int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001258 struct sdw_stream_config *stream_config,
1259 struct sdw_port_config *port_config,
1260 unsigned int num_ports,
1261 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301262{
1263 struct sdw_master_runtime *m_rt = NULL;
1264 int ret;
1265
1266 mutex_lock(&bus->bus_lock);
1267
Shreyas NCce6e74d2018-07-27 14:44:16 +05301268 /*
1269 * For multi link streams, add the second master only if
1270 * the bus supports it.
1271 * Check if bus->multi_link is set
1272 */
1273 if (!bus->multi_link && stream->m_rt_count > 0) {
1274 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001275 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301276 ret = -EINVAL;
1277 goto unlock;
1278 }
1279
Sanyog Kale89e59052018-04-26 18:38:08 +05301280 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1281 if (!m_rt) {
1282 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001283 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001284 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301285 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301286 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301287 }
1288
1289 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1290 if (ret)
1291 goto stream_error;
1292
Sanyog Kalebbe73792018-04-26 18:38:13 +05301293 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1294 if (ret)
1295 goto stream_error;
1296
Shreyas NCce6e74d2018-07-27 14:44:16 +05301297 stream->m_rt_count++;
1298
Shreyas NC3fef1a22018-07-27 14:44:09 +05301299 goto unlock;
1300
Sanyog Kale89e59052018-04-26 18:38:08 +05301301stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301302 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301303unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301304 mutex_unlock(&bus->bus_lock);
1305 return ret;
1306}
1307EXPORT_SYMBOL(sdw_stream_add_master);
1308
1309/**
1310 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1311 *
1312 * @slave: SDW Slave instance
1313 * @stream_config: Stream configuration for audio stream
1314 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301315 * @port_config: Port configuration for audio stream
1316 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301317 *
1318 * It is expected that Slave is added before adding Master
1319 * to the Stream.
1320 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301321 */
1322int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001323 struct sdw_stream_config *stream_config,
1324 struct sdw_port_config *port_config,
1325 unsigned int num_ports,
1326 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301327{
1328 struct sdw_slave_runtime *s_rt;
1329 struct sdw_master_runtime *m_rt;
1330 int ret;
1331
1332 mutex_lock(&slave->bus->bus_lock);
1333
1334 /*
1335 * If this API is invoked by Slave first then m_rt is not valid.
1336 * So, allocate m_rt and add Slave to it.
1337 */
1338 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1339 if (!m_rt) {
1340 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001341 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001342 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301343 ret = -ENOMEM;
1344 goto error;
1345 }
1346
1347 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1348 if (!s_rt) {
1349 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001350 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001351 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301352 ret = -ENOMEM;
1353 goto stream_error;
1354 }
1355
1356 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1357 if (ret)
1358 goto stream_error;
1359
1360 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1361
Sanyog Kalebbe73792018-04-26 18:38:13 +05301362 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1363 if (ret)
1364 goto stream_error;
1365
Shreyas NC0aebe402018-07-27 14:44:08 +05301366 /*
1367 * Change stream state to CONFIGURED on first Slave add.
1368 * Bus is not aware of number of Slave(s) in a stream at this
1369 * point so cannot depend on all Slave(s) to be added in order to
1370 * change stream state to CONFIGURED.
1371 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301372 stream->state = SDW_STREAM_CONFIGURED;
1373 goto error;
1374
1375stream_error:
1376 /*
1377 * we hit error so cleanup the stream, release all Slave(s) and
1378 * Master runtime
1379 */
Vinod Koul48949722018-07-27 14:44:14 +05301380 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301381error:
1382 mutex_unlock(&slave->bus->bus_lock);
1383 return ret;
1384}
1385EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301386
1387/**
1388 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1389 *
1390 * @slave: Slave handle
1391 * @direction: Data direction.
1392 * @port_num: Port number
1393 */
1394struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001395 enum sdw_data_direction direction,
1396 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301397{
1398 struct sdw_dpn_prop *dpn_prop;
1399 u8 num_ports;
1400 int i;
1401
1402 if (direction == SDW_DATA_DIR_TX) {
1403 num_ports = hweight32(slave->prop.source_ports);
1404 dpn_prop = slave->prop.src_dpn_prop;
1405 } else {
1406 num_ports = hweight32(slave->prop.sink_ports);
1407 dpn_prop = slave->prop.sink_dpn_prop;
1408 }
1409
1410 for (i = 0; i < num_ports; i++) {
1411 dpn_prop = &dpn_prop[i];
1412
1413 if (dpn_prop->num == port_num)
1414 return &dpn_prop[i];
1415 }
1416
1417 return NULL;
1418}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301419
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301420/**
1421 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1422 *
1423 * @stream: SoundWire stream
1424 *
1425 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1426 * stream to reconfigure the bus.
1427 * NOTE: This function is called from SoundWire stream ops and is
1428 * expected that a global lock is held before acquiring bus_lock.
1429 */
1430static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1431{
1432 struct sdw_master_runtime *m_rt = NULL;
1433 struct sdw_bus *bus = NULL;
1434
1435 /* Iterate for all Master(s) in Master list */
1436 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1437 bus = m_rt->bus;
1438
1439 mutex_lock(&bus->bus_lock);
1440 }
1441}
1442
1443/**
1444 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1445 *
1446 * @stream: SoundWire stream
1447 *
1448 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301449 * NOTE: This function is called from SoundWire stream ops and is
1450 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301451 */
1452static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1453{
1454 struct sdw_master_runtime *m_rt = NULL;
1455 struct sdw_bus *bus = NULL;
1456
1457 /* Iterate for all Master(s) in Master list */
1458 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1459 bus = m_rt->bus;
1460 mutex_unlock(&bus->bus_lock);
1461 }
1462}
1463
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301464static int _sdw_prepare_stream(struct sdw_stream_runtime *stream)
1465{
Vinod Koul48949722018-07-27 14:44:14 +05301466 struct sdw_master_runtime *m_rt = NULL;
1467 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301468 struct sdw_master_prop *prop = NULL;
1469 struct sdw_bus_params params;
1470 int ret;
1471
Vinod Koul48949722018-07-27 14:44:14 +05301472 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1473 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1474 bus = m_rt->bus;
1475 prop = &bus->prop;
1476 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301477
Vinod Koul48949722018-07-27 14:44:14 +05301478 /* TODO: Support Asynchronous mode */
1479 if ((prop->max_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001480 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301481 return -EINVAL;
1482 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301483
Vinod Koul48949722018-07-27 14:44:14 +05301484 /* Increment cumulative bus bandwidth */
1485 /* TODO: Update this during Device-Device support */
1486 bus->params.bandwidth += m_rt->stream->params.rate *
1487 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301488
Vinod Koul48949722018-07-27 14:44:14 +05301489 /* Program params */
1490 ret = sdw_program_params(bus);
1491 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001492 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301493 goto restore_params;
1494 }
1495
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301496 }
1497
1498 ret = do_bank_switch(stream);
1499 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001500 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301501 goto restore_params;
1502 }
1503
Vinod Koul48949722018-07-27 14:44:14 +05301504 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1505 bus = m_rt->bus;
1506
1507 /* Prepare port(s) on the new clock configuration */
1508 ret = sdw_prep_deprep_ports(m_rt, true);
1509 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001510 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001511 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301512 return ret;
1513 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301514 }
1515
1516 stream->state = SDW_STREAM_PREPARED;
1517
1518 return ret;
1519
1520restore_params:
1521 memcpy(&bus->params, &params, sizeof(params));
1522 return ret;
1523}
1524
1525/**
1526 * sdw_prepare_stream() - Prepare SoundWire stream
1527 *
1528 * @stream: Soundwire stream
1529 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001530 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301531 */
1532int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1533{
1534 int ret = 0;
1535
1536 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001537 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301538 return -EINVAL;
1539 }
1540
Vinod Koul48949722018-07-27 14:44:14 +05301541 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301542
1543 ret = _sdw_prepare_stream(stream);
1544 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001545 pr_err("Prepare for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301546
Vinod Koul48949722018-07-27 14:44:14 +05301547 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301548 return ret;
1549}
1550EXPORT_SYMBOL(sdw_prepare_stream);
1551
1552static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1553{
Vinod Koul48949722018-07-27 14:44:14 +05301554 struct sdw_master_runtime *m_rt = NULL;
1555 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301556 int ret;
1557
Vinod Koul48949722018-07-27 14:44:14 +05301558 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1559 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1560 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301561
Vinod Koul48949722018-07-27 14:44:14 +05301562 /* Program params */
1563 ret = sdw_program_params(bus);
1564 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001565 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301566 return ret;
1567 }
1568
1569 /* Enable port(s) */
1570 ret = sdw_enable_disable_ports(m_rt, true);
1571 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001572 dev_err(bus->dev, "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301573 return ret;
1574 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301575 }
1576
1577 ret = do_bank_switch(stream);
1578 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001579 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301580 return ret;
1581 }
1582
1583 stream->state = SDW_STREAM_ENABLED;
1584 return 0;
1585}
1586
1587/**
1588 * sdw_enable_stream() - Enable SoundWire stream
1589 *
1590 * @stream: Soundwire stream
1591 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001592 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301593 */
1594int sdw_enable_stream(struct sdw_stream_runtime *stream)
1595{
1596 int ret = 0;
1597
1598 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001599 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301600 return -EINVAL;
1601 }
1602
Vinod Koul48949722018-07-27 14:44:14 +05301603 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301604
1605 ret = _sdw_enable_stream(stream);
1606 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001607 pr_err("Enable for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301608
Vinod Koul48949722018-07-27 14:44:14 +05301609 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301610 return ret;
1611}
1612EXPORT_SYMBOL(sdw_enable_stream);
1613
1614static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1615{
Vinod Koul48949722018-07-27 14:44:14 +05301616 struct sdw_master_runtime *m_rt = NULL;
1617 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301618 int ret;
1619
Vinod Koul48949722018-07-27 14:44:14 +05301620 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1621 bus = m_rt->bus;
1622 /* Disable port(s) */
1623 ret = sdw_enable_disable_ports(m_rt, false);
1624 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001625 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301626 return ret;
1627 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301628 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301629 stream->state = SDW_STREAM_DISABLED;
1630
Vinod Koul48949722018-07-27 14:44:14 +05301631 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1632 bus = m_rt->bus;
1633 /* Program params */
1634 ret = sdw_program_params(bus);
1635 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001636 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301637 return ret;
1638 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301639 }
1640
1641 return do_bank_switch(stream);
1642}
1643
1644/**
1645 * sdw_disable_stream() - Disable SoundWire stream
1646 *
1647 * @stream: Soundwire stream
1648 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001649 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301650 */
1651int sdw_disable_stream(struct sdw_stream_runtime *stream)
1652{
1653 int ret = 0;
1654
1655 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001656 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301657 return -EINVAL;
1658 }
1659
Vinod Koul48949722018-07-27 14:44:14 +05301660 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301661
1662 ret = _sdw_disable_stream(stream);
1663 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001664 pr_err("Disable for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301665
Vinod Koul48949722018-07-27 14:44:14 +05301666 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301667 return ret;
1668}
1669EXPORT_SYMBOL(sdw_disable_stream);
1670
1671static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1672{
Vinod Koul48949722018-07-27 14:44:14 +05301673 struct sdw_master_runtime *m_rt = NULL;
1674 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301675 int ret = 0;
1676
Vinod Koul48949722018-07-27 14:44:14 +05301677 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1678 bus = m_rt->bus;
1679 /* De-prepare port(s) */
1680 ret = sdw_prep_deprep_ports(m_rt, false);
1681 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001682 dev_err(bus->dev, "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301683 return ret;
1684 }
1685
1686 /* TODO: Update this during Device-Device support */
1687 bus->params.bandwidth -= m_rt->stream->params.rate *
1688 m_rt->ch_count * m_rt->stream->params.bps;
1689
1690 /* Program params */
1691 ret = sdw_program_params(bus);
1692 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001693 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301694 return ret;
1695 }
1696
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301697 }
1698
1699 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301700 return do_bank_switch(stream);
1701}
1702
1703/**
1704 * sdw_deprepare_stream() - Deprepare SoundWire stream
1705 *
1706 * @stream: Soundwire stream
1707 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001708 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301709 */
1710int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1711{
1712 int ret = 0;
1713
1714 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001715 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301716 return -EINVAL;
1717 }
1718
Vinod Koul48949722018-07-27 14:44:14 +05301719 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301720 ret = _sdw_deprepare_stream(stream);
1721 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001722 pr_err("De-prepare for stream:%d failed: %d\n", ret, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301723
Vinod Koul48949722018-07-27 14:44:14 +05301724 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301725 return ret;
1726}
1727EXPORT_SYMBOL(sdw_deprepare_stream);