blob: e4cf484f590526fcda2177076e6af5c8274e4451 [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
Pierre-Louis Bossart45505692020-07-01 02:43:53 +080016#include <sound/soc.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053017#include "bus.h"
18
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053019/*
20 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
21 *
22 * The rows are arranged as per the array index value programmed
23 * in register. The index 15 has dummy value 0 in order to fill hole.
24 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050025int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053026 96, 100, 120, 128, 150, 160, 250, 0,
27 192, 200, 240, 256, 72, 144, 90, 180};
28
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050029int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053030
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050031int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053032{
33 int i;
34
35 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050036 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053037 return i;
38 }
39
40 pr_warn("Requested column not found, selecting lowest column no: 2\n");
41 return 0;
42}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050043EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053044
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050045int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053046{
47 int i;
48
49 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050050 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053051 return i;
52 }
53
54 pr_warn("Requested row not found, selecting lowest row no: 48\n");
55 return 0;
56}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050057EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053058
Sanyog Kalef8101c72018-04-26 18:38:17 +053059static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050060 struct sdw_slave *slave,
61 struct sdw_transport_params *t_params,
62 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053063{
64 u32 addr1, addr2, addr3, addr4;
65 int ret;
66 u16 wbuf;
67
68 if (bus->params.next_bank) {
69 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
70 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
71 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
72 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
73 } else {
74 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
75 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
76 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
77 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
78 }
79
80 /* Program DPN_OffsetCtrl2 registers */
81 ret = sdw_write(slave, addr1, t_params->offset2);
82 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050083 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053084 return ret;
85 }
86
87 /* Program DPN_BlockCtrl3 register */
88 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
89 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050090 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053091 return ret;
92 }
93
94 /*
95 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053096 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053097 * handled, so bail out if we are not FULL data port type
98 */
99 if (type != SDW_DPN_FULL)
100 return ret;
101
102 /* Program DPN_SampleCtrl2 register */
103 wbuf = (t_params->sample_interval - 1);
104 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
105 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
106
107 ret = sdw_write(slave, addr3, wbuf);
108 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500109 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530110 return ret;
111 }
112
113 /* Program DPN_HCtrl register */
114 wbuf = t_params->hstart;
115 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
116 wbuf |= t_params->hstop;
117
118 ret = sdw_write(slave, addr4, wbuf);
119 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500120 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530121
122 return ret;
123}
124
125static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500126 struct sdw_slave_runtime *s_rt,
127 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530128{
129 struct sdw_transport_params *t_params = &p_rt->transport_params;
130 struct sdw_port_params *p_params = &p_rt->port_params;
131 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
132 u32 addr1, addr2, addr3, addr4, addr5, addr6;
133 struct sdw_dpn_prop *dpn_prop;
134 int ret;
135 u8 wbuf;
136
137 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500138 s_rt->direction,
139 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530140 if (!dpn_prop)
141 return -EINVAL;
142
143 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
144 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
145
146 if (bus->params.next_bank) {
147 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
148 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
149 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
150 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
151
152 } else {
153 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
154 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
155 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
156 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
157 }
158
159 /* Program DPN_PortCtrl register */
160 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
161 wbuf |= p_params->flow_mode;
162
163 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
164 if (ret < 0) {
165 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500166 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530167 t_params->port_num);
168 return ret;
169 }
170
Srinivas Kandagatlaa9107de2020-03-11 11:35:44 +0000171 if (!dpn_prop->read_only_wordlength) {
172 /* Program DPN_BlockCtrl1 register */
173 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
174 if (ret < 0) {
175 dev_err(&s_rt->slave->dev,
176 "DPN_BlockCtrl1 register write failed for port %d\n",
177 t_params->port_num);
178 return ret;
179 }
Sanyog Kalef8101c72018-04-26 18:38:17 +0530180 }
181
182 /* Program DPN_SampleCtrl1 register */
183 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
184 ret = sdw_write(s_rt->slave, addr3, wbuf);
185 if (ret < 0) {
186 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500187 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530188 t_params->port_num);
189 return ret;
190 }
191
192 /* Program DPN_OffsetCtrl1 registers */
193 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
194 if (ret < 0) {
195 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500196 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530197 t_params->port_num);
198 return ret;
199 }
200
201 /* Program DPN_BlockCtrl2 register*/
202 if (t_params->blk_grp_ctrl_valid) {
203 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
204 if (ret < 0) {
205 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500206 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530207 t_params->port_num);
208 return ret;
209 }
210 }
211
212 /* program DPN_LaneCtrl register */
213 if (slave_prop->lane_control_support) {
214 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
215 if (ret < 0) {
216 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500217 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530218 t_params->port_num);
219 return ret;
220 }
221 }
222
223 if (dpn_prop->type != SDW_DPN_SIMPLE) {
224 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500225 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530226 if (ret < 0)
227 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500228 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530229 t_params->port_num);
230 }
231
232 return ret;
233}
234
235static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500236 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530237{
238 int ret;
239
240 /*
241 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530242 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530243 * hstart/stop etc of the data. Port parameters refers to word
244 * length, flow mode etc of the port
245 */
246 ret = bus->port_ops->dpn_set_port_transport_params(bus,
247 &p_rt->transport_params,
248 bus->params.next_bank);
249 if (ret < 0)
250 return ret;
251
252 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500253 &p_rt->port_params,
254 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530255}
256
257/**
258 * sdw_program_port_params() - Programs transport parameters of Master(s)
259 * and Slave(s)
260 *
261 * @m_rt: Master stream runtime
262 */
263static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
264{
265 struct sdw_slave_runtime *s_rt = NULL;
266 struct sdw_bus *bus = m_rt->bus;
267 struct sdw_port_runtime *p_rt;
268 int ret = 0;
269
270 /* Program transport & port parameters for Slave(s) */
271 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
272 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
273 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
274 if (ret < 0)
275 return ret;
276 }
277 }
278
279 /* Program transport & port parameters for Master(s) */
280 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
281 ret = sdw_program_master_port_params(bus, p_rt);
282 if (ret < 0)
283 return ret;
284 }
285
286 return 0;
287}
288
Sanyog Kale89e59052018-04-26 18:38:08 +0530289/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530290 * sdw_enable_disable_slave_ports: Enable/disable slave data port
291 *
292 * @bus: bus instance
293 * @s_rt: slave runtime
294 * @p_rt: port runtime
295 * @en: enable or disable operation
296 *
297 * This function only sets the enable/disable bits in the relevant bank, the
298 * actual enable/disable is done with a bank switch
299 */
300static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500301 struct sdw_slave_runtime *s_rt,
302 struct sdw_port_runtime *p_rt,
303 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530304{
305 struct sdw_transport_params *t_params = &p_rt->transport_params;
306 u32 addr;
307 int ret;
308
309 if (bus->params.next_bank)
310 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
311 else
312 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
313
314 /*
315 * Since bus doesn't support sharing a port across two streams,
316 * it is safe to reset this register
317 */
318 if (en)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000319 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530320 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000321 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530322
323 if (ret < 0)
324 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500325 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530326 ret, t_params->port_num);
327
328 return ret;
329}
330
331static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500332 struct sdw_port_runtime *p_rt,
333 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530334{
335 struct sdw_transport_params *t_params = &p_rt->transport_params;
336 struct sdw_bus *bus = m_rt->bus;
337 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500338 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530339
340 enable_ch.port_num = p_rt->num;
341 enable_ch.ch_mask = p_rt->ch_mask;
342 enable_ch.enable = en;
343
344 /* Perform Master port channel(s) enable/disable */
345 if (bus->port_ops->dpn_port_enable_ch) {
346 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500347 &enable_ch,
348 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530349 if (ret < 0) {
350 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500351 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530352 ret, t_params->port_num);
353 return ret;
354 }
355 } else {
356 dev_err(bus->dev,
357 "dpn_port_enable_ch not supported, %s failed\n",
358 en ? "enable" : "disable");
359 return -EINVAL;
360 }
361
362 return 0;
363}
364
365/**
366 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
367 * Slave(s)
368 *
369 * @m_rt: Master stream runtime
370 * @en: mode (enable/disable)
371 */
372static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
373{
374 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500375 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530376 int ret = 0;
377
378 /* Enable/Disable Slave port(s) */
379 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
380 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
381 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500382 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530383 if (ret < 0)
384 return ret;
385 }
386 }
387
388 /* Enable/Disable Master port(s) */
389 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
390 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
391 if (ret < 0)
392 return ret;
393 }
394
395 return 0;
396}
397
398static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500399 struct sdw_prepare_ch prep_ch,
400 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530401{
402 const struct sdw_slave_ops *ops = s_rt->slave->ops;
403 int ret;
404
405 if (ops->port_prep) {
406 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
407 if (ret < 0) {
408 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530409 "Slave Port Prep cmd %d failed: %d\n",
410 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530411 return ret;
412 }
413 }
414
415 return 0;
416}
417
418static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500419 struct sdw_slave_runtime *s_rt,
420 struct sdw_port_runtime *p_rt,
421 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530422{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500423 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530424 struct sdw_dpn_prop *dpn_prop;
425 struct sdw_prepare_ch prep_ch;
426 unsigned int time_left;
427 bool intr = false;
428 int ret = 0, val;
429 u32 addr;
430
431 prep_ch.num = p_rt->num;
432 prep_ch.ch_mask = p_rt->ch_mask;
433
434 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500435 s_rt->direction,
436 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530437 if (!dpn_prop) {
438 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500439 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530440 return -EINVAL;
441 }
442
443 prep_ch.prepare = prep;
444
445 prep_ch.bank = bus->params.next_bank;
446
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500447 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530448 intr = true;
449
450 /*
451 * Enable interrupt before Port prepare.
452 * For Port de-prepare, it is assumed that port
453 * was prepared earlier
454 */
455 if (prep && intr) {
456 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500457 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530458 if (ret < 0)
459 return ret;
460 }
461
462 /* Inform slave about the impending port prepare */
463 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
464
465 /* Prepare Slave port implementing CP_SM */
466 if (!dpn_prop->simple_ch_prep_sm) {
467 addr = SDW_DPN_PREPARECTRL(p_rt->num);
468
469 if (prep)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000470 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530471 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000472 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530473
474 if (ret < 0) {
475 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500476 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530477 return ret;
478 }
479
480 /* Wait for completion on port ready */
481 port_ready = &s_rt->slave->port_ready[prep_ch.num];
482 time_left = wait_for_completion_timeout(port_ready,
483 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
484
485 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
486 val &= p_rt->ch_mask;
487 if (!time_left || val) {
488 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500489 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530490 return -ETIMEDOUT;
491 }
492 }
493
494 /* Inform slaves about ports prepared */
495 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
496
497 /* Disable interrupt after Port de-prepare */
498 if (!prep && intr)
499 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500500 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530501
502 return ret;
503}
504
505static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500506 struct sdw_port_runtime *p_rt,
507 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530508{
509 struct sdw_transport_params *t_params = &p_rt->transport_params;
510 struct sdw_bus *bus = m_rt->bus;
511 const struct sdw_master_port_ops *ops = bus->port_ops;
512 struct sdw_prepare_ch prep_ch;
513 int ret = 0;
514
515 prep_ch.num = p_rt->num;
516 prep_ch.ch_mask = p_rt->ch_mask;
517 prep_ch.prepare = prep; /* Prepare/De-prepare */
518 prep_ch.bank = bus->params.next_bank;
519
520 /* Pre-prepare/Pre-deprepare port(s) */
521 if (ops->dpn_port_prep) {
522 ret = ops->dpn_port_prep(bus, &prep_ch);
523 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500524 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500525 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530526 return ret;
527 }
528 }
529
530 return ret;
531}
532
533/**
534 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
535 * Slave(s)
536 *
537 * @m_rt: Master runtime handle
538 * @prep: Prepare or De-prepare
539 */
540static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
541{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500542 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530543 struct sdw_port_runtime *p_rt;
544 int ret = 0;
545
546 /* Prepare/De-prepare Slave port(s) */
547 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
548 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
549 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500550 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530551 if (ret < 0)
552 return ret;
553 }
554 }
555
556 /* Prepare/De-prepare Master port(s) */
557 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
558 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
559 if (ret < 0)
560 return ret;
561 }
562
563 return ret;
564}
565
566/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530567 * sdw_notify_config() - Notify bus configuration
568 *
569 * @m_rt: Master runtime handle
570 *
571 * This function notifies the Master(s) and Slave(s) of the
572 * new bus configuration.
573 */
574static int sdw_notify_config(struct sdw_master_runtime *m_rt)
575{
576 struct sdw_slave_runtime *s_rt;
577 struct sdw_bus *bus = m_rt->bus;
578 struct sdw_slave *slave;
579 int ret = 0;
580
581 if (bus->ops->set_bus_conf) {
582 ret = bus->ops->set_bus_conf(bus, &bus->params);
583 if (ret < 0)
584 return ret;
585 }
586
587 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
588 slave = s_rt->slave;
589
590 if (slave->ops->bus_config) {
591 ret = slave->ops->bus_config(slave, &bus->params);
Rander Wang60835022020-01-14 17:52:26 -0600592 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500593 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500594 slave->dev_num);
Rander Wang60835022020-01-14 17:52:26 -0600595 return ret;
596 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530597 }
598 }
599
600 return ret;
601}
602
603/**
604 * sdw_program_params() - Program transport and port parameters for Master(s)
605 * and Slave(s)
606 *
607 * @bus: SDW bus instance
Rander Wangbfaa3542020-01-14 17:52:27 -0600608 * @prepare: true if sdw_program_params() is called by _prepare.
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530609 */
Rander Wangbfaa3542020-01-14 17:52:27 -0600610static int sdw_program_params(struct sdw_bus *bus, bool prepare)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530611{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500612 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530613 int ret = 0;
614
615 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
Rander Wangbfaa3542020-01-14 17:52:27 -0600616
617 /*
618 * this loop walks through all master runtimes for a
619 * bus, but the ports can only be configured while
620 * explicitly preparing a stream or handling an
621 * already-prepared stream otherwise.
622 */
623 if (!prepare &&
624 m_rt->stream->state == SDW_STREAM_CONFIGURED)
625 continue;
626
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530627 ret = sdw_program_port_params(m_rt);
628 if (ret < 0) {
629 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500630 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530631 return ret;
632 }
633
634 ret = sdw_notify_config(m_rt);
635 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530636 dev_err(bus->dev,
637 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530638 return ret;
639 }
640
641 /* Enable port(s) on alternate bank for all active streams */
642 if (m_rt->stream->state != SDW_STREAM_ENABLED)
643 continue;
644
645 ret = sdw_enable_disable_ports(m_rt, true);
646 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500647 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530648 return ret;
649 }
650 }
651
652 return ret;
653}
654
Shreyas NCce6e74d2018-07-27 14:44:16 +0530655static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530656{
657 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530658 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530659 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500660 u8 *wbuf;
661 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530662 u16 addr;
663
664 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
665 if (!wr_msg)
666 return -ENOMEM;
667
Shreyas NCce6e74d2018-07-27 14:44:16 +0530668 bus->defer_msg.msg = wr_msg;
669
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530670 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
671 if (!wbuf) {
672 ret = -ENOMEM;
673 goto error_1;
674 }
675
676 /* Get row and column index to program register */
677 col_index = sdw_find_col_index(bus->params.col);
678 row_index = sdw_find_row_index(bus->params.row);
679 wbuf[0] = col_index | (row_index << 3);
680
681 if (bus->params.next_bank)
682 addr = SDW_SCP_FRAMECTRL_B1;
683 else
684 addr = SDW_SCP_FRAMECTRL_B0;
685
686 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500687 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530688 wr_msg->ssp_sync = true;
689
Shreyas NCce6e74d2018-07-27 14:44:16 +0530690 /*
691 * Set the multi_link flag only when both the hardware supports
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800692 * and hardware-based sync is required
Shreyas NCce6e74d2018-07-27 14:44:16 +0530693 */
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800694 multi_link = bus->multi_link && (m_rt_count >= bus->hw_sync_min_links);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530695
696 if (multi_link)
697 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
698 else
699 ret = sdw_transfer(bus, wr_msg);
700
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530701 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500702 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530703 goto error;
704 }
705
Shreyas NCce6e74d2018-07-27 14:44:16 +0530706 if (!multi_link) {
707 kfree(wr_msg);
708 kfree(wbuf);
709 bus->defer_msg.msg = NULL;
710 bus->params.curr_bank = !bus->params.curr_bank;
711 bus->params.next_bank = !bus->params.next_bank;
712 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530713
714 return 0;
715
716error:
717 kfree(wbuf);
718error_1:
719 kfree(wr_msg);
720 return ret;
721}
722
Shreyas NCce6e74d2018-07-27 14:44:16 +0530723/**
724 * sdw_ml_sync_bank_switch: Multilink register bank switch
725 *
726 * @bus: SDW bus instance
727 *
728 * Caller function should free the buffers on error
729 */
730static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
731{
732 unsigned long time_left;
733
734 if (!bus->multi_link)
735 return 0;
736
737 /* Wait for completion of transfer */
738 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
739 bus->bank_switch_timeout);
740
741 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500742 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530743 return -ETIMEDOUT;
744 }
745
746 bus->params.curr_bank = !bus->params.curr_bank;
747 bus->params.next_bank = !bus->params.next_bank;
748
749 if (bus->defer_msg.msg) {
750 kfree(bus->defer_msg.msg->buf);
751 kfree(bus->defer_msg.msg);
752 }
753
754 return 0;
755}
756
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530757static int do_bank_switch(struct sdw_stream_runtime *stream)
758{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500759 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530760 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500761 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530762 bool multi_link = false;
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800763 int m_rt_count;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530764 int ret = 0;
765
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800766 m_rt_count = stream->m_rt_count;
767
Vinod Koul48949722018-07-27 14:44:14 +0530768 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
769 bus = m_rt->bus;
770 ops = bus->ops;
771
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800772 if (bus->multi_link && m_rt_count >= bus->hw_sync_min_links) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530773 multi_link = true;
774 mutex_lock(&bus->msg_lock);
775 }
776
Vinod Koul48949722018-07-27 14:44:14 +0530777 /* Pre-bank switch */
778 if (ops->pre_bank_switch) {
779 ret = ops->pre_bank_switch(bus);
780 if (ret < 0) {
781 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500782 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530783 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530784 }
785 }
786
Shreyas NCce6e74d2018-07-27 14:44:16 +0530787 /*
788 * Perform Bank switch operation.
789 * For multi link cases, the actual bank switch is
790 * synchronized across all Masters and happens later as a
791 * part of post_bank_switch ops.
792 */
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800793 ret = sdw_bank_switch(bus, m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530794 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500795 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530796 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530797 }
798 }
799
Shreyas NCce6e74d2018-07-27 14:44:16 +0530800 /*
801 * For multi link cases, it is expected that the bank switch is
802 * triggered by the post_bank_switch for the first Master in the list
803 * and for the other Masters the post_bank_switch() should return doing
804 * nothing.
805 */
Vinod Koul48949722018-07-27 14:44:14 +0530806 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
807 bus = m_rt->bus;
808 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530809
Vinod Koul48949722018-07-27 14:44:14 +0530810 /* Post-bank switch */
811 if (ops->post_bank_switch) {
812 ret = ops->post_bank_switch(bus);
813 if (ret < 0) {
814 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530815 "Post bank switch op failed: %d\n",
816 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530817 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530818 }
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800819 } else if (multi_link) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530820 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500821 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530822 goto error;
823 }
824
825 /* Set the bank switch timeout to default, if not set */
826 if (!bus->bank_switch_timeout)
827 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
828
829 /* Check if bank switch was successful */
830 ret = sdw_ml_sync_bank_switch(bus);
831 if (ret < 0) {
832 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500833 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530834 goto error;
835 }
836
Pierre-Louis Bossart063ff4e2020-09-01 23:05:53 +0800837 if (multi_link)
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100838 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530839 }
840
841 return ret;
842
843error:
844 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530845 bus = m_rt->bus;
846
847 kfree(bus->defer_msg.msg->buf);
848 kfree(bus->defer_msg.msg);
849 }
850
851msg_unlock:
852
853 if (multi_link) {
854 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
855 bus = m_rt->bus;
856 if (mutex_is_locked(&bus->msg_lock))
857 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530858 }
859 }
860
861 return ret;
862}
863
864/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530865 * sdw_release_stream() - Free the assigned stream runtime
866 *
867 * @stream: SoundWire stream runtime
868 *
869 * sdw_release_stream should be called only once per stream
870 */
871void sdw_release_stream(struct sdw_stream_runtime *stream)
872{
873 kfree(stream);
874}
875EXPORT_SYMBOL(sdw_release_stream);
876
877/**
878 * sdw_alloc_stream() - Allocate and return stream runtime
879 *
880 * @stream_name: SoundWire stream name
881 *
882 * Allocates a SoundWire stream runtime instance.
883 * sdw_alloc_stream should be called only once per stream. Typically
884 * invoked from ALSA/ASoC machine/platform driver.
885 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100886struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530887{
888 struct sdw_stream_runtime *stream;
889
890 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
891 if (!stream)
892 return NULL;
893
894 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530895 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530896 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530897 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530898
899 return stream;
900}
901EXPORT_SYMBOL(sdw_alloc_stream);
902
Vinod Koul48949722018-07-27 14:44:14 +0530903static struct sdw_master_runtime
904*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500905 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530906{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500907 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530908
909 /* Retrieve Bus handle if already available */
910 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
911 if (m_rt->bus == bus)
912 return m_rt;
913 }
914
915 return NULL;
916}
917
Sanyog Kale89e59052018-04-26 18:38:08 +0530918/**
919 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
920 *
921 * @bus: SDW bus instance
922 * @stream_config: Stream configuration
923 * @stream: Stream runtime handle.
924 *
925 * This function is to be called with bus_lock held.
926 */
927static struct sdw_master_runtime
928*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500929 struct sdw_stream_config *stream_config,
930 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530931{
932 struct sdw_master_runtime *m_rt;
933
Sanyog Kale89e59052018-04-26 18:38:08 +0530934 /*
935 * check if Master is already allocated (as a result of Slave adding
936 * it first), if so skip allocation and go to configure
937 */
Vinod Koul48949722018-07-27 14:44:14 +0530938 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530939 if (m_rt)
940 goto stream_config;
941
942 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
943 if (!m_rt)
944 return NULL;
945
946 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530947 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530948 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530949 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530950
951 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
952
953stream_config:
954 m_rt->ch_count = stream_config->ch_count;
955 m_rt->bus = bus;
956 m_rt->stream = stream;
957 m_rt->direction = stream_config->direction;
958
959 return m_rt;
960}
961
962/**
963 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
964 *
965 * @slave: Slave handle
966 * @stream_config: Stream configuration
967 * @stream: Stream runtime handle
968 *
969 * This function is to be called with bus_lock held.
970 */
971static struct sdw_slave_runtime
972*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500973 struct sdw_stream_config *stream_config,
974 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530975{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500976 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530977
978 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
979 if (!s_rt)
980 return NULL;
981
Sanyog Kalebbe73792018-04-26 18:38:13 +0530982 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530983 s_rt->ch_count = stream_config->ch_count;
984 s_rt->direction = stream_config->direction;
985 s_rt->slave = slave;
986
987 return s_rt;
988}
989
Sanyog Kalebbe73792018-04-26 18:38:13 +0530990static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500991 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530992{
993 struct sdw_port_runtime *p_rt, *_p_rt;
994
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500995 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530996 list_del(&p_rt->port_node);
997 kfree(p_rt);
998 }
999}
1000
1001static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001002 struct sdw_slave *slave,
1003 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301004{
1005 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301006 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +05301007 struct sdw_slave_runtime *s_rt;
1008
Vinod Koul48949722018-07-27 14:44:14 +05301009 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1010 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301011 if (s_rt->slave != slave)
1012 continue;
1013
1014 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001015 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301016 list_del(&p_rt->port_node);
1017 kfree(p_rt);
1018 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301019 }
1020 }
1021}
1022
Sanyog Kale89e59052018-04-26 18:38:08 +05301023/**
1024 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1025 *
1026 * @slave: Slave handle.
1027 * @stream: Stream runtime handle.
1028 *
1029 * This function is to be called with bus_lock held.
1030 */
1031static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001032 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301033{
1034 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301035 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301036
Vinod Koul48949722018-07-27 14:44:14 +05301037 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1038 /* Retrieve Slave runtime handle */
1039 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001040 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301041 if (s_rt->slave == slave) {
1042 list_del(&s_rt->m_rt_node);
1043 kfree(s_rt);
1044 return;
1045 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301046 }
1047 }
1048}
1049
1050/**
1051 * sdw_release_master_stream() - Free Master runtime handle
1052 *
Vinod Koul48949722018-07-27 14:44:14 +05301053 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301054 * @stream: Stream runtime handle.
1055 *
1056 * This function is to be called with bus_lock held
1057 * It frees the Master runtime handle and associated Slave(s) runtime
1058 * handle. If this is called first then sdw_release_slave_stream() will have
1059 * no effect as Slave(s) runtime handle would already be freed up.
1060 */
Vinod Koul48949722018-07-27 14:44:14 +05301061static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001062 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301063{
Sanyog Kale89e59052018-04-26 18:38:08 +05301064 struct sdw_slave_runtime *s_rt, *_s_rt;
1065
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301066 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1067 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1068 sdw_release_slave_stream(s_rt->slave, stream);
1069 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301070
Vinod Koul48949722018-07-27 14:44:14 +05301071 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301072 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301073 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301074}
1075
1076/**
1077 * sdw_stream_remove_master() - Remove master from sdw_stream
1078 *
1079 * @bus: SDW Bus instance
1080 * @stream: SoundWire stream
1081 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301082 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301083 */
1084int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001085 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301086{
Vinod Koul48949722018-07-27 14:44:14 +05301087 struct sdw_master_runtime *m_rt, *_m_rt;
1088
Sanyog Kale89e59052018-04-26 18:38:08 +05301089 mutex_lock(&bus->bus_lock);
1090
Vinod Koul48949722018-07-27 14:44:14 +05301091 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001092 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301093 if (m_rt->bus != bus)
1094 continue;
1095
1096 sdw_master_port_release(bus, m_rt);
1097 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301098 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301099 }
1100
1101 if (list_empty(&stream->master_list))
1102 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301103
1104 mutex_unlock(&bus->bus_lock);
1105
1106 return 0;
1107}
1108EXPORT_SYMBOL(sdw_stream_remove_master);
1109
1110/**
1111 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1112 *
1113 * @slave: SDW Slave instance
1114 * @stream: SoundWire stream
1115 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301116 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301117 */
1118int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001119 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301120{
1121 mutex_lock(&slave->bus->bus_lock);
1122
Sanyog Kalebbe73792018-04-26 18:38:13 +05301123 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301124 sdw_release_slave_stream(slave, stream);
1125
1126 mutex_unlock(&slave->bus->bus_lock);
1127
1128 return 0;
1129}
1130EXPORT_SYMBOL(sdw_stream_remove_slave);
1131
1132/**
1133 * sdw_config_stream() - Configure the allocated stream
1134 *
1135 * @dev: SDW device
1136 * @stream: SoundWire stream
1137 * @stream_config: Stream configuration for audio stream
1138 * @is_slave: is API called from Slave or Master
1139 *
1140 * This function is to be called with bus_lock held.
1141 */
1142static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001143 struct sdw_stream_runtime *stream,
1144 struct sdw_stream_config *stream_config,
1145 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301146{
1147 /*
1148 * Update the stream rate, channel and bps based on data
1149 * source. For more than one data source (multilink),
1150 * match the rate, bps, stream type and increment number of channels.
1151 *
1152 * If rate/bps is zero, it means the values are not set, so skip
1153 * comparison and allow the value to be set and stored in stream
1154 */
1155 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001156 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001157 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301158 return -EINVAL;
1159 }
1160
1161 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001162 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001163 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301164 return -EINVAL;
1165 }
1166
1167 stream->type = stream_config->type;
1168 stream->params.rate = stream_config->frame_rate;
1169 stream->params.bps = stream_config->bps;
1170
1171 /* TODO: Update this check during Device-device support */
1172 if (is_slave)
1173 stream->params.ch_count += stream_config->ch_count;
1174
1175 return 0;
1176}
1177
Sanyog Kalebbe73792018-04-26 18:38:13 +05301178static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001179 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301180{
1181 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1182 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001183 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301184 return -EINVAL;
1185 }
1186
1187 return 0;
1188}
1189
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001190static struct sdw_port_runtime
1191*sdw_port_alloc(struct device *dev,
1192 struct sdw_port_config *port_config,
1193 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301194{
1195 struct sdw_port_runtime *p_rt;
1196
1197 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1198 if (!p_rt)
1199 return NULL;
1200
1201 p_rt->ch_mask = port_config[port_index].ch_mask;
1202 p_rt->num = port_config[port_index].num;
1203
1204 return p_rt;
1205}
1206
1207static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001208 struct sdw_master_runtime *m_rt,
1209 struct sdw_port_config *port_config,
1210 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301211{
1212 struct sdw_port_runtime *p_rt;
1213 int i;
1214
1215 /* Iterate for number of ports to perform initialization */
1216 for (i = 0; i < num_ports; i++) {
1217 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1218 if (!p_rt)
1219 return -ENOMEM;
1220
1221 /*
1222 * TODO: Check port capabilities for requested
1223 * configuration (audio mode support)
1224 */
1225
1226 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1227 }
1228
1229 return 0;
1230}
1231
1232static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001233 struct sdw_slave_runtime *s_rt,
1234 struct sdw_port_config *port_config,
1235 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301236{
1237 struct sdw_port_runtime *p_rt;
1238 int i, ret;
1239
1240 /* Iterate for number of ports to perform initialization */
1241 for (i = 0; i < num_config; i++) {
1242 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1243 if (!p_rt)
1244 return -ENOMEM;
1245
1246 /*
1247 * TODO: Check valid port range as defined by DisCo/
1248 * slave
1249 */
1250 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1251 if (ret < 0) {
1252 kfree(p_rt);
1253 return ret;
1254 }
1255
1256 /*
1257 * TODO: Check port capabilities for requested
1258 * configuration (audio mode support)
1259 */
1260
1261 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1262 }
1263
1264 return 0;
1265}
1266
Sanyog Kale89e59052018-04-26 18:38:08 +05301267/**
1268 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1269 *
1270 * @bus: SDW Bus instance
1271 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301272 * @port_config: Port configuration for audio stream
1273 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301274 * @stream: SoundWire stream
1275 */
1276int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001277 struct sdw_stream_config *stream_config,
1278 struct sdw_port_config *port_config,
1279 unsigned int num_ports,
1280 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301281{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001282 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301283 int ret;
1284
1285 mutex_lock(&bus->bus_lock);
1286
Shreyas NCce6e74d2018-07-27 14:44:16 +05301287 /*
1288 * For multi link streams, add the second master only if
1289 * the bus supports it.
1290 * Check if bus->multi_link is set
1291 */
1292 if (!bus->multi_link && stream->m_rt_count > 0) {
1293 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001294 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301295 ret = -EINVAL;
1296 goto unlock;
1297 }
1298
Sanyog Kale89e59052018-04-26 18:38:08 +05301299 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1300 if (!m_rt) {
1301 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001302 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001303 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301304 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301305 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301306 }
1307
1308 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1309 if (ret)
1310 goto stream_error;
1311
Sanyog Kalebbe73792018-04-26 18:38:13 +05301312 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1313 if (ret)
1314 goto stream_error;
1315
Shreyas NCce6e74d2018-07-27 14:44:16 +05301316 stream->m_rt_count++;
1317
Shreyas NC3fef1a22018-07-27 14:44:09 +05301318 goto unlock;
1319
Sanyog Kale89e59052018-04-26 18:38:08 +05301320stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301321 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301322unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301323 mutex_unlock(&bus->bus_lock);
1324 return ret;
1325}
1326EXPORT_SYMBOL(sdw_stream_add_master);
1327
1328/**
1329 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1330 *
1331 * @slave: SDW Slave instance
1332 * @stream_config: Stream configuration for audio stream
1333 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301334 * @port_config: Port configuration for audio stream
1335 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301336 *
1337 * It is expected that Slave is added before adding Master
1338 * to the Stream.
1339 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301340 */
1341int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001342 struct sdw_stream_config *stream_config,
1343 struct sdw_port_config *port_config,
1344 unsigned int num_ports,
1345 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301346{
1347 struct sdw_slave_runtime *s_rt;
1348 struct sdw_master_runtime *m_rt;
1349 int ret;
1350
1351 mutex_lock(&slave->bus->bus_lock);
1352
1353 /*
1354 * If this API is invoked by Slave first then m_rt is not valid.
1355 * So, allocate m_rt and add Slave to it.
1356 */
1357 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1358 if (!m_rt) {
1359 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001360 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001361 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301362 ret = -ENOMEM;
1363 goto error;
1364 }
1365
1366 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1367 if (!s_rt) {
1368 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001369 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001370 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301371 ret = -ENOMEM;
1372 goto stream_error;
1373 }
1374
1375 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1376 if (ret)
1377 goto stream_error;
1378
1379 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1380
Sanyog Kalebbe73792018-04-26 18:38:13 +05301381 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1382 if (ret)
1383 goto stream_error;
1384
Shreyas NC0aebe402018-07-27 14:44:08 +05301385 /*
1386 * Change stream state to CONFIGURED on first Slave add.
1387 * Bus is not aware of number of Slave(s) in a stream at this
1388 * point so cannot depend on all Slave(s) to be added in order to
1389 * change stream state to CONFIGURED.
1390 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301391 stream->state = SDW_STREAM_CONFIGURED;
1392 goto error;
1393
1394stream_error:
1395 /*
1396 * we hit error so cleanup the stream, release all Slave(s) and
1397 * Master runtime
1398 */
Vinod Koul48949722018-07-27 14:44:14 +05301399 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301400error:
1401 mutex_unlock(&slave->bus->bus_lock);
1402 return ret;
1403}
1404EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301405
1406/**
1407 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1408 *
1409 * @slave: Slave handle
1410 * @direction: Data direction.
1411 * @port_num: Port number
1412 */
1413struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001414 enum sdw_data_direction direction,
1415 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301416{
1417 struct sdw_dpn_prop *dpn_prop;
1418 u8 num_ports;
1419 int i;
1420
1421 if (direction == SDW_DATA_DIR_TX) {
1422 num_ports = hweight32(slave->prop.source_ports);
1423 dpn_prop = slave->prop.src_dpn_prop;
1424 } else {
1425 num_ports = hweight32(slave->prop.sink_ports);
1426 dpn_prop = slave->prop.sink_dpn_prop;
1427 }
1428
1429 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001430 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301431 return &dpn_prop[i];
1432 }
1433
1434 return NULL;
1435}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301436
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301437/**
1438 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1439 *
1440 * @stream: SoundWire stream
1441 *
1442 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1443 * stream to reconfigure the bus.
1444 * NOTE: This function is called from SoundWire stream ops and is
1445 * expected that a global lock is held before acquiring bus_lock.
1446 */
1447static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1448{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001449 struct sdw_master_runtime *m_rt;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301450 struct sdw_bus *bus = NULL;
1451
1452 /* Iterate for all Master(s) in Master list */
1453 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1454 bus = m_rt->bus;
1455
1456 mutex_lock(&bus->bus_lock);
1457 }
1458}
1459
1460/**
1461 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1462 *
1463 * @stream: SoundWire stream
1464 *
1465 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301466 * NOTE: This function is called from SoundWire stream ops and is
1467 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301468 */
1469static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1470{
1471 struct sdw_master_runtime *m_rt = NULL;
1472 struct sdw_bus *bus = NULL;
1473
1474 /* Iterate for all Master(s) in Master list */
1475 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1476 bus = m_rt->bus;
1477 mutex_unlock(&bus->bus_lock);
1478 }
1479}
1480
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001481static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1482 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301483{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001484 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301485 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001486 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301487 struct sdw_bus_params params;
1488 int ret;
1489
Vinod Koul48949722018-07-27 14:44:14 +05301490 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1491 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1492 bus = m_rt->bus;
1493 prop = &bus->prop;
1494 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301495
Vinod Koul48949722018-07-27 14:44:14 +05301496 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001497 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001498 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301499 return -EINVAL;
1500 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301501
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001502 if (!update_params)
1503 goto program_params;
1504
Vinod Koul48949722018-07-27 14:44:14 +05301505 /* Increment cumulative bus bandwidth */
1506 /* TODO: Update this during Device-Device support */
1507 bus->params.bandwidth += m_rt->stream->params.rate *
1508 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301509
Vinod Koulc7578c12019-08-13 09:35:46 +01001510 /* Compute params */
1511 if (bus->compute_params) {
1512 ret = bus->compute_params(bus);
1513 if (ret < 0) {
1514 dev_err(bus->dev, "Compute params failed: %d",
1515 ret);
1516 return ret;
1517 }
1518 }
1519
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001520program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301521 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001522 ret = sdw_program_params(bus, true);
Vinod Koul48949722018-07-27 14:44:14 +05301523 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001524 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301525 goto restore_params;
1526 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301527 }
1528
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001529 if (!bus) {
1530 pr_err("Configuration error in %s\n", __func__);
1531 return -EINVAL;
1532 }
1533
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301534 ret = do_bank_switch(stream);
1535 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001536 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301537 goto restore_params;
1538 }
1539
Vinod Koul48949722018-07-27 14:44:14 +05301540 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1541 bus = m_rt->bus;
1542
1543 /* Prepare port(s) on the new clock configuration */
1544 ret = sdw_prep_deprep_ports(m_rt, true);
1545 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001546 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001547 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301548 return ret;
1549 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301550 }
1551
1552 stream->state = SDW_STREAM_PREPARED;
1553
1554 return ret;
1555
1556restore_params:
1557 memcpy(&bus->params, &params, sizeof(params));
1558 return ret;
1559}
1560
1561/**
1562 * sdw_prepare_stream() - Prepare SoundWire stream
1563 *
1564 * @stream: Soundwire stream
1565 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001566 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301567 */
1568int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1569{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001570 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001571 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301572
1573 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001574 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301575 return -EINVAL;
1576 }
1577
Vinod Koul48949722018-07-27 14:44:14 +05301578 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301579
Bard Liaoc32464c2020-01-14 17:52:24 -06001580 if (stream->state == SDW_STREAM_PREPARED) {
1581 ret = 0;
1582 goto state_err;
1583 }
1584
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001585 if (stream->state != SDW_STREAM_CONFIGURED &&
1586 stream->state != SDW_STREAM_DEPREPARED &&
1587 stream->state != SDW_STREAM_DISABLED) {
1588 pr_err("%s: %s: inconsistent state state %d\n",
1589 __func__, stream->name, stream->state);
1590 ret = -EINVAL;
1591 goto state_err;
1592 }
1593
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001594 /*
1595 * when the stream is DISABLED, this means sdw_prepare_stream()
1596 * is called as a result of an underflow or a resume operation.
1597 * In this case, the bus parameters shall not be recomputed, but
1598 * still need to be re-applied
1599 */
1600 if (stream->state == SDW_STREAM_DISABLED)
1601 update_params = false;
1602
1603 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301604
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001605state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301606 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301607 return ret;
1608}
1609EXPORT_SYMBOL(sdw_prepare_stream);
1610
1611static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1612{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001613 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301614 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301615 int ret;
1616
Vinod Koul48949722018-07-27 14:44:14 +05301617 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1618 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1619 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301620
Vinod Koul48949722018-07-27 14:44:14 +05301621 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001622 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301623 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001624 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301625 return ret;
1626 }
1627
1628 /* Enable port(s) */
1629 ret = sdw_enable_disable_ports(m_rt, true);
1630 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301631 dev_err(bus->dev,
1632 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301633 return ret;
1634 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301635 }
1636
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001637 if (!bus) {
1638 pr_err("Configuration error in %s\n", __func__);
1639 return -EINVAL;
1640 }
1641
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301642 ret = do_bank_switch(stream);
1643 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001644 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301645 return ret;
1646 }
1647
1648 stream->state = SDW_STREAM_ENABLED;
1649 return 0;
1650}
1651
1652/**
1653 * sdw_enable_stream() - Enable SoundWire stream
1654 *
1655 * @stream: Soundwire stream
1656 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001657 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301658 */
1659int sdw_enable_stream(struct sdw_stream_runtime *stream)
1660{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001661 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301662
1663 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001664 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301665 return -EINVAL;
1666 }
1667
Vinod Koul48949722018-07-27 14:44:14 +05301668 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301669
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001670 if (stream->state != SDW_STREAM_PREPARED &&
1671 stream->state != SDW_STREAM_DISABLED) {
1672 pr_err("%s: %s: inconsistent state state %d\n",
1673 __func__, stream->name, stream->state);
1674 ret = -EINVAL;
1675 goto state_err;
1676 }
1677
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301678 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301679
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001680state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301681 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301682 return ret;
1683}
1684EXPORT_SYMBOL(sdw_enable_stream);
1685
1686static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1687{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001688 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301689 int ret;
1690
Vinod Koul48949722018-07-27 14:44:14 +05301691 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001692 struct sdw_bus *bus = m_rt->bus;
1693
Vinod Koul48949722018-07-27 14:44:14 +05301694 /* Disable port(s) */
1695 ret = sdw_enable_disable_ports(m_rt, false);
1696 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001697 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301698 return ret;
1699 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301700 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301701 stream->state = SDW_STREAM_DISABLED;
1702
Vinod Koul48949722018-07-27 14:44:14 +05301703 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001704 struct sdw_bus *bus = m_rt->bus;
1705
Vinod Koul48949722018-07-27 14:44:14 +05301706 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001707 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301708 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001709 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301710 return ret;
1711 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301712 }
1713
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001714 ret = do_bank_switch(stream);
1715 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001716 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001717 return ret;
1718 }
1719
1720 /* make sure alternate bank (previous current) is also disabled */
1721 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001722 struct sdw_bus *bus = m_rt->bus;
1723
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001724 /* Disable port(s) */
1725 ret = sdw_enable_disable_ports(m_rt, false);
1726 if (ret < 0) {
1727 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1728 return ret;
1729 }
1730 }
1731
1732 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301733}
1734
1735/**
1736 * sdw_disable_stream() - Disable SoundWire stream
1737 *
1738 * @stream: Soundwire stream
1739 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001740 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301741 */
1742int sdw_disable_stream(struct sdw_stream_runtime *stream)
1743{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001744 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301745
1746 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001747 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301748 return -EINVAL;
1749 }
1750
Vinod Koul48949722018-07-27 14:44:14 +05301751 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301752
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001753 if (stream->state != SDW_STREAM_ENABLED) {
1754 pr_err("%s: %s: inconsistent state state %d\n",
1755 __func__, stream->name, stream->state);
1756 ret = -EINVAL;
1757 goto state_err;
1758 }
1759
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301760 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301761
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001762state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301763 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301764 return ret;
1765}
1766EXPORT_SYMBOL(sdw_disable_stream);
1767
1768static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1769{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001770 struct sdw_master_runtime *m_rt;
1771 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301772 int ret = 0;
1773
Vinod Koul48949722018-07-27 14:44:14 +05301774 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1775 bus = m_rt->bus;
1776 /* De-prepare port(s) */
1777 ret = sdw_prep_deprep_ports(m_rt, false);
1778 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301779 dev_err(bus->dev,
1780 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301781 return ret;
1782 }
1783
1784 /* TODO: Update this during Device-Device support */
1785 bus->params.bandwidth -= m_rt->stream->params.rate *
1786 m_rt->ch_count * m_rt->stream->params.bps;
1787
1788 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001789 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301790 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001791 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301792 return ret;
1793 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301794 }
1795
1796 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301797 return do_bank_switch(stream);
1798}
1799
1800/**
1801 * sdw_deprepare_stream() - Deprepare SoundWire stream
1802 *
1803 * @stream: Soundwire stream
1804 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001805 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301806 */
1807int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1808{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001809 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301810
1811 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001812 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301813 return -EINVAL;
1814 }
1815
Vinod Koul48949722018-07-27 14:44:14 +05301816 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001817
1818 if (stream->state != SDW_STREAM_PREPARED &&
1819 stream->state != SDW_STREAM_DISABLED) {
1820 pr_err("%s: %s: inconsistent state state %d\n",
1821 __func__, stream->name, stream->state);
1822 ret = -EINVAL;
1823 goto state_err;
1824 }
1825
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301826 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301827
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001828state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301829 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301830 return ret;
1831}
1832EXPORT_SYMBOL(sdw_deprepare_stream);
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001833
1834static int set_stream(struct snd_pcm_substream *substream,
1835 struct sdw_stream_runtime *sdw_stream)
1836{
1837 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1838 struct snd_soc_dai *dai;
1839 int ret = 0;
1840 int i;
1841
1842 /* Set stream pointer on all DAIs */
1843 for_each_rtd_dais(rtd, i, dai) {
1844 ret = snd_soc_dai_set_sdw_stream(dai, sdw_stream, substream->stream);
1845 if (ret < 0) {
1846 dev_err(rtd->dev, "failed to set stream pointer on dai %s", dai->name);
1847 break;
1848 }
1849 }
1850
1851 return ret;
1852}
1853
1854/**
1855 * sdw_startup_stream() - Startup SoundWire stream
1856 *
Vinod Koul3b71c692020-07-15 15:27:02 +05301857 * @sdw_substream: Soundwire stream
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001858 *
1859 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1860 */
1861int sdw_startup_stream(void *sdw_substream)
1862{
1863 struct snd_pcm_substream *substream = sdw_substream;
1864 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1865 struct sdw_stream_runtime *sdw_stream;
1866 char *name;
1867 int ret;
1868
1869 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1870 name = kasprintf(GFP_KERNEL, "%s-Playback", substream->name);
1871 else
1872 name = kasprintf(GFP_KERNEL, "%s-Capture", substream->name);
1873
1874 if (!name)
1875 return -ENOMEM;
1876
1877 sdw_stream = sdw_alloc_stream(name);
1878 if (!sdw_stream) {
1879 dev_err(rtd->dev, "alloc stream failed for substream DAI %s", substream->name);
1880 ret = -ENOMEM;
1881 goto error;
1882 }
1883
1884 ret = set_stream(substream, sdw_stream);
1885 if (ret < 0)
1886 goto release_stream;
1887 return 0;
1888
1889release_stream:
1890 sdw_release_stream(sdw_stream);
1891 set_stream(substream, NULL);
1892error:
1893 kfree(name);
1894 return ret;
1895}
1896EXPORT_SYMBOL(sdw_startup_stream);
1897
1898/**
1899 * sdw_shutdown_stream() - Shutdown SoundWire stream
1900 *
Vinod Koul3b71c692020-07-15 15:27:02 +05301901 * @sdw_substream: Soundwire stream
Pierre-Louis Bossart45505692020-07-01 02:43:53 +08001902 *
1903 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1904 */
1905void sdw_shutdown_stream(void *sdw_substream)
1906{
1907 struct snd_pcm_substream *substream = sdw_substream;
1908 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1909 struct sdw_stream_runtime *sdw_stream;
1910 struct snd_soc_dai *dai;
1911
1912 /* Find stream from first CPU DAI */
1913 dai = asoc_rtd_to_cpu(rtd, 0);
1914
1915 sdw_stream = snd_soc_dai_get_sdw_stream(dai, substream->stream);
1916
1917 if (!sdw_stream) {
1918 dev_err(rtd->dev, "no stream found for DAI %s", dai->name);
1919 return;
1920 }
1921
1922 /* release memory */
1923 kfree(sdw_stream->name);
1924 sdw_release_stream(sdw_stream);
1925
1926 /* clear DAI data */
1927 set_stream(substream, NULL);
1928}
1929EXPORT_SYMBOL(sdw_shutdown_stream);