blob: da10f38298c068da9bf9271e7b6e3ec648594e61 [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050024int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053025 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050028int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053029
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050030int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053031{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050035 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053036 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050042EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053043
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050044int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053045{
46 int i;
47
48 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050049 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053050 return i;
51 }
52
53 pr_warn("Requested row not found, selecting lowest row no: 48\n");
54 return 0;
55}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050056EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053057
Sanyog Kalef8101c72018-04-26 18:38:17 +053058static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050059 struct sdw_slave *slave,
60 struct sdw_transport_params *t_params,
61 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053062{
63 u32 addr1, addr2, addr3, addr4;
64 int ret;
65 u16 wbuf;
66
67 if (bus->params.next_bank) {
68 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
69 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
70 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
71 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
72 } else {
73 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
74 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
75 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
76 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
77 }
78
79 /* Program DPN_OffsetCtrl2 registers */
80 ret = sdw_write(slave, addr1, t_params->offset2);
81 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050082 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053083 return ret;
84 }
85
86 /* Program DPN_BlockCtrl3 register */
87 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
88 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050089 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053090 return ret;
91 }
92
93 /*
94 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053095 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053096 * handled, so bail out if we are not FULL data port type
97 */
98 if (type != SDW_DPN_FULL)
99 return ret;
100
101 /* Program DPN_SampleCtrl2 register */
102 wbuf = (t_params->sample_interval - 1);
103 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
104 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
105
106 ret = sdw_write(slave, addr3, wbuf);
107 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500108 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530109 return ret;
110 }
111
112 /* Program DPN_HCtrl register */
113 wbuf = t_params->hstart;
114 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
115 wbuf |= t_params->hstop;
116
117 ret = sdw_write(slave, addr4, wbuf);
118 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500119 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530120
121 return ret;
122}
123
124static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500125 struct sdw_slave_runtime *s_rt,
126 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530127{
128 struct sdw_transport_params *t_params = &p_rt->transport_params;
129 struct sdw_port_params *p_params = &p_rt->port_params;
130 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
131 u32 addr1, addr2, addr3, addr4, addr5, addr6;
132 struct sdw_dpn_prop *dpn_prop;
133 int ret;
134 u8 wbuf;
135
136 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500137 s_rt->direction,
138 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530139 if (!dpn_prop)
140 return -EINVAL;
141
142 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
143 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
144
145 if (bus->params.next_bank) {
146 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
147 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
148 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
149 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
150
151 } else {
152 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
153 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
154 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
155 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
156 }
157
158 /* Program DPN_PortCtrl register */
159 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
160 wbuf |= p_params->flow_mode;
161
162 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
163 if (ret < 0) {
164 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500165 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530166 t_params->port_num);
167 return ret;
168 }
169
170 /* Program DPN_BlockCtrl1 register */
171 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
172 if (ret < 0) {
173 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500174 "DPN_BlockCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530175 t_params->port_num);
176 return ret;
177 }
178
179 /* Program DPN_SampleCtrl1 register */
180 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
181 ret = sdw_write(s_rt->slave, addr3, wbuf);
182 if (ret < 0) {
183 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500184 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530185 t_params->port_num);
186 return ret;
187 }
188
189 /* Program DPN_OffsetCtrl1 registers */
190 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
191 if (ret < 0) {
192 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500193 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530194 t_params->port_num);
195 return ret;
196 }
197
198 /* Program DPN_BlockCtrl2 register*/
199 if (t_params->blk_grp_ctrl_valid) {
200 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
201 if (ret < 0) {
202 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500203 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530204 t_params->port_num);
205 return ret;
206 }
207 }
208
209 /* program DPN_LaneCtrl register */
210 if (slave_prop->lane_control_support) {
211 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
212 if (ret < 0) {
213 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500214 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530215 t_params->port_num);
216 return ret;
217 }
218 }
219
220 if (dpn_prop->type != SDW_DPN_SIMPLE) {
221 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500222 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530223 if (ret < 0)
224 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500225 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530226 t_params->port_num);
227 }
228
229 return ret;
230}
231
232static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500233 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530234{
235 int ret;
236
237 /*
238 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530239 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530240 * hstart/stop etc of the data. Port parameters refers to word
241 * length, flow mode etc of the port
242 */
243 ret = bus->port_ops->dpn_set_port_transport_params(bus,
244 &p_rt->transport_params,
245 bus->params.next_bank);
246 if (ret < 0)
247 return ret;
248
249 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500250 &p_rt->port_params,
251 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530252}
253
254/**
255 * sdw_program_port_params() - Programs transport parameters of Master(s)
256 * and Slave(s)
257 *
258 * @m_rt: Master stream runtime
259 */
260static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
261{
262 struct sdw_slave_runtime *s_rt = NULL;
263 struct sdw_bus *bus = m_rt->bus;
264 struct sdw_port_runtime *p_rt;
265 int ret = 0;
266
267 /* Program transport & port parameters for Slave(s) */
268 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
269 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
270 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
271 if (ret < 0)
272 return ret;
273 }
274 }
275
276 /* Program transport & port parameters for Master(s) */
277 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
278 ret = sdw_program_master_port_params(bus, p_rt);
279 if (ret < 0)
280 return ret;
281 }
282
283 return 0;
284}
285
Sanyog Kale89e59052018-04-26 18:38:08 +0530286/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530287 * sdw_enable_disable_slave_ports: Enable/disable slave data port
288 *
289 * @bus: bus instance
290 * @s_rt: slave runtime
291 * @p_rt: port runtime
292 * @en: enable or disable operation
293 *
294 * This function only sets the enable/disable bits in the relevant bank, the
295 * actual enable/disable is done with a bank switch
296 */
297static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500298 struct sdw_slave_runtime *s_rt,
299 struct sdw_port_runtime *p_rt,
300 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530301{
302 struct sdw_transport_params *t_params = &p_rt->transport_params;
303 u32 addr;
304 int ret;
305
306 if (bus->params.next_bank)
307 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
308 else
309 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
310
311 /*
312 * Since bus doesn't support sharing a port across two streams,
313 * it is safe to reset this register
314 */
315 if (en)
316 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
317 else
318 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
319
320 if (ret < 0)
321 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500322 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530323 ret, t_params->port_num);
324
325 return ret;
326}
327
328static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500329 struct sdw_port_runtime *p_rt,
330 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530331{
332 struct sdw_transport_params *t_params = &p_rt->transport_params;
333 struct sdw_bus *bus = m_rt->bus;
334 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500335 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530336
337 enable_ch.port_num = p_rt->num;
338 enable_ch.ch_mask = p_rt->ch_mask;
339 enable_ch.enable = en;
340
341 /* Perform Master port channel(s) enable/disable */
342 if (bus->port_ops->dpn_port_enable_ch) {
343 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500344 &enable_ch,
345 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530346 if (ret < 0) {
347 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500348 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530349 ret, t_params->port_num);
350 return ret;
351 }
352 } else {
353 dev_err(bus->dev,
354 "dpn_port_enable_ch not supported, %s failed\n",
355 en ? "enable" : "disable");
356 return -EINVAL;
357 }
358
359 return 0;
360}
361
362/**
363 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
364 * Slave(s)
365 *
366 * @m_rt: Master stream runtime
367 * @en: mode (enable/disable)
368 */
369static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
370{
371 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500372 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530373 int ret = 0;
374
375 /* Enable/Disable Slave port(s) */
376 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
377 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
378 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500379 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530380 if (ret < 0)
381 return ret;
382 }
383 }
384
385 /* Enable/Disable Master port(s) */
386 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
387 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
388 if (ret < 0)
389 return ret;
390 }
391
392 return 0;
393}
394
395static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500396 struct sdw_prepare_ch prep_ch,
397 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530398{
399 const struct sdw_slave_ops *ops = s_rt->slave->ops;
400 int ret;
401
402 if (ops->port_prep) {
403 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
404 if (ret < 0) {
405 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530406 "Slave Port Prep cmd %d failed: %d\n",
407 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530408 return ret;
409 }
410 }
411
412 return 0;
413}
414
415static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500416 struct sdw_slave_runtime *s_rt,
417 struct sdw_port_runtime *p_rt,
418 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530419{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500420 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530421 struct sdw_dpn_prop *dpn_prop;
422 struct sdw_prepare_ch prep_ch;
423 unsigned int time_left;
424 bool intr = false;
425 int ret = 0, val;
426 u32 addr;
427
428 prep_ch.num = p_rt->num;
429 prep_ch.ch_mask = p_rt->ch_mask;
430
431 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500432 s_rt->direction,
433 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530434 if (!dpn_prop) {
435 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500436 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530437 return -EINVAL;
438 }
439
440 prep_ch.prepare = prep;
441
442 prep_ch.bank = bus->params.next_bank;
443
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500444 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530445 intr = true;
446
447 /*
448 * Enable interrupt before Port prepare.
449 * For Port de-prepare, it is assumed that port
450 * was prepared earlier
451 */
452 if (prep && intr) {
453 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500454 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530455 if (ret < 0)
456 return ret;
457 }
458
459 /* Inform slave about the impending port prepare */
460 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
461
462 /* Prepare Slave port implementing CP_SM */
463 if (!dpn_prop->simple_ch_prep_sm) {
464 addr = SDW_DPN_PREPARECTRL(p_rt->num);
465
466 if (prep)
467 ret = sdw_update(s_rt->slave, addr,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500468 0xFF, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530469 else
470 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
471
472 if (ret < 0) {
473 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500474 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530475 return ret;
476 }
477
478 /* Wait for completion on port ready */
479 port_ready = &s_rt->slave->port_ready[prep_ch.num];
480 time_left = wait_for_completion_timeout(port_ready,
481 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
482
483 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
484 val &= p_rt->ch_mask;
485 if (!time_left || val) {
486 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500487 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530488 return -ETIMEDOUT;
489 }
490 }
491
492 /* Inform slaves about ports prepared */
493 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
494
495 /* Disable interrupt after Port de-prepare */
496 if (!prep && intr)
497 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500498 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530499
500 return ret;
501}
502
503static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500504 struct sdw_port_runtime *p_rt,
505 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530506{
507 struct sdw_transport_params *t_params = &p_rt->transport_params;
508 struct sdw_bus *bus = m_rt->bus;
509 const struct sdw_master_port_ops *ops = bus->port_ops;
510 struct sdw_prepare_ch prep_ch;
511 int ret = 0;
512
513 prep_ch.num = p_rt->num;
514 prep_ch.ch_mask = p_rt->ch_mask;
515 prep_ch.prepare = prep; /* Prepare/De-prepare */
516 prep_ch.bank = bus->params.next_bank;
517
518 /* Pre-prepare/Pre-deprepare port(s) */
519 if (ops->dpn_port_prep) {
520 ret = ops->dpn_port_prep(bus, &prep_ch);
521 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500522 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500523 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530524 return ret;
525 }
526 }
527
528 return ret;
529}
530
531/**
532 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
533 * Slave(s)
534 *
535 * @m_rt: Master runtime handle
536 * @prep: Prepare or De-prepare
537 */
538static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
539{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500540 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530541 struct sdw_port_runtime *p_rt;
542 int ret = 0;
543
544 /* Prepare/De-prepare Slave port(s) */
545 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
546 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
547 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500548 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530549 if (ret < 0)
550 return ret;
551 }
552 }
553
554 /* Prepare/De-prepare Master port(s) */
555 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
556 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
557 if (ret < 0)
558 return ret;
559 }
560
561 return ret;
562}
563
564/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530565 * sdw_notify_config() - Notify bus configuration
566 *
567 * @m_rt: Master runtime handle
568 *
569 * This function notifies the Master(s) and Slave(s) of the
570 * new bus configuration.
571 */
572static int sdw_notify_config(struct sdw_master_runtime *m_rt)
573{
574 struct sdw_slave_runtime *s_rt;
575 struct sdw_bus *bus = m_rt->bus;
576 struct sdw_slave *slave;
577 int ret = 0;
578
579 if (bus->ops->set_bus_conf) {
580 ret = bus->ops->set_bus_conf(bus, &bus->params);
581 if (ret < 0)
582 return ret;
583 }
584
585 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
586 slave = s_rt->slave;
587
588 if (slave->ops->bus_config) {
589 ret = slave->ops->bus_config(slave, &bus->params);
Rander Wang60835022020-01-14 17:52:26 -0600590 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500591 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500592 slave->dev_num);
Rander Wang60835022020-01-14 17:52:26 -0600593 return ret;
594 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530595 }
596 }
597
598 return ret;
599}
600
601/**
602 * sdw_program_params() - Program transport and port parameters for Master(s)
603 * and Slave(s)
604 *
605 * @bus: SDW bus instance
606 */
607static int sdw_program_params(struct sdw_bus *bus)
608{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500609 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530610 int ret = 0;
611
612 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
613 ret = sdw_program_port_params(m_rt);
614 if (ret < 0) {
615 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500616 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530617 return ret;
618 }
619
620 ret = sdw_notify_config(m_rt);
621 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530622 dev_err(bus->dev,
623 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530624 return ret;
625 }
626
627 /* Enable port(s) on alternate bank for all active streams */
628 if (m_rt->stream->state != SDW_STREAM_ENABLED)
629 continue;
630
631 ret = sdw_enable_disable_ports(m_rt, true);
632 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500633 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530634 return ret;
635 }
636 }
637
638 return ret;
639}
640
Shreyas NCce6e74d2018-07-27 14:44:16 +0530641static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530642{
643 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530644 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530645 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500646 u8 *wbuf;
647 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530648 u16 addr;
649
650 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
651 if (!wr_msg)
652 return -ENOMEM;
653
Shreyas NCce6e74d2018-07-27 14:44:16 +0530654 bus->defer_msg.msg = wr_msg;
655
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530656 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
657 if (!wbuf) {
658 ret = -ENOMEM;
659 goto error_1;
660 }
661
662 /* Get row and column index to program register */
663 col_index = sdw_find_col_index(bus->params.col);
664 row_index = sdw_find_row_index(bus->params.row);
665 wbuf[0] = col_index | (row_index << 3);
666
667 if (bus->params.next_bank)
668 addr = SDW_SCP_FRAMECTRL_B1;
669 else
670 addr = SDW_SCP_FRAMECTRL_B0;
671
672 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500673 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530674 wr_msg->ssp_sync = true;
675
Shreyas NCce6e74d2018-07-27 14:44:16 +0530676 /*
677 * Set the multi_link flag only when both the hardware supports
678 * and there is a stream handled by multiple masters
679 */
680 multi_link = bus->multi_link && (m_rt_count > 1);
681
682 if (multi_link)
683 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
684 else
685 ret = sdw_transfer(bus, wr_msg);
686
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530687 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500688 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530689 goto error;
690 }
691
Shreyas NCce6e74d2018-07-27 14:44:16 +0530692 if (!multi_link) {
693 kfree(wr_msg);
694 kfree(wbuf);
695 bus->defer_msg.msg = NULL;
696 bus->params.curr_bank = !bus->params.curr_bank;
697 bus->params.next_bank = !bus->params.next_bank;
698 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530699
700 return 0;
701
702error:
703 kfree(wbuf);
704error_1:
705 kfree(wr_msg);
706 return ret;
707}
708
Shreyas NCce6e74d2018-07-27 14:44:16 +0530709/**
710 * sdw_ml_sync_bank_switch: Multilink register bank switch
711 *
712 * @bus: SDW bus instance
713 *
714 * Caller function should free the buffers on error
715 */
716static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
717{
718 unsigned long time_left;
719
720 if (!bus->multi_link)
721 return 0;
722
723 /* Wait for completion of transfer */
724 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
725 bus->bank_switch_timeout);
726
727 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500728 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530729 return -ETIMEDOUT;
730 }
731
732 bus->params.curr_bank = !bus->params.curr_bank;
733 bus->params.next_bank = !bus->params.next_bank;
734
735 if (bus->defer_msg.msg) {
736 kfree(bus->defer_msg.msg->buf);
737 kfree(bus->defer_msg.msg);
738 }
739
740 return 0;
741}
742
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530743static int do_bank_switch(struct sdw_stream_runtime *stream)
744{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500745 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530746 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500747 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530748 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530749 int ret = 0;
750
Vinod Koul48949722018-07-27 14:44:14 +0530751 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
752 bus = m_rt->bus;
753 ops = bus->ops;
754
Shreyas NCce6e74d2018-07-27 14:44:16 +0530755 if (bus->multi_link) {
756 multi_link = true;
757 mutex_lock(&bus->msg_lock);
758 }
759
Vinod Koul48949722018-07-27 14:44:14 +0530760 /* Pre-bank switch */
761 if (ops->pre_bank_switch) {
762 ret = ops->pre_bank_switch(bus);
763 if (ret < 0) {
764 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500765 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530766 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530767 }
768 }
769
Shreyas NCce6e74d2018-07-27 14:44:16 +0530770 /*
771 * Perform Bank switch operation.
772 * For multi link cases, the actual bank switch is
773 * synchronized across all Masters and happens later as a
774 * part of post_bank_switch ops.
775 */
776 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530777 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500778 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530779 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530780 }
781 }
782
Shreyas NCce6e74d2018-07-27 14:44:16 +0530783 /*
784 * For multi link cases, it is expected that the bank switch is
785 * triggered by the post_bank_switch for the first Master in the list
786 * and for the other Masters the post_bank_switch() should return doing
787 * nothing.
788 */
Vinod Koul48949722018-07-27 14:44:14 +0530789 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
790 bus = m_rt->bus;
791 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530792
Vinod Koul48949722018-07-27 14:44:14 +0530793 /* Post-bank switch */
794 if (ops->post_bank_switch) {
795 ret = ops->post_bank_switch(bus);
796 if (ret < 0) {
797 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530798 "Post bank switch op failed: %d\n",
799 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530800 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530801 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530802 } else if (bus->multi_link && stream->m_rt_count > 1) {
803 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500804 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530805 goto error;
806 }
807
808 /* Set the bank switch timeout to default, if not set */
809 if (!bus->bank_switch_timeout)
810 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
811
812 /* Check if bank switch was successful */
813 ret = sdw_ml_sync_bank_switch(bus);
814 if (ret < 0) {
815 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500816 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530817 goto error;
818 }
819
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100820 if (bus->multi_link)
821 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530822 }
823
824 return ret;
825
826error:
827 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530828 bus = m_rt->bus;
829
830 kfree(bus->defer_msg.msg->buf);
831 kfree(bus->defer_msg.msg);
832 }
833
834msg_unlock:
835
836 if (multi_link) {
837 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
838 bus = m_rt->bus;
839 if (mutex_is_locked(&bus->msg_lock))
840 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530841 }
842 }
843
844 return ret;
845}
846
847/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530848 * sdw_release_stream() - Free the assigned stream runtime
849 *
850 * @stream: SoundWire stream runtime
851 *
852 * sdw_release_stream should be called only once per stream
853 */
854void sdw_release_stream(struct sdw_stream_runtime *stream)
855{
856 kfree(stream);
857}
858EXPORT_SYMBOL(sdw_release_stream);
859
860/**
861 * sdw_alloc_stream() - Allocate and return stream runtime
862 *
863 * @stream_name: SoundWire stream name
864 *
865 * Allocates a SoundWire stream runtime instance.
866 * sdw_alloc_stream should be called only once per stream. Typically
867 * invoked from ALSA/ASoC machine/platform driver.
868 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100869struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530870{
871 struct sdw_stream_runtime *stream;
872
873 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
874 if (!stream)
875 return NULL;
876
877 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530878 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530879 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530880 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530881
882 return stream;
883}
884EXPORT_SYMBOL(sdw_alloc_stream);
885
Vinod Koul48949722018-07-27 14:44:14 +0530886static struct sdw_master_runtime
887*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500888 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530889{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500890 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530891
892 /* Retrieve Bus handle if already available */
893 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
894 if (m_rt->bus == bus)
895 return m_rt;
896 }
897
898 return NULL;
899}
900
Sanyog Kale89e59052018-04-26 18:38:08 +0530901/**
902 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
903 *
904 * @bus: SDW bus instance
905 * @stream_config: Stream configuration
906 * @stream: Stream runtime handle.
907 *
908 * This function is to be called with bus_lock held.
909 */
910static struct sdw_master_runtime
911*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500912 struct sdw_stream_config *stream_config,
913 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530914{
915 struct sdw_master_runtime *m_rt;
916
Sanyog Kale89e59052018-04-26 18:38:08 +0530917 /*
918 * check if Master is already allocated (as a result of Slave adding
919 * it first), if so skip allocation and go to configure
920 */
Vinod Koul48949722018-07-27 14:44:14 +0530921 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530922 if (m_rt)
923 goto stream_config;
924
925 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
926 if (!m_rt)
927 return NULL;
928
929 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530930 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530931 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530932 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530933
934 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
935
936stream_config:
937 m_rt->ch_count = stream_config->ch_count;
938 m_rt->bus = bus;
939 m_rt->stream = stream;
940 m_rt->direction = stream_config->direction;
941
942 return m_rt;
943}
944
945/**
946 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
947 *
948 * @slave: Slave handle
949 * @stream_config: Stream configuration
950 * @stream: Stream runtime handle
951 *
952 * This function is to be called with bus_lock held.
953 */
954static struct sdw_slave_runtime
955*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500956 struct sdw_stream_config *stream_config,
957 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530958{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500959 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530960
961 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
962 if (!s_rt)
963 return NULL;
964
Sanyog Kalebbe73792018-04-26 18:38:13 +0530965 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530966 s_rt->ch_count = stream_config->ch_count;
967 s_rt->direction = stream_config->direction;
968 s_rt->slave = slave;
969
970 return s_rt;
971}
972
Sanyog Kalebbe73792018-04-26 18:38:13 +0530973static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500974 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530975{
976 struct sdw_port_runtime *p_rt, *_p_rt;
977
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500978 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530979 list_del(&p_rt->port_node);
980 kfree(p_rt);
981 }
982}
983
984static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500985 struct sdw_slave *slave,
986 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530987{
988 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530989 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +0530990 struct sdw_slave_runtime *s_rt;
991
Vinod Koul48949722018-07-27 14:44:14 +0530992 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
993 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530994 if (s_rt->slave != slave)
995 continue;
996
997 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500998 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530999 list_del(&p_rt->port_node);
1000 kfree(p_rt);
1001 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301002 }
1003 }
1004}
1005
Sanyog Kale89e59052018-04-26 18:38:08 +05301006/**
1007 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1008 *
1009 * @slave: Slave handle.
1010 * @stream: Stream runtime handle.
1011 *
1012 * This function is to be called with bus_lock held.
1013 */
1014static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001015 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301016{
1017 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301018 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301019
Vinod Koul48949722018-07-27 14:44:14 +05301020 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1021 /* Retrieve Slave runtime handle */
1022 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001023 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301024 if (s_rt->slave == slave) {
1025 list_del(&s_rt->m_rt_node);
1026 kfree(s_rt);
1027 return;
1028 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301029 }
1030 }
1031}
1032
1033/**
1034 * sdw_release_master_stream() - Free Master runtime handle
1035 *
Vinod Koul48949722018-07-27 14:44:14 +05301036 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301037 * @stream: Stream runtime handle.
1038 *
1039 * This function is to be called with bus_lock held
1040 * It frees the Master runtime handle and associated Slave(s) runtime
1041 * handle. If this is called first then sdw_release_slave_stream() will have
1042 * no effect as Slave(s) runtime handle would already be freed up.
1043 */
Vinod Koul48949722018-07-27 14:44:14 +05301044static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001045 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301046{
Sanyog Kale89e59052018-04-26 18:38:08 +05301047 struct sdw_slave_runtime *s_rt, *_s_rt;
1048
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301049 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1050 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1051 sdw_release_slave_stream(s_rt->slave, stream);
1052 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301053
Vinod Koul48949722018-07-27 14:44:14 +05301054 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301055 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301056 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301057}
1058
1059/**
1060 * sdw_stream_remove_master() - Remove master from sdw_stream
1061 *
1062 * @bus: SDW Bus instance
1063 * @stream: SoundWire stream
1064 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301065 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301066 */
1067int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001068 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301069{
Vinod Koul48949722018-07-27 14:44:14 +05301070 struct sdw_master_runtime *m_rt, *_m_rt;
1071
Sanyog Kale89e59052018-04-26 18:38:08 +05301072 mutex_lock(&bus->bus_lock);
1073
Vinod Koul48949722018-07-27 14:44:14 +05301074 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001075 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301076 if (m_rt->bus != bus)
1077 continue;
1078
1079 sdw_master_port_release(bus, m_rt);
1080 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301081 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301082 }
1083
1084 if (list_empty(&stream->master_list))
1085 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301086
1087 mutex_unlock(&bus->bus_lock);
1088
1089 return 0;
1090}
1091EXPORT_SYMBOL(sdw_stream_remove_master);
1092
1093/**
1094 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1095 *
1096 * @slave: SDW Slave instance
1097 * @stream: SoundWire stream
1098 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301099 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301100 */
1101int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001102 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301103{
1104 mutex_lock(&slave->bus->bus_lock);
1105
Sanyog Kalebbe73792018-04-26 18:38:13 +05301106 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301107 sdw_release_slave_stream(slave, stream);
1108
1109 mutex_unlock(&slave->bus->bus_lock);
1110
1111 return 0;
1112}
1113EXPORT_SYMBOL(sdw_stream_remove_slave);
1114
1115/**
1116 * sdw_config_stream() - Configure the allocated stream
1117 *
1118 * @dev: SDW device
1119 * @stream: SoundWire stream
1120 * @stream_config: Stream configuration for audio stream
1121 * @is_slave: is API called from Slave or Master
1122 *
1123 * This function is to be called with bus_lock held.
1124 */
1125static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001126 struct sdw_stream_runtime *stream,
1127 struct sdw_stream_config *stream_config,
1128 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301129{
1130 /*
1131 * Update the stream rate, channel and bps based on data
1132 * source. For more than one data source (multilink),
1133 * match the rate, bps, stream type and increment number of channels.
1134 *
1135 * If rate/bps is zero, it means the values are not set, so skip
1136 * comparison and allow the value to be set and stored in stream
1137 */
1138 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001139 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001140 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301141 return -EINVAL;
1142 }
1143
1144 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001145 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001146 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301147 return -EINVAL;
1148 }
1149
1150 stream->type = stream_config->type;
1151 stream->params.rate = stream_config->frame_rate;
1152 stream->params.bps = stream_config->bps;
1153
1154 /* TODO: Update this check during Device-device support */
1155 if (is_slave)
1156 stream->params.ch_count += stream_config->ch_count;
1157
1158 return 0;
1159}
1160
Sanyog Kalebbe73792018-04-26 18:38:13 +05301161static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001162 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301163{
1164 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1165 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001166 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301167 return -EINVAL;
1168 }
1169
1170 return 0;
1171}
1172
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001173static struct sdw_port_runtime
1174*sdw_port_alloc(struct device *dev,
1175 struct sdw_port_config *port_config,
1176 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301177{
1178 struct sdw_port_runtime *p_rt;
1179
1180 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1181 if (!p_rt)
1182 return NULL;
1183
1184 p_rt->ch_mask = port_config[port_index].ch_mask;
1185 p_rt->num = port_config[port_index].num;
1186
1187 return p_rt;
1188}
1189
1190static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001191 struct sdw_master_runtime *m_rt,
1192 struct sdw_port_config *port_config,
1193 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301194{
1195 struct sdw_port_runtime *p_rt;
1196 int i;
1197
1198 /* Iterate for number of ports to perform initialization */
1199 for (i = 0; i < num_ports; i++) {
1200 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1201 if (!p_rt)
1202 return -ENOMEM;
1203
1204 /*
1205 * TODO: Check port capabilities for requested
1206 * configuration (audio mode support)
1207 */
1208
1209 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1210 }
1211
1212 return 0;
1213}
1214
1215static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001216 struct sdw_slave_runtime *s_rt,
1217 struct sdw_port_config *port_config,
1218 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301219{
1220 struct sdw_port_runtime *p_rt;
1221 int i, ret;
1222
1223 /* Iterate for number of ports to perform initialization */
1224 for (i = 0; i < num_config; i++) {
1225 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1226 if (!p_rt)
1227 return -ENOMEM;
1228
1229 /*
1230 * TODO: Check valid port range as defined by DisCo/
1231 * slave
1232 */
1233 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1234 if (ret < 0) {
1235 kfree(p_rt);
1236 return ret;
1237 }
1238
1239 /*
1240 * TODO: Check port capabilities for requested
1241 * configuration (audio mode support)
1242 */
1243
1244 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1245 }
1246
1247 return 0;
1248}
1249
Sanyog Kale89e59052018-04-26 18:38:08 +05301250/**
1251 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1252 *
1253 * @bus: SDW Bus instance
1254 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301255 * @port_config: Port configuration for audio stream
1256 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301257 * @stream: SoundWire stream
1258 */
1259int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001260 struct sdw_stream_config *stream_config,
1261 struct sdw_port_config *port_config,
1262 unsigned int num_ports,
1263 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301264{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001265 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301266 int ret;
1267
1268 mutex_lock(&bus->bus_lock);
1269
Shreyas NCce6e74d2018-07-27 14:44:16 +05301270 /*
1271 * For multi link streams, add the second master only if
1272 * the bus supports it.
1273 * Check if bus->multi_link is set
1274 */
1275 if (!bus->multi_link && stream->m_rt_count > 0) {
1276 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001277 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301278 ret = -EINVAL;
1279 goto unlock;
1280 }
1281
Sanyog Kale89e59052018-04-26 18:38:08 +05301282 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1283 if (!m_rt) {
1284 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001285 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001286 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301287 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301288 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301289 }
1290
1291 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1292 if (ret)
1293 goto stream_error;
1294
Sanyog Kalebbe73792018-04-26 18:38:13 +05301295 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1296 if (ret)
1297 goto stream_error;
1298
Shreyas NCce6e74d2018-07-27 14:44:16 +05301299 stream->m_rt_count++;
1300
Shreyas NC3fef1a22018-07-27 14:44:09 +05301301 goto unlock;
1302
Sanyog Kale89e59052018-04-26 18:38:08 +05301303stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301304 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301305unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301306 mutex_unlock(&bus->bus_lock);
1307 return ret;
1308}
1309EXPORT_SYMBOL(sdw_stream_add_master);
1310
1311/**
1312 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1313 *
1314 * @slave: SDW Slave instance
1315 * @stream_config: Stream configuration for audio stream
1316 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301317 * @port_config: Port configuration for audio stream
1318 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301319 *
1320 * It is expected that Slave is added before adding Master
1321 * to the Stream.
1322 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301323 */
1324int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001325 struct sdw_stream_config *stream_config,
1326 struct sdw_port_config *port_config,
1327 unsigned int num_ports,
1328 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301329{
1330 struct sdw_slave_runtime *s_rt;
1331 struct sdw_master_runtime *m_rt;
1332 int ret;
1333
1334 mutex_lock(&slave->bus->bus_lock);
1335
1336 /*
1337 * If this API is invoked by Slave first then m_rt is not valid.
1338 * So, allocate m_rt and add Slave to it.
1339 */
1340 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1341 if (!m_rt) {
1342 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001343 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001344 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301345 ret = -ENOMEM;
1346 goto error;
1347 }
1348
1349 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1350 if (!s_rt) {
1351 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001352 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001353 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301354 ret = -ENOMEM;
1355 goto stream_error;
1356 }
1357
1358 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1359 if (ret)
1360 goto stream_error;
1361
1362 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1363
Sanyog Kalebbe73792018-04-26 18:38:13 +05301364 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1365 if (ret)
1366 goto stream_error;
1367
Shreyas NC0aebe402018-07-27 14:44:08 +05301368 /*
1369 * Change stream state to CONFIGURED on first Slave add.
1370 * Bus is not aware of number of Slave(s) in a stream at this
1371 * point so cannot depend on all Slave(s) to be added in order to
1372 * change stream state to CONFIGURED.
1373 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301374 stream->state = SDW_STREAM_CONFIGURED;
1375 goto error;
1376
1377stream_error:
1378 /*
1379 * we hit error so cleanup the stream, release all Slave(s) and
1380 * Master runtime
1381 */
Vinod Koul48949722018-07-27 14:44:14 +05301382 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301383error:
1384 mutex_unlock(&slave->bus->bus_lock);
1385 return ret;
1386}
1387EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301388
1389/**
1390 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1391 *
1392 * @slave: Slave handle
1393 * @direction: Data direction.
1394 * @port_num: Port number
1395 */
1396struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001397 enum sdw_data_direction direction,
1398 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301399{
1400 struct sdw_dpn_prop *dpn_prop;
1401 u8 num_ports;
1402 int i;
1403
1404 if (direction == SDW_DATA_DIR_TX) {
1405 num_ports = hweight32(slave->prop.source_ports);
1406 dpn_prop = slave->prop.src_dpn_prop;
1407 } else {
1408 num_ports = hweight32(slave->prop.sink_ports);
1409 dpn_prop = slave->prop.sink_dpn_prop;
1410 }
1411
1412 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001413 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301414 return &dpn_prop[i];
1415 }
1416
1417 return NULL;
1418}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301419
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301420/**
1421 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1422 *
1423 * @stream: SoundWire stream
1424 *
1425 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1426 * stream to reconfigure the bus.
1427 * NOTE: This function is called from SoundWire stream ops and is
1428 * expected that a global lock is held before acquiring bus_lock.
1429 */
1430static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1431{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001432 struct sdw_master_runtime *m_rt;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301433 struct sdw_bus *bus = NULL;
1434
1435 /* Iterate for all Master(s) in Master list */
1436 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1437 bus = m_rt->bus;
1438
1439 mutex_lock(&bus->bus_lock);
1440 }
1441}
1442
1443/**
1444 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1445 *
1446 * @stream: SoundWire stream
1447 *
1448 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301449 * NOTE: This function is called from SoundWire stream ops and is
1450 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301451 */
1452static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1453{
1454 struct sdw_master_runtime *m_rt = NULL;
1455 struct sdw_bus *bus = NULL;
1456
1457 /* Iterate for all Master(s) in Master list */
1458 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1459 bus = m_rt->bus;
1460 mutex_unlock(&bus->bus_lock);
1461 }
1462}
1463
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001464static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1465 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301466{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001467 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301468 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001469 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301470 struct sdw_bus_params params;
1471 int ret;
1472
Vinod Koul48949722018-07-27 14:44:14 +05301473 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1474 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1475 bus = m_rt->bus;
1476 prop = &bus->prop;
1477 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301478
Vinod Koul48949722018-07-27 14:44:14 +05301479 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001480 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001481 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301482 return -EINVAL;
1483 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301484
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001485 if (!update_params)
1486 goto program_params;
1487
Vinod Koul48949722018-07-27 14:44:14 +05301488 /* Increment cumulative bus bandwidth */
1489 /* TODO: Update this during Device-Device support */
1490 bus->params.bandwidth += m_rt->stream->params.rate *
1491 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301492
Vinod Koulc7578c12019-08-13 09:35:46 +01001493 /* Compute params */
1494 if (bus->compute_params) {
1495 ret = bus->compute_params(bus);
1496 if (ret < 0) {
1497 dev_err(bus->dev, "Compute params failed: %d",
1498 ret);
1499 return ret;
1500 }
1501 }
1502
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001503program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301504 /* Program params */
1505 ret = sdw_program_params(bus);
1506 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001507 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301508 goto restore_params;
1509 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301510 }
1511
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001512 if (!bus) {
1513 pr_err("Configuration error in %s\n", __func__);
1514 return -EINVAL;
1515 }
1516
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301517 ret = do_bank_switch(stream);
1518 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001519 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301520 goto restore_params;
1521 }
1522
Vinod Koul48949722018-07-27 14:44:14 +05301523 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1524 bus = m_rt->bus;
1525
1526 /* Prepare port(s) on the new clock configuration */
1527 ret = sdw_prep_deprep_ports(m_rt, true);
1528 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001529 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001530 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301531 return ret;
1532 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301533 }
1534
1535 stream->state = SDW_STREAM_PREPARED;
1536
1537 return ret;
1538
1539restore_params:
1540 memcpy(&bus->params, &params, sizeof(params));
1541 return ret;
1542}
1543
1544/**
1545 * sdw_prepare_stream() - Prepare SoundWire stream
1546 *
1547 * @stream: Soundwire stream
1548 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001549 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301550 */
1551int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1552{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001553 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001554 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301555
1556 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001557 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301558 return -EINVAL;
1559 }
1560
Vinod Koul48949722018-07-27 14:44:14 +05301561 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301562
Bard Liaoc32464c2020-01-14 17:52:24 -06001563 if (stream->state == SDW_STREAM_PREPARED) {
1564 ret = 0;
1565 goto state_err;
1566 }
1567
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001568 if (stream->state != SDW_STREAM_CONFIGURED &&
1569 stream->state != SDW_STREAM_DEPREPARED &&
1570 stream->state != SDW_STREAM_DISABLED) {
1571 pr_err("%s: %s: inconsistent state state %d\n",
1572 __func__, stream->name, stream->state);
1573 ret = -EINVAL;
1574 goto state_err;
1575 }
1576
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001577 /*
1578 * when the stream is DISABLED, this means sdw_prepare_stream()
1579 * is called as a result of an underflow or a resume operation.
1580 * In this case, the bus parameters shall not be recomputed, but
1581 * still need to be re-applied
1582 */
1583 if (stream->state == SDW_STREAM_DISABLED)
1584 update_params = false;
1585
1586 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301587
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001588state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301589 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301590 return ret;
1591}
1592EXPORT_SYMBOL(sdw_prepare_stream);
1593
1594static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1595{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001596 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301597 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301598 int ret;
1599
Vinod Koul48949722018-07-27 14:44:14 +05301600 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1601 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1602 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301603
Vinod Koul48949722018-07-27 14:44:14 +05301604 /* Program params */
1605 ret = sdw_program_params(bus);
1606 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001607 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301608 return ret;
1609 }
1610
1611 /* Enable port(s) */
1612 ret = sdw_enable_disable_ports(m_rt, true);
1613 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301614 dev_err(bus->dev,
1615 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301616 return ret;
1617 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301618 }
1619
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001620 if (!bus) {
1621 pr_err("Configuration error in %s\n", __func__);
1622 return -EINVAL;
1623 }
1624
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301625 ret = do_bank_switch(stream);
1626 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001627 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301628 return ret;
1629 }
1630
1631 stream->state = SDW_STREAM_ENABLED;
1632 return 0;
1633}
1634
1635/**
1636 * sdw_enable_stream() - Enable SoundWire stream
1637 *
1638 * @stream: Soundwire stream
1639 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001640 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301641 */
1642int sdw_enable_stream(struct sdw_stream_runtime *stream)
1643{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001644 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301645
1646 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001647 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301648 return -EINVAL;
1649 }
1650
Vinod Koul48949722018-07-27 14:44:14 +05301651 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301652
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001653 if (stream->state != SDW_STREAM_PREPARED &&
1654 stream->state != SDW_STREAM_DISABLED) {
1655 pr_err("%s: %s: inconsistent state state %d\n",
1656 __func__, stream->name, stream->state);
1657 ret = -EINVAL;
1658 goto state_err;
1659 }
1660
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301661 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301662
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001663state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301664 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301665 return ret;
1666}
1667EXPORT_SYMBOL(sdw_enable_stream);
1668
1669static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1670{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001671 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301672 int ret;
1673
Vinod Koul48949722018-07-27 14:44:14 +05301674 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001675 struct sdw_bus *bus = m_rt->bus;
1676
Vinod Koul48949722018-07-27 14:44:14 +05301677 /* Disable port(s) */
1678 ret = sdw_enable_disable_ports(m_rt, false);
1679 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001680 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301681 return ret;
1682 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301683 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301684 stream->state = SDW_STREAM_DISABLED;
1685
Vinod Koul48949722018-07-27 14:44:14 +05301686 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001687 struct sdw_bus *bus = m_rt->bus;
1688
Vinod Koul48949722018-07-27 14:44:14 +05301689 /* Program params */
1690 ret = sdw_program_params(bus);
1691 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001692 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301693 return ret;
1694 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301695 }
1696
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001697 ret = do_bank_switch(stream);
1698 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001699 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001700 return ret;
1701 }
1702
1703 /* make sure alternate bank (previous current) is also disabled */
1704 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001705 struct sdw_bus *bus = m_rt->bus;
1706
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001707 /* Disable port(s) */
1708 ret = sdw_enable_disable_ports(m_rt, false);
1709 if (ret < 0) {
1710 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1711 return ret;
1712 }
1713 }
1714
1715 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301716}
1717
1718/**
1719 * sdw_disable_stream() - Disable SoundWire stream
1720 *
1721 * @stream: Soundwire stream
1722 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001723 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301724 */
1725int sdw_disable_stream(struct sdw_stream_runtime *stream)
1726{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001727 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301728
1729 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001730 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301731 return -EINVAL;
1732 }
1733
Vinod Koul48949722018-07-27 14:44:14 +05301734 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301735
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001736 if (stream->state != SDW_STREAM_ENABLED) {
1737 pr_err("%s: %s: inconsistent state state %d\n",
1738 __func__, stream->name, stream->state);
1739 ret = -EINVAL;
1740 goto state_err;
1741 }
1742
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301743 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301744
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001745state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301746 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301747 return ret;
1748}
1749EXPORT_SYMBOL(sdw_disable_stream);
1750
1751static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1752{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001753 struct sdw_master_runtime *m_rt;
1754 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301755 int ret = 0;
1756
Vinod Koul48949722018-07-27 14:44:14 +05301757 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1758 bus = m_rt->bus;
1759 /* De-prepare port(s) */
1760 ret = sdw_prep_deprep_ports(m_rt, false);
1761 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301762 dev_err(bus->dev,
1763 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301764 return ret;
1765 }
1766
1767 /* TODO: Update this during Device-Device support */
1768 bus->params.bandwidth -= m_rt->stream->params.rate *
1769 m_rt->ch_count * m_rt->stream->params.bps;
1770
1771 /* Program params */
1772 ret = sdw_program_params(bus);
1773 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001774 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301775 return ret;
1776 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301777 }
1778
1779 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301780 return do_bank_switch(stream);
1781}
1782
1783/**
1784 * sdw_deprepare_stream() - Deprepare SoundWire stream
1785 *
1786 * @stream: Soundwire stream
1787 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001788 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301789 */
1790int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1791{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001792 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301793
1794 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001795 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301796 return -EINVAL;
1797 }
1798
Vinod Koul48949722018-07-27 14:44:14 +05301799 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001800
1801 if (stream->state != SDW_STREAM_PREPARED &&
1802 stream->state != SDW_STREAM_DISABLED) {
1803 pr_err("%s: %s: inconsistent state state %d\n",
1804 __func__, stream->name, stream->state);
1805 ret = -EINVAL;
1806 goto state_err;
1807 }
1808
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301809 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301810
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001811state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301812 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301813 return ret;
1814}
1815EXPORT_SYMBOL(sdw_deprepare_stream);