blob: 89edc897b8eba07b033f5901d1e64140c33a37dd [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
24int rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
25 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
28int cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
29
30static int sdw_find_col_index(int col)
31{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
35 if (cols[i] == col)
36 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
42
43static int sdw_find_row_index(int row)
44{
45 int i;
46
47 for (i = 0; i < SDW_FRAME_ROWS; i++) {
48 if (rows[i] == row)
49 return i;
50 }
51
52 pr_warn("Requested row not found, selecting lowest row no: 48\n");
53 return 0;
54}
Vinod Koul897fe402019-05-02 16:29:29 +053055
Sanyog Kalef8101c72018-04-26 18:38:17 +053056static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050057 struct sdw_slave *slave,
58 struct sdw_transport_params *t_params,
59 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053060{
61 u32 addr1, addr2, addr3, addr4;
62 int ret;
63 u16 wbuf;
64
65 if (bus->params.next_bank) {
66 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
67 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
68 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
69 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
70 } else {
71 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
72 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
73 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
74 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
75 }
76
77 /* Program DPN_OffsetCtrl2 registers */
78 ret = sdw_write(slave, addr1, t_params->offset2);
79 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050080 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053081 return ret;
82 }
83
84 /* Program DPN_BlockCtrl3 register */
85 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
86 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050087 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053088 return ret;
89 }
90
91 /*
92 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053093 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053094 * handled, so bail out if we are not FULL data port type
95 */
96 if (type != SDW_DPN_FULL)
97 return ret;
98
99 /* Program DPN_SampleCtrl2 register */
100 wbuf = (t_params->sample_interval - 1);
101 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
102 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
103
104 ret = sdw_write(slave, addr3, wbuf);
105 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500106 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530107 return ret;
108 }
109
110 /* Program DPN_HCtrl register */
111 wbuf = t_params->hstart;
112 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
113 wbuf |= t_params->hstop;
114
115 ret = sdw_write(slave, addr4, wbuf);
116 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500117 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530118
119 return ret;
120}
121
122static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500123 struct sdw_slave_runtime *s_rt,
124 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530125{
126 struct sdw_transport_params *t_params = &p_rt->transport_params;
127 struct sdw_port_params *p_params = &p_rt->port_params;
128 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
129 u32 addr1, addr2, addr3, addr4, addr5, addr6;
130 struct sdw_dpn_prop *dpn_prop;
131 int ret;
132 u8 wbuf;
133
134 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500135 s_rt->direction,
136 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530137 if (!dpn_prop)
138 return -EINVAL;
139
140 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
141 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
142
143 if (bus->params.next_bank) {
144 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
145 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
146 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
147 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
148
149 } else {
150 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
151 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
152 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
153 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
154 }
155
156 /* Program DPN_PortCtrl register */
157 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
158 wbuf |= p_params->flow_mode;
159
160 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
161 if (ret < 0) {
162 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500163 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530164 t_params->port_num);
165 return ret;
166 }
167
168 /* Program DPN_BlockCtrl1 register */
169 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
170 if (ret < 0) {
171 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500172 "DPN_BlockCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530173 t_params->port_num);
174 return ret;
175 }
176
177 /* Program DPN_SampleCtrl1 register */
178 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
179 ret = sdw_write(s_rt->slave, addr3, wbuf);
180 if (ret < 0) {
181 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500182 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530183 t_params->port_num);
184 return ret;
185 }
186
187 /* Program DPN_OffsetCtrl1 registers */
188 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
189 if (ret < 0) {
190 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500191 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530192 t_params->port_num);
193 return ret;
194 }
195
196 /* Program DPN_BlockCtrl2 register*/
197 if (t_params->blk_grp_ctrl_valid) {
198 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
199 if (ret < 0) {
200 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500201 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530202 t_params->port_num);
203 return ret;
204 }
205 }
206
207 /* program DPN_LaneCtrl register */
208 if (slave_prop->lane_control_support) {
209 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
210 if (ret < 0) {
211 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500212 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530213 t_params->port_num);
214 return ret;
215 }
216 }
217
218 if (dpn_prop->type != SDW_DPN_SIMPLE) {
219 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500220 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530221 if (ret < 0)
222 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500223 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530224 t_params->port_num);
225 }
226
227 return ret;
228}
229
230static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500231 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530232{
233 int ret;
234
235 /*
236 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530237 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530238 * hstart/stop etc of the data. Port parameters refers to word
239 * length, flow mode etc of the port
240 */
241 ret = bus->port_ops->dpn_set_port_transport_params(bus,
242 &p_rt->transport_params,
243 bus->params.next_bank);
244 if (ret < 0)
245 return ret;
246
247 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500248 &p_rt->port_params,
249 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530250}
251
252/**
253 * sdw_program_port_params() - Programs transport parameters of Master(s)
254 * and Slave(s)
255 *
256 * @m_rt: Master stream runtime
257 */
258static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
259{
260 struct sdw_slave_runtime *s_rt = NULL;
261 struct sdw_bus *bus = m_rt->bus;
262 struct sdw_port_runtime *p_rt;
263 int ret = 0;
264
265 /* Program transport & port parameters for Slave(s) */
266 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
267 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
268 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
269 if (ret < 0)
270 return ret;
271 }
272 }
273
274 /* Program transport & port parameters for Master(s) */
275 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
276 ret = sdw_program_master_port_params(bus, p_rt);
277 if (ret < 0)
278 return ret;
279 }
280
281 return 0;
282}
283
Sanyog Kale89e59052018-04-26 18:38:08 +0530284/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530285 * sdw_enable_disable_slave_ports: Enable/disable slave data port
286 *
287 * @bus: bus instance
288 * @s_rt: slave runtime
289 * @p_rt: port runtime
290 * @en: enable or disable operation
291 *
292 * This function only sets the enable/disable bits in the relevant bank, the
293 * actual enable/disable is done with a bank switch
294 */
295static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500296 struct sdw_slave_runtime *s_rt,
297 struct sdw_port_runtime *p_rt,
298 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530299{
300 struct sdw_transport_params *t_params = &p_rt->transport_params;
301 u32 addr;
302 int ret;
303
304 if (bus->params.next_bank)
305 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
306 else
307 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
308
309 /*
310 * Since bus doesn't support sharing a port across two streams,
311 * it is safe to reset this register
312 */
313 if (en)
314 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
315 else
316 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
317
318 if (ret < 0)
319 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500320 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530321 ret, t_params->port_num);
322
323 return ret;
324}
325
326static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500327 struct sdw_port_runtime *p_rt,
328 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530329{
330 struct sdw_transport_params *t_params = &p_rt->transport_params;
331 struct sdw_bus *bus = m_rt->bus;
332 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500333 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530334
335 enable_ch.port_num = p_rt->num;
336 enable_ch.ch_mask = p_rt->ch_mask;
337 enable_ch.enable = en;
338
339 /* Perform Master port channel(s) enable/disable */
340 if (bus->port_ops->dpn_port_enable_ch) {
341 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500342 &enable_ch,
343 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530344 if (ret < 0) {
345 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500346 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530347 ret, t_params->port_num);
348 return ret;
349 }
350 } else {
351 dev_err(bus->dev,
352 "dpn_port_enable_ch not supported, %s failed\n",
353 en ? "enable" : "disable");
354 return -EINVAL;
355 }
356
357 return 0;
358}
359
360/**
361 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
362 * Slave(s)
363 *
364 * @m_rt: Master stream runtime
365 * @en: mode (enable/disable)
366 */
367static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
368{
369 struct sdw_port_runtime *s_port, *m_port;
370 struct sdw_slave_runtime *s_rt = NULL;
371 int ret = 0;
372
373 /* Enable/Disable Slave port(s) */
374 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
375 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
376 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500377 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530378 if (ret < 0)
379 return ret;
380 }
381 }
382
383 /* Enable/Disable Master port(s) */
384 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
385 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
386 if (ret < 0)
387 return ret;
388 }
389
390 return 0;
391}
392
393static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500394 struct sdw_prepare_ch prep_ch,
395 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530396{
397 const struct sdw_slave_ops *ops = s_rt->slave->ops;
398 int ret;
399
400 if (ops->port_prep) {
401 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
402 if (ret < 0) {
403 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530404 "Slave Port Prep cmd %d failed: %d\n",
405 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530406 return ret;
407 }
408 }
409
410 return 0;
411}
412
413static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500414 struct sdw_slave_runtime *s_rt,
415 struct sdw_port_runtime *p_rt,
416 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530417{
418 struct completion *port_ready = NULL;
419 struct sdw_dpn_prop *dpn_prop;
420 struct sdw_prepare_ch prep_ch;
421 unsigned int time_left;
422 bool intr = false;
423 int ret = 0, val;
424 u32 addr;
425
426 prep_ch.num = p_rt->num;
427 prep_ch.ch_mask = p_rt->ch_mask;
428
429 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500430 s_rt->direction,
431 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530432 if (!dpn_prop) {
433 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500434 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530435 return -EINVAL;
436 }
437
438 prep_ch.prepare = prep;
439
440 prep_ch.bank = bus->params.next_bank;
441
442 if (dpn_prop->device_interrupts || !dpn_prop->simple_ch_prep_sm)
443 intr = true;
444
445 /*
446 * Enable interrupt before Port prepare.
447 * For Port de-prepare, it is assumed that port
448 * was prepared earlier
449 */
450 if (prep && intr) {
451 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500452 dpn_prop->device_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530453 if (ret < 0)
454 return ret;
455 }
456
457 /* Inform slave about the impending port prepare */
458 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
459
460 /* Prepare Slave port implementing CP_SM */
461 if (!dpn_prop->simple_ch_prep_sm) {
462 addr = SDW_DPN_PREPARECTRL(p_rt->num);
463
464 if (prep)
465 ret = sdw_update(s_rt->slave, addr,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500466 0xFF, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530467 else
468 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
469
470 if (ret < 0) {
471 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500472 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530473 return ret;
474 }
475
476 /* Wait for completion on port ready */
477 port_ready = &s_rt->slave->port_ready[prep_ch.num];
478 time_left = wait_for_completion_timeout(port_ready,
479 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
480
481 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
482 val &= p_rt->ch_mask;
483 if (!time_left || val) {
484 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500485 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530486 return -ETIMEDOUT;
487 }
488 }
489
490 /* Inform slaves about ports prepared */
491 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
492
493 /* Disable interrupt after Port de-prepare */
494 if (!prep && intr)
495 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500496 dpn_prop->device_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530497
498 return ret;
499}
500
501static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500502 struct sdw_port_runtime *p_rt,
503 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530504{
505 struct sdw_transport_params *t_params = &p_rt->transport_params;
506 struct sdw_bus *bus = m_rt->bus;
507 const struct sdw_master_port_ops *ops = bus->port_ops;
508 struct sdw_prepare_ch prep_ch;
509 int ret = 0;
510
511 prep_ch.num = p_rt->num;
512 prep_ch.ch_mask = p_rt->ch_mask;
513 prep_ch.prepare = prep; /* Prepare/De-prepare */
514 prep_ch.bank = bus->params.next_bank;
515
516 /* Pre-prepare/Pre-deprepare port(s) */
517 if (ops->dpn_port_prep) {
518 ret = ops->dpn_port_prep(bus, &prep_ch);
519 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500520 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500521 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530522 return ret;
523 }
524 }
525
526 return ret;
527}
528
529/**
530 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
531 * Slave(s)
532 *
533 * @m_rt: Master runtime handle
534 * @prep: Prepare or De-prepare
535 */
536static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
537{
538 struct sdw_slave_runtime *s_rt = NULL;
539 struct sdw_port_runtime *p_rt;
540 int ret = 0;
541
542 /* Prepare/De-prepare Slave port(s) */
543 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
544 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
545 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500546 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530547 if (ret < 0)
548 return ret;
549 }
550 }
551
552 /* Prepare/De-prepare Master port(s) */
553 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
554 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
555 if (ret < 0)
556 return ret;
557 }
558
559 return ret;
560}
561
562/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530563 * sdw_notify_config() - Notify bus configuration
564 *
565 * @m_rt: Master runtime handle
566 *
567 * This function notifies the Master(s) and Slave(s) of the
568 * new bus configuration.
569 */
570static int sdw_notify_config(struct sdw_master_runtime *m_rt)
571{
572 struct sdw_slave_runtime *s_rt;
573 struct sdw_bus *bus = m_rt->bus;
574 struct sdw_slave *slave;
575 int ret = 0;
576
577 if (bus->ops->set_bus_conf) {
578 ret = bus->ops->set_bus_conf(bus, &bus->params);
579 if (ret < 0)
580 return ret;
581 }
582
583 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
584 slave = s_rt->slave;
585
586 if (slave->ops->bus_config) {
587 ret = slave->ops->bus_config(slave, &bus->params);
588 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500589 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500590 slave->dev_num);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530591 return ret;
592 }
593 }
594
595 return ret;
596}
597
598/**
599 * sdw_program_params() - Program transport and port parameters for Master(s)
600 * and Slave(s)
601 *
602 * @bus: SDW bus instance
603 */
604static int sdw_program_params(struct sdw_bus *bus)
605{
606 struct sdw_master_runtime *m_rt = NULL;
607 int ret = 0;
608
609 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
610 ret = sdw_program_port_params(m_rt);
611 if (ret < 0) {
612 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500613 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530614 return ret;
615 }
616
617 ret = sdw_notify_config(m_rt);
618 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530619 dev_err(bus->dev,
620 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530621 return ret;
622 }
623
624 /* Enable port(s) on alternate bank for all active streams */
625 if (m_rt->stream->state != SDW_STREAM_ENABLED)
626 continue;
627
628 ret = sdw_enable_disable_ports(m_rt, true);
629 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500630 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530631 return ret;
632 }
633 }
634
635 return ret;
636}
637
Shreyas NCce6e74d2018-07-27 14:44:16 +0530638static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530639{
640 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530641 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530642 struct sdw_msg *wr_msg;
643 u8 *wbuf = NULL;
644 int ret = 0;
645 u16 addr;
646
647 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
648 if (!wr_msg)
649 return -ENOMEM;
650
Shreyas NCce6e74d2018-07-27 14:44:16 +0530651 bus->defer_msg.msg = wr_msg;
652
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530653 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
654 if (!wbuf) {
655 ret = -ENOMEM;
656 goto error_1;
657 }
658
659 /* Get row and column index to program register */
660 col_index = sdw_find_col_index(bus->params.col);
661 row_index = sdw_find_row_index(bus->params.row);
662 wbuf[0] = col_index | (row_index << 3);
663
664 if (bus->params.next_bank)
665 addr = SDW_SCP_FRAMECTRL_B1;
666 else
667 addr = SDW_SCP_FRAMECTRL_B0;
668
669 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500670 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530671 wr_msg->ssp_sync = true;
672
Shreyas NCce6e74d2018-07-27 14:44:16 +0530673 /*
674 * Set the multi_link flag only when both the hardware supports
675 * and there is a stream handled by multiple masters
676 */
677 multi_link = bus->multi_link && (m_rt_count > 1);
678
679 if (multi_link)
680 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
681 else
682 ret = sdw_transfer(bus, wr_msg);
683
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530684 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500685 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530686 goto error;
687 }
688
Shreyas NCce6e74d2018-07-27 14:44:16 +0530689 if (!multi_link) {
690 kfree(wr_msg);
691 kfree(wbuf);
692 bus->defer_msg.msg = NULL;
693 bus->params.curr_bank = !bus->params.curr_bank;
694 bus->params.next_bank = !bus->params.next_bank;
695 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530696
697 return 0;
698
699error:
700 kfree(wbuf);
701error_1:
702 kfree(wr_msg);
703 return ret;
704}
705
Shreyas NCce6e74d2018-07-27 14:44:16 +0530706/**
707 * sdw_ml_sync_bank_switch: Multilink register bank switch
708 *
709 * @bus: SDW bus instance
710 *
711 * Caller function should free the buffers on error
712 */
713static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
714{
715 unsigned long time_left;
716
717 if (!bus->multi_link)
718 return 0;
719
720 /* Wait for completion of transfer */
721 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
722 bus->bank_switch_timeout);
723
724 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500725 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530726 return -ETIMEDOUT;
727 }
728
729 bus->params.curr_bank = !bus->params.curr_bank;
730 bus->params.next_bank = !bus->params.next_bank;
731
732 if (bus->defer_msg.msg) {
733 kfree(bus->defer_msg.msg->buf);
734 kfree(bus->defer_msg.msg);
735 }
736
737 return 0;
738}
739
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530740static int do_bank_switch(struct sdw_stream_runtime *stream)
741{
Vinod Koul48949722018-07-27 14:44:14 +0530742 struct sdw_master_runtime *m_rt = NULL;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530743 const struct sdw_master_ops *ops;
Vinod Koul48949722018-07-27 14:44:14 +0530744 struct sdw_bus *bus = NULL;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530745 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530746 int ret = 0;
747
Vinod Koul48949722018-07-27 14:44:14 +0530748 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
749 bus = m_rt->bus;
750 ops = bus->ops;
751
Shreyas NCce6e74d2018-07-27 14:44:16 +0530752 if (bus->multi_link) {
753 multi_link = true;
754 mutex_lock(&bus->msg_lock);
755 }
756
Vinod Koul48949722018-07-27 14:44:14 +0530757 /* Pre-bank switch */
758 if (ops->pre_bank_switch) {
759 ret = ops->pre_bank_switch(bus);
760 if (ret < 0) {
761 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500762 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530763 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530764 }
765 }
766
Shreyas NCce6e74d2018-07-27 14:44:16 +0530767 /*
768 * Perform Bank switch operation.
769 * For multi link cases, the actual bank switch is
770 * synchronized across all Masters and happens later as a
771 * part of post_bank_switch ops.
772 */
773 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530774 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500775 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530776 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530777 }
778 }
779
Shreyas NCce6e74d2018-07-27 14:44:16 +0530780 /*
781 * For multi link cases, it is expected that the bank switch is
782 * triggered by the post_bank_switch for the first Master in the list
783 * and for the other Masters the post_bank_switch() should return doing
784 * nothing.
785 */
Vinod Koul48949722018-07-27 14:44:14 +0530786 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
787 bus = m_rt->bus;
788 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530789
Vinod Koul48949722018-07-27 14:44:14 +0530790 /* Post-bank switch */
791 if (ops->post_bank_switch) {
792 ret = ops->post_bank_switch(bus);
793 if (ret < 0) {
794 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530795 "Post bank switch op failed: %d\n",
796 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530797 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530798 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530799 } else if (bus->multi_link && stream->m_rt_count > 1) {
800 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500801 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530802 goto error;
803 }
804
805 /* Set the bank switch timeout to default, if not set */
806 if (!bus->bank_switch_timeout)
807 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
808
809 /* Check if bank switch was successful */
810 ret = sdw_ml_sync_bank_switch(bus);
811 if (ret < 0) {
812 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500813 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530814 goto error;
815 }
816
817 mutex_unlock(&bus->msg_lock);
818 }
819
820 return ret;
821
822error:
823 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530824 bus = m_rt->bus;
825
826 kfree(bus->defer_msg.msg->buf);
827 kfree(bus->defer_msg.msg);
828 }
829
830msg_unlock:
831
832 if (multi_link) {
833 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
834 bus = m_rt->bus;
835 if (mutex_is_locked(&bus->msg_lock))
836 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530837 }
838 }
839
840 return ret;
841}
842
843/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530844 * sdw_release_stream() - Free the assigned stream runtime
845 *
846 * @stream: SoundWire stream runtime
847 *
848 * sdw_release_stream should be called only once per stream
849 */
850void sdw_release_stream(struct sdw_stream_runtime *stream)
851{
852 kfree(stream);
853}
854EXPORT_SYMBOL(sdw_release_stream);
855
856/**
857 * sdw_alloc_stream() - Allocate and return stream runtime
858 *
859 * @stream_name: SoundWire stream name
860 *
861 * Allocates a SoundWire stream runtime instance.
862 * sdw_alloc_stream should be called only once per stream. Typically
863 * invoked from ALSA/ASoC machine/platform driver.
864 */
865struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name)
866{
867 struct sdw_stream_runtime *stream;
868
869 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
870 if (!stream)
871 return NULL;
872
873 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530874 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530875 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530876 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530877
878 return stream;
879}
880EXPORT_SYMBOL(sdw_alloc_stream);
881
Vinod Koul48949722018-07-27 14:44:14 +0530882static struct sdw_master_runtime
883*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500884 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530885{
886 struct sdw_master_runtime *m_rt = NULL;
887
888 /* Retrieve Bus handle if already available */
889 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
890 if (m_rt->bus == bus)
891 return m_rt;
892 }
893
894 return NULL;
895}
896
Sanyog Kale89e59052018-04-26 18:38:08 +0530897/**
898 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
899 *
900 * @bus: SDW bus instance
901 * @stream_config: Stream configuration
902 * @stream: Stream runtime handle.
903 *
904 * This function is to be called with bus_lock held.
905 */
906static struct sdw_master_runtime
907*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500908 struct sdw_stream_config *stream_config,
909 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530910{
911 struct sdw_master_runtime *m_rt;
912
Sanyog Kale89e59052018-04-26 18:38:08 +0530913 /*
914 * check if Master is already allocated (as a result of Slave adding
915 * it first), if so skip allocation and go to configure
916 */
Vinod Koul48949722018-07-27 14:44:14 +0530917 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530918 if (m_rt)
919 goto stream_config;
920
921 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
922 if (!m_rt)
923 return NULL;
924
925 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530926 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530927 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530928 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530929
930 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
931
932stream_config:
933 m_rt->ch_count = stream_config->ch_count;
934 m_rt->bus = bus;
935 m_rt->stream = stream;
936 m_rt->direction = stream_config->direction;
937
938 return m_rt;
939}
940
941/**
942 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
943 *
944 * @slave: Slave handle
945 * @stream_config: Stream configuration
946 * @stream: Stream runtime handle
947 *
948 * This function is to be called with bus_lock held.
949 */
950static struct sdw_slave_runtime
951*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500952 struct sdw_stream_config *stream_config,
953 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530954{
955 struct sdw_slave_runtime *s_rt = NULL;
956
957 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
958 if (!s_rt)
959 return NULL;
960
Sanyog Kalebbe73792018-04-26 18:38:13 +0530961 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530962 s_rt->ch_count = stream_config->ch_count;
963 s_rt->direction = stream_config->direction;
964 s_rt->slave = slave;
965
966 return s_rt;
967}
968
Sanyog Kalebbe73792018-04-26 18:38:13 +0530969static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500970 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530971{
972 struct sdw_port_runtime *p_rt, *_p_rt;
973
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500974 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530975 list_del(&p_rt->port_node);
976 kfree(p_rt);
977 }
978}
979
980static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500981 struct sdw_slave *slave,
982 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530983{
984 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530985 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +0530986 struct sdw_slave_runtime *s_rt;
987
Vinod Koul48949722018-07-27 14:44:14 +0530988 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
989 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530990 if (s_rt->slave != slave)
991 continue;
992
993 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500994 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +0530995 list_del(&p_rt->port_node);
996 kfree(p_rt);
997 }
Sanyog Kalebbe73792018-04-26 18:38:13 +0530998 }
999 }
1000}
1001
Sanyog Kale89e59052018-04-26 18:38:08 +05301002/**
1003 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1004 *
1005 * @slave: Slave handle.
1006 * @stream: Stream runtime handle.
1007 *
1008 * This function is to be called with bus_lock held.
1009 */
1010static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001011 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301012{
1013 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301014 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301015
Vinod Koul48949722018-07-27 14:44:14 +05301016 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1017 /* Retrieve Slave runtime handle */
1018 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001019 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301020 if (s_rt->slave == slave) {
1021 list_del(&s_rt->m_rt_node);
1022 kfree(s_rt);
1023 return;
1024 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301025 }
1026 }
1027}
1028
1029/**
1030 * sdw_release_master_stream() - Free Master runtime handle
1031 *
Vinod Koul48949722018-07-27 14:44:14 +05301032 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301033 * @stream: Stream runtime handle.
1034 *
1035 * This function is to be called with bus_lock held
1036 * It frees the Master runtime handle and associated Slave(s) runtime
1037 * handle. If this is called first then sdw_release_slave_stream() will have
1038 * no effect as Slave(s) runtime handle would already be freed up.
1039 */
Vinod Koul48949722018-07-27 14:44:14 +05301040static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001041 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301042{
Sanyog Kale89e59052018-04-26 18:38:08 +05301043 struct sdw_slave_runtime *s_rt, *_s_rt;
1044
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301045 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1046 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1047 sdw_release_slave_stream(s_rt->slave, stream);
1048 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301049
Vinod Koul48949722018-07-27 14:44:14 +05301050 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301051 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301052 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301053}
1054
1055/**
1056 * sdw_stream_remove_master() - Remove master from sdw_stream
1057 *
1058 * @bus: SDW Bus instance
1059 * @stream: SoundWire stream
1060 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301061 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301062 */
1063int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001064 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301065{
Vinod Koul48949722018-07-27 14:44:14 +05301066 struct sdw_master_runtime *m_rt, *_m_rt;
1067
Sanyog Kale89e59052018-04-26 18:38:08 +05301068 mutex_lock(&bus->bus_lock);
1069
Vinod Koul48949722018-07-27 14:44:14 +05301070 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001071 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301072 if (m_rt->bus != bus)
1073 continue;
1074
1075 sdw_master_port_release(bus, m_rt);
1076 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301077 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301078 }
1079
1080 if (list_empty(&stream->master_list))
1081 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301082
1083 mutex_unlock(&bus->bus_lock);
1084
1085 return 0;
1086}
1087EXPORT_SYMBOL(sdw_stream_remove_master);
1088
1089/**
1090 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1091 *
1092 * @slave: SDW Slave instance
1093 * @stream: SoundWire stream
1094 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301095 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301096 */
1097int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001098 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301099{
1100 mutex_lock(&slave->bus->bus_lock);
1101
Sanyog Kalebbe73792018-04-26 18:38:13 +05301102 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301103 sdw_release_slave_stream(slave, stream);
1104
1105 mutex_unlock(&slave->bus->bus_lock);
1106
1107 return 0;
1108}
1109EXPORT_SYMBOL(sdw_stream_remove_slave);
1110
1111/**
1112 * sdw_config_stream() - Configure the allocated stream
1113 *
1114 * @dev: SDW device
1115 * @stream: SoundWire stream
1116 * @stream_config: Stream configuration for audio stream
1117 * @is_slave: is API called from Slave or Master
1118 *
1119 * This function is to be called with bus_lock held.
1120 */
1121static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001122 struct sdw_stream_runtime *stream,
1123 struct sdw_stream_config *stream_config,
1124 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301125{
1126 /*
1127 * Update the stream rate, channel and bps based on data
1128 * source. For more than one data source (multilink),
1129 * match the rate, bps, stream type and increment number of channels.
1130 *
1131 * If rate/bps is zero, it means the values are not set, so skip
1132 * comparison and allow the value to be set and stored in stream
1133 */
1134 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001135 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001136 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301137 return -EINVAL;
1138 }
1139
1140 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001141 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001142 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301143 return -EINVAL;
1144 }
1145
1146 stream->type = stream_config->type;
1147 stream->params.rate = stream_config->frame_rate;
1148 stream->params.bps = stream_config->bps;
1149
1150 /* TODO: Update this check during Device-device support */
1151 if (is_slave)
1152 stream->params.ch_count += stream_config->ch_count;
1153
1154 return 0;
1155}
1156
Sanyog Kalebbe73792018-04-26 18:38:13 +05301157static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001158 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301159{
1160 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1161 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001162 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301163 return -EINVAL;
1164 }
1165
1166 return 0;
1167}
1168
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001169static struct sdw_port_runtime
1170*sdw_port_alloc(struct device *dev,
1171 struct sdw_port_config *port_config,
1172 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301173{
1174 struct sdw_port_runtime *p_rt;
1175
1176 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1177 if (!p_rt)
1178 return NULL;
1179
1180 p_rt->ch_mask = port_config[port_index].ch_mask;
1181 p_rt->num = port_config[port_index].num;
1182
1183 return p_rt;
1184}
1185
1186static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001187 struct sdw_master_runtime *m_rt,
1188 struct sdw_port_config *port_config,
1189 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301190{
1191 struct sdw_port_runtime *p_rt;
1192 int i;
1193
1194 /* Iterate for number of ports to perform initialization */
1195 for (i = 0; i < num_ports; i++) {
1196 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1197 if (!p_rt)
1198 return -ENOMEM;
1199
1200 /*
1201 * TODO: Check port capabilities for requested
1202 * configuration (audio mode support)
1203 */
1204
1205 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1206 }
1207
1208 return 0;
1209}
1210
1211static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001212 struct sdw_slave_runtime *s_rt,
1213 struct sdw_port_config *port_config,
1214 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301215{
1216 struct sdw_port_runtime *p_rt;
1217 int i, ret;
1218
1219 /* Iterate for number of ports to perform initialization */
1220 for (i = 0; i < num_config; i++) {
1221 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1222 if (!p_rt)
1223 return -ENOMEM;
1224
1225 /*
1226 * TODO: Check valid port range as defined by DisCo/
1227 * slave
1228 */
1229 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1230 if (ret < 0) {
1231 kfree(p_rt);
1232 return ret;
1233 }
1234
1235 /*
1236 * TODO: Check port capabilities for requested
1237 * configuration (audio mode support)
1238 */
1239
1240 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1241 }
1242
1243 return 0;
1244}
1245
Sanyog Kale89e59052018-04-26 18:38:08 +05301246/**
1247 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1248 *
1249 * @bus: SDW Bus instance
1250 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301251 * @port_config: Port configuration for audio stream
1252 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301253 * @stream: SoundWire stream
1254 */
1255int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001256 struct sdw_stream_config *stream_config,
1257 struct sdw_port_config *port_config,
1258 unsigned int num_ports,
1259 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301260{
1261 struct sdw_master_runtime *m_rt = NULL;
1262 int ret;
1263
1264 mutex_lock(&bus->bus_lock);
1265
Shreyas NCce6e74d2018-07-27 14:44:16 +05301266 /*
1267 * For multi link streams, add the second master only if
1268 * the bus supports it.
1269 * Check if bus->multi_link is set
1270 */
1271 if (!bus->multi_link && stream->m_rt_count > 0) {
1272 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001273 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301274 ret = -EINVAL;
1275 goto unlock;
1276 }
1277
Sanyog Kale89e59052018-04-26 18:38:08 +05301278 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1279 if (!m_rt) {
1280 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001281 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001282 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301283 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301284 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301285 }
1286
1287 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1288 if (ret)
1289 goto stream_error;
1290
Sanyog Kalebbe73792018-04-26 18:38:13 +05301291 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1292 if (ret)
1293 goto stream_error;
1294
Shreyas NCce6e74d2018-07-27 14:44:16 +05301295 stream->m_rt_count++;
1296
Shreyas NC3fef1a22018-07-27 14:44:09 +05301297 goto unlock;
1298
Sanyog Kale89e59052018-04-26 18:38:08 +05301299stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301300 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301301unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301302 mutex_unlock(&bus->bus_lock);
1303 return ret;
1304}
1305EXPORT_SYMBOL(sdw_stream_add_master);
1306
1307/**
1308 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1309 *
1310 * @slave: SDW Slave instance
1311 * @stream_config: Stream configuration for audio stream
1312 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301313 * @port_config: Port configuration for audio stream
1314 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301315 *
1316 * It is expected that Slave is added before adding Master
1317 * to the Stream.
1318 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301319 */
1320int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001321 struct sdw_stream_config *stream_config,
1322 struct sdw_port_config *port_config,
1323 unsigned int num_ports,
1324 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301325{
1326 struct sdw_slave_runtime *s_rt;
1327 struct sdw_master_runtime *m_rt;
1328 int ret;
1329
1330 mutex_lock(&slave->bus->bus_lock);
1331
1332 /*
1333 * If this API is invoked by Slave first then m_rt is not valid.
1334 * So, allocate m_rt and add Slave to it.
1335 */
1336 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1337 if (!m_rt) {
1338 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001339 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001340 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301341 ret = -ENOMEM;
1342 goto error;
1343 }
1344
1345 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1346 if (!s_rt) {
1347 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001348 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001349 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301350 ret = -ENOMEM;
1351 goto stream_error;
1352 }
1353
1354 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1355 if (ret)
1356 goto stream_error;
1357
1358 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1359
Sanyog Kalebbe73792018-04-26 18:38:13 +05301360 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1361 if (ret)
1362 goto stream_error;
1363
Shreyas NC0aebe402018-07-27 14:44:08 +05301364 /*
1365 * Change stream state to CONFIGURED on first Slave add.
1366 * Bus is not aware of number of Slave(s) in a stream at this
1367 * point so cannot depend on all Slave(s) to be added in order to
1368 * change stream state to CONFIGURED.
1369 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301370 stream->state = SDW_STREAM_CONFIGURED;
1371 goto error;
1372
1373stream_error:
1374 /*
1375 * we hit error so cleanup the stream, release all Slave(s) and
1376 * Master runtime
1377 */
Vinod Koul48949722018-07-27 14:44:14 +05301378 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301379error:
1380 mutex_unlock(&slave->bus->bus_lock);
1381 return ret;
1382}
1383EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301384
1385/**
1386 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1387 *
1388 * @slave: Slave handle
1389 * @direction: Data direction.
1390 * @port_num: Port number
1391 */
1392struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001393 enum sdw_data_direction direction,
1394 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301395{
1396 struct sdw_dpn_prop *dpn_prop;
1397 u8 num_ports;
1398 int i;
1399
1400 if (direction == SDW_DATA_DIR_TX) {
1401 num_ports = hweight32(slave->prop.source_ports);
1402 dpn_prop = slave->prop.src_dpn_prop;
1403 } else {
1404 num_ports = hweight32(slave->prop.sink_ports);
1405 dpn_prop = slave->prop.sink_dpn_prop;
1406 }
1407
1408 for (i = 0; i < num_ports; i++) {
1409 dpn_prop = &dpn_prop[i];
1410
1411 if (dpn_prop->num == port_num)
1412 return &dpn_prop[i];
1413 }
1414
1415 return NULL;
1416}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301417
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301418/**
1419 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1420 *
1421 * @stream: SoundWire stream
1422 *
1423 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1424 * stream to reconfigure the bus.
1425 * NOTE: This function is called from SoundWire stream ops and is
1426 * expected that a global lock is held before acquiring bus_lock.
1427 */
1428static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1429{
1430 struct sdw_master_runtime *m_rt = NULL;
1431 struct sdw_bus *bus = NULL;
1432
1433 /* Iterate for all Master(s) in Master list */
1434 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1435 bus = m_rt->bus;
1436
1437 mutex_lock(&bus->bus_lock);
1438 }
1439}
1440
1441/**
1442 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1443 *
1444 * @stream: SoundWire stream
1445 *
1446 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301447 * NOTE: This function is called from SoundWire stream ops and is
1448 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301449 */
1450static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1451{
1452 struct sdw_master_runtime *m_rt = NULL;
1453 struct sdw_bus *bus = NULL;
1454
1455 /* Iterate for all Master(s) in Master list */
1456 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1457 bus = m_rt->bus;
1458 mutex_unlock(&bus->bus_lock);
1459 }
1460}
1461
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301462static int _sdw_prepare_stream(struct sdw_stream_runtime *stream)
1463{
Vinod Koul48949722018-07-27 14:44:14 +05301464 struct sdw_master_runtime *m_rt = NULL;
1465 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301466 struct sdw_master_prop *prop = NULL;
1467 struct sdw_bus_params params;
1468 int ret;
1469
Vinod Koul48949722018-07-27 14:44:14 +05301470 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1471 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1472 bus = m_rt->bus;
1473 prop = &bus->prop;
1474 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301475
Vinod Koul48949722018-07-27 14:44:14 +05301476 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001477 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001478 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301479 return -EINVAL;
1480 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301481
Vinod Koul48949722018-07-27 14:44:14 +05301482 /* Increment cumulative bus bandwidth */
1483 /* TODO: Update this during Device-Device support */
1484 bus->params.bandwidth += m_rt->stream->params.rate *
1485 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301486
Vinod Koul48949722018-07-27 14:44:14 +05301487 /* Program params */
1488 ret = sdw_program_params(bus);
1489 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001490 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301491 goto restore_params;
1492 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301493 }
1494
1495 ret = do_bank_switch(stream);
1496 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001497 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301498 goto restore_params;
1499 }
1500
Vinod Koul48949722018-07-27 14:44:14 +05301501 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1502 bus = m_rt->bus;
1503
1504 /* Prepare port(s) on the new clock configuration */
1505 ret = sdw_prep_deprep_ports(m_rt, true);
1506 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001507 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001508 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301509 return ret;
1510 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301511 }
1512
1513 stream->state = SDW_STREAM_PREPARED;
1514
1515 return ret;
1516
1517restore_params:
1518 memcpy(&bus->params, &params, sizeof(params));
1519 return ret;
1520}
1521
1522/**
1523 * sdw_prepare_stream() - Prepare SoundWire stream
1524 *
1525 * @stream: Soundwire stream
1526 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001527 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301528 */
1529int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1530{
1531 int ret = 0;
1532
1533 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001534 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301535 return -EINVAL;
1536 }
1537
Vinod Koul48949722018-07-27 14:44:14 +05301538 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301539
1540 ret = _sdw_prepare_stream(stream);
1541 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001542 pr_err("Prepare for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301543
Vinod Koul48949722018-07-27 14:44:14 +05301544 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301545 return ret;
1546}
1547EXPORT_SYMBOL(sdw_prepare_stream);
1548
1549static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1550{
Vinod Koul48949722018-07-27 14:44:14 +05301551 struct sdw_master_runtime *m_rt = NULL;
1552 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301553 int ret;
1554
Vinod Koul48949722018-07-27 14:44:14 +05301555 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1556 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1557 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301558
Vinod Koul48949722018-07-27 14:44:14 +05301559 /* Program params */
1560 ret = sdw_program_params(bus);
1561 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001562 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301563 return ret;
1564 }
1565
1566 /* Enable port(s) */
1567 ret = sdw_enable_disable_ports(m_rt, true);
1568 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301569 dev_err(bus->dev,
1570 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301571 return ret;
1572 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301573 }
1574
1575 ret = do_bank_switch(stream);
1576 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001577 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301578 return ret;
1579 }
1580
1581 stream->state = SDW_STREAM_ENABLED;
1582 return 0;
1583}
1584
1585/**
1586 * sdw_enable_stream() - Enable SoundWire stream
1587 *
1588 * @stream: Soundwire stream
1589 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001590 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301591 */
1592int sdw_enable_stream(struct sdw_stream_runtime *stream)
1593{
1594 int ret = 0;
1595
1596 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001597 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301598 return -EINVAL;
1599 }
1600
Vinod Koul48949722018-07-27 14:44:14 +05301601 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301602
1603 ret = _sdw_enable_stream(stream);
1604 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001605 pr_err("Enable for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301606
Vinod Koul48949722018-07-27 14:44:14 +05301607 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301608 return ret;
1609}
1610EXPORT_SYMBOL(sdw_enable_stream);
1611
1612static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1613{
Vinod Koul48949722018-07-27 14:44:14 +05301614 struct sdw_master_runtime *m_rt = NULL;
1615 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301616 int ret;
1617
Vinod Koul48949722018-07-27 14:44:14 +05301618 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1619 bus = m_rt->bus;
1620 /* Disable port(s) */
1621 ret = sdw_enable_disable_ports(m_rt, false);
1622 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001623 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301624 return ret;
1625 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301626 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301627 stream->state = SDW_STREAM_DISABLED;
1628
Vinod Koul48949722018-07-27 14:44:14 +05301629 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1630 bus = m_rt->bus;
1631 /* Program params */
1632 ret = sdw_program_params(bus);
1633 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001634 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301635 return ret;
1636 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301637 }
1638
1639 return do_bank_switch(stream);
1640}
1641
1642/**
1643 * sdw_disable_stream() - Disable SoundWire stream
1644 *
1645 * @stream: Soundwire stream
1646 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001647 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301648 */
1649int sdw_disable_stream(struct sdw_stream_runtime *stream)
1650{
1651 int ret = 0;
1652
1653 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001654 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301655 return -EINVAL;
1656 }
1657
Vinod Koul48949722018-07-27 14:44:14 +05301658 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301659
1660 ret = _sdw_disable_stream(stream);
1661 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001662 pr_err("Disable for stream:%s failed: %d\n", stream->name, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301663
Vinod Koul48949722018-07-27 14:44:14 +05301664 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301665 return ret;
1666}
1667EXPORT_SYMBOL(sdw_disable_stream);
1668
1669static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1670{
Vinod Koul48949722018-07-27 14:44:14 +05301671 struct sdw_master_runtime *m_rt = NULL;
1672 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301673 int ret = 0;
1674
Vinod Koul48949722018-07-27 14:44:14 +05301675 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1676 bus = m_rt->bus;
1677 /* De-prepare port(s) */
1678 ret = sdw_prep_deprep_ports(m_rt, false);
1679 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301680 dev_err(bus->dev,
1681 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301682 return ret;
1683 }
1684
1685 /* TODO: Update this during Device-Device support */
1686 bus->params.bandwidth -= m_rt->stream->params.rate *
1687 m_rt->ch_count * m_rt->stream->params.bps;
1688
1689 /* Program params */
1690 ret = sdw_program_params(bus);
1691 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001692 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301693 return ret;
1694 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301695 }
1696
1697 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301698 return do_bank_switch(stream);
1699}
1700
1701/**
1702 * sdw_deprepare_stream() - Deprepare SoundWire stream
1703 *
1704 * @stream: Soundwire stream
1705 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001706 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301707 */
1708int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1709{
1710 int ret = 0;
1711
1712 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001713 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301714 return -EINVAL;
1715 }
1716
Vinod Koul48949722018-07-27 14:44:14 +05301717 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301718 ret = _sdw_deprepare_stream(stream);
1719 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001720 pr_err("De-prepare for stream:%d failed: %d\n", ret, ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301721
Vinod Koul48949722018-07-27 14:44:14 +05301722 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301723 return ret;
1724}
1725EXPORT_SYMBOL(sdw_deprepare_stream);