blob: fc30a3e3df474f95be4f271fd78ea3439f41a696 [file] [log] [blame]
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04002 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00004 * Copyright (c) 2008 Marvell Semiconductor
5 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02006 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
Vivien Didelot4333d612017-03-28 15:10:36 -04008 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
Barry Grussling19b2f972013-01-08 16:05:54 +000017#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070018#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020019#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070020#include <linux/if_bridge.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020021#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000024#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000025#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020026#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000027#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040028#include <linux/of_device.h>
Andrew Lunndc30c352016-10-16 19:56:49 +020029#include <linux/of_irq.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020030#include <linux/of_mdio.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000031#include <linux/netdevice.h>
Andrew Lunnc8c1b39a2015-11-20 03:56:24 +010032#include <linux/gpio/consumer.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000033#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000034#include <net/dsa.h>
Vivien Didelot1f36faf2015-10-08 11:35:13 -040035#include <net/switchdev.h>
Vivien Didelotec561272016-09-02 14:45:33 -040036
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000037#include "mv88e6xxx.h"
Vivien Didelota935c052016-09-29 12:21:53 -040038#include "global1.h"
Vivien Didelotec561272016-09-02 14:45:33 -040039#include "global2.h"
Vivien Didelot18abed22016-11-04 03:23:26 +010040#include "port.h"
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000041
Vivien Didelotfad09c72016-06-21 12:28:20 -040042static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040043{
Vivien Didelotfad09c72016-06-21 12:28:20 -040044 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040046 dump_stack();
47 }
48}
49
Vivien Didelot914b32f2016-06-20 13:14:11 -040050/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000060 */
Vivien Didelot914b32f2016-06-20 13:14:11 -040061
Vivien Didelotfad09c72016-06-21 12:28:20 -040062static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040063 int addr, int reg, u16 *val)
64{
Vivien Didelotfad09c72016-06-21 12:28:20 -040065 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040066 return -EOPNOTSUPP;
67
Vivien Didelotfad09c72016-06-21 12:28:20 -040068 return chip->smi_ops->read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040069}
70
Vivien Didelotfad09c72016-06-21 12:28:20 -040071static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040072 int addr, int reg, u16 val)
73{
Vivien Didelotfad09c72016-06-21 12:28:20 -040074 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040075 return -EOPNOTSUPP;
76
Vivien Didelotfad09c72016-06-21 12:28:20 -040077 return chip->smi_ops->write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040078}
79
Vivien Didelotfad09c72016-06-21 12:28:20 -040080static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040081 int addr, int reg, u16 *val)
82{
83 int ret;
84
Vivien Didelotfad09c72016-06-21 12:28:20 -040085 ret = mdiobus_read_nested(chip->bus, addr, reg);
Vivien Didelot914b32f2016-06-20 13:14:11 -040086 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
Vivien Didelotfad09c72016-06-21 12:28:20 -040094static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040095 int addr, int reg, u16 val)
96{
97 int ret;
98
Vivien Didelotfad09c72016-06-21 12:28:20 -040099 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
Vivien Didelotc08026a2016-09-29 12:21:59 -0400106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
Vivien Didelot914b32f2016-06-20 13:14:11 -0400107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
Vivien Didelotfad09c72016-06-21 12:28:20 -0400111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000118 if (ret < 0)
119 return ret;
120
Andrew Lunncca8b132015-04-02 04:06:39 +0200121 if ((ret & SMI_CMD_BUSY) == 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
Vivien Didelotfad09c72016-06-21 12:28:20 -0400128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400129 int addr, int reg, u16 *val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000130{
131 int ret;
132
Barry Grussling3675c8d2013-01-08 16:05:53 +0000133 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000135 if (ret < 0)
136 return ret;
137
Barry Grussling3675c8d2013-01-08 16:05:53 +0000138 /* Transmit the read command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Neil Armstrong6e899e62015-10-22 10:37:53 +0200140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000141 if (ret < 0)
142 return ret;
143
Barry Grussling3675c8d2013-01-08 16:05:53 +0000144 /* Wait for the read command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000146 if (ret < 0)
147 return ret;
148
Barry Grussling3675c8d2013-01-08 16:05:53 +0000149 /* Read the data. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000151 if (ret < 0)
152 return ret;
153
Vivien Didelot914b32f2016-06-20 13:14:11 -0400154 *val = ret & 0xffff;
155
156 return 0;
157}
158
Vivien Didelotfad09c72016-06-21 12:28:20 -0400159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400160 int addr, int reg, u16 val)
161{
162 int ret;
163
164 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
Vivien Didelotc08026a2016-09-29 12:21:59 -0400188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
Vivien Didelot914b32f2016-06-20 13:14:11 -0400189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
Vivien Didelotec561272016-09-02 14:45:33 -0400193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
Vivien Didelot914b32f2016-06-20 13:14:11 -0400194{
195 int err;
196
Vivien Didelotfad09c72016-06-21 12:28:20 -0400197 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400198
Vivien Didelotfad09c72016-06-21 12:28:20 -0400199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400200 if (err)
201 return err;
202
Vivien Didelotfad09c72016-06-21 12:28:20 -0400203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400204 addr, reg, *val);
205
206 return 0;
207}
208
Vivien Didelotec561272016-09-02 14:45:33 -0400209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
Vivien Didelot914b32f2016-06-20 13:14:11 -0400210{
211 int err;
212
Vivien Didelotfad09c72016-06-21 12:28:20 -0400213 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400214
Vivien Didelotfad09c72016-06-21 12:28:20 -0400215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400216 if (err)
217 return err;
218
Vivien Didelotfad09c72016-06-21 12:28:20 -0400219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400220 addr, reg, val);
221
222 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000223}
224
Andrew Lunnee26a222017-01-24 14:53:48 +0100225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
Andrew Lunnefb3e742017-01-24 14:53:47 +0100228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
Andrew Lunnee26a222017-01-24 14:53:48 +0100232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
Andrew Lunnefb3e742017-01-24 14:53:47 +0100235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
Andrew Lunna3c53be52017-01-24 14:53:50 +0100239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
Vivien Didelote57e5e72016-08-15 17:19:00 -0400251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
Andrew Lunna3c53be52017-01-24 14:53:50 +0100255 struct mii_bus *bus;
Vivien Didelote57e5e72016-08-15 17:19:00 -0400256
Andrew Lunna3c53be52017-01-24 14:53:50 +0100257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
Vivien Didelote57e5e72016-08-15 17:19:00 -0400259 return -EOPNOTSUPP;
260
Andrew Lunna3c53be52017-01-24 14:53:50 +0100261 if (!chip->info->ops->phy_read)
Andrew Lunnee26a222017-01-24 14:53:48 +0100262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
Vivien Didelote57e5e72016-08-15 17:19:00 -0400265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
Andrew Lunna3c53be52017-01-24 14:53:50 +0100271 struct mii_bus *bus;
Vivien Didelote57e5e72016-08-15 17:19:00 -0400272
Andrew Lunna3c53be52017-01-24 14:53:50 +0100273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
Vivien Didelote57e5e72016-08-15 17:19:00 -0400275 return -EOPNOTSUPP;
276
Andrew Lunna3c53be52017-01-24 14:53:50 +0100277 if (!chip->info->ops->phy_write)
Andrew Lunnee26a222017-01-24 14:53:48 +0100278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
Vivien Didelote57e5e72016-08-15 17:19:00 -0400281}
282
Vivien Didelot09cb7df2016-08-15 17:19:01 -0400283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
Andrew Lunndc30c352016-10-16 19:56:49 +0200351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
Andrew Lunn3460a572016-11-20 20:14:16 +0100452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
Andrew Lunndc30c352016-10-16 19:56:49 +0200459
Andreas Färber5edef2f2016-11-27 23:26:28 +0100460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
Andrew Lunna3db3d32016-11-20 20:14:14 +0100461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
Andrew Lunndc30c352016-10-16 19:56:49 +0200462 irq_dispose_mapping(virq);
463 }
464
Andrew Lunna3db3d32016-11-20 20:14:14 +0100465 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100470 int err, irq, virq;
471 u16 reg, mask;
Andrew Lunndc30c352016-10-16 19:56:49 +0200472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200487 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100488 goto out_mapping;
Andrew Lunndc30c352016-10-16 19:56:49 +0200489
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
Andrew Lunndc30c352016-10-16 19:56:49 +0200491
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
Andrew Lunndc30c352016-10-16 19:56:49 +0200493 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100494 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100499 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100506 goto out_disable;
Andrew Lunndc30c352016-10-16 19:56:49 +0200507
508 return 0;
509
Andrew Lunn3dd0ef02016-11-20 20:14:17 +0100510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
Andrew Lunndc30c352016-10-16 19:56:49 +0200521
522 return err;
523}
524
Vivien Didelotec561272016-09-02 14:45:33 -0400525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
Vivien Didelot2d79af62016-08-15 17:18:57 -0400526{
Andrew Lunn6441e6692016-08-19 00:01:55 +0200527 int i;
Vivien Didelot2d79af62016-08-15 17:18:57 -0400528
Andrew Lunn6441e6692016-08-19 00:01:55 +0200529 for (i = 0; i < 16; i++) {
Vivien Didelot2d79af62016-08-15 17:18:57 -0400530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
Andrew Lunn30853552016-08-19 00:01:57 +0200543 dev_err(chip->dev, "Timeout while waiting for switch\n");
Vivien Didelot2d79af62016-08-15 17:18:57 -0400544 return -ETIMEDOUT;
545}
546
Vivien Didelotf22ab642016-07-18 20:45:31 -0400547/* Indirect write to single pointer-data register with an Update bit */
Vivien Didelotec561272016-09-02 14:45:33 -0400548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
Vivien Didelotf22ab642016-07-18 20:45:31 -0400549{
550 u16 val;
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200551 int err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400552
553 /* Wait until the previous operation is completed */
Andrew Lunn0f02b4f2016-08-19 00:01:56 +0200554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
Vivien Didelotf22ab642016-07-18 20:45:31 -0400557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
Vivien Didelota935c052016-09-29 12:21:53 -0400564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000565{
Vivien Didelota199d8b2016-12-05 17:30:28 -0500566 if (!chip->info->ops->ppu_disable)
567 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000568
Vivien Didelota199d8b2016-12-05 17:30:28 -0500569 return chip->info->ops->ppu_disable(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000570}
571
Vivien Didelotfad09c72016-06-21 12:28:20 -0400572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000573{
Vivien Didelota199d8b2016-12-05 17:30:28 -0500574 if (!chip->info->ops->ppu_enable)
575 return 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000576
Vivien Didelota199d8b2016-12-05 17:30:28 -0500577 return chip->info->ops->ppu_enable(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400582 struct mv88e6xxx_chip *chip;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000583
Vivien Didelotfad09c72016-06-21 12:28:20 -0400584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
Vivien Didelot762eb672016-06-04 21:16:54 +0200585
Vivien Didelotfad09c72016-06-21 12:28:20 -0400586 mutex_lock(&chip->reg_lock);
Vivien Didelot762eb672016-06-04 21:16:54 +0200587
Vivien Didelotfad09c72016-06-21 12:28:20 -0400588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000592 }
Vivien Didelot762eb672016-06-04 21:16:54 +0200593
Vivien Didelotfad09c72016-06-21 12:28:20 -0400594 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400599 struct mv88e6xxx_chip *chip = (void *)_ps;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000600
Vivien Didelotfad09c72016-06-21 12:28:20 -0400601 schedule_work(&chip->ppu_work);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000602}
603
Vivien Didelotfad09c72016-06-21 12:28:20 -0400604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000605{
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000606 int ret;
607
Vivien Didelotfad09c72016-06-21 12:28:20 -0400608 mutex_lock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000609
Barry Grussling3675c8d2013-01-08 16:05:53 +0000610 /* If the PHY polling unit is enabled, disable it so that
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
Barry Grussling85686582013-01-08 16:05:56 +0000617 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400618 mutex_unlock(&chip->ppu_mutex);
Barry Grussling85686582013-01-08 16:05:56 +0000619 return ret;
620 }
Vivien Didelotfad09c72016-06-21 12:28:20 -0400621 chip->ppu_disabled = 1;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000622 } else {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400623 del_timer(&chip->ppu_timer);
Barry Grussling85686582013-01-08 16:05:56 +0000624 ret = 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000625 }
626
627 return ret;
628}
629
Vivien Didelotfad09c72016-06-21 12:28:20 -0400630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000631{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000632 /* Schedule a timer to re-enable the PHY polling unit. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000635}
636
Vivien Didelotfad09c72016-06-21 12:28:20 -0400637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000638{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
Wei Yongjun68497a82016-10-22 14:28:00 +0000641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000643}
644
Andrew Lunn930188c2016-08-22 16:01:03 +0200645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
Andrew Lunnee26a222017-01-24 14:53:48 +0100650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000653{
Vivien Didelote57e5e72016-08-15 17:19:00 -0400654 int err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000655
Vivien Didelote57e5e72016-08-15 17:19:00 -0400656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400659 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000660 }
661
Vivien Didelote57e5e72016-08-15 17:19:00 -0400662 return err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000663}
664
Andrew Lunnee26a222017-01-24 14:53:48 +0100665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000668{
Vivien Didelote57e5e72016-08-15 17:19:00 -0400669 int err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000670
Vivien Didelote57e5e72016-08-15 17:19:00 -0400671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400674 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000675 }
676
Vivien Didelote57e5e72016-08-15 17:19:00 -0400677 return err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000678}
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000679
Vivien Didelotd78343d2016-11-04 03:23:36 +0100680static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
681 int link, int speed, int duplex,
682 phy_interface_t mode)
683{
684 int err;
685
686 if (!chip->info->ops->port_set_link)
687 return 0;
688
689 /* Port's MAC control must not be changed unless the link is down */
690 err = chip->info->ops->port_set_link(chip, port, 0);
691 if (err)
692 return err;
693
694 if (chip->info->ops->port_set_speed) {
695 err = chip->info->ops->port_set_speed(chip, port, speed);
696 if (err && err != -EOPNOTSUPP)
697 goto restore_link;
698 }
699
700 if (chip->info->ops->port_set_duplex) {
701 err = chip->info->ops->port_set_duplex(chip, port, duplex);
702 if (err && err != -EOPNOTSUPP)
703 goto restore_link;
704 }
705
706 if (chip->info->ops->port_set_rgmii_delay) {
707 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
708 if (err && err != -EOPNOTSUPP)
709 goto restore_link;
710 }
711
Andrew Lunnf39908d2017-02-04 20:02:50 +0100712 if (chip->info->ops->port_set_cmode) {
713 err = chip->info->ops->port_set_cmode(chip, port, mode);
714 if (err && err != -EOPNOTSUPP)
715 goto restore_link;
716 }
717
Vivien Didelotd78343d2016-11-04 03:23:36 +0100718 err = 0;
719restore_link:
720 if (chip->info->ops->port_set_link(chip, port, link))
721 netdev_err(chip->ds->ports[port].netdev,
722 "failed to restore MAC's link\n");
723
724 return err;
725}
726
Andrew Lunndea87022015-08-31 15:56:47 +0200727/* We expect the switch to perform auto negotiation if there is a real
728 * phy. However, in the case of a fixed link phy, we force the port
729 * settings from the fixed link settings.
730 */
Vivien Didelotf81ec902016-05-09 13:22:58 -0400731static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
732 struct phy_device *phydev)
Andrew Lunndea87022015-08-31 15:56:47 +0200733{
Vivien Didelot04bed142016-08-31 18:06:13 -0400734 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200735 int err;
Andrew Lunndea87022015-08-31 15:56:47 +0200736
737 if (!phy_is_pseudo_fixed_link(phydev))
738 return;
739
Vivien Didelotfad09c72016-06-21 12:28:20 -0400740 mutex_lock(&chip->reg_lock);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100741 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
742 phydev->duplex, phydev->interface);
Vivien Didelotfad09c72016-06-21 12:28:20 -0400743 mutex_unlock(&chip->reg_lock);
Vivien Didelotd78343d2016-11-04 03:23:36 +0100744
745 if (err && err != -EOPNOTSUPP)
746 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
Andrew Lunndea87022015-08-31 15:56:47 +0200747}
748
Andrew Lunna605a0f2016-11-21 23:26:58 +0100749static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000750{
Andrew Lunna605a0f2016-11-21 23:26:58 +0100751 if (!chip->info->ops->stats_snapshot)
752 return -EOPNOTSUPP;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000753
Andrew Lunna605a0f2016-11-21 23:26:58 +0100754 return chip->info->ops->stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000755}
756
Andrew Lunne413e7e2015-04-02 04:06:38 +0200757static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunndfafe442016-11-21 23:27:02 +0100758 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
759 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
760 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
761 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
762 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
763 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
764 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
765 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
766 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
767 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
768 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
769 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
770 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
771 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
772 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
773 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
774 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
775 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
776 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
777 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
778 { "single", 4, 0x14, STATS_TYPE_BANK0, },
779 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
780 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
781 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
782 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
783 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
784 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
785 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
786 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
787 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
788 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
789 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
790 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
791 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
792 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
793 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
794 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
795 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
796 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
797 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
798 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
799 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
800 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
801 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
802 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
803 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
804 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
805 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
806 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
807 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
808 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
809 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
810 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
811 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
812 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
813 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
814 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
815 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
816 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200817};
818
Vivien Didelotfad09c72016-06-21 12:28:20 -0400819static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100820 struct mv88e6xxx_hw_stat *s,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100821 int port, u16 bank1_select,
822 u16 histogram)
Andrew Lunn80c46272015-06-20 18:42:30 +0200823{
Andrew Lunn80c46272015-06-20 18:42:30 +0200824 u32 low;
825 u32 high = 0;
Andrew Lunndfafe442016-11-21 23:27:02 +0100826 u16 reg = 0;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200827 int err;
Andrew Lunn80c46272015-06-20 18:42:30 +0200828 u64 value;
829
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100830 switch (s->type) {
Andrew Lunndfafe442016-11-21 23:27:02 +0100831 case STATS_TYPE_PORT:
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200832 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
833 if (err)
Andrew Lunn80c46272015-06-20 18:42:30 +0200834 return UINT64_MAX;
835
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200836 low = reg;
Andrew Lunn80c46272015-06-20 18:42:30 +0200837 if (s->sizeof_stat == 4) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200838 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
839 if (err)
Andrew Lunn80c46272015-06-20 18:42:30 +0200840 return UINT64_MAX;
Andrew Lunn0e7b9922016-09-21 01:40:31 +0200841 high = reg;
Andrew Lunn80c46272015-06-20 18:42:30 +0200842 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100843 break;
Andrew Lunndfafe442016-11-21 23:27:02 +0100844 case STATS_TYPE_BANK1:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100845 reg = bank1_select;
Andrew Lunndfafe442016-11-21 23:27:02 +0100846 /* fall through */
847 case STATS_TYPE_BANK0:
Andrew Lunne0d8b612016-11-21 23:27:04 +0100848 reg |= s->reg | histogram;
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100849 mv88e6xxx_g1_stats_read(chip, reg, &low);
Andrew Lunn80c46272015-06-20 18:42:30 +0200850 if (s->sizeof_stat == 8)
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100851 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
Andrew Lunn80c46272015-06-20 18:42:30 +0200852 }
853 value = (((u64)high) << 16) | low;
854 return value;
855}
856
Andrew Lunndfafe442016-11-21 23:27:02 +0100857static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
858 uint8_t *data, int types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100859{
860 struct mv88e6xxx_hw_stat *stat;
861 int i, j;
862
863 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
864 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100865 if (stat->type & types) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100866 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
867 ETH_GSTRING_LEN);
868 j++;
869 }
870 }
871}
872
Andrew Lunndfafe442016-11-21 23:27:02 +0100873static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
874 uint8_t *data)
875{
876 mv88e6xxx_stats_get_strings(chip, data,
877 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
878}
879
880static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
881 uint8_t *data)
882{
883 mv88e6xxx_stats_get_strings(chip, data,
884 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
885}
886
887static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
888 uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100889{
Vivien Didelot04bed142016-08-31 18:06:13 -0400890 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunndfafe442016-11-21 23:27:02 +0100891
892 if (chip->info->ops->stats_get_strings)
893 chip->info->ops->stats_get_strings(chip, data);
894}
895
896static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
897 int types)
898{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100899 struct mv88e6xxx_hw_stat *stat;
900 int i, j;
901
902 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
903 stat = &mv88e6xxx_hw_stats[i];
Andrew Lunndfafe442016-11-21 23:27:02 +0100904 if (stat->type & types)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100905 j++;
906 }
907 return j;
908}
909
Andrew Lunndfafe442016-11-21 23:27:02 +0100910static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
911{
912 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
913 STATS_TYPE_PORT);
914}
915
916static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
917{
918 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
919 STATS_TYPE_BANK1);
920}
921
922static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
923{
924 struct mv88e6xxx_chip *chip = ds->priv;
925
926 if (chip->info->ops->stats_get_sset_count)
927 return chip->info->ops->stats_get_sset_count(chip);
928
929 return 0;
930}
931
Andrew Lunn052f9472016-11-21 23:27:03 +0100932static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100933 uint64_t *data, int types,
934 u16 bank1_select, u16 histogram)
Andrew Lunn052f9472016-11-21 23:27:03 +0100935{
936 struct mv88e6xxx_hw_stat *stat;
937 int i, j;
938
939 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
940 stat = &mv88e6xxx_hw_stats[i];
941 if (stat->type & types) {
Andrew Lunne0d8b612016-11-21 23:27:04 +0100942 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
943 bank1_select,
944 histogram);
Andrew Lunn052f9472016-11-21 23:27:03 +0100945 j++;
946 }
947 }
948}
949
950static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
951 uint64_t *data)
952{
953 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100954 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
955 0, GLOBAL_STATS_OP_HIST_RX_TX);
Andrew Lunn052f9472016-11-21 23:27:03 +0100956}
957
958static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
959 uint64_t *data)
960{
961 return mv88e6xxx_stats_get_stats(chip, port, data,
Andrew Lunne0d8b612016-11-21 23:27:04 +0100962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
963 GLOBAL_STATS_OP_BANK_1_BIT_9,
964 GLOBAL_STATS_OP_HIST_RX_TX);
965}
966
967static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
968 uint64_t *data)
969{
970 return mv88e6xxx_stats_get_stats(chip, port, data,
971 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
972 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
Andrew Lunn052f9472016-11-21 23:27:03 +0100973}
974
975static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
976 uint64_t *data)
977{
978 if (chip->info->ops->stats_get_stats)
979 chip->info->ops->stats_get_stats(chip, port, data);
980}
981
Vivien Didelotf81ec902016-05-09 13:22:58 -0400982static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
983 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000984{
Vivien Didelot04bed142016-08-31 18:06:13 -0400985 struct mv88e6xxx_chip *chip = ds->priv;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000986 int ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000987
Vivien Didelotfad09c72016-06-21 12:28:20 -0400988 mutex_lock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000989
Andrew Lunna605a0f2016-11-21 23:26:58 +0100990 ret = mv88e6xxx_stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000991 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400992 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000993 return;
994 }
Andrew Lunn052f9472016-11-21 23:27:03 +0100995
996 mv88e6xxx_get_stats(chip, port, data);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000997
Vivien Didelotfad09c72016-06-21 12:28:20 -0400998 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000999}
Ben Hutchings98e67302011-11-25 14:36:19 +00001000
Andrew Lunnde2273872016-11-21 23:27:01 +01001001static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1002{
1003 if (chip->info->ops->stats_set_histogram)
1004 return chip->info->ops->stats_set_histogram(chip);
1005
1006 return 0;
1007}
1008
Vivien Didelotf81ec902016-05-09 13:22:58 -04001009static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001010{
1011 return 32 * sizeof(u16);
1012}
1013
Vivien Didelotf81ec902016-05-09 13:22:58 -04001014static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1015 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001016{
Vivien Didelot04bed142016-08-31 18:06:13 -04001017 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001018 int err;
1019 u16 reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001020 u16 *p = _p;
1021 int i;
1022
1023 regs->version = 0;
1024
1025 memset(p, 0xff, 32 * sizeof(u16));
1026
Vivien Didelotfad09c72016-06-21 12:28:20 -04001027 mutex_lock(&chip->reg_lock);
Vivien Didelot23062512016-05-09 13:22:45 -04001028
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001029 for (i = 0; i < 32; i++) {
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001030
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001031 err = mv88e6xxx_port_read(chip, port, i, &reg);
1032 if (!err)
1033 p[i] = reg;
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001034 }
Vivien Didelot23062512016-05-09 13:22:45 -04001035
Vivien Didelotfad09c72016-06-21 12:28:20 -04001036 mutex_unlock(&chip->reg_lock);
Guenter Roecka1ab91f2014-10-29 10:45:05 -07001037}
1038
Vivien Didelotf81ec902016-05-09 13:22:58 -04001039static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1040 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001041{
Vivien Didelot04bed142016-08-31 18:06:13 -04001042 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot9c938292016-08-15 17:19:02 -04001043 u16 reg;
1044 int err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001045
Vivien Didelotfad09c72016-06-21 12:28:20 -04001046 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001047 return -EOPNOTSUPP;
1048
Vivien Didelotfad09c72016-06-21 12:28:20 -04001049 mutex_lock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001050
Vivien Didelot9c938292016-08-15 17:19:02 -04001051 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1052 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001053 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001054
1055 e->eee_enabled = !!(reg & 0x0200);
1056 e->tx_lpi_enabled = !!(reg & 0x0100);
1057
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001058 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
Vivien Didelot9c938292016-08-15 17:19:02 -04001059 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001060 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001061
Andrew Lunncca8b132015-04-02 04:06:39 +02001062 e->eee_active = !!(reg & PORT_STATUS_EEE);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001063out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001064 mutex_unlock(&chip->reg_lock);
Vivien Didelot9c938292016-08-15 17:19:02 -04001065
1066 return err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001067}
1068
Vivien Didelotf81ec902016-05-09 13:22:58 -04001069static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1070 struct phy_device *phydev, struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001071{
Vivien Didelot04bed142016-08-31 18:06:13 -04001072 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot9c938292016-08-15 17:19:02 -04001073 u16 reg;
1074 int err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001075
Vivien Didelotfad09c72016-06-21 12:28:20 -04001076 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001077 return -EOPNOTSUPP;
1078
Vivien Didelotfad09c72016-06-21 12:28:20 -04001079 mutex_lock(&chip->reg_lock);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001080
Vivien Didelot9c938292016-08-15 17:19:02 -04001081 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1082 if (err)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001083 goto out;
1084
Vivien Didelot9c938292016-08-15 17:19:02 -04001085 reg &= ~0x0300;
Andrew Lunn2f40c692015-04-02 04:06:37 +02001086 if (e->eee_enabled)
1087 reg |= 0x0200;
1088 if (e->tx_lpi_enabled)
1089 reg |= 0x0100;
1090
Vivien Didelot9c938292016-08-15 17:19:02 -04001091 err = mv88e6xxx_phy_write(chip, port, 16, reg);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001092out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001093 mutex_unlock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001094
Vivien Didelot9c938292016-08-15 17:19:02 -04001095 return err;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001096}
1097
Vivien Didelote5887a22017-03-30 17:37:11 -04001098static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001099{
Vivien Didelote5887a22017-03-30 17:37:11 -04001100 struct dsa_switch *ds = NULL;
1101 struct net_device *br;
1102 u16 pvlan;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001103 int i;
1104
Vivien Didelote5887a22017-03-30 17:37:11 -04001105 if (dev < DSA_MAX_SWITCHES)
1106 ds = chip->ds->dst->ds[dev];
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001107
Vivien Didelote5887a22017-03-30 17:37:11 -04001108 /* Prevent frames from unknown switch or port */
1109 if (!ds || port >= ds->num_ports)
1110 return 0;
1111
1112 /* Frames from DSA links and CPU ports can egress any local port */
1113 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1114 return mv88e6xxx_port_mask(chip);
1115
1116 br = ds->ports[port].bridge_dev;
1117 pvlan = 0;
1118
1119 /* Frames from user ports can egress any local DSA links and CPU ports,
1120 * as well as any local member of their bridge group.
1121 */
1122 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1123 if (dsa_is_cpu_port(chip->ds, i) ||
1124 dsa_is_dsa_port(chip->ds, i) ||
1125 (br && chip->ds->ports[i].bridge_dev == br))
1126 pvlan |= BIT(i);
1127
1128 return pvlan;
1129}
1130
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001131static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
Vivien Didelote5887a22017-03-30 17:37:11 -04001132{
1133 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001134
1135 /* prevent frames from going back out of the port they came in on */
1136 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001137
Vivien Didelot5a7921f2016-11-04 03:23:28 +01001138 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001139}
1140
Vivien Didelotf81ec902016-05-09 13:22:58 -04001141static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1142 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001143{
Vivien Didelot04bed142016-08-31 18:06:13 -04001144 struct mv88e6xxx_chip *chip = ds->priv;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001145 int stp_state;
Vivien Didelot553eb542016-05-13 20:38:23 -04001146 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001147
1148 switch (state) {
1149 case BR_STATE_DISABLED:
Andrew Lunncca8b132015-04-02 04:06:39 +02001150 stp_state = PORT_CONTROL_STATE_DISABLED;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001151 break;
1152 case BR_STATE_BLOCKING:
1153 case BR_STATE_LISTENING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001154 stp_state = PORT_CONTROL_STATE_BLOCKING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001155 break;
1156 case BR_STATE_LEARNING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001157 stp_state = PORT_CONTROL_STATE_LEARNING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001158 break;
1159 case BR_STATE_FORWARDING:
1160 default:
Andrew Lunncca8b132015-04-02 04:06:39 +02001161 stp_state = PORT_CONTROL_STATE_FORWARDING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001162 break;
1163 }
1164
Vivien Didelotfad09c72016-06-21 12:28:20 -04001165 mutex_lock(&chip->reg_lock);
Vivien Didelote28def332016-11-04 03:23:27 +01001166 err = mv88e6xxx_port_set_state(chip, port, stp_state);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001167 mutex_unlock(&chip->reg_lock);
Vivien Didelot553eb542016-05-13 20:38:23 -04001168
1169 if (err)
Vivien Didelote28def332016-11-04 03:23:27 +01001170 netdev_err(ds->ports[port].netdev, "failed to update state\n");
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001171}
1172
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001173static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1174{
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001175 int err;
1176
Vivien Didelotdaefc942017-03-11 16:12:54 -05001177 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1178 if (err)
1179 return err;
1180
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -05001181 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1182 if (err)
1183 return err;
1184
Vivien Didelota2ac29d2017-03-11 16:12:49 -05001185 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1186}
1187
Vivien Didelot17a15942017-03-30 17:37:09 -04001188static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1189{
1190 u16 pvlan = 0;
1191
1192 if (!mv88e6xxx_has_pvt(chip))
1193 return -EOPNOTSUPP;
1194
1195 /* Skip the local source device, which uses in-chip port VLAN */
1196 if (dev != chip->ds->index)
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001197 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
Vivien Didelot17a15942017-03-30 17:37:09 -04001198
1199 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1200}
1201
Vivien Didelot81228992017-03-30 17:37:08 -04001202static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1203{
Vivien Didelot17a15942017-03-30 17:37:09 -04001204 int dev, port;
1205 int err;
1206
Vivien Didelot81228992017-03-30 17:37:08 -04001207 if (!mv88e6xxx_has_pvt(chip))
1208 return 0;
1209
1210 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1211 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1212 */
Vivien Didelot17a15942017-03-30 17:37:09 -04001213 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1214 if (err)
1215 return err;
1216
1217 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1218 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1219 err = mv88e6xxx_pvt_map(chip, dev, port);
1220 if (err)
1221 return err;
1222 }
1223 }
1224
1225 return 0;
Vivien Didelot81228992017-03-30 17:37:08 -04001226}
1227
Vivien Didelot749efcb2016-09-22 16:49:24 -04001228static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1229{
1230 struct mv88e6xxx_chip *chip = ds->priv;
1231 int err;
1232
1233 mutex_lock(&chip->reg_lock);
Vivien Didelote606ca32017-03-11 16:12:55 -05001234 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
Vivien Didelot749efcb2016-09-22 16:49:24 -04001235 mutex_unlock(&chip->reg_lock);
1236
1237 if (err)
1238 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1239}
1240
Vivien Didelotfad09c72016-06-21 12:28:20 -04001241static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001242 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelotb8fee952015-08-13 12:52:19 -04001243{
Vivien Didelotf169e5e2017-05-01 14:05:17 -04001244 struct mv88e6xxx_vtu_entry next = *entry;
Vivien Didelota935c052016-09-29 12:21:53 -04001245 u16 val;
1246 int err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001247
Vivien Didelotf169e5e2017-05-01 14:05:17 -04001248 err = mv88e6xxx_g1_vtu_getnext(chip, &next);
Vivien Didelota935c052016-09-29 12:21:53 -04001249 if (err)
1250 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001251
Vivien Didelotb8fee952015-08-13 12:52:19 -04001252 if (next.valid) {
Vivien Didelot6dc10bb2016-09-29 12:21:55 -04001253 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
Vivien Didelot8ee51f62017-05-01 14:05:14 -04001254 err = mv88e6xxx_g1_vtu_fid_read(chip, &next);
Vivien Didelota935c052016-09-29 12:21:53 -04001255 if (err)
1256 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001257 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001258 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1259 * VTU DBNum[3:0] are located in VTU Operation 3:0
1260 */
Vivien Didelota935c052016-09-29 12:21:53 -04001261 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1262 if (err)
1263 return err;
Vivien Didelot11ea8092016-03-31 16:53:44 -04001264
Vivien Didelota935c052016-09-29 12:21:53 -04001265 next.fid = (val & 0xf00) >> 4;
1266 next.fid |= val & 0xf;
Vivien Didelot2e7bd5e2016-03-31 16:53:41 -04001267 }
Vivien Didelotb8fee952015-08-13 12:52:19 -04001268
Vivien Didelotfad09c72016-06-21 12:28:20 -04001269 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
Vivien Didelotef6fcea2017-05-01 14:05:20 -04001270 err = mv88e6xxx_g1_vtu_stu_get(chip, &next);
Vivien Didelota935c052016-09-29 12:21:53 -04001271 if (err)
1272 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001273 }
Vivien Didelotc499a642017-05-01 14:05:18 -04001274
1275 err = mv88e6185_g1_vtu_data_read(chip, &next);
1276 if (err)
1277 return err;
Vivien Didelotb8fee952015-08-13 12:52:19 -04001278 }
1279
1280 *entry = next;
1281 return 0;
1282}
1283
Vivien Didelotb486d7c2017-05-01 14:05:13 -04001284static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1285{
1286 if (!chip->info->max_vid)
1287 return 0;
1288
1289 return mv88e6xxx_g1_vtu_flush(chip);
1290}
1291
Vivien Didelotf81ec902016-05-09 13:22:58 -04001292static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1293 struct switchdev_obj_port_vlan *vlan,
1294 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001295{
Vivien Didelot04bed142016-08-31 18:06:13 -04001296 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001297 struct mv88e6xxx_vtu_entry next = {
1298 .vid = chip->info->max_vid,
1299 };
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001300 u16 pvid;
1301 int err;
1302
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001303 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001304 return -EOPNOTSUPP;
1305
Vivien Didelotfad09c72016-06-21 12:28:20 -04001306 mutex_lock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001307
Vivien Didelot77064f32016-11-04 03:23:30 +01001308 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001309 if (err)
1310 goto unlock;
1311
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001312 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001313 err = _mv88e6xxx_vtu_getnext(chip, &next);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001314 if (err)
1315 break;
1316
1317 if (!next.valid)
1318 break;
1319
Vivien Didelotbd00e052017-05-01 14:05:11 -04001320 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001321 continue;
1322
1323 /* reinit and dump this VLAN obj */
Vivien Didelot57d32312016-06-20 13:13:58 -04001324 vlan->vid_begin = next.vid;
1325 vlan->vid_end = next.vid;
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001326 vlan->flags = 0;
1327
Vivien Didelotbd00e052017-05-01 14:05:11 -04001328 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001329 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1330
1331 if (next.vid == pvid)
1332 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1333
1334 err = cb(&vlan->obj);
1335 if (err)
1336 break;
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001337 } while (next.vid < chip->info->max_vid);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001338
1339unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001340 mutex_unlock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001341
1342 return err;
1343}
1344
Vivien Didelotfad09c72016-06-21 12:28:20 -04001345static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001346 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001347{
Vivien Didelot11ea8092016-03-31 16:53:44 -04001348 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
Vivien Didelota935c052016-09-29 12:21:53 -04001349 int err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001350
Vivien Didelot332aa5c2017-05-01 14:05:12 -04001351 err = mv88e6xxx_g1_vtu_op_wait(chip);
Vivien Didelota935c052016-09-29 12:21:53 -04001352 if (err)
1353 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001354
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001355 err = mv88e6xxx_g1_vtu_vid_write(chip, entry);
1356 if (err)
1357 return err;
1358
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001359 if (!entry->valid)
1360 goto loadpurge;
1361
1362 /* Write port member tags */
Vivien Didelotc499a642017-05-01 14:05:18 -04001363 err = mv88e6185_g1_vtu_data_write(chip, entry);
Vivien Didelota935c052016-09-29 12:21:53 -04001364 if (err)
1365 return err;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001366
Vivien Didelotfad09c72016-06-21 12:28:20 -04001367 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
Vivien Didelotd2ca1ea2017-05-01 14:05:15 -04001368 err = mv88e6xxx_g1_vtu_sid_write(chip, entry);
Vivien Didelota935c052016-09-29 12:21:53 -04001369 if (err)
1370 return err;
Vivien Didelot021e64f2017-05-01 14:05:21 -04001371
1372 err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1373 if (err)
1374 return err;
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001375 }
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001376
Vivien Didelot6dc10bb2016-09-29 12:21:55 -04001377 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
Vivien Didelot8ee51f62017-05-01 14:05:14 -04001378 err = mv88e6xxx_g1_vtu_fid_write(chip, entry);
Vivien Didelota935c052016-09-29 12:21:53 -04001379 if (err)
1380 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001381 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001382 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1383 * VTU DBNum[3:0] are located in VTU Operation 3:0
1384 */
1385 op |= (entry->fid & 0xf0) << 8;
1386 op |= entry->fid & 0xf;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001387 }
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001388loadpurge:
Vivien Didelot332aa5c2017-05-01 14:05:12 -04001389 return mv88e6xxx_g1_vtu_op(chip, op);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001390}
1391
Vivien Didelotd7f435f2017-03-11 16:12:56 -05001392static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001393{
1394 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001395 struct mv88e6xxx_vtu_entry vlan = {
1396 .vid = chip->info->max_vid,
1397 };
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001398 int i, err;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001399
1400 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1401
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001402 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001403 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001404 err = mv88e6xxx_port_get_fid(chip, i, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001405 if (err)
1406 return err;
1407
1408 set_bit(*fid, fid_bitmap);
1409 }
1410
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001411 /* Set every FID bit used by the VLAN entries */
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001412 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001413 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001414 if (err)
1415 return err;
1416
1417 if (!vlan.valid)
1418 break;
1419
1420 set_bit(vlan.fid, fid_bitmap);
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001421 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001422
1423 /* The reset value 0x000 is used to indicate that multiple address
1424 * databases are not needed. Return the next positive available.
1425 */
1426 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001427 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001428 return -ENOSPC;
1429
1430 /* Clear the database */
Vivien Didelotdaefc942017-03-11 16:12:54 -05001431 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001432}
1433
Vivien Didelotfad09c72016-06-21 12:28:20 -04001434static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001435 struct mv88e6xxx_vtu_entry *entry)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001436{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001437 struct dsa_switch *ds = chip->ds;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001438 struct mv88e6xxx_vtu_entry vlan = {
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001439 .valid = true,
1440 .vid = vid,
1441 };
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001442 int i, err;
1443
Vivien Didelotd7f435f2017-03-11 16:12:56 -05001444 err = mv88e6xxx_atu_new(chip, &vlan.fid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001445 if (err)
1446 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001447
Vivien Didelot3d131f02015-11-03 10:52:52 -05001448 /* exclude all ports except the CPU and DSA ports */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001449 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
Vivien Didelotbd00e052017-05-01 14:05:11 -04001450 vlan.member[i] = dsa_is_cpu_port(ds, i) ||
1451 dsa_is_dsa_port(ds, i)
Vivien Didelot3d131f02015-11-03 10:52:52 -05001452 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1453 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001454
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001455 *entry = vlan;
1456 return 0;
1457}
1458
Vivien Didelotfad09c72016-06-21 12:28:20 -04001459static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001460 struct mv88e6xxx_vtu_entry *entry, bool creat)
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001461{
1462 int err;
1463
1464 if (!vid)
1465 return -EINVAL;
1466
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001467 entry->vid = vid - 1;
1468 entry->valid = false;
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001469
Vivien Didelotfad09c72016-06-21 12:28:20 -04001470 err = _mv88e6xxx_vtu_getnext(chip, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001471 if (err)
1472 return err;
1473
1474 if (entry->vid != vid || !entry->valid) {
1475 if (!creat)
1476 return -EOPNOTSUPP;
1477 /* -ENOENT would've been more appropriate, but switchdev expects
1478 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1479 */
1480
Vivien Didelotfad09c72016-06-21 12:28:20 -04001481 err = _mv88e6xxx_vtu_new(chip, vid, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001482 }
1483
1484 return err;
1485}
1486
Vivien Didelotda9c3592016-02-12 12:09:40 -05001487static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1488 u16 vid_begin, u16 vid_end)
1489{
Vivien Didelot04bed142016-08-31 18:06:13 -04001490 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot3afb4bd2017-05-01 14:05:16 -04001491 struct mv88e6xxx_vtu_entry vlan = {
1492 .vid = vid_begin - 1,
1493 };
Vivien Didelotda9c3592016-02-12 12:09:40 -05001494 int i, err;
1495
1496 if (!vid_begin)
1497 return -EOPNOTSUPP;
1498
Vivien Didelotfad09c72016-06-21 12:28:20 -04001499 mutex_lock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001500
Vivien Didelotda9c3592016-02-12 12:09:40 -05001501 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001502 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001503 if (err)
1504 goto unlock;
1505
1506 if (!vlan.valid)
1507 break;
1508
1509 if (vlan.vid > vid_end)
1510 break;
1511
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001512 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelotda9c3592016-02-12 12:09:40 -05001513 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1514 continue;
1515
Andrew Lunn66e28092016-12-11 21:07:19 +01001516 if (!ds->ports[port].netdev)
1517 continue;
1518
Vivien Didelotbd00e052017-05-01 14:05:11 -04001519 if (vlan.member[i] ==
Vivien Didelotda9c3592016-02-12 12:09:40 -05001520 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1521 continue;
1522
Vivien Didelotfae8a252017-01-27 15:29:42 -05001523 if (ds->ports[i].bridge_dev ==
1524 ds->ports[port].bridge_dev)
Vivien Didelotda9c3592016-02-12 12:09:40 -05001525 break; /* same bridge, check next VLAN */
1526
Vivien Didelotfae8a252017-01-27 15:29:42 -05001527 if (!ds->ports[i].bridge_dev)
Andrew Lunn66e28092016-12-11 21:07:19 +01001528 continue;
1529
Andrew Lunnc8b09802016-06-04 21:16:57 +02001530 netdev_warn(ds->ports[port].netdev,
Vivien Didelotda9c3592016-02-12 12:09:40 -05001531 "hardware VLAN %d already used by %s\n",
1532 vlan.vid,
Vivien Didelotfae8a252017-01-27 15:29:42 -05001533 netdev_name(ds->ports[i].bridge_dev));
Vivien Didelotda9c3592016-02-12 12:09:40 -05001534 err = -EOPNOTSUPP;
1535 goto unlock;
1536 }
1537 } while (vlan.vid < vid_end);
1538
1539unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001540 mutex_unlock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05001541
1542 return err;
1543}
1544
Vivien Didelotf81ec902016-05-09 13:22:58 -04001545static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1546 bool vlan_filtering)
Vivien Didelot214cdb92016-02-26 13:16:08 -05001547{
Vivien Didelot04bed142016-08-31 18:06:13 -04001548 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot385a0992016-11-04 03:23:31 +01001549 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
Vivien Didelot214cdb92016-02-26 13:16:08 -05001550 PORT_CONTROL_2_8021Q_DISABLED;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001551 int err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001552
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001553 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001554 return -EOPNOTSUPP;
1555
Vivien Didelotfad09c72016-06-21 12:28:20 -04001556 mutex_lock(&chip->reg_lock);
Vivien Didelot385a0992016-11-04 03:23:31 +01001557 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001558 mutex_unlock(&chip->reg_lock);
Vivien Didelot214cdb92016-02-26 13:16:08 -05001559
Andrew Lunn0e7b9922016-09-21 01:40:31 +02001560 return err;
Vivien Didelot214cdb92016-02-26 13:16:08 -05001561}
1562
Vivien Didelot57d32312016-06-20 13:13:58 -04001563static int
1564mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1565 const struct switchdev_obj_port_vlan *vlan,
1566 struct switchdev_trans *trans)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001567{
Vivien Didelot04bed142016-08-31 18:06:13 -04001568 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotda9c3592016-02-12 12:09:40 -05001569 int err;
1570
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001571 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001572 return -EOPNOTSUPP;
1573
Vivien Didelotda9c3592016-02-12 12:09:40 -05001574 /* If the requested port doesn't belong to the same bridge as the VLAN
1575 * members, do not support it (yet) and fallback to software VLAN.
1576 */
1577 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1578 vlan->vid_end);
1579 if (err)
1580 return err;
1581
Vivien Didelot76e398a2015-11-01 12:33:55 -05001582 /* We don't need any dynamic resource from the kernel (yet),
1583 * so skip the prepare phase.
1584 */
1585 return 0;
1586}
1587
Vivien Didelotfad09c72016-06-21 12:28:20 -04001588static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04001589 u16 vid, bool untagged)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001590{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001591 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001592 int err;
1593
Vivien Didelotfad09c72016-06-21 12:28:20 -04001594 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001595 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001596 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001597
Vivien Didelotbd00e052017-05-01 14:05:11 -04001598 vlan.member[port] = untagged ?
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001599 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1600 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1601
Vivien Didelotfad09c72016-06-21 12:28:20 -04001602 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001603}
1604
Vivien Didelotf81ec902016-05-09 13:22:58 -04001605static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1606 const struct switchdev_obj_port_vlan *vlan,
1607 struct switchdev_trans *trans)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001608{
Vivien Didelot04bed142016-08-31 18:06:13 -04001609 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001610 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1611 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1612 u16 vid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001613
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001614 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001615 return;
1616
Vivien Didelotfad09c72016-06-21 12:28:20 -04001617 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001618
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001619 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
Vivien Didelotfad09c72016-06-21 12:28:20 -04001620 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
Andrew Lunnc8b09802016-06-04 21:16:57 +02001621 netdev_err(ds->ports[port].netdev,
1622 "failed to add VLAN %d%c\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001623 vid, untagged ? 'u' : 't');
Vivien Didelot76e398a2015-11-01 12:33:55 -05001624
Vivien Didelot77064f32016-11-04 03:23:30 +01001625 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
Andrew Lunnc8b09802016-06-04 21:16:57 +02001626 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04001627 vlan->vid_end);
1628
Vivien Didelotfad09c72016-06-21 12:28:20 -04001629 mutex_unlock(&chip->reg_lock);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001630}
1631
Vivien Didelotfad09c72016-06-21 12:28:20 -04001632static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001633 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001634{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001635 struct dsa_switch *ds = chip->ds;
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001636 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001637 int i, err;
1638
Vivien Didelotfad09c72016-06-21 12:28:20 -04001639 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001640 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001641 return err;
Vivien Didelot36d04ba2015-10-22 09:34:39 -04001642
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001643 /* Tell switchdev if this VLAN is handled in software */
Vivien Didelotbd00e052017-05-01 14:05:11 -04001644 if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05001645 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001646
Vivien Didelotbd00e052017-05-01 14:05:11 -04001647 vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001648
1649 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001650 vlan.valid = false;
Vivien Didelot370b4ff2016-09-29 12:21:57 -04001651 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
Vivien Didelot3d131f02015-11-03 10:52:52 -05001652 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001653 continue;
1654
Vivien Didelotbd00e052017-05-01 14:05:11 -04001655 if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04001656 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001657 break;
1658 }
1659 }
1660
Vivien Didelotfad09c72016-06-21 12:28:20 -04001661 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001662 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001663 return err;
1664
Vivien Didelote606ca32017-03-11 16:12:55 -05001665 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001666}
1667
Vivien Didelotf81ec902016-05-09 13:22:58 -04001668static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1669 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001670{
Vivien Didelot04bed142016-08-31 18:06:13 -04001671 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001672 u16 pvid, vid;
1673 int err = 0;
1674
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001675 if (!chip->info->max_vid)
Vivien Didelot54d77b52016-05-09 13:22:47 -04001676 return -EOPNOTSUPP;
1677
Vivien Didelotfad09c72016-06-21 12:28:20 -04001678 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001679
Vivien Didelot77064f32016-11-04 03:23:30 +01001680 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001681 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001682 goto unlock;
1683
Vivien Didelot76e398a2015-11-01 12:33:55 -05001684 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001685 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001686 if (err)
1687 goto unlock;
1688
1689 if (vid == pvid) {
Vivien Didelot77064f32016-11-04 03:23:30 +01001690 err = mv88e6xxx_port_set_pvid(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001691 if (err)
1692 goto unlock;
1693 }
1694 }
1695
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001696unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001697 mutex_unlock(&chip->reg_lock);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001698
1699 return err;
1700}
1701
Vivien Didelot83dabd12016-08-31 11:50:04 -04001702static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1703 const unsigned char *addr, u16 vid,
1704 u8 state)
Vivien Didelotfd231c82015-08-10 09:09:50 -04001705{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001706 struct mv88e6xxx_vtu_entry vlan;
Vivien Didelot88472932016-09-19 19:56:11 -04001707 struct mv88e6xxx_atu_entry entry;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001708 int err;
Vivien Didelotfd231c82015-08-10 09:09:50 -04001709
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001710 /* Null VLAN ID corresponds to the port private database */
1711 if (vid == 0)
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001712 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001713 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04001714 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001715 if (err)
1716 return err;
1717
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001718 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1719 ether_addr_copy(entry.mac, addr);
1720 eth_addr_dec(entry.mac);
1721
1722 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
Vivien Didelot88472932016-09-19 19:56:11 -04001723 if (err)
1724 return err;
1725
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001726 /* Initialize a fresh ATU entry if it isn't found */
1727 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1728 !ether_addr_equal(entry.mac, addr)) {
1729 memset(&entry, 0, sizeof(entry));
1730 ether_addr_copy(entry.mac, addr);
1731 }
1732
Vivien Didelot88472932016-09-19 19:56:11 -04001733 /* Purge the ATU entry only if no port is using it anymore */
1734 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
Vivien Didelot01bd96c2017-03-11 16:12:57 -05001735 entry.portvec &= ~BIT(port);
1736 if (!entry.portvec)
Vivien Didelot88472932016-09-19 19:56:11 -04001737 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1738 } else {
Vivien Didelot01bd96c2017-03-11 16:12:57 -05001739 entry.portvec |= BIT(port);
Vivien Didelot88472932016-09-19 19:56:11 -04001740 entry.state = state;
Vivien Didelotfd231c82015-08-10 09:09:50 -04001741 }
1742
Vivien Didelot9c13c022017-03-11 16:12:52 -05001743 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07001744}
1745
Vivien Didelotf81ec902016-05-09 13:22:58 -04001746static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1747 const struct switchdev_obj_port_fdb *fdb,
1748 struct switchdev_trans *trans)
Vivien Didelot146a3202015-10-08 11:35:12 -04001749{
1750 /* We don't need any dynamic resource from the kernel (yet),
1751 * so skip the prepare phase.
1752 */
1753 return 0;
1754}
1755
Vivien Didelotf81ec902016-05-09 13:22:58 -04001756static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1757 const struct switchdev_obj_port_fdb *fdb,
1758 struct switchdev_trans *trans)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07001759{
Vivien Didelot04bed142016-08-31 18:06:13 -04001760 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot6630e232015-08-06 01:44:07 -04001761
Vivien Didelotfad09c72016-06-21 12:28:20 -04001762 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001763 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1764 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1765 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
Vivien Didelotfad09c72016-06-21 12:28:20 -04001766 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07001767}
1768
Vivien Didelotf81ec902016-05-09 13:22:58 -04001769static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1770 const struct switchdev_obj_port_fdb *fdb)
David S. Millercdf09692015-08-11 12:00:37 -07001771{
Vivien Didelot04bed142016-08-31 18:06:13 -04001772 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot83dabd12016-08-31 11:50:04 -04001773 int err;
David S. Millercdf09692015-08-11 12:00:37 -07001774
Vivien Didelotfad09c72016-06-21 12:28:20 -04001775 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001776 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1777 GLOBAL_ATU_DATA_STATE_UNUSED);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001778 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07001779
Vivien Didelot83dabd12016-08-31 11:50:04 -04001780 return err;
David S. Millercdf09692015-08-11 12:00:37 -07001781}
1782
Vivien Didelot83dabd12016-08-31 11:50:04 -04001783static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1784 u16 fid, u16 vid, int port,
1785 struct switchdev_obj *obj,
1786 int (*cb)(struct switchdev_obj *obj))
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001787{
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001788 struct mv88e6xxx_atu_entry addr;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001789 int err;
1790
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001791 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1792 eth_broadcast_addr(addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001793
1794 do {
Vivien Didelotdabc1a92017-03-11 16:12:53 -05001795 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001796 if (err)
Vivien Didelot83dabd12016-08-31 11:50:04 -04001797 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001798
1799 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1800 break;
1801
Vivien Didelot01bd96c2017-03-11 16:12:57 -05001802 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
Vivien Didelot83dabd12016-08-31 11:50:04 -04001803 continue;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001804
Vivien Didelot83dabd12016-08-31 11:50:04 -04001805 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1806 struct switchdev_obj_port_fdb *fdb;
1807
1808 if (!is_unicast_ether_addr(addr.mac))
1809 continue;
1810
1811 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001812 fdb->vid = vid;
1813 ether_addr_copy(fdb->addr, addr.mac);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001814 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
1815 fdb->ndm_state = NUD_NOARP;
1816 else
1817 fdb->ndm_state = NUD_REACHABLE;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04001818 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1819 struct switchdev_obj_port_mdb *mdb;
1820
1821 if (!is_multicast_ether_addr(addr.mac))
1822 continue;
1823
1824 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1825 mdb->vid = vid;
1826 ether_addr_copy(mdb->addr, addr.mac);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001827 } else {
1828 return -EOPNOTSUPP;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001829 }
Vivien Didelot83dabd12016-08-31 11:50:04 -04001830
1831 err = cb(obj);
1832 if (err)
1833 return err;
Vivien Didelot74b6ba02016-02-26 13:16:02 -05001834 } while (!is_broadcast_ether_addr(addr.mac));
1835
1836 return err;
1837}
1838
Vivien Didelot83dabd12016-08-31 11:50:04 -04001839static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1840 struct switchdev_obj *obj,
1841 int (*cb)(struct switchdev_obj *obj))
1842{
Vivien Didelotb4e47c02016-09-29 12:21:58 -04001843 struct mv88e6xxx_vtu_entry vlan = {
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001844 .vid = chip->info->max_vid,
Vivien Didelot83dabd12016-08-31 11:50:04 -04001845 };
1846 u16 fid;
1847 int err;
1848
1849 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01001850 err = mv88e6xxx_port_get_fid(chip, port, &fid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001851 if (err)
1852 return err;
1853
1854 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1855 if (err)
1856 return err;
1857
1858 /* Dump VLANs' Filtering Information Databases */
Vivien Didelot83dabd12016-08-31 11:50:04 -04001859 do {
1860 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1861 if (err)
1862 return err;
1863
1864 if (!vlan.valid)
1865 break;
1866
1867 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1868 obj, cb);
1869 if (err)
1870 return err;
Vivien Didelot3cf3c842017-05-01 14:05:10 -04001871 } while (vlan.vid < chip->info->max_vid);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001872
1873 return err;
1874}
1875
Vivien Didelotf81ec902016-05-09 13:22:58 -04001876static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1877 struct switchdev_obj_port_fdb *fdb,
1878 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotf33475b2015-10-22 09:34:41 -04001879{
Vivien Didelot04bed142016-08-31 18:06:13 -04001880 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelotf33475b2015-10-22 09:34:41 -04001881 int err;
1882
Vivien Didelotfad09c72016-06-21 12:28:20 -04001883 mutex_lock(&chip->reg_lock);
Vivien Didelot83dabd12016-08-31 11:50:04 -04001884 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001885 mutex_unlock(&chip->reg_lock);
Vivien Didelotf33475b2015-10-22 09:34:41 -04001886
1887 return err;
1888}
1889
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001890static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1891 struct net_device *br)
1892{
Vivien Didelote96a6e02017-03-30 17:37:13 -04001893 struct dsa_switch *ds;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001894 int port;
Vivien Didelote96a6e02017-03-30 17:37:13 -04001895 int dev;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001896 int err;
1897
1898 /* Remap the Port VLAN of each local bridge group member */
1899 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1900 if (chip->ds->ports[port].bridge_dev == br) {
1901 err = mv88e6xxx_port_vlan_map(chip, port);
1902 if (err)
1903 return err;
1904 }
1905 }
1906
Vivien Didelote96a6e02017-03-30 17:37:13 -04001907 if (!mv88e6xxx_has_pvt(chip))
1908 return 0;
1909
1910 /* Remap the Port VLAN of each cross-chip bridge group member */
1911 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1912 ds = chip->ds->dst->ds[dev];
1913 if (!ds)
1914 break;
1915
1916 for (port = 0; port < ds->num_ports; ++port) {
1917 if (ds->ports[port].bridge_dev == br) {
1918 err = mv88e6xxx_pvt_map(chip, dev, port);
1919 if (err)
1920 return err;
1921 }
1922 }
1923 }
1924
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001925 return 0;
1926}
1927
Vivien Didelotf81ec902016-05-09 13:22:58 -04001928static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
Vivien Didelotfae8a252017-01-27 15:29:42 -05001929 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001930{
Vivien Didelot04bed142016-08-31 18:06:13 -04001931 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001932 int err;
Vivien Didelot466dfa02016-02-26 13:16:05 -05001933
Vivien Didelotfad09c72016-06-21 12:28:20 -04001934 mutex_lock(&chip->reg_lock);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001935 err = mv88e6xxx_bridge_map(chip, br);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001936 mutex_unlock(&chip->reg_lock);
Vivien Didelota6692752016-02-12 12:09:39 -05001937
Vivien Didelot466dfa02016-02-26 13:16:05 -05001938 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001939}
1940
Vivien Didelotf123f2f2017-01-27 15:29:41 -05001941static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1942 struct net_device *br)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05001943{
Vivien Didelot04bed142016-08-31 18:06:13 -04001944 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot466dfa02016-02-26 13:16:05 -05001945
Vivien Didelotfad09c72016-06-21 12:28:20 -04001946 mutex_lock(&chip->reg_lock);
Vivien Didelot240ea3e2017-03-30 17:37:12 -04001947 if (mv88e6xxx_bridge_map(chip, br) ||
1948 mv88e6xxx_port_vlan_map(chip, port))
1949 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
Vivien Didelotfad09c72016-06-21 12:28:20 -04001950 mutex_unlock(&chip->reg_lock);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05001951}
1952
Vivien Didelotaec5ac82017-03-30 17:37:15 -04001953static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1954 int port, struct net_device *br)
1955{
1956 struct mv88e6xxx_chip *chip = ds->priv;
1957 int err;
1958
1959 if (!mv88e6xxx_has_pvt(chip))
1960 return 0;
1961
1962 mutex_lock(&chip->reg_lock);
1963 err = mv88e6xxx_pvt_map(chip, dev, port);
1964 mutex_unlock(&chip->reg_lock);
1965
1966 return err;
1967}
1968
1969static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1970 int port, struct net_device *br)
1971{
1972 struct mv88e6xxx_chip *chip = ds->priv;
1973
1974 if (!mv88e6xxx_has_pvt(chip))
1975 return;
1976
1977 mutex_lock(&chip->reg_lock);
1978 if (mv88e6xxx_pvt_map(chip, dev, port))
1979 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1980 mutex_unlock(&chip->reg_lock);
1981}
1982
Vivien Didelot17e708b2016-12-05 17:30:27 -05001983static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1984{
1985 if (chip->info->ops->reset)
1986 return chip->info->ops->reset(chip);
1987
1988 return 0;
1989}
1990
Vivien Didelot309eca62016-12-05 17:30:26 -05001991static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1992{
1993 struct gpio_desc *gpiod = chip->reset;
1994
1995 /* If there is a GPIO connected to the reset pin, toggle it */
1996 if (gpiod) {
1997 gpiod_set_value_cansleep(gpiod, 1);
1998 usleep_range(10000, 20000);
1999 gpiod_set_value_cansleep(gpiod, 0);
2000 usleep_range(10000, 20000);
2001 }
2002}
2003
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002004static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2005{
2006 int i, err;
2007
2008 /* Set all ports to the Disabled state */
2009 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2010 err = mv88e6xxx_port_set_state(chip, i,
2011 PORT_CONTROL_STATE_DISABLED);
2012 if (err)
2013 return err;
2014 }
2015
2016 /* Wait for transmit queues to drain,
2017 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2018 */
2019 usleep_range(2000, 4000);
2020
2021 return 0;
2022}
2023
Vivien Didelotfad09c72016-06-21 12:28:20 -04002024static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002025{
Vivien Didelota935c052016-09-29 12:21:53 -04002026 int err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002027
Vivien Didelot4ac4b5a2016-12-05 17:30:25 -05002028 err = mv88e6xxx_disable_ports(chip);
2029 if (err)
2030 return err;
Vivien Didelot552238b2016-05-09 13:22:49 -04002031
Vivien Didelot309eca62016-12-05 17:30:26 -05002032 mv88e6xxx_hardware_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002033
Vivien Didelot17e708b2016-12-05 17:30:27 -05002034 return mv88e6xxx_software_reset(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002035}
2036
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002037static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002038{
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002039 u16 val;
2040 int err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002041
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002042 /* Clear Power Down bit */
2043 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2044 if (err)
2045 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002046
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002047 if (val & BMCR_PDOWN) {
2048 val &= ~BMCR_PDOWN;
2049 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002050 }
2051
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002052 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002053}
2054
Vivien Didelot43145572017-03-11 16:12:59 -05002055static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2056 enum mv88e6xxx_frame_mode frame, u16 egress,
2057 u16 etype)
Andrew Lunn56995cb2016-12-03 04:35:19 +01002058{
2059 int err;
2060
Vivien Didelot43145572017-03-11 16:12:59 -05002061 if (!chip->info->ops->port_set_frame_mode)
2062 return -EOPNOTSUPP;
2063
2064 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002065 if (err)
2066 return err;
2067
Vivien Didelot43145572017-03-11 16:12:59 -05002068 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2069 if (err)
2070 return err;
2071
2072 if (chip->info->ops->port_set_ether_type)
2073 return chip->info->ops->port_set_ether_type(chip, port, etype);
2074
2075 return 0;
2076}
2077
2078static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2079{
2080 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2081 PORT_CONTROL_EGRESS_UNMODIFIED,
2082 PORT_ETH_TYPE_DEFAULT);
2083}
2084
2085static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2086{
2087 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2088 PORT_CONTROL_EGRESS_UNMODIFIED,
2089 PORT_ETH_TYPE_DEFAULT);
2090}
2091
2092static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2093{
2094 return mv88e6xxx_set_port_mode(chip, port,
2095 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2096 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2097}
2098
2099static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2100{
2101 if (dsa_is_dsa_port(chip->ds, port))
2102 return mv88e6xxx_set_port_mode_dsa(chip, port);
2103
2104 if (dsa_is_normal_port(chip->ds, port))
2105 return mv88e6xxx_set_port_mode_normal(chip, port);
2106
2107 /* Setup CPU port mode depending on its supported tag format */
2108 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2109 return mv88e6xxx_set_port_mode_dsa(chip, port);
2110
2111 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2112 return mv88e6xxx_set_port_mode_edsa(chip, port);
2113
2114 return -EINVAL;
2115}
2116
Vivien Didelotea698f42017-03-11 16:12:50 -05002117static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2118{
2119 bool message = dsa_is_dsa_port(chip->ds, port);
2120
2121 return mv88e6xxx_port_set_message_port(chip, port, message);
2122}
2123
Vivien Didelot601aeed2017-03-11 16:13:00 -05002124static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2125{
2126 bool flood = port == dsa_upstream_port(chip->ds);
2127
2128 /* Upstream ports flood frames with unknown unicast or multicast DA */
2129 if (chip->info->ops->port_set_egress_floods)
2130 return chip->info->ops->port_set_egress_floods(chip, port,
2131 flood, flood);
2132
2133 return 0;
2134}
2135
Vivien Didelotfad09c72016-06-21 12:28:20 -04002136static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002137{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002138 struct dsa_switch *ds = chip->ds;
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002139 int err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002140 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002141
Vivien Didelotd78343d2016-11-04 03:23:36 +01002142 /* MAC Forcing register: don't force link, speed, duplex or flow control
2143 * state to any particular values on physical ports, but force the CPU
2144 * port and all DSA ports to their maximum bandwidth and full duplex.
2145 */
2146 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2147 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2148 SPEED_MAX, DUPLEX_FULL,
2149 PHY_INTERFACE_MODE_NA);
2150 else
2151 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2152 SPEED_UNFORCED, DUPLEX_UNFORCED,
2153 PHY_INTERFACE_MODE_NA);
2154 if (err)
2155 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002156
2157 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2158 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2159 * tunneling, determine priority by looking at 802.1p and IP
2160 * priority fields (IP prio has precedence), and set STP state
2161 * to Forwarding.
2162 *
2163 * If this is the CPU link, use DSA or EDSA tagging depending
2164 * on which tagging mode was configured.
2165 *
2166 * If this is a link to another switch, use DSA tagging mode.
2167 *
2168 * If this is the upstream port for this switch, enable
2169 * forwarding of unknown unicasts and multicasts.
2170 */
Andrew Lunn56995cb2016-12-03 04:35:19 +01002171 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
Andrew Lunn54d792f2015-05-06 01:09:47 +02002172 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2173 PORT_CONTROL_STATE_FORWARDING;
Andrew Lunn56995cb2016-12-03 04:35:19 +01002174 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2175 if (err)
2176 return err;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002177
Vivien Didelot601aeed2017-03-11 16:13:00 -05002178 err = mv88e6xxx_setup_port_mode(chip, port);
Andrew Lunn56995cb2016-12-03 04:35:19 +01002179 if (err)
2180 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002181
Vivien Didelot601aeed2017-03-11 16:13:00 -05002182 err = mv88e6xxx_setup_egress_floods(chip, port);
Vivien Didelot43145572017-03-11 16:12:59 -05002183 if (err)
2184 return err;
2185
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002186 /* If this port is connected to a SerDes, make sure the SerDes is not
2187 * powered down.
2188 */
Vivien Didelot09cb7df2016-08-15 17:19:01 -04002189 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002190 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2191 if (err)
2192 return err;
2193 reg &= PORT_STATUS_CMODE_MASK;
2194 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2195 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2196 (reg == PORT_STATUS_CMODE_SGMII)) {
2197 err = mv88e6xxx_serdes_power_on(chip);
2198 if (err < 0)
2199 return err;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002200 }
2201 }
2202
Vivien Didelot8efdda42015-08-13 12:52:23 -04002203 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002204 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002205 * untagged frames on this port, do a destination address lookup on all
2206 * received packets as usual, disable ARP mirroring and don't send a
2207 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002208 */
Andrew Lunna23b2962017-02-04 20:15:28 +01002209 err = mv88e6xxx_port_set_map_da(chip, port);
2210 if (err)
2211 return err;
2212
Andrew Lunn54d792f2015-05-06 01:09:47 +02002213 reg = 0;
Andrew Lunna23b2962017-02-04 20:15:28 +01002214 if (chip->info->ops->port_set_upstream_port) {
2215 err = chip->info->ops->port_set_upstream_port(
2216 chip, port, dsa_upstream_port(ds));
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002217 if (err)
2218 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002219 }
2220
Andrew Lunna23b2962017-02-04 20:15:28 +01002221 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2222 PORT_CONTROL_2_8021Q_DISABLED);
2223 if (err)
2224 return err;
2225
Andrew Lunn5f436662016-12-03 04:45:17 +01002226 if (chip->info->ops->port_jumbo_config) {
2227 err = chip->info->ops->port_jumbo_config(chip, port);
2228 if (err)
2229 return err;
2230 }
2231
Andrew Lunn54d792f2015-05-06 01:09:47 +02002232 /* Port Association Vector: when learning source addresses
2233 * of packets, add the address to the address database using
2234 * a port bitmap that has only the bit for this port set and
2235 * the other bits clear.
2236 */
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002237 reg = 1 << port;
Vivien Didelot996ecb82016-04-14 14:42:08 -04002238 /* Disable learning for CPU port */
2239 if (dsa_is_cpu_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002240 reg = 0;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002241
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002242 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2243 if (err)
2244 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002245
2246 /* Egress rate control 2: disable egress rate control. */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002247 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2248 if (err)
2249 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002250
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002251 if (chip->info->ops->port_pause_config) {
2252 err = chip->info->ops->port_pause_config(chip, port);
2253 if (err)
2254 return err;
2255 }
2256
Vivien Didelotc8c94892017-03-11 16:13:01 -05002257 if (chip->info->ops->port_disable_learn_limit) {
2258 err = chip->info->ops->port_disable_learn_limit(chip, port);
2259 if (err)
2260 return err;
2261 }
2262
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002263 if (chip->info->ops->port_disable_pri_override) {
2264 err = chip->info->ops->port_disable_pri_override(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002265 if (err)
2266 return err;
Andrew Lunnef0a7312016-12-03 04:35:16 +01002267 }
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02002268
Andrew Lunnef0a7312016-12-03 04:35:16 +01002269 if (chip->info->ops->port_tag_remap) {
2270 err = chip->info->ops->port_tag_remap(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002271 if (err)
2272 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002273 }
2274
Andrew Lunnef70b112016-12-03 04:45:18 +01002275 if (chip->info->ops->port_egress_rate_limiting) {
2276 err = chip->info->ops->port_egress_rate_limiting(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002277 if (err)
2278 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002279 }
2280
Vivien Didelotea698f42017-03-11 16:12:50 -05002281 err = mv88e6xxx_setup_message_port(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002282 if (err)
2283 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002284
Vivien Didelot207afda2016-04-14 14:42:09 -04002285 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002286 * database, and allow bidirectional communication between the
2287 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002288 */
Vivien Didelotb4e48c52016-11-04 03:23:29 +01002289 err = mv88e6xxx_port_set_fid(chip, port, 0);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002290 if (err)
2291 return err;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002292
Vivien Didelot240ea3e2017-03-30 17:37:12 -04002293 err = mv88e6xxx_port_vlan_map(chip, port);
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002294 if (err)
2295 return err;
Guenter Roeckd827e882015-03-26 18:36:29 -07002296
2297 /* Default VLAN ID and priority: don't set a default VLAN
2298 * ID, and set the default packet priority to zero.
2299 */
Andrew Lunn0e7b9922016-09-21 01:40:31 +02002300 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
Andrew Lunndbde9e62015-05-06 01:09:48 +02002301}
2302
Wei Yongjunaa0938c2016-10-18 15:53:37 +00002303static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002304{
2305 int err;
2306
Vivien Didelota935c052016-09-29 12:21:53 -04002307 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002308 if (err)
2309 return err;
2310
Vivien Didelota935c052016-09-29 12:21:53 -04002311 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002312 if (err)
2313 return err;
2314
Vivien Didelota935c052016-09-29 12:21:53 -04002315 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2316 if (err)
2317 return err;
2318
2319 return 0;
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002320}
2321
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002322static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2323 unsigned int ageing_time)
2324{
Vivien Didelot04bed142016-08-31 18:06:13 -04002325 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002326 int err;
2327
2328 mutex_lock(&chip->reg_lock);
Vivien Didelot720c6342017-03-11 16:12:48 -05002329 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
Vivien Didelot2cfcd962016-07-18 20:45:40 -04002330 mutex_unlock(&chip->reg_lock);
2331
2332 return err;
2333}
2334
Vivien Didelot97299342016-07-18 20:45:30 -04002335static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002336{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002337 struct dsa_switch *ds = chip->ds;
Vivien Didelotb0745e872016-05-09 13:22:53 -04002338 u32 upstream_port = dsa_upstream_port(ds);
Vivien Didelot08a01262016-05-09 13:22:50 -04002339 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002340
Vivien Didelot119477b2016-05-09 13:22:51 -04002341 /* Enable the PHY Polling Unit if present, don't discard any packets,
2342 * and mask all interrupt sources.
2343 */
Vivien Didelota199d8b2016-12-05 17:30:28 -05002344 err = mv88e6xxx_ppu_enable(chip);
Vivien Didelot119477b2016-05-09 13:22:51 -04002345 if (err)
2346 return err;
2347
Andrew Lunn33641992016-12-03 04:35:17 +01002348 if (chip->info->ops->g1_set_cpu_port) {
2349 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2350 if (err)
2351 return err;
2352 }
2353
2354 if (chip->info->ops->g1_set_egress_port) {
2355 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2356 if (err)
2357 return err;
2358 }
Vivien Didelotb0745e872016-05-09 13:22:53 -04002359
Vivien Didelot50484ff2016-05-09 13:22:54 -04002360 /* Disable remote management, and set the switch's DSA device number. */
Vivien Didelota935c052016-09-29 12:21:53 -04002361 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2362 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2363 (ds->index & 0x1f));
Vivien Didelot50484ff2016-05-09 13:22:54 -04002364 if (err)
2365 return err;
2366
Vivien Didelot08a01262016-05-09 13:22:50 -04002367 /* Configure the IP ToS mapping registers. */
Vivien Didelota935c052016-09-29 12:21:53 -04002368 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04002369 if (err)
2370 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002371 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04002372 if (err)
2373 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002374 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04002375 if (err)
2376 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002377 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04002378 if (err)
2379 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002380 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04002381 if (err)
2382 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002383 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04002384 if (err)
2385 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002386 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04002387 if (err)
2388 return err;
Vivien Didelota935c052016-09-29 12:21:53 -04002389 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04002390 if (err)
2391 return err;
2392
2393 /* Configure the IEEE 802.1p priority mapping register. */
Vivien Didelota935c052016-09-29 12:21:53 -04002394 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
Vivien Didelot08a01262016-05-09 13:22:50 -04002395 if (err)
2396 return err;
2397
Andrew Lunnde2273872016-11-21 23:27:01 +01002398 /* Initialize the statistics unit */
2399 err = mv88e6xxx_stats_set_histogram(chip);
2400 if (err)
2401 return err;
2402
Vivien Didelot97299342016-07-18 20:45:30 -04002403 /* Clear the statistics counters for all ports */
Vivien Didelota935c052016-09-29 12:21:53 -04002404 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2405 GLOBAL_STATS_OP_FLUSH_ALL);
Vivien Didelot97299342016-07-18 20:45:30 -04002406 if (err)
2407 return err;
2408
2409 /* Wait for the flush to complete. */
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +01002410 err = mv88e6xxx_g1_stats_wait(chip);
Vivien Didelot97299342016-07-18 20:45:30 -04002411 if (err)
2412 return err;
2413
2414 return 0;
2415}
2416
Vivien Didelotf81ec902016-05-09 13:22:58 -04002417static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07002418{
Vivien Didelot04bed142016-08-31 18:06:13 -04002419 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot552238b2016-05-09 13:22:49 -04002420 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002421 int i;
2422
Vivien Didelotfad09c72016-06-21 12:28:20 -04002423 chip->ds = ds;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002424 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
Vivien Didelot552238b2016-05-09 13:22:49 -04002425
Vivien Didelotfad09c72016-06-21 12:28:20 -04002426 mutex_lock(&chip->reg_lock);
Vivien Didelot552238b2016-05-09 13:22:49 -04002427
Vivien Didelot97299342016-07-18 20:45:30 -04002428 /* Setup Switch Port Registers */
Vivien Didelot370b4ff2016-09-29 12:21:57 -04002429 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
Vivien Didelot97299342016-07-18 20:45:30 -04002430 err = mv88e6xxx_setup_port(chip, i);
2431 if (err)
2432 goto unlock;
2433 }
2434
2435 /* Setup Switch Global 1 Registers */
2436 err = mv88e6xxx_g1_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002437 if (err)
2438 goto unlock;
2439
Vivien Didelot97299342016-07-18 20:45:30 -04002440 /* Setup Switch Global 2 Registers */
2441 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2442 err = mv88e6xxx_g2_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002443 if (err)
2444 goto unlock;
2445 }
Andrew Lunn54d792f2015-05-06 01:09:47 +02002446
Vivien Didelotb486d7c2017-05-01 14:05:13 -04002447 err = mv88e6xxx_vtu_setup(chip);
2448 if (err)
2449 goto unlock;
2450
Vivien Didelot81228992017-03-30 17:37:08 -04002451 err = mv88e6xxx_pvt_setup(chip);
2452 if (err)
2453 goto unlock;
2454
Vivien Didelota2ac29d2017-03-11 16:12:49 -05002455 err = mv88e6xxx_atu_setup(chip);
2456 if (err)
2457 goto unlock;
2458
Andrew Lunn6e55f692016-12-03 04:45:16 +01002459 /* Some generations have the configuration of sending reserved
2460 * management frames to the CPU in global2, others in
2461 * global1. Hence it does not fit the two setup functions
2462 * above.
2463 */
2464 if (chip->info->ops->mgmt_rsvd2cpu) {
2465 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2466 if (err)
2467 goto unlock;
2468 }
2469
Vivien Didelot6b17e862015-08-13 12:52:18 -04002470unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002471 mutex_unlock(&chip->reg_lock);
Andrew Lunndb687a52015-06-20 21:31:29 +02002472
Andrew Lunn48ace4e2016-04-14 23:47:12 +02002473 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002474}
2475
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002476static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2477{
Vivien Didelot04bed142016-08-31 18:06:13 -04002478 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002479 int err;
2480
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002481 if (!chip->info->ops->set_switch_mac)
2482 return -EOPNOTSUPP;
2483
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002484 mutex_lock(&chip->reg_lock);
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002485 err = chip->info->ops->set_switch_mac(chip, addr);
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002486 mutex_unlock(&chip->reg_lock);
2487
2488 return err;
2489}
2490
Vivien Didelote57e5e72016-08-15 17:19:00 -04002491static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002492{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002493 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2494 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002495 u16 val;
2496 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002497
Andrew Lunnee26a222017-01-24 14:53:48 +01002498 if (!chip->info->ops->phy_read)
2499 return -EOPNOTSUPP;
2500
Vivien Didelotfad09c72016-06-21 12:28:20 -04002501 mutex_lock(&chip->reg_lock);
Andrew Lunnee26a222017-01-24 14:53:48 +01002502 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002503 mutex_unlock(&chip->reg_lock);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002504
Andrew Lunnda9f3302017-02-01 03:40:05 +01002505 if (reg == MII_PHYSID2) {
2506 /* Some internal PHYS don't have a model number. Use
2507 * the mv88e6390 family model number instead.
2508 */
2509 if (!(val & 0x3f0))
2510 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2511 }
2512
Vivien Didelote57e5e72016-08-15 17:19:00 -04002513 return err ? err : val;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002514}
2515
Vivien Didelote57e5e72016-08-15 17:19:00 -04002516static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002517{
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002518 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2519 struct mv88e6xxx_chip *chip = mdio_bus->chip;
Vivien Didelote57e5e72016-08-15 17:19:00 -04002520 int err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002521
Andrew Lunnee26a222017-01-24 14:53:48 +01002522 if (!chip->info->ops->phy_write)
2523 return -EOPNOTSUPP;
2524
Vivien Didelotfad09c72016-06-21 12:28:20 -04002525 mutex_lock(&chip->reg_lock);
Andrew Lunnee26a222017-01-24 14:53:48 +01002526 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002527 mutex_unlock(&chip->reg_lock);
Vivien Didelote57e5e72016-08-15 17:19:00 -04002528
2529 return err;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02002530}
2531
Vivien Didelotfad09c72016-06-21 12:28:20 -04002532static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunna3c53be52017-01-24 14:53:50 +01002533 struct device_node *np,
2534 bool external)
Andrew Lunnb516d452016-06-04 21:17:06 +02002535{
2536 static int index;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002537 struct mv88e6xxx_mdio_bus *mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02002538 struct mii_bus *bus;
2539 int err;
2540
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002541 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
Andrew Lunnb516d452016-06-04 21:17:06 +02002542 if (!bus)
2543 return -ENOMEM;
2544
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002545 mdio_bus = bus->priv;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002546 mdio_bus->bus = bus;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002547 mdio_bus->chip = chip;
Andrew Lunna3c53be52017-01-24 14:53:50 +01002548 INIT_LIST_HEAD(&mdio_bus->list);
2549 mdio_bus->external = external;
Andrew Lunn0dd12d52017-01-24 14:53:49 +01002550
Andrew Lunnb516d452016-06-04 21:17:06 +02002551 if (np) {
2552 bus->name = np->full_name;
2553 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2554 } else {
2555 bus->name = "mv88e6xxx SMI";
2556 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2557 }
2558
2559 bus->read = mv88e6xxx_mdio_read;
2560 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002561 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02002562
Andrew Lunna3c53be52017-01-24 14:53:50 +01002563 if (np)
2564 err = of_mdiobus_register(bus, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02002565 else
2566 err = mdiobus_register(bus);
2567 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002568 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunna3c53be52017-01-24 14:53:50 +01002569 return err;
Andrew Lunnb516d452016-06-04 21:17:06 +02002570 }
Andrew Lunna3c53be52017-01-24 14:53:50 +01002571
2572 if (external)
2573 list_add_tail(&mdio_bus->list, &chip->mdios);
2574 else
2575 list_add(&mdio_bus->list, &chip->mdios);
Andrew Lunnb516d452016-06-04 21:17:06 +02002576
2577 return 0;
Andrew Lunnb516d452016-06-04 21:17:06 +02002578}
2579
Andrew Lunna3c53be52017-01-24 14:53:50 +01002580static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2581 { .compatible = "marvell,mv88e6xxx-mdio-external",
2582 .data = (void *)true },
2583 { },
2584};
2585
2586static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2587 struct device_node *np)
2588{
2589 const struct of_device_id *match;
2590 struct device_node *child;
2591 int err;
2592
2593 /* Always register one mdio bus for the internal/default mdio
2594 * bus. This maybe represented in the device tree, but is
2595 * optional.
2596 */
2597 child = of_get_child_by_name(np, "mdio");
2598 err = mv88e6xxx_mdio_register(chip, child, false);
2599 if (err)
2600 return err;
2601
2602 /* Walk the device tree, and see if there are any other nodes
2603 * which say they are compatible with the external mdio
2604 * bus.
2605 */
2606 for_each_available_child_of_node(np, child) {
2607 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2608 if (match) {
2609 err = mv88e6xxx_mdio_register(chip, child, true);
2610 if (err)
2611 return err;
2612 }
2613 }
2614
2615 return 0;
2616}
2617
2618static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
Andrew Lunnb516d452016-06-04 21:17:06 +02002619
2620{
Andrew Lunna3c53be52017-01-24 14:53:50 +01002621 struct mv88e6xxx_mdio_bus *mdio_bus;
2622 struct mii_bus *bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02002623
Andrew Lunna3c53be52017-01-24 14:53:50 +01002624 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2625 bus = mdio_bus->bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02002626
Andrew Lunna3c53be52017-01-24 14:53:50 +01002627 mdiobus_unregister(bus);
2628 }
Andrew Lunnb516d452016-06-04 21:17:06 +02002629}
2630
Vivien Didelot855b1932016-07-20 18:18:35 -04002631static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2632{
Vivien Didelot04bed142016-08-31 18:06:13 -04002633 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002634
2635 return chip->eeprom_len;
2636}
2637
Vivien Didelot855b1932016-07-20 18:18:35 -04002638static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2639 struct ethtool_eeprom *eeprom, u8 *data)
2640{
Vivien Didelot04bed142016-08-31 18:06:13 -04002641 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002642 int err;
2643
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002644 if (!chip->info->ops->get_eeprom)
2645 return -EOPNOTSUPP;
2646
Vivien Didelot855b1932016-07-20 18:18:35 -04002647 mutex_lock(&chip->reg_lock);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002648 err = chip->info->ops->get_eeprom(chip, eeprom, data);
Vivien Didelot855b1932016-07-20 18:18:35 -04002649 mutex_unlock(&chip->reg_lock);
2650
2651 if (err)
2652 return err;
2653
2654 eeprom->magic = 0xc3ec4951;
2655
2656 return 0;
2657}
2658
Vivien Didelot855b1932016-07-20 18:18:35 -04002659static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2660 struct ethtool_eeprom *eeprom, u8 *data)
2661{
Vivien Didelot04bed142016-08-31 18:06:13 -04002662 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot855b1932016-07-20 18:18:35 -04002663 int err;
2664
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002665 if (!chip->info->ops->set_eeprom)
2666 return -EOPNOTSUPP;
2667
Vivien Didelot855b1932016-07-20 18:18:35 -04002668 if (eeprom->magic != 0xc3ec4951)
2669 return -EINVAL;
2670
2671 mutex_lock(&chip->reg_lock);
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002672 err = chip->info->ops->set_eeprom(chip, eeprom, data);
Vivien Didelot855b1932016-07-20 18:18:35 -04002673 mutex_unlock(&chip->reg_lock);
2674
2675 return err;
2676}
2677
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002678static const struct mv88e6xxx_ops mv88e6085_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002679 /* MV88E6XXX_FAMILY_6097 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002680 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002681 .phy_read = mv88e6xxx_phy_ppu_read,
2682 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002683 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002684 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002685 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002686 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002687 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002688 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002689 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunnef70b112016-12-03 04:45:18 +01002690 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002691 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002694 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002695 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2696 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002697 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002698 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2699 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002700 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002701 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002702 .ppu_enable = mv88e6185_g1_ppu_enable,
2703 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002704 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002705};
2706
2707static const struct mv88e6xxx_ops mv88e6095_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002708 /* MV88E6XXX_FAMILY_6095 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002709 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002710 .phy_read = mv88e6xxx_phy_ppu_read,
2711 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002712 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002713 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002714 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002715 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002716 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunna23b2962017-02-04 20:15:28 +01002717 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002718 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002719 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2720 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002721 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002722 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002723 .ppu_enable = mv88e6185_g1_ppu_enable,
2724 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002725 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002726};
2727
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002728static const struct mv88e6xxx_ops mv88e6097_ops = {
Stefan Eichenberger15da3cc2016-11-25 09:41:30 +01002729 /* MV88E6XXX_FAMILY_6097 */
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002730 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2731 .phy_read = mv88e6xxx_g2_smi_phy_read,
2732 .phy_write = mv88e6xxx_g2_smi_phy_write,
2733 .port_set_link = mv88e6xxx_port_set_link,
2734 .port_set_duplex = mv88e6xxx_port_set_duplex,
2735 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002736 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002737 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002738 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002739 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002740 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002741 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002742 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002745 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2746 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2747 .stats_get_strings = mv88e6095_stats_get_strings,
2748 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002749 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2750 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Volodymyr Bendiuga91eaa472017-02-14 11:29:30 +01002751 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002752 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002753 .reset = mv88e6352_g1_reset,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01002754};
2755
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002756static const struct mv88e6xxx_ops mv88e6123_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002757 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002758 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01002759 .phy_read = mv88e6165_phy_read,
2760 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002761 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002762 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002763 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002764 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002765 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002766 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002767 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002768 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002769 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2770 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002771 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002772 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2773 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002774 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002775 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002776 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002777};
2778
2779static const struct mv88e6xxx_ops mv88e6131_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002780 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002781 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002782 .phy_read = mv88e6xxx_phy_ppu_read,
2783 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002784 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002785 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002786 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002787 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002788 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002789 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002790 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunna23b2962017-02-04 20:15:28 +01002791 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunn5f436662016-12-03 04:45:17 +01002792 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002793 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002794 .port_pause_config = mv88e6097_port_pause_config,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002795 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002796 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2797 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002798 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002799 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2800 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002801 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002802 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05002803 .ppu_enable = mv88e6185_g1_ppu_enable,
2804 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002805 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002806};
2807
Vivien Didelot990e27b2017-03-28 13:50:32 -04002808static const struct mv88e6xxx_ops mv88e6141_ops = {
2809 /* MV88E6XXX_FAMILY_6341 */
2810 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2811 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2812 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2813 .phy_read = mv88e6xxx_g2_smi_phy_read,
2814 .phy_write = mv88e6xxx_g2_smi_phy_write,
2815 .port_set_link = mv88e6xxx_port_set_link,
2816 .port_set_duplex = mv88e6xxx_port_set_duplex,
2817 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2818 .port_set_speed = mv88e6390_port_set_speed,
2819 .port_tag_remap = mv88e6095_port_tag_remap,
2820 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2821 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2822 .port_set_ether_type = mv88e6351_port_set_ether_type,
2823 .port_jumbo_config = mv88e6165_port_jumbo_config,
2824 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2825 .port_pause_config = mv88e6097_port_pause_config,
2826 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2827 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2828 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2829 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2830 .stats_get_strings = mv88e6320_stats_get_strings,
2831 .stats_get_stats = mv88e6390_stats_get_stats,
2832 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
2833 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
2834 .watchdog_ops = &mv88e6390_watchdog_ops,
2835 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2836 .reset = mv88e6352_g1_reset,
2837};
2838
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002839static const struct mv88e6xxx_ops mv88e6161_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002840 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01002842 .phy_read = mv88e6165_phy_read,
2843 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002844 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002845 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002846 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002847 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002848 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002849 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002850 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002851 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002852 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002853 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002854 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002855 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002856 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002857 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2858 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002859 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002860 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2861 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002862 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002863 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002864 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002865};
2866
2867static const struct mv88e6xxx_ops mv88e6165_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002868 /* MV88E6XXX_FAMILY_6165 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002869 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Andrew Lunnefb3e742017-01-24 14:53:47 +01002870 .phy_read = mv88e6165_phy_read,
2871 .phy_write = mv88e6165_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002872 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002873 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002874 .port_set_speed = mv88e6185_port_set_speed,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002875 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002876 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002877 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002878 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2879 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002880 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002881 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2882 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002883 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002884 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002885 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002886};
2887
2888static const struct mv88e6xxx_ops mv88e6171_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002889 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002890 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002891 .phy_read = mv88e6xxx_g2_smi_phy_read,
2892 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002893 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002894 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01002895 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002896 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002897 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002898 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002899 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002900 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002901 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002902 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002903 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002904 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002905 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002906 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002907 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2908 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002909 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002910 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2911 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002912 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002913 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002914 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002915};
2916
2917static const struct mv88e6xxx_ops mv88e6172_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002918 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002919 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2920 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002921 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002922 .phy_read = mv88e6xxx_g2_smi_phy_read,
2923 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002924 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002925 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01002926 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002927 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002928 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002929 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002930 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002931 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002932 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002933 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002934 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002935 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002936 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002937 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002938 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2939 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002940 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002941 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2942 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002943 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002944 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002945 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002946};
2947
2948static const struct mv88e6xxx_ops mv88e6175_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002949 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002950 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002951 .phy_read = mv88e6xxx_g2_smi_phy_read,
2952 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002953 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002954 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01002955 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002956 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002957 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002958 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002959 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002960 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002961 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002962 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002963 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002964 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002965 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002966 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002967 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2968 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01002969 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01002970 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2971 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01002972 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01002973 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05002974 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002975};
2976
2977static const struct mv88e6xxx_ops mv88e6176_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01002978 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04002979 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2980 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04002981 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04002982 .phy_read = mv88e6xxx_g2_smi_phy_read,
2983 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01002984 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01002985 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01002986 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01002987 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01002988 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002989 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05002990 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01002991 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01002992 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01002993 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01002994 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05002995 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05002996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01002997 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01002998 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2999 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003000 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003001 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3002 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003003 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003004 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003005 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003006};
3007
3008static const struct mv88e6xxx_ops mv88e6185_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003009 /* MV88E6XXX_FAMILY_6185 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003010 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003011 .phy_read = mv88e6xxx_phy_ppu_read,
3012 .phy_write = mv88e6xxx_phy_ppu_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003013 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003014 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003015 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003016 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003017 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
Andrew Lunnef70b112016-12-03 04:45:18 +01003018 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
Andrew Lunna23b2962017-02-04 20:15:28 +01003019 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003020 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003021 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3022 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003023 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003024 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3025 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003026 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003027 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelota199d8b2016-12-05 17:30:28 -05003028 .ppu_enable = mv88e6185_g1_ppu_enable,
3029 .ppu_disable = mv88e6185_g1_ppu_disable,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003030 .reset = mv88e6185_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003031};
3032
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003033static const struct mv88e6xxx_ops mv88e6190_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003034 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003035 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3036 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003037 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3038 .phy_read = mv88e6xxx_g2_smi_phy_read,
3039 .phy_write = mv88e6xxx_g2_smi_phy_write,
3040 .port_set_link = mv88e6xxx_port_set_link,
3041 .port_set_duplex = mv88e6xxx_port_set_duplex,
3042 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3043 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003044 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003045 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003046 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003047 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003048 .port_pause_config = mv88e6390_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003049 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003050 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003051 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003052 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003053 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3054 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003055 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003056 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3057 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003058 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003059 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003060 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003061};
3062
3063static const struct mv88e6xxx_ops mv88e6190x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003064 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003065 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3066 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003067 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3068 .phy_read = mv88e6xxx_g2_smi_phy_read,
3069 .phy_write = mv88e6xxx_g2_smi_phy_write,
3070 .port_set_link = mv88e6xxx_port_set_link,
3071 .port_set_duplex = mv88e6xxx_port_set_duplex,
3072 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3073 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003074 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003075 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003076 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003077 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003078 .port_pause_config = mv88e6390_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003079 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003080 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003081 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003082 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003083 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3084 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003085 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003086 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3087 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003088 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003089 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003090 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003091};
3092
3093static const struct mv88e6xxx_ops mv88e6191_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003094 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003095 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3096 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003097 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3098 .phy_read = mv88e6xxx_g2_smi_phy_read,
3099 .phy_write = mv88e6xxx_g2_smi_phy_write,
3100 .port_set_link = mv88e6xxx_port_set_link,
3101 .port_set_duplex = mv88e6xxx_port_set_duplex,
3102 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3103 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003104 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003105 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003106 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003107 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003108 .port_pause_config = mv88e6390_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003111 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003112 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003113 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3114 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003115 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003116 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3117 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003118 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003119 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003120 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003121};
3122
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003123static const struct mv88e6xxx_ops mv88e6240_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003124 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003125 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3126 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003127 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003128 .phy_read = mv88e6xxx_g2_smi_phy_read,
3129 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003130 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003131 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003132 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003133 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003134 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003135 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003136 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003137 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003138 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003139 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003140 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003141 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003142 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003143 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003144 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3145 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003146 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003147 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3148 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003149 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003150 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003151 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003152};
3153
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003154static const struct mv88e6xxx_ops mv88e6290_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003155 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003156 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3157 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003158 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3159 .phy_read = mv88e6xxx_g2_smi_phy_read,
3160 .phy_write = mv88e6xxx_g2_smi_phy_write,
3161 .port_set_link = mv88e6xxx_port_set_link,
3162 .port_set_duplex = mv88e6xxx_port_set_duplex,
3163 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3164 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003165 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003166 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003167 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003168 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003169 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunnf39908d2017-02-04 20:02:50 +01003170 .port_set_cmode = mv88e6390x_port_set_cmode,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003171 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003172 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003173 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003174 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003175 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3176 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003177 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003178 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3179 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003180 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003181 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003182 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003183};
3184
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003185static const struct mv88e6xxx_ops mv88e6320_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003186 /* MV88E6XXX_FAMILY_6320 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003187 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3188 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003189 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003190 .phy_read = mv88e6xxx_g2_smi_phy_read,
3191 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003192 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003193 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003194 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003195 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003196 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003197 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003198 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003199 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003200 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003201 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003202 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003203 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003204 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003205 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3206 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003207 .stats_get_stats = mv88e6320_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003208 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3209 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003210 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003211 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003212};
3213
3214static const struct mv88e6xxx_ops mv88e6321_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003215 /* MV88E6XXX_FAMILY_6321 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003216 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3217 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003219 .phy_read = mv88e6xxx_g2_smi_phy_read,
3220 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003221 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003222 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003223 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003224 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003225 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003226 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003227 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003228 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003229 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003230 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003231 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003232 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003233 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003234 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3235 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003236 .stats_get_stats = mv88e6320_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003237 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3238 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003239 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003240};
3241
Vivien Didelot16e329a2017-03-28 13:50:33 -04003242static const struct mv88e6xxx_ops mv88e6341_ops = {
3243 /* MV88E6XXX_FAMILY_6341 */
3244 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3245 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3247 .phy_read = mv88e6xxx_g2_smi_phy_read,
3248 .phy_write = mv88e6xxx_g2_smi_phy_write,
3249 .port_set_link = mv88e6xxx_port_set_link,
3250 .port_set_duplex = mv88e6xxx_port_set_duplex,
3251 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3252 .port_set_speed = mv88e6390_port_set_speed,
3253 .port_tag_remap = mv88e6095_port_tag_remap,
3254 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3255 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3256 .port_set_ether_type = mv88e6351_port_set_ether_type,
3257 .port_jumbo_config = mv88e6165_port_jumbo_config,
3258 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3259 .port_pause_config = mv88e6097_port_pause_config,
3260 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3261 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3262 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3263 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3264 .stats_get_strings = mv88e6320_stats_get_strings,
3265 .stats_get_stats = mv88e6390_stats_get_stats,
3266 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3267 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3268 .watchdog_ops = &mv88e6390_watchdog_ops,
3269 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3270 .reset = mv88e6352_g1_reset,
3271};
3272
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003273static const struct mv88e6xxx_ops mv88e6350_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003274 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003275 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003276 .phy_read = mv88e6xxx_g2_smi_phy_read,
3277 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003278 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003279 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003280 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003281 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003282 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003283 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003284 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003285 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003286 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003287 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003288 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003289 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003290 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003291 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003292 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3293 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003294 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003295 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3296 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003297 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003298 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003299 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003300};
3301
3302static const struct mv88e6xxx_ops mv88e6351_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003303 /* MV88E6XXX_FAMILY_6351 */
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003304 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003305 .phy_read = mv88e6xxx_g2_smi_phy_read,
3306 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003307 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003308 .port_set_duplex = mv88e6xxx_port_set_duplex,
Andrew Lunn94d66ae2016-11-10 15:44:01 +01003309 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003310 .port_set_speed = mv88e6185_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003311 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003312 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003313 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003314 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003315 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003316 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003317 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003318 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003319 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003320 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003321 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3322 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003323 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003324 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3325 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003326 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003327 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003328 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003329};
3330
3331static const struct mv88e6xxx_ops mv88e6352_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003332 /* MV88E6XXX_FAMILY_6352 */
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04003333 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3334 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
Vivien Didelotb073d4e2016-09-29 12:22:01 -04003335 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003336 .phy_read = mv88e6xxx_g2_smi_phy_read,
3337 .phy_write = mv88e6xxx_g2_smi_phy_write,
Vivien Didelot08ef7f12016-11-04 03:23:32 +01003338 .port_set_link = mv88e6xxx_port_set_link,
Vivien Didelot7f1ae072016-11-04 03:23:33 +01003339 .port_set_duplex = mv88e6xxx_port_set_duplex,
Vivien Didelota0a0f622016-11-04 03:23:34 +01003340 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
Vivien Didelot96a2b402016-11-04 03:23:35 +01003341 .port_set_speed = mv88e6352_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003342 .port_tag_remap = mv88e6095_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003343 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003344 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003345 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003346 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003347 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunnb35d322a2016-12-03 04:45:19 +01003348 .port_pause_config = mv88e6097_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunna605a0f2016-11-21 23:26:58 +01003351 .stats_snapshot = mv88e6320_g1_stats_snapshot,
Andrew Lunndfafe442016-11-21 23:27:02 +01003352 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3353 .stats_get_strings = mv88e6095_stats_get_strings,
Andrew Lunn052f9472016-11-21 23:27:03 +01003354 .stats_get_stats = mv88e6095_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003355 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3356 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
Andrew Lunnfcd25162017-02-09 00:03:42 +01003357 .watchdog_ops = &mv88e6097_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003358 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003359 .reset = mv88e6352_g1_reset,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003360};
3361
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003362static const struct mv88e6xxx_ops mv88e6390_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003363 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003364 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3365 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003366 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3367 .phy_read = mv88e6xxx_g2_smi_phy_read,
3368 .phy_write = mv88e6xxx_g2_smi_phy_write,
3369 .port_set_link = mv88e6xxx_port_set_link,
3370 .port_set_duplex = mv88e6xxx_port_set_duplex,
3371 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3372 .port_set_speed = mv88e6390_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003373 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003374 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003375 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003376 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003377 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003378 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003379 .port_pause_config = mv88e6390_port_pause_config,
Andrew Lunnf39908d2017-02-04 20:02:50 +01003380 .port_set_cmode = mv88e6390x_port_set_cmode,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003381 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003382 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003383 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003384 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003385 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3386 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003387 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003388 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3389 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003390 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003391 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003392 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003393};
3394
3395static const struct mv88e6xxx_ops mv88e6390x_ops = {
Andrew Lunn4b325d82016-11-21 23:26:59 +01003396 /* MV88E6XXX_FAMILY_6390 */
Vivien Didelot98fc3c62017-01-12 18:07:16 -05003397 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3398 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003399 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3400 .phy_read = mv88e6xxx_g2_smi_phy_read,
3401 .phy_write = mv88e6xxx_g2_smi_phy_write,
3402 .port_set_link = mv88e6xxx_port_set_link,
3403 .port_set_duplex = mv88e6xxx_port_set_duplex,
3404 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3405 .port_set_speed = mv88e6390x_port_set_speed,
Andrew Lunnef0a7312016-12-03 04:35:16 +01003406 .port_tag_remap = mv88e6390_port_tag_remap,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003407 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
Vivien Didelot601aeed2017-03-11 16:13:00 -05003408 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
Andrew Lunn56995cb2016-12-03 04:35:19 +01003409 .port_set_ether_type = mv88e6351_port_set_ether_type,
Andrew Lunn5f436662016-12-03 04:45:17 +01003410 .port_jumbo_config = mv88e6165_port_jumbo_config,
Andrew Lunnef70b112016-12-03 04:45:18 +01003411 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
Andrew Lunn3ce0e652016-12-03 04:45:20 +01003412 .port_pause_config = mv88e6390_port_pause_config,
Vivien Didelotc8c94892017-03-11 16:13:01 -05003413 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
Vivien Didelot9dbfb4e2017-03-11 16:13:02 -05003414 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
Andrew Lunn79523472016-11-21 23:27:00 +01003415 .stats_snapshot = mv88e6390_g1_stats_snapshot,
Andrew Lunnde2273872016-11-21 23:27:01 +01003416 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
Andrew Lunndfafe442016-11-21 23:27:02 +01003417 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3418 .stats_get_strings = mv88e6320_stats_get_strings,
Andrew Lunne0d8b612016-11-21 23:27:04 +01003419 .stats_get_stats = mv88e6390_stats_get_stats,
Andrew Lunn33641992016-12-03 04:35:17 +01003420 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3421 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
Andrew Lunn61303732017-02-09 00:03:43 +01003422 .watchdog_ops = &mv88e6390_watchdog_ops,
Andrew Lunn6e55f692016-12-03 04:45:16 +01003423 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
Vivien Didelot17e708b2016-12-05 17:30:27 -05003424 .reset = mv88e6352_g1_reset,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003425};
3426
Vivien Didelotf81ec902016-05-09 13:22:58 -04003427static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3428 [MV88E6085] = {
3429 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3430 .family = MV88E6XXX_FAMILY_6097,
3431 .name = "Marvell 88E6085",
3432 .num_databases = 4096,
3433 .num_ports = 10,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003434 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003435 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003436 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003437 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003438 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003439 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003440 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003441 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003442 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003443 .ops = &mv88e6085_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003444 },
3445
3446 [MV88E6095] = {
3447 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3448 .family = MV88E6XXX_FAMILY_6095,
3449 .name = "Marvell 88E6095/88E6095F",
3450 .num_databases = 256,
3451 .num_ports = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003452 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003453 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003454 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003455 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003456 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003457 .atu_move_port_mask = 0xf,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003458 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003459 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003460 .ops = &mv88e6095_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003461 },
3462
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003463 [MV88E6097] = {
3464 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3465 .family = MV88E6XXX_FAMILY_6097,
3466 .name = "Marvell 88E6097/88E6097F",
3467 .num_databases = 4096,
3468 .num_ports = 11,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003469 .max_vid = 4095,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003470 .port_base_addr = 0x10,
3471 .global1_addr = 0x1b,
3472 .age_time_coeff = 15000,
Stefan Eichenbergerc5341782016-11-25 09:41:29 +01003473 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003474 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003475 .pvt = true,
Stefan Eichenberger2bfcfcd2016-12-05 14:12:42 +01003476 .tag_protocol = DSA_TAG_PROTO_EDSA,
Stefan Eichenberger7d381a02016-11-22 17:47:21 +01003477 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3478 .ops = &mv88e6097_ops,
3479 },
3480
Vivien Didelotf81ec902016-05-09 13:22:58 -04003481 [MV88E6123] = {
3482 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3483 .family = MV88E6XXX_FAMILY_6165,
3484 .name = "Marvell 88E6123",
3485 .num_databases = 4096,
3486 .num_ports = 3,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003487 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003488 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003489 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003490 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003491 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003492 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003493 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003494 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003495 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003496 .ops = &mv88e6123_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003497 },
3498
3499 [MV88E6131] = {
3500 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3501 .family = MV88E6XXX_FAMILY_6185,
3502 .name = "Marvell 88E6131",
3503 .num_databases = 256,
3504 .num_ports = 8,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003505 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003506 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003507 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003508 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003509 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003510 .atu_move_port_mask = 0xf,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003511 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003512 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003513 .ops = &mv88e6131_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003514 },
3515
Vivien Didelot990e27b2017-03-28 13:50:32 -04003516 [MV88E6141] = {
3517 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3518 .family = MV88E6XXX_FAMILY_6341,
3519 .name = "Marvell 88E6341",
3520 .num_databases = 4096,
3521 .num_ports = 6,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003522 .max_vid = 4095,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003523 .port_base_addr = 0x10,
3524 .global1_addr = 0x1b,
3525 .age_time_coeff = 3750,
3526 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003527 .pvt = true,
Vivien Didelot990e27b2017-03-28 13:50:32 -04003528 .tag_protocol = DSA_TAG_PROTO_EDSA,
3529 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3530 .ops = &mv88e6141_ops,
3531 },
3532
Vivien Didelotf81ec902016-05-09 13:22:58 -04003533 [MV88E6161] = {
3534 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3535 .family = MV88E6XXX_FAMILY_6165,
3536 .name = "Marvell 88E6161",
3537 .num_databases = 4096,
3538 .num_ports = 6,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003539 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003540 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003541 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003542 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003543 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003544 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003545 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003546 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003547 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003548 .ops = &mv88e6161_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003549 },
3550
3551 [MV88E6165] = {
3552 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3553 .family = MV88E6XXX_FAMILY_6165,
3554 .name = "Marvell 88E6165",
3555 .num_databases = 4096,
3556 .num_ports = 6,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003557 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003558 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003559 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003560 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003561 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003562 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003563 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003564 .tag_protocol = DSA_TAG_PROTO_DSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003565 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003566 .ops = &mv88e6165_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003567 },
3568
3569 [MV88E6171] = {
3570 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3571 .family = MV88E6XXX_FAMILY_6351,
3572 .name = "Marvell 88E6171",
3573 .num_databases = 4096,
3574 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003575 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003576 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003577 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003578 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003579 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003580 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003581 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003582 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003583 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003584 .ops = &mv88e6171_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003585 },
3586
3587 [MV88E6172] = {
3588 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3589 .family = MV88E6XXX_FAMILY_6352,
3590 .name = "Marvell 88E6172",
3591 .num_databases = 4096,
3592 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003593 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003594 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003595 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003596 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003597 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003598 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003599 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003600 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003601 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003602 .ops = &mv88e6172_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003603 },
3604
3605 [MV88E6175] = {
3606 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3607 .family = MV88E6XXX_FAMILY_6351,
3608 .name = "Marvell 88E6175",
3609 .num_databases = 4096,
3610 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003611 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003612 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003613 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003614 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003615 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003616 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003617 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003618 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003619 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003620 .ops = &mv88e6175_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003621 },
3622
3623 [MV88E6176] = {
3624 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3625 .family = MV88E6XXX_FAMILY_6352,
3626 .name = "Marvell 88E6176",
3627 .num_databases = 4096,
3628 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003629 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003630 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003631 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003632 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003633 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003634 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003635 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003636 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003637 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003638 .ops = &mv88e6176_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003639 },
3640
3641 [MV88E6185] = {
3642 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3643 .family = MV88E6XXX_FAMILY_6185,
3644 .name = "Marvell 88E6185",
3645 .num_databases = 256,
3646 .num_ports = 10,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003647 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003648 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003649 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003650 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003651 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003652 .atu_move_port_mask = 0xf,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003653 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003654 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003655 .ops = &mv88e6185_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003656 },
3657
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003658 [MV88E6190] = {
3659 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3660 .family = MV88E6XXX_FAMILY_6390,
3661 .name = "Marvell 88E6190",
3662 .num_databases = 4096,
3663 .num_ports = 11, /* 10 + Z80 */
3664 .port_base_addr = 0x0,
3665 .global1_addr = 0x1b,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003666 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003667 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003668 .g1_irqs = 9,
Vivien Didelotf3645652017-03-30 17:37:07 -04003669 .pvt = true,
Vivien Didelote606ca32017-03-11 16:12:55 -05003670 .atu_move_port_mask = 0x1f,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003671 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3672 .ops = &mv88e6190_ops,
3673 },
3674
3675 [MV88E6190X] = {
3676 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3677 .family = MV88E6XXX_FAMILY_6390,
3678 .name = "Marvell 88E6190X",
3679 .num_databases = 4096,
3680 .num_ports = 11, /* 10 + Z80 */
3681 .port_base_addr = 0x0,
3682 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003683 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003684 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003685 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003686 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003687 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003688 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3689 .ops = &mv88e6190x_ops,
3690 },
3691
3692 [MV88E6191] = {
3693 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3694 .family = MV88E6XXX_FAMILY_6390,
3695 .name = "Marvell 88E6191",
3696 .num_databases = 4096,
3697 .num_ports = 11, /* 10 + Z80 */
3698 .port_base_addr = 0x0,
3699 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003700 .age_time_coeff = 3750,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003701 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003702 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003703 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003704 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003705 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
Vivien Didelot2cf4cefb2017-03-28 13:50:34 -04003706 .ops = &mv88e6191_ops,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003707 },
3708
Vivien Didelotf81ec902016-05-09 13:22:58 -04003709 [MV88E6240] = {
3710 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3711 .family = MV88E6XXX_FAMILY_6352,
3712 .name = "Marvell 88E6240",
3713 .num_databases = 4096,
3714 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003715 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003716 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003717 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003718 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003719 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003720 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003721 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003722 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003723 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003724 .ops = &mv88e6240_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003725 },
3726
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003727 [MV88E6290] = {
3728 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3729 .family = MV88E6XXX_FAMILY_6390,
3730 .name = "Marvell 88E6290",
3731 .num_databases = 4096,
3732 .num_ports = 11, /* 10 + Z80 */
3733 .port_base_addr = 0x0,
3734 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003735 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003736 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003737 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003738 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003739 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003740 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3741 .ops = &mv88e6290_ops,
3742 },
3743
Vivien Didelotf81ec902016-05-09 13:22:58 -04003744 [MV88E6320] = {
3745 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3746 .family = MV88E6XXX_FAMILY_6320,
3747 .name = "Marvell 88E6320",
3748 .num_databases = 4096,
3749 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003750 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003751 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003752 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003753 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003754 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003755 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003756 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003757 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003758 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003759 .ops = &mv88e6320_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003760 },
3761
3762 [MV88E6321] = {
3763 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3764 .family = MV88E6XXX_FAMILY_6320,
3765 .name = "Marvell 88E6321",
3766 .num_databases = 4096,
3767 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003768 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003769 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003770 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003771 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003772 .g1_irqs = 8,
Vivien Didelote606ca32017-03-11 16:12:55 -05003773 .atu_move_port_mask = 0xf,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003774 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003775 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003776 .ops = &mv88e6321_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003777 },
3778
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01003779 [MV88E6341] = {
3780 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3781 .family = MV88E6XXX_FAMILY_6341,
3782 .name = "Marvell 88E6341",
3783 .num_databases = 4096,
3784 .num_ports = 6,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003785 .max_vid = 4095,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01003786 .port_base_addr = 0x10,
3787 .global1_addr = 0x1b,
3788 .age_time_coeff = 3750,
Vivien Didelote606ca32017-03-11 16:12:55 -05003789 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003790 .pvt = true,
Gregory CLEMENTa75961d2017-01-30 20:29:34 +01003791 .tag_protocol = DSA_TAG_PROTO_EDSA,
3792 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3793 .ops = &mv88e6341_ops,
3794 },
3795
Vivien Didelotf81ec902016-05-09 13:22:58 -04003796 [MV88E6350] = {
3797 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3798 .family = MV88E6XXX_FAMILY_6351,
3799 .name = "Marvell 88E6350",
3800 .num_databases = 4096,
3801 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003802 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003803 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003804 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003805 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003806 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003807 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003808 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003809 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003810 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003811 .ops = &mv88e6350_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003812 },
3813
3814 [MV88E6351] = {
3815 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3816 .family = MV88E6XXX_FAMILY_6351,
3817 .name = "Marvell 88E6351",
3818 .num_databases = 4096,
3819 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003820 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003821 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003822 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003823 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003824 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003825 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003826 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003827 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003828 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003829 .ops = &mv88e6351_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003830 },
3831
3832 [MV88E6352] = {
3833 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3834 .family = MV88E6XXX_FAMILY_6352,
3835 .name = "Marvell 88E6352",
3836 .num_databases = 4096,
3837 .num_ports = 7,
Vivien Didelot3cf3c842017-05-01 14:05:10 -04003838 .max_vid = 4095,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003839 .port_base_addr = 0x10,
Vivien Didelota935c052016-09-29 12:21:53 -04003840 .global1_addr = 0x1b,
Vivien Didelotacddbd22016-07-18 20:45:39 -04003841 .age_time_coeff = 15000,
Andrew Lunndc30c352016-10-16 19:56:49 +02003842 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003843 .atu_move_port_mask = 0xf,
Vivien Didelotf3645652017-03-30 17:37:07 -04003844 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003845 .tag_protocol = DSA_TAG_PROTO_EDSA,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003846 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
Vivien Didelotb3469dd2016-09-29 12:22:00 -04003847 .ops = &mv88e6352_ops,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003848 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003849 [MV88E6390] = {
3850 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3851 .family = MV88E6XXX_FAMILY_6390,
3852 .name = "Marvell 88E6390",
3853 .num_databases = 4096,
3854 .num_ports = 11, /* 10 + Z80 */
3855 .port_base_addr = 0x0,
3856 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003857 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003858 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003859 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003860 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003861 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003862 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3863 .ops = &mv88e6390_ops,
3864 },
3865 [MV88E6390X] = {
3866 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3867 .family = MV88E6XXX_FAMILY_6390,
3868 .name = "Marvell 88E6390X",
3869 .num_databases = 4096,
3870 .num_ports = 11, /* 10 + Z80 */
3871 .port_base_addr = 0x0,
3872 .global1_addr = 0x1b,
Andrew Lunnb91e0552017-02-02 00:46:15 +01003873 .age_time_coeff = 3750,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003874 .g1_irqs = 9,
Vivien Didelote606ca32017-03-11 16:12:55 -05003875 .atu_move_port_mask = 0x1f,
Vivien Didelotf3645652017-03-30 17:37:07 -04003876 .pvt = true,
Andrew Lunn443d5a12016-12-03 04:35:18 +01003877 .tag_protocol = DSA_TAG_PROTO_DSA,
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01003878 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3879 .ops = &mv88e6390x_ops,
3880 },
Vivien Didelotf81ec902016-05-09 13:22:58 -04003881};
3882
Vivien Didelot5f7c0362016-06-20 13:14:04 -04003883static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04003884{
Vivien Didelota439c062016-04-17 13:23:58 -04003885 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04003886
Vivien Didelot5f7c0362016-06-20 13:14:04 -04003887 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3888 if (mv88e6xxx_table[i].prod_num == prod_num)
3889 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04003890
Vivien Didelotb9b37712015-10-30 19:39:48 -04003891 return NULL;
3892}
3893
Vivien Didelotfad09c72016-06-21 12:28:20 -04003894static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003895{
3896 const struct mv88e6xxx_info *info;
Vivien Didelot8f6345b2016-07-20 18:18:36 -04003897 unsigned int prod_num, rev;
3898 u16 id;
3899 int err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003900
Vivien Didelot8f6345b2016-07-20 18:18:36 -04003901 mutex_lock(&chip->reg_lock);
3902 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3903 mutex_unlock(&chip->reg_lock);
3904 if (err)
3905 return err;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003906
3907 prod_num = (id & 0xfff0) >> 4;
3908 rev = id & 0x000f;
3909
3910 info = mv88e6xxx_lookup_info(prod_num);
3911 if (!info)
3912 return -ENODEV;
3913
Vivien Didelotcaac8542016-06-20 13:14:09 -04003914 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003915 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003916
Vivien Didelotca070c12016-09-02 14:45:34 -04003917 err = mv88e6xxx_g2_require(chip);
3918 if (err)
3919 return err;
3920
Vivien Didelotfad09c72016-06-21 12:28:20 -04003921 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3922 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003923
3924 return 0;
3925}
3926
Vivien Didelotfad09c72016-06-21 12:28:20 -04003927static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04003928{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003929 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04003930
Vivien Didelotfad09c72016-06-21 12:28:20 -04003931 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3932 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04003933 return NULL;
3934
Vivien Didelotfad09c72016-06-21 12:28:20 -04003935 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04003936
Vivien Didelotfad09c72016-06-21 12:28:20 -04003937 mutex_init(&chip->reg_lock);
Andrew Lunna3c53be52017-01-24 14:53:50 +01003938 INIT_LIST_HEAD(&chip->mdios);
Vivien Didelot469d7292016-06-20 13:14:06 -04003939
Vivien Didelotfad09c72016-06-21 12:28:20 -04003940 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04003941}
3942
Vivien Didelote57e5e72016-08-15 17:19:00 -04003943static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3944{
Vivien Didelota199d8b2016-12-05 17:30:28 -05003945 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
Vivien Didelote57e5e72016-08-15 17:19:00 -04003946 mv88e6xxx_ppu_state_init(chip);
Vivien Didelote57e5e72016-08-15 17:19:00 -04003947}
3948
Andrew Lunn930188c2016-08-22 16:01:03 +02003949static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3950{
Vivien Didelota199d8b2016-12-05 17:30:28 -05003951 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
Andrew Lunn930188c2016-08-22 16:01:03 +02003952 mv88e6xxx_ppu_state_destroy(chip);
Andrew Lunn930188c2016-08-22 16:01:03 +02003953}
3954
Vivien Didelotfad09c72016-06-21 12:28:20 -04003955static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003956 struct mii_bus *bus, int sw_addr)
3957{
Vivien Didelot914b32f2016-06-20 13:14:11 -04003958 if (sw_addr == 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -04003959 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
Vivien Didelota0ffff22016-08-15 17:18:58 -04003960 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
Vivien Didelotfad09c72016-06-21 12:28:20 -04003961 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
Vivien Didelot914b32f2016-06-20 13:14:11 -04003962 else
3963 return -EINVAL;
3964
Vivien Didelotfad09c72016-06-21 12:28:20 -04003965 chip->bus = bus;
3966 chip->sw_addr = sw_addr;
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003967
3968 return 0;
3969}
3970
Andrew Lunn7b314362016-08-22 16:01:01 +02003971static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3972{
Vivien Didelot04bed142016-08-31 18:06:13 -04003973 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn2bbb33b2016-08-22 16:01:02 +02003974
Andrew Lunn443d5a12016-12-03 04:35:18 +01003975 return chip->info->tag_protocol;
Andrew Lunn7b314362016-08-22 16:01:01 +02003976}
3977
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02003978static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3979 struct device *host_dev, int sw_addr,
3980 void **priv)
Andrew Lunna77d43f2016-04-13 02:40:42 +02003981{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003982 struct mv88e6xxx_chip *chip;
Vivien Didelota439c062016-04-17 13:23:58 -04003983 struct mii_bus *bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003984 int err;
Andrew Lunna77d43f2016-04-13 02:40:42 +02003985
Vivien Didelota439c062016-04-17 13:23:58 -04003986 bus = dsa_host_dev_to_mii_bus(host_dev);
Andrew Lunnc1569132016-04-13 02:40:45 +02003987 if (!bus)
3988 return NULL;
3989
Vivien Didelotfad09c72016-06-21 12:28:20 -04003990 chip = mv88e6xxx_alloc_chip(dsa_dev);
3991 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04003992 return NULL;
3993
Vivien Didelotcaac8542016-06-20 13:14:09 -04003994 /* Legacy SMI probing will only support chips similar to 88E6085 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003995 chip->info = &mv88e6xxx_table[MV88E6085];
Vivien Didelotcaac8542016-06-20 13:14:09 -04003996
Vivien Didelotfad09c72016-06-21 12:28:20 -04003997 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003998 if (err)
3999 goto free;
4000
Vivien Didelotfad09c72016-06-21 12:28:20 -04004001 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004002 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04004003 goto free;
Vivien Didelota439c062016-04-17 13:23:58 -04004004
Andrew Lunndc30c352016-10-16 19:56:49 +02004005 mutex_lock(&chip->reg_lock);
4006 err = mv88e6xxx_switch_reset(chip);
4007 mutex_unlock(&chip->reg_lock);
4008 if (err)
4009 goto free;
4010
Vivien Didelote57e5e72016-08-15 17:19:00 -04004011 mv88e6xxx_phy_init(chip);
4012
Andrew Lunna3c53be52017-01-24 14:53:50 +01004013 err = mv88e6xxx_mdios_register(chip, NULL);
Andrew Lunnb516d452016-06-04 21:17:06 +02004014 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04004015 goto free;
Andrew Lunnb516d452016-06-04 21:17:06 +02004016
Vivien Didelotfad09c72016-06-21 12:28:20 -04004017 *priv = chip;
Vivien Didelota439c062016-04-17 13:23:58 -04004018
Vivien Didelotfad09c72016-06-21 12:28:20 -04004019 return chip->info->name;
Vivien Didelot469d7292016-06-20 13:14:06 -04004020free:
Vivien Didelotfad09c72016-06-21 12:28:20 -04004021 devm_kfree(dsa_dev, chip);
Vivien Didelot469d7292016-06-20 13:14:06 -04004022
4023 return NULL;
Andrew Lunna77d43f2016-04-13 02:40:42 +02004024}
4025
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004026static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4027 const struct switchdev_obj_port_mdb *mdb,
4028 struct switchdev_trans *trans)
4029{
4030 /* We don't need any dynamic resource from the kernel (yet),
4031 * so skip the prepare phase.
4032 */
4033
4034 return 0;
4035}
4036
4037static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4038 const struct switchdev_obj_port_mdb *mdb,
4039 struct switchdev_trans *trans)
4040{
Vivien Didelot04bed142016-08-31 18:06:13 -04004041 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004042
4043 mutex_lock(&chip->reg_lock);
4044 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4045 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4046 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4047 mutex_unlock(&chip->reg_lock);
4048}
4049
4050static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4051 const struct switchdev_obj_port_mdb *mdb)
4052{
Vivien Didelot04bed142016-08-31 18:06:13 -04004053 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004054 int err;
4055
4056 mutex_lock(&chip->reg_lock);
4057 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4058 GLOBAL_ATU_DATA_STATE_UNUSED);
4059 mutex_unlock(&chip->reg_lock);
4060
4061 return err;
4062}
4063
4064static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4065 struct switchdev_obj_port_mdb *mdb,
4066 int (*cb)(struct switchdev_obj *obj))
4067{
Vivien Didelot04bed142016-08-31 18:06:13 -04004068 struct mv88e6xxx_chip *chip = ds->priv;
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004069 int err;
4070
4071 mutex_lock(&chip->reg_lock);
4072 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4073 mutex_unlock(&chip->reg_lock);
4074
4075 return err;
4076}
4077
Florian Fainellia82f67a2017-01-08 14:52:08 -08004078static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02004079 .probe = mv88e6xxx_drv_probe,
Andrew Lunn7b314362016-08-22 16:01:01 +02004080 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004081 .setup = mv88e6xxx_setup,
4082 .set_addr = mv88e6xxx_set_addr,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004083 .adjust_link = mv88e6xxx_adjust_link,
4084 .get_strings = mv88e6xxx_get_strings,
4085 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4086 .get_sset_count = mv88e6xxx_get_sset_count,
4087 .set_eee = mv88e6xxx_set_eee,
4088 .get_eee = mv88e6xxx_get_eee,
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004089 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004090 .get_eeprom = mv88e6xxx_get_eeprom,
4091 .set_eeprom = mv88e6xxx_set_eeprom,
4092 .get_regs_len = mv88e6xxx_get_regs_len,
4093 .get_regs = mv88e6xxx_get_regs,
Vivien Didelot2cfcd962016-07-18 20:45:40 -04004094 .set_ageing_time = mv88e6xxx_set_ageing_time,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004095 .port_bridge_join = mv88e6xxx_port_bridge_join,
4096 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4097 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
Vivien Didelot749efcb2016-09-22 16:49:24 -04004098 .port_fast_age = mv88e6xxx_port_fast_age,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004099 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4100 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4101 .port_vlan_add = mv88e6xxx_port_vlan_add,
4102 .port_vlan_del = mv88e6xxx_port_vlan_del,
4103 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4104 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4105 .port_fdb_add = mv88e6xxx_port_fdb_add,
4106 .port_fdb_del = mv88e6xxx_port_fdb_del,
4107 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
Vivien Didelot7df8fbd2016-08-31 11:50:05 -04004108 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4109 .port_mdb_add = mv88e6xxx_port_mdb_add,
4110 .port_mdb_del = mv88e6xxx_port_mdb_del,
4111 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
Vivien Didelotaec5ac82017-03-30 17:37:15 -04004112 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4113 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
Vivien Didelotf81ec902016-05-09 13:22:58 -04004114};
4115
Florian Fainelliab3d4082017-01-08 14:52:07 -08004116static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4117 .ops = &mv88e6xxx_switch_ops,
4118};
4119
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004120static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004121{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004122 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004123 struct dsa_switch *ds;
4124
Vivien Didelot73b12042017-03-30 17:37:10 -04004125 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004126 if (!ds)
4127 return -ENOMEM;
4128
Vivien Didelotfad09c72016-06-21 12:28:20 -04004129 ds->priv = chip;
Vivien Didelot9d490b42016-08-23 12:38:56 -04004130 ds->ops = &mv88e6xxx_switch_ops;
Vivien Didelot9ff74f22017-03-15 15:53:50 -04004131 ds->ageing_time_min = chip->info->age_time_coeff;
4132 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004133
4134 dev_set_drvdata(dev, ds);
4135
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004136 return dsa_register_switch(ds, dev);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004137}
4138
Vivien Didelotfad09c72016-06-21 12:28:20 -04004139static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004140{
Vivien Didelotfad09c72016-06-21 12:28:20 -04004141 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04004142}
4143
Vivien Didelot57d32312016-06-20 13:13:58 -04004144static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004145{
4146 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004147 struct device_node *np = dev->of_node;
Vivien Didelotcaac8542016-06-20 13:14:09 -04004148 const struct mv88e6xxx_info *compat_info;
Vivien Didelotfad09c72016-06-21 12:28:20 -04004149 struct mv88e6xxx_chip *chip;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004150 u32 eeprom_len;
Andrew Lunn52638f72016-05-10 23:27:22 +02004151 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004152
Vivien Didelotcaac8542016-06-20 13:14:09 -04004153 compat_info = of_device_get_match_data(dev);
4154 if (!compat_info)
4155 return -EINVAL;
4156
Vivien Didelotfad09c72016-06-21 12:28:20 -04004157 chip = mv88e6xxx_alloc_chip(dev);
4158 if (!chip)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004159 return -ENOMEM;
4160
Vivien Didelotfad09c72016-06-21 12:28:20 -04004161 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04004162
Vivien Didelotfad09c72016-06-21 12:28:20 -04004163 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04004164 if (err)
4165 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004166
Andrew Lunnb4308f02016-11-21 23:26:55 +01004167 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4168 if (IS_ERR(chip->reset))
4169 return PTR_ERR(chip->reset);
4170
Vivien Didelotfad09c72016-06-21 12:28:20 -04004171 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04004172 if (err)
4173 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004174
Vivien Didelote57e5e72016-08-15 17:19:00 -04004175 mv88e6xxx_phy_init(chip);
4176
Vivien Didelotee4dc2e72016-09-29 12:22:02 -04004177 if (chip->info->ops->get_eeprom &&
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004178 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
Vivien Didelotfad09c72016-06-21 12:28:20 -04004179 chip->eeprom_len = eeprom_len;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02004180
Andrew Lunndc30c352016-10-16 19:56:49 +02004181 mutex_lock(&chip->reg_lock);
4182 err = mv88e6xxx_switch_reset(chip);
4183 mutex_unlock(&chip->reg_lock);
Andrew Lunnb516d452016-06-04 21:17:06 +02004184 if (err)
Andrew Lunndc30c352016-10-16 19:56:49 +02004185 goto out;
Andrew Lunnb516d452016-06-04 21:17:06 +02004186
Andrew Lunndc30c352016-10-16 19:56:49 +02004187 chip->irq = of_irq_get(np, 0);
4188 if (chip->irq == -EPROBE_DEFER) {
4189 err = chip->irq;
4190 goto out;
Andrew Lunn83c0afa2016-06-04 21:17:07 +02004191 }
4192
Andrew Lunndc30c352016-10-16 19:56:49 +02004193 if (chip->irq > 0) {
4194 /* Has to be performed before the MDIO bus is created,
4195 * because the PHYs will link there interrupts to these
4196 * interrupt controllers
4197 */
4198 mutex_lock(&chip->reg_lock);
4199 err = mv88e6xxx_g1_irq_setup(chip);
4200 mutex_unlock(&chip->reg_lock);
4201
4202 if (err)
4203 goto out;
4204
4205 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4206 err = mv88e6xxx_g2_irq_setup(chip);
4207 if (err)
4208 goto out_g1_irq;
4209 }
4210 }
4211
Andrew Lunna3c53be52017-01-24 14:53:50 +01004212 err = mv88e6xxx_mdios_register(chip, np);
Andrew Lunndc30c352016-10-16 19:56:49 +02004213 if (err)
4214 goto out_g2_irq;
4215
Florian Fainelli55ed0ce2017-01-26 10:45:51 -08004216 err = mv88e6xxx_register_switch(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004217 if (err)
4218 goto out_mdio;
4219
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004220 return 0;
Andrew Lunndc30c352016-10-16 19:56:49 +02004221
4222out_mdio:
Andrew Lunna3c53be52017-01-24 14:53:50 +01004223 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004224out_g2_irq:
Andrew Lunn467126442016-11-20 20:14:15 +01004225 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
Andrew Lunndc30c352016-10-16 19:56:49 +02004226 mv88e6xxx_g2_irq_free(chip);
4227out_g1_irq:
Andrew Lunn61f7c3f2016-11-20 20:14:19 +01004228 if (chip->irq > 0) {
4229 mutex_lock(&chip->reg_lock);
Andrew Lunn467126442016-11-20 20:14:15 +01004230 mv88e6xxx_g1_irq_free(chip);
Andrew Lunn61f7c3f2016-11-20 20:14:19 +01004231 mutex_unlock(&chip->reg_lock);
4232 }
Andrew Lunndc30c352016-10-16 19:56:49 +02004233out:
4234 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004235}
4236
4237static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4238{
4239 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelot04bed142016-08-31 18:06:13 -04004240 struct mv88e6xxx_chip *chip = ds->priv;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004241
Andrew Lunn930188c2016-08-22 16:01:03 +02004242 mv88e6xxx_phy_destroy(chip);
Vivien Didelotfad09c72016-06-21 12:28:20 -04004243 mv88e6xxx_unregister_switch(chip);
Andrew Lunna3c53be52017-01-24 14:53:50 +01004244 mv88e6xxx_mdios_unregister(chip);
Andrew Lunndc30c352016-10-16 19:56:49 +02004245
Andrew Lunn467126442016-11-20 20:14:15 +01004246 if (chip->irq > 0) {
4247 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4248 mv88e6xxx_g2_irq_free(chip);
4249 mv88e6xxx_g1_irq_free(chip);
4250 }
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004251}
4252
4253static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04004254 {
4255 .compatible = "marvell,mv88e6085",
4256 .data = &mv88e6xxx_table[MV88E6085],
4257 },
Andrew Lunn1a3b39e2016-11-21 23:26:57 +01004258 {
4259 .compatible = "marvell,mv88e6190",
4260 .data = &mv88e6xxx_table[MV88E6190],
4261 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004262 { /* sentinel */ },
4263};
4264
4265MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4266
4267static struct mdio_driver mv88e6xxx_driver = {
4268 .probe = mv88e6xxx_probe,
4269 .remove = mv88e6xxx_remove,
4270 .mdiodrv.driver = {
4271 .name = "mv88e6085",
4272 .of_match_table = mv88e6xxx_of_match,
4273 },
4274};
4275
Ben Hutchings98e67302011-11-25 14:36:19 +00004276static int __init mv88e6xxx_init(void)
4277{
Florian Fainelliab3d4082017-01-08 14:52:07 -08004278 register_switch_driver(&mv88e6xxx_switch_drv);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004279 return mdio_driver_register(&mv88e6xxx_driver);
Ben Hutchings98e67302011-11-25 14:36:19 +00004280}
4281module_init(mv88e6xxx_init);
4282
4283static void __exit mv88e6xxx_cleanup(void)
4284{
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004285 mdio_driver_unregister(&mv88e6xxx_driver);
Florian Fainelliab3d4082017-01-08 14:52:07 -08004286 unregister_switch_driver(&mv88e6xxx_switch_drv);
Ben Hutchings98e67302011-11-25 14:36:19 +00004287}
4288module_exit(mv88e6xxx_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00004289
4290MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4291MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4292MODULE_LICENSE("GPL");