Blame - include/linux/mlx5/mlx5_ifc.h - SHIFTPHONES/kernel/common

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Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	1	/*
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2	* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	3	*
				4	* This software is available to you under a choice of one of two
				5	* licenses. You may choose to be licensed under the terms of the GNU
				6	* General Public License (GPL) Version 2, available from the file
				7	* COPYING in the main directory of this source tree, or the
				8	* OpenIB.org BSD license below:
				9	*
				10	* Redistribution and use in source and binary forms, with or
				11	* without modification, are permitted provided that the following
				12	* conditions are met:
				13	*
				14	* - Redistributions of source code must retain the above
				15	* copyright notice, this list of conditions and the following
				16	* disclaimer.
				17	*
				18	* - Redistributions in binary form must reproduce the above
				19	* copyright notice, this list of conditions and the following
				20	* disclaimer in the documentation and/or other materials
				21	* provided with the distribution.
				22	*
				23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
				24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
				25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
				26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
				27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
				28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
				29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
				30	* SOFTWARE.
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	31	*/
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	32	#ifndef MLX5_IFC_H
				33	#define MLX5_IFC_H
				34
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	35	#include "mlx5_ifc_fpga.h"
				36
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	37	enum {
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	38	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
				39	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
				40	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
				41	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
				42	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
				43	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
				44	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
				45	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
				46	MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
				47	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
				48	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
				49	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
				50	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
				51	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
				52	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
				53	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
				54	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
				55	MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
				56	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
				57	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
				58	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
				59	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
				60	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	61	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
				62	MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
Ilan Tayari	1f0cf89	2018-05-30 10:59:50 -0700	[diff] [blame]	63	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	64	};
				65
				66	enum {
				67	MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
				68	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
				69	MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
				70	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
				71	};
				72
				73	enum {
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	74	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
Moni Shoua	46861e3	2019-01-22 08:48:51 +0200	[diff] [blame]	75	MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	76	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
				77	};
				78
				79	enum {
Leon Romanovsky	2acc795	2018-12-06 14:40:11 +0200	[diff] [blame]	80	MLX5_SHARED_RESOURCE_UID = 0xffff,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	81	};
				82
				83	enum {
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	84	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
				85	};
				86
				87	enum {
				88	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
				89	};
				90
				91	enum {
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	92	MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
				93	MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
				94	MLX5_CMD_OP_INIT_HCA = 0x102,
				95	MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
				96	MLX5_CMD_OP_ENABLE_HCA = 0x104,
				97	MLX5_CMD_OP_DISABLE_HCA = 0x105,
				98	MLX5_CMD_OP_QUERY_PAGES = 0x107,
				99	MLX5_CMD_OP_MANAGE_PAGES = 0x108,
				100	MLX5_CMD_OP_SET_HCA_CAP = 0x109,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	101	MLX5_CMD_OP_QUERY_ISSI = 0x10a,
				102	MLX5_CMD_OP_SET_ISSI = 0x10b,
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	103	MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	104	MLX5_CMD_OP_CREATE_MKEY = 0x200,
				105	MLX5_CMD_OP_QUERY_MKEY = 0x201,
				106	MLX5_CMD_OP_DESTROY_MKEY = 0x202,
				107	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
				108	MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
Ariel Levkovich	24da001	2018-04-05 18:53:27 +0300	[diff] [blame]	109	MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
				110	MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	111	MLX5_CMD_OP_CREATE_EQ = 0x301,
				112	MLX5_CMD_OP_DESTROY_EQ = 0x302,
				113	MLX5_CMD_OP_QUERY_EQ = 0x303,
				114	MLX5_CMD_OP_GEN_EQE = 0x304,
				115	MLX5_CMD_OP_CREATE_CQ = 0x400,
				116	MLX5_CMD_OP_DESTROY_CQ = 0x401,
				117	MLX5_CMD_OP_QUERY_CQ = 0x402,
				118	MLX5_CMD_OP_MODIFY_CQ = 0x403,
				119	MLX5_CMD_OP_CREATE_QP = 0x500,
				120	MLX5_CMD_OP_DESTROY_QP = 0x501,
				121	MLX5_CMD_OP_RST2INIT_QP = 0x502,
				122	MLX5_CMD_OP_INIT2RTR_QP = 0x503,
				123	MLX5_CMD_OP_RTR2RTS_QP = 0x504,
				124	MLX5_CMD_OP_RTS2RTS_QP = 0x505,
				125	MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
				126	MLX5_CMD_OP_2ERR_QP = 0x507,
				127	MLX5_CMD_OP_2RST_QP = 0x50a,
				128	MLX5_CMD_OP_QUERY_QP = 0x50b,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	129	MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	130	MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
				131	MLX5_CMD_OP_CREATE_PSV = 0x600,
				132	MLX5_CMD_OP_DESTROY_PSV = 0x601,
				133	MLX5_CMD_OP_CREATE_SRQ = 0x700,
				134	MLX5_CMD_OP_DESTROY_SRQ = 0x701,
				135	MLX5_CMD_OP_QUERY_SRQ = 0x702,
				136	MLX5_CMD_OP_ARM_RQ = 0x703,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	137	MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
				138	MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
				139	MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
				140	MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	141	MLX5_CMD_OP_CREATE_DCT = 0x710,
				142	MLX5_CMD_OP_DESTROY_DCT = 0x711,
				143	MLX5_CMD_OP_DRAIN_DCT = 0x712,
				144	MLX5_CMD_OP_QUERY_DCT = 0x713,
				145	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	146	MLX5_CMD_OP_CREATE_XRQ = 0x717,
				147	MLX5_CMD_OP_DESTROY_XRQ = 0x718,
				148	MLX5_CMD_OP_QUERY_XRQ = 0x719,
				149	MLX5_CMD_OP_ARM_XRQ = 0x71a,
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	150	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
				151	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
				152	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
Bodong Wang	c3a4e9f	2019-02-12 22:55:37 -0800	[diff] [blame]	153	MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	154	MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
				155	MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
				156	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
				157	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
				158	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
				159	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	160	MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	161	MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	162	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
				163	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
				164	MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
				165	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	166	MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	167	MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
				168	MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
				169	MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
				170	MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	171	MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
				172	MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	173	MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	174	MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	175	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
				176	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
				177	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
				178	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
				179	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
				180	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	181	MLX5_CMD_OP_ALLOC_PD = 0x800,
				182	MLX5_CMD_OP_DEALLOC_PD = 0x801,
				183	MLX5_CMD_OP_ALLOC_UAR = 0x802,
				184	MLX5_CMD_OP_DEALLOC_UAR = 0x803,
				185	MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
				186	MLX5_CMD_OP_ACCESS_REG = 0x805,
				187	MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
Saeed Mahameed	20bb566	2016-07-17 02:01:45 +0300	[diff] [blame]	188	MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	189	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
				190	MLX5_CMD_OP_MAD_IFC = 0x50d,
				191	MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
				192	MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
				193	MLX5_CMD_OP_NOP = 0x80d,
				194	MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
				195	MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	196	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
				197	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
				198	MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
				199	MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
				200	MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
				201	MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
				202	MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
				203	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
				204	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
				205	MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
				206	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
				207	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	208	MLX5_CMD_OP_SET_WOL_ROL = 0x830,
				209	MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	210	MLX5_CMD_OP_CREATE_LAG = 0x840,
				211	MLX5_CMD_OP_MODIFY_LAG = 0x841,
				212	MLX5_CMD_OP_QUERY_LAG = 0x842,
				213	MLX5_CMD_OP_DESTROY_LAG = 0x843,
				214	MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
				215	MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	216	MLX5_CMD_OP_CREATE_TIR = 0x900,
				217	MLX5_CMD_OP_MODIFY_TIR = 0x901,
				218	MLX5_CMD_OP_DESTROY_TIR = 0x902,
				219	MLX5_CMD_OP_QUERY_TIR = 0x903,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	220	MLX5_CMD_OP_CREATE_SQ = 0x904,
				221	MLX5_CMD_OP_MODIFY_SQ = 0x905,
				222	MLX5_CMD_OP_DESTROY_SQ = 0x906,
				223	MLX5_CMD_OP_QUERY_SQ = 0x907,
				224	MLX5_CMD_OP_CREATE_RQ = 0x908,
				225	MLX5_CMD_OP_MODIFY_RQ = 0x909,
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	226	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	227	MLX5_CMD_OP_DESTROY_RQ = 0x90a,
				228	MLX5_CMD_OP_QUERY_RQ = 0x90b,
				229	MLX5_CMD_OP_CREATE_RMP = 0x90c,
				230	MLX5_CMD_OP_MODIFY_RMP = 0x90d,
				231	MLX5_CMD_OP_DESTROY_RMP = 0x90e,
				232	MLX5_CMD_OP_QUERY_RMP = 0x90f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	233	MLX5_CMD_OP_CREATE_TIS = 0x912,
				234	MLX5_CMD_OP_MODIFY_TIS = 0x913,
				235	MLX5_CMD_OP_DESTROY_TIS = 0x914,
				236	MLX5_CMD_OP_QUERY_TIS = 0x915,
				237	MLX5_CMD_OP_CREATE_RQT = 0x916,
				238	MLX5_CMD_OP_MODIFY_RQT = 0x917,
				239	MLX5_CMD_OP_DESTROY_RQT = 0x918,
				240	MLX5_CMD_OP_QUERY_RQT = 0x919,
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	241	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	242	MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
				243	MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
				244	MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
				245	MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
				246	MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
				247	MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
				248	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
				249	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	250	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	251	MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
				252	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
				253	MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
Shahar Klein	86d56a1	2016-06-10 00:07:30 +0300	[diff] [blame]	254	MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	255	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
				256	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	257	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	258	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
				259	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
Yishai Hadas	e662e14	2018-06-17 13:00:02 +0300	[diff] [blame]	260	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
Ilan Tayari	6062118	2017-03-27 14:52:09 +0300	[diff] [blame]	261	MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
				262	MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
				263	MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
				264	MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
				265	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	266	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
Yishai Hadas	e662e14	2018-06-17 13:00:02 +0300	[diff] [blame]	267	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
				268	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	269	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	270	MLX5_CMD_OP_CREATE_UCTX = 0xa04,
				271	MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
				272	MLX5_CMD_OP_CREATE_UMEM = 0xa08,
				273	MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
Shahar Klein	86d56a1	2016-06-10 00:07:30 +0300	[diff] [blame]	274	MLX5_CMD_OP_MAX
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	275	};
				276
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	277	/* Valid range for general commands that don't work over an object */
				278	enum {
				279	MLX5_CMD_OP_GENERAL_START = 0xb00,
				280	MLX5_CMD_OP_GENERAL_END = 0xd00,
				281	};
				282
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	283	struct mlx5_ifc_flow_table_fields_supported_bits {
				284	u8 outer_dmac[0x1];
				285	u8 outer_smac[0x1];
				286	u8 outer_ether_type[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	287	u8 outer_ip_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	288	u8 outer_first_prio[0x1];
				289	u8 outer_first_cfi[0x1];
				290	u8 outer_first_vid[0x1];
Or Gerlitz	a8ade55	2017-06-07 17:49:56 +0300	[diff] [blame]	291	u8 outer_ipv4_ttl[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	292	u8 outer_second_prio[0x1];
				293	u8 outer_second_cfi[0x1];
				294	u8 outer_second_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	295	u8 reserved_at_b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	296	u8 outer_sip[0x1];
				297	u8 outer_dip[0x1];
				298	u8 outer_frag[0x1];
				299	u8 outer_ip_protocol[0x1];
				300	u8 outer_ip_ecn[0x1];
				301	u8 outer_ip_dscp[0x1];
				302	u8 outer_udp_sport[0x1];
				303	u8 outer_udp_dport[0x1];
				304	u8 outer_tcp_sport[0x1];
				305	u8 outer_tcp_dport[0x1];
				306	u8 outer_tcp_flags[0x1];
				307	u8 outer_gre_protocol[0x1];
				308	u8 outer_gre_key[0x1];
				309	u8 outer_vxlan_vni[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	310	u8 reserved_at_1a[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	311	u8 source_eswitch_port[0x1];
				312
				313	u8 inner_dmac[0x1];
				314	u8 inner_smac[0x1];
				315	u8 inner_ether_type[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	316	u8 inner_ip_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	317	u8 inner_first_prio[0x1];
				318	u8 inner_first_cfi[0x1];
				319	u8 inner_first_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	320	u8 reserved_at_27[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	321	u8 inner_second_prio[0x1];
				322	u8 inner_second_cfi[0x1];
				323	u8 inner_second_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	324	u8 reserved_at_2b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	325	u8 inner_sip[0x1];
				326	u8 inner_dip[0x1];
				327	u8 inner_frag[0x1];
				328	u8 inner_ip_protocol[0x1];
				329	u8 inner_ip_ecn[0x1];
				330	u8 inner_ip_dscp[0x1];
				331	u8 inner_udp_sport[0x1];
				332	u8 inner_udp_dport[0x1];
				333	u8 inner_tcp_sport[0x1];
				334	u8 inner_tcp_dport[0x1];
				335	u8 inner_tcp_flags[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	336	u8 reserved_at_37[0x9];
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	337
				338	u8 reserved_at_40[0x5];
				339	u8 outer_first_mpls_over_udp[0x4];
				340	u8 outer_first_mpls_over_gre[0x4];
				341	u8 inner_first_mpls[0x4];
				342	u8 outer_first_mpls[0x4];
				343	u8 reserved_at_55[0x2];
Boris Pismenny	3346c48	2017-08-20 15:13:08 +0300	[diff] [blame]	344	u8 outer_esp_spi[0x1];
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	345	u8 reserved_at_58[0x2];
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	346	u8 bth_dst_qp[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	347
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	348	u8 reserved_at_5b[0x25];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	349	};
				350
				351	struct mlx5_ifc_flow_table_prop_layout_bits {
				352	u8 ft_support[0x1];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	353	u8 reserved_at_1[0x1];
				354	u8 flow_counter[0x1];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	355	u8 flow_modify_en[0x1];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	356	u8 modify_root[0x1];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	357	u8 identified_miss_table_mode[0x1];
				358	u8 flow_table_modify[0x1];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	359	u8 reformat[0x1];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	360	u8 decap[0x1];
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	361	u8 reserved_at_9[0x1];
				362	u8 pop_vlan[0x1];
				363	u8 push_vlan[0x1];
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	364	u8 reserved_at_c[0x1];
				365	u8 pop_vlan_2[0x1];
				366	u8 push_vlan_2[0x1];
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	367	u8 reformat_and_vlan_action[0x1];
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	368	u8 reserved_at_10[0x1];
				369	u8 sw_owner[0x1];
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	370	u8 reformat_l3_tunnel_to_l2[0x1];
				371	u8 reformat_l2_to_l3_tunnel[0x1];
				372	u8 reformat_and_modify_action[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	373	u8 reserved_at_15[0xb];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	374	u8 reserved_at_20[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	375	u8 log_max_ft_size[0x6];
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	376	u8 log_max_modify_header_context[0x8];
				377	u8 max_modify_header_actions[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	378	u8 max_ft_level[0x8];
				379
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	380	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	381
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	382	u8 reserved_at_60[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	383	u8 log_max_ft_num[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	384
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	385	u8 reserved_at_80[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	386	u8 log_max_destination[0x8];
				387
Raed Salem	16f1c5b	2017-07-30 11:02:51 +0300	[diff] [blame]	388	u8 log_max_flow_counter[0x8];
				389	u8 reserved_at_a8[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	390	u8 log_max_flow[0x8];
				391
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	392	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	393
				394	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
				395
				396	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
				397	};
				398
				399	struct mlx5_ifc_odp_per_transport_service_cap_bits {
				400	u8 send[0x1];
				401	u8 receive[0x1];
				402	u8 write[0x1];
				403	u8 read[0x1];
Artemy Kovalyov	17d2f88	2017-01-02 11:37:47 +0200	[diff] [blame]	404	u8 atomic[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	405	u8 srq_receive[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	406	u8 reserved_at_6[0x1a];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	407	};
				408
				409	struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
				410	u8 smac_47_16[0x20];
				411
				412	u8 smac_15_0[0x10];
				413	u8 ethertype[0x10];
				414
				415	u8 dmac_47_16[0x20];
				416
				417	u8 dmac_15_0[0x10];
				418	u8 first_prio[0x3];
				419	u8 first_cfi[0x1];
				420	u8 first_vid[0xc];
				421
				422	u8 ip_protocol[0x8];
				423	u8 ip_dscp[0x6];
				424	u8 ip_ecn[0x2];
Mohamad Haj Yahia	1054336	2016-10-09 16:25:43 +0300	[diff] [blame]	425	u8 cvlan_tag[0x1];
				426	u8 svlan_tag[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	427	u8 frag[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	428	u8 ip_version[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	429	u8 tcp_flags[0x9];
				430
				431	u8 tcp_sport[0x10];
				432	u8 tcp_dport[0x10];
				433
Or Gerlitz	a8ade55	2017-06-07 17:49:56 +0300	[diff] [blame]	434	u8 reserved_at_c0[0x18];
				435	u8 ttl_hoplimit[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	436
				437	u8 udp_sport[0x10];
				438	u8 udp_dport[0x10];
				439
Maor Gottlieb	b4d1f03	2016-01-11 10:26:05 +0200	[diff] [blame]	440	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	441
Maor Gottlieb	b4d1f03	2016-01-11 10:26:05 +0200	[diff] [blame]	442	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	443	};
				444
Oz Shlomo	5886a96	2018-12-10 13:15:13 -0800	[diff] [blame]	445	struct mlx5_ifc_nvgre_key_bits {
				446	u8 hi[0x18];
				447	u8 lo[0x8];
				448	};
				449
				450	union mlx5_ifc_gre_key_bits {
				451	struct mlx5_ifc_nvgre_key_bits nvgre;
				452	u8 key[0x20];
				453	};
				454
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	455	struct mlx5_ifc_fte_match_set_misc_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	456	u8 reserved_at_0[0x8];
				457	u8 source_sqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	458
Shahar Klein	3e99df8	2018-03-18 09:02:06 +0200	[diff] [blame]	459	u8 source_eswitch_owner_vhca_id[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	460	u8 source_port[0x10];
				461
				462	u8 outer_second_prio[0x3];
				463	u8 outer_second_cfi[0x1];
				464	u8 outer_second_vid[0xc];
				465	u8 inner_second_prio[0x3];
				466	u8 inner_second_cfi[0x1];
				467	u8 inner_second_vid[0xc];
				468
Mohamad Haj Yahia	1054336	2016-10-09 16:25:43 +0300	[diff] [blame]	469	u8 outer_second_cvlan_tag[0x1];
				470	u8 inner_second_cvlan_tag[0x1];
				471	u8 outer_second_svlan_tag[0x1];
				472	u8 inner_second_svlan_tag[0x1];
				473	u8 reserved_at_64[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	474	u8 gre_protocol[0x10];
				475
Oz Shlomo	5886a96	2018-12-10 13:15:13 -0800	[diff] [blame]	476	union mlx5_ifc_gre_key_bits gre_key;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	477
				478	u8 vxlan_vni[0x18];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	479	u8 reserved_at_b8[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	480
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	481	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	482
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	483	u8 reserved_at_e0[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	484	u8 outer_ipv6_flow_label[0x14];
				485
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	486	u8 reserved_at_100[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	487	u8 inner_ipv6_flow_label[0x14];
				488
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	489	u8 reserved_at_120[0x28];
				490	u8 bth_dst_qp[0x18];
Boris Pismenny	3346c48	2017-08-20 15:13:08 +0300	[diff] [blame]	491	u8 reserved_at_160[0x20];
				492	u8 outer_esp_spi[0x20];
				493	u8 reserved_at_1a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	494	};
				495
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	496	struct mlx5_ifc_fte_match_mpls_bits {
				497	u8 mpls_label[0x14];
				498	u8 mpls_exp[0x3];
				499	u8 mpls_s_bos[0x1];
				500	u8 mpls_ttl[0x8];
				501	};
				502
				503	struct mlx5_ifc_fte_match_set_misc2_bits {
				504	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
				505
				506	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
				507
				508	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
				509
				510	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
				511
				512	u8 reserved_at_80[0x100];
				513
				514	u8 metadata_reg_a[0x20];
				515
				516	u8 reserved_at_1a0[0x60];
				517	};
				518
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	519	struct mlx5_ifc_cmd_pas_bits {
				520	u8 pa_h[0x20];
				521
				522	u8 pa_l[0x14];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	523	u8 reserved_at_34[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	524	};
				525
				526	struct mlx5_ifc_uint64_bits {
				527	u8 hi[0x20];
				528
				529	u8 lo[0x20];
				530	};
				531
				532	enum {
				533	MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
				534	MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
				535	MLX5_ADS_STAT_RATE_10GBPS = 0x8,
				536	MLX5_ADS_STAT_RATE_30GBPS = 0x9,
				537	MLX5_ADS_STAT_RATE_5GBPS = 0xa,
				538	MLX5_ADS_STAT_RATE_20GBPS = 0xb,
				539	MLX5_ADS_STAT_RATE_40GBPS = 0xc,
				540	MLX5_ADS_STAT_RATE_60GBPS = 0xd,
				541	MLX5_ADS_STAT_RATE_80GBPS = 0xe,
				542	MLX5_ADS_STAT_RATE_120GBPS = 0xf,
				543	};
				544
				545	struct mlx5_ifc_ads_bits {
				546	u8 fl[0x1];
				547	u8 free_ar[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	548	u8 reserved_at_2[0xe];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	549	u8 pkey_index[0x10];
				550
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	551	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	552	u8 grh[0x1];
				553	u8 mlid[0x7];
				554	u8 rlid[0x10];
				555
				556	u8 ack_timeout[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	557	u8 reserved_at_45[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	558	u8 src_addr_index[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	559	u8 reserved_at_50[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	560	u8 stat_rate[0x4];
				561	u8 hop_limit[0x8];
				562
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	563	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	564	u8 tclass[0x8];
				565	u8 flow_label[0x14];
				566
				567	u8 rgid_rip[16][0x8];
				568
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	569	u8 reserved_at_100[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	570	u8 f_dscp[0x1];
				571	u8 f_ecn[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	572	u8 reserved_at_106[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	573	u8 f_eth_prio[0x1];
				574	u8 ecn[0x2];
				575	u8 dscp[0x6];
				576	u8 udp_sport[0x10];
				577
				578	u8 dei_cfi[0x1];
				579	u8 eth_prio[0x3];
				580	u8 sl[0x4];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	581	u8 vhca_port_num[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	582	u8 rmac_47_32[0x10];
				583
				584	u8 rmac_31_0[0x20];
				585	};
				586
				587	struct mlx5_ifc_flow_table_nic_cap_bits {
Maor Gottlieb	b3638e1	2016-03-07 18:51:46 +0200	[diff] [blame]	588	u8 nic_rx_multi_path_tirs[0x1];
Maor Gottlieb	cea824d	2016-05-31 14:09:09 +0300	[diff] [blame]	589	u8 nic_rx_multi_path_tirs_fts[0x1];
				590	u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	591	u8 reserved_at_3[0x1d];
				592	u8 encap_general_header[0x1];
				593	u8 reserved_at_21[0xa];
				594	u8 log_max_packet_reformat_context[0x5];
				595	u8 reserved_at_30[0x6];
				596	u8 max_encap_header_size[0xa];
				597	u8 reserved_at_40[0x1c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	598
				599	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
				600
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	601	u8 reserved_at_400[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	602
				603	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
				604
				605	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
				606
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	607	u8 reserved_at_a00[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	608
				609	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
				610
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	611	u8 reserved_at_e00[0x7200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	612	};
				613
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	614	struct mlx5_ifc_flow_table_eswitch_cap_bits {
Vu Pham	663f146	2018-10-31 16:03:21 +0200	[diff] [blame]	615	u8 reserved_at_0[0x1a];
Paul Blakey	b9aa0ba	2018-05-31 11:50:23 +0300	[diff] [blame]	616	u8 multi_fdb_encap[0x1];
Vu Pham	663f146	2018-10-31 16:03:21 +0200	[diff] [blame]	617	u8 reserved_at_1b[0x1];
				618	u8 fdb_multi_path_to_table[0x1];
				619	u8 reserved_at_1d[0x3];
				620
				621	u8 reserved_at_20[0x1e0];
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	622
				623	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
				624
				625	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
				626
				627	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
				628
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	629	u8 reserved_at_800[0x7800];
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	630	};
				631
Shahar Klein	8bb957d	2018-12-12 19:11:38 -0800	[diff] [blame]	632	enum {
				633	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
				634	MLX5_COUNTER_FLOW_ESWITCH = 0x1,
				635	};
				636
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	637	struct mlx5_ifc_e_switch_cap_bits {
				638	u8 vport_svlan_strip[0x1];
				639	u8 vport_cvlan_strip[0x1];
				640	u8 vport_svlan_insert[0x1];
				641	u8 vport_cvlan_insert_if_not_exist[0x1];
				642	u8 vport_cvlan_insert_overwrite[0x1];
Bodong Wang	81cd229	2018-12-10 11:59:33 -0600	[diff] [blame]	643	u8 reserved_at_5[0x16];
				644	u8 ecpf_vport_exists[0x1];
Shahar Klein	8bb957d	2018-12-12 19:11:38 -0800	[diff] [blame]	645	u8 counter_eswitch_affinity[0x1];
Roi Dayan	a6d0456	2017-12-05 10:38:58 +0200	[diff] [blame]	646	u8 merged_eswitch[0x1];
Noa Osherovich	23898c7	2016-06-10 00:07:37 +0300	[diff] [blame]	647	u8 nic_vport_node_guid_modify[0x1];
				648	u8 nic_vport_port_guid_modify[0x1];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	649
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	650	u8 vxlan_encap_decap[0x1];
				651	u8 nvgre_encap_decap[0x1];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	652	u8 reserved_at_22[0x1];
				653	u8 log_max_fdb_encap_uplink[0x5];
				654	u8 reserved_at_21[0x3];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	655	u8 log_max_packet_reformat_context[0x5];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	656	u8 reserved_2b[0x6];
				657	u8 max_encap_header_size[0xa];
				658
				659	u8 reserved_40[0x7c0];
				660
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	661	};
				662
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	663	struct mlx5_ifc_qos_cap_bits {
				664	u8 packet_pacing[0x1];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	665	u8 esw_scheduling[0x1];
Mohamad Haj Yahia	c9497c9	2016-12-15 14:02:53 +0200	[diff] [blame]	666	u8 esw_bw_share[0x1];
				667	u8 esw_rate_limit[0x1];
Bodong Wang	05d3ac9	2018-03-19 15:10:29 +0200	[diff] [blame]	668	u8 reserved_at_4[0x1];
				669	u8 packet_pacing_burst_bound[0x1];
				670	u8 packet_pacing_typical_size[0x1];
				671	u8 reserved_at_7[0x19];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	672
				673	u8 reserved_at_20[0x20];
				674
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	675	u8 packet_pacing_max_rate[0x20];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	676
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	677	u8 packet_pacing_min_rate[0x20];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	678
				679	u8 reserved_at_80[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	680	u8 packet_pacing_rate_table_size[0x10];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	681
				682	u8 esw_element_type[0x10];
				683	u8 esw_tsar_type[0x10];
				684
				685	u8 reserved_at_c0[0x10];
				686	u8 max_qos_para_vport[0x10];
				687
				688	u8 max_tsar_bw_share[0x20];
				689
				690	u8 reserved_at_100[0x700];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	691	};
				692
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	693	struct mlx5_ifc_debug_cap_bits {
				694	u8 reserved_at_0[0x20];
				695
				696	u8 reserved_at_20[0x2];
				697	u8 stall_detect[0x1];
				698	u8 reserved_at_23[0x1d];
				699
				700	u8 reserved_at_40[0x7c0];
				701	};
				702
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	703	struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
				704	u8 csum_cap[0x1];
				705	u8 vlan_cap[0x1];
				706	u8 lro_cap[0x1];
				707	u8 lro_psh_flag[0x1];
				708	u8 lro_time_stamp[0x1];
Saeed Mahameed	2b31f7a	2016-11-28 18:04:50 +0200	[diff] [blame]	709	u8 reserved_at_5[0x2];
				710	u8 wqe_vlan_insert[0x1];
Tariq Toukan	6618996	2015-11-12 19:35:26 +0200	[diff] [blame]	711	u8 self_lb_en_modifiable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	712	u8 reserved_at_9[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	713	u8 max_lso_cap[0x5];
Leon Romanovsky	c226dc2	2016-10-31 12:15:20 +0200	[diff] [blame]	714	u8 multi_pkt_send_wqe[0x2];
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	715	u8 wqe_inline_mode[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	716	u8 rss_ind_tbl_cap[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	717	u8 reg_umr_sq[0x1];
				718	u8 scatter_fcs[0x1];
Bodong Wang	050da90	2017-08-17 15:52:35 +0300	[diff] [blame]	719	u8 enhanced_multi_pkt_send_wqe[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	720	u8 tunnel_lso_const_out_ip_id[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	721	u8 reserved_at_1c[0x2];
Gal Pressman	2729984	2017-08-13 13:34:42 +0300	[diff] [blame]	722	u8 tunnel_stateless_gre[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	723	u8 tunnel_stateless_vxlan[0x1];
				724
Ilan Tayari	547eede	2017-04-18 16:04:28 +0300	[diff] [blame]	725	u8 swp[0x1];
				726	u8 swp_csum[0x1];
				727	u8 swp_lso[0x1];
Gal Pressman	22a65aa	2017-12-25 18:40:52 +0200	[diff] [blame]	728	u8 reserved_at_23[0xd];
				729	u8 max_vxlan_udp_ports[0x8];
				730	u8 reserved_at_38[0x6];
Maor Gottlieb	4d350f1	2017-10-19 08:25:54 +0300	[diff] [blame]	731	u8 max_geneve_opt_len[0x1];
				732	u8 tunnel_stateless_geneve_rx[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	733
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	734	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	735	u8 lro_min_mss_size[0x10];
				736
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	737	u8 reserved_at_60[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	738
				739	u8 lro_timer_supported_periods[4][0x20];
				740
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	741	u8 reserved_at_200[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	742	};
				743
				744	struct mlx5_ifc_roce_cap_bits {
				745	u8 roce_apm[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	746	u8 reserved_at_1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	747
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	748	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	749
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	750	u8 reserved_at_80[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	751	u8 l3_type[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	752	u8 reserved_at_90[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	753	u8 roce_version[0x8];
				754
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	755	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	756	u8 r_roce_dest_udp_port[0x10];
				757
				758	u8 r_roce_max_src_udp_port[0x10];
				759	u8 r_roce_min_src_udp_port[0x10];
				760
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	761	u8 reserved_at_e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	762	u8 roce_address_table_size[0x10];
				763
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	764	u8 reserved_at_100[0x700];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	765	};
				766
Ariel Levkovich	e72bd81	2018-04-05 18:53:26 +0300	[diff] [blame]	767	struct mlx5_ifc_device_mem_cap_bits {
				768	u8 memic[0x1];
				769	u8 reserved_at_1[0x1f];
				770
				771	u8 reserved_at_20[0xb];
				772	u8 log_min_memic_alloc_size[0x5];
				773	u8 reserved_at_30[0x8];
				774	u8 log_max_memic_addr_alignment[0x8];
				775
				776	u8 memic_bar_start_addr[0x40];
				777
				778	u8 memic_bar_size[0x20];
				779
				780	u8 max_memic_size[0x20];
				781
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	782	u8 steering_sw_icm_start_address[0x40];
				783
				784	u8 reserved_at_100[0x8];
				785	u8 log_header_modify_sw_icm_size[0x8];
				786	u8 reserved_at_110[0x2];
				787	u8 log_sw_icm_alloc_granularity[0x6];
				788	u8 log_steering_sw_icm_size[0x8];
				789
				790	u8 reserved_at_120[0x20];
				791
				792	u8 header_modify_sw_icm_start_address[0x40];
				793
				794	u8 reserved_at_180[0x680];
Ariel Levkovich	e72bd81	2018-04-05 18:53:26 +0300	[diff] [blame]	795	};
				796
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	797	enum {
				798	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
				799	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
				800	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
				801	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
				802	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
				803	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
				804	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
				805	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
				806	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
				807	};
				808
				809	enum {
				810	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
				811	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
				812	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
				813	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
				814	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
				815	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
				816	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
				817	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
				818	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
				819	};
				820
				821	struct mlx5_ifc_atomic_caps_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	822	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	823
Or Gerlitz	bd10838	2017-05-28 15:24:17 +0300	[diff] [blame]	824	u8 atomic_req_8B_endianness_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	825	u8 reserved_at_42[0x4];
Or Gerlitz	bd10838	2017-05-28 15:24:17 +0300	[diff] [blame]	826	u8 supported_atomic_req_8B_endianness_mode_1[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	827
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	828	u8 reserved_at_47[0x19];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	829
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	830	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	831
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	832	u8 reserved_at_80[0x10];
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	833	u8 atomic_operations[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	834
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	835	u8 reserved_at_a0[0x10];
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	836	u8 atomic_size_qp[0x10];
				837
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	838	u8 reserved_at_c0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	839	u8 atomic_size_dc[0x10];
				840
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	841	u8 reserved_at_e0[0x720];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	842	};
				843
				844	struct mlx5_ifc_odp_cap_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	845	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	846
				847	u8 sig[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	848	u8 reserved_at_41[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	849
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	850	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	851
				852	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
				853
				854	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
				855
				856	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
				857
Moni Shoua	dda7a81	2019-01-22 08:48:49 +0200	[diff] [blame]	858	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
				859
				860	u8 reserved_at_100[0x700];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	861	};
				862
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	863	struct mlx5_ifc_calc_op {
				864	u8 reserved_at_0[0x10];
				865	u8 reserved_at_10[0x9];
				866	u8 op_swap_endianness[0x1];
				867	u8 op_min[0x1];
				868	u8 op_xor[0x1];
				869	u8 op_or[0x1];
				870	u8 op_and[0x1];
				871	u8 op_max[0x1];
				872	u8 op_add[0x1];
				873	};
				874
				875	struct mlx5_ifc_vector_calc_cap_bits {
				876	u8 calc_matrix[0x1];
				877	u8 reserved_at_1[0x1f];
				878	u8 reserved_at_20[0x8];
				879	u8 max_vec_count[0x8];
				880	u8 reserved_at_30[0xd];
				881	u8 max_chunk_size[0x3];
				882	struct mlx5_ifc_calc_op calc0;
				883	struct mlx5_ifc_calc_op calc1;
				884	struct mlx5_ifc_calc_op calc2;
				885	struct mlx5_ifc_calc_op calc3;
				886
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	887	u8 reserved_at_c0[0x720];
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	888	};
				889
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	890	enum {
				891	MLX5_WQ_TYPE_LINKED_LIST = 0x0,
				892	MLX5_WQ_TYPE_CYCLIC = 0x1,
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	893	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
Noa Osherovich	ccc87087	2017-10-17 18:01:13 +0300	[diff] [blame]	894	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	895	};
				896
				897	enum {
				898	MLX5_WQ_END_PAD_MODE_NONE = 0x0,
				899	MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
				900	};
				901
				902	enum {
				903	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
				904	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
				905	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
				906	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
				907	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
				908	};
				909
				910	enum {
				911	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
				912	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
				913	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
				914	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
				915	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
				916	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
				917	};
				918
				919	enum {
				920	MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
				921	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
				922	};
				923
				924	enum {
				925	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
				926	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
				927	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
				928	};
				929
				930	enum {
				931	MLX5_CAP_PORT_TYPE_IB = 0x0,
				932	MLX5_CAP_PORT_TYPE_ETH = 0x1,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	933	};
				934
Max Gurtovoy	1410a90	2017-05-28 10:53:10 +0300	[diff] [blame]	935	enum {
				936	MLX5_CAP_UMR_FENCE_STRONG = 0x0,
				937	MLX5_CAP_UMR_FENCE_SMALL = 0x1,
				938	MLX5_CAP_UMR_FENCE_NONE = 0x2,
				939	};
				940
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	941	enum {
				942	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	943	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	944	};
				945
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	946	struct mlx5_ifc_cmd_hca_cap_bits {
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	947	u8 reserved_at_0[0x30];
				948	u8 vhca_id[0x10];
				949
				950	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	951
				952	u8 log_max_srq_sz[0x8];
				953	u8 log_max_qp_sz[0x8];
Eli Britstein	316793f	2019-04-29 18:14:01 +0000	[diff] [blame^]	954	u8 reserved_at_90[0x8];
				955	u8 prio_tag_required[0x1];
				956	u8 reserved_at_99[0x2];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	957	u8 log_max_qp[0x5];
				958
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	959	u8 reserved_at_a0[0xb];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	960	u8 log_max_srq[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	961	u8 reserved_at_b0[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	962
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	963	u8 reserved_at_c0[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	964	u8 log_max_cq_sz[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	965	u8 reserved_at_d0[0xb];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	966	u8 log_max_cq[0x5];
				967
				968	u8 log_max_eq_sz[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	969	u8 reserved_at_e8[0x2];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	970	u8 log_max_mkey[0x6];
Leon Romanovsky	b183ee2	2018-06-19 08:47:23 +0300	[diff] [blame]	971	u8 reserved_at_f0[0x8];
				972	u8 dump_fill_mkey[0x1];
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	973	u8 reserved_at_f9[0x2];
				974	u8 fast_teardown[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	975	u8 log_max_eq[0x4];
				976
				977	u8 max_indirection[0x8];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	978	u8 fixed_buffer_size[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	979	u8 log_max_mrw_sz[0x7];
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	980	u8 force_teardown[0x1];
				981	u8 reserved_at_111[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	982	u8 log_max_bsf_list_size[0x6];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	983	u8 umr_extended_translation_offset[0x1];
				984	u8 null_mkey[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	985	u8 log_max_klm_list_size[0x6];
				986
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	987	u8 reserved_at_120[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	988	u8 log_max_ra_req_dc[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	989	u8 reserved_at_130[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	990	u8 log_max_ra_res_dc[0x6];
				991
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	992	u8 reserved_at_140[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	993	u8 log_max_ra_req_qp[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	994	u8 reserved_at_150[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	995	u8 log_max_ra_res_qp[0x6];
				996
Daniel Jurgens	f32f5bd	2015-11-19 17:12:26 +0200	[diff] [blame]	997	u8 end_pad[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	998	u8 cc_query_allowed[0x1];
				999	u8 cc_modify_allowed[0x1];
Daniel Jurgens	f32f5bd	2015-11-19 17:12:26 +0200	[diff] [blame]	1000	u8 start_pad[0x1];
				1001	u8 cache_line_128byte[0x1];
Huy Nguyen	c02762e	2017-07-18 16:03:17 -0500	[diff] [blame]	1002	u8 reserved_at_165[0xa];
				1003	u8 qcam_reg[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1004	u8 gid_table_size[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1005
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1006	u8 out_of_seq_cnt[0x1];
				1007	u8 vport_counters[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1008	u8 retransmission_q_counters[0x1];
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	1009	u8 debug[0x1];
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	1010	u8 modify_rq_counter_set_id[0x1];
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	1011	u8 rq_delay_drop[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1012	u8 max_qp_cnt[0xa];
				1013	u8 pkey_table_size[0x10];
				1014
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1015	u8 vport_group_manager[0x1];
				1016	u8 vhca_group_manager[0x1];
				1017	u8 ib_virt[0x1];
				1018	u8 eth_virt[0x1];
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	1019	u8 vnic_env_queue_counters[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1020	u8 ets[0x1];
				1021	u8 nic_flow_table[0x1];
Or Gerlitz	0efc856	2018-05-31 11:16:18 +0300	[diff] [blame]	1022	u8 eswitch_manager[0x1];
Ariel Levkovich	e72bd81	2018-04-05 18:53:26 +0300	[diff] [blame]	1023	u8 device_memory[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	1024	u8 mcam_reg[0x1];
				1025	u8 pcam_reg[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1026	u8 local_ca_ack_delay[0x5];
Huy Nguyen	4ce3bf2	2016-11-17 13:45:56 +0200	[diff] [blame]	1027	u8 port_module_event[0x1];
Parav Pandit	58dcb60	2017-06-19 07:19:37 +0300	[diff] [blame]	1028	u8 enhanced_error_q_counters[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1029	u8 ports_check[0x1];
Max Gurtovoy	7b13558	2017-01-02 11:37:38 +0200	[diff] [blame]	1030	u8 reserved_at_1b3[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1031	u8 disable_link_up[0x1];
				1032	u8 beacon_led[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1033	u8 port_type[0x2];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1034	u8 num_ports[0x8];
				1035
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	1036	u8 reserved_at_1c0[0x1];
				1037	u8 pps[0x1];
				1038	u8 pps_modify[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1039	u8 log_max_msg[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1040	u8 reserved_at_1c8[0x4];
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	1041	u8 max_tc[0x4];
Ilan Tayari	1865ea9a	2018-05-30 10:59:49 -0700	[diff] [blame]	1042	u8 temp_warn_event[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1043	u8 dcbx[0x1];
Maor Gottlieb	246ac98	2017-05-30 10:29:12 +0300	[diff] [blame]	1044	u8 general_notification_event[0x1];
				1045	u8 reserved_at_1d3[0x2];
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	1046	u8 fpga[0x1];
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	1047	u8 rol_s[0x1];
				1048	u8 rol_g[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1049	u8 reserved_at_1d8[0x1];
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	1050	u8 wol_s[0x1];
				1051	u8 wol_g[0x1];
				1052	u8 wol_a[0x1];
				1053	u8 wol_b[0x1];
				1054	u8 wol_m[0x1];
				1055	u8 wol_u[0x1];
				1056	u8 wol_p[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1057
				1058	u8 stat_rate_support[0x10];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1059	u8 reserved_at_1f0[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1060	u8 cqe_version[0x4];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1061
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1062	u8 compact_address_vector[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1063	u8 striding_rq[0x1];
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	1064	u8 reserved_at_202[0x1];
				1065	u8 ipoib_enhanced_offloads[0x1];
Erez Shitrit	1015c2e	2016-02-21 16:27:16 +0200	[diff] [blame]	1066	u8 ipoib_basic_offloads[0x1];
Majd Dibbiny	c8d75a9	2018-03-22 15:34:04 +0200	[diff] [blame]	1067	u8 reserved_at_205[0x1];
				1068	u8 repeated_block_disabled[0x1];
				1069	u8 umr_modify_entity_size_disabled[0x1];
				1070	u8 umr_modify_atomic_disabled[0x1];
				1071	u8 umr_indirect_mkey_disabled[0x1];
Max Gurtovoy	1410a90	2017-05-28 10:53:10 +0300	[diff] [blame]	1072	u8 umr_fence[0x2];
Yonatan Cohen	94a04d1	2018-10-09 12:05:12 +0300	[diff] [blame]	1073	u8 dc_req_scat_data_cqe[0x1];
				1074	u8 reserved_at_20d[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1075	u8 drain_sigerr[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1076	u8 cmdif_checksum[0x2];
				1077	u8 sigerr_cqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1078	u8 reserved_at_213[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1079	u8 wq_signature[0x1];
				1080	u8 sctr_data_cqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1081	u8 reserved_at_216[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1082	u8 sho[0x1];
				1083	u8 tph[0x1];
				1084	u8 rf[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1085	u8 dct[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1086	u8 qos[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1087	u8 eth_net_offloads[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1088	u8 roce[0x1];
				1089	u8 atomic[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1090	u8 reserved_at_21f[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1091
				1092	u8 cq_oi[0x1];
				1093	u8 cq_resize[0x1];
				1094	u8 cq_moderation[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1095	u8 reserved_at_223[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1096	u8 cq_eq_remap[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1097	u8 pg[0x1];
				1098	u8 block_lb_mc[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1099	u8 reserved_at_229[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1100	u8 scqe_break_moderation[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1101	u8 cq_period_start_from_cqe[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1102	u8 cd[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1103	u8 reserved_at_22d[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1104	u8 apm[0x1];
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	1105	u8 vector_calc[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1106	u8 umr_ptr_rlky[0x1];
Matan Barak	d2370e0	2016-02-29 18:05:30 +0200	[diff] [blame]	1107	u8 imaicl[0x1];
Danit Goldberg	3fd3c80	2018-11-30 13:22:04 +0200	[diff] [blame]	1108	u8 qp_packet_based[0x1];
				1109	u8 reserved_at_233[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1110	u8 qkv[0x1];
				1111	u8 pkv[0x1];
Haggai Eran	b11a4f9	2016-02-29 15:45:03 +0200	[diff] [blame]	1112	u8 set_deth_sqpn[0x1];
				1113	u8 reserved_at_239[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1114	u8 xrc[0x1];
				1115	u8 ud[0x1];
				1116	u8 uc[0x1];
				1117	u8 rc[0x1];
				1118
Eli Cohen	a6d51b6	2017-01-03 23:55:23 +0200	[diff] [blame]	1119	u8 uar_4k[0x1];
				1120	u8 reserved_at_241[0x9];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1121	u8 uar_sz[0x6];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1122	u8 reserved_at_250[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1123	u8 log_pg_sz[0x8];
				1124
				1125	u8 bf[0x1];
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	1126	u8 driver_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1127	u8 pad_tx_eth_packet[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1128	u8 reserved_at_263[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1129	u8 log_bf_reg_size[0x5];
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	1130
				1131	u8 reserved_at_270[0xb];
				1132	u8 lag_master[0x1];
				1133	u8 num_lag_ports[0x4];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1134
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1135	u8 reserved_at_280[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1136	u8 max_wqe_sz_sq[0x10];
				1137
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1138	u8 reserved_at_2a0[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1139	u8 max_wqe_sz_rq[0x10];
				1140
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1141	u8 max_flow_counter_31_16[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1142	u8 max_wqe_sz_sq_dc[0x10];
				1143
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1144	u8 reserved_at_2e0[0x7];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1145	u8 max_qp_mcg[0x19];
				1146
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1147	u8 reserved_at_300[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1148	u8 log_max_mcg[0x8];
				1149
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1150	u8 reserved_at_320[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1151	u8 log_max_transport_domain[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1152	u8 reserved_at_328[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1153	u8 log_max_pd[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1154	u8 reserved_at_330[0xb];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1155	u8 log_max_xrcd[0x5];
				1156
Moshe Shemesh	5c29814	2017-12-26 16:46:29 +0200	[diff] [blame]	1157	u8 nic_receive_steering_discard[0x1];
Moshe Shemesh	aaabd07	2018-01-14 00:56:25 +0200	[diff] [blame]	1158	u8 receive_discard_vport_down[0x1];
				1159	u8 transmit_discard_vport_down[0x1];
				1160	u8 reserved_at_343[0x5];
Amir Vadai	a351a1b0	2016-07-14 10:32:38 +0300	[diff] [blame]	1161	u8 log_max_flow_counter_bulk[0x8];
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1162	u8 max_flow_counter_15_0[0x10];
Amir Vadai	a351a1b0	2016-07-14 10:32:38 +0300	[diff] [blame]	1163
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1164
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1165	u8 reserved_at_360[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1166	u8 log_max_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1167	u8 reserved_at_368[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1168	u8 log_max_sq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1169	u8 reserved_at_370[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1170	u8 log_max_tir[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1171	u8 reserved_at_378[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1172	u8 log_max_tis[0x5];
				1173
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1174	u8 basic_cyclic_rcv_wqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1175	u8 reserved_at_381[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1176	u8 log_max_rmp[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1177	u8 reserved_at_388[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1178	u8 log_max_rqt[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1179	u8 reserved_at_390[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1180	u8 log_max_rqt_size[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1181	u8 reserved_at_398[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1182	u8 log_max_tis_per_sq[0x5];
				1183
Tariq Toukan	619a8f2a	2018-02-07 14:41:25 +0200	[diff] [blame]	1184	u8 ext_stride_num_range[0x1];
				1185	u8 reserved_at_3a1[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1186	u8 log_max_stride_sz_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1187	u8 reserved_at_3a8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1188	u8 log_min_stride_sz_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1189	u8 reserved_at_3b0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1190	u8 log_max_stride_sz_sq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1191	u8 reserved_at_3b8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1192	u8 log_min_stride_sz_sq[0x5];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1193
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1194	u8 hairpin[0x1];
				1195	u8 reserved_at_3c1[0x2];
				1196	u8 log_max_hairpin_queues[0x5];
				1197	u8 reserved_at_3c8[0x3];
				1198	u8 log_max_hairpin_wq_data_sz[0x5];
Or Gerlitz	4d533e0	2018-01-04 12:26:21 +0200	[diff] [blame]	1199	u8 reserved_at_3d0[0x3];
				1200	u8 log_max_hairpin_num_packets[0x5];
				1201	u8 reserved_at_3d8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1202	u8 log_max_wq_sz[0x5];
				1203
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1204	u8 nic_vport_change_event[0x1];
Eran Ben Elisha	8978cc9	2018-01-09 11:41:10 +0200	[diff] [blame]	1205	u8 disable_local_lb_uc[0x1];
				1206	u8 disable_local_lb_mc[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1207	u8 log_min_hairpin_wq_data_sz[0x5];
				1208	u8 reserved_at_3e8[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1209	u8 log_max_vlan_list[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1210	u8 reserved_at_3f0[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1211	u8 log_max_current_mc_list[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1212	u8 reserved_at_3f8[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1213	u8 log_max_current_uc_list[0x5];
				1214
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	1215	u8 general_obj_types[0x40];
				1216
Denis Drozdov	342ac84	2018-08-08 16:23:48 -0700	[diff] [blame]	1217	u8 reserved_at_440[0x20];
				1218
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	1219	u8 reserved_at_460[0x3];
				1220	u8 log_max_uctx[0x5];
				1221	u8 reserved_at_468[0x3];
				1222	u8 log_max_umem[0x5];
Denis Drozdov	342ac84	2018-08-08 16:23:48 -0700	[diff] [blame]	1223	u8 max_num_eqs[0x10];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1224
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1225	u8 reserved_at_480[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1226	u8 log_max_l2_table[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1227	u8 reserved_at_488[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1228	u8 log_uar_page_sz[0x10];
				1229
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1230	u8 reserved_at_4a0[0x20];
Linus Torvalds	048ccca	2016-01-23 18:45:06 -0800	[diff] [blame]	1231	u8 device_frequency_mhz[0x20];
Eran Ben Elisha	b084444	2015-12-29 14:58:30 +0200	[diff] [blame]	1232	u8 device_frequency_khz[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1233
Eli Cohen	a6d51b6	2017-01-03 23:55:23 +0200	[diff] [blame]	1234	u8 reserved_at_500[0x20];
				1235	u8 num_of_uars_per_page[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1236
Ariel Levkovich	e818e25	2018-05-13 14:33:35 +0300	[diff] [blame]	1237	u8 flex_parser_protocols[0x20];
				1238	u8 reserved_at_560[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1239
Yonatan Cohen	ab741b2	2018-05-27 13:42:32 +0300	[diff] [blame]	1240	u8 reserved_at_580[0x3c];
				1241	u8 mini_cqe_resp_stride_index[0x1];
Guy Levi	0ff8e79	2017-10-19 08:25:51 +0300	[diff] [blame]	1242	u8 cqe_128_always[0x1];
				1243	u8 cqe_compression_128[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1244	u8 cqe_compression[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1245
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1246	u8 cqe_compression_timeout[0x10];
				1247	u8 cqe_compression_max_num[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1248
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1249	u8 reserved_at_5e0[0x10];
				1250	u8 tag_matching[0x1];
				1251	u8 rndv_offload_rc[0x1];
				1252	u8 rndv_offload_dc[0x1];
				1253	u8 log_tag_matching_list_sz[0x5];
Max Gurtovoy	7b13558	2017-01-02 11:37:38 +0200	[diff] [blame]	1254	u8 reserved_at_5f8[0x3];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1255	u8 log_max_xrq[0x5];
				1256
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	1257	u8 affiliate_nic_vport_criteria[0x8];
				1258	u8 native_port_num[0x8];
				1259	u8 num_vhca_ports[0x8];
				1260	u8 reserved_at_618[0x6];
				1261	u8 sw_owner_id[0x1];
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	1262	u8 reserved_at_61f[0x1];
				1263
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	1264	u8 max_num_of_monitor_counters[0x10];
				1265	u8 num_ppcnt_monitor_counters[0x10];
				1266
				1267	u8 reserved_at_640[0x10];
				1268	u8 num_q_monitor_counters[0x10];
				1269
				1270	u8 reserved_at_660[0x40];
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	1271
				1272	u8 uctx_cap[0x20];
				1273
				1274	u8 reserved_at_6c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1275	};
				1276
Saeed Mahameed	8184873	2015-12-01 18:03:20 +0200	[diff] [blame]	1277	enum mlx5_flow_destination_type {
				1278	MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
				1279	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
				1280	MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
Amir Vadai	bd5251db	2016-05-13 12:55:40 +0000	[diff] [blame]	1281
Aviad Yehezkel	5f41837	2018-02-18 13:17:17 +0200	[diff] [blame]	1282	MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
Amir Vadai	bd5251db	2016-05-13 12:55:40 +0000	[diff] [blame]	1283	MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
Yishai Hadas	664000b	2018-06-19 15:23:36 +0300	[diff] [blame]	1284	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1285	};
				1286
				1287	struct mlx5_ifc_dest_format_struct_bits {
				1288	u8 destination_type[0x8];
				1289	u8 destination_id[0x18];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1290
Shahar Klein	b17f7fc	2018-03-22 12:32:12 +0200	[diff] [blame]	1291	u8 destination_eswitch_owner_vhca_id_valid[0x1];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1292	u8 packet_reformat[0x1];
				1293	u8 reserved_at_22[0xe];
Shahar Klein	b17f7fc	2018-03-22 12:32:12 +0200	[diff] [blame]	1294	u8 destination_eswitch_owner_vhca_id[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1295	};
				1296
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1297	struct mlx5_ifc_flow_counter_list_bits {
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1298	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1299
				1300	u8 reserved_at_20[0x20];
				1301	};
				1302
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1303	struct mlx5_ifc_extended_dest_format_bits {
				1304	struct mlx5_ifc_dest_format_struct_bits destination_entry;
				1305
				1306	u8 packet_reformat_id[0x20];
				1307
				1308	u8 reserved_at_60[0x20];
				1309	};
				1310
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1311	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
				1312	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
				1313	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
				1314	u8 reserved_at_0[0x40];
				1315	};
				1316
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1317	struct mlx5_ifc_fte_match_param_bits {
				1318	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
				1319
				1320	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
				1321
				1322	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
				1323
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	1324	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
				1325
				1326	u8 reserved_at_800[0x800];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1327	};
				1328
				1329	enum {
				1330	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
				1331	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
				1332	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
				1333	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
				1334	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
				1335	};
				1336
				1337	struct mlx5_ifc_rx_hash_field_select_bits {
				1338	u8 l3_prot_type[0x1];
				1339	u8 l4_prot_type[0x1];
				1340	u8 selected_fields[0x1e];
				1341	};
				1342
				1343	enum {
				1344	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
				1345	MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
				1346	};
				1347
				1348	enum {
				1349	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
				1350	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
				1351	};
				1352
				1353	struct mlx5_ifc_wq_bits {
				1354	u8 wq_type[0x4];
				1355	u8 wq_signature[0x1];
				1356	u8 end_padding_mode[0x2];
				1357	u8 cd_slave[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1358	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1359
				1360	u8 hds_skip_first_sge[0x1];
				1361	u8 log2_hds_buf_size[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1362	u8 reserved_at_24[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1363	u8 page_offset[0x5];
				1364	u8 lwm[0x10];
				1365
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1366	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1367	u8 pd[0x18];
				1368
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1369	u8 reserved_at_60[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1370	u8 uar_page[0x18];
				1371
				1372	u8 dbr_addr[0x40];
				1373
				1374	u8 hw_counter[0x20];
				1375
				1376	u8 sw_counter[0x20];
				1377
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1378	u8 reserved_at_100[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1379	u8 log_wq_stride[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1380	u8 reserved_at_110[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1381	u8 log_wq_pg_sz[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1382	u8 reserved_at_118[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1383	u8 log_wq_sz[0x5];
				1384
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	1385	u8 dbr_umem_valid[0x1];
				1386	u8 wq_umem_valid[0x1];
				1387	u8 reserved_at_122[0x1];
Or Gerlitz	4d533e0	2018-01-04 12:26:21 +0200	[diff] [blame]	1388	u8 log_hairpin_num_packets[0x5];
				1389	u8 reserved_at_128[0x3];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1390	u8 log_hairpin_data_sz[0x5];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1391
Tariq Toukan	619a8f2a	2018-02-07 14:41:25 +0200	[diff] [blame]	1392	u8 reserved_at_130[0x4];
				1393	u8 log_wqe_num_of_strides[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1394	u8 two_byte_shift_en[0x1];
				1395	u8 reserved_at_139[0x4];
				1396	u8 log_wqe_stride_size[0x3];
				1397
				1398	u8 reserved_at_140[0x4c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1399
				1400	struct mlx5_ifc_cmd_pas_bits pas[0];
				1401	};
				1402
				1403	struct mlx5_ifc_rq_num_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1404	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1405	u8 rq_num[0x18];
				1406	};
				1407
				1408	struct mlx5_ifc_mac_address_layout_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1409	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1410	u8 mac_addr_47_32[0x10];
				1411
				1412	u8 mac_addr_31_0[0x20];
				1413	};
				1414
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1415	struct mlx5_ifc_vlan_layout_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1416	u8 reserved_at_0[0x14];
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1417	u8 vlan[0x0c];
				1418
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1419	u8 reserved_at_20[0x20];
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1420	};
				1421
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1422	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1423	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1424
				1425	u8 min_time_between_cnps[0x20];
				1426
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1427	u8 reserved_at_c0[0x12];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1428	u8 cnp_dscp[0x6];
Parav Pandit	4a2da0b	2017-05-30 10:05:15 +0300	[diff] [blame]	1429	u8 reserved_at_d8[0x4];
				1430	u8 cnp_prio_mode[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1431	u8 cnp_802p_prio[0x3];
				1432
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1433	u8 reserved_at_e0[0x720];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1434	};
				1435
				1436	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1437	u8 reserved_at_0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1438
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1439	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1440	u8 clamp_tgt_rate[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1441	u8 reserved_at_65[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1442	u8 clamp_tgt_rate_after_time_inc[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1443	u8 reserved_at_69[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1444
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1445	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1446
				1447	u8 rpg_time_reset[0x20];
				1448
				1449	u8 rpg_byte_reset[0x20];
				1450
				1451	u8 rpg_threshold[0x20];
				1452
				1453	u8 rpg_max_rate[0x20];
				1454
				1455	u8 rpg_ai_rate[0x20];
				1456
				1457	u8 rpg_hai_rate[0x20];
				1458
				1459	u8 rpg_gd[0x20];
				1460
				1461	u8 rpg_min_dec_fac[0x20];
				1462
				1463	u8 rpg_min_rate[0x20];
				1464
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1465	u8 reserved_at_1c0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1466
				1467	u8 rate_to_set_on_first_cnp[0x20];
				1468
				1469	u8 dce_tcp_g[0x20];
				1470
				1471	u8 dce_tcp_rtt[0x20];
				1472
				1473	u8 rate_reduce_monitor_period[0x20];
				1474
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1475	u8 reserved_at_320[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1476
				1477	u8 initial_alpha_value[0x20];
				1478
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1479	u8 reserved_at_360[0x4a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1480	};
				1481
				1482	struct mlx5_ifc_cong_control_802_1qau_rp_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1483	u8 reserved_at_0[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1484
				1485	u8 rppp_max_rps[0x20];
				1486
				1487	u8 rpg_time_reset[0x20];
				1488
				1489	u8 rpg_byte_reset[0x20];
				1490
				1491	u8 rpg_threshold[0x20];
				1492
				1493	u8 rpg_max_rate[0x20];
				1494
				1495	u8 rpg_ai_rate[0x20];
				1496
				1497	u8 rpg_hai_rate[0x20];
				1498
				1499	u8 rpg_gd[0x20];
				1500
				1501	u8 rpg_min_dec_fac[0x20];
				1502
				1503	u8 rpg_min_rate[0x20];
				1504
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1505	u8 reserved_at_1c0[0x640];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1506	};
				1507
				1508	enum {
				1509	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
				1510	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
				1511	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
				1512	};
				1513
				1514	struct mlx5_ifc_resize_field_select_bits {
				1515	u8 resize_field_select[0x20];
				1516	};
				1517
				1518	enum {
				1519	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
				1520	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
				1521	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
				1522	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
				1523	};
				1524
				1525	struct mlx5_ifc_modify_field_select_bits {
				1526	u8 modify_field_select[0x20];
				1527	};
				1528
				1529	struct mlx5_ifc_field_select_r_roce_np_bits {
				1530	u8 field_select_r_roce_np[0x20];
				1531	};
				1532
				1533	struct mlx5_ifc_field_select_r_roce_rp_bits {
				1534	u8 field_select_r_roce_rp[0x20];
				1535	};
				1536
				1537	enum {
				1538	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
				1539	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
				1540	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
				1541	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
				1542	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
				1543	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
				1544	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
				1545	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
				1546	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
				1547	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
				1548	};
				1549
				1550	struct mlx5_ifc_field_select_802_1qau_rp_bits {
				1551	u8 field_select_8021qaurp[0x20];
				1552	};
				1553
				1554	struct mlx5_ifc_phys_layer_cntrs_bits {
				1555	u8 time_since_last_clear_high[0x20];
				1556
				1557	u8 time_since_last_clear_low[0x20];
				1558
				1559	u8 symbol_errors_high[0x20];
				1560
				1561	u8 symbol_errors_low[0x20];
				1562
				1563	u8 sync_headers_errors_high[0x20];
				1564
				1565	u8 sync_headers_errors_low[0x20];
				1566
				1567	u8 edpl_bip_errors_lane0_high[0x20];
				1568
				1569	u8 edpl_bip_errors_lane0_low[0x20];
				1570
				1571	u8 edpl_bip_errors_lane1_high[0x20];
				1572
				1573	u8 edpl_bip_errors_lane1_low[0x20];
				1574
				1575	u8 edpl_bip_errors_lane2_high[0x20];
				1576
				1577	u8 edpl_bip_errors_lane2_low[0x20];
				1578
				1579	u8 edpl_bip_errors_lane3_high[0x20];
				1580
				1581	u8 edpl_bip_errors_lane3_low[0x20];
				1582
				1583	u8 fc_fec_corrected_blocks_lane0_high[0x20];
				1584
				1585	u8 fc_fec_corrected_blocks_lane0_low[0x20];
				1586
				1587	u8 fc_fec_corrected_blocks_lane1_high[0x20];
				1588
				1589	u8 fc_fec_corrected_blocks_lane1_low[0x20];
				1590
				1591	u8 fc_fec_corrected_blocks_lane2_high[0x20];
				1592
				1593	u8 fc_fec_corrected_blocks_lane2_low[0x20];
				1594
				1595	u8 fc_fec_corrected_blocks_lane3_high[0x20];
				1596
				1597	u8 fc_fec_corrected_blocks_lane3_low[0x20];
				1598
				1599	u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
				1600
				1601	u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
				1602
				1603	u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
				1604
				1605	u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
				1606
				1607	u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
				1608
				1609	u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
				1610
				1611	u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
				1612
				1613	u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
				1614
				1615	u8 rs_fec_corrected_blocks_high[0x20];
				1616
				1617	u8 rs_fec_corrected_blocks_low[0x20];
				1618
				1619	u8 rs_fec_uncorrectable_blocks_high[0x20];
				1620
				1621	u8 rs_fec_uncorrectable_blocks_low[0x20];
				1622
				1623	u8 rs_fec_no_errors_blocks_high[0x20];
				1624
				1625	u8 rs_fec_no_errors_blocks_low[0x20];
				1626
				1627	u8 rs_fec_single_error_blocks_high[0x20];
				1628
				1629	u8 rs_fec_single_error_blocks_low[0x20];
				1630
				1631	u8 rs_fec_corrected_symbols_total_high[0x20];
				1632
				1633	u8 rs_fec_corrected_symbols_total_low[0x20];
				1634
				1635	u8 rs_fec_corrected_symbols_lane0_high[0x20];
				1636
				1637	u8 rs_fec_corrected_symbols_lane0_low[0x20];
				1638
				1639	u8 rs_fec_corrected_symbols_lane1_high[0x20];
				1640
				1641	u8 rs_fec_corrected_symbols_lane1_low[0x20];
				1642
				1643	u8 rs_fec_corrected_symbols_lane2_high[0x20];
				1644
				1645	u8 rs_fec_corrected_symbols_lane2_low[0x20];
				1646
				1647	u8 rs_fec_corrected_symbols_lane3_high[0x20];
				1648
				1649	u8 rs_fec_corrected_symbols_lane3_low[0x20];
				1650
				1651	u8 link_down_events[0x20];
				1652
				1653	u8 successful_recovery_events[0x20];
				1654
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1655	u8 reserved_at_640[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1656	};
				1657
Gal Pressman	d8dc050	2016-09-27 17:04:51 +0300	[diff] [blame]	1658	struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
				1659	u8 time_since_last_clear_high[0x20];
				1660
				1661	u8 time_since_last_clear_low[0x20];
				1662
				1663	u8 phy_received_bits_high[0x20];
				1664
				1665	u8 phy_received_bits_low[0x20];
				1666
				1667	u8 phy_symbol_errors_high[0x20];
				1668
				1669	u8 phy_symbol_errors_low[0x20];
				1670
				1671	u8 phy_corrected_bits_high[0x20];
				1672
				1673	u8 phy_corrected_bits_low[0x20];
				1674
				1675	u8 phy_corrected_bits_lane0_high[0x20];
				1676
				1677	u8 phy_corrected_bits_lane0_low[0x20];
				1678
				1679	u8 phy_corrected_bits_lane1_high[0x20];
				1680
				1681	u8 phy_corrected_bits_lane1_low[0x20];
				1682
				1683	u8 phy_corrected_bits_lane2_high[0x20];
				1684
				1685	u8 phy_corrected_bits_lane2_low[0x20];
				1686
				1687	u8 phy_corrected_bits_lane3_high[0x20];
				1688
				1689	u8 phy_corrected_bits_lane3_low[0x20];
				1690
				1691	u8 reserved_at_200[0x5c0];
				1692	};
				1693
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	1694	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
				1695	u8 symbol_error_counter[0x10];
				1696
				1697	u8 link_error_recovery_counter[0x8];
				1698
				1699	u8 link_downed_counter[0x8];
				1700
				1701	u8 port_rcv_errors[0x10];
				1702
				1703	u8 port_rcv_remote_physical_errors[0x10];
				1704
				1705	u8 port_rcv_switch_relay_errors[0x10];
				1706
				1707	u8 port_xmit_discards[0x10];
				1708
				1709	u8 port_xmit_constraint_errors[0x8];
				1710
				1711	u8 port_rcv_constraint_errors[0x8];
				1712
				1713	u8 reserved_at_70[0x8];
				1714
				1715	u8 link_overrun_errors[0x8];
				1716
				1717	u8 reserved_at_80[0x10];
				1718
				1719	u8 vl_15_dropped[0x10];
				1720
Tim Wright	133bea0	2017-05-01 17:30:08 +0100	[diff] [blame]	1721	u8 reserved_at_a0[0x80];
				1722
				1723	u8 port_xmit_wait[0x20];
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	1724	};
				1725
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1726	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
				1727	u8 transmit_queue_high[0x20];
				1728
				1729	u8 transmit_queue_low[0x20];
				1730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1731	u8 reserved_at_40[0x780];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1732	};
				1733
				1734	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
				1735	u8 rx_octets_high[0x20];
				1736
				1737	u8 rx_octets_low[0x20];
				1738
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1739	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1740
				1741	u8 rx_frames_high[0x20];
				1742
				1743	u8 rx_frames_low[0x20];
				1744
				1745	u8 tx_octets_high[0x20];
				1746
				1747	u8 tx_octets_low[0x20];
				1748
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1749	u8 reserved_at_180[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1750
				1751	u8 tx_frames_high[0x20];
				1752
				1753	u8 tx_frames_low[0x20];
				1754
				1755	u8 rx_pause_high[0x20];
				1756
				1757	u8 rx_pause_low[0x20];
				1758
				1759	u8 rx_pause_duration_high[0x20];
				1760
				1761	u8 rx_pause_duration_low[0x20];
				1762
				1763	u8 tx_pause_high[0x20];
				1764
				1765	u8 tx_pause_low[0x20];
				1766
				1767	u8 tx_pause_duration_high[0x20];
				1768
				1769	u8 tx_pause_duration_low[0x20];
				1770
				1771	u8 rx_pause_transition_high[0x20];
				1772
				1773	u8 rx_pause_transition_low[0x20];
				1774
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	1775	u8 reserved_at_3c0[0x40];
				1776
				1777	u8 device_stall_minor_watermark_cnt_high[0x20];
				1778
				1779	u8 device_stall_minor_watermark_cnt_low[0x20];
				1780
				1781	u8 device_stall_critical_watermark_cnt_high[0x20];
				1782
				1783	u8 device_stall_critical_watermark_cnt_low[0x20];
				1784
				1785	u8 reserved_at_480[0x340];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1786	};
				1787
				1788	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
				1789	u8 port_transmit_wait_high[0x20];
				1790
				1791	u8 port_transmit_wait_low[0x20];
				1792
Gal Pressman	2dba079	2017-06-18 14:56:45 +0300	[diff] [blame]	1793	u8 reserved_at_40[0x100];
				1794
				1795	u8 rx_buffer_almost_full_high[0x20];
				1796
				1797	u8 rx_buffer_almost_full_low[0x20];
				1798
				1799	u8 rx_buffer_full_high[0x20];
				1800
				1801	u8 rx_buffer_full_low[0x20];
				1802
Talat Batheesh	0af5107	2018-05-17 11:14:18 +0300	[diff] [blame]	1803	u8 rx_icrc_encapsulated_high[0x20];
				1804
				1805	u8 rx_icrc_encapsulated_low[0x20];
				1806
				1807	u8 reserved_at_200[0x5c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1808	};
				1809
				1810	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
				1811	u8 dot3stats_alignment_errors_high[0x20];
				1812
				1813	u8 dot3stats_alignment_errors_low[0x20];
				1814
				1815	u8 dot3stats_fcs_errors_high[0x20];
				1816
				1817	u8 dot3stats_fcs_errors_low[0x20];
				1818
				1819	u8 dot3stats_single_collision_frames_high[0x20];
				1820
				1821	u8 dot3stats_single_collision_frames_low[0x20];
				1822
				1823	u8 dot3stats_multiple_collision_frames_high[0x20];
				1824
				1825	u8 dot3stats_multiple_collision_frames_low[0x20];
				1826
				1827	u8 dot3stats_sqe_test_errors_high[0x20];
				1828
				1829	u8 dot3stats_sqe_test_errors_low[0x20];
				1830
				1831	u8 dot3stats_deferred_transmissions_high[0x20];
				1832
				1833	u8 dot3stats_deferred_transmissions_low[0x20];
				1834
				1835	u8 dot3stats_late_collisions_high[0x20];
				1836
				1837	u8 dot3stats_late_collisions_low[0x20];
				1838
				1839	u8 dot3stats_excessive_collisions_high[0x20];
				1840
				1841	u8 dot3stats_excessive_collisions_low[0x20];
				1842
				1843	u8 dot3stats_internal_mac_transmit_errors_high[0x20];
				1844
				1845	u8 dot3stats_internal_mac_transmit_errors_low[0x20];
				1846
				1847	u8 dot3stats_carrier_sense_errors_high[0x20];
				1848
				1849	u8 dot3stats_carrier_sense_errors_low[0x20];
				1850
				1851	u8 dot3stats_frame_too_longs_high[0x20];
				1852
				1853	u8 dot3stats_frame_too_longs_low[0x20];
				1854
				1855	u8 dot3stats_internal_mac_receive_errors_high[0x20];
				1856
				1857	u8 dot3stats_internal_mac_receive_errors_low[0x20];
				1858
				1859	u8 dot3stats_symbol_errors_high[0x20];
				1860
				1861	u8 dot3stats_symbol_errors_low[0x20];
				1862
				1863	u8 dot3control_in_unknown_opcodes_high[0x20];
				1864
				1865	u8 dot3control_in_unknown_opcodes_low[0x20];
				1866
				1867	u8 dot3in_pause_frames_high[0x20];
				1868
				1869	u8 dot3in_pause_frames_low[0x20];
				1870
				1871	u8 dot3out_pause_frames_high[0x20];
				1872
				1873	u8 dot3out_pause_frames_low[0x20];
				1874
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1875	u8 reserved_at_400[0x3c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1876	};
				1877
				1878	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
				1879	u8 ether_stats_drop_events_high[0x20];
				1880
				1881	u8 ether_stats_drop_events_low[0x20];
				1882
				1883	u8 ether_stats_octets_high[0x20];
				1884
				1885	u8 ether_stats_octets_low[0x20];
				1886
				1887	u8 ether_stats_pkts_high[0x20];
				1888
				1889	u8 ether_stats_pkts_low[0x20];
				1890
				1891	u8 ether_stats_broadcast_pkts_high[0x20];
				1892
				1893	u8 ether_stats_broadcast_pkts_low[0x20];
				1894
				1895	u8 ether_stats_multicast_pkts_high[0x20];
				1896
				1897	u8 ether_stats_multicast_pkts_low[0x20];
				1898
				1899	u8 ether_stats_crc_align_errors_high[0x20];
				1900
				1901	u8 ether_stats_crc_align_errors_low[0x20];
				1902
				1903	u8 ether_stats_undersize_pkts_high[0x20];
				1904
				1905	u8 ether_stats_undersize_pkts_low[0x20];
				1906
				1907	u8 ether_stats_oversize_pkts_high[0x20];
				1908
				1909	u8 ether_stats_oversize_pkts_low[0x20];
				1910
				1911	u8 ether_stats_fragments_high[0x20];
				1912
				1913	u8 ether_stats_fragments_low[0x20];
				1914
				1915	u8 ether_stats_jabbers_high[0x20];
				1916
				1917	u8 ether_stats_jabbers_low[0x20];
				1918
				1919	u8 ether_stats_collisions_high[0x20];
				1920
				1921	u8 ether_stats_collisions_low[0x20];
				1922
				1923	u8 ether_stats_pkts64octets_high[0x20];
				1924
				1925	u8 ether_stats_pkts64octets_low[0x20];
				1926
				1927	u8 ether_stats_pkts65to127octets_high[0x20];
				1928
				1929	u8 ether_stats_pkts65to127octets_low[0x20];
				1930
				1931	u8 ether_stats_pkts128to255octets_high[0x20];
				1932
				1933	u8 ether_stats_pkts128to255octets_low[0x20];
				1934
				1935	u8 ether_stats_pkts256to511octets_high[0x20];
				1936
				1937	u8 ether_stats_pkts256to511octets_low[0x20];
				1938
				1939	u8 ether_stats_pkts512to1023octets_high[0x20];
				1940
				1941	u8 ether_stats_pkts512to1023octets_low[0x20];
				1942
				1943	u8 ether_stats_pkts1024to1518octets_high[0x20];
				1944
				1945	u8 ether_stats_pkts1024to1518octets_low[0x20];
				1946
				1947	u8 ether_stats_pkts1519to2047octets_high[0x20];
				1948
				1949	u8 ether_stats_pkts1519to2047octets_low[0x20];
				1950
				1951	u8 ether_stats_pkts2048to4095octets_high[0x20];
				1952
				1953	u8 ether_stats_pkts2048to4095octets_low[0x20];
				1954
				1955	u8 ether_stats_pkts4096to8191octets_high[0x20];
				1956
				1957	u8 ether_stats_pkts4096to8191octets_low[0x20];
				1958
				1959	u8 ether_stats_pkts8192to10239octets_high[0x20];
				1960
				1961	u8 ether_stats_pkts8192to10239octets_low[0x20];
				1962
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1963	u8 reserved_at_540[0x280];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1964	};
				1965
				1966	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
				1967	u8 if_in_octets_high[0x20];
				1968
				1969	u8 if_in_octets_low[0x20];
				1970
				1971	u8 if_in_ucast_pkts_high[0x20];
				1972
				1973	u8 if_in_ucast_pkts_low[0x20];
				1974
				1975	u8 if_in_discards_high[0x20];
				1976
				1977	u8 if_in_discards_low[0x20];
				1978
				1979	u8 if_in_errors_high[0x20];
				1980
				1981	u8 if_in_errors_low[0x20];
				1982
				1983	u8 if_in_unknown_protos_high[0x20];
				1984
				1985	u8 if_in_unknown_protos_low[0x20];
				1986
				1987	u8 if_out_octets_high[0x20];
				1988
				1989	u8 if_out_octets_low[0x20];
				1990
				1991	u8 if_out_ucast_pkts_high[0x20];
				1992
				1993	u8 if_out_ucast_pkts_low[0x20];
				1994
				1995	u8 if_out_discards_high[0x20];
				1996
				1997	u8 if_out_discards_low[0x20];
				1998
				1999	u8 if_out_errors_high[0x20];
				2000
				2001	u8 if_out_errors_low[0x20];
				2002
				2003	u8 if_in_multicast_pkts_high[0x20];
				2004
				2005	u8 if_in_multicast_pkts_low[0x20];
				2006
				2007	u8 if_in_broadcast_pkts_high[0x20];
				2008
				2009	u8 if_in_broadcast_pkts_low[0x20];
				2010
				2011	u8 if_out_multicast_pkts_high[0x20];
				2012
				2013	u8 if_out_multicast_pkts_low[0x20];
				2014
				2015	u8 if_out_broadcast_pkts_high[0x20];
				2016
				2017	u8 if_out_broadcast_pkts_low[0x20];
				2018
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2019	u8 reserved_at_340[0x480];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2020	};
				2021
				2022	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
				2023	u8 a_frames_transmitted_ok_high[0x20];
				2024
				2025	u8 a_frames_transmitted_ok_low[0x20];
				2026
				2027	u8 a_frames_received_ok_high[0x20];
				2028
				2029	u8 a_frames_received_ok_low[0x20];
				2030
				2031	u8 a_frame_check_sequence_errors_high[0x20];
				2032
				2033	u8 a_frame_check_sequence_errors_low[0x20];
				2034
				2035	u8 a_alignment_errors_high[0x20];
				2036
				2037	u8 a_alignment_errors_low[0x20];
				2038
				2039	u8 a_octets_transmitted_ok_high[0x20];
				2040
				2041	u8 a_octets_transmitted_ok_low[0x20];
				2042
				2043	u8 a_octets_received_ok_high[0x20];
				2044
				2045	u8 a_octets_received_ok_low[0x20];
				2046
				2047	u8 a_multicast_frames_xmitted_ok_high[0x20];
				2048
				2049	u8 a_multicast_frames_xmitted_ok_low[0x20];
				2050
				2051	u8 a_broadcast_frames_xmitted_ok_high[0x20];
				2052
				2053	u8 a_broadcast_frames_xmitted_ok_low[0x20];
				2054
				2055	u8 a_multicast_frames_received_ok_high[0x20];
				2056
				2057	u8 a_multicast_frames_received_ok_low[0x20];
				2058
				2059	u8 a_broadcast_frames_received_ok_high[0x20];
				2060
				2061	u8 a_broadcast_frames_received_ok_low[0x20];
				2062
				2063	u8 a_in_range_length_errors_high[0x20];
				2064
				2065	u8 a_in_range_length_errors_low[0x20];
				2066
				2067	u8 a_out_of_range_length_field_high[0x20];
				2068
				2069	u8 a_out_of_range_length_field_low[0x20];
				2070
				2071	u8 a_frame_too_long_errors_high[0x20];
				2072
				2073	u8 a_frame_too_long_errors_low[0x20];
				2074
				2075	u8 a_symbol_error_during_carrier_high[0x20];
				2076
				2077	u8 a_symbol_error_during_carrier_low[0x20];
				2078
				2079	u8 a_mac_control_frames_transmitted_high[0x20];
				2080
				2081	u8 a_mac_control_frames_transmitted_low[0x20];
				2082
				2083	u8 a_mac_control_frames_received_high[0x20];
				2084
				2085	u8 a_mac_control_frames_received_low[0x20];
				2086
				2087	u8 a_unsupported_opcodes_received_high[0x20];
				2088
				2089	u8 a_unsupported_opcodes_received_low[0x20];
				2090
				2091	u8 a_pause_mac_ctrl_frames_received_high[0x20];
				2092
				2093	u8 a_pause_mac_ctrl_frames_received_low[0x20];
				2094
				2095	u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
				2096
				2097	u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
				2098
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2099	u8 reserved_at_4c0[0x300];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2100	};
				2101
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	2102	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
				2103	u8 life_time_counter_high[0x20];
				2104
				2105	u8 life_time_counter_low[0x20];
				2106
				2107	u8 rx_errors[0x20];
				2108
				2109	u8 tx_errors[0x20];
				2110
				2111	u8 l0_to_recovery_eieos[0x20];
				2112
				2113	u8 l0_to_recovery_ts[0x20];
				2114
				2115	u8 l0_to_recovery_framing[0x20];
				2116
				2117	u8 l0_to_recovery_retrain[0x20];
				2118
				2119	u8 crc_error_dllp[0x20];
				2120
				2121	u8 crc_error_tlp[0x20];
				2122
Eran Ben Elisha	efae7f7	2017-05-12 02:47:02 +0300	[diff] [blame]	2123	u8 tx_overflow_buffer_pkt_high[0x20];
				2124
				2125	u8 tx_overflow_buffer_pkt_low[0x20];
Gal Pressman	5405fa2	2017-06-15 18:29:23 +0300	[diff] [blame]	2126
				2127	u8 outbound_stalled_reads[0x20];
				2128
				2129	u8 outbound_stalled_writes[0x20];
				2130
				2131	u8 outbound_stalled_reads_events[0x20];
				2132
				2133	u8 outbound_stalled_writes_events[0x20];
				2134
				2135	u8 reserved_at_200[0x5c0];
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	2136	};
				2137
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2138	struct mlx5_ifc_cmd_inter_comp_event_bits {
				2139	u8 command_completion_vector[0x20];
				2140
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2141	u8 reserved_at_20[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2142	};
				2143
				2144	struct mlx5_ifc_stall_vl_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2145	u8 reserved_at_0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2146	u8 port_num[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2147	u8 reserved_at_19[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2148	u8 vl[0x4];
				2149
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2150	u8 reserved_at_20[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2151	};
				2152
				2153	struct mlx5_ifc_db_bf_congestion_event_bits {
				2154	u8 event_subtype[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2155	u8 reserved_at_8[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2156	u8 congestion_level[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2157	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2158
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2159	u8 reserved_at_20[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2160	};
				2161
				2162	struct mlx5_ifc_gpio_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2163	u8 reserved_at_0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2164
				2165	u8 gpio_event_hi[0x20];
				2166
				2167	u8 gpio_event_lo[0x20];
				2168
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2169	u8 reserved_at_a0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2170	};
				2171
				2172	struct mlx5_ifc_port_state_change_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2173	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2174
				2175	u8 port_num[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2176	u8 reserved_at_44[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2177
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2178	u8 reserved_at_60[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2179	};
				2180
				2181	struct mlx5_ifc_dropped_packet_logged_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2182	u8 reserved_at_0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2183	};
				2184
				2185	enum {
				2186	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
				2187	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
				2188	};
				2189
				2190	struct mlx5_ifc_cq_error_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2191	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2192	u8 cqn[0x18];
				2193
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2194	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2195
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2196	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2197	u8 syndrome[0x8];
				2198
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2199	u8 reserved_at_60[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2200	};
				2201
				2202	struct mlx5_ifc_rdma_page_fault_event_bits {
				2203	u8 bytes_committed[0x20];
				2204
				2205	u8 r_key[0x20];
				2206
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2207	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2208	u8 packet_len[0x10];
				2209
				2210	u8 rdma_op_len[0x20];
				2211
				2212	u8 rdma_va[0x40];
				2213
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2214	u8 reserved_at_c0[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2215	u8 rdma[0x1];
				2216	u8 write[0x1];
				2217	u8 requestor[0x1];
				2218	u8 qp_number[0x18];
				2219	};
				2220
				2221	struct mlx5_ifc_wqe_associated_page_fault_event_bits {
				2222	u8 bytes_committed[0x20];
				2223
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2224	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2225	u8 wqe_index[0x10];
				2226
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2227	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2228	u8 len[0x10];
				2229
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2230	u8 reserved_at_60[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2231
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2232	u8 reserved_at_c0[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2233	u8 rdma[0x1];
				2234	u8 write_read[0x1];
				2235	u8 requestor[0x1];
				2236	u8 qpn[0x18];
				2237	};
				2238
				2239	struct mlx5_ifc_qp_events_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2240	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2241
				2242	u8 type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2243	u8 reserved_at_a8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2244
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2245	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2246	u8 qpn_rqn_sqn[0x18];
				2247	};
				2248
				2249	struct mlx5_ifc_dct_events_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2250	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2251
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2252	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2253	u8 dct_number[0x18];
				2254	};
				2255
				2256	struct mlx5_ifc_comp_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2257	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2258
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2259	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2260	u8 cq_number[0x18];
				2261	};
				2262
				2263	enum {
				2264	MLX5_QPC_STATE_RST = 0x0,
				2265	MLX5_QPC_STATE_INIT = 0x1,
				2266	MLX5_QPC_STATE_RTR = 0x2,
				2267	MLX5_QPC_STATE_RTS = 0x3,
				2268	MLX5_QPC_STATE_SQER = 0x4,
				2269	MLX5_QPC_STATE_ERR = 0x6,
				2270	MLX5_QPC_STATE_SQD = 0x7,
				2271	MLX5_QPC_STATE_SUSPENDED = 0x9,
				2272	};
				2273
				2274	enum {
				2275	MLX5_QPC_ST_RC = 0x0,
				2276	MLX5_QPC_ST_UC = 0x1,
				2277	MLX5_QPC_ST_UD = 0x2,
				2278	MLX5_QPC_ST_XRC = 0x3,
				2279	MLX5_QPC_ST_DCI = 0x5,
				2280	MLX5_QPC_ST_QP0 = 0x7,
				2281	MLX5_QPC_ST_QP1 = 0x8,
				2282	MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
				2283	MLX5_QPC_ST_REG_UMR = 0xc,
				2284	};
				2285
				2286	enum {
				2287	MLX5_QPC_PM_STATE_ARMED = 0x0,
				2288	MLX5_QPC_PM_STATE_REARM = 0x1,
				2289	MLX5_QPC_PM_STATE_RESERVED = 0x2,
				2290	MLX5_QPC_PM_STATE_MIGRATED = 0x3,
				2291	};
				2292
				2293	enum {
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	2294	MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
				2295	};
				2296
				2297	enum {
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2298	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
				2299	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
				2300	};
				2301
				2302	enum {
				2303	MLX5_QPC_MTU_256_BYTES = 0x1,
				2304	MLX5_QPC_MTU_512_BYTES = 0x2,
				2305	MLX5_QPC_MTU_1K_BYTES = 0x3,
				2306	MLX5_QPC_MTU_2K_BYTES = 0x4,
				2307	MLX5_QPC_MTU_4K_BYTES = 0x5,
				2308	MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
				2309	};
				2310
				2311	enum {
				2312	MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
				2313	MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
				2314	MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
				2315	MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
				2316	MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
				2317	MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
				2318	MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
				2319	MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
				2320	};
				2321
				2322	enum {
				2323	MLX5_QPC_CS_REQ_DISABLE = 0x0,
				2324	MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
				2325	MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
				2326	};
				2327
				2328	enum {
				2329	MLX5_QPC_CS_RES_DISABLE = 0x0,
				2330	MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
				2331	MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
				2332	};
				2333
				2334	struct mlx5_ifc_qpc_bits {
				2335	u8 state[0x4];
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	2336	u8 lag_tx_port_affinity[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2337	u8 st[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2338	u8 reserved_at_10[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2339	u8 pm_state[0x2];
Danit Goldberg	3fd3c80	2018-11-30 13:22:04 +0200	[diff] [blame]	2340	u8 reserved_at_15[0x1];
				2341	u8 req_e2e_credit_mode[0x2];
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	2342	u8 offload_type[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2343	u8 end_padding_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2344	u8 reserved_at_1e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2345
				2346	u8 wq_signature[0x1];
				2347	u8 block_lb_mc[0x1];
				2348	u8 atomic_like_write_en[0x1];
				2349	u8 latency_sensitive[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2350	u8 reserved_at_24[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2351	u8 drain_sigerr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2352	u8 reserved_at_26[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2353	u8 pd[0x18];
				2354
				2355	u8 mtu[0x3];
				2356	u8 log_msg_max[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2357	u8 reserved_at_48[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2358	u8 log_rq_size[0x4];
				2359	u8 log_rq_stride[0x3];
				2360	u8 no_sq[0x1];
				2361	u8 log_sq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2362	u8 reserved_at_55[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2363	u8 rlky[0x1];
Erez Shitrit	1015c2e	2016-02-21 16:27:16 +0200	[diff] [blame]	2364	u8 ulp_stateless_offload_mode[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2365
				2366	u8 counter_set_id[0x8];
				2367	u8 uar_page[0x18];
				2368
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2369	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2370	u8 user_index[0x18];
				2371
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2372	u8 reserved_at_a0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2373	u8 log_page_size[0x5];
				2374	u8 remote_qpn[0x18];
				2375
				2376	struct mlx5_ifc_ads_bits primary_address_path;
				2377
				2378	struct mlx5_ifc_ads_bits secondary_address_path;
				2379
				2380	u8 log_ack_req_freq[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2381	u8 reserved_at_384[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2382	u8 log_sra_max[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2383	u8 reserved_at_38b[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2384	u8 retry_count[0x3];
				2385	u8 rnr_retry[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2386	u8 reserved_at_393[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2387	u8 fre[0x1];
				2388	u8 cur_rnr_retry[0x3];
				2389	u8 cur_retry_count[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2390	u8 reserved_at_39b[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2391
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2392	u8 reserved_at_3a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2393
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2394	u8 reserved_at_3c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2395	u8 next_send_psn[0x18];
				2396
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2397	u8 reserved_at_3e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2398	u8 cqn_snd[0x18];
				2399
Saeed Mahameed	09a7d9e	2016-07-19 01:17:59 +0300	[diff] [blame]	2400	u8 reserved_at_400[0x8];
				2401	u8 deth_sqpn[0x18];
				2402
				2403	u8 reserved_at_420[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2404
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2405	u8 reserved_at_440[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2406	u8 last_acked_psn[0x18];
				2407
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2408	u8 reserved_at_460[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2409	u8 ssn[0x18];
				2410
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2411	u8 reserved_at_480[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2412	u8 log_rra_max[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2413	u8 reserved_at_48b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2414	u8 atomic_mode[0x4];
				2415	u8 rre[0x1];
				2416	u8 rwe[0x1];
				2417	u8 rae[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2418	u8 reserved_at_493[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2419	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2420	u8 reserved_at_49a[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2421	u8 cd_slave_receive[0x1];
				2422	u8 cd_slave_send[0x1];
				2423	u8 cd_master[0x1];
				2424
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2425	u8 reserved_at_4a0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2426	u8 min_rnr_nak[0x5];
				2427	u8 next_rcv_psn[0x18];
				2428
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2429	u8 reserved_at_4c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2430	u8 xrcd[0x18];
				2431
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2432	u8 reserved_at_4e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2433	u8 cqn_rcv[0x18];
				2434
				2435	u8 dbr_addr[0x40];
				2436
				2437	u8 q_key[0x20];
				2438
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2439	u8 reserved_at_560[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2440	u8 rq_type[0x3];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2441	u8 srqn_rmpn_xrqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2442
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2443	u8 reserved_at_580[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2444	u8 rmsn[0x18];
				2445
				2446	u8 hw_sq_wqebb_counter[0x10];
				2447	u8 sw_sq_wqebb_counter[0x10];
				2448
				2449	u8 hw_rq_counter[0x20];
				2450
				2451	u8 sw_rq_counter[0x20];
				2452
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2453	u8 reserved_at_600[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2454
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2455	u8 reserved_at_620[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2456	u8 cgs[0x1];
				2457	u8 cs_req[0x8];
				2458	u8 cs_res[0x8];
				2459
				2460	u8 dc_access_key[0x40];
				2461
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	2462	u8 reserved_at_680[0x3];
				2463	u8 dbr_umem_valid[0x1];
				2464
				2465	u8 reserved_at_684[0xbc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2466	};
				2467
				2468	struct mlx5_ifc_roce_addr_layout_bits {
				2469	u8 source_l3_address[16][0x8];
				2470
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2471	u8 reserved_at_80[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2472	u8 vlan_valid[0x1];
				2473	u8 vlan_id[0xc];
				2474	u8 source_mac_47_32[0x10];
				2475
				2476	u8 source_mac_31_0[0x20];
				2477
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2478	u8 reserved_at_c0[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2479	u8 roce_l3_type[0x4];
				2480	u8 roce_version[0x8];
				2481
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2482	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2483	};
				2484
				2485	union mlx5_ifc_hca_cap_union_bits {
				2486	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
				2487	struct mlx5_ifc_odp_cap_bits odp_cap;
				2488	struct mlx5_ifc_atomic_caps_bits atomic_caps;
				2489	struct mlx5_ifc_roce_cap_bits roce_cap;
				2490	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
				2491	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	2492	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	2493	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	2494	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2495	struct mlx5_ifc_qos_cap_bits qos_cap;
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	2496	struct mlx5_ifc_fpga_cap_bits fpga_cap;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2497	u8 reserved_at_0[0x8000];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2498	};
				2499
				2500	enum {
				2501	MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
				2502	MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
				2503	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2504	MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	2505	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	2506	MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	2507	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2508	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
				2509	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	2510	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
				2511	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2512	};
				2513
				2514	struct mlx5_ifc_vlan_bits {
				2515	u8 ethtype[0x10];
				2516	u8 prio[0x3];
				2517	u8 cfi[0x1];
				2518	u8 vid[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2519	};
				2520
				2521	struct mlx5_ifc_flow_context_bits {
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2522	struct mlx5_ifc_vlan_bits push_vlan;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2523
				2524	u8 group_id[0x20];
				2525
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2526	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2527	u8 flow_tag[0x18];
				2528
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2529	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2530	u8 action[0x10];
				2531
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	2532	u8 extended_destination[0x1];
				2533	u8 reserved_at_80[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2534	u8 destination_list_size[0x18];
				2535
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2536	u8 reserved_at_a0[0x8];
				2537	u8 flow_counter_list_size[0x18];
				2538
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	2539	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	2540
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	2541	u8 modify_header_id[0x20];
				2542
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	2543	struct mlx5_ifc_vlan_bits push_vlan_2;
				2544
				2545	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2546
				2547	struct mlx5_ifc_fte_match_param_bits match_value;
				2548
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2549	u8 reserved_at_1200[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2550
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2551	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2552	};
				2553
				2554	enum {
				2555	MLX5_XRC_SRQC_STATE_GOOD = 0x0,
				2556	MLX5_XRC_SRQC_STATE_ERROR = 0x1,
				2557	};
				2558
				2559	struct mlx5_ifc_xrc_srqc_bits {
				2560	u8 state[0x4];
				2561	u8 log_xrc_srq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2562	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2563
				2564	u8 wq_signature[0x1];
				2565	u8 cont_srq[0x1];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	2566	u8 reserved_at_22[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2567	u8 rlky[0x1];
				2568	u8 basic_cyclic_rcv_wqe[0x1];
				2569	u8 log_rq_stride[0x3];
				2570	u8 xrcd[0x18];
				2571
				2572	u8 page_offset[0x6];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	2573	u8 reserved_at_46[0x1];
				2574	u8 dbr_umem_valid[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2575	u8 cqn[0x18];
				2576
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2577	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2578
				2579	u8 user_index_equal_xrc_srqn[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2580	u8 reserved_at_81[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2581	u8 log_page_size[0x6];
				2582	u8 user_index[0x18];
				2583
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2584	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2585
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2586	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2587	u8 pd[0x18];
				2588
				2589	u8 lwm[0x10];
				2590	u8 wqe_cnt[0x10];
				2591
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2592	u8 reserved_at_100[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2593
				2594	u8 db_record_addr_h[0x20];
				2595
				2596	u8 db_record_addr_l[0x1e];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2597	u8 reserved_at_17e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2598
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2599	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2600	};
				2601
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	2602	struct mlx5_ifc_vnic_diagnostic_statistics_bits {
				2603	u8 counter_error_queues[0x20];
				2604
				2605	u8 total_error_queues[0x20];
				2606
				2607	u8 send_queue_priority_update_flow[0x20];
				2608
				2609	u8 reserved_at_60[0x20];
				2610
				2611	u8 nic_receive_steering_discard[0x40];
				2612
				2613	u8 receive_discard_vport_down[0x40];
				2614
				2615	u8 transmit_discard_vport_down[0x40];
				2616
				2617	u8 reserved_at_140[0xec0];
				2618	};
				2619
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2620	struct mlx5_ifc_traffic_counter_bits {
				2621	u8 packets[0x40];
				2622
				2623	u8 octets[0x40];
				2624	};
				2625
				2626	struct mlx5_ifc_tisc_bits {
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	2627	u8 strict_lag_tx_port_affinity[0x1];
				2628	u8 reserved_at_1[0x3];
				2629	u8 lag_tx_port_affinity[0x04];
				2630
				2631	u8 reserved_at_8[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2632	u8 prio[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2633	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2634
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2635	u8 reserved_at_20[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2636
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2637	u8 reserved_at_120[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2638	u8 transport_domain[0x18];
				2639
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	2640	u8 reserved_at_140[0x8];
				2641	u8 underlay_qpn[0x18];
				2642	u8 reserved_at_160[0x3a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2643	};
				2644
				2645	enum {
				2646	MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
				2647	MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
				2648	};
				2649
				2650	enum {
				2651	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
				2652	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
				2653	};
				2654
				2655	enum {
Saeed Mahameed	2be6967	2015-07-23 23:35:56 +0300	[diff] [blame]	2656	MLX5_RX_HASH_FN_NONE = 0x0,
				2657	MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
				2658	MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2659	};
				2660
				2661	enum {
Mark Bloch	5d773ff	2018-09-17 13:30:46 +0300	[diff] [blame]	2662	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
				2663	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2664	};
				2665
				2666	struct mlx5_ifc_tirc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2667	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2668
				2669	u8 disp_type[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2670	u8 reserved_at_24[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2671
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2672	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2673
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2674	u8 reserved_at_80[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2675	u8 lro_timeout_period_usecs[0x10];
				2676	u8 lro_enable_mask[0x4];
				2677	u8 lro_max_ip_payload_size[0x8];
				2678
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2679	u8 reserved_at_a0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2680
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2681	u8 reserved_at_e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2682	u8 inline_rqn[0x18];
				2683
				2684	u8 rx_hash_symmetric[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2685	u8 reserved_at_101[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2686	u8 tunneled_offload_en[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2687	u8 reserved_at_103[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2688	u8 indirect_table[0x18];
				2689
				2690	u8 rx_hash_fn[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2691	u8 reserved_at_124[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2692	u8 self_lb_block[0x2];
				2693	u8 transport_domain[0x18];
				2694
				2695	u8 rx_hash_toeplitz_key[10][0x20];
				2696
				2697	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
				2698
				2699	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
				2700
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2701	u8 reserved_at_2c0[0x4c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2702	};
				2703
				2704	enum {
				2705	MLX5_SRQC_STATE_GOOD = 0x0,
				2706	MLX5_SRQC_STATE_ERROR = 0x1,
				2707	};
				2708
				2709	struct mlx5_ifc_srqc_bits {
				2710	u8 state[0x4];
				2711	u8 log_srq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2712	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2713
				2714	u8 wq_signature[0x1];
				2715	u8 cont_srq[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2716	u8 reserved_at_22[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2717	u8 rlky[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2718	u8 reserved_at_24[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2719	u8 log_rq_stride[0x3];
				2720	u8 xrcd[0x18];
				2721
				2722	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2723	u8 reserved_at_46[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2724	u8 cqn[0x18];
				2725
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2726	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2727
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2728	u8 reserved_at_80[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2729	u8 log_page_size[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2730	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2731
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2732	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2733
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2734	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2735	u8 pd[0x18];
				2736
				2737	u8 lwm[0x10];
				2738	u8 wqe_cnt[0x10];
				2739
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2740	u8 reserved_at_100[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2741
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	2742	u8 dbr_addr[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2743
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2744	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2745	};
				2746
				2747	enum {
				2748	MLX5_SQC_STATE_RST = 0x0,
				2749	MLX5_SQC_STATE_RDY = 0x1,
				2750	MLX5_SQC_STATE_ERR = 0x3,
				2751	};
				2752
				2753	struct mlx5_ifc_sqc_bits {
				2754	u8 rlky[0x1];
				2755	u8 cd_master[0x1];
				2756	u8 fre[0x1];
				2757	u8 flush_in_error_en[0x1];
Bodong Wang	795b609	2017-08-17 15:52:34 +0300	[diff] [blame]	2758	u8 allow_multi_pkt_send_wqe[0x1];
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	2759	u8 min_wqe_inline_mode[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2760	u8 state[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	2761	u8 reg_umr[0x1];
Ilan Tayari	547eede	2017-04-18 16:04:28 +0300	[diff] [blame]	2762	u8 allow_swp[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2763	u8 hairpin[0x1];
				2764	u8 reserved_at_f[0x11];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2765
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2766	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2767	u8 user_index[0x18];
				2768
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2769	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2770	u8 cqn[0x18];
				2771
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2772	u8 reserved_at_60[0x8];
				2773	u8 hairpin_peer_rq[0x18];
				2774
				2775	u8 reserved_at_80[0x10];
				2776	u8 hairpin_peer_vhca[0x10];
				2777
				2778	u8 reserved_at_a0[0x50];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2779
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2780	u8 packet_pacing_rate_limit_index[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2781	u8 tis_lst_sz[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2782	u8 reserved_at_110[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2783
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2784	u8 reserved_at_120[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2785
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2786	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2787	u8 tis_num_0[0x18];
				2788
				2789	struct mlx5_ifc_wq_bits wq;
				2790	};
				2791
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	2792	enum {
				2793	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
				2794	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
				2795	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
				2796	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
				2797	};
				2798
				2799	struct mlx5_ifc_scheduling_context_bits {
				2800	u8 element_type[0x8];
				2801	u8 reserved_at_8[0x18];
				2802
				2803	u8 element_attributes[0x20];
				2804
				2805	u8 parent_element_id[0x20];
				2806
				2807	u8 reserved_at_60[0x40];
				2808
				2809	u8 bw_share[0x20];
				2810
				2811	u8 max_average_bw[0x20];
				2812
				2813	u8 reserved_at_e0[0x120];
				2814	};
				2815
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2816	struct mlx5_ifc_rqtc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2817	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2818
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2819	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2820	u8 rqt_max_size[0x10];
				2821
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2822	u8 reserved_at_c0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2823	u8 rqt_actual_size[0x10];
				2824
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2825	u8 reserved_at_e0[0x6a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2826
				2827	struct mlx5_ifc_rq_num_bits rq_num[0];
				2828	};
				2829
				2830	enum {
				2831	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
				2832	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
				2833	};
				2834
				2835	enum {
				2836	MLX5_RQC_STATE_RST = 0x0,
				2837	MLX5_RQC_STATE_RDY = 0x1,
				2838	MLX5_RQC_STATE_ERR = 0x3,
				2839	};
				2840
				2841	struct mlx5_ifc_rqc_bits {
				2842	u8 rlky[0x1];
Maor Gottlieb	03404e8	2017-05-30 10:29:13 +0300	[diff] [blame]	2843	u8 delay_drop_en[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	2844	u8 scatter_fcs[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2845	u8 vsd[0x1];
				2846	u8 mem_rq_type[0x4];
				2847	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2848	u8 reserved_at_c[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2849	u8 flush_in_error_en[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2850	u8 hairpin[0x1];
				2851	u8 reserved_at_f[0x11];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2852
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2853	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2854	u8 user_index[0x18];
				2855
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2856	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2857	u8 cqn[0x18];
				2858
				2859	u8 counter_set_id[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2860	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2861
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2862	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2863	u8 rmpn[0x18];
				2864
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2865	u8 reserved_at_a0[0x8];
				2866	u8 hairpin_peer_sq[0x18];
				2867
				2868	u8 reserved_at_c0[0x10];
				2869	u8 hairpin_peer_vhca[0x10];
				2870
				2871	u8 reserved_at_e0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2872
				2873	struct mlx5_ifc_wq_bits wq;
				2874	};
				2875
				2876	enum {
				2877	MLX5_RMPC_STATE_RDY = 0x1,
				2878	MLX5_RMPC_STATE_ERR = 0x3,
				2879	};
				2880
				2881	struct mlx5_ifc_rmpc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2882	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2883	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2884	u8 reserved_at_c[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2885
				2886	u8 basic_cyclic_rcv_wqe[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2887	u8 reserved_at_21[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2888
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2889	u8 reserved_at_40[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2890
				2891	struct mlx5_ifc_wq_bits wq;
				2892	};
				2893
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2894	struct mlx5_ifc_nic_vport_context_bits {
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	2895	u8 reserved_at_0[0x5];
				2896	u8 min_wqe_inline_mode[0x3];
Huy Nguyen	bded747	2017-05-30 09:42:53 +0300	[diff] [blame]	2897	u8 reserved_at_8[0x15];
				2898	u8 disable_mc_local_lb[0x1];
				2899	u8 disable_uc_local_lb[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2900	u8 roce_en[0x1];
				2901
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2902	u8 arm_change_event[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2903	u8 reserved_at_21[0x1a];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2904	u8 event_on_mtu[0x1];
				2905	u8 event_on_promisc_change[0x1];
				2906	u8 event_on_vlan_change[0x1];
				2907	u8 event_on_mc_address_change[0x1];
				2908	u8 event_on_uc_address_change[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2909
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	2910	u8 reserved_at_40[0xc];
				2911
				2912	u8 affiliation_criteria[0x4];
				2913	u8 affiliated_vhca_id[0x10];
				2914
				2915	u8 reserved_at_60[0xd0];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2916
				2917	u8 mtu[0x10];
				2918
Achiad Shochat	9efa752	2015-12-23 18:47:20 +0200	[diff] [blame]	2919	u8 system_image_guid[0x40];
				2920	u8 port_guid[0x40];
				2921	u8 node_guid[0x40];
				2922
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2923	u8 reserved_at_200[0x140];
Achiad Shochat	9efa752	2015-12-23 18:47:20 +0200	[diff] [blame]	2924	u8 qkey_violation_counter[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2925	u8 reserved_at_350[0x430];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2926
				2927	u8 promisc_uc[0x1];
				2928	u8 promisc_mc[0x1];
				2929	u8 promisc_all[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2930	u8 reserved_at_783[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2931	u8 allowed_list_type[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2932	u8 reserved_at_788[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2933	u8 allowed_list_size[0xc];
				2934
				2935	struct mlx5_ifc_mac_address_layout_bits permanent_address;
				2936
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2937	u8 reserved_at_7e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2938
				2939	u8 current_uc_mac_address[0][0x40];
				2940	};
				2941
				2942	enum {
				2943	MLX5_MKC_ACCESS_MODE_PA = 0x0,
				2944	MLX5_MKC_ACCESS_MODE_MTT = 0x1,
				2945	MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	2946	MLX5_MKC_ACCESS_MODE_KSM = 0x3,
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	2947	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2948	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2949	};
				2950
				2951	struct mlx5_ifc_mkc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2952	u8 reserved_at_0[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2953	u8 free[0x1];
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2954	u8 reserved_at_2[0x1];
				2955	u8 access_mode_4_2[0x3];
				2956	u8 reserved_at_6[0x7];
				2957	u8 relaxed_ordering_write[0x1];
				2958	u8 reserved_at_e[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2959	u8 small_fence_on_rdma_read_response[0x1];
				2960	u8 umr_en[0x1];
				2961	u8 a[0x1];
				2962	u8 rw[0x1];
				2963	u8 rr[0x1];
				2964	u8 lw[0x1];
				2965	u8 lr[0x1];
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2966	u8 access_mode_1_0[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2967	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2968
				2969	u8 qpn[0x18];
				2970	u8 mkey_7_0[0x8];
				2971
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2972	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2973
				2974	u8 length64[0x1];
				2975	u8 bsf_en[0x1];
				2976	u8 sync_umr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2977	u8 reserved_at_63[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2978	u8 expected_sigerr_count[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2979	u8 reserved_at_66[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2980	u8 en_rinval[0x1];
				2981	u8 pd[0x18];
				2982
				2983	u8 start_addr[0x40];
				2984
				2985	u8 len[0x40];
				2986
				2987	u8 bsf_octword_size[0x20];
				2988
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2989	u8 reserved_at_120[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2990
				2991	u8 translations_octword_size[0x20];
				2992
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2993	u8 reserved_at_1c0[0x1b];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2994	u8 log_page_size[0x5];
				2995
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2996	u8 reserved_at_1e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2997	};
				2998
				2999	struct mlx5_ifc_pkey_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3000	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3001	u8 pkey[0x10];
				3002	};
				3003
				3004	struct mlx5_ifc_array128_auto_bits {
				3005	u8 array128_auto[16][0x8];
				3006	};
				3007
				3008	struct mlx5_ifc_hca_vport_context_bits {
				3009	u8 field_select[0x20];
				3010
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3011	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3012
				3013	u8 sm_virt_aware[0x1];
				3014	u8 has_smi[0x1];
				3015	u8 has_raw[0x1];
				3016	u8 grh_required[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3017	u8 reserved_at_104[0xc];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	3018	u8 port_physical_state[0x4];
				3019	u8 vport_state_policy[0x4];
				3020	u8 port_state[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3021	u8 vport_state[0x4];
				3022
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3023	u8 reserved_at_120[0x20];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	3024
				3025	u8 system_image_guid[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3026
				3027	u8 port_guid[0x40];
				3028
				3029	u8 node_guid[0x40];
				3030
				3031	u8 cap_mask1[0x20];
				3032
				3033	u8 cap_mask1_field_select[0x20];
				3034
				3035	u8 cap_mask2[0x20];
				3036
				3037	u8 cap_mask2_field_select[0x20];
				3038
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3039	u8 reserved_at_280[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3040
				3041	u8 lid[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3042	u8 reserved_at_310[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3043	u8 init_type_reply[0x4];
				3044	u8 lmc[0x3];
				3045	u8 subnet_timeout[0x5];
				3046
				3047	u8 sm_lid[0x10];
				3048	u8 sm_sl[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3049	u8 reserved_at_334[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3050
				3051	u8 qkey_violation_counter[0x10];
				3052	u8 pkey_violation_counter[0x10];
				3053
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3054	u8 reserved_at_360[0xca0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3055	};
				3056
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3057	struct mlx5_ifc_esw_vport_context_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3058	u8 reserved_at_0[0x3];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3059	u8 vport_svlan_strip[0x1];
				3060	u8 vport_cvlan_strip[0x1];
				3061	u8 vport_svlan_insert[0x1];
				3062	u8 vport_cvlan_insert[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3063	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3064
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3065	u8 reserved_at_20[0x20];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3066
				3067	u8 svlan_cfi[0x1];
				3068	u8 svlan_pcp[0x3];
				3069	u8 svlan_id[0xc];
				3070	u8 cvlan_cfi[0x1];
				3071	u8 cvlan_pcp[0x3];
				3072	u8 cvlan_id[0xc];
				3073
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3074	u8 reserved_at_60[0x7a0];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3075	};
				3076
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3077	enum {
				3078	MLX5_EQC_STATUS_OK = 0x0,
				3079	MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
				3080	};
				3081
				3082	enum {
				3083	MLX5_EQC_ST_ARMED = 0x9,
				3084	MLX5_EQC_ST_FIRED = 0xa,
				3085	};
				3086
				3087	struct mlx5_ifc_eqc_bits {
				3088	u8 status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3089	u8 reserved_at_4[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3090	u8 ec[0x1];
				3091	u8 oi[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3092	u8 reserved_at_f[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3093	u8 st[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3094	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3095
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3096	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3097
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3098	u8 reserved_at_40[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3099	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3100	u8 reserved_at_5a[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3101
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3102	u8 reserved_at_60[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3103	u8 log_eq_size[0x5];
				3104	u8 uar_page[0x18];
				3105
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3106	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3107
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3108	u8 reserved_at_a0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3109	u8 intr[0x8];
				3110
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3111	u8 reserved_at_c0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3112	u8 log_page_size[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3113	u8 reserved_at_c8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3114
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3115	u8 reserved_at_e0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3116
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3117	u8 reserved_at_140[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3118	u8 consumer_counter[0x18];
				3119
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3120	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3121	u8 producer_counter[0x18];
				3122
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3123	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3124	};
				3125
				3126	enum {
				3127	MLX5_DCTC_STATE_ACTIVE = 0x0,
				3128	MLX5_DCTC_STATE_DRAINING = 0x1,
				3129	MLX5_DCTC_STATE_DRAINED = 0x2,
				3130	};
				3131
				3132	enum {
				3133	MLX5_DCTC_CS_RES_DISABLE = 0x0,
				3134	MLX5_DCTC_CS_RES_NA = 0x1,
				3135	MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
				3136	};
				3137
				3138	enum {
				3139	MLX5_DCTC_MTU_256_BYTES = 0x1,
				3140	MLX5_DCTC_MTU_512_BYTES = 0x2,
				3141	MLX5_DCTC_MTU_1K_BYTES = 0x3,
				3142	MLX5_DCTC_MTU_2K_BYTES = 0x4,
				3143	MLX5_DCTC_MTU_4K_BYTES = 0x5,
				3144	};
				3145
				3146	struct mlx5_ifc_dctc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3147	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3148	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3149	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3150
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3151	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3152	u8 user_index[0x18];
				3153
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3154	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3155	u8 cqn[0x18];
				3156
				3157	u8 counter_set_id[0x8];
				3158	u8 atomic_mode[0x4];
				3159	u8 rre[0x1];
				3160	u8 rwe[0x1];
				3161	u8 rae[0x1];
				3162	u8 atomic_like_write_en[0x1];
				3163	u8 latency_sensitive[0x1];
				3164	u8 rlky[0x1];
				3165	u8 free_ar[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3166	u8 reserved_at_73[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3167
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3168	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3169	u8 cs_res[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3170	u8 reserved_at_90[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3171	u8 min_rnr_nak[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3172	u8 reserved_at_98[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3173
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3174	u8 reserved_at_a0[0x8];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3175	u8 srqn_xrqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3176
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3177	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3178	u8 pd[0x18];
				3179
				3180	u8 tclass[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3181	u8 reserved_at_e8[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3182	u8 flow_label[0x14];
				3183
				3184	u8 dc_access_key[0x40];
				3185
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3186	u8 reserved_at_140[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3187	u8 mtu[0x3];
				3188	u8 port[0x8];
				3189	u8 pkey_index[0x10];
				3190
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3191	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3192	u8 my_addr_index[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3193	u8 reserved_at_170[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3194	u8 hop_limit[0x8];
				3195
				3196	u8 dc_access_key_violation_count[0x20];
				3197
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3198	u8 reserved_at_1a0[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3199	u8 dei_cfi[0x1];
				3200	u8 eth_prio[0x3];
				3201	u8 ecn[0x2];
				3202	u8 dscp[0x6];
				3203
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3204	u8 reserved_at_1c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3205	};
				3206
				3207	enum {
				3208	MLX5_CQC_STATUS_OK = 0x0,
				3209	MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
				3210	MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
				3211	};
				3212
				3213	enum {
				3214	MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
				3215	MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
				3216	};
				3217
				3218	enum {
				3219	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
				3220	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
				3221	MLX5_CQC_ST_FIRED = 0xa,
				3222	};
				3223
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3224	enum {
				3225	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
				3226	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3227	MLX5_CQ_PERIOD_NUM_MODES
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3228	};
				3229
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3230	struct mlx5_ifc_cqc_bits {
				3231	u8 status[0x4];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	3232	u8 reserved_at_4[0x2];
				3233	u8 dbr_umem_valid[0x1];
				3234	u8 reserved_at_7[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3235	u8 cqe_sz[0x3];
				3236	u8 cc[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3237	u8 reserved_at_c[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3238	u8 scqe_break_moderation_en[0x1];
				3239	u8 oi[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3240	u8 cq_period_mode[0x2];
				3241	u8 cqe_comp_en[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3242	u8 mini_cqe_res_format[0x2];
				3243	u8 st[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3244	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3245
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3246	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3247
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3248	u8 reserved_at_40[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3249	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3250	u8 reserved_at_5a[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3251
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3252	u8 reserved_at_60[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3253	u8 log_cq_size[0x5];
				3254	u8 uar_page[0x18];
				3255
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3256	u8 reserved_at_80[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3257	u8 cq_period[0xc];
				3258	u8 cq_max_count[0x10];
				3259
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3260	u8 reserved_at_a0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3261	u8 c_eqn[0x8];
				3262
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3263	u8 reserved_at_c0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3264	u8 log_page_size[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3265	u8 reserved_at_c8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3266
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3267	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3268
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3269	u8 reserved_at_100[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3270	u8 last_notified_index[0x18];
				3271
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3272	u8 reserved_at_120[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3273	u8 last_solicit_index[0x18];
				3274
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3275	u8 reserved_at_140[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3276	u8 consumer_counter[0x18];
				3277
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3278	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3279	u8 producer_counter[0x18];
				3280
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3281	u8 reserved_at_180[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3282
				3283	u8 dbr_addr[0x40];
				3284	};
				3285
				3286	union mlx5_ifc_cong_control_roce_ecn_auto_bits {
				3287	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
				3288	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
				3289	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3290	u8 reserved_at_0[0x800];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3291	};
				3292
				3293	struct mlx5_ifc_query_adapter_param_block_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3294	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3295
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3296	u8 reserved_at_c0[0x8];
Majd Dibbiny	211e6c8	2015-06-04 19:30:42 +0300	[diff] [blame]	3297	u8 ieee_vendor_id[0x18];
				3298
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3299	u8 reserved_at_e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3300	u8 vsd_vendor_id[0x10];
				3301
				3302	u8 vsd[208][0x8];
				3303
				3304	u8 vsd_contd_psid[16][0x8];
				3305	};
				3306
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3307	enum {
				3308	MLX5_XRQC_STATE_GOOD = 0x0,
				3309	MLX5_XRQC_STATE_ERROR = 0x1,
				3310	};
				3311
				3312	enum {
				3313	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
				3314	MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
				3315	};
				3316
				3317	enum {
				3318	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
				3319	};
				3320
				3321	struct mlx5_ifc_tag_matching_topology_context_bits {
				3322	u8 log_matching_list_sz[0x4];
				3323	u8 reserved_at_4[0xc];
				3324	u8 append_next_index[0x10];
				3325
				3326	u8 sw_phase_cnt[0x10];
				3327	u8 hw_phase_cnt[0x10];
				3328
				3329	u8 reserved_at_40[0x40];
				3330	};
				3331
				3332	struct mlx5_ifc_xrqc_bits {
				3333	u8 state[0x4];
				3334	u8 rlkey[0x1];
				3335	u8 reserved_at_5[0xf];
				3336	u8 topology[0x4];
				3337	u8 reserved_at_18[0x4];
				3338	u8 offload[0x4];
				3339
				3340	u8 reserved_at_20[0x8];
				3341	u8 user_index[0x18];
				3342
				3343	u8 reserved_at_40[0x8];
				3344	u8 cqn[0x18];
				3345
				3346	u8 reserved_at_60[0xa0];
				3347
				3348	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
				3349
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	3350	u8 reserved_at_180[0x280];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3351
				3352	struct mlx5_ifc_wq_bits wq;
				3353	};
				3354
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3355	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
				3356	struct mlx5_ifc_modify_field_select_bits modify_field_select;
				3357	struct mlx5_ifc_resize_field_select_bits resize_field_select;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3358	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3359	};
				3360
				3361	union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
				3362	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
				3363	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
				3364	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3365	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3366	};
				3367
				3368	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
				3369	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
				3370	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
				3371	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
				3372	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
				3373	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
				3374	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
				3375	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	3376	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3377	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
Gal Pressman	d8dc050	2016-09-27 17:04:51 +0300	[diff] [blame]	3378	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3379	u8 reserved_at_0[0x7c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3380	};
				3381
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	3382	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
				3383	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
				3384	u8 reserved_at_0[0x7c0];
				3385	};
				3386
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3387	union mlx5_ifc_event_auto_bits {
				3388	struct mlx5_ifc_comp_event_bits comp_event;
				3389	struct mlx5_ifc_dct_events_bits dct_events;
				3390	struct mlx5_ifc_qp_events_bits qp_events;
				3391	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
				3392	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
				3393	struct mlx5_ifc_cq_error_bits cq_error;
				3394	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
				3395	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
				3396	struct mlx5_ifc_gpio_event_bits gpio_event;
				3397	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
				3398	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
				3399	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3400	u8 reserved_at_0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3401	};
				3402
				3403	struct mlx5_ifc_health_buffer_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3404	u8 reserved_at_0[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3405
				3406	u8 assert_existptr[0x20];
				3407
				3408	u8 assert_callra[0x20];
				3409
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3410	u8 reserved_at_140[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3411
				3412	u8 fw_version[0x20];
				3413
				3414	u8 hw_id[0x20];
				3415
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3416	u8 reserved_at_1c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3417
				3418	u8 irisc_index[0x8];
				3419	u8 synd[0x8];
				3420	u8 ext_synd[0x10];
				3421	};
				3422
				3423	struct mlx5_ifc_register_loopback_control_bits {
				3424	u8 no_lb[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3425	u8 reserved_at_1[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3426	u8 port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3427	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3428
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3429	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3430	};
				3431
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	3432	struct mlx5_ifc_vport_tc_element_bits {
				3433	u8 traffic_class[0x4];
				3434	u8 reserved_at_4[0xc];
				3435	u8 vport_number[0x10];
				3436	};
				3437
				3438	struct mlx5_ifc_vport_element_bits {
				3439	u8 reserved_at_0[0x10];
				3440	u8 vport_number[0x10];
				3441	};
				3442
				3443	enum {
				3444	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
				3445	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
				3446	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
				3447	};
				3448
				3449	struct mlx5_ifc_tsar_element_bits {
				3450	u8 reserved_at_0[0x8];
				3451	u8 tsar_type[0x8];
				3452	u8 reserved_at_10[0x10];
				3453	};
				3454
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3455	enum {
				3456	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
				3457	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
				3458	};
				3459
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3460	struct mlx5_ifc_teardown_hca_out_bits {
				3461	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3462	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3463
				3464	u8 syndrome[0x20];
				3465
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3466	u8 reserved_at_40[0x3f];
				3467
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	3468	u8 state[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3469	};
				3470
				3471	enum {
				3472	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3473	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	3474	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3475	};
				3476
				3477	struct mlx5_ifc_teardown_hca_in_bits {
				3478	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3479	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3480
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3481	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3482	u8 op_mod[0x10];
				3483
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3484	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3485	u8 profile[0x10];
				3486
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3487	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3488	};
				3489
				3490	struct mlx5_ifc_sqerr2rts_qp_out_bits {
				3491	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3492	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3493
				3494	u8 syndrome[0x20];
				3495
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3496	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3497	};
				3498
				3499	struct mlx5_ifc_sqerr2rts_qp_in_bits {
				3500	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3501	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3502
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3503	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3504	u8 op_mod[0x10];
				3505
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3506	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3507	u8 qpn[0x18];
				3508
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3509	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3510
				3511	u8 opt_param_mask[0x20];
				3512
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3513	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3514
				3515	struct mlx5_ifc_qpc_bits qpc;
				3516
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3517	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3518	};
				3519
				3520	struct mlx5_ifc_sqd2rts_qp_out_bits {
				3521	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3522	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3523
				3524	u8 syndrome[0x20];
				3525
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3526	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3527	};
				3528
				3529	struct mlx5_ifc_sqd2rts_qp_in_bits {
				3530	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3531	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3532
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3533	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3534	u8 op_mod[0x10];
				3535
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3536	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3537	u8 qpn[0x18];
				3538
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3539	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3540
				3541	u8 opt_param_mask[0x20];
				3542
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3543	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3544
				3545	struct mlx5_ifc_qpc_bits qpc;
				3546
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3547	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3548	};
				3549
				3550	struct mlx5_ifc_set_roce_address_out_bits {
				3551	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3552	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3553
				3554	u8 syndrome[0x20];
				3555
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3556	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3557	};
				3558
				3559	struct mlx5_ifc_set_roce_address_in_bits {
				3560	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3561	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3562
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3563	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3564	u8 op_mod[0x10];
				3565
				3566	u8 roce_address_index[0x10];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	3567	u8 reserved_at_50[0xc];
				3568	u8 vhca_port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3569
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3570	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3571
				3572	struct mlx5_ifc_roce_addr_layout_bits roce_address;
				3573	};
				3574
				3575	struct mlx5_ifc_set_mad_demux_out_bits {
				3576	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3577	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3578
				3579	u8 syndrome[0x20];
				3580
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3581	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3582	};
				3583
				3584	enum {
				3585	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
				3586	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
				3587	};
				3588
				3589	struct mlx5_ifc_set_mad_demux_in_bits {
				3590	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3591	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3592
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3593	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3594	u8 op_mod[0x10];
				3595
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3596	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3598	u8 reserved_at_60[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3599	u8 demux_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3600	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3601	};
				3602
				3603	struct mlx5_ifc_set_l2_table_entry_out_bits {
				3604	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3605	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3606
				3607	u8 syndrome[0x20];
				3608
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3609	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3610	};
				3611
				3612	struct mlx5_ifc_set_l2_table_entry_in_bits {
				3613	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3614	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3615
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3616	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3617	u8 op_mod[0x10];
				3618
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3619	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3620
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3621	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3622	u8 table_index[0x18];
				3623
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3624	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3625
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3626	u8 reserved_at_e0[0x13];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3627	u8 vlan_valid[0x1];
				3628	u8 vlan[0xc];
				3629
				3630	struct mlx5_ifc_mac_address_layout_bits mac_address;
				3631
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3632	u8 reserved_at_140[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3633	};
				3634
				3635	struct mlx5_ifc_set_issi_out_bits {
				3636	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3637	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3638
				3639	u8 syndrome[0x20];
				3640
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3641	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3642	};
				3643
				3644	struct mlx5_ifc_set_issi_in_bits {
				3645	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3646	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3647
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3648	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3649	u8 op_mod[0x10];
				3650
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3651	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3652	u8 current_issi[0x10];
				3653
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3654	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3655	};
				3656
				3657	struct mlx5_ifc_set_hca_cap_out_bits {
				3658	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3659	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3660
				3661	u8 syndrome[0x20];
				3662
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3663	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3664	};
				3665
				3666	struct mlx5_ifc_set_hca_cap_in_bits {
				3667	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3668	u8 reserved_at_10[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3669
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3670	u8 reserved_at_20[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3671	u8 op_mod[0x10];
				3672
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3673	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3674
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3675	union mlx5_ifc_hca_cap_union_bits capability;
				3676	};
				3677
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	3678	enum {
				3679	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
				3680	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
				3681	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
				3682	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
				3683	};
				3684
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3685	struct mlx5_ifc_set_fte_out_bits {
				3686	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3687	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3688
				3689	u8 syndrome[0x20];
				3690
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3691	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3692	};
				3693
				3694	struct mlx5_ifc_set_fte_in_bits {
				3695	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3696	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3697
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3698	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3699	u8 op_mod[0x10];
				3700
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3701	u8 other_vport[0x1];
				3702	u8 reserved_at_41[0xf];
				3703	u8 vport_number[0x10];
				3704
				3705	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3706
				3707	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3708	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3709
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3710	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3711	u8 table_id[0x18];
				3712
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3713	u8 reserved_at_c0[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	3714	u8 modify_enable_mask[0x8];
				3715
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3716	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3717
				3718	u8 flow_index[0x20];
				3719
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3720	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3721
				3722	struct mlx5_ifc_flow_context_bits flow_context;
				3723	};
				3724
				3725	struct mlx5_ifc_rts2rts_qp_out_bits {
				3726	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3727	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3728
				3729	u8 syndrome[0x20];
				3730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3731	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3732	};
				3733
				3734	struct mlx5_ifc_rts2rts_qp_in_bits {
				3735	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3736	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3737
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3738	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3739	u8 op_mod[0x10];
				3740
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3741	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3742	u8 qpn[0x18];
				3743
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3744	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3745
				3746	u8 opt_param_mask[0x20];
				3747
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3748	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3749
				3750	struct mlx5_ifc_qpc_bits qpc;
				3751
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3752	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3753	};
				3754
				3755	struct mlx5_ifc_rtr2rts_qp_out_bits {
				3756	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3757	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3758
				3759	u8 syndrome[0x20];
				3760
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3761	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3762	};
				3763
				3764	struct mlx5_ifc_rtr2rts_qp_in_bits {
				3765	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3766	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3767
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3768	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3769	u8 op_mod[0x10];
				3770
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3771	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3772	u8 qpn[0x18];
				3773
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3774	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3775
				3776	u8 opt_param_mask[0x20];
				3777
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3778	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3779
				3780	struct mlx5_ifc_qpc_bits qpc;
				3781
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3782	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3783	};
				3784
				3785	struct mlx5_ifc_rst2init_qp_out_bits {
				3786	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3787	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3788
				3789	u8 syndrome[0x20];
				3790
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3791	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3792	};
				3793
				3794	struct mlx5_ifc_rst2init_qp_in_bits {
				3795	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3796	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3797
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3798	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3799	u8 op_mod[0x10];
				3800
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3801	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3802	u8 qpn[0x18];
				3803
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3804	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3805
				3806	u8 opt_param_mask[0x20];
				3807
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3808	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3809
				3810	struct mlx5_ifc_qpc_bits qpc;
				3811
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3812	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3813	};
				3814
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3815	struct mlx5_ifc_query_xrq_out_bits {
				3816	u8 status[0x8];
				3817	u8 reserved_at_8[0x18];
				3818
				3819	u8 syndrome[0x20];
				3820
				3821	u8 reserved_at_40[0x40];
				3822
				3823	struct mlx5_ifc_xrqc_bits xrq_context;
				3824	};
				3825
				3826	struct mlx5_ifc_query_xrq_in_bits {
				3827	u8 opcode[0x10];
				3828	u8 reserved_at_10[0x10];
				3829
				3830	u8 reserved_at_20[0x10];
				3831	u8 op_mod[0x10];
				3832
				3833	u8 reserved_at_40[0x8];
				3834	u8 xrqn[0x18];
				3835
				3836	u8 reserved_at_60[0x20];
				3837	};
				3838
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3839	struct mlx5_ifc_query_xrc_srq_out_bits {
				3840	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3841	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3842
				3843	u8 syndrome[0x20];
				3844
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3845	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3846
				3847	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
				3848
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3849	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3850
				3851	u8 pas[0][0x40];
				3852	};
				3853
				3854	struct mlx5_ifc_query_xrc_srq_in_bits {
				3855	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3856	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3857
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3858	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3859	u8 op_mod[0x10];
				3860
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3861	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3862	u8 xrc_srqn[0x18];
				3863
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3864	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3865	};
				3866
				3867	enum {
				3868	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
				3869	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
				3870	};
				3871
				3872	struct mlx5_ifc_query_vport_state_out_bits {
				3873	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3874	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3875
				3876	u8 syndrome[0x20];
				3877
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3878	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3879
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3880	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3881	u8 admin_state[0x4];
				3882	u8 state[0x4];
				3883	};
				3884
				3885	enum {
Eran Ben Elisha	cc9c82a	2018-08-08 16:23:49 -0700	[diff] [blame]	3886	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
				3887	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3888	};
				3889
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3890	struct mlx5_ifc_arm_monitor_counter_in_bits {
				3891	u8 opcode[0x10];
				3892	u8 uid[0x10];
				3893
				3894	u8 reserved_at_20[0x10];
				3895	u8 op_mod[0x10];
				3896
				3897	u8 reserved_at_40[0x20];
				3898
				3899	u8 reserved_at_60[0x20];
				3900	};
				3901
				3902	struct mlx5_ifc_arm_monitor_counter_out_bits {
				3903	u8 status[0x8];
				3904	u8 reserved_at_8[0x18];
				3905
				3906	u8 syndrome[0x20];
				3907
				3908	u8 reserved_at_40[0x40];
				3909	};
				3910
				3911	enum {
				3912	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
				3913	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
				3914	};
				3915
				3916	enum mlx5_monitor_counter_ppcnt {
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	3917	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
				3918	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
				3919	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
				3920	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
				3921	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
				3922	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3923	};
				3924
				3925	enum {
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	3926	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3927	};
				3928
				3929	struct mlx5_ifc_monitor_counter_output_bits {
				3930	u8 reserved_at_0[0x4];
				3931	u8 type[0x4];
				3932	u8 reserved_at_8[0x8];
				3933	u8 counter[0x10];
				3934
				3935	u8 counter_group_id[0x20];
				3936	};
				3937
				3938	#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
				3939	#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
				3940	#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
				3941	MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
				3942
				3943	struct mlx5_ifc_set_monitor_counter_in_bits {
				3944	u8 opcode[0x10];
				3945	u8 uid[0x10];
				3946
				3947	u8 reserved_at_20[0x10];
				3948	u8 op_mod[0x10];
				3949
				3950	u8 reserved_at_40[0x10];
				3951	u8 num_of_counters[0x10];
				3952
				3953	u8 reserved_at_60[0x20];
				3954
				3955	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
				3956	};
				3957
				3958	struct mlx5_ifc_set_monitor_counter_out_bits {
				3959	u8 status[0x8];
				3960	u8 reserved_at_8[0x18];
				3961
				3962	u8 syndrome[0x20];
				3963
				3964	u8 reserved_at_40[0x40];
				3965	};
				3966
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3967	struct mlx5_ifc_query_vport_state_in_bits {
				3968	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3969	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3970
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3971	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3972	u8 op_mod[0x10];
				3973
				3974	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3975	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3976	u8 vport_number[0x10];
				3977
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3978	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3979	};
				3980
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	3981	struct mlx5_ifc_query_vnic_env_out_bits {
				3982	u8 status[0x8];
				3983	u8 reserved_at_8[0x18];
				3984
				3985	u8 syndrome[0x20];
				3986
				3987	u8 reserved_at_40[0x40];
				3988
				3989	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
				3990	};
				3991
				3992	enum {
				3993	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
				3994	};
				3995
				3996	struct mlx5_ifc_query_vnic_env_in_bits {
				3997	u8 opcode[0x10];
				3998	u8 reserved_at_10[0x10];
				3999
				4000	u8 reserved_at_20[0x10];
				4001	u8 op_mod[0x10];
				4002
				4003	u8 other_vport[0x1];
				4004	u8 reserved_at_41[0xf];
				4005	u8 vport_number[0x10];
				4006
				4007	u8 reserved_at_60[0x20];
				4008	};
				4009
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4010	struct mlx5_ifc_query_vport_counter_out_bits {
				4011	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4012	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4013
				4014	u8 syndrome[0x20];
				4015
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4016	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4017
				4018	struct mlx5_ifc_traffic_counter_bits received_errors;
				4019
				4020	struct mlx5_ifc_traffic_counter_bits transmit_errors;
				4021
				4022	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
				4023
				4024	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
				4025
				4026	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
				4027
				4028	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
				4029
				4030	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
				4031
				4032	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
				4033
				4034	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
				4035
				4036	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
				4037
				4038	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
				4039
				4040	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
				4041
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4042	u8 reserved_at_680[0xa00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4043	};
				4044
				4045	enum {
				4046	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
				4047	};
				4048
				4049	struct mlx5_ifc_query_vport_counter_in_bits {
				4050	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4051	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4052
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4053	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4054	u8 op_mod[0x10];
				4055
				4056	u8 other_vport[0x1];
Meny Yossefi	b54ba27	2016-02-18 18:14:59 +0200	[diff] [blame]	4057	u8 reserved_at_41[0xb];
				4058	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4059	u8 vport_number[0x10];
				4060
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4061	u8 reserved_at_60[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4062
				4063	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4064	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4065
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4066	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4067	};
				4068
				4069	struct mlx5_ifc_query_tis_out_bits {
				4070	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4071	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4072
				4073	u8 syndrome[0x20];
				4074
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4075	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4076
				4077	struct mlx5_ifc_tisc_bits tis_context;
				4078	};
				4079
				4080	struct mlx5_ifc_query_tis_in_bits {
				4081	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4082	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4083
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4084	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4085	u8 op_mod[0x10];
				4086
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4087	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4088	u8 tisn[0x18];
				4089
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4090	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4091	};
				4092
				4093	struct mlx5_ifc_query_tir_out_bits {
				4094	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4095	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4096
				4097	u8 syndrome[0x20];
				4098
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4099	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4100
				4101	struct mlx5_ifc_tirc_bits tir_context;
				4102	};
				4103
				4104	struct mlx5_ifc_query_tir_in_bits {
				4105	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4106	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4107
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4108	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4109	u8 op_mod[0x10];
				4110
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4111	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4112	u8 tirn[0x18];
				4113
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4114	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4115	};
				4116
				4117	struct mlx5_ifc_query_srq_out_bits {
				4118	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4119	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4120
				4121	u8 syndrome[0x20];
				4122
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4123	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4124
				4125	struct mlx5_ifc_srqc_bits srq_context_entry;
				4126
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4127	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4128
				4129	u8 pas[0][0x40];
				4130	};
				4131
				4132	struct mlx5_ifc_query_srq_in_bits {
				4133	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4134	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4135
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4136	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4137	u8 op_mod[0x10];
				4138
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4139	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4140	u8 srqn[0x18];
				4141
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4142	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4143	};
				4144
				4145	struct mlx5_ifc_query_sq_out_bits {
				4146	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4147	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4148
				4149	u8 syndrome[0x20];
				4150
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4151	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4152
				4153	struct mlx5_ifc_sqc_bits sq_context;
				4154	};
				4155
				4156	struct mlx5_ifc_query_sq_in_bits {
				4157	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4158	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4159
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4160	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4161	u8 op_mod[0x10];
				4162
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4163	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4164	u8 sqn[0x18];
				4165
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4166	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4167	};
				4168
				4169	struct mlx5_ifc_query_special_contexts_out_bits {
				4170	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4171	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4172
				4173	u8 syndrome[0x20];
				4174
Saeed Mahameed	ec22eb5	2016-07-16 06:28:36 +0300	[diff] [blame]	4175	u8 dump_fill_mkey[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4176
				4177	u8 resd_lkey[0x20];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	4178
				4179	u8 null_mkey[0x20];
				4180
				4181	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4182	};
				4183
				4184	struct mlx5_ifc_query_special_contexts_in_bits {
				4185	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4186	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4187
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4188	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4189	u8 op_mod[0x10];
				4190
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4191	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4192	};
				4193
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	4194	struct mlx5_ifc_query_scheduling_element_out_bits {
				4195	u8 opcode[0x10];
				4196	u8 reserved_at_10[0x10];
				4197
				4198	u8 reserved_at_20[0x10];
				4199	u8 op_mod[0x10];
				4200
				4201	u8 reserved_at_40[0xc0];
				4202
				4203	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				4204
				4205	u8 reserved_at_300[0x100];
				4206	};
				4207
				4208	enum {
				4209	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
				4210	};
				4211
				4212	struct mlx5_ifc_query_scheduling_element_in_bits {
				4213	u8 opcode[0x10];
				4214	u8 reserved_at_10[0x10];
				4215
				4216	u8 reserved_at_20[0x10];
				4217	u8 op_mod[0x10];
				4218
				4219	u8 scheduling_hierarchy[0x8];
				4220	u8 reserved_at_48[0x18];
				4221
				4222	u8 scheduling_element_id[0x20];
				4223
				4224	u8 reserved_at_80[0x180];
				4225	};
				4226
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4227	struct mlx5_ifc_query_rqt_out_bits {
				4228	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4229	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4230
				4231	u8 syndrome[0x20];
				4232
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4233	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4234
				4235	struct mlx5_ifc_rqtc_bits rqt_context;
				4236	};
				4237
				4238	struct mlx5_ifc_query_rqt_in_bits {
				4239	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4240	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4241
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4242	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4243	u8 op_mod[0x10];
				4244
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4245	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4246	u8 rqtn[0x18];
				4247
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4248	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4249	};
				4250
				4251	struct mlx5_ifc_query_rq_out_bits {
				4252	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4253	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4254
				4255	u8 syndrome[0x20];
				4256
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4257	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4258
				4259	struct mlx5_ifc_rqc_bits rq_context;
				4260	};
				4261
				4262	struct mlx5_ifc_query_rq_in_bits {
				4263	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4264	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4265
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4266	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4267	u8 op_mod[0x10];
				4268
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4269	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4270	u8 rqn[0x18];
				4271
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4272	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4273	};
				4274
				4275	struct mlx5_ifc_query_roce_address_out_bits {
				4276	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4277	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4278
				4279	u8 syndrome[0x20];
				4280
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4281	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4282
				4283	struct mlx5_ifc_roce_addr_layout_bits roce_address;
				4284	};
				4285
				4286	struct mlx5_ifc_query_roce_address_in_bits {
				4287	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4288	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4289
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4290	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4291	u8 op_mod[0x10];
				4292
				4293	u8 roce_address_index[0x10];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	4294	u8 reserved_at_50[0xc];
				4295	u8 vhca_port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4296
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4297	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4298	};
				4299
				4300	struct mlx5_ifc_query_rmp_out_bits {
				4301	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4302	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4303
				4304	u8 syndrome[0x20];
				4305
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4306	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4307
				4308	struct mlx5_ifc_rmpc_bits rmp_context;
				4309	};
				4310
				4311	struct mlx5_ifc_query_rmp_in_bits {
				4312	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4313	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4314
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4315	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4316	u8 op_mod[0x10];
				4317
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4318	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4319	u8 rmpn[0x18];
				4320
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4321	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4322	};
				4323
				4324	struct mlx5_ifc_query_qp_out_bits {
				4325	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4326	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4327
				4328	u8 syndrome[0x20];
				4329
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4330	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4331
				4332	u8 opt_param_mask[0x20];
				4333
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4334	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4335
				4336	struct mlx5_ifc_qpc_bits qpc;
				4337
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4338	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4339
				4340	u8 pas[0][0x40];
				4341	};
				4342
				4343	struct mlx5_ifc_query_qp_in_bits {
				4344	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4345	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4346
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4347	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4348	u8 op_mod[0x10];
				4349
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4350	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4351	u8 qpn[0x18];
				4352
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4353	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4354	};
				4355
				4356	struct mlx5_ifc_query_q_counter_out_bits {
				4357	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4358	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4359
				4360	u8 syndrome[0x20];
				4361
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4362	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4363
				4364	u8 rx_write_requests[0x20];
				4365
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4366	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4367
				4368	u8 rx_read_requests[0x20];
				4369
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4370	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4371
				4372	u8 rx_atomic_requests[0x20];
				4373
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4374	u8 reserved_at_120[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4375
				4376	u8 rx_dct_connect[0x20];
				4377
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4378	u8 reserved_at_160[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4379
				4380	u8 out_of_buffer[0x20];
				4381
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4382	u8 reserved_at_1a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4383
				4384	u8 out_of_sequence[0x20];
				4385
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	4386	u8 reserved_at_1e0[0x20];
				4387
				4388	u8 duplicate_request[0x20];
				4389
				4390	u8 reserved_at_220[0x20];
				4391
				4392	u8 rnr_nak_retry_err[0x20];
				4393
				4394	u8 reserved_at_260[0x20];
				4395
				4396	u8 packet_seq_err[0x20];
				4397
				4398	u8 reserved_at_2a0[0x20];
				4399
				4400	u8 implied_nak_seq_err[0x20];
				4401
				4402	u8 reserved_at_2e0[0x20];
				4403
				4404	u8 local_ack_timeout_err[0x20];
				4405
Parav Pandit	58dcb60	2017-06-19 07:19:37 +0300	[diff] [blame]	4406	u8 reserved_at_320[0xa0];
				4407
				4408	u8 resp_local_length_error[0x20];
				4409
				4410	u8 req_local_length_error[0x20];
				4411
				4412	u8 resp_local_qp_error[0x20];
				4413
				4414	u8 local_operation_error[0x20];
				4415
				4416	u8 resp_local_protection[0x20];
				4417
				4418	u8 req_local_protection[0x20];
				4419
				4420	u8 resp_cqe_error[0x20];
				4421
				4422	u8 req_cqe_error[0x20];
				4423
				4424	u8 req_mw_binding[0x20];
				4425
				4426	u8 req_bad_response[0x20];
				4427
				4428	u8 req_remote_invalid_request[0x20];
				4429
				4430	u8 resp_remote_invalid_request[0x20];
				4431
				4432	u8 req_remote_access_errors[0x20];
				4433
				4434	u8 resp_remote_access_errors[0x20];
				4435
				4436	u8 req_remote_operation_errors[0x20];
				4437
				4438	u8 req_transport_retries_exceeded[0x20];
				4439
				4440	u8 cq_overflow[0x20];
				4441
				4442	u8 resp_cqe_flush_error[0x20];
				4443
				4444	u8 req_cqe_flush_error[0x20];
				4445
				4446	u8 reserved_at_620[0x1e0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4447	};
				4448
				4449	struct mlx5_ifc_query_q_counter_in_bits {
				4450	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4451	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4452
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4453	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4454	u8 op_mod[0x10];
				4455
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4456	u8 reserved_at_40[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4457
				4458	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4459	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4460
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4461	u8 reserved_at_e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4462	u8 counter_set_id[0x8];
				4463	};
				4464
				4465	struct mlx5_ifc_query_pages_out_bits {
				4466	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4467	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4468
				4469	u8 syndrome[0x20];
				4470
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	4471	u8 embedded_cpu_function[0x1];
				4472	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4473	u8 function_id[0x10];
				4474
				4475	u8 num_pages[0x20];
				4476	};
				4477
				4478	enum {
				4479	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
				4480	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
				4481	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
				4482	};
				4483
				4484	struct mlx5_ifc_query_pages_in_bits {
				4485	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4486	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4487
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4488	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4489	u8 op_mod[0x10];
				4490
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	4491	u8 embedded_cpu_function[0x1];
				4492	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4493	u8 function_id[0x10];
				4494
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4495	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4496	};
				4497
				4498	struct mlx5_ifc_query_nic_vport_context_out_bits {
				4499	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4500	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4501
				4502	u8 syndrome[0x20];
				4503
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4504	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4505
				4506	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
				4507	};
				4508
				4509	struct mlx5_ifc_query_nic_vport_context_in_bits {
				4510	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4511	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4512
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4513	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4514	u8 op_mod[0x10];
				4515
				4516	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4517	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4518	u8 vport_number[0x10];
				4519
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4520	u8 reserved_at_60[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4521	u8 allowed_list_type[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4522	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4523	};
				4524
				4525	struct mlx5_ifc_query_mkey_out_bits {
				4526	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4527	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4528
				4529	u8 syndrome[0x20];
				4530
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4531	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4532
				4533	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
				4534
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4535	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4536
				4537	u8 bsf0_klm0_pas_mtt0_1[16][0x8];
				4538
				4539	u8 bsf1_klm1_pas_mtt2_3[16][0x8];
				4540	};
				4541
				4542	struct mlx5_ifc_query_mkey_in_bits {
				4543	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4544	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4545
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4546	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4547	u8 op_mod[0x10];
				4548
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4549	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4550	u8 mkey_index[0x18];
				4551
				4552	u8 pg_access[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4553	u8 reserved_at_61[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4554	};
				4555
				4556	struct mlx5_ifc_query_mad_demux_out_bits {
				4557	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4558	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4559
				4560	u8 syndrome[0x20];
				4561
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4562	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4563
				4564	u8 mad_dumux_parameters_block[0x20];
				4565	};
				4566
				4567	struct mlx5_ifc_query_mad_demux_in_bits {
				4568	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4569	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4570
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4571	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4572	u8 op_mod[0x10];
				4573
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4574	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4575	};
				4576
				4577	struct mlx5_ifc_query_l2_table_entry_out_bits {
				4578	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4579	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4580
				4581	u8 syndrome[0x20];
				4582
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4583	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4584
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4585	u8 reserved_at_e0[0x13];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4586	u8 vlan_valid[0x1];
				4587	u8 vlan[0xc];
				4588
				4589	struct mlx5_ifc_mac_address_layout_bits mac_address;
				4590
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4591	u8 reserved_at_140[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4592	};
				4593
				4594	struct mlx5_ifc_query_l2_table_entry_in_bits {
				4595	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4596	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4598	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4599	u8 op_mod[0x10];
				4600
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4601	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4602
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4603	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4604	u8 table_index[0x18];
				4605
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4606	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4607	};
				4608
				4609	struct mlx5_ifc_query_issi_out_bits {
				4610	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4611	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4612
				4613	u8 syndrome[0x20];
				4614
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4615	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4616	u8 current_issi[0x10];
				4617
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4618	u8 reserved_at_60[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4619
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4620	u8 reserved_at_100[76][0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4621	u8 supported_issi_dw0[0x20];
				4622	};
				4623
				4624	struct mlx5_ifc_query_issi_in_bits {
				4625	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4626	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4627
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4628	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4629	u8 op_mod[0x10];
				4630
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4631	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4632	};
				4633
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	4634	struct mlx5_ifc_set_driver_version_out_bits {
				4635	u8 status[0x8];
				4636	u8 reserved_0[0x18];
				4637
				4638	u8 syndrome[0x20];
				4639	u8 reserved_1[0x40];
				4640	};
				4641
				4642	struct mlx5_ifc_set_driver_version_in_bits {
				4643	u8 opcode[0x10];
				4644	u8 reserved_0[0x10];
				4645
				4646	u8 reserved_1[0x10];
				4647	u8 op_mod[0x10];
				4648
				4649	u8 reserved_2[0x40];
				4650	u8 driver_version[64][0x8];
				4651	};
				4652
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4653	struct mlx5_ifc_query_hca_vport_pkey_out_bits {
				4654	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4655	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4656
				4657	u8 syndrome[0x20];
				4658
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4659	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4660
				4661	struct mlx5_ifc_pkey_bits pkey[0];
				4662	};
				4663
				4664	struct mlx5_ifc_query_hca_vport_pkey_in_bits {
				4665	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4666	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4667
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4668	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4669	u8 op_mod[0x10];
				4670
				4671	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4672	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4673	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4674	u8 vport_number[0x10];
				4675
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4676	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4677	u8 pkey_index[0x10];
				4678	};
				4679
Eli Cohen	eff901d	2016-03-11 22:58:42 +0200	[diff] [blame]	4680	enum {
				4681	MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
				4682	MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
				4683	MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
				4684	};
				4685
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4686	struct mlx5_ifc_query_hca_vport_gid_out_bits {
				4687	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4688	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4689
				4690	u8 syndrome[0x20];
				4691
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4692	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4693
				4694	u8 gids_num[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4695	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4696
				4697	struct mlx5_ifc_array128_auto_bits gid[0];
				4698	};
				4699
				4700	struct mlx5_ifc_query_hca_vport_gid_in_bits {
				4701	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4702	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4703
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4704	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4705	u8 op_mod[0x10];
				4706
				4707	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4708	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4709	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4710	u8 vport_number[0x10];
				4711
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4712	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4713	u8 gid_index[0x10];
				4714	};
				4715
				4716	struct mlx5_ifc_query_hca_vport_context_out_bits {
				4717	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4718	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4719
				4720	u8 syndrome[0x20];
				4721
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4722	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4723
				4724	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
				4725	};
				4726
				4727	struct mlx5_ifc_query_hca_vport_context_in_bits {
				4728	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4729	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4731	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4732	u8 op_mod[0x10];
				4733
				4734	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4735	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4736	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4737	u8 vport_number[0x10];
				4738
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4739	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4740	};
				4741
				4742	struct mlx5_ifc_query_hca_cap_out_bits {
				4743	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4744	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4745
				4746	u8 syndrome[0x20];
				4747
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4748	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4749
				4750	union mlx5_ifc_hca_cap_union_bits capability;
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4751	};
				4752
				4753	struct mlx5_ifc_query_hca_cap_in_bits {
				4754	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4755	u8 reserved_at_10[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4756
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4757	u8 reserved_at_20[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4758	u8 op_mod[0x10];
				4759
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4760	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4761	};
				4762
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4763	struct mlx5_ifc_query_flow_table_out_bits {
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4764	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4765	u8 reserved_at_8[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4766
				4767	u8 syndrome[0x20];
				4768
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4769	u8 reserved_at_40[0x80];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4770
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4771	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4772	u8 level[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4773	u8 reserved_at_d0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4774	u8 log_size[0x8];
				4775
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4776	u8 reserved_at_e0[0x120];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4777	};
				4778
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4779	struct mlx5_ifc_query_flow_table_in_bits {
				4780	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4781	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4782
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4783	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4784	u8 op_mod[0x10];
				4785
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4786	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4787
				4788	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4789	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4790
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4791	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4792	u8 table_id[0x18];
				4793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4794	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4795	};
				4796
				4797	struct mlx5_ifc_query_fte_out_bits {
				4798	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4799	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4800
				4801	u8 syndrome[0x20];
				4802
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4803	u8 reserved_at_40[0x1c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4804
				4805	struct mlx5_ifc_flow_context_bits flow_context;
				4806	};
				4807
				4808	struct mlx5_ifc_query_fte_in_bits {
				4809	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4810	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4811
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4812	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4813	u8 op_mod[0x10];
				4814
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4815	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4816
				4817	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4818	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4819
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4820	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4821	u8 table_id[0x18];
				4822
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4823	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4824
				4825	u8 flow_index[0x20];
				4826
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4827	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4828	};
				4829
				4830	enum {
				4831	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
				4832	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
				4833	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	4834	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4835	};
				4836
				4837	struct mlx5_ifc_query_flow_group_out_bits {
				4838	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4839	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4840
				4841	u8 syndrome[0x20];
				4842
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4843	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4844
				4845	u8 start_flow_index[0x20];
				4846
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4847	u8 reserved_at_100[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4848
				4849	u8 end_flow_index[0x20];
				4850
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4851	u8 reserved_at_140[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4852
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4853	u8 reserved_at_1e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4854	u8 match_criteria_enable[0x8];
				4855
				4856	struct mlx5_ifc_fte_match_param_bits match_criteria;
				4857
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4858	u8 reserved_at_1200[0xe00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4859	};
				4860
				4861	struct mlx5_ifc_query_flow_group_in_bits {
				4862	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4863	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4864
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4865	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4866	u8 op_mod[0x10];
				4867
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4868	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4869
				4870	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4871	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4872
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4873	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4874	u8 table_id[0x18];
				4875
				4876	u8 group_id[0x20];
				4877
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4878	u8 reserved_at_e0[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4879	};
				4880
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	4881	struct mlx5_ifc_query_flow_counter_out_bits {
				4882	u8 status[0x8];
				4883	u8 reserved_at_8[0x18];
				4884
				4885	u8 syndrome[0x20];
				4886
				4887	u8 reserved_at_40[0x40];
				4888
				4889	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
				4890	};
				4891
				4892	struct mlx5_ifc_query_flow_counter_in_bits {
				4893	u8 opcode[0x10];
				4894	u8 reserved_at_10[0x10];
				4895
				4896	u8 reserved_at_20[0x10];
				4897	u8 op_mod[0x10];
				4898
				4899	u8 reserved_at_40[0x80];
				4900
				4901	u8 clear[0x1];
				4902	u8 reserved_at_c1[0xf];
				4903	u8 num_of_counters[0x10];
				4904
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	4905	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	4906	};
				4907
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4908	struct mlx5_ifc_query_esw_vport_context_out_bits {
				4909	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4910	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4911
				4912	u8 syndrome[0x20];
				4913
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4914	u8 reserved_at_40[0x40];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4915
				4916	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
				4917	};
				4918
				4919	struct mlx5_ifc_query_esw_vport_context_in_bits {
				4920	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4921	u8 reserved_at_10[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4922
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4923	u8 reserved_at_20[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4924	u8 op_mod[0x10];
				4925
				4926	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4927	u8 reserved_at_41[0xf];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4928	u8 vport_number[0x10];
				4929
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4930	u8 reserved_at_60[0x20];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4931	};
				4932
				4933	struct mlx5_ifc_modify_esw_vport_context_out_bits {
				4934	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4935	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4936
				4937	u8 syndrome[0x20];
				4938
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4939	u8 reserved_at_40[0x40];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4940	};
				4941
				4942	struct mlx5_ifc_esw_vport_context_fields_select_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4943	u8 reserved_at_0[0x1c];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4944	u8 vport_cvlan_insert[0x1];
				4945	u8 vport_svlan_insert[0x1];
				4946	u8 vport_cvlan_strip[0x1];
				4947	u8 vport_svlan_strip[0x1];
				4948	};
				4949
				4950	struct mlx5_ifc_modify_esw_vport_context_in_bits {
				4951	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4952	u8 reserved_at_10[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4953
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4954	u8 reserved_at_20[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4955	u8 op_mod[0x10];
				4956
				4957	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4958	u8 reserved_at_41[0xf];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4959	u8 vport_number[0x10];
				4960
				4961	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
				4962
				4963	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
				4964	};
				4965
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4966	struct mlx5_ifc_query_eq_out_bits {
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4967	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4968	u8 reserved_at_8[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4969
				4970	u8 syndrome[0x20];
				4971
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4972	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4973
				4974	struct mlx5_ifc_eqc_bits eq_context_entry;
				4975
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4976	u8 reserved_at_280[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4977
				4978	u8 event_bitmask[0x40];
				4979
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4980	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4981
				4982	u8 pas[0][0x40];
				4983	};
				4984
				4985	struct mlx5_ifc_query_eq_in_bits {
				4986	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4987	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4988
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4989	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4990	u8 op_mod[0x10];
				4991
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4992	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4993	u8 eq_number[0x8];
				4994
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4995	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4996	};
				4997
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4998	struct mlx5_ifc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4999	u8 reserved_at_0[0x5];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5000	u8 reformat_type[0x3];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5001	u8 reserved_at_8[0xe];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5002	u8 reformat_data_size[0xa];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5003
				5004	u8 reserved_at_20[0x10];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5005	u8 reformat_data[2][0x8];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5006
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5007	u8 more_reformat_data[0][0x8];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5008	};
				5009
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5010	struct mlx5_ifc_query_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5011	u8 status[0x8];
				5012	u8 reserved_at_8[0x18];
				5013
				5014	u8 syndrome[0x20];
				5015
				5016	u8 reserved_at_40[0xa0];
				5017
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5018	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5019	};
				5020
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5021	struct mlx5_ifc_query_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5022	u8 opcode[0x10];
				5023	u8 reserved_at_10[0x10];
				5024
				5025	u8 reserved_at_20[0x10];
				5026	u8 op_mod[0x10];
				5027
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5028	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5029
				5030	u8 reserved_at_60[0xa0];
				5031	};
				5032
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5033	struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5034	u8 status[0x8];
				5035	u8 reserved_at_8[0x18];
				5036
				5037	u8 syndrome[0x20];
				5038
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5039	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5040
				5041	u8 reserved_at_60[0x20];
				5042	};
				5043
Mark Bloch	e0e7a38	2018-08-28 14:18:45 +0300	[diff] [blame]	5044	enum {
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5045	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
				5046	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	5047	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
				5048	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
				5049	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
Mark Bloch	e0e7a38	2018-08-28 14:18:45 +0300	[diff] [blame]	5050	};
				5051
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5052	struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5053	u8 opcode[0x10];
				5054	u8 reserved_at_10[0x10];
				5055
				5056	u8 reserved_at_20[0x10];
				5057	u8 op_mod[0x10];
				5058
				5059	u8 reserved_at_40[0xa0];
				5060
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5061	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5062	};
				5063
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5064	struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5065	u8 status[0x8];
				5066	u8 reserved_at_8[0x18];
				5067
				5068	u8 syndrome[0x20];
				5069
				5070	u8 reserved_at_40[0x40];
				5071	};
				5072
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5073	struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5074	u8 opcode[0x10];
				5075	u8 reserved_at_10[0x10];
				5076
				5077	u8 reserved_20[0x10];
				5078	u8 op_mod[0x10];
				5079
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5080	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5081
				5082	u8 reserved_60[0x20];
				5083	};
				5084
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	5085	struct mlx5_ifc_set_action_in_bits {
				5086	u8 action_type[0x4];
				5087	u8 field[0xc];
				5088	u8 reserved_at_10[0x3];
				5089	u8 offset[0x5];
				5090	u8 reserved_at_18[0x3];
				5091	u8 length[0x5];
				5092
				5093	u8 data[0x20];
				5094	};
				5095
				5096	struct mlx5_ifc_add_action_in_bits {
				5097	u8 action_type[0x4];
				5098	u8 field[0xc];
				5099	u8 reserved_at_10[0x10];
				5100
				5101	u8 data[0x20];
				5102	};
				5103
				5104	union mlx5_ifc_set_action_in_add_action_in_auto_bits {
				5105	struct mlx5_ifc_set_action_in_bits set_action_in;
				5106	struct mlx5_ifc_add_action_in_bits add_action_in;
				5107	u8 reserved_at_0[0x40];
				5108	};
				5109
				5110	enum {
				5111	MLX5_ACTION_TYPE_SET = 0x1,
				5112	MLX5_ACTION_TYPE_ADD = 0x2,
				5113	};
				5114
				5115	enum {
				5116	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
				5117	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
				5118	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
				5119	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
				5120	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
				5121	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
				5122	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
				5123	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
				5124	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
				5125	MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
				5126	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
				5127	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
				5128	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
				5129	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
				5130	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
				5131	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
				5132	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
				5133	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
				5134	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
				5135	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
				5136	MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
				5137	MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
Or Gerlitz	0c0316f	2017-06-13 11:09:57 +0300	[diff] [blame]	5138	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	5139	};
				5140
				5141	struct mlx5_ifc_alloc_modify_header_context_out_bits {
				5142	u8 status[0x8];
				5143	u8 reserved_at_8[0x18];
				5144
				5145	u8 syndrome[0x20];
				5146
				5147	u8 modify_header_id[0x20];
				5148
				5149	u8 reserved_at_60[0x20];
				5150	};
				5151
				5152	struct mlx5_ifc_alloc_modify_header_context_in_bits {
				5153	u8 opcode[0x10];
				5154	u8 reserved_at_10[0x10];
				5155
				5156	u8 reserved_at_20[0x10];
				5157	u8 op_mod[0x10];
				5158
				5159	u8 reserved_at_40[0x20];
				5160
				5161	u8 table_type[0x8];
				5162	u8 reserved_at_68[0x10];
				5163	u8 num_of_actions[0x8];
				5164
				5165	union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
				5166	};
				5167
				5168	struct mlx5_ifc_dealloc_modify_header_context_out_bits {
				5169	u8 status[0x8];
				5170	u8 reserved_at_8[0x18];
				5171
				5172	u8 syndrome[0x20];
				5173
				5174	u8 reserved_at_40[0x40];
				5175	};
				5176
				5177	struct mlx5_ifc_dealloc_modify_header_context_in_bits {
				5178	u8 opcode[0x10];
				5179	u8 reserved_at_10[0x10];
				5180
				5181	u8 reserved_at_20[0x10];
				5182	u8 op_mod[0x10];
				5183
				5184	u8 modify_header_id[0x20];
				5185
				5186	u8 reserved_at_60[0x20];
				5187	};
				5188
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5189	struct mlx5_ifc_query_dct_out_bits {
				5190	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5191	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5192
				5193	u8 syndrome[0x20];
				5194
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5195	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5196
				5197	struct mlx5_ifc_dctc_bits dct_context_entry;
				5198
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5199	u8 reserved_at_280[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5200	};
				5201
				5202	struct mlx5_ifc_query_dct_in_bits {
				5203	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5204	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5205
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5206	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5207	u8 op_mod[0x10];
				5208
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5209	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5210	u8 dctn[0x18];
				5211
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5212	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5213	};
				5214
				5215	struct mlx5_ifc_query_cq_out_bits {
				5216	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5217	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5218
				5219	u8 syndrome[0x20];
				5220
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5221	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5222
				5223	struct mlx5_ifc_cqc_bits cq_context;
				5224
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5225	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5226
				5227	u8 pas[0][0x40];
				5228	};
				5229
				5230	struct mlx5_ifc_query_cq_in_bits {
				5231	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5232	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5233
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5234	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5235	u8 op_mod[0x10];
				5236
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5237	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5238	u8 cqn[0x18];
				5239
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5240	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5241	};
				5242
				5243	struct mlx5_ifc_query_cong_status_out_bits {
				5244	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5245	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5246
				5247	u8 syndrome[0x20];
				5248
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5249	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5250
				5251	u8 enable[0x1];
				5252	u8 tag_enable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5253	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5254	};
				5255
				5256	struct mlx5_ifc_query_cong_status_in_bits {
				5257	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5258	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5259
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5260	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5261	u8 op_mod[0x10];
				5262
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5263	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5264	u8 priority[0x4];
				5265	u8 cong_protocol[0x4];
				5266
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5267	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5268	};
				5269
				5270	struct mlx5_ifc_query_cong_statistics_out_bits {
				5271	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5272	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5273
				5274	u8 syndrome[0x20];
				5275
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5276	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5277
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5278	u8 rp_cur_flows[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5279
				5280	u8 sum_flows[0x20];
				5281
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5282	u8 rp_cnp_ignored_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5283
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5284	u8 rp_cnp_ignored_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5285
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5286	u8 rp_cnp_handled_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5287
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5288	u8 rp_cnp_handled_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5289
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5290	u8 reserved_at_140[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5291
				5292	u8 time_stamp_high[0x20];
				5293
				5294	u8 time_stamp_low[0x20];
				5295
				5296	u8 accumulators_period[0x20];
				5297
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5298	u8 np_ecn_marked_roce_packets_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5299
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5300	u8 np_ecn_marked_roce_packets_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5301
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5302	u8 np_cnp_sent_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5303
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5304	u8 np_cnp_sent_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5305
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5306	u8 reserved_at_320[0x560];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5307	};
				5308
				5309	struct mlx5_ifc_query_cong_statistics_in_bits {
				5310	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5311	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5312
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5313	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5314	u8 op_mod[0x10];
				5315
				5316	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5317	u8 reserved_at_41[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5318
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5319	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5320	};
				5321
				5322	struct mlx5_ifc_query_cong_params_out_bits {
				5323	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5324	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5325
				5326	u8 syndrome[0x20];
				5327
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5328	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5329
				5330	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
				5331	};
				5332
				5333	struct mlx5_ifc_query_cong_params_in_bits {
				5334	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5335	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5336
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5337	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5338	u8 op_mod[0x10];
				5339
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5340	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5341	u8 cong_protocol[0x4];
				5342
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5343	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5344	};
				5345
				5346	struct mlx5_ifc_query_adapter_out_bits {
				5347	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5348	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5349
				5350	u8 syndrome[0x20];
				5351
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5352	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5353
				5354	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
				5355	};
				5356
				5357	struct mlx5_ifc_query_adapter_in_bits {
				5358	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5359	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5360
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5361	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5362	u8 op_mod[0x10];
				5363
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5364	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5365	};
				5366
				5367	struct mlx5_ifc_qp_2rst_out_bits {
				5368	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5369	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5370
				5371	u8 syndrome[0x20];
				5372
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5373	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5374	};
				5375
				5376	struct mlx5_ifc_qp_2rst_in_bits {
				5377	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5378	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5379
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5380	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5381	u8 op_mod[0x10];
				5382
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5383	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5384	u8 qpn[0x18];
				5385
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5386	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5387	};
				5388
				5389	struct mlx5_ifc_qp_2err_out_bits {
				5390	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5391	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5392
				5393	u8 syndrome[0x20];
				5394
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5395	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5396	};
				5397
				5398	struct mlx5_ifc_qp_2err_in_bits {
				5399	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5400	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5401
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5402	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5403	u8 op_mod[0x10];
				5404
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5405	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5406	u8 qpn[0x18];
				5407
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5408	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5409	};
				5410
				5411	struct mlx5_ifc_page_fault_resume_out_bits {
				5412	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5413	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5414
				5415	u8 syndrome[0x20];
				5416
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5417	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5418	};
				5419
				5420	struct mlx5_ifc_page_fault_resume_in_bits {
				5421	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5422	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5423
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5424	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5425	u8 op_mod[0x10];
				5426
				5427	u8 error[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5428	u8 reserved_at_41[0x4];
Artemy Kovalyov	223cdc7	2017-01-02 11:37:45 +0200	[diff] [blame]	5429	u8 page_fault_type[0x3];
				5430	u8 wq_number[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5431
Artemy Kovalyov	223cdc7	2017-01-02 11:37:45 +0200	[diff] [blame]	5432	u8 reserved_at_60[0x8];
				5433	u8 token[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5434	};
				5435
				5436	struct mlx5_ifc_nop_out_bits {
				5437	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5438	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5439
				5440	u8 syndrome[0x20];
				5441
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5442	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5443	};
				5444
				5445	struct mlx5_ifc_nop_in_bits {
				5446	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5447	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5448
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5449	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5450	u8 op_mod[0x10];
				5451
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5452	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5453	};
				5454
				5455	struct mlx5_ifc_modify_vport_state_out_bits {
				5456	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5457	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5458
				5459	u8 syndrome[0x20];
				5460
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5461	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5462	};
				5463
				5464	struct mlx5_ifc_modify_vport_state_in_bits {
				5465	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5466	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5467
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5468	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5469	u8 op_mod[0x10];
				5470
				5471	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5472	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5473	u8 vport_number[0x10];
				5474
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5475	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5476	u8 admin_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5477	u8 reserved_at_7c[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5478	};
				5479
				5480	struct mlx5_ifc_modify_tis_out_bits {
				5481	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5482	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5483
				5484	u8 syndrome[0x20];
				5485
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5486	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5487	};
				5488
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5489	struct mlx5_ifc_modify_tis_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5490	u8 reserved_at_0[0x20];
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5491
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	5492	u8 reserved_at_20[0x1d];
				5493	u8 lag_tx_port_affinity[0x1];
				5494	u8 strict_lag_tx_port_affinity[0x1];
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5495	u8 prio[0x1];
				5496	};
				5497
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5498	struct mlx5_ifc_modify_tis_in_bits {
				5499	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5500	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5501
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5502	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5503	u8 op_mod[0x10];
				5504
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5505	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5506	u8 tisn[0x18];
				5507
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5508	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5509
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5510	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5511
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5512	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5513
				5514	struct mlx5_ifc_tisc_bits ctx;
				5515	};
				5516
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5517	struct mlx5_ifc_modify_tir_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5518	u8 reserved_at_0[0x20];
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5519
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5520	u8 reserved_at_20[0x1b];
Tariq Toukan	6618996	2015-11-12 19:35:26 +0200	[diff] [blame]	5521	u8 self_lb_en[0x1];
Tariq Toukan	bdfc028	2016-02-29 21:17:12 +0200	[diff] [blame]	5522	u8 reserved_at_3c[0x1];
				5523	u8 hash[0x1];
				5524	u8 reserved_at_3e[0x1];
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5525	u8 lro[0x1];
				5526	};
				5527
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5528	struct mlx5_ifc_modify_tir_out_bits {
				5529	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5530	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5531
				5532	u8 syndrome[0x20];
				5533
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5534	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5535	};
				5536
				5537	struct mlx5_ifc_modify_tir_in_bits {
				5538	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5539	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5540
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5541	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5542	u8 op_mod[0x10];
				5543
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5544	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5545	u8 tirn[0x18];
				5546
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5547	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5548
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5549	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5550
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5551	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5552
				5553	struct mlx5_ifc_tirc_bits ctx;
				5554	};
				5555
				5556	struct mlx5_ifc_modify_sq_out_bits {
				5557	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5558	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5559
				5560	u8 syndrome[0x20];
				5561
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5562	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5563	};
				5564
				5565	struct mlx5_ifc_modify_sq_in_bits {
				5566	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	5567	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5568
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5569	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5570	u8 op_mod[0x10];
				5571
				5572	u8 sq_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5573	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5574	u8 sqn[0x18];
				5575
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5576	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5577
				5578	u8 modify_bitmask[0x40];
				5579
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5580	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5581
				5582	struct mlx5_ifc_sqc_bits ctx;
				5583	};
				5584
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	5585	struct mlx5_ifc_modify_scheduling_element_out_bits {
				5586	u8 status[0x8];
				5587	u8 reserved_at_8[0x18];
				5588
				5589	u8 syndrome[0x20];
				5590
				5591	u8 reserved_at_40[0x1c0];
				5592	};
				5593
				5594	enum {
				5595	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
				5596	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
				5597	};
				5598
				5599	struct mlx5_ifc_modify_scheduling_element_in_bits {
				5600	u8 opcode[0x10];
				5601	u8 reserved_at_10[0x10];
				5602
				5603	u8 reserved_at_20[0x10];
				5604	u8 op_mod[0x10];
				5605
				5606	u8 scheduling_hierarchy[0x8];
				5607	u8 reserved_at_48[0x18];
				5608
				5609	u8 scheduling_element_id[0x20];
				5610
				5611	u8 reserved_at_80[0x20];
				5612
				5613	u8 modify_bitmask[0x20];
				5614
				5615	u8 reserved_at_c0[0x40];
				5616
				5617	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				5618
				5619	u8 reserved_at_300[0x100];
				5620	};
				5621
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5622	struct mlx5_ifc_modify_rqt_out_bits {
				5623	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5624	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5625
				5626	u8 syndrome[0x20];
				5627
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5628	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5629	};
				5630
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5631	struct mlx5_ifc_rqt_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5632	u8 reserved_at_0[0x20];
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5633
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5634	u8 reserved_at_20[0x1f];
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5635	u8 rqn_list[0x1];
				5636	};
				5637
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5638	struct mlx5_ifc_modify_rqt_in_bits {
				5639	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5640	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5641
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5642	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5643	u8 op_mod[0x10];
				5644
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5645	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5646	u8 rqtn[0x18];
				5647
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5648	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5649
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5650	struct mlx5_ifc_rqt_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5651
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5652	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5653
				5654	struct mlx5_ifc_rqtc_bits ctx;
				5655	};
				5656
				5657	struct mlx5_ifc_modify_rq_out_bits {
				5658	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5659	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5660
				5661	u8 syndrome[0x20];
				5662
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5663	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5664	};
				5665
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	5666	enum {
				5667	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
Guy Ergas	102722f	2017-02-20 16:18:17 +0200	[diff] [blame]	5668	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
Majd Dibbiny	23a6964	2017-01-18 15:25:10 +0200	[diff] [blame]	5669	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	5670	};
				5671
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5672	struct mlx5_ifc_modify_rq_in_bits {
				5673	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	5674	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5675
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5676	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5677	u8 op_mod[0x10];
				5678
				5679	u8 rq_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5680	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5681	u8 rqn[0x18];
				5682
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5683	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5684
				5685	u8 modify_bitmask[0x40];
				5686
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5687	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5688
				5689	struct mlx5_ifc_rqc_bits ctx;
				5690	};
				5691
				5692	struct mlx5_ifc_modify_rmp_out_bits {
				5693	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5694	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5695
				5696	u8 syndrome[0x20];
				5697
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5698	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5699	};
				5700
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5701	struct mlx5_ifc_rmp_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5702	u8 reserved_at_0[0x20];
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5703
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5704	u8 reserved_at_20[0x1f];
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5705	u8 lwm[0x1];
				5706	};
				5707
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5708	struct mlx5_ifc_modify_rmp_in_bits {
				5709	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	5710	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5711
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5712	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5713	u8 op_mod[0x10];
				5714
				5715	u8 rmp_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5716	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5717	u8 rmpn[0x18];
				5718
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5719	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5720
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5721	struct mlx5_ifc_rmp_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5722
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5723	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5724
				5725	struct mlx5_ifc_rmpc_bits ctx;
				5726	};
				5727
				5728	struct mlx5_ifc_modify_nic_vport_context_out_bits {
				5729	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5730	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5731
				5732	u8 syndrome[0x20];
				5733
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5734	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5735	};
				5736
				5737	struct mlx5_ifc_modify_nic_vport_field_select_bits {
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	5738	u8 reserved_at_0[0x12];
				5739	u8 affiliation[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	5740	u8 reserved_at_13[0x1];
Huy Nguyen	bded747	2017-05-30 09:42:53 +0300	[diff] [blame]	5741	u8 disable_uc_local_lb[0x1];
				5742	u8 disable_mc_local_lb[0x1];
Noa Osherovich	23898c7	2016-06-10 00:07:37 +0300	[diff] [blame]	5743	u8 node_guid[0x1];
				5744	u8 port_guid[0x1];
Hadar Hen Zion	9def712	2016-08-03 17:27:30 +0300	[diff] [blame]	5745	u8 min_inline[0x1];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	5746	u8 mtu[0x1];
				5747	u8 change_event[0x1];
				5748	u8 promisc[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5749	u8 permanent_address[0x1];
				5750	u8 addresses_list[0x1];
				5751	u8 roce_en[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5752	u8 reserved_at_1f[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5753	};
				5754
				5755	struct mlx5_ifc_modify_nic_vport_context_in_bits {
				5756	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5757	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5758
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5759	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5760	u8 op_mod[0x10];
				5761
				5762	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5763	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5764	u8 vport_number[0x10];
				5765
				5766	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
				5767
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5768	u8 reserved_at_80[0x780];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5769
				5770	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
				5771	};
				5772
				5773	struct mlx5_ifc_modify_hca_vport_context_out_bits {
				5774	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5775	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5776
				5777	u8 syndrome[0x20];
				5778
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5779	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5780	};
				5781
				5782	struct mlx5_ifc_modify_hca_vport_context_in_bits {
				5783	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5784	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5785
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5786	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5787	u8 op_mod[0x10];
				5788
				5789	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5790	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	5791	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5792	u8 vport_number[0x10];
				5793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5794	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5795
				5796	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
				5797	};
				5798
				5799	struct mlx5_ifc_modify_cq_out_bits {
				5800	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5801	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5802
				5803	u8 syndrome[0x20];
				5804
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5805	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5806	};
				5807
				5808	enum {
				5809	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
				5810	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
				5811	};
				5812
				5813	struct mlx5_ifc_modify_cq_in_bits {
				5814	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	5815	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5816
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5817	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5818	u8 op_mod[0x10];
				5819
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5820	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5821	u8 cqn[0x18];
				5822
				5823	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
				5824
				5825	struct mlx5_ifc_cqc_bits cq_context;
				5826
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5827	u8 reserved_at_280[0x40];
				5828
				5829	u8 cq_umem_valid[0x1];
				5830	u8 reserved_at_2c1[0x5bf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5831
				5832	u8 pas[0][0x40];
				5833	};
				5834
				5835	struct mlx5_ifc_modify_cong_status_out_bits {
				5836	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5837	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5838
				5839	u8 syndrome[0x20];
				5840
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5841	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5842	};
				5843
				5844	struct mlx5_ifc_modify_cong_status_in_bits {
				5845	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5846	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5847
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5848	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5849	u8 op_mod[0x10];
				5850
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5851	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5852	u8 priority[0x4];
				5853	u8 cong_protocol[0x4];
				5854
				5855	u8 enable[0x1];
				5856	u8 tag_enable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5857	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5858	};
				5859
				5860	struct mlx5_ifc_modify_cong_params_out_bits {
				5861	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5862	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5863
				5864	u8 syndrome[0x20];
				5865
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5866	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5867	};
				5868
				5869	struct mlx5_ifc_modify_cong_params_in_bits {
				5870	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5871	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5872
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5873	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5874	u8 op_mod[0x10];
				5875
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5876	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5877	u8 cong_protocol[0x4];
				5878
				5879	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
				5880
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5881	u8 reserved_at_80[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5882
				5883	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
				5884	};
				5885
				5886	struct mlx5_ifc_manage_pages_out_bits {
				5887	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5888	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5889
				5890	u8 syndrome[0x20];
				5891
				5892	u8 output_num_entries[0x20];
				5893
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5894	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5895
				5896	u8 pas[0][0x40];
				5897	};
				5898
				5899	enum {
				5900	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
				5901	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
				5902	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
				5903	};
				5904
				5905	struct mlx5_ifc_manage_pages_in_bits {
				5906	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5907	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5908
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5909	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5910	u8 op_mod[0x10];
				5911
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	5912	u8 embedded_cpu_function[0x1];
				5913	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5914	u8 function_id[0x10];
				5915
				5916	u8 input_num_entries[0x20];
				5917
				5918	u8 pas[0][0x40];
				5919	};
				5920
				5921	struct mlx5_ifc_mad_ifc_out_bits {
				5922	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5923	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5924
				5925	u8 syndrome[0x20];
				5926
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5927	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5928
				5929	u8 response_mad_packet[256][0x8];
				5930	};
				5931
				5932	struct mlx5_ifc_mad_ifc_in_bits {
				5933	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5934	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5935
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5936	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5937	u8 op_mod[0x10];
				5938
				5939	u8 remote_lid[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5940	u8 reserved_at_50[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5941	u8 port[0x8];
				5942
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5943	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5944
				5945	u8 mad[256][0x8];
				5946	};
				5947
				5948	struct mlx5_ifc_init_hca_out_bits {
				5949	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5950	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5951
				5952	u8 syndrome[0x20];
				5953
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5954	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5955	};
				5956
				5957	struct mlx5_ifc_init_hca_in_bits {
				5958	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5959	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5960
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5961	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5962	u8 op_mod[0x10];
				5963
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5964	u8 reserved_at_40[0x40];
Daniel Jurgens	8737f81	2018-01-04 17:25:32 +0200	[diff] [blame]	5965	u8 sw_owner_id[4][0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5966	};
				5967
				5968	struct mlx5_ifc_init2rtr_qp_out_bits {
				5969	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5970	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5971
				5972	u8 syndrome[0x20];
				5973
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5974	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5975	};
				5976
				5977	struct mlx5_ifc_init2rtr_qp_in_bits {
				5978	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5979	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5980
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5981	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5982	u8 op_mod[0x10];
				5983
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5984	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5985	u8 qpn[0x18];
				5986
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5987	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5988
				5989	u8 opt_param_mask[0x20];
				5990
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5991	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5992
				5993	struct mlx5_ifc_qpc_bits qpc;
				5994
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5995	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5996	};
				5997
				5998	struct mlx5_ifc_init2init_qp_out_bits {
				5999	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6000	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6001
				6002	u8 syndrome[0x20];
				6003
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6004	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6005	};
				6006
				6007	struct mlx5_ifc_init2init_qp_in_bits {
				6008	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	6009	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6010
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6011	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6012	u8 op_mod[0x10];
				6013
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6014	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6015	u8 qpn[0x18];
				6016
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6017	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6018
				6019	u8 opt_param_mask[0x20];
				6020
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6021	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6022
				6023	struct mlx5_ifc_qpc_bits qpc;
				6024
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6025	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6026	};
				6027
				6028	struct mlx5_ifc_get_dropped_packet_log_out_bits {
				6029	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6030	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6031
				6032	u8 syndrome[0x20];
				6033
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6034	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6035
				6036	u8 packet_headers_log[128][0x8];
				6037
				6038	u8 packet_syndrome[64][0x8];
				6039	};
				6040
				6041	struct mlx5_ifc_get_dropped_packet_log_in_bits {
				6042	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6043	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6044
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6045	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6046	u8 op_mod[0x10];
				6047
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6048	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6049	};
				6050
				6051	struct mlx5_ifc_gen_eqe_in_bits {
				6052	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6053	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6054
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6055	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6056	u8 op_mod[0x10];
				6057
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6058	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6059	u8 eq_number[0x8];
				6060
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6061	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6062
				6063	u8 eqe[64][0x8];
				6064	};
				6065
				6066	struct mlx5_ifc_gen_eq_out_bits {
				6067	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6068	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6069
				6070	u8 syndrome[0x20];
				6071
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6072	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6073	};
				6074
				6075	struct mlx5_ifc_enable_hca_out_bits {
				6076	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6077	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6078
				6079	u8 syndrome[0x20];
				6080
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6081	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6082	};
				6083
				6084	struct mlx5_ifc_enable_hca_in_bits {
				6085	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6086	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6087
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6088	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6089	u8 op_mod[0x10];
				6090
Bodong Wang	22e939a	2019-02-12 22:55:36 -0800	[diff] [blame]	6091	u8 embedded_cpu_function[0x1];
				6092	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6093	u8 function_id[0x10];
				6094
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6095	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6096	};
				6097
				6098	struct mlx5_ifc_drain_dct_out_bits {
				6099	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6100	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6101
				6102	u8 syndrome[0x20];
				6103
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6104	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6105	};
				6106
				6107	struct mlx5_ifc_drain_dct_in_bits {
				6108	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	6109	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6110
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6111	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6112	u8 op_mod[0x10];
				6113
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6114	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6115	u8 dctn[0x18];
				6116
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6117	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6118	};
				6119
				6120	struct mlx5_ifc_disable_hca_out_bits {
				6121	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6122	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6123
				6124	u8 syndrome[0x20];
				6125
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6126	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6127	};
				6128
				6129	struct mlx5_ifc_disable_hca_in_bits {
				6130	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6131	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6132
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6133	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6134	u8 op_mod[0x10];
				6135
Bodong Wang	22e939a	2019-02-12 22:55:36 -0800	[diff] [blame]	6136	u8 embedded_cpu_function[0x1];
				6137	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6138	u8 function_id[0x10];
				6139
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6140	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6141	};
				6142
				6143	struct mlx5_ifc_detach_from_mcg_out_bits {
				6144	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6145	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6146
				6147	u8 syndrome[0x20];
				6148
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6149	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6150	};
				6151
				6152	struct mlx5_ifc_detach_from_mcg_in_bits {
				6153	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6154	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6155
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6156	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6157	u8 op_mod[0x10];
				6158
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6159	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6160	u8 qpn[0x18];
				6161
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6162	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6163
				6164	u8 multicast_gid[16][0x8];
				6165	};
				6166
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6167	struct mlx5_ifc_destroy_xrq_out_bits {
				6168	u8 status[0x8];
				6169	u8 reserved_at_8[0x18];
				6170
				6171	u8 syndrome[0x20];
				6172
				6173	u8 reserved_at_40[0x40];
				6174	};
				6175
				6176	struct mlx5_ifc_destroy_xrq_in_bits {
				6177	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6178	u8 uid[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6179
				6180	u8 reserved_at_20[0x10];
				6181	u8 op_mod[0x10];
				6182
				6183	u8 reserved_at_40[0x8];
				6184	u8 xrqn[0x18];
				6185
				6186	u8 reserved_at_60[0x20];
				6187	};
				6188
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6189	struct mlx5_ifc_destroy_xrc_srq_out_bits {
				6190	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6191	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6192
				6193	u8 syndrome[0x20];
				6194
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6195	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6196	};
				6197
				6198	struct mlx5_ifc_destroy_xrc_srq_in_bits {
				6199	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6200	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6201
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6202	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6203	u8 op_mod[0x10];
				6204
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6205	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6206	u8 xrc_srqn[0x18];
				6207
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6208	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6209	};
				6210
				6211	struct mlx5_ifc_destroy_tis_out_bits {
				6212	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6213	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6214
				6215	u8 syndrome[0x20];
				6216
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6217	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6218	};
				6219
				6220	struct mlx5_ifc_destroy_tis_in_bits {
				6221	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6222	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6223
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6224	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6225	u8 op_mod[0x10];
				6226
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6227	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6228	u8 tisn[0x18];
				6229
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6230	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6231	};
				6232
				6233	struct mlx5_ifc_destroy_tir_out_bits {
				6234	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6235	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6236
				6237	u8 syndrome[0x20];
				6238
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6239	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6240	};
				6241
				6242	struct mlx5_ifc_destroy_tir_in_bits {
				6243	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6244	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6245
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6246	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6247	u8 op_mod[0x10];
				6248
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6249	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6250	u8 tirn[0x18];
				6251
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6252	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6253	};
				6254
				6255	struct mlx5_ifc_destroy_srq_out_bits {
				6256	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6257	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6258
				6259	u8 syndrome[0x20];
				6260
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6261	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6262	};
				6263
				6264	struct mlx5_ifc_destroy_srq_in_bits {
				6265	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6266	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6267
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6268	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6269	u8 op_mod[0x10];
				6270
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6271	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6272	u8 srqn[0x18];
				6273
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6274	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6275	};
				6276
				6277	struct mlx5_ifc_destroy_sq_out_bits {
				6278	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6279	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6280
				6281	u8 syndrome[0x20];
				6282
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6283	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6284	};
				6285
				6286	struct mlx5_ifc_destroy_sq_in_bits {
				6287	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	6288	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6289
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6290	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6291	u8 op_mod[0x10];
				6292
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6293	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6294	u8 sqn[0x18];
				6295
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6296	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6297	};
				6298
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	6299	struct mlx5_ifc_destroy_scheduling_element_out_bits {
				6300	u8 status[0x8];
				6301	u8 reserved_at_8[0x18];
				6302
				6303	u8 syndrome[0x20];
				6304
				6305	u8 reserved_at_40[0x1c0];
				6306	};
				6307
				6308	struct mlx5_ifc_destroy_scheduling_element_in_bits {
				6309	u8 opcode[0x10];
				6310	u8 reserved_at_10[0x10];
				6311
				6312	u8 reserved_at_20[0x10];
				6313	u8 op_mod[0x10];
				6314
				6315	u8 scheduling_hierarchy[0x8];
				6316	u8 reserved_at_48[0x18];
				6317
				6318	u8 scheduling_element_id[0x20];
				6319
				6320	u8 reserved_at_80[0x180];
				6321	};
				6322
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6323	struct mlx5_ifc_destroy_rqt_out_bits {
				6324	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6325	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6326
				6327	u8 syndrome[0x20];
				6328
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6329	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6330	};
				6331
				6332	struct mlx5_ifc_destroy_rqt_in_bits {
				6333	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6334	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6335
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6336	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6337	u8 op_mod[0x10];
				6338
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6339	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6340	u8 rqtn[0x18];
				6341
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6342	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6343	};
				6344
				6345	struct mlx5_ifc_destroy_rq_out_bits {
				6346	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6347	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6348
				6349	u8 syndrome[0x20];
				6350
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6351	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6352	};
				6353
				6354	struct mlx5_ifc_destroy_rq_in_bits {
				6355	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	6356	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6357
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6358	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6359	u8 op_mod[0x10];
				6360
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6361	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6362	u8 rqn[0x18];
				6363
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6364	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6365	};
				6366
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	6367	struct mlx5_ifc_set_delay_drop_params_in_bits {
				6368	u8 opcode[0x10];
				6369	u8 reserved_at_10[0x10];
				6370
				6371	u8 reserved_at_20[0x10];
				6372	u8 op_mod[0x10];
				6373
				6374	u8 reserved_at_40[0x20];
				6375
				6376	u8 reserved_at_60[0x10];
				6377	u8 delay_drop_timeout[0x10];
				6378	};
				6379
				6380	struct mlx5_ifc_set_delay_drop_params_out_bits {
				6381	u8 status[0x8];
				6382	u8 reserved_at_8[0x18];
				6383
				6384	u8 syndrome[0x20];
				6385
				6386	u8 reserved_at_40[0x40];
				6387	};
				6388
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6389	struct mlx5_ifc_destroy_rmp_out_bits {
				6390	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6391	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6392
				6393	u8 syndrome[0x20];
				6394
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6395	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6396	};
				6397
				6398	struct mlx5_ifc_destroy_rmp_in_bits {
				6399	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6400	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6401
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6402	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6403	u8 op_mod[0x10];
				6404
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6405	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6406	u8 rmpn[0x18];
				6407
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6408	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6409	};
				6410
				6411	struct mlx5_ifc_destroy_qp_out_bits {
				6412	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6413	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6414
				6415	u8 syndrome[0x20];
				6416
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6417	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6418	};
				6419
				6420	struct mlx5_ifc_destroy_qp_in_bits {
				6421	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	6422	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6423
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6424	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6425	u8 op_mod[0x10];
				6426
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6427	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6428	u8 qpn[0x18];
				6429
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6430	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6431	};
				6432
				6433	struct mlx5_ifc_destroy_psv_out_bits {
				6434	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6435	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6436
				6437	u8 syndrome[0x20];
				6438
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6439	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6440	};
				6441
				6442	struct mlx5_ifc_destroy_psv_in_bits {
				6443	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6444	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6445
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6446	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6447	u8 op_mod[0x10];
				6448
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6449	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6450	u8 psvn[0x18];
				6451
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6452	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6453	};
				6454
				6455	struct mlx5_ifc_destroy_mkey_out_bits {
				6456	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6457	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6458
				6459	u8 syndrome[0x20];
				6460
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6461	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6462	};
				6463
				6464	struct mlx5_ifc_destroy_mkey_in_bits {
				6465	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6466	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6467
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6468	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6469	u8 op_mod[0x10];
				6470
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6471	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6472	u8 mkey_index[0x18];
				6473
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6474	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6475	};
				6476
				6477	struct mlx5_ifc_destroy_flow_table_out_bits {
				6478	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6479	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6480
				6481	u8 syndrome[0x20];
				6482
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6483	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6484	};
				6485
				6486	struct mlx5_ifc_destroy_flow_table_in_bits {
				6487	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6488	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6489
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6490	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6491	u8 op_mod[0x10];
				6492
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6493	u8 other_vport[0x1];
				6494	u8 reserved_at_41[0xf];
				6495	u8 vport_number[0x10];
				6496
				6497	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6498
				6499	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6500	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6501
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6502	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6503	u8 table_id[0x18];
				6504
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6505	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6506	};
				6507
				6508	struct mlx5_ifc_destroy_flow_group_out_bits {
				6509	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6510	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6511
				6512	u8 syndrome[0x20];
				6513
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6514	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6515	};
				6516
				6517	struct mlx5_ifc_destroy_flow_group_in_bits {
				6518	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6519	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6520
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6521	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6522	u8 op_mod[0x10];
				6523
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6524	u8 other_vport[0x1];
				6525	u8 reserved_at_41[0xf];
				6526	u8 vport_number[0x10];
				6527
				6528	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6529
				6530	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6531	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6532
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6533	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6534	u8 table_id[0x18];
				6535
				6536	u8 group_id[0x20];
				6537
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6538	u8 reserved_at_e0[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6539	};
				6540
				6541	struct mlx5_ifc_destroy_eq_out_bits {
				6542	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6543	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6544
				6545	u8 syndrome[0x20];
				6546
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6547	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6548	};
				6549
				6550	struct mlx5_ifc_destroy_eq_in_bits {
				6551	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6552	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6553
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6554	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6555	u8 op_mod[0x10];
				6556
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6557	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6558	u8 eq_number[0x8];
				6559
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6560	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6561	};
				6562
				6563	struct mlx5_ifc_destroy_dct_out_bits {
				6564	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6565	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6566
				6567	u8 syndrome[0x20];
				6568
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6569	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6570	};
				6571
				6572	struct mlx5_ifc_destroy_dct_in_bits {
				6573	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	6574	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6575
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6576	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6577	u8 op_mod[0x10];
				6578
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6579	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6580	u8 dctn[0x18];
				6581
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6582	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6583	};
				6584
				6585	struct mlx5_ifc_destroy_cq_out_bits {
				6586	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6587	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6588
				6589	u8 syndrome[0x20];
				6590
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6591	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6592	};
				6593
				6594	struct mlx5_ifc_destroy_cq_in_bits {
				6595	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	6596	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6598	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6599	u8 op_mod[0x10];
				6600
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6601	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6602	u8 cqn[0x18];
				6603
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6604	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6605	};
				6606
				6607	struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
				6608	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6609	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6610
				6611	u8 syndrome[0x20];
				6612
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6613	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6614	};
				6615
				6616	struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
				6617	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6618	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6619
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6620	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6621	u8 op_mod[0x10];
				6622
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6623	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6624
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6625	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6626	u8 vxlan_udp_port[0x10];
				6627	};
				6628
				6629	struct mlx5_ifc_delete_l2_table_entry_out_bits {
				6630	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6631	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6632
				6633	u8 syndrome[0x20];
				6634
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6635	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6636	};
				6637
				6638	struct mlx5_ifc_delete_l2_table_entry_in_bits {
				6639	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6640	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6641
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6642	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6643	u8 op_mod[0x10];
				6644
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6645	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6646
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6647	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6648	u8 table_index[0x18];
				6649
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6650	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6651	};
				6652
				6653	struct mlx5_ifc_delete_fte_out_bits {
				6654	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6655	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6656
				6657	u8 syndrome[0x20];
				6658
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6659	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6660	};
				6661
				6662	struct mlx5_ifc_delete_fte_in_bits {
				6663	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6664	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6665
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6666	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6667	u8 op_mod[0x10];
				6668
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6669	u8 other_vport[0x1];
				6670	u8 reserved_at_41[0xf];
				6671	u8 vport_number[0x10];
				6672
				6673	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6674
				6675	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6676	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6677
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6678	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6679	u8 table_id[0x18];
				6680
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6681	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6682
				6683	u8 flow_index[0x20];
				6684
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6685	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6686	};
				6687
				6688	struct mlx5_ifc_dealloc_xrcd_out_bits {
				6689	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6690	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6691
				6692	u8 syndrome[0x20];
				6693
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6694	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6695	};
				6696
				6697	struct mlx5_ifc_dealloc_xrcd_in_bits {
				6698	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6699	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6700
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6701	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6702	u8 op_mod[0x10];
				6703
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6704	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6705	u8 xrcd[0x18];
				6706
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6707	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6708	};
				6709
				6710	struct mlx5_ifc_dealloc_uar_out_bits {
				6711	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6712	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6713
				6714	u8 syndrome[0x20];
				6715
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6716	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6717	};
				6718
				6719	struct mlx5_ifc_dealloc_uar_in_bits {
				6720	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6721	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6722
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6723	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6724	u8 op_mod[0x10];
				6725
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6726	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6727	u8 uar[0x18];
				6728
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6729	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6730	};
				6731
				6732	struct mlx5_ifc_dealloc_transport_domain_out_bits {
				6733	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6734	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6735
				6736	u8 syndrome[0x20];
				6737
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6738	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6739	};
				6740
				6741	struct mlx5_ifc_dealloc_transport_domain_in_bits {
				6742	u8 opcode[0x10];
Yishai Hadas	71bef2f	2018-12-19 16:28:10 +0200	[diff] [blame]	6743	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6745	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6746	u8 op_mod[0x10];
				6747
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6748	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6749	u8 transport_domain[0x18];
				6750
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6751	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6752	};
				6753
				6754	struct mlx5_ifc_dealloc_q_counter_out_bits {
				6755	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6756	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6757
				6758	u8 syndrome[0x20];
				6759
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6760	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6761	};
				6762
				6763	struct mlx5_ifc_dealloc_q_counter_in_bits {
				6764	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6765	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6766
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6767	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6768	u8 op_mod[0x10];
				6769
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6770	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6771	u8 counter_set_id[0x8];
				6772
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6773	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6774	};
				6775
				6776	struct mlx5_ifc_dealloc_pd_out_bits {
				6777	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6778	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6779
				6780	u8 syndrome[0x20];
				6781
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6782	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6783	};
				6784
				6785	struct mlx5_ifc_dealloc_pd_in_bits {
				6786	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6787	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6788
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6789	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6790	u8 op_mod[0x10];
				6791
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6792	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6793	u8 pd[0x18];
				6794
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6795	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6796	};
				6797
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	6798	struct mlx5_ifc_dealloc_flow_counter_out_bits {
				6799	u8 status[0x8];
				6800	u8 reserved_at_8[0x18];
				6801
				6802	u8 syndrome[0x20];
				6803
				6804	u8 reserved_at_40[0x40];
				6805	};
				6806
				6807	struct mlx5_ifc_dealloc_flow_counter_in_bits {
				6808	u8 opcode[0x10];
				6809	u8 reserved_at_10[0x10];
				6810
				6811	u8 reserved_at_20[0x10];
				6812	u8 op_mod[0x10];
				6813
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	6814	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	6815
				6816	u8 reserved_at_60[0x20];
				6817	};
				6818
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6819	struct mlx5_ifc_create_xrq_out_bits {
				6820	u8 status[0x8];
				6821	u8 reserved_at_8[0x18];
				6822
				6823	u8 syndrome[0x20];
				6824
				6825	u8 reserved_at_40[0x8];
				6826	u8 xrqn[0x18];
				6827
				6828	u8 reserved_at_60[0x20];
				6829	};
				6830
				6831	struct mlx5_ifc_create_xrq_in_bits {
				6832	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6833	u8 uid[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6834
				6835	u8 reserved_at_20[0x10];
				6836	u8 op_mod[0x10];
				6837
				6838	u8 reserved_at_40[0x40];
				6839
				6840	struct mlx5_ifc_xrqc_bits xrq_context;
				6841	};
				6842
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6843	struct mlx5_ifc_create_xrc_srq_out_bits {
				6844	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6845	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6846
				6847	u8 syndrome[0x20];
				6848
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6849	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6850	u8 xrc_srqn[0x18];
				6851
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6852	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6853	};
				6854
				6855	struct mlx5_ifc_create_xrc_srq_in_bits {
				6856	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6857	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6858
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6859	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6860	u8 op_mod[0x10];
				6861
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6862	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6863
				6864	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
				6865
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	6866	u8 reserved_at_280[0x60];
				6867
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6868	u8 xrc_srq_umem_valid[0x1];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	6869	u8 reserved_at_2e1[0x1f];
				6870
				6871	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6872
				6873	u8 pas[0][0x40];
				6874	};
				6875
				6876	struct mlx5_ifc_create_tis_out_bits {
				6877	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6878	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6879
				6880	u8 syndrome[0x20];
				6881
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6882	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6883	u8 tisn[0x18];
				6884
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6885	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6886	};
				6887
				6888	struct mlx5_ifc_create_tis_in_bits {
				6889	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6890	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6891
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6892	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6893	u8 op_mod[0x10];
				6894
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6895	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6896
				6897	struct mlx5_ifc_tisc_bits ctx;
				6898	};
				6899
				6900	struct mlx5_ifc_create_tir_out_bits {
				6901	u8 status[0x8];
Ariel Levkovich	3e07047	2019-03-31 19:44:48 +0300	[diff] [blame]	6902	u8 icm_address_63_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6903
				6904	u8 syndrome[0x20];
				6905
Ariel Levkovich	3e07047	2019-03-31 19:44:48 +0300	[diff] [blame]	6906	u8 icm_address_39_32[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6907	u8 tirn[0x18];
				6908
Ariel Levkovich	3e07047	2019-03-31 19:44:48 +0300	[diff] [blame]	6909	u8 icm_address_31_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6910	};
				6911
				6912	struct mlx5_ifc_create_tir_in_bits {
				6913	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6914	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6915
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6916	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6917	u8 op_mod[0x10];
				6918
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6919	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6920
				6921	struct mlx5_ifc_tirc_bits ctx;
				6922	};
				6923
				6924	struct mlx5_ifc_create_srq_out_bits {
				6925	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6926	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6927
				6928	u8 syndrome[0x20];
				6929
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6930	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6931	u8 srqn[0x18];
				6932
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6933	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6934	};
				6935
				6936	struct mlx5_ifc_create_srq_in_bits {
				6937	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6938	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6939
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6940	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6941	u8 op_mod[0x10];
				6942
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6943	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6944
				6945	struct mlx5_ifc_srqc_bits srq_context_entry;
				6946
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6947	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6948
				6949	u8 pas[0][0x40];
				6950	};
				6951
				6952	struct mlx5_ifc_create_sq_out_bits {
				6953	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6954	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6955
				6956	u8 syndrome[0x20];
				6957
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6958	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6959	u8 sqn[0x18];
				6960
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6961	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6962	};
				6963
				6964	struct mlx5_ifc_create_sq_in_bits {
				6965	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	6966	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6967
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6968	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6969	u8 op_mod[0x10];
				6970
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6971	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6972
				6973	struct mlx5_ifc_sqc_bits ctx;
				6974	};
				6975
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	6976	struct mlx5_ifc_create_scheduling_element_out_bits {
				6977	u8 status[0x8];
				6978	u8 reserved_at_8[0x18];
				6979
				6980	u8 syndrome[0x20];
				6981
				6982	u8 reserved_at_40[0x40];
				6983
				6984	u8 scheduling_element_id[0x20];
				6985
				6986	u8 reserved_at_a0[0x160];
				6987	};
				6988
				6989	struct mlx5_ifc_create_scheduling_element_in_bits {
				6990	u8 opcode[0x10];
				6991	u8 reserved_at_10[0x10];
				6992
				6993	u8 reserved_at_20[0x10];
				6994	u8 op_mod[0x10];
				6995
				6996	u8 scheduling_hierarchy[0x8];
				6997	u8 reserved_at_48[0x18];
				6998
				6999	u8 reserved_at_60[0xa0];
				7000
				7001	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				7002
				7003	u8 reserved_at_300[0x100];
				7004	};
				7005
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7006	struct mlx5_ifc_create_rqt_out_bits {
				7007	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7008	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7009
				7010	u8 syndrome[0x20];
				7011
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7012	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7013	u8 rqtn[0x18];
				7014
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7015	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7016	};
				7017
				7018	struct mlx5_ifc_create_rqt_in_bits {
				7019	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7020	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7021
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7022	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7023	u8 op_mod[0x10];
				7024
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7025	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7026
				7027	struct mlx5_ifc_rqtc_bits rqt_context;
				7028	};
				7029
				7030	struct mlx5_ifc_create_rq_out_bits {
				7031	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7032	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7033
				7034	u8 syndrome[0x20];
				7035
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7036	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7037	u8 rqn[0x18];
				7038
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7039	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7040	};
				7041
				7042	struct mlx5_ifc_create_rq_in_bits {
				7043	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	7044	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7045
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7046	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7047	u8 op_mod[0x10];
				7048
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7049	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7050
				7051	struct mlx5_ifc_rqc_bits ctx;
				7052	};
				7053
				7054	struct mlx5_ifc_create_rmp_out_bits {
				7055	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7056	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7057
				7058	u8 syndrome[0x20];
				7059
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7060	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7061	u8 rmpn[0x18];
				7062
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7063	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7064	};
				7065
				7066	struct mlx5_ifc_create_rmp_in_bits {
				7067	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7068	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7069
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7070	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7071	u8 op_mod[0x10];
				7072
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7073	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7074
				7075	struct mlx5_ifc_rmpc_bits ctx;
				7076	};
				7077
				7078	struct mlx5_ifc_create_qp_out_bits {
				7079	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7080	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7081
				7082	u8 syndrome[0x20];
				7083
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7084	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7085	u8 qpn[0x18];
				7086
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7087	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7088	};
				7089
				7090	struct mlx5_ifc_create_qp_in_bits {
				7091	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	7092	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7093
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7094	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7095	u8 op_mod[0x10];
				7096
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7097	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7098
				7099	u8 opt_param_mask[0x20];
				7100
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7101	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7102
				7103	struct mlx5_ifc_qpc_bits qpc;
				7104
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7105	u8 reserved_at_800[0x60];
				7106
				7107	u8 wq_umem_valid[0x1];
				7108	u8 reserved_at_861[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7109
				7110	u8 pas[0][0x40];
				7111	};
				7112
				7113	struct mlx5_ifc_create_psv_out_bits {
				7114	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7115	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7116
				7117	u8 syndrome[0x20];
				7118
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7119	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7120
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7121	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7122	u8 psv0_index[0x18];
				7123
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7124	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7125	u8 psv1_index[0x18];
				7126
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7127	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7128	u8 psv2_index[0x18];
				7129
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7130	u8 reserved_at_e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7131	u8 psv3_index[0x18];
				7132	};
				7133
				7134	struct mlx5_ifc_create_psv_in_bits {
				7135	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7136	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7137
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7138	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7139	u8 op_mod[0x10];
				7140
				7141	u8 num_psv[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7142	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7143	u8 pd[0x18];
				7144
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7145	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7146	};
				7147
				7148	struct mlx5_ifc_create_mkey_out_bits {
				7149	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7150	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7151
				7152	u8 syndrome[0x20];
				7153
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7154	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7155	u8 mkey_index[0x18];
				7156
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7157	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7158	};
				7159
				7160	struct mlx5_ifc_create_mkey_in_bits {
				7161	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7162	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7163
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7164	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7165	u8 op_mod[0x10];
				7166
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7167	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7168
				7169	u8 pg_access[0x1];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7170	u8 mkey_umem_valid[0x1];
				7171	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7172
				7173	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
				7174
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7175	u8 reserved_at_280[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7176
				7177	u8 translations_octword_actual_size[0x20];
				7178
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7179	u8 reserved_at_320[0x560];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7180
				7181	u8 klm_pas_mtt[0][0x20];
				7182	};
				7183
				7184	struct mlx5_ifc_create_flow_table_out_bits {
				7185	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7186	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7187
				7188	u8 syndrome[0x20];
				7189
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7190	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7191	u8 table_id[0x18];
				7192
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7193	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7194	};
				7195
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7196	struct mlx5_ifc_flow_table_context_bits {
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	7197	u8 reformat_en[0x1];
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7198	u8 decap_en[0x1];
				7199	u8 reserved_at_2[0x2];
				7200	u8 table_miss_action[0x4];
				7201	u8 level[0x8];
				7202	u8 reserved_at_10[0x8];
				7203	u8 log_size[0x8];
				7204
				7205	u8 reserved_at_20[0x8];
				7206	u8 table_miss_id[0x18];
				7207
				7208	u8 reserved_at_40[0x8];
				7209	u8 lag_master_next_table_id[0x18];
				7210
				7211	u8 reserved_at_60[0xe0];
				7212	};
				7213
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7214	struct mlx5_ifc_create_flow_table_in_bits {
				7215	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7216	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7217
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7218	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7219	u8 op_mod[0x10];
				7220
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7221	u8 other_vport[0x1];
				7222	u8 reserved_at_41[0xf];
				7223	u8 vport_number[0x10];
				7224
				7225	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7226
				7227	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7228	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7229
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7230	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7231
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7232	struct mlx5_ifc_flow_table_context_bits flow_table_context;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7233	};
				7234
				7235	struct mlx5_ifc_create_flow_group_out_bits {
				7236	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7237	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7238
				7239	u8 syndrome[0x20];
				7240
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7241	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7242	u8 group_id[0x18];
				7243
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7244	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7245	};
				7246
				7247	enum {
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	7248	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
				7249	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
				7250	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
				7251	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7252	};
				7253
				7254	struct mlx5_ifc_create_flow_group_in_bits {
				7255	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7256	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7257
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7258	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7259	u8 op_mod[0x10];
				7260
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7261	u8 other_vport[0x1];
				7262	u8 reserved_at_41[0xf];
				7263	u8 vport_number[0x10];
				7264
				7265	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7266
				7267	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7268	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7269
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7270	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7271	u8 table_id[0x18];
				7272
Shahar Klein	3e99df8	2018-03-18 09:02:06 +0200	[diff] [blame]	7273	u8 source_eswitch_owner_vhca_id_valid[0x1];
				7274
				7275	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7276
				7277	u8 start_flow_index[0x20];
				7278
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7279	u8 reserved_at_100[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7280
				7281	u8 end_flow_index[0x20];
				7282
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7283	u8 reserved_at_140[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7284
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7285	u8 reserved_at_1e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7286	u8 match_criteria_enable[0x8];
				7287
				7288	struct mlx5_ifc_fte_match_param_bits match_criteria;
				7289
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7290	u8 reserved_at_1200[0xe00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7291	};
				7292
				7293	struct mlx5_ifc_create_eq_out_bits {
				7294	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7295	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7296
				7297	u8 syndrome[0x20];
				7298
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7299	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7300	u8 eq_number[0x8];
				7301
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7302	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7303	};
				7304
				7305	struct mlx5_ifc_create_eq_in_bits {
				7306	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7307	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7308
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7309	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7310	u8 op_mod[0x10];
				7311
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7312	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7313
				7314	struct mlx5_ifc_eqc_bits eq_context_entry;
				7315
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7316	u8 reserved_at_280[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7317
				7318	u8 event_bitmask[0x40];
				7319
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7320	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7321
				7322	u8 pas[0][0x40];
				7323	};
				7324
				7325	struct mlx5_ifc_create_dct_out_bits {
				7326	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7327	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7328
				7329	u8 syndrome[0x20];
				7330
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7331	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7332	u8 dctn[0x18];
				7333
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7334	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7335	};
				7336
				7337	struct mlx5_ifc_create_dct_in_bits {
				7338	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	7339	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7340
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7341	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7342	u8 op_mod[0x10];
				7343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7344	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7345
				7346	struct mlx5_ifc_dctc_bits dct_context_entry;
				7347
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7348	u8 reserved_at_280[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7349	};
				7350
				7351	struct mlx5_ifc_create_cq_out_bits {
				7352	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7353	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7354
				7355	u8 syndrome[0x20];
				7356
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7357	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7358	u8 cqn[0x18];
				7359
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7360	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7361	};
				7362
				7363	struct mlx5_ifc_create_cq_in_bits {
				7364	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	7365	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7366
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7367	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7368	u8 op_mod[0x10];
				7369
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7370	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7371
				7372	struct mlx5_ifc_cqc_bits cq_context;
				7373
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7374	u8 reserved_at_280[0x60];
				7375
				7376	u8 cq_umem_valid[0x1];
				7377	u8 reserved_at_2e1[0x59f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7378
				7379	u8 pas[0][0x40];
				7380	};
				7381
				7382	struct mlx5_ifc_config_int_moderation_out_bits {
				7383	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7384	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7385
				7386	u8 syndrome[0x20];
				7387
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7388	u8 reserved_at_40[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7389	u8 min_delay[0xc];
				7390	u8 int_vector[0x10];
				7391
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7392	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7393	};
				7394
				7395	enum {
				7396	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
				7397	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
				7398	};
				7399
				7400	struct mlx5_ifc_config_int_moderation_in_bits {
				7401	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7402	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7403
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7404	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7405	u8 op_mod[0x10];
				7406
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7407	u8 reserved_at_40[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7408	u8 min_delay[0xc];
				7409	u8 int_vector[0x10];
				7410
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7411	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7412	};
				7413
				7414	struct mlx5_ifc_attach_to_mcg_out_bits {
				7415	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7416	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7417
				7418	u8 syndrome[0x20];
				7419
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7420	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7421	};
				7422
				7423	struct mlx5_ifc_attach_to_mcg_in_bits {
				7424	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7425	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7426
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7427	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7428	u8 op_mod[0x10];
				7429
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7430	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7431	u8 qpn[0x18];
				7432
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7433	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7434
				7435	u8 multicast_gid[16][0x8];
				7436	};
				7437
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7438	struct mlx5_ifc_arm_xrq_out_bits {
				7439	u8 status[0x8];
				7440	u8 reserved_at_8[0x18];
				7441
				7442	u8 syndrome[0x20];
				7443
				7444	u8 reserved_at_40[0x40];
				7445	};
				7446
				7447	struct mlx5_ifc_arm_xrq_in_bits {
				7448	u8 opcode[0x10];
				7449	u8 reserved_at_10[0x10];
				7450
				7451	u8 reserved_at_20[0x10];
				7452	u8 op_mod[0x10];
				7453
				7454	u8 reserved_at_40[0x8];
				7455	u8 xrqn[0x18];
				7456
				7457	u8 reserved_at_60[0x10];
				7458	u8 lwm[0x10];
				7459	};
				7460
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7461	struct mlx5_ifc_arm_xrc_srq_out_bits {
				7462	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7463	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7464
				7465	u8 syndrome[0x20];
				7466
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7467	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7468	};
				7469
				7470	enum {
				7471	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
				7472	};
				7473
				7474	struct mlx5_ifc_arm_xrc_srq_in_bits {
				7475	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7476	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7477
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7478	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7479	u8 op_mod[0x10];
				7480
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7481	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7482	u8 xrc_srqn[0x18];
				7483
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7484	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7485	u8 lwm[0x10];
				7486	};
				7487
				7488	struct mlx5_ifc_arm_rq_out_bits {
				7489	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7490	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7491
				7492	u8 syndrome[0x20];
				7493
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7494	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7495	};
				7496
				7497	enum {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7498	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
				7499	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7500	};
				7501
				7502	struct mlx5_ifc_arm_rq_in_bits {
				7503	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7504	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7505
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7506	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7507	u8 op_mod[0x10];
				7508
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7509	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7510	u8 srq_number[0x18];
				7511
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7512	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7513	u8 lwm[0x10];
				7514	};
				7515
				7516	struct mlx5_ifc_arm_dct_out_bits {
				7517	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7518	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7519
				7520	u8 syndrome[0x20];
				7521
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7522	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7523	};
				7524
				7525	struct mlx5_ifc_arm_dct_in_bits {
				7526	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7527	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7528
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7529	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7530	u8 op_mod[0x10];
				7531
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7532	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7533	u8 dct_number[0x18];
				7534
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7535	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7536	};
				7537
				7538	struct mlx5_ifc_alloc_xrcd_out_bits {
				7539	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7540	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7541
				7542	u8 syndrome[0x20];
				7543
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7544	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7545	u8 xrcd[0x18];
				7546
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7547	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7548	};
				7549
				7550	struct mlx5_ifc_alloc_xrcd_in_bits {
				7551	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7552	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7553
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7554	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7555	u8 op_mod[0x10];
				7556
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7557	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7558	};
				7559
				7560	struct mlx5_ifc_alloc_uar_out_bits {
				7561	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7562	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7563
				7564	u8 syndrome[0x20];
				7565
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7566	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7567	u8 uar[0x18];
				7568
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7569	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7570	};
				7571
				7572	struct mlx5_ifc_alloc_uar_in_bits {
				7573	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7574	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7575
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7576	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7577	u8 op_mod[0x10];
				7578
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7579	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7580	};
				7581
				7582	struct mlx5_ifc_alloc_transport_domain_out_bits {
				7583	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7584	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7585
				7586	u8 syndrome[0x20];
				7587
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7588	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7589	u8 transport_domain[0x18];
				7590
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7591	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7592	};
				7593
				7594	struct mlx5_ifc_alloc_transport_domain_in_bits {
				7595	u8 opcode[0x10];
Yishai Hadas	71bef2f	2018-12-19 16:28:10 +0200	[diff] [blame]	7596	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7598	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7599	u8 op_mod[0x10];
				7600
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7601	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7602	};
				7603
				7604	struct mlx5_ifc_alloc_q_counter_out_bits {
				7605	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7606	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7607
				7608	u8 syndrome[0x20];
				7609
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7610	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7611	u8 counter_set_id[0x8];
				7612
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7613	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7614	};
				7615
				7616	struct mlx5_ifc_alloc_q_counter_in_bits {
				7617	u8 opcode[0x10];
Leon Romanovsky	2acc795	2018-12-06 14:40:11 +0200	[diff] [blame]	7618	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7619
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7620	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7621	u8 op_mod[0x10];
				7622
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7623	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7624	};
				7625
				7626	struct mlx5_ifc_alloc_pd_out_bits {
				7627	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7628	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7629
				7630	u8 syndrome[0x20];
				7631
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7632	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7633	u8 pd[0x18];
				7634
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7635	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7636	};
				7637
				7638	struct mlx5_ifc_alloc_pd_in_bits {
				7639	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7640	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7641
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7642	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7643	u8 op_mod[0x10];
				7644
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7645	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7646	};
				7647
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	7648	struct mlx5_ifc_alloc_flow_counter_out_bits {
				7649	u8 status[0x8];
				7650	u8 reserved_at_8[0x18];
				7651
				7652	u8 syndrome[0x20];
				7653
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	7654	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	7655
				7656	u8 reserved_at_60[0x20];
				7657	};
				7658
				7659	struct mlx5_ifc_alloc_flow_counter_in_bits {
				7660	u8 opcode[0x10];
				7661	u8 reserved_at_10[0x10];
				7662
				7663	u8 reserved_at_20[0x10];
				7664	u8 op_mod[0x10];
				7665
				7666	u8 reserved_at_40[0x40];
				7667	};
				7668
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7669	struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
				7670	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7671	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7672
				7673	u8 syndrome[0x20];
				7674
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7675	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7676	};
				7677
				7678	struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
				7679	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7680	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7681
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7682	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7683	u8 op_mod[0x10];
				7684
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7685	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7686
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7687	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7688	u8 vxlan_udp_port[0x10];
				7689	};
				7690
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7691	struct mlx5_ifc_set_pp_rate_limit_out_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7692	u8 status[0x8];
				7693	u8 reserved_at_8[0x18];
				7694
				7695	u8 syndrome[0x20];
				7696
				7697	u8 reserved_at_40[0x40];
				7698	};
				7699
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7700	struct mlx5_ifc_set_pp_rate_limit_in_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7701	u8 opcode[0x10];
				7702	u8 reserved_at_10[0x10];
				7703
				7704	u8 reserved_at_20[0x10];
				7705	u8 op_mod[0x10];
				7706
				7707	u8 reserved_at_40[0x10];
				7708	u8 rate_limit_index[0x10];
				7709
				7710	u8 reserved_at_60[0x20];
				7711
				7712	u8 rate_limit[0x20];
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7713
Bodong Wang	05d3ac9	2018-03-19 15:10:29 +0200	[diff] [blame]	7714	u8 burst_upper_bound[0x20];
				7715
				7716	u8 reserved_at_c0[0x10];
				7717	u8 typical_packet_size[0x10];
				7718
				7719	u8 reserved_at_e0[0x120];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7720	};
				7721
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7722	struct mlx5_ifc_access_register_out_bits {
				7723	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7724	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7725
				7726	u8 syndrome[0x20];
				7727
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7728	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7729
				7730	u8 register_data[0][0x20];
				7731	};
				7732
				7733	enum {
				7734	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
				7735	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
				7736	};
				7737
				7738	struct mlx5_ifc_access_register_in_bits {
				7739	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7740	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7741
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7742	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7743	u8 op_mod[0x10];
				7744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7745	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7746	u8 register_id[0x10];
				7747
				7748	u8 argument[0x20];
				7749
				7750	u8 register_data[0][0x20];
				7751	};
				7752
				7753	struct mlx5_ifc_sltp_reg_bits {
				7754	u8 status[0x4];
				7755	u8 version[0x4];
				7756	u8 local_port[0x8];
				7757	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7758	u8 reserved_at_12[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7759	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7760	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7761
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7762	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7763
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7764	u8 reserved_at_40[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7765	u8 polarity[0x1];
				7766	u8 ob_tap0[0x8];
				7767	u8 ob_tap1[0x8];
				7768	u8 ob_tap2[0x8];
				7769
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7770	u8 reserved_at_60[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7771	u8 ob_preemp_mode[0x4];
				7772	u8 ob_reg[0x8];
				7773	u8 ob_bias[0x8];
				7774
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7775	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7776	};
				7777
				7778	struct mlx5_ifc_slrg_reg_bits {
				7779	u8 status[0x4];
				7780	u8 version[0x4];
				7781	u8 local_port[0x8];
				7782	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7783	u8 reserved_at_12[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7784	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7785	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7786
				7787	u8 time_to_link_up[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7788	u8 reserved_at_30[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7789	u8 grade_lane_speed[0x4];
				7790
				7791	u8 grade_version[0x8];
				7792	u8 grade[0x18];
				7793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7794	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7795	u8 height_grade_type[0x4];
				7796	u8 height_grade[0x18];
				7797
				7798	u8 height_dz[0x10];
				7799	u8 height_dv[0x10];
				7800
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7801	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7802	u8 height_sigma[0x10];
				7803
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7804	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7805
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7806	u8 reserved_at_e0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7807	u8 phase_grade_type[0x4];
				7808	u8 phase_grade[0x18];
				7809
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7810	u8 reserved_at_100[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7811	u8 phase_eo_pos[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7812	u8 reserved_at_110[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7813	u8 phase_eo_neg[0x8];
				7814
				7815	u8 ffe_set_tested[0x10];
				7816	u8 test_errors_per_lane[0x10];
				7817	};
				7818
				7819	struct mlx5_ifc_pvlc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7820	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7821	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7822	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7823
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7824	u8 reserved_at_20[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7825	u8 vl_hw_cap[0x4];
				7826
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7827	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7828	u8 vl_admin[0x4];
				7829
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7830	u8 reserved_at_60[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7831	u8 vl_operational[0x4];
				7832	};
				7833
				7834	struct mlx5_ifc_pude_reg_bits {
				7835	u8 swid[0x8];
				7836	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7837	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7838	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7839	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7840	u8 oper_status[0x4];
				7841
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7842	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7843	};
				7844
				7845	struct mlx5_ifc_ptys_reg_bits {
Bodong Wang	e7e31ca	2016-09-07 19:07:58 +0300	[diff] [blame]	7846	u8 reserved_at_0[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7847	u8 an_disable_admin[0x1];
Bodong Wang	e7e31ca	2016-09-07 19:07:58 +0300	[diff] [blame]	7848	u8 an_disable_cap[0x1];
				7849	u8 reserved_at_3[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7850	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7851	u8 reserved_at_10[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7852	u8 proto_mask[0x3];
				7853
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7854	u8 an_status[0x4];
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame]	7855	u8 reserved_at_24[0x1c];
				7856
				7857	u8 ext_eth_proto_capability[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7858
				7859	u8 eth_proto_capability[0x20];
				7860
				7861	u8 ib_link_width_capability[0x10];
				7862	u8 ib_proto_capability[0x10];
				7863
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame]	7864	u8 ext_eth_proto_admin[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7865
				7866	u8 eth_proto_admin[0x20];
				7867
				7868	u8 ib_link_width_admin[0x10];
				7869	u8 ib_proto_admin[0x10];
				7870
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame]	7871	u8 ext_eth_proto_oper[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7872
				7873	u8 eth_proto_oper[0x20];
				7874
				7875	u8 ib_link_width_oper[0x10];
				7876	u8 ib_proto_oper[0x10];
				7877
Eran Ben Elisha	5b4793f	2017-02-13 14:00:59 +0200	[diff] [blame]	7878	u8 reserved_at_160[0x1c];
				7879	u8 connector_type[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7880
				7881	u8 eth_proto_lp_advertise[0x20];
				7882
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7883	u8 reserved_at_1a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7884	};
				7885
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7886	struct mlx5_ifc_mlcr_reg_bits {
				7887	u8 reserved_at_0[0x8];
				7888	u8 local_port[0x8];
				7889	u8 reserved_at_10[0x20];
				7890
				7891	u8 beacon_duration[0x10];
				7892	u8 reserved_at_40[0x10];
				7893
				7894	u8 beacon_remain[0x10];
				7895	};
				7896
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7897	struct mlx5_ifc_ptas_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7898	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7899
				7900	u8 algorithm_options[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7901	u8 reserved_at_30[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7902	u8 repetitions_mode[0x4];
				7903	u8 num_of_repetitions[0x8];
				7904
				7905	u8 grade_version[0x8];
				7906	u8 height_grade_type[0x4];
				7907	u8 phase_grade_type[0x4];
				7908	u8 height_grade_weight[0x8];
				7909	u8 phase_grade_weight[0x8];
				7910
				7911	u8 gisim_measure_bits[0x10];
				7912	u8 adaptive_tap_measure_bits[0x10];
				7913
				7914	u8 ber_bath_high_error_threshold[0x10];
				7915	u8 ber_bath_mid_error_threshold[0x10];
				7916
				7917	u8 ber_bath_low_error_threshold[0x10];
				7918	u8 one_ratio_high_threshold[0x10];
				7919
				7920	u8 one_ratio_high_mid_threshold[0x10];
				7921	u8 one_ratio_low_mid_threshold[0x10];
				7922
				7923	u8 one_ratio_low_threshold[0x10];
				7924	u8 ndeo_error_threshold[0x10];
				7925
				7926	u8 mixer_offset_step_size[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7927	u8 reserved_at_110[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7928	u8 mix90_phase_for_voltage_bath[0x8];
				7929
				7930	u8 mixer_offset_start[0x10];
				7931	u8 mixer_offset_end[0x10];
				7932
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7933	u8 reserved_at_140[0x15];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7934	u8 ber_test_time[0xb];
				7935	};
				7936
				7937	struct mlx5_ifc_pspa_reg_bits {
				7938	u8 swid[0x8];
				7939	u8 local_port[0x8];
				7940	u8 sub_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7941	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7942
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7943	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7944	};
				7945
				7946	struct mlx5_ifc_pqdr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7947	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7948	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7949	u8 reserved_at_10[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7950	u8 prio[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7951	u8 reserved_at_18[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7952	u8 mode[0x2];
				7953
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7954	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7955
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7956	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7957	u8 min_threshold[0x10];
				7958
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7959	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7960	u8 max_threshold[0x10];
				7961
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7962	u8 reserved_at_80[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7963	u8 mark_probability_denominator[0x10];
				7964
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7965	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7966	};
				7967
				7968	struct mlx5_ifc_ppsc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7969	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7970	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7971	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7972
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7973	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7974
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7975	u8 reserved_at_80[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7976	u8 wrps_admin[0x4];
				7977
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7978	u8 reserved_at_a0[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7979	u8 wrps_status[0x4];
				7980
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7981	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7982	u8 up_threshold[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7983	u8 reserved_at_d0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7984	u8 down_threshold[0x8];
				7985
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7986	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7987
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7988	u8 reserved_at_100[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7989	u8 srps_admin[0x4];
				7990
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7991	u8 reserved_at_120[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7992	u8 srps_status[0x4];
				7993
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7994	u8 reserved_at_140[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7995	};
				7996
				7997	struct mlx5_ifc_pplr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7998	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7999	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8000	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8001
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8002	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8003	u8 lb_cap[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8004	u8 reserved_at_30[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8005	u8 lb_en[0x8];
				8006	};
				8007
				8008	struct mlx5_ifc_pplm_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8009	u8 reserved_at_0[0x8];
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8010	u8 local_port[0x8];
				8011	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8012
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8013	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8014
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8015	u8 port_profile_mode[0x8];
				8016	u8 static_port_profile[0x8];
				8017	u8 active_port_profile[0x8];
				8018	u8 reserved_at_58[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8019
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8020	u8 retransmission_active[0x8];
				8021	u8 fec_mode_active[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8022
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8023	u8 rs_fec_correction_bypass_cap[0x4];
				8024	u8 reserved_at_84[0x8];
				8025	u8 fec_override_cap_56g[0x4];
				8026	u8 fec_override_cap_100g[0x4];
				8027	u8 fec_override_cap_50g[0x4];
				8028	u8 fec_override_cap_25g[0x4];
				8029	u8 fec_override_cap_10g_40g[0x4];
				8030
				8031	u8 rs_fec_correction_bypass_admin[0x4];
				8032	u8 reserved_at_a4[0x8];
				8033	u8 fec_override_admin_56g[0x4];
				8034	u8 fec_override_admin_100g[0x4];
				8035	u8 fec_override_admin_50g[0x4];
				8036	u8 fec_override_admin_25g[0x4];
				8037	u8 fec_override_admin_10g_40g[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8038	};
				8039
				8040	struct mlx5_ifc_ppcnt_reg_bits {
				8041	u8 swid[0x8];
				8042	u8 local_port[0x8];
				8043	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8044	u8 reserved_at_12[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8045	u8 grp[0x6];
				8046
				8047	u8 clr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8048	u8 reserved_at_21[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8049	u8 prio_tc[0x3];
				8050
				8051	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
				8052	};
				8053
Aya Levin	4039049	2019-03-29 15:38:03 -0700	[diff] [blame]	8054	struct mlx5_ifc_mpein_reg_bits {
				8055	u8 reserved_at_0[0x2];
				8056	u8 depth[0x6];
				8057	u8 pcie_index[0x8];
				8058	u8 node[0x8];
				8059	u8 reserved_at_18[0x8];
				8060
				8061	u8 capability_mask[0x20];
				8062
				8063	u8 reserved_at_40[0x8];
				8064	u8 link_width_enabled[0x8];
				8065	u8 link_speed_enabled[0x10];
				8066
				8067	u8 lane0_physical_position[0x8];
				8068	u8 link_width_active[0x8];
				8069	u8 link_speed_active[0x10];
				8070
				8071	u8 num_of_pfs[0x10];
				8072	u8 num_of_vfs[0x10];
				8073
				8074	u8 bdf0[0x10];
				8075	u8 reserved_at_b0[0x10];
				8076
				8077	u8 max_read_request_size[0x4];
				8078	u8 max_payload_size[0x4];
				8079	u8 reserved_at_c8[0x5];
				8080	u8 pwr_status[0x3];
				8081	u8 port_type[0x4];
				8082	u8 reserved_at_d4[0xb];
				8083	u8 lane_reversal[0x1];
				8084
				8085	u8 reserved_at_e0[0x14];
				8086	u8 pci_power[0xc];
				8087
				8088	u8 reserved_at_100[0x20];
				8089
				8090	u8 device_status[0x10];
				8091	u8 port_state[0x8];
				8092	u8 reserved_at_138[0x8];
				8093
				8094	u8 reserved_at_140[0x10];
				8095	u8 receiver_detect_result[0x10];
				8096
				8097	u8 reserved_at_160[0x20];
				8098	};
				8099
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	8100	struct mlx5_ifc_mpcnt_reg_bits {
				8101	u8 reserved_at_0[0x8];
				8102	u8 pcie_index[0x8];
				8103	u8 reserved_at_10[0xa];
				8104	u8 grp[0x6];
				8105
				8106	u8 clr[0x1];
				8107	u8 reserved_at_21[0x1f];
				8108
				8109	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
				8110	};
				8111
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8112	struct mlx5_ifc_ppad_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8113	u8 reserved_at_0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8114	u8 single_mac[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8115	u8 reserved_at_4[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8116	u8 local_port[0x8];
				8117	u8 mac_47_32[0x10];
				8118
				8119	u8 mac_31_0[0x20];
				8120
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8121	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8122	};
				8123
				8124	struct mlx5_ifc_pmtu_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8125	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8126	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8127	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8128
				8129	u8 max_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8130	u8 reserved_at_30[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8131
				8132	u8 admin_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8133	u8 reserved_at_50[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8134
				8135	u8 oper_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8136	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8137	};
				8138
				8139	struct mlx5_ifc_pmpr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8140	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8141	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8142	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8143
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8144	u8 reserved_at_20[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8145	u8 attenuation_5g[0x8];
				8146
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8147	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8148	u8 attenuation_7g[0x8];
				8149
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8150	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8151	u8 attenuation_12g[0x8];
				8152	};
				8153
				8154	struct mlx5_ifc_pmpe_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8155	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8156	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8157	u8 reserved_at_10[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8158	u8 module_status[0x4];
				8159
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8160	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8161	};
				8162
				8163	struct mlx5_ifc_pmpc_reg_bits {
				8164	u8 module_state_updated[32][0x8];
				8165	};
				8166
				8167	struct mlx5_ifc_pmlpn_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8168	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8169	u8 mlpn_status[0x4];
				8170	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8171	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8172
				8173	u8 e[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8174	u8 reserved_at_21[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8175	};
				8176
				8177	struct mlx5_ifc_pmlp_reg_bits {
				8178	u8 rxtx[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8179	u8 reserved_at_1[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8180	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8181	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8182	u8 width[0x8];
				8183
				8184	u8 lane0_module_mapping[0x20];
				8185
				8186	u8 lane1_module_mapping[0x20];
				8187
				8188	u8 lane2_module_mapping[0x20];
				8189
				8190	u8 lane3_module_mapping[0x20];
				8191
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8192	u8 reserved_at_a0[0x160];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8193	};
				8194
				8195	struct mlx5_ifc_pmaos_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8196	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8197	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8198	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8199	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8200	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8201	u8 oper_status[0x4];
				8202
				8203	u8 ase[0x1];
				8204	u8 ee[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8205	u8 reserved_at_22[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8206	u8 e[0x2];
				8207
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8208	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8209	};
				8210
				8211	struct mlx5_ifc_plpc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8212	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8213	u8 profile_id[0xc];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8214	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8215	u8 proto_mask[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8216	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8217
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8218	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8219	u8 lane_speed[0x10];
				8220
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8221	u8 reserved_at_40[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8222	u8 lpbf[0x1];
				8223	u8 fec_mode_policy[0x8];
				8224
				8225	u8 retransmission_capability[0x8];
				8226	u8 fec_mode_capability[0x18];
				8227
				8228	u8 retransmission_support_admin[0x8];
				8229	u8 fec_mode_support_admin[0x18];
				8230
				8231	u8 retransmission_request_admin[0x8];
				8232	u8 fec_mode_request_admin[0x18];
				8233
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8234	u8 reserved_at_c0[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8235	};
				8236
				8237	struct mlx5_ifc_plib_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8238	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8239	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8240	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8241	u8 ib_port[0x8];
				8242
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8243	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8244	};
				8245
				8246	struct mlx5_ifc_plbf_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8247	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8248	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8249	u8 reserved_at_10[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8250	u8 lbf_mode[0x3];
				8251
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8252	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8253	};
				8254
				8255	struct mlx5_ifc_pipg_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8256	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8257	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8258	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8259
				8260	u8 dic[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8261	u8 reserved_at_21[0x19];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8262	u8 ipg[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8263	u8 reserved_at_3e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8264	};
				8265
				8266	struct mlx5_ifc_pifr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8267	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8268	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8269	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8270
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8271	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8272
				8273	u8 port_filter[8][0x20];
				8274
				8275	u8 port_filter_update_en[8][0x20];
				8276	};
				8277
				8278	struct mlx5_ifc_pfcc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8279	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8280	u8 local_port[0x8];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8281	u8 reserved_at_10[0xb];
				8282	u8 ppan_mask_n[0x1];
				8283	u8 minor_stall_mask[0x1];
				8284	u8 critical_stall_mask[0x1];
				8285	u8 reserved_at_1e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8286
				8287	u8 ppan[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8288	u8 reserved_at_24[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8289	u8 prio_mask_tx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8290	u8 reserved_at_30[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8291	u8 prio_mask_rx[0x8];
				8292
				8293	u8 pptx[0x1];
				8294	u8 aptx[0x1];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8295	u8 pptx_mask_n[0x1];
				8296	u8 reserved_at_43[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8297	u8 pfctx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8298	u8 reserved_at_50[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8299
				8300	u8 pprx[0x1];
				8301	u8 aprx[0x1];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8302	u8 pprx_mask_n[0x1];
				8303	u8 reserved_at_63[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8304	u8 pfcrx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8305	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8306
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8307	u8 device_stall_minor_watermark[0x10];
				8308	u8 device_stall_critical_watermark[0x10];
				8309
				8310	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8311	};
				8312
				8313	struct mlx5_ifc_pelc_reg_bits {
				8314	u8 op[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8315	u8 reserved_at_4[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8316	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8317	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8318
				8319	u8 op_admin[0x8];
				8320	u8 op_capability[0x8];
				8321	u8 op_request[0x8];
				8322	u8 op_active[0x8];
				8323
				8324	u8 admin[0x40];
				8325
				8326	u8 capability[0x40];
				8327
				8328	u8 request[0x40];
				8329
				8330	u8 active[0x40];
				8331
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8332	u8 reserved_at_140[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8333	};
				8334
				8335	struct mlx5_ifc_peir_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8336	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8337	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8338	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8339
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8340	u8 reserved_at_20[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8341	u8 error_count[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8342	u8 reserved_at_30[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8344	u8 reserved_at_40[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8345	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8346	u8 reserved_at_50[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8347	u8 error_type[0x8];
				8348	};
				8349
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8350	struct mlx5_ifc_mpegc_reg_bits {
				8351	u8 reserved_at_0[0x30];
				8352	u8 field_select[0x10];
				8353
				8354	u8 tx_overflow_sense[0x1];
				8355	u8 mark_cqe[0x1];
				8356	u8 mark_cnp[0x1];
				8357	u8 reserved_at_43[0x1b];
				8358	u8 tx_lossy_overflow_oper[0x2];
				8359
				8360	u8 reserved_at_60[0x100];
				8361	};
				8362
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8363	struct mlx5_ifc_pcam_enhanced_features_bits {
Talat Batheesh	0af5107	2018-05-17 11:14:18 +0300	[diff] [blame]	8364	u8 reserved_at_0[0x6d];
				8365	u8 rx_icrc_encapsulated_counter[0x1];
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame]	8366	u8 reserved_at_6e[0x4];
				8367	u8 ptys_extended_ethernet[0x1];
				8368	u8 reserved_at_73[0x3];
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	8369	u8 pfcc_mask[0x1];
Shay Agroskin	67daf11	2018-09-30 09:58:08 +0300	[diff] [blame]	8370	u8 reserved_at_77[0x3];
				8371	u8 per_lane_error_counters[0x1];
Gal Pressman	2dba079	2017-06-18 14:56:45 +0300	[diff] [blame]	8372	u8 rx_buffer_fullness_counters[0x1];
Eran Ben Elisha	5b4793f	2017-02-13 14:00:59 +0200	[diff] [blame]	8373	u8 ptys_connector_type[0x1];
				8374	u8 reserved_at_7d[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8375	u8 ppcnt_discard_group[0x1];
				8376	u8 ppcnt_statistical_group[0x1];
				8377	};
				8378
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8379	struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
				8380	u8 port_access_reg_cap_mask_127_to_96[0x20];
				8381	u8 port_access_reg_cap_mask_95_to_64[0x20];
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8382
				8383	u8 port_access_reg_cap_mask_63_to_36[0x1c];
				8384	u8 pplm[0x1];
				8385	u8 port_access_reg_cap_mask_34_to_32[0x3];
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8386
				8387	u8 port_access_reg_cap_mask_31_to_13[0x13];
				8388	u8 pbmc[0x1];
				8389	u8 pptb[0x1];
Eyal Davidovich	75370eb	2018-10-07 15:18:37 +0300	[diff] [blame]	8390	u8 port_access_reg_cap_mask_10_to_09[0x2];
				8391	u8 ppcnt[0x1];
				8392	u8 port_access_reg_cap_mask_07_to_00[0x8];
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8393	};
				8394
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8395	struct mlx5_ifc_pcam_reg_bits {
				8396	u8 reserved_at_0[0x8];
				8397	u8 feature_group[0x8];
				8398	u8 reserved_at_10[0x8];
				8399	u8 access_reg_group[0x8];
				8400
				8401	u8 reserved_at_20[0x20];
				8402
				8403	union {
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8404	struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8405	u8 reserved_at_0[0x80];
				8406	} port_access_reg_cap_mask;
				8407
				8408	u8 reserved_at_c0[0x80];
				8409
				8410	union {
				8411	struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
				8412	u8 reserved_at_0[0x80];
				8413	} feature_cap_mask;
				8414
				8415	u8 reserved_at_1c0[0xc0];
				8416	};
				8417
				8418	struct mlx5_ifc_mcam_enhanced_features_bits {
Aya Levin	4039049	2019-03-29 15:38:03 -0700	[diff] [blame]	8419	u8 reserved_at_0[0x6e];
				8420	u8 pci_status_and_power[0x1];
				8421	u8 reserved_at_6f[0x5];
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8422	u8 mark_tx_action_cnp[0x1];
				8423	u8 mark_tx_action_cqe[0x1];
				8424	u8 dynamic_tx_overflow[0x1];
				8425	u8 reserved_at_77[0x4];
Gal Pressman	5405fa2	2017-06-15 18:29:23 +0300	[diff] [blame]	8426	u8 pcie_outbound_stalled[0x1];
Eran Ben Elisha	efae7f7	2017-05-12 02:47:02 +0300	[diff] [blame]	8427	u8 tx_overflow_buffer_pkt[0x1];
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8428	u8 mtpps_enh_out_per_adj[0x1];
				8429	u8 mtpps_fs[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8430	u8 pcie_performance_group[0x1];
				8431	};
				8432
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8433	struct mlx5_ifc_mcam_access_reg_bits {
				8434	u8 reserved_at_0[0x1c];
				8435	u8 mcda[0x1];
				8436	u8 mcc[0x1];
				8437	u8 mcqi[0x1];
				8438	u8 reserved_at_1f[0x1];
				8439
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8440	u8 regs_95_to_87[0x9];
				8441	u8 mpegc[0x1];
				8442	u8 regs_85_to_68[0x12];
Feras Daoud	eff8ea8	2018-07-16 18:35:30 -0700	[diff] [blame]	8443	u8 tracer_registers[0x4];
				8444
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8445	u8 regs_63_to_32[0x20];
				8446	u8 regs_31_to_0[0x20];
				8447	};
				8448
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8449	struct mlx5_ifc_mcam_reg_bits {
				8450	u8 reserved_at_0[0x8];
				8451	u8 feature_group[0x8];
				8452	u8 reserved_at_10[0x8];
				8453	u8 access_reg_group[0x8];
				8454
				8455	u8 reserved_at_20[0x20];
				8456
				8457	union {
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8458	struct mlx5_ifc_mcam_access_reg_bits access_regs;
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8459	u8 reserved_at_0[0x80];
				8460	} mng_access_reg_cap_mask;
				8461
				8462	u8 reserved_at_c0[0x80];
				8463
				8464	union {
				8465	struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
				8466	u8 reserved_at_0[0x80];
				8467	} mng_feature_cap_mask;
				8468
				8469	u8 reserved_at_1c0[0x80];
				8470	};
				8471
Huy Nguyen	c02762e	2017-07-18 16:03:17 -0500	[diff] [blame]	8472	struct mlx5_ifc_qcam_access_reg_cap_mask {
				8473	u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
				8474	u8 qpdpm[0x1];
				8475	u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
				8476	u8 qdpm[0x1];
				8477	u8 qpts[0x1];
				8478	u8 qcap[0x1];
				8479	u8 qcam_access_reg_cap_mask_0[0x1];
				8480	};
				8481
				8482	struct mlx5_ifc_qcam_qos_feature_cap_mask {
				8483	u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
				8484	u8 qpts_trust_both[0x1];
				8485	};
				8486
				8487	struct mlx5_ifc_qcam_reg_bits {
				8488	u8 reserved_at_0[0x8];
				8489	u8 feature_group[0x8];
				8490	u8 reserved_at_10[0x8];
				8491	u8 access_reg_group[0x8];
				8492	u8 reserved_at_20[0x20];
				8493
				8494	union {
				8495	struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
				8496	u8 reserved_at_0[0x80];
				8497	} qos_access_reg_cap_mask;
				8498
				8499	u8 reserved_at_c0[0x80];
				8500
				8501	union {
				8502	struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
				8503	u8 reserved_at_0[0x80];
				8504	} qos_feature_cap_mask;
				8505
				8506	u8 reserved_at_1c0[0x80];
				8507	};
				8508
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8509	struct mlx5_ifc_pcap_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8510	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8511	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8512	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8513
				8514	u8 port_capability_mask[4][0x20];
				8515	};
				8516
				8517	struct mlx5_ifc_paos_reg_bits {
				8518	u8 swid[0x8];
				8519	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8520	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8521	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8522	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8523	u8 oper_status[0x4];
				8524
				8525	u8 ase[0x1];
				8526	u8 ee[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8527	u8 reserved_at_22[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8528	u8 e[0x2];
				8529
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8530	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8531	};
				8532
				8533	struct mlx5_ifc_pamp_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8534	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8535	u8 opamp_group[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8536	u8 reserved_at_10[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8537	u8 opamp_group_type[0x4];
				8538
				8539	u8 start_index[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8540	u8 reserved_at_30[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8541	u8 num_of_indices[0xc];
				8542
				8543	u8 index_data[18][0x10];
				8544	};
				8545
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8546	struct mlx5_ifc_pcmr_reg_bits {
				8547	u8 reserved_at_0[0x8];
				8548	u8 local_port[0x8];
Eli Britstein	0dcaafc	2019-01-20 22:33:19 +0200	[diff] [blame]	8549	u8 reserved_at_10[0x10];
				8550	u8 entropy_force_cap[0x1];
				8551	u8 entropy_calc_cap[0x1];
				8552	u8 entropy_gre_calc_cap[0x1];
				8553	u8 reserved_at_23[0x1b];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8554	u8 fcs_cap[0x1];
Eli Britstein	0dcaafc	2019-01-20 22:33:19 +0200	[diff] [blame]	8555	u8 reserved_at_3f[0x1];
				8556	u8 entropy_force[0x1];
				8557	u8 entropy_calc[0x1];
				8558	u8 entropy_gre_calc[0x1];
				8559	u8 reserved_at_43[0x1b];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8560	u8 fcs_chk[0x1];
				8561	u8 reserved_at_5f[0x1];
				8562	};
				8563
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8564	struct mlx5_ifc_lane_2_module_mapping_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8565	u8 reserved_at_0[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8566	u8 rx_lane[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8567	u8 reserved_at_8[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8568	u8 tx_lane[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8569	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8570	u8 module[0x8];
				8571	};
				8572
				8573	struct mlx5_ifc_bufferx_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8574	u8 reserved_at_0[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8575	u8 lossy[0x1];
				8576	u8 epsb[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8577	u8 reserved_at_8[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8578	u8 size[0xc];
				8579
				8580	u8 xoff_threshold[0x10];
				8581	u8 xon_threshold[0x10];
				8582	};
				8583
				8584	struct mlx5_ifc_set_node_in_bits {
				8585	u8 node_description[64][0x8];
				8586	};
				8587
				8588	struct mlx5_ifc_register_power_settings_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8589	u8 reserved_at_0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8590	u8 power_settings_level[0x8];
				8591
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8592	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8593	};
				8594
				8595	struct mlx5_ifc_register_host_endianness_bits {
				8596	u8 he[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8597	u8 reserved_at_1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8598
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8599	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8600	};
				8601
				8602	struct mlx5_ifc_umr_pointer_desc_argument_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8603	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8604
				8605	u8 mkey[0x20];
				8606
				8607	u8 addressh_63_32[0x20];
				8608
				8609	u8 addressl_31_0[0x20];
				8610	};
				8611
				8612	struct mlx5_ifc_ud_adrs_vector_bits {
				8613	u8 dc_key[0x40];
				8614
				8615	u8 ext[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8616	u8 reserved_at_41[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8617	u8 destination_qp_dct[0x18];
				8618
				8619	u8 static_rate[0x4];
				8620	u8 sl_eth_prio[0x4];
				8621	u8 fl[0x1];
				8622	u8 mlid[0x7];
				8623	u8 rlid_udp_sport[0x10];
				8624
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8625	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8626
				8627	u8 rmac_47_16[0x20];
				8628
				8629	u8 rmac_15_0[0x10];
				8630	u8 tclass[0x8];
				8631	u8 hop_limit[0x8];
				8632
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8633	u8 reserved_at_e0[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8634	u8 grh[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8635	u8 reserved_at_e2[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8636	u8 src_addr_index[0x8];
				8637	u8 flow_label[0x14];
				8638
				8639	u8 rgid_rip[16][0x8];
				8640	};
				8641
				8642	struct mlx5_ifc_pages_req_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8643	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8644	u8 function_id[0x10];
				8645
				8646	u8 num_pages[0x20];
				8647
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8648	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8649	};
				8650
				8651	struct mlx5_ifc_eqe_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8652	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8653	u8 event_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8654	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8655	u8 event_sub_type[0x8];
				8656
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8657	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8658
				8659	union mlx5_ifc_event_auto_bits event_data;
				8660
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8661	u8 reserved_at_1e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8662	u8 signature[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8663	u8 reserved_at_1f8[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8664	u8 owner[0x1];
				8665	};
				8666
				8667	enum {
				8668	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
				8669	};
				8670
				8671	struct mlx5_ifc_cmd_queue_entry_bits {
				8672	u8 type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8673	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8674
				8675	u8 input_length[0x20];
				8676
				8677	u8 input_mailbox_pointer_63_32[0x20];
				8678
				8679	u8 input_mailbox_pointer_31_9[0x17];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8680	u8 reserved_at_77[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8681
				8682	u8 command_input_inline_data[16][0x8];
				8683
				8684	u8 command_output_inline_data[16][0x8];
				8685
				8686	u8 output_mailbox_pointer_63_32[0x20];
				8687
				8688	u8 output_mailbox_pointer_31_9[0x17];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8689	u8 reserved_at_1b7[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8690
				8691	u8 output_length[0x20];
				8692
				8693	u8 token[0x8];
				8694	u8 signature[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8695	u8 reserved_at_1f0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8696	u8 status[0x7];
				8697	u8 ownership[0x1];
				8698	};
				8699
				8700	struct mlx5_ifc_cmd_out_bits {
				8701	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8702	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8703
				8704	u8 syndrome[0x20];
				8705
				8706	u8 command_output[0x20];
				8707	};
				8708
				8709	struct mlx5_ifc_cmd_in_bits {
				8710	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8711	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8712
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8713	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8714	u8 op_mod[0x10];
				8715
				8716	u8 command[0][0x20];
				8717	};
				8718
				8719	struct mlx5_ifc_cmd_if_box_bits {
				8720	u8 mailbox_data[512][0x8];
				8721
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8722	u8 reserved_at_1000[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8723
				8724	u8 next_pointer_63_32[0x20];
				8725
				8726	u8 next_pointer_31_10[0x16];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8727	u8 reserved_at_11b6[0xa];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8728
				8729	u8 block_number[0x20];
				8730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8731	u8 reserved_at_11e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8732	u8 token[0x8];
				8733	u8 ctrl_signature[0x8];
				8734	u8 signature[0x8];
				8735	};
				8736
				8737	struct mlx5_ifc_mtt_bits {
				8738	u8 ptag_63_32[0x20];
				8739
				8740	u8 ptag_31_8[0x18];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8741	u8 reserved_at_38[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8742	u8 wr_en[0x1];
				8743	u8 rd_en[0x1];
				8744	};
				8745
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	8746	struct mlx5_ifc_query_wol_rol_out_bits {
				8747	u8 status[0x8];
				8748	u8 reserved_at_8[0x18];
				8749
				8750	u8 syndrome[0x20];
				8751
				8752	u8 reserved_at_40[0x10];
				8753	u8 rol_mode[0x8];
				8754	u8 wol_mode[0x8];
				8755
				8756	u8 reserved_at_60[0x20];
				8757	};
				8758
				8759	struct mlx5_ifc_query_wol_rol_in_bits {
				8760	u8 opcode[0x10];
				8761	u8 reserved_at_10[0x10];
				8762
				8763	u8 reserved_at_20[0x10];
				8764	u8 op_mod[0x10];
				8765
				8766	u8 reserved_at_40[0x40];
				8767	};
				8768
				8769	struct mlx5_ifc_set_wol_rol_out_bits {
				8770	u8 status[0x8];
				8771	u8 reserved_at_8[0x18];
				8772
				8773	u8 syndrome[0x20];
				8774
				8775	u8 reserved_at_40[0x40];
				8776	};
				8777
				8778	struct mlx5_ifc_set_wol_rol_in_bits {
				8779	u8 opcode[0x10];
				8780	u8 reserved_at_10[0x10];
				8781
				8782	u8 reserved_at_20[0x10];
				8783	u8 op_mod[0x10];
				8784
				8785	u8 rol_mode_valid[0x1];
				8786	u8 wol_mode_valid[0x1];
				8787	u8 reserved_at_42[0xe];
				8788	u8 rol_mode[0x8];
				8789	u8 wol_mode[0x8];
				8790
				8791	u8 reserved_at_60[0x20];
				8792	};
				8793
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8794	enum {
				8795	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
				8796	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
				8797	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
				8798	};
				8799
				8800	enum {
				8801	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
				8802	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
				8803	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
				8804	};
				8805
				8806	enum {
				8807	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
				8808	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
				8809	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
				8810	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
				8811	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
				8812	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
				8813	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
				8814	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
				8815	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
				8816	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
				8817	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
				8818	};
				8819
				8820	struct mlx5_ifc_initial_seg_bits {
				8821	u8 fw_rev_minor[0x10];
				8822	u8 fw_rev_major[0x10];
				8823
				8824	u8 cmd_interface_rev[0x10];
				8825	u8 fw_rev_subminor[0x10];
				8826
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8827	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8828
				8829	u8 cmdq_phy_addr_63_32[0x20];
				8830
				8831	u8 cmdq_phy_addr_31_12[0x14];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8832	u8 reserved_at_b4[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8833	u8 nic_interface[0x2];
				8834	u8 log_cmdq_size[0x4];
				8835	u8 log_cmdq_stride[0x4];
				8836
				8837	u8 command_doorbell_vector[0x20];
				8838
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8839	u8 reserved_at_e0[0xf00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8840
				8841	u8 initializing[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8842	u8 reserved_at_fe1[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8843	u8 nic_interface_supported[0x3];
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	8844	u8 embedded_cpu[0x1];
				8845	u8 reserved_at_fe9[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8846
				8847	struct mlx5_ifc_health_buffer_bits health_buffer;
				8848
				8849	u8 no_dram_nic_offset[0x20];
				8850
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8851	u8 reserved_at_1220[0x6e40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8852
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8853	u8 reserved_at_8060[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8854	u8 clear_int[0x1];
				8855
				8856	u8 health_syndrome[0x8];
				8857	u8 health_counter[0x18];
				8858
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8859	u8 reserved_at_80a0[0x17fc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8860	};
				8861
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8862	struct mlx5_ifc_mtpps_reg_bits {
				8863	u8 reserved_at_0[0xc];
				8864	u8 cap_number_of_pps_pins[0x4];
				8865	u8 reserved_at_10[0x4];
				8866	u8 cap_max_num_of_pps_in_pins[0x4];
				8867	u8 reserved_at_18[0x4];
				8868	u8 cap_max_num_of_pps_out_pins[0x4];
				8869
				8870	u8 reserved_at_20[0x24];
				8871	u8 cap_pin_3_mode[0x4];
				8872	u8 reserved_at_48[0x4];
				8873	u8 cap_pin_2_mode[0x4];
				8874	u8 reserved_at_50[0x4];
				8875	u8 cap_pin_1_mode[0x4];
				8876	u8 reserved_at_58[0x4];
				8877	u8 cap_pin_0_mode[0x4];
				8878
				8879	u8 reserved_at_60[0x4];
				8880	u8 cap_pin_7_mode[0x4];
				8881	u8 reserved_at_68[0x4];
				8882	u8 cap_pin_6_mode[0x4];
				8883	u8 reserved_at_70[0x4];
				8884	u8 cap_pin_5_mode[0x4];
				8885	u8 reserved_at_78[0x4];
				8886	u8 cap_pin_4_mode[0x4];
				8887
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8888	u8 field_select[0x20];
				8889	u8 reserved_at_a0[0x60];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8890
				8891	u8 enable[0x1];
				8892	u8 reserved_at_101[0xb];
				8893	u8 pattern[0x4];
				8894	u8 reserved_at_110[0x4];
				8895	u8 pin_mode[0x4];
				8896	u8 pin[0x8];
				8897
				8898	u8 reserved_at_120[0x20];
				8899
				8900	u8 time_stamp[0x40];
				8901
				8902	u8 out_pulse_duration[0x10];
				8903	u8 out_periodic_adjustment[0x10];
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8904	u8 enhanced_out_periodic_adjustment[0x20];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8905
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8906	u8 reserved_at_1c0[0x20];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8907	};
				8908
				8909	struct mlx5_ifc_mtppse_reg_bits {
				8910	u8 reserved_at_0[0x18];
				8911	u8 pin[0x8];
				8912	u8 event_arm[0x1];
				8913	u8 reserved_at_21[0x1b];
				8914	u8 event_generation_mode[0x4];
				8915	u8 reserved_at_40[0x40];
				8916	};
				8917
Or Gerlitz	4717628	2017-04-18 13:35:39 +0300	[diff] [blame]	8918	struct mlx5_ifc_mcqi_cap_bits {
				8919	u8 supported_info_bitmask[0x20];
				8920
				8921	u8 component_size[0x20];
				8922
				8923	u8 max_component_size[0x20];
				8924
				8925	u8 log_mcda_word_size[0x4];
				8926	u8 reserved_at_64[0xc];
				8927	u8 mcda_max_write_size[0x10];
				8928
				8929	u8 rd_en[0x1];
				8930	u8 reserved_at_81[0x1];
				8931	u8 match_chip_id[0x1];
				8932	u8 match_psid[0x1];
				8933	u8 check_user_timestamp[0x1];
				8934	u8 match_base_guid_mac[0x1];
				8935	u8 reserved_at_86[0x1a];
				8936	};
				8937
				8938	struct mlx5_ifc_mcqi_reg_bits {
				8939	u8 read_pending_component[0x1];
				8940	u8 reserved_at_1[0xf];
				8941	u8 component_index[0x10];
				8942
				8943	u8 reserved_at_20[0x20];
				8944
				8945	u8 reserved_at_40[0x1b];
				8946	u8 info_type[0x5];
				8947
				8948	u8 info_size[0x20];
				8949
				8950	u8 offset[0x20];
				8951
				8952	u8 reserved_at_a0[0x10];
				8953	u8 data_size[0x10];
				8954
				8955	u8 data[0][0x20];
				8956	};
				8957
				8958	struct mlx5_ifc_mcc_reg_bits {
				8959	u8 reserved_at_0[0x4];
				8960	u8 time_elapsed_since_last_cmd[0xc];
				8961	u8 reserved_at_10[0x8];
				8962	u8 instruction[0x8];
				8963
				8964	u8 reserved_at_20[0x10];
				8965	u8 component_index[0x10];
				8966
				8967	u8 reserved_at_40[0x8];
				8968	u8 update_handle[0x18];
				8969
				8970	u8 handle_owner_type[0x4];
				8971	u8 handle_owner_host_id[0x4];
				8972	u8 reserved_at_68[0x1];
				8973	u8 control_progress[0x7];
				8974	u8 error_code[0x8];
				8975	u8 reserved_at_78[0x4];
				8976	u8 control_state[0x4];
				8977
				8978	u8 component_size[0x20];
				8979
				8980	u8 reserved_at_a0[0x60];
				8981	};
				8982
				8983	struct mlx5_ifc_mcda_reg_bits {
				8984	u8 reserved_at_0[0x8];
				8985	u8 update_handle[0x18];
				8986
				8987	u8 offset[0x20];
				8988
				8989	u8 reserved_at_40[0x10];
				8990	u8 size[0x10];
				8991
				8992	u8 reserved_at_60[0x20];
				8993
				8994	u8 data[0][0x20];
				8995	};
				8996
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8997	union mlx5_ifc_ports_control_registers_document_bits {
				8998	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
				8999	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
				9000	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
				9001	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
				9002	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
				9003	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
				9004	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
				9005	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
				9006	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
				9007	struct mlx5_ifc_pamp_reg_bits pamp_reg;
				9008	struct mlx5_ifc_paos_reg_bits paos_reg;
				9009	struct mlx5_ifc_pcap_reg_bits pcap_reg;
				9010	struct mlx5_ifc_peir_reg_bits peir_reg;
				9011	struct mlx5_ifc_pelc_reg_bits pelc_reg;
				9012	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	9013	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	9014	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
				9015	struct mlx5_ifc_pifr_reg_bits pifr_reg;
				9016	struct mlx5_ifc_pipg_reg_bits pipg_reg;
				9017	struct mlx5_ifc_plbf_reg_bits plbf_reg;
				9018	struct mlx5_ifc_plib_reg_bits plib_reg;
				9019	struct mlx5_ifc_plpc_reg_bits plpc_reg;
				9020	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
				9021	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
				9022	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
				9023	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
				9024	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
				9025	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
				9026	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
				9027	struct mlx5_ifc_ppad_reg_bits ppad_reg;
				9028	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
Aya Levin	4039049	2019-03-29 15:38:03 -0700	[diff] [blame]	9029	struct mlx5_ifc_mpein_reg_bits mpein_reg;
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	9030	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	9031	struct mlx5_ifc_pplm_reg_bits pplm_reg;
				9032	struct mlx5_ifc_pplr_reg_bits pplr_reg;
				9033	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
				9034	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
				9035	struct mlx5_ifc_pspa_reg_bits pspa_reg;
				9036	struct mlx5_ifc_ptas_reg_bits ptas_reg;
				9037	struct mlx5_ifc_ptys_reg_bits ptys_reg;
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9038	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	9039	struct mlx5_ifc_pude_reg_bits pude_reg;
				9040	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
				9041	struct mlx5_ifc_slrg_reg_bits slrg_reg;
				9042	struct mlx5_ifc_sltp_reg_bits sltp_reg;
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	9043	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
				9044	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
Ilan Tayari	a9956d3	2017-04-18 13:10:41 +0300	[diff] [blame]	9045	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	9046	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
				9047	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
Or Gerlitz	4717628	2017-04-18 13:35:39 +0300	[diff] [blame]	9048	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
				9049	struct mlx5_ifc_mcc_reg_bits mcc_reg;
				9050	struct mlx5_ifc_mcda_reg_bits mcda_reg;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9051	u8 reserved_at_0[0x60e0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	9052	};
				9053
				9054	union mlx5_ifc_debug_enhancements_document_bits {
				9055	struct mlx5_ifc_health_buffer_bits health_buffer;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9056	u8 reserved_at_0[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	9057	};
				9058
				9059	union mlx5_ifc_uplink_pci_interface_document_bits {
				9060	struct mlx5_ifc_initial_seg_bits initial_seg;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9061	u8 reserved_at_0[0x20060];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	9062	};
				9063
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9064	struct mlx5_ifc_set_flow_table_root_out_bits {
				9065	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9066	u8 reserved_at_8[0x18];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9067
				9068	u8 syndrome[0x20];
				9069
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9070	u8 reserved_at_40[0x40];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9071	};
				9072
				9073	struct mlx5_ifc_set_flow_table_root_in_bits {
				9074	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9075	u8 reserved_at_10[0x10];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9076
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9077	u8 reserved_at_20[0x10];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9078	u8 op_mod[0x10];
				9079
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9080	u8 other_vport[0x1];
				9081	u8 reserved_at_41[0xf];
				9082	u8 vport_number[0x10];
				9083
				9084	u8 reserved_at_60[0x20];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9085
				9086	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9087	u8 reserved_at_88[0x18];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9088
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9089	u8 reserved_at_a0[0x8];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9090	u8 table_id[0x18];
				9091
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	9092	u8 reserved_at_c0[0x8];
				9093	u8 underlay_qpn[0x18];
				9094	u8 reserved_at_e0[0x120];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9095	};
				9096
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9097	enum {
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	9098	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
				9099	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9100	};
				9101
				9102	struct mlx5_ifc_modify_flow_table_out_bits {
				9103	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9104	u8 reserved_at_8[0x18];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9105
				9106	u8 syndrome[0x20];
				9107
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9108	u8 reserved_at_40[0x40];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9109	};
				9110
				9111	struct mlx5_ifc_modify_flow_table_in_bits {
				9112	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9113	u8 reserved_at_10[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9114
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9115	u8 reserved_at_20[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9116	u8 op_mod[0x10];
				9117
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9118	u8 other_vport[0x1];
				9119	u8 reserved_at_41[0xf];
				9120	u8 vport_number[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9121
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9122	u8 reserved_at_60[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9123	u8 modify_field_select[0x10];
				9124
				9125	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9126	u8 reserved_at_88[0x18];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9127
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9128	u8 reserved_at_a0[0x8];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9129	u8 table_id[0x18];
				9130
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	9131	struct mlx5_ifc_flow_table_context_bits flow_table_context;
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9132	};
				9133
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	9134	struct mlx5_ifc_ets_tcn_config_reg_bits {
				9135	u8 g[0x1];
				9136	u8 b[0x1];
				9137	u8 r[0x1];
				9138	u8 reserved_at_3[0x9];
				9139	u8 group[0x4];
				9140	u8 reserved_at_10[0x9];
				9141	u8 bw_allocation[0x7];
				9142
				9143	u8 reserved_at_20[0xc];
				9144	u8 max_bw_units[0x4];
				9145	u8 reserved_at_30[0x8];
				9146	u8 max_bw_value[0x8];
				9147	};
				9148
				9149	struct mlx5_ifc_ets_global_config_reg_bits {
				9150	u8 reserved_at_0[0x2];
				9151	u8 r[0x1];
				9152	u8 reserved_at_3[0x1d];
				9153
				9154	u8 reserved_at_20[0xc];
				9155	u8 max_bw_units[0x4];
				9156	u8 reserved_at_30[0x8];
				9157	u8 max_bw_value[0x8];
				9158	};
				9159
				9160	struct mlx5_ifc_qetc_reg_bits {
				9161	u8 reserved_at_0[0x8];
				9162	u8 port_number[0x8];
				9163	u8 reserved_at_10[0x30];
				9164
				9165	struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
				9166	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
				9167	};
				9168
Huy Nguyen	415a64a	2017-07-18 16:08:46 -0500	[diff] [blame]	9169	struct mlx5_ifc_qpdpm_dscp_reg_bits {
				9170	u8 e[0x1];
				9171	u8 reserved_at_01[0x0b];
				9172	u8 prio[0x04];
				9173	};
				9174
				9175	struct mlx5_ifc_qpdpm_reg_bits {
				9176	u8 reserved_at_0[0x8];
				9177	u8 local_port[0x8];
				9178	u8 reserved_at_10[0x10];
				9179	struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
				9180	};
				9181
				9182	struct mlx5_ifc_qpts_reg_bits {
				9183	u8 reserved_at_0[0x8];
				9184	u8 local_port[0x8];
				9185	u8 reserved_at_10[0x2d];
				9186	u8 trust_state[0x3];
				9187	};
				9188
Huy Nguyen	50b4a3c	2018-03-02 15:47:01 -0600	[diff] [blame]	9189	struct mlx5_ifc_pptb_reg_bits {
				9190	u8 reserved_at_0[0x2];
				9191	u8 mm[0x2];
				9192	u8 reserved_at_4[0x4];
				9193	u8 local_port[0x8];
				9194	u8 reserved_at_10[0x6];
				9195	u8 cm[0x1];
				9196	u8 um[0x1];
				9197	u8 pm[0x8];
				9198
				9199	u8 prio_x_buff[0x20];
				9200
				9201	u8 pm_msb[0x8];
				9202	u8 reserved_at_48[0x10];
				9203	u8 ctrl_buff[0x4];
				9204	u8 untagged_buff[0x4];
				9205	};
				9206
				9207	struct mlx5_ifc_pbmc_reg_bits {
				9208	u8 reserved_at_0[0x8];
				9209	u8 local_port[0x8];
				9210	u8 reserved_at_10[0x10];
				9211
				9212	u8 xoff_timer_value[0x10];
				9213	u8 xoff_refresh[0x10];
				9214
				9215	u8 reserved_at_40[0x9];
				9216	u8 fullness_threshold[0x7];
				9217	u8 port_buffer_size[0x10];
				9218
				9219	struct mlx5_ifc_bufferx_reg_bits buffer[10];
				9220
				9221	u8 reserved_at_2e0[0x40];
				9222	};
				9223
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	9224	struct mlx5_ifc_qtct_reg_bits {
				9225	u8 reserved_at_0[0x8];
				9226	u8 port_number[0x8];
				9227	u8 reserved_at_10[0xd];
				9228	u8 prio[0x3];
				9229
				9230	u8 reserved_at_20[0x1d];
				9231	u8 tclass[0x3];
				9232	};
				9233
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9234	struct mlx5_ifc_mcia_reg_bits {
				9235	u8 l[0x1];
				9236	u8 reserved_at_1[0x7];
				9237	u8 module[0x8];
				9238	u8 reserved_at_10[0x8];
				9239	u8 status[0x8];
				9240
				9241	u8 i2c_device_address[0x8];
				9242	u8 page_number[0x8];
				9243	u8 device_address[0x10];
				9244
				9245	u8 reserved_at_40[0x10];
				9246	u8 size[0x10];
				9247
				9248	u8 reserved_at_60[0x20];
				9249
				9250	u8 dword_0[0x20];
				9251	u8 dword_1[0x20];
				9252	u8 dword_2[0x20];
				9253	u8 dword_3[0x20];
				9254	u8 dword_4[0x20];
				9255	u8 dword_5[0x20];
				9256	u8 dword_6[0x20];
				9257	u8 dword_7[0x20];
				9258	u8 dword_8[0x20];
				9259	u8 dword_9[0x20];
				9260	u8 dword_10[0x20];
				9261	u8 dword_11[0x20];
				9262	};
				9263
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	9264	struct mlx5_ifc_dcbx_param_bits {
				9265	u8 dcbx_cee_cap[0x1];
				9266	u8 dcbx_ieee_cap[0x1];
				9267	u8 dcbx_standby_cap[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	9268	u8 reserved_at_3[0x5];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	9269	u8 port_number[0x8];
				9270	u8 reserved_at_10[0xa];
				9271	u8 max_application_table_size[6];
				9272	u8 reserved_at_20[0x15];
				9273	u8 version_oper[0x3];
				9274	u8 reserved_at_38[5];
				9275	u8 version_admin[0x3];
				9276	u8 willing_admin[0x1];
				9277	u8 reserved_at_41[0x3];
				9278	u8 pfc_cap_oper[0x4];
				9279	u8 reserved_at_48[0x4];
				9280	u8 pfc_cap_admin[0x4];
				9281	u8 reserved_at_50[0x4];
				9282	u8 num_of_tc_oper[0x4];
				9283	u8 reserved_at_58[0x4];
				9284	u8 num_of_tc_admin[0x4];
				9285	u8 remote_willing[0x1];
				9286	u8 reserved_at_61[3];
				9287	u8 remote_pfc_cap[4];
				9288	u8 reserved_at_68[0x14];
				9289	u8 remote_num_of_tc[0x4];
				9290	u8 reserved_at_80[0x18];
				9291	u8 error[0x8];
				9292	u8 reserved_at_a0[0x160];
				9293	};
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	9294
				9295	struct mlx5_ifc_lagc_bits {
				9296	u8 reserved_at_0[0x1d];
				9297	u8 lag_state[0x3];
				9298
				9299	u8 reserved_at_20[0x14];
				9300	u8 tx_remap_affinity_2[0x4];
				9301	u8 reserved_at_38[0x4];
				9302	u8 tx_remap_affinity_1[0x4];
				9303	};
				9304
				9305	struct mlx5_ifc_create_lag_out_bits {
				9306	u8 status[0x8];
				9307	u8 reserved_at_8[0x18];
				9308
				9309	u8 syndrome[0x20];
				9310
				9311	u8 reserved_at_40[0x40];
				9312	};
				9313
				9314	struct mlx5_ifc_create_lag_in_bits {
				9315	u8 opcode[0x10];
				9316	u8 reserved_at_10[0x10];
				9317
				9318	u8 reserved_at_20[0x10];
				9319	u8 op_mod[0x10];
				9320
				9321	struct mlx5_ifc_lagc_bits ctx;
				9322	};
				9323
				9324	struct mlx5_ifc_modify_lag_out_bits {
				9325	u8 status[0x8];
				9326	u8 reserved_at_8[0x18];
				9327
				9328	u8 syndrome[0x20];
				9329
				9330	u8 reserved_at_40[0x40];
				9331	};
				9332
				9333	struct mlx5_ifc_modify_lag_in_bits {
				9334	u8 opcode[0x10];
				9335	u8 reserved_at_10[0x10];
				9336
				9337	u8 reserved_at_20[0x10];
				9338	u8 op_mod[0x10];
				9339
				9340	u8 reserved_at_40[0x20];
				9341	u8 field_select[0x20];
				9342
				9343	struct mlx5_ifc_lagc_bits ctx;
				9344	};
				9345
				9346	struct mlx5_ifc_query_lag_out_bits {
				9347	u8 status[0x8];
				9348	u8 reserved_at_8[0x18];
				9349
				9350	u8 syndrome[0x20];
				9351
				9352	u8 reserved_at_40[0x40];
				9353
				9354	struct mlx5_ifc_lagc_bits ctx;
				9355	};
				9356
				9357	struct mlx5_ifc_query_lag_in_bits {
				9358	u8 opcode[0x10];
				9359	u8 reserved_at_10[0x10];
				9360
				9361	u8 reserved_at_20[0x10];
				9362	u8 op_mod[0x10];
				9363
				9364	u8 reserved_at_40[0x40];
				9365	};
				9366
				9367	struct mlx5_ifc_destroy_lag_out_bits {
				9368	u8 status[0x8];
				9369	u8 reserved_at_8[0x18];
				9370
				9371	u8 syndrome[0x20];
				9372
				9373	u8 reserved_at_40[0x40];
				9374	};
				9375
				9376	struct mlx5_ifc_destroy_lag_in_bits {
				9377	u8 opcode[0x10];
				9378	u8 reserved_at_10[0x10];
				9379
				9380	u8 reserved_at_20[0x10];
				9381	u8 op_mod[0x10];
				9382
				9383	u8 reserved_at_40[0x40];
				9384	};
				9385
				9386	struct mlx5_ifc_create_vport_lag_out_bits {
				9387	u8 status[0x8];
				9388	u8 reserved_at_8[0x18];
				9389
				9390	u8 syndrome[0x20];
				9391
				9392	u8 reserved_at_40[0x40];
				9393	};
				9394
				9395	struct mlx5_ifc_create_vport_lag_in_bits {
				9396	u8 opcode[0x10];
				9397	u8 reserved_at_10[0x10];
				9398
				9399	u8 reserved_at_20[0x10];
				9400	u8 op_mod[0x10];
				9401
				9402	u8 reserved_at_40[0x40];
				9403	};
				9404
				9405	struct mlx5_ifc_destroy_vport_lag_out_bits {
				9406	u8 status[0x8];
				9407	u8 reserved_at_8[0x18];
				9408
				9409	u8 syndrome[0x20];
				9410
				9411	u8 reserved_at_40[0x40];
				9412	};
				9413
				9414	struct mlx5_ifc_destroy_vport_lag_in_bits {
				9415	u8 opcode[0x10];
				9416	u8 reserved_at_10[0x10];
				9417
				9418	u8 reserved_at_20[0x10];
				9419	u8 op_mod[0x10];
				9420
				9421	u8 reserved_at_40[0x40];
				9422	};
				9423
Ariel Levkovich	24da001	2018-04-05 18:53:27 +0300	[diff] [blame]	9424	struct mlx5_ifc_alloc_memic_in_bits {
				9425	u8 opcode[0x10];
				9426	u8 reserved_at_10[0x10];
				9427
				9428	u8 reserved_at_20[0x10];
				9429	u8 op_mod[0x10];
				9430
				9431	u8 reserved_at_30[0x20];
				9432
				9433	u8 reserved_at_40[0x18];
				9434	u8 log_memic_addr_alignment[0x8];
				9435
				9436	u8 range_start_addr[0x40];
				9437
				9438	u8 range_size[0x20];
				9439
				9440	u8 memic_size[0x20];
				9441	};
				9442
				9443	struct mlx5_ifc_alloc_memic_out_bits {
				9444	u8 status[0x8];
				9445	u8 reserved_at_8[0x18];
				9446
				9447	u8 syndrome[0x20];
				9448
				9449	u8 memic_start_addr[0x40];
				9450	};
				9451
				9452	struct mlx5_ifc_dealloc_memic_in_bits {
				9453	u8 opcode[0x10];
				9454	u8 reserved_at_10[0x10];
				9455
				9456	u8 reserved_at_20[0x10];
				9457	u8 op_mod[0x10];
				9458
				9459	u8 reserved_at_40[0x40];
				9460
				9461	u8 memic_start_addr[0x40];
				9462
				9463	u8 memic_size[0x20];
				9464
				9465	u8 reserved_at_e0[0x20];
				9466	};
				9467
				9468	struct mlx5_ifc_dealloc_memic_out_bits {
				9469	u8 status[0x8];
				9470	u8 reserved_at_8[0x18];
				9471
				9472	u8 syndrome[0x20];
				9473
				9474	u8 reserved_at_40[0x40];
				9475	};
				9476
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9477	struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
				9478	u8 opcode[0x10];
				9479	u8 uid[0x10];
				9480
				9481	u8 reserved_at_20[0x10];
				9482	u8 obj_type[0x10];
				9483
				9484	u8 obj_id[0x20];
				9485
				9486	u8 reserved_at_60[0x20];
				9487	};
				9488
				9489	struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
				9490	u8 status[0x8];
				9491	u8 reserved_at_8[0x18];
				9492
				9493	u8 syndrome[0x20];
				9494
				9495	u8 obj_id[0x20];
				9496
				9497	u8 reserved_at_60[0x20];
				9498	};
				9499
				9500	struct mlx5_ifc_umem_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9501	u8 reserved_at_0[0x80];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9502
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9503	u8 reserved_at_80[0x1b];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9504	u8 log_page_size[0x5];
				9505
				9506	u8 page_offset[0x20];
				9507
				9508	u8 num_of_mtt[0x40];
				9509
				9510	struct mlx5_ifc_mtt_bits mtt[0];
				9511	};
				9512
				9513	struct mlx5_ifc_uctx_bits {
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	9514	u8 cap[0x20];
				9515
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9516	u8 reserved_at_20[0x160];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9517	};
				9518
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	9519	struct mlx5_ifc_sw_icm_bits {
				9520	u8 modify_field_select[0x40];
				9521
				9522	u8 reserved_at_40[0x18];
				9523	u8 log_sw_icm_size[0x8];
				9524
				9525	u8 reserved_at_60[0x20];
				9526
				9527	u8 sw_icm_start_addr[0x40];
				9528
				9529	u8 reserved_at_c0[0x140];
				9530	};
				9531
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9532	struct mlx5_ifc_create_umem_in_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9533	u8 opcode[0x10];
				9534	u8 uid[0x10];
				9535
				9536	u8 reserved_at_20[0x10];
				9537	u8 op_mod[0x10];
				9538
				9539	u8 reserved_at_40[0x40];
				9540
				9541	struct mlx5_ifc_umem_bits umem;
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9542	};
				9543
				9544	struct mlx5_ifc_create_uctx_in_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9545	u8 opcode[0x10];
				9546	u8 reserved_at_10[0x10];
				9547
				9548	u8 reserved_at_20[0x10];
				9549	u8 op_mod[0x10];
				9550
				9551	u8 reserved_at_40[0x40];
				9552
				9553	struct mlx5_ifc_uctx_bits uctx;
				9554	};
				9555
				9556	struct mlx5_ifc_destroy_uctx_in_bits {
				9557	u8 opcode[0x10];
				9558	u8 reserved_at_10[0x10];
				9559
				9560	u8 reserved_at_20[0x10];
				9561	u8 op_mod[0x10];
				9562
				9563	u8 reserved_at_40[0x10];
				9564	u8 uid[0x10];
				9565
				9566	u8 reserved_at_60[0x20];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9567	};
				9568
Ariel Levkovich	9fba2b9	2019-03-31 19:44:43 +0300	[diff] [blame]	9569	struct mlx5_ifc_create_sw_icm_in_bits {
				9570	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
				9571	struct mlx5_ifc_sw_icm_bits sw_icm;
				9572	};
				9573
Feras Daoud	eff8ea8	2018-07-16 18:35:30 -0700	[diff] [blame]	9574	struct mlx5_ifc_mtrc_string_db_param_bits {
				9575	u8 string_db_base_address[0x20];
				9576
				9577	u8 reserved_at_20[0x8];
				9578	u8 string_db_size[0x18];
				9579	};
				9580
				9581	struct mlx5_ifc_mtrc_cap_bits {
				9582	u8 trace_owner[0x1];
				9583	u8 trace_to_memory[0x1];
				9584	u8 reserved_at_2[0x4];
				9585	u8 trc_ver[0x2];
				9586	u8 reserved_at_8[0x14];
				9587	u8 num_string_db[0x4];
				9588
				9589	u8 first_string_trace[0x8];
				9590	u8 num_string_trace[0x8];
				9591	u8 reserved_at_30[0x28];
				9592
				9593	u8 log_max_trace_buffer_size[0x8];
				9594
				9595	u8 reserved_at_60[0x20];
				9596
				9597	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
				9598
				9599	u8 reserved_at_280[0x180];
				9600	};
				9601
				9602	struct mlx5_ifc_mtrc_conf_bits {
				9603	u8 reserved_at_0[0x1c];
				9604	u8 trace_mode[0x4];
				9605	u8 reserved_at_20[0x18];
				9606	u8 log_trace_buffer_size[0x8];
				9607	u8 trace_mkey[0x20];
				9608	u8 reserved_at_60[0x3a0];
				9609	};
				9610
				9611	struct mlx5_ifc_mtrc_stdb_bits {
				9612	u8 string_db_index[0x4];
				9613	u8 reserved_at_4[0x4];
				9614	u8 read_size[0x18];
				9615	u8 start_offset[0x20];
				9616	u8 string_db_data[0];
				9617	};
				9618
				9619	struct mlx5_ifc_mtrc_ctrl_bits {
				9620	u8 trace_status[0x2];
				9621	u8 reserved_at_2[0x2];
				9622	u8 arm_event[0x1];
				9623	u8 reserved_at_5[0xb];
				9624	u8 modify_field_select[0x10];
				9625	u8 reserved_at_20[0x2b];
				9626	u8 current_timestamp52_32[0x15];
				9627	u8 current_timestamp31_0[0x20];
				9628	u8 reserved_at_80[0x180];
				9629	};
				9630
Bodong Wang	c3a4e9f	2019-02-12 22:55:37 -0800	[diff] [blame]	9631	struct mlx5_ifc_host_params_context_bits {
				9632	u8 host_number[0x8];
				9633	u8 reserved_at_8[0x8];
				9634	u8 host_num_of_vfs[0x10];
				9635
				9636	u8 reserved_at_20[0x10];
				9637	u8 host_pci_bus[0x10];
				9638
				9639	u8 reserved_at_40[0x10];
				9640	u8 host_pci_device[0x10];
				9641
				9642	u8 reserved_at_60[0x10];
				9643	u8 host_pci_function[0x10];
				9644
				9645	u8 reserved_at_80[0x180];
				9646	};
				9647
				9648	struct mlx5_ifc_query_host_params_in_bits {
				9649	u8 opcode[0x10];
				9650	u8 reserved_at_10[0x10];
				9651
				9652	u8 reserved_at_20[0x10];
				9653	u8 op_mod[0x10];
				9654
				9655	u8 reserved_at_40[0x40];
				9656	};
				9657
				9658	struct mlx5_ifc_query_host_params_out_bits {
				9659	u8 status[0x8];
				9660	u8 reserved_at_8[0x18];
				9661
				9662	u8 syndrome[0x20];
				9663
				9664	u8 reserved_at_40[0x40];
				9665
				9666	struct mlx5_ifc_host_params_context_bits host_params_context;
				9667
				9668	u8 reserved_at_280[0x180];
				9669	};
				9670
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	9671	#endif /* MLX5_IFC_H */