Blame - include/linux/mlx5/mlx5_ifc.h - SHIFTPHONES/kernel/common

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Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	1	/*
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2	* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	3	*
				4	* This software is available to you under a choice of one of two
				5	* licenses. You may choose to be licensed under the terms of the GNU
				6	* General Public License (GPL) Version 2, available from the file
				7	* COPYING in the main directory of this source tree, or the
				8	* OpenIB.org BSD license below:
				9	*
				10	* Redistribution and use in source and binary forms, with or
				11	* without modification, are permitted provided that the following
				12	* conditions are met:
				13	*
				14	* - Redistributions of source code must retain the above
				15	* copyright notice, this list of conditions and the following
				16	* disclaimer.
				17	*
				18	* - Redistributions in binary form must reproduce the above
				19	* copyright notice, this list of conditions and the following
				20	* disclaimer in the documentation and/or other materials
				21	* provided with the distribution.
				22	*
				23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
				24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
				25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
				26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
				27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
				28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
				29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
				30	* SOFTWARE.
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	31	*/
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	32	#ifndef MLX5_IFC_H
				33	#define MLX5_IFC_H
				34
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	35	#include "mlx5_ifc_fpga.h"
				36
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	37	enum {
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	38	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
				39	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
				40	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
				41	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
				42	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
				43	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
				44	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
				45	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
				46	MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
				47	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
				48	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
				49	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
				50	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
				51	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
				52	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
				53	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
				54	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
				55	MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
				56	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
				57	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
				58	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
				59	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
				60	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	61	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
				62	MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
Ilan Tayari	1f0cf89	2018-05-30 10:59:50 -0700	[diff] [blame]	63	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	64	};
				65
				66	enum {
				67	MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
				68	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
				69	MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
				70	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
				71	};
				72
				73	enum {
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	74	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
Moni Shoua	46861e3	2019-01-22 08:48:51 +0200	[diff] [blame]	75	MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	76	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
				77	};
				78
				79	enum {
Leon Romanovsky	2acc795	2018-12-06 14:40:11 +0200	[diff] [blame]	80	MLX5_SHARED_RESOURCE_UID = 0xffff,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	81	};
				82
				83	enum {
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	84	MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
				85	MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
				86	MLX5_CMD_OP_INIT_HCA = 0x102,
				87	MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
				88	MLX5_CMD_OP_ENABLE_HCA = 0x104,
				89	MLX5_CMD_OP_DISABLE_HCA = 0x105,
				90	MLX5_CMD_OP_QUERY_PAGES = 0x107,
				91	MLX5_CMD_OP_MANAGE_PAGES = 0x108,
				92	MLX5_CMD_OP_SET_HCA_CAP = 0x109,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	93	MLX5_CMD_OP_QUERY_ISSI = 0x10a,
				94	MLX5_CMD_OP_SET_ISSI = 0x10b,
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	95	MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	96	MLX5_CMD_OP_CREATE_MKEY = 0x200,
				97	MLX5_CMD_OP_QUERY_MKEY = 0x201,
				98	MLX5_CMD_OP_DESTROY_MKEY = 0x202,
				99	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
				100	MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
Ariel Levkovich	24da001	2018-04-05 18:53:27 +0300	[diff] [blame]	101	MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
				102	MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	103	MLX5_CMD_OP_CREATE_EQ = 0x301,
				104	MLX5_CMD_OP_DESTROY_EQ = 0x302,
				105	MLX5_CMD_OP_QUERY_EQ = 0x303,
				106	MLX5_CMD_OP_GEN_EQE = 0x304,
				107	MLX5_CMD_OP_CREATE_CQ = 0x400,
				108	MLX5_CMD_OP_DESTROY_CQ = 0x401,
				109	MLX5_CMD_OP_QUERY_CQ = 0x402,
				110	MLX5_CMD_OP_MODIFY_CQ = 0x403,
				111	MLX5_CMD_OP_CREATE_QP = 0x500,
				112	MLX5_CMD_OP_DESTROY_QP = 0x501,
				113	MLX5_CMD_OP_RST2INIT_QP = 0x502,
				114	MLX5_CMD_OP_INIT2RTR_QP = 0x503,
				115	MLX5_CMD_OP_RTR2RTS_QP = 0x504,
				116	MLX5_CMD_OP_RTS2RTS_QP = 0x505,
				117	MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
				118	MLX5_CMD_OP_2ERR_QP = 0x507,
				119	MLX5_CMD_OP_2RST_QP = 0x50a,
				120	MLX5_CMD_OP_QUERY_QP = 0x50b,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	121	MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	122	MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
				123	MLX5_CMD_OP_CREATE_PSV = 0x600,
				124	MLX5_CMD_OP_DESTROY_PSV = 0x601,
				125	MLX5_CMD_OP_CREATE_SRQ = 0x700,
				126	MLX5_CMD_OP_DESTROY_SRQ = 0x701,
				127	MLX5_CMD_OP_QUERY_SRQ = 0x702,
				128	MLX5_CMD_OP_ARM_RQ = 0x703,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	129	MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
				130	MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
				131	MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
				132	MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	133	MLX5_CMD_OP_CREATE_DCT = 0x710,
				134	MLX5_CMD_OP_DESTROY_DCT = 0x711,
				135	MLX5_CMD_OP_DRAIN_DCT = 0x712,
				136	MLX5_CMD_OP_QUERY_DCT = 0x713,
				137	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	138	MLX5_CMD_OP_CREATE_XRQ = 0x717,
				139	MLX5_CMD_OP_DESTROY_XRQ = 0x718,
				140	MLX5_CMD_OP_QUERY_XRQ = 0x719,
				141	MLX5_CMD_OP_ARM_XRQ = 0x71a,
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	142	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
				143	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
				144	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
Bodong Wang	c3a4e9f	2019-02-12 22:55:37 -0800	[diff] [blame]	145	MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	146	MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
				147	MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
				148	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
				149	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
				150	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
				151	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	152	MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	153	MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	154	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
				155	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
				156	MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
				157	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	158	MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	159	MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
				160	MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
				161	MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
				162	MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	163	MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
				164	MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	165	MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	166	MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	167	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
				168	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
				169	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
				170	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
				171	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
				172	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	173	MLX5_CMD_OP_ALLOC_PD = 0x800,
				174	MLX5_CMD_OP_DEALLOC_PD = 0x801,
				175	MLX5_CMD_OP_ALLOC_UAR = 0x802,
				176	MLX5_CMD_OP_DEALLOC_UAR = 0x803,
				177	MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
				178	MLX5_CMD_OP_ACCESS_REG = 0x805,
				179	MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
Saeed Mahameed	20bb566	2016-07-17 02:01:45 +0300	[diff] [blame]	180	MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	181	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
				182	MLX5_CMD_OP_MAD_IFC = 0x50d,
				183	MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
				184	MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
				185	MLX5_CMD_OP_NOP = 0x80d,
				186	MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
				187	MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	188	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
				189	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
				190	MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
				191	MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
				192	MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
				193	MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
				194	MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
				195	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
				196	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
				197	MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
				198	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
				199	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	200	MLX5_CMD_OP_SET_WOL_ROL = 0x830,
				201	MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	202	MLX5_CMD_OP_CREATE_LAG = 0x840,
				203	MLX5_CMD_OP_MODIFY_LAG = 0x841,
				204	MLX5_CMD_OP_QUERY_LAG = 0x842,
				205	MLX5_CMD_OP_DESTROY_LAG = 0x843,
				206	MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
				207	MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	208	MLX5_CMD_OP_CREATE_TIR = 0x900,
				209	MLX5_CMD_OP_MODIFY_TIR = 0x901,
				210	MLX5_CMD_OP_DESTROY_TIR = 0x902,
				211	MLX5_CMD_OP_QUERY_TIR = 0x903,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	212	MLX5_CMD_OP_CREATE_SQ = 0x904,
				213	MLX5_CMD_OP_MODIFY_SQ = 0x905,
				214	MLX5_CMD_OP_DESTROY_SQ = 0x906,
				215	MLX5_CMD_OP_QUERY_SQ = 0x907,
				216	MLX5_CMD_OP_CREATE_RQ = 0x908,
				217	MLX5_CMD_OP_MODIFY_RQ = 0x909,
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	218	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	219	MLX5_CMD_OP_DESTROY_RQ = 0x90a,
				220	MLX5_CMD_OP_QUERY_RQ = 0x90b,
				221	MLX5_CMD_OP_CREATE_RMP = 0x90c,
				222	MLX5_CMD_OP_MODIFY_RMP = 0x90d,
				223	MLX5_CMD_OP_DESTROY_RMP = 0x90e,
				224	MLX5_CMD_OP_QUERY_RMP = 0x90f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	225	MLX5_CMD_OP_CREATE_TIS = 0x912,
				226	MLX5_CMD_OP_MODIFY_TIS = 0x913,
				227	MLX5_CMD_OP_DESTROY_TIS = 0x914,
				228	MLX5_CMD_OP_QUERY_TIS = 0x915,
				229	MLX5_CMD_OP_CREATE_RQT = 0x916,
				230	MLX5_CMD_OP_MODIFY_RQT = 0x917,
				231	MLX5_CMD_OP_DESTROY_RQT = 0x918,
				232	MLX5_CMD_OP_QUERY_RQT = 0x919,
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	233	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	234	MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
				235	MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
				236	MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
				237	MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
				238	MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
				239	MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
				240	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
				241	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	242	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	243	MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
				244	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
				245	MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
Shahar Klein	86d56a1	2016-06-10 00:07:30 +0300	[diff] [blame]	246	MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	247	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
				248	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	249	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	250	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
				251	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
Yishai Hadas	e662e14	2018-06-17 13:00:02 +0300	[diff] [blame]	252	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
Ilan Tayari	6062118	2017-03-27 14:52:09 +0300	[diff] [blame]	253	MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
				254	MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
				255	MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
				256	MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
				257	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	258	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
Yishai Hadas	e662e14	2018-06-17 13:00:02 +0300	[diff] [blame]	259	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
				260	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	261	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	262	MLX5_CMD_OP_CREATE_UCTX = 0xa04,
				263	MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
				264	MLX5_CMD_OP_CREATE_UMEM = 0xa08,
				265	MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
Shahar Klein	86d56a1	2016-06-10 00:07:30 +0300	[diff] [blame]	266	MLX5_CMD_OP_MAX
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	267	};
				268
Yishai Hadas	719598c	2018-11-26 08:28:37 +0200	[diff] [blame]	269	/* Valid range for general commands that don't work over an object */
				270	enum {
				271	MLX5_CMD_OP_GENERAL_START = 0xb00,
				272	MLX5_CMD_OP_GENERAL_END = 0xd00,
				273	};
				274
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	275	struct mlx5_ifc_flow_table_fields_supported_bits {
				276	u8 outer_dmac[0x1];
				277	u8 outer_smac[0x1];
				278	u8 outer_ether_type[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	279	u8 outer_ip_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	280	u8 outer_first_prio[0x1];
				281	u8 outer_first_cfi[0x1];
				282	u8 outer_first_vid[0x1];
Or Gerlitz	a8ade55	2017-06-07 17:49:56 +0300	[diff] [blame]	283	u8 outer_ipv4_ttl[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	284	u8 outer_second_prio[0x1];
				285	u8 outer_second_cfi[0x1];
				286	u8 outer_second_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	287	u8 reserved_at_b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	288	u8 outer_sip[0x1];
				289	u8 outer_dip[0x1];
				290	u8 outer_frag[0x1];
				291	u8 outer_ip_protocol[0x1];
				292	u8 outer_ip_ecn[0x1];
				293	u8 outer_ip_dscp[0x1];
				294	u8 outer_udp_sport[0x1];
				295	u8 outer_udp_dport[0x1];
				296	u8 outer_tcp_sport[0x1];
				297	u8 outer_tcp_dport[0x1];
				298	u8 outer_tcp_flags[0x1];
				299	u8 outer_gre_protocol[0x1];
				300	u8 outer_gre_key[0x1];
				301	u8 outer_vxlan_vni[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	302	u8 reserved_at_1a[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	303	u8 source_eswitch_port[0x1];
				304
				305	u8 inner_dmac[0x1];
				306	u8 inner_smac[0x1];
				307	u8 inner_ether_type[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	308	u8 inner_ip_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	309	u8 inner_first_prio[0x1];
				310	u8 inner_first_cfi[0x1];
				311	u8 inner_first_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	312	u8 reserved_at_27[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	313	u8 inner_second_prio[0x1];
				314	u8 inner_second_cfi[0x1];
				315	u8 inner_second_vid[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	316	u8 reserved_at_2b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	317	u8 inner_sip[0x1];
				318	u8 inner_dip[0x1];
				319	u8 inner_frag[0x1];
				320	u8 inner_ip_protocol[0x1];
				321	u8 inner_ip_ecn[0x1];
				322	u8 inner_ip_dscp[0x1];
				323	u8 inner_udp_sport[0x1];
				324	u8 inner_udp_dport[0x1];
				325	u8 inner_tcp_sport[0x1];
				326	u8 inner_tcp_dport[0x1];
				327	u8 inner_tcp_flags[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	328	u8 reserved_at_37[0x9];
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	329
				330	u8 reserved_at_40[0x5];
				331	u8 outer_first_mpls_over_udp[0x4];
				332	u8 outer_first_mpls_over_gre[0x4];
				333	u8 inner_first_mpls[0x4];
				334	u8 outer_first_mpls[0x4];
				335	u8 reserved_at_55[0x2];
Boris Pismenny	3346c48	2017-08-20 15:13:08 +0300	[diff] [blame]	336	u8 outer_esp_spi[0x1];
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	337	u8 reserved_at_58[0x2];
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	338	u8 bth_dst_qp[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	339
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	340	u8 reserved_at_5b[0x25];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	341	};
				342
				343	struct mlx5_ifc_flow_table_prop_layout_bits {
				344	u8 ft_support[0x1];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	345	u8 reserved_at_1[0x1];
				346	u8 flow_counter[0x1];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	347	u8 flow_modify_en[0x1];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	348	u8 modify_root[0x1];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	349	u8 identified_miss_table_mode[0x1];
				350	u8 flow_table_modify[0x1];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	351	u8 reformat[0x1];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	352	u8 decap[0x1];
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	353	u8 reserved_at_9[0x1];
				354	u8 pop_vlan[0x1];
				355	u8 push_vlan[0x1];
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	356	u8 reserved_at_c[0x1];
				357	u8 pop_vlan_2[0x1];
				358	u8 push_vlan_2[0x1];
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	359	u8 reformat_and_vlan_action[0x1];
				360	u8 reserved_at_10[0x2];
				361	u8 reformat_l3_tunnel_to_l2[0x1];
				362	u8 reformat_l2_to_l3_tunnel[0x1];
				363	u8 reformat_and_modify_action[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	364	u8 reserved_at_15[0xb];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	365	u8 reserved_at_20[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	366	u8 log_max_ft_size[0x6];
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	367	u8 log_max_modify_header_context[0x8];
				368	u8 max_modify_header_actions[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	369	u8 max_ft_level[0x8];
				370
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	371	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	372
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	373	u8 reserved_at_60[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	374	u8 log_max_ft_num[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	375
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	376	u8 reserved_at_80[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	377	u8 log_max_destination[0x8];
				378
Raed Salem	16f1c5b	2017-07-30 11:02:51 +0300	[diff] [blame]	379	u8 log_max_flow_counter[0x8];
				380	u8 reserved_at_a8[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	381	u8 log_max_flow[0x8];
				382
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	383	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	384
				385	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
				386
				387	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
				388	};
				389
				390	struct mlx5_ifc_odp_per_transport_service_cap_bits {
				391	u8 send[0x1];
				392	u8 receive[0x1];
				393	u8 write[0x1];
				394	u8 read[0x1];
Artemy Kovalyov	17d2f88	2017-01-02 11:37:47 +0200	[diff] [blame]	395	u8 atomic[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	396	u8 srq_receive[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	397	u8 reserved_at_6[0x1a];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	398	};
				399
				400	struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
				401	u8 smac_47_16[0x20];
				402
				403	u8 smac_15_0[0x10];
				404	u8 ethertype[0x10];
				405
				406	u8 dmac_47_16[0x20];
				407
				408	u8 dmac_15_0[0x10];
				409	u8 first_prio[0x3];
				410	u8 first_cfi[0x1];
				411	u8 first_vid[0xc];
				412
				413	u8 ip_protocol[0x8];
				414	u8 ip_dscp[0x6];
				415	u8 ip_ecn[0x2];
Mohamad Haj Yahia	1054336	2016-10-09 16:25:43 +0300	[diff] [blame]	416	u8 cvlan_tag[0x1];
				417	u8 svlan_tag[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	418	u8 frag[0x1];
Ariel Levkovich	19cc752	2017-04-03 13:11:03 +0300	[diff] [blame]	419	u8 ip_version[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	420	u8 tcp_flags[0x9];
				421
				422	u8 tcp_sport[0x10];
				423	u8 tcp_dport[0x10];
				424
Or Gerlitz	a8ade55	2017-06-07 17:49:56 +0300	[diff] [blame]	425	u8 reserved_at_c0[0x18];
				426	u8 ttl_hoplimit[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	427
				428	u8 udp_sport[0x10];
				429	u8 udp_dport[0x10];
				430
Maor Gottlieb	b4d1f03	2016-01-11 10:26:05 +0200	[diff] [blame]	431	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	432
Maor Gottlieb	b4d1f03	2016-01-11 10:26:05 +0200	[diff] [blame]	433	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	434	};
				435
Oz Shlomo	5886a96	2018-12-10 13:15:13 -0800	[diff] [blame]	436	struct mlx5_ifc_nvgre_key_bits {
				437	u8 hi[0x18];
				438	u8 lo[0x8];
				439	};
				440
				441	union mlx5_ifc_gre_key_bits {
				442	struct mlx5_ifc_nvgre_key_bits nvgre;
				443	u8 key[0x20];
				444	};
				445
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	446	struct mlx5_ifc_fte_match_set_misc_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	447	u8 reserved_at_0[0x8];
				448	u8 source_sqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	449
Shahar Klein	3e99df8	2018-03-18 09:02:06 +0200	[diff] [blame]	450	u8 source_eswitch_owner_vhca_id[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	451	u8 source_port[0x10];
				452
				453	u8 outer_second_prio[0x3];
				454	u8 outer_second_cfi[0x1];
				455	u8 outer_second_vid[0xc];
				456	u8 inner_second_prio[0x3];
				457	u8 inner_second_cfi[0x1];
				458	u8 inner_second_vid[0xc];
				459
Mohamad Haj Yahia	1054336	2016-10-09 16:25:43 +0300	[diff] [blame]	460	u8 outer_second_cvlan_tag[0x1];
				461	u8 inner_second_cvlan_tag[0x1];
				462	u8 outer_second_svlan_tag[0x1];
				463	u8 inner_second_svlan_tag[0x1];
				464	u8 reserved_at_64[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	465	u8 gre_protocol[0x10];
				466
Oz Shlomo	5886a96	2018-12-10 13:15:13 -0800	[diff] [blame]	467	union mlx5_ifc_gre_key_bits gre_key;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	468
				469	u8 vxlan_vni[0x18];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	470	u8 reserved_at_b8[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	471
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	472	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	473
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	474	u8 reserved_at_e0[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	475	u8 outer_ipv6_flow_label[0x14];
				476
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	477	u8 reserved_at_100[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	478	u8 inner_ipv6_flow_label[0x14];
				479
Yishai Hadas	a550ddf	2017-08-17 15:52:33 +0300	[diff] [blame]	480	u8 reserved_at_120[0x28];
				481	u8 bth_dst_qp[0x18];
Boris Pismenny	3346c48	2017-08-20 15:13:08 +0300	[diff] [blame]	482	u8 reserved_at_160[0x20];
				483	u8 outer_esp_spi[0x20];
				484	u8 reserved_at_1a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	485	};
				486
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	487	struct mlx5_ifc_fte_match_mpls_bits {
				488	u8 mpls_label[0x14];
				489	u8 mpls_exp[0x3];
				490	u8 mpls_s_bos[0x1];
				491	u8 mpls_ttl[0x8];
				492	};
				493
				494	struct mlx5_ifc_fte_match_set_misc2_bits {
				495	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
				496
				497	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
				498
				499	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
				500
				501	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
				502
				503	u8 reserved_at_80[0x100];
				504
				505	u8 metadata_reg_a[0x20];
				506
				507	u8 reserved_at_1a0[0x60];
				508	};
				509
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	510	struct mlx5_ifc_cmd_pas_bits {
				511	u8 pa_h[0x20];
				512
				513	u8 pa_l[0x14];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	514	u8 reserved_at_34[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	515	};
				516
				517	struct mlx5_ifc_uint64_bits {
				518	u8 hi[0x20];
				519
				520	u8 lo[0x20];
				521	};
				522
				523	enum {
				524	MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
				525	MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
				526	MLX5_ADS_STAT_RATE_10GBPS = 0x8,
				527	MLX5_ADS_STAT_RATE_30GBPS = 0x9,
				528	MLX5_ADS_STAT_RATE_5GBPS = 0xa,
				529	MLX5_ADS_STAT_RATE_20GBPS = 0xb,
				530	MLX5_ADS_STAT_RATE_40GBPS = 0xc,
				531	MLX5_ADS_STAT_RATE_60GBPS = 0xd,
				532	MLX5_ADS_STAT_RATE_80GBPS = 0xe,
				533	MLX5_ADS_STAT_RATE_120GBPS = 0xf,
				534	};
				535
				536	struct mlx5_ifc_ads_bits {
				537	u8 fl[0x1];
				538	u8 free_ar[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	539	u8 reserved_at_2[0xe];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	540	u8 pkey_index[0x10];
				541
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	542	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	543	u8 grh[0x1];
				544	u8 mlid[0x7];
				545	u8 rlid[0x10];
				546
				547	u8 ack_timeout[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	548	u8 reserved_at_45[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	549	u8 src_addr_index[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	550	u8 reserved_at_50[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	551	u8 stat_rate[0x4];
				552	u8 hop_limit[0x8];
				553
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	554	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	555	u8 tclass[0x8];
				556	u8 flow_label[0x14];
				557
				558	u8 rgid_rip[16][0x8];
				559
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	560	u8 reserved_at_100[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	561	u8 f_dscp[0x1];
				562	u8 f_ecn[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	563	u8 reserved_at_106[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	564	u8 f_eth_prio[0x1];
				565	u8 ecn[0x2];
				566	u8 dscp[0x6];
				567	u8 udp_sport[0x10];
				568
				569	u8 dei_cfi[0x1];
				570	u8 eth_prio[0x3];
				571	u8 sl[0x4];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	572	u8 vhca_port_num[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	573	u8 rmac_47_32[0x10];
				574
				575	u8 rmac_31_0[0x20];
				576	};
				577
				578	struct mlx5_ifc_flow_table_nic_cap_bits {
Maor Gottlieb	b3638e1	2016-03-07 18:51:46 +0200	[diff] [blame]	579	u8 nic_rx_multi_path_tirs[0x1];
Maor Gottlieb	cea824d	2016-05-31 14:09:09 +0300	[diff] [blame]	580	u8 nic_rx_multi_path_tirs_fts[0x1];
				581	u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	582	u8 reserved_at_3[0x1d];
				583	u8 encap_general_header[0x1];
				584	u8 reserved_at_21[0xa];
				585	u8 log_max_packet_reformat_context[0x5];
				586	u8 reserved_at_30[0x6];
				587	u8 max_encap_header_size[0xa];
				588	u8 reserved_at_40[0x1c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	589
				590	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
				591
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	592	u8 reserved_at_400[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	593
				594	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
				595
				596	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
				597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	598	u8 reserved_at_a00[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	599
				600	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
				601
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	602	u8 reserved_at_e00[0x7200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	603	};
				604
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	605	struct mlx5_ifc_flow_table_eswitch_cap_bits {
Vu Pham	663f146	2018-10-31 16:03:21 +0200	[diff] [blame]	606	u8 reserved_at_0[0x1a];
Paul Blakey	b9aa0ba	2018-05-31 11:50:23 +0300	[diff] [blame]	607	u8 multi_fdb_encap[0x1];
Vu Pham	663f146	2018-10-31 16:03:21 +0200	[diff] [blame]	608	u8 reserved_at_1b[0x1];
				609	u8 fdb_multi_path_to_table[0x1];
				610	u8 reserved_at_1d[0x3];
				611
				612	u8 reserved_at_20[0x1e0];
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	613
				614	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
				615
				616	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
				617
				618	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
				619
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	620	u8 reserved_at_800[0x7800];
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	621	};
				622
Shahar Klein	8bb957d	2018-12-12 19:11:38 -0800	[diff] [blame]	623	enum {
				624	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
				625	MLX5_COUNTER_FLOW_ESWITCH = 0x1,
				626	};
				627
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	628	struct mlx5_ifc_e_switch_cap_bits {
				629	u8 vport_svlan_strip[0x1];
				630	u8 vport_cvlan_strip[0x1];
				631	u8 vport_svlan_insert[0x1];
				632	u8 vport_cvlan_insert_if_not_exist[0x1];
				633	u8 vport_cvlan_insert_overwrite[0x1];
Shahar Klein	8bb957d	2018-12-12 19:11:38 -0800	[diff] [blame]	634	u8 reserved_at_5[0x17];
				635	u8 counter_eswitch_affinity[0x1];
Roi Dayan	a6d0456	2017-12-05 10:38:58 +0200	[diff] [blame]	636	u8 merged_eswitch[0x1];
Noa Osherovich	23898c7	2016-06-10 00:07:37 +0300	[diff] [blame]	637	u8 nic_vport_node_guid_modify[0x1];
				638	u8 nic_vport_port_guid_modify[0x1];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	639
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	640	u8 vxlan_encap_decap[0x1];
				641	u8 nvgre_encap_decap[0x1];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	642	u8 reserved_at_22[0x1];
				643	u8 log_max_fdb_encap_uplink[0x5];
				644	u8 reserved_at_21[0x3];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	645	u8 log_max_packet_reformat_context[0x5];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	646	u8 reserved_2b[0x6];
				647	u8 max_encap_header_size[0xa];
				648
				649	u8 reserved_40[0x7c0];
				650
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	651	};
				652
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	653	struct mlx5_ifc_qos_cap_bits {
				654	u8 packet_pacing[0x1];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	655	u8 esw_scheduling[0x1];
Mohamad Haj Yahia	c9497c9	2016-12-15 14:02:53 +0200	[diff] [blame]	656	u8 esw_bw_share[0x1];
				657	u8 esw_rate_limit[0x1];
Bodong Wang	05d3ac9	2018-03-19 15:10:29 +0200	[diff] [blame]	658	u8 reserved_at_4[0x1];
				659	u8 packet_pacing_burst_bound[0x1];
				660	u8 packet_pacing_typical_size[0x1];
				661	u8 reserved_at_7[0x19];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	662
				663	u8 reserved_at_20[0x20];
				664
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	665	u8 packet_pacing_max_rate[0x20];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	666
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	667	u8 packet_pacing_min_rate[0x20];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	668
				669	u8 reserved_at_80[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	670	u8 packet_pacing_rate_table_size[0x10];
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	671
				672	u8 esw_element_type[0x10];
				673	u8 esw_tsar_type[0x10];
				674
				675	u8 reserved_at_c0[0x10];
				676	u8 max_qos_para_vport[0x10];
				677
				678	u8 max_tsar_bw_share[0x20];
				679
				680	u8 reserved_at_100[0x700];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	681	};
				682
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	683	struct mlx5_ifc_debug_cap_bits {
				684	u8 reserved_at_0[0x20];
				685
				686	u8 reserved_at_20[0x2];
				687	u8 stall_detect[0x1];
				688	u8 reserved_at_23[0x1d];
				689
				690	u8 reserved_at_40[0x7c0];
				691	};
				692
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	693	struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
				694	u8 csum_cap[0x1];
				695	u8 vlan_cap[0x1];
				696	u8 lro_cap[0x1];
				697	u8 lro_psh_flag[0x1];
				698	u8 lro_time_stamp[0x1];
Saeed Mahameed	2b31f7a	2016-11-28 18:04:50 +0200	[diff] [blame]	699	u8 reserved_at_5[0x2];
				700	u8 wqe_vlan_insert[0x1];
Tariq Toukan	6618996	2015-11-12 19:35:26 +0200	[diff] [blame]	701	u8 self_lb_en_modifiable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	702	u8 reserved_at_9[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	703	u8 max_lso_cap[0x5];
Leon Romanovsky	c226dc2	2016-10-31 12:15:20 +0200	[diff] [blame]	704	u8 multi_pkt_send_wqe[0x2];
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	705	u8 wqe_inline_mode[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	706	u8 rss_ind_tbl_cap[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	707	u8 reg_umr_sq[0x1];
				708	u8 scatter_fcs[0x1];
Bodong Wang	050da90	2017-08-17 15:52:35 +0300	[diff] [blame]	709	u8 enhanced_multi_pkt_send_wqe[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	710	u8 tunnel_lso_const_out_ip_id[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	711	u8 reserved_at_1c[0x2];
Gal Pressman	2729984	2017-08-13 13:34:42 +0300	[diff] [blame]	712	u8 tunnel_stateless_gre[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	713	u8 tunnel_stateless_vxlan[0x1];
				714
Ilan Tayari	547eede	2017-04-18 16:04:28 +0300	[diff] [blame]	715	u8 swp[0x1];
				716	u8 swp_csum[0x1];
				717	u8 swp_lso[0x1];
Gal Pressman	22a65aa	2017-12-25 18:40:52 +0200	[diff] [blame]	718	u8 reserved_at_23[0xd];
				719	u8 max_vxlan_udp_ports[0x8];
				720	u8 reserved_at_38[0x6];
Maor Gottlieb	4d350f1	2017-10-19 08:25:54 +0300	[diff] [blame]	721	u8 max_geneve_opt_len[0x1];
				722	u8 tunnel_stateless_geneve_rx[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	723
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	724	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	725	u8 lro_min_mss_size[0x10];
				726
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	727	u8 reserved_at_60[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	728
				729	u8 lro_timer_supported_periods[4][0x20];
				730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	731	u8 reserved_at_200[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	732	};
				733
				734	struct mlx5_ifc_roce_cap_bits {
				735	u8 roce_apm[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	736	u8 reserved_at_1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	737
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	738	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	739
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	740	u8 reserved_at_80[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	741	u8 l3_type[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	742	u8 reserved_at_90[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	743	u8 roce_version[0x8];
				744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	745	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	746	u8 r_roce_dest_udp_port[0x10];
				747
				748	u8 r_roce_max_src_udp_port[0x10];
				749	u8 r_roce_min_src_udp_port[0x10];
				750
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	751	u8 reserved_at_e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	752	u8 roce_address_table_size[0x10];
				753
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	754	u8 reserved_at_100[0x700];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	755	};
				756
Ariel Levkovich	e72bd81	2018-04-05 18:53:26 +0300	[diff] [blame]	757	struct mlx5_ifc_device_mem_cap_bits {
				758	u8 memic[0x1];
				759	u8 reserved_at_1[0x1f];
				760
				761	u8 reserved_at_20[0xb];
				762	u8 log_min_memic_alloc_size[0x5];
				763	u8 reserved_at_30[0x8];
				764	u8 log_max_memic_addr_alignment[0x8];
				765
				766	u8 memic_bar_start_addr[0x40];
				767
				768	u8 memic_bar_size[0x20];
				769
				770	u8 max_memic_size[0x20];
				771
				772	u8 reserved_at_c0[0x740];
				773	};
				774
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	775	enum {
				776	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
				777	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
				778	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
				779	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
				780	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
				781	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
				782	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
				783	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
				784	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
				785	};
				786
				787	enum {
				788	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
				789	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
				790	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
				791	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
				792	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
				793	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
				794	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
				795	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
				796	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
				797	};
				798
				799	struct mlx5_ifc_atomic_caps_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	800	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	801
Or Gerlitz	bd10838	2017-05-28 15:24:17 +0300	[diff] [blame]	802	u8 atomic_req_8B_endianness_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	803	u8 reserved_at_42[0x4];
Or Gerlitz	bd10838	2017-05-28 15:24:17 +0300	[diff] [blame]	804	u8 supported_atomic_req_8B_endianness_mode_1[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	805
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	806	u8 reserved_at_47[0x19];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	807
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	808	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	809
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	810	u8 reserved_at_80[0x10];
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	811	u8 atomic_operations[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	812
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	813	u8 reserved_at_a0[0x10];
Eran Ben Elisha	f91e6d8	2015-12-14 16:34:09 +0200	[diff] [blame]	814	u8 atomic_size_qp[0x10];
				815
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	816	u8 reserved_at_c0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	817	u8 atomic_size_dc[0x10];
				818
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	819	u8 reserved_at_e0[0x720];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	820	};
				821
				822	struct mlx5_ifc_odp_cap_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	823	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	824
				825	u8 sig[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	826	u8 reserved_at_41[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	827
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	828	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	829
				830	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
				831
				832	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
				833
				834	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
				835
Moni Shoua	dda7a81	2019-01-22 08:48:49 +0200	[diff] [blame]	836	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
				837
				838	u8 reserved_at_100[0x700];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	839	};
				840
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	841	struct mlx5_ifc_calc_op {
				842	u8 reserved_at_0[0x10];
				843	u8 reserved_at_10[0x9];
				844	u8 op_swap_endianness[0x1];
				845	u8 op_min[0x1];
				846	u8 op_xor[0x1];
				847	u8 op_or[0x1];
				848	u8 op_and[0x1];
				849	u8 op_max[0x1];
				850	u8 op_add[0x1];
				851	};
				852
				853	struct mlx5_ifc_vector_calc_cap_bits {
				854	u8 calc_matrix[0x1];
				855	u8 reserved_at_1[0x1f];
				856	u8 reserved_at_20[0x8];
				857	u8 max_vec_count[0x8];
				858	u8 reserved_at_30[0xd];
				859	u8 max_chunk_size[0x3];
				860	struct mlx5_ifc_calc_op calc0;
				861	struct mlx5_ifc_calc_op calc1;
				862	struct mlx5_ifc_calc_op calc2;
				863	struct mlx5_ifc_calc_op calc3;
				864
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	865	u8 reserved_at_c0[0x720];
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	866	};
				867
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	868	enum {
				869	MLX5_WQ_TYPE_LINKED_LIST = 0x0,
				870	MLX5_WQ_TYPE_CYCLIC = 0x1,
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	871	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
Noa Osherovich	ccc87087	2017-10-17 18:01:13 +0300	[diff] [blame]	872	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	873	};
				874
				875	enum {
				876	MLX5_WQ_END_PAD_MODE_NONE = 0x0,
				877	MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
				878	};
				879
				880	enum {
				881	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
				882	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
				883	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
				884	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
				885	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
				886	};
				887
				888	enum {
				889	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
				890	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
				891	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
				892	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
				893	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
				894	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
				895	};
				896
				897	enum {
				898	MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
				899	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
				900	};
				901
				902	enum {
				903	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
				904	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
				905	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
				906	};
				907
				908	enum {
				909	MLX5_CAP_PORT_TYPE_IB = 0x0,
				910	MLX5_CAP_PORT_TYPE_ETH = 0x1,
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	911	};
				912
Max Gurtovoy	1410a90	2017-05-28 10:53:10 +0300	[diff] [blame]	913	enum {
				914	MLX5_CAP_UMR_FENCE_STRONG = 0x0,
				915	MLX5_CAP_UMR_FENCE_SMALL = 0x1,
				916	MLX5_CAP_UMR_FENCE_NONE = 0x2,
				917	};
				918
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	919	enum {
				920	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
				921	};
				922
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	923	struct mlx5_ifc_cmd_hca_cap_bits {
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	924	u8 reserved_at_0[0x30];
				925	u8 vhca_id[0x10];
				926
				927	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	928
				929	u8 log_max_srq_sz[0x8];
				930	u8 log_max_qp_sz[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	931	u8 reserved_at_90[0xb];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	932	u8 log_max_qp[0x5];
				933
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	934	u8 reserved_at_a0[0xb];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	935	u8 log_max_srq[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	936	u8 reserved_at_b0[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	937
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	938	u8 reserved_at_c0[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	939	u8 log_max_cq_sz[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	940	u8 reserved_at_d0[0xb];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	941	u8 log_max_cq[0x5];
				942
				943	u8 log_max_eq_sz[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	944	u8 reserved_at_e8[0x2];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	945	u8 log_max_mkey[0x6];
Leon Romanovsky	b183ee2	2018-06-19 08:47:23 +0300	[diff] [blame]	946	u8 reserved_at_f0[0x8];
				947	u8 dump_fill_mkey[0x1];
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	948	u8 reserved_at_f9[0x2];
				949	u8 fast_teardown[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	950	u8 log_max_eq[0x4];
				951
				952	u8 max_indirection[0x8];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	953	u8 fixed_buffer_size[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	954	u8 log_max_mrw_sz[0x7];
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	955	u8 force_teardown[0x1];
				956	u8 reserved_at_111[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	957	u8 log_max_bsf_list_size[0x6];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	958	u8 umr_extended_translation_offset[0x1];
				959	u8 null_mkey[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	960	u8 log_max_klm_list_size[0x6];
				961
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	962	u8 reserved_at_120[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	963	u8 log_max_ra_req_dc[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	964	u8 reserved_at_130[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	965	u8 log_max_ra_res_dc[0x6];
				966
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	967	u8 reserved_at_140[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	968	u8 log_max_ra_req_qp[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	969	u8 reserved_at_150[0xa];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	970	u8 log_max_ra_res_qp[0x6];
				971
Daniel Jurgens	f32f5bd	2015-11-19 17:12:26 +0200	[diff] [blame]	972	u8 end_pad[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	973	u8 cc_query_allowed[0x1];
				974	u8 cc_modify_allowed[0x1];
Daniel Jurgens	f32f5bd	2015-11-19 17:12:26 +0200	[diff] [blame]	975	u8 start_pad[0x1];
				976	u8 cache_line_128byte[0x1];
Huy Nguyen	c02762e	2017-07-18 16:03:17 -0500	[diff] [blame]	977	u8 reserved_at_165[0xa];
				978	u8 qcam_reg[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	979	u8 gid_table_size[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	980
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	981	u8 out_of_seq_cnt[0x1];
				982	u8 vport_counters[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	983	u8 retransmission_q_counters[0x1];
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	984	u8 debug[0x1];
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	985	u8 modify_rq_counter_set_id[0x1];
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	986	u8 rq_delay_drop[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	987	u8 max_qp_cnt[0xa];
				988	u8 pkey_table_size[0x10];
				989
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	990	u8 vport_group_manager[0x1];
				991	u8 vhca_group_manager[0x1];
				992	u8 ib_virt[0x1];
				993	u8 eth_virt[0x1];
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	994	u8 vnic_env_queue_counters[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	995	u8 ets[0x1];
				996	u8 nic_flow_table[0x1];
Or Gerlitz	0efc856	2018-05-31 11:16:18 +0300	[diff] [blame]	997	u8 eswitch_manager[0x1];
Ariel Levkovich	e72bd81	2018-04-05 18:53:26 +0300	[diff] [blame]	998	u8 device_memory[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	999	u8 mcam_reg[0x1];
				1000	u8 pcam_reg[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1001	u8 local_ca_ack_delay[0x5];
Huy Nguyen	4ce3bf2	2016-11-17 13:45:56 +0200	[diff] [blame]	1002	u8 port_module_event[0x1];
Parav Pandit	58dcb60	2017-06-19 07:19:37 +0300	[diff] [blame]	1003	u8 enhanced_error_q_counters[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1004	u8 ports_check[0x1];
Max Gurtovoy	7b13558	2017-01-02 11:37:38 +0200	[diff] [blame]	1005	u8 reserved_at_1b3[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1006	u8 disable_link_up[0x1];
				1007	u8 beacon_led[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1008	u8 port_type[0x2];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1009	u8 num_ports[0x8];
				1010
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	1011	u8 reserved_at_1c0[0x1];
				1012	u8 pps[0x1];
				1013	u8 pps_modify[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1014	u8 log_max_msg[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1015	u8 reserved_at_1c8[0x4];
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	1016	u8 max_tc[0x4];
Ilan Tayari	1865ea9a	2018-05-30 10:59:49 -0700	[diff] [blame]	1017	u8 temp_warn_event[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1018	u8 dcbx[0x1];
Maor Gottlieb	246ac98	2017-05-30 10:29:12 +0300	[diff] [blame]	1019	u8 general_notification_event[0x1];
				1020	u8 reserved_at_1d3[0x2];
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	1021	u8 fpga[0x1];
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	1022	u8 rol_s[0x1];
				1023	u8 rol_g[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1024	u8 reserved_at_1d8[0x1];
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	1025	u8 wol_s[0x1];
				1026	u8 wol_g[0x1];
				1027	u8 wol_a[0x1];
				1028	u8 wol_b[0x1];
				1029	u8 wol_m[0x1];
				1030	u8 wol_u[0x1];
				1031	u8 wol_p[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1032
				1033	u8 stat_rate_support[0x10];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1034	u8 reserved_at_1f0[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1035	u8 cqe_version[0x4];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1036
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1037	u8 compact_address_vector[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1038	u8 striding_rq[0x1];
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	1039	u8 reserved_at_202[0x1];
				1040	u8 ipoib_enhanced_offloads[0x1];
Erez Shitrit	1015c2e	2016-02-21 16:27:16 +0200	[diff] [blame]	1041	u8 ipoib_basic_offloads[0x1];
Majd Dibbiny	c8d75a9	2018-03-22 15:34:04 +0200	[diff] [blame]	1042	u8 reserved_at_205[0x1];
				1043	u8 repeated_block_disabled[0x1];
				1044	u8 umr_modify_entity_size_disabled[0x1];
				1045	u8 umr_modify_atomic_disabled[0x1];
				1046	u8 umr_indirect_mkey_disabled[0x1];
Max Gurtovoy	1410a90	2017-05-28 10:53:10 +0300	[diff] [blame]	1047	u8 umr_fence[0x2];
Yonatan Cohen	94a04d1	2018-10-09 12:05:12 +0300	[diff] [blame]	1048	u8 dc_req_scat_data_cqe[0x1];
				1049	u8 reserved_at_20d[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1050	u8 drain_sigerr[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1051	u8 cmdif_checksum[0x2];
				1052	u8 sigerr_cqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1053	u8 reserved_at_213[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1054	u8 wq_signature[0x1];
				1055	u8 sctr_data_cqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1056	u8 reserved_at_216[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1057	u8 sho[0x1];
				1058	u8 tph[0x1];
				1059	u8 rf[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1060	u8 dct[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1061	u8 qos[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1062	u8 eth_net_offloads[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1063	u8 roce[0x1];
				1064	u8 atomic[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1065	u8 reserved_at_21f[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1066
				1067	u8 cq_oi[0x1];
				1068	u8 cq_resize[0x1];
				1069	u8 cq_moderation[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1070	u8 reserved_at_223[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1071	u8 cq_eq_remap[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1072	u8 pg[0x1];
				1073	u8 block_lb_mc[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1074	u8 reserved_at_229[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1075	u8 scqe_break_moderation[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1076	u8 cq_period_start_from_cqe[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1077	u8 cd[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1078	u8 reserved_at_22d[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1079	u8 apm[0x1];
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	1080	u8 vector_calc[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1081	u8 umr_ptr_rlky[0x1];
Matan Barak	d2370e0	2016-02-29 18:05:30 +0200	[diff] [blame]	1082	u8 imaicl[0x1];
Danit Goldberg	3fd3c80	2018-11-30 13:22:04 +0200	[diff] [blame]	1083	u8 qp_packet_based[0x1];
				1084	u8 reserved_at_233[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1085	u8 qkv[0x1];
				1086	u8 pkv[0x1];
Haggai Eran	b11a4f9	2016-02-29 15:45:03 +0200	[diff] [blame]	1087	u8 set_deth_sqpn[0x1];
				1088	u8 reserved_at_239[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1089	u8 xrc[0x1];
				1090	u8 ud[0x1];
				1091	u8 uc[0x1];
				1092	u8 rc[0x1];
				1093
Eli Cohen	a6d51b6	2017-01-03 23:55:23 +0200	[diff] [blame]	1094	u8 uar_4k[0x1];
				1095	u8 reserved_at_241[0x9];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1096	u8 uar_sz[0x6];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1097	u8 reserved_at_250[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1098	u8 log_pg_sz[0x8];
				1099
				1100	u8 bf[0x1];
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	1101	u8 driver_version[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1102	u8 pad_tx_eth_packet[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1103	u8 reserved_at_263[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1104	u8 log_bf_reg_size[0x5];
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	1105
				1106	u8 reserved_at_270[0xb];
				1107	u8 lag_master[0x1];
				1108	u8 num_lag_ports[0x4];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1109
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1110	u8 reserved_at_280[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1111	u8 max_wqe_sz_sq[0x10];
				1112
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1113	u8 reserved_at_2a0[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1114	u8 max_wqe_sz_rq[0x10];
				1115
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1116	u8 max_flow_counter_31_16[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1117	u8 max_wqe_sz_sq_dc[0x10];
				1118
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1119	u8 reserved_at_2e0[0x7];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1120	u8 max_qp_mcg[0x19];
				1121
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1122	u8 reserved_at_300[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1123	u8 log_max_mcg[0x8];
				1124
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1125	u8 reserved_at_320[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1126	u8 log_max_transport_domain[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1127	u8 reserved_at_328[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1128	u8 log_max_pd[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1129	u8 reserved_at_330[0xb];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1130	u8 log_max_xrcd[0x5];
				1131
Moshe Shemesh	5c29814	2017-12-26 16:46:29 +0200	[diff] [blame]	1132	u8 nic_receive_steering_discard[0x1];
Moshe Shemesh	aaabd07	2018-01-14 00:56:25 +0200	[diff] [blame]	1133	u8 receive_discard_vport_down[0x1];
				1134	u8 transmit_discard_vport_down[0x1];
				1135	u8 reserved_at_343[0x5];
Amir Vadai	a351a1b0	2016-07-14 10:32:38 +0300	[diff] [blame]	1136	u8 log_max_flow_counter_bulk[0x8];
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1137	u8 max_flow_counter_15_0[0x10];
Amir Vadai	a351a1b0	2016-07-14 10:32:38 +0300	[diff] [blame]	1138
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1139
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1140	u8 reserved_at_360[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1141	u8 log_max_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1142	u8 reserved_at_368[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1143	u8 log_max_sq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1144	u8 reserved_at_370[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1145	u8 log_max_tir[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1146	u8 reserved_at_378[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1147	u8 log_max_tis[0x5];
				1148
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1149	u8 basic_cyclic_rcv_wqe[0x1];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1150	u8 reserved_at_381[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1151	u8 log_max_rmp[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1152	u8 reserved_at_388[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1153	u8 log_max_rqt[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1154	u8 reserved_at_390[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1155	u8 log_max_rqt_size[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1156	u8 reserved_at_398[0x3];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1157	u8 log_max_tis_per_sq[0x5];
				1158
Tariq Toukan	619a8f2a	2018-02-07 14:41:25 +0200	[diff] [blame]	1159	u8 ext_stride_num_range[0x1];
				1160	u8 reserved_at_3a1[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1161	u8 log_max_stride_sz_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1162	u8 reserved_at_3a8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1163	u8 log_min_stride_sz_rq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1164	u8 reserved_at_3b0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1165	u8 log_max_stride_sz_sq[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1166	u8 reserved_at_3b8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1167	u8 log_min_stride_sz_sq[0x5];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1168
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1169	u8 hairpin[0x1];
				1170	u8 reserved_at_3c1[0x2];
				1171	u8 log_max_hairpin_queues[0x5];
				1172	u8 reserved_at_3c8[0x3];
				1173	u8 log_max_hairpin_wq_data_sz[0x5];
Or Gerlitz	4d533e0	2018-01-04 12:26:21 +0200	[diff] [blame]	1174	u8 reserved_at_3d0[0x3];
				1175	u8 log_max_hairpin_num_packets[0x5];
				1176	u8 reserved_at_3d8[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1177	u8 log_max_wq_sz[0x5];
				1178
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1179	u8 nic_vport_change_event[0x1];
Eran Ben Elisha	8978cc9	2018-01-09 11:41:10 +0200	[diff] [blame]	1180	u8 disable_local_lb_uc[0x1];
				1181	u8 disable_local_lb_mc[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1182	u8 log_min_hairpin_wq_data_sz[0x5];
				1183	u8 reserved_at_3e8[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1184	u8 log_max_vlan_list[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1185	u8 reserved_at_3f0[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1186	u8 log_max_current_mc_list[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1187	u8 reserved_at_3f8[0x3];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1188	u8 log_max_current_uc_list[0x5];
				1189
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	1190	u8 general_obj_types[0x40];
				1191
Denis Drozdov	342ac84	2018-08-08 16:23:48 -0700	[diff] [blame]	1192	u8 reserved_at_440[0x20];
				1193
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	1194	u8 reserved_at_460[0x3];
				1195	u8 log_max_uctx[0x5];
				1196	u8 reserved_at_468[0x3];
				1197	u8 log_max_umem[0x5];
Denis Drozdov	342ac84	2018-08-08 16:23:48 -0700	[diff] [blame]	1198	u8 max_num_eqs[0x10];
Saeed Mahameed	54f0a41	2015-12-01 18:03:10 +0200	[diff] [blame]	1199
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1200	u8 reserved_at_480[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1201	u8 log_max_l2_table[0x5];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1202	u8 reserved_at_488[0x8];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1203	u8 log_uar_page_sz[0x10];
				1204
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1205	u8 reserved_at_4a0[0x20];
Linus Torvalds	048ccca	2016-01-23 18:45:06 -0800	[diff] [blame]	1206	u8 device_frequency_mhz[0x20];
Eran Ben Elisha	b084444	2015-12-29 14:58:30 +0200	[diff] [blame]	1207	u8 device_frequency_khz[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1208
Eli Cohen	a6d51b6	2017-01-03 23:55:23 +0200	[diff] [blame]	1209	u8 reserved_at_500[0x20];
				1210	u8 num_of_uars_per_page[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1211
Ariel Levkovich	e818e25	2018-05-13 14:33:35 +0300	[diff] [blame]	1212	u8 flex_parser_protocols[0x20];
				1213	u8 reserved_at_560[0x20];
Tariq Toukan	e1c9c62	2016-04-11 23:10:21 +0300	[diff] [blame]	1214
Yonatan Cohen	ab741b2	2018-05-27 13:42:32 +0300	[diff] [blame]	1215	u8 reserved_at_580[0x3c];
				1216	u8 mini_cqe_resp_stride_index[0x1];
Guy Levi	0ff8e79	2017-10-19 08:25:51 +0300	[diff] [blame]	1217	u8 cqe_128_always[0x1];
				1218	u8 cqe_compression_128[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1219	u8 cqe_compression[0x1];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1220
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1221	u8 cqe_compression_timeout[0x10];
				1222	u8 cqe_compression_max_num[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	1223
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1224	u8 reserved_at_5e0[0x10];
				1225	u8 tag_matching[0x1];
				1226	u8 rndv_offload_rc[0x1];
				1227	u8 rndv_offload_dc[0x1];
				1228	u8 log_tag_matching_list_sz[0x5];
Max Gurtovoy	7b13558	2017-01-02 11:37:38 +0200	[diff] [blame]	1229	u8 reserved_at_5f8[0x3];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	1230	u8 log_max_xrq[0x5];
				1231
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	1232	u8 affiliate_nic_vport_criteria[0x8];
				1233	u8 native_port_num[0x8];
				1234	u8 num_vhca_ports[0x8];
				1235	u8 reserved_at_618[0x6];
				1236	u8 sw_owner_id[0x1];
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	1237	u8 reserved_at_61f[0x1];
				1238
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	1239	u8 max_num_of_monitor_counters[0x10];
				1240	u8 num_ppcnt_monitor_counters[0x10];
				1241
				1242	u8 reserved_at_640[0x10];
				1243	u8 num_q_monitor_counters[0x10];
				1244
				1245	u8 reserved_at_660[0x40];
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	1246
				1247	u8 uctx_cap[0x20];
				1248
				1249	u8 reserved_at_6c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1250	};
				1251
Saeed Mahameed	8184873	2015-12-01 18:03:20 +0200	[diff] [blame]	1252	enum mlx5_flow_destination_type {
				1253	MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
				1254	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
				1255	MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
Amir Vadai	bd5251db	2016-05-13 12:55:40 +0000	[diff] [blame]	1256
Aviad Yehezkel	5f41837	2018-02-18 13:17:17 +0200	[diff] [blame]	1257	MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
Amir Vadai	bd5251db	2016-05-13 12:55:40 +0000	[diff] [blame]	1258	MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
Yishai Hadas	664000b	2018-06-19 15:23:36 +0300	[diff] [blame]	1259	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1260	};
				1261
				1262	struct mlx5_ifc_dest_format_struct_bits {
				1263	u8 destination_type[0x8];
				1264	u8 destination_id[0x18];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1265
Shahar Klein	b17f7fc	2018-03-22 12:32:12 +0200	[diff] [blame]	1266	u8 destination_eswitch_owner_vhca_id_valid[0x1];
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1267	u8 packet_reformat[0x1];
				1268	u8 reserved_at_22[0xe];
Shahar Klein	b17f7fc	2018-03-22 12:32:12 +0200	[diff] [blame]	1269	u8 destination_eswitch_owner_vhca_id[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1270	};
				1271
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1272	struct mlx5_ifc_flow_counter_list_bits {
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	1273	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1274
				1275	u8 reserved_at_20[0x20];
				1276	};
				1277
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	1278	struct mlx5_ifc_extended_dest_format_bits {
				1279	struct mlx5_ifc_dest_format_struct_bits destination_entry;
				1280
				1281	u8 packet_reformat_id[0x20];
				1282
				1283	u8 reserved_at_60[0x20];
				1284	};
				1285
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	1286	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
				1287	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
				1288	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
				1289	u8 reserved_at_0[0x40];
				1290	};
				1291
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1292	struct mlx5_ifc_fte_match_param_bits {
				1293	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
				1294
				1295	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
				1296
				1297	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
				1298
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	1299	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
				1300
				1301	u8 reserved_at_800[0x800];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1302	};
				1303
				1304	enum {
				1305	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
				1306	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
				1307	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
				1308	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
				1309	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
				1310	};
				1311
				1312	struct mlx5_ifc_rx_hash_field_select_bits {
				1313	u8 l3_prot_type[0x1];
				1314	u8 l4_prot_type[0x1];
				1315	u8 selected_fields[0x1e];
				1316	};
				1317
				1318	enum {
				1319	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
				1320	MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
				1321	};
				1322
				1323	enum {
				1324	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
				1325	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
				1326	};
				1327
				1328	struct mlx5_ifc_wq_bits {
				1329	u8 wq_type[0x4];
				1330	u8 wq_signature[0x1];
				1331	u8 end_padding_mode[0x2];
				1332	u8 cd_slave[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1333	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1334
				1335	u8 hds_skip_first_sge[0x1];
				1336	u8 log2_hds_buf_size[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1337	u8 reserved_at_24[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1338	u8 page_offset[0x5];
				1339	u8 lwm[0x10];
				1340
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1341	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1342	u8 pd[0x18];
				1343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1344	u8 reserved_at_60[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1345	u8 uar_page[0x18];
				1346
				1347	u8 dbr_addr[0x40];
				1348
				1349	u8 hw_counter[0x20];
				1350
				1351	u8 sw_counter[0x20];
				1352
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1353	u8 reserved_at_100[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1354	u8 log_wq_stride[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1355	u8 reserved_at_110[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1356	u8 log_wq_pg_sz[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1357	u8 reserved_at_118[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1358	u8 log_wq_sz[0x5];
				1359
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	1360	u8 dbr_umem_valid[0x1];
				1361	u8 wq_umem_valid[0x1];
				1362	u8 reserved_at_122[0x1];
Or Gerlitz	4d533e0	2018-01-04 12:26:21 +0200	[diff] [blame]	1363	u8 log_hairpin_num_packets[0x5];
				1364	u8 reserved_at_128[0x3];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1365	u8 log_hairpin_data_sz[0x5];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	1366
Tariq Toukan	619a8f2a	2018-02-07 14:41:25 +0200	[diff] [blame]	1367	u8 reserved_at_130[0x4];
				1368	u8 log_wqe_num_of_strides[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	1369	u8 two_byte_shift_en[0x1];
				1370	u8 reserved_at_139[0x4];
				1371	u8 log_wqe_stride_size[0x3];
				1372
				1373	u8 reserved_at_140[0x4c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1374
				1375	struct mlx5_ifc_cmd_pas_bits pas[0];
				1376	};
				1377
				1378	struct mlx5_ifc_rq_num_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1379	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1380	u8 rq_num[0x18];
				1381	};
				1382
				1383	struct mlx5_ifc_mac_address_layout_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1384	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1385	u8 mac_addr_47_32[0x10];
				1386
				1387	u8 mac_addr_31_0[0x20];
				1388	};
				1389
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1390	struct mlx5_ifc_vlan_layout_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1391	u8 reserved_at_0[0x14];
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1392	u8 vlan[0x0c];
				1393
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1394	u8 reserved_at_20[0x20];
Saeed Mahameed	c0046cf	2015-12-01 18:03:15 +0200	[diff] [blame]	1395	};
				1396
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1397	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1398	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1399
				1400	u8 min_time_between_cnps[0x20];
				1401
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1402	u8 reserved_at_c0[0x12];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1403	u8 cnp_dscp[0x6];
Parav Pandit	4a2da0b	2017-05-30 10:05:15 +0300	[diff] [blame]	1404	u8 reserved_at_d8[0x4];
				1405	u8 cnp_prio_mode[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1406	u8 cnp_802p_prio[0x3];
				1407
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1408	u8 reserved_at_e0[0x720];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1409	};
				1410
				1411	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1412	u8 reserved_at_0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1413
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1414	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1415	u8 clamp_tgt_rate[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1416	u8 reserved_at_65[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1417	u8 clamp_tgt_rate_after_time_inc[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1418	u8 reserved_at_69[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1419
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1420	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1421
				1422	u8 rpg_time_reset[0x20];
				1423
				1424	u8 rpg_byte_reset[0x20];
				1425
				1426	u8 rpg_threshold[0x20];
				1427
				1428	u8 rpg_max_rate[0x20];
				1429
				1430	u8 rpg_ai_rate[0x20];
				1431
				1432	u8 rpg_hai_rate[0x20];
				1433
				1434	u8 rpg_gd[0x20];
				1435
				1436	u8 rpg_min_dec_fac[0x20];
				1437
				1438	u8 rpg_min_rate[0x20];
				1439
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1440	u8 reserved_at_1c0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1441
				1442	u8 rate_to_set_on_first_cnp[0x20];
				1443
				1444	u8 dce_tcp_g[0x20];
				1445
				1446	u8 dce_tcp_rtt[0x20];
				1447
				1448	u8 rate_reduce_monitor_period[0x20];
				1449
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1450	u8 reserved_at_320[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1451
				1452	u8 initial_alpha_value[0x20];
				1453
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1454	u8 reserved_at_360[0x4a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1455	};
				1456
				1457	struct mlx5_ifc_cong_control_802_1qau_rp_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1458	u8 reserved_at_0[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1459
				1460	u8 rppp_max_rps[0x20];
				1461
				1462	u8 rpg_time_reset[0x20];
				1463
				1464	u8 rpg_byte_reset[0x20];
				1465
				1466	u8 rpg_threshold[0x20];
				1467
				1468	u8 rpg_max_rate[0x20];
				1469
				1470	u8 rpg_ai_rate[0x20];
				1471
				1472	u8 rpg_hai_rate[0x20];
				1473
				1474	u8 rpg_gd[0x20];
				1475
				1476	u8 rpg_min_dec_fac[0x20];
				1477
				1478	u8 rpg_min_rate[0x20];
				1479
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1480	u8 reserved_at_1c0[0x640];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1481	};
				1482
				1483	enum {
				1484	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
				1485	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
				1486	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
				1487	};
				1488
				1489	struct mlx5_ifc_resize_field_select_bits {
				1490	u8 resize_field_select[0x20];
				1491	};
				1492
				1493	enum {
				1494	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
				1495	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
				1496	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
				1497	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
				1498	};
				1499
				1500	struct mlx5_ifc_modify_field_select_bits {
				1501	u8 modify_field_select[0x20];
				1502	};
				1503
				1504	struct mlx5_ifc_field_select_r_roce_np_bits {
				1505	u8 field_select_r_roce_np[0x20];
				1506	};
				1507
				1508	struct mlx5_ifc_field_select_r_roce_rp_bits {
				1509	u8 field_select_r_roce_rp[0x20];
				1510	};
				1511
				1512	enum {
				1513	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
				1514	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
				1515	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
				1516	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
				1517	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
				1518	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
				1519	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
				1520	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
				1521	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
				1522	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
				1523	};
				1524
				1525	struct mlx5_ifc_field_select_802_1qau_rp_bits {
				1526	u8 field_select_8021qaurp[0x20];
				1527	};
				1528
				1529	struct mlx5_ifc_phys_layer_cntrs_bits {
				1530	u8 time_since_last_clear_high[0x20];
				1531
				1532	u8 time_since_last_clear_low[0x20];
				1533
				1534	u8 symbol_errors_high[0x20];
				1535
				1536	u8 symbol_errors_low[0x20];
				1537
				1538	u8 sync_headers_errors_high[0x20];
				1539
				1540	u8 sync_headers_errors_low[0x20];
				1541
				1542	u8 edpl_bip_errors_lane0_high[0x20];
				1543
				1544	u8 edpl_bip_errors_lane0_low[0x20];
				1545
				1546	u8 edpl_bip_errors_lane1_high[0x20];
				1547
				1548	u8 edpl_bip_errors_lane1_low[0x20];
				1549
				1550	u8 edpl_bip_errors_lane2_high[0x20];
				1551
				1552	u8 edpl_bip_errors_lane2_low[0x20];
				1553
				1554	u8 edpl_bip_errors_lane3_high[0x20];
				1555
				1556	u8 edpl_bip_errors_lane3_low[0x20];
				1557
				1558	u8 fc_fec_corrected_blocks_lane0_high[0x20];
				1559
				1560	u8 fc_fec_corrected_blocks_lane0_low[0x20];
				1561
				1562	u8 fc_fec_corrected_blocks_lane1_high[0x20];
				1563
				1564	u8 fc_fec_corrected_blocks_lane1_low[0x20];
				1565
				1566	u8 fc_fec_corrected_blocks_lane2_high[0x20];
				1567
				1568	u8 fc_fec_corrected_blocks_lane2_low[0x20];
				1569
				1570	u8 fc_fec_corrected_blocks_lane3_high[0x20];
				1571
				1572	u8 fc_fec_corrected_blocks_lane3_low[0x20];
				1573
				1574	u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
				1575
				1576	u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
				1577
				1578	u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
				1579
				1580	u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
				1581
				1582	u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
				1583
				1584	u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
				1585
				1586	u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
				1587
				1588	u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
				1589
				1590	u8 rs_fec_corrected_blocks_high[0x20];
				1591
				1592	u8 rs_fec_corrected_blocks_low[0x20];
				1593
				1594	u8 rs_fec_uncorrectable_blocks_high[0x20];
				1595
				1596	u8 rs_fec_uncorrectable_blocks_low[0x20];
				1597
				1598	u8 rs_fec_no_errors_blocks_high[0x20];
				1599
				1600	u8 rs_fec_no_errors_blocks_low[0x20];
				1601
				1602	u8 rs_fec_single_error_blocks_high[0x20];
				1603
				1604	u8 rs_fec_single_error_blocks_low[0x20];
				1605
				1606	u8 rs_fec_corrected_symbols_total_high[0x20];
				1607
				1608	u8 rs_fec_corrected_symbols_total_low[0x20];
				1609
				1610	u8 rs_fec_corrected_symbols_lane0_high[0x20];
				1611
				1612	u8 rs_fec_corrected_symbols_lane0_low[0x20];
				1613
				1614	u8 rs_fec_corrected_symbols_lane1_high[0x20];
				1615
				1616	u8 rs_fec_corrected_symbols_lane1_low[0x20];
				1617
				1618	u8 rs_fec_corrected_symbols_lane2_high[0x20];
				1619
				1620	u8 rs_fec_corrected_symbols_lane2_low[0x20];
				1621
				1622	u8 rs_fec_corrected_symbols_lane3_high[0x20];
				1623
				1624	u8 rs_fec_corrected_symbols_lane3_low[0x20];
				1625
				1626	u8 link_down_events[0x20];
				1627
				1628	u8 successful_recovery_events[0x20];
				1629
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1630	u8 reserved_at_640[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1631	};
				1632
Gal Pressman	d8dc050	2016-09-27 17:04:51 +0300	[diff] [blame]	1633	struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
				1634	u8 time_since_last_clear_high[0x20];
				1635
				1636	u8 time_since_last_clear_low[0x20];
				1637
				1638	u8 phy_received_bits_high[0x20];
				1639
				1640	u8 phy_received_bits_low[0x20];
				1641
				1642	u8 phy_symbol_errors_high[0x20];
				1643
				1644	u8 phy_symbol_errors_low[0x20];
				1645
				1646	u8 phy_corrected_bits_high[0x20];
				1647
				1648	u8 phy_corrected_bits_low[0x20];
				1649
				1650	u8 phy_corrected_bits_lane0_high[0x20];
				1651
				1652	u8 phy_corrected_bits_lane0_low[0x20];
				1653
				1654	u8 phy_corrected_bits_lane1_high[0x20];
				1655
				1656	u8 phy_corrected_bits_lane1_low[0x20];
				1657
				1658	u8 phy_corrected_bits_lane2_high[0x20];
				1659
				1660	u8 phy_corrected_bits_lane2_low[0x20];
				1661
				1662	u8 phy_corrected_bits_lane3_high[0x20];
				1663
				1664	u8 phy_corrected_bits_lane3_low[0x20];
				1665
				1666	u8 reserved_at_200[0x5c0];
				1667	};
				1668
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	1669	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
				1670	u8 symbol_error_counter[0x10];
				1671
				1672	u8 link_error_recovery_counter[0x8];
				1673
				1674	u8 link_downed_counter[0x8];
				1675
				1676	u8 port_rcv_errors[0x10];
				1677
				1678	u8 port_rcv_remote_physical_errors[0x10];
				1679
				1680	u8 port_rcv_switch_relay_errors[0x10];
				1681
				1682	u8 port_xmit_discards[0x10];
				1683
				1684	u8 port_xmit_constraint_errors[0x8];
				1685
				1686	u8 port_rcv_constraint_errors[0x8];
				1687
				1688	u8 reserved_at_70[0x8];
				1689
				1690	u8 link_overrun_errors[0x8];
				1691
				1692	u8 reserved_at_80[0x10];
				1693
				1694	u8 vl_15_dropped[0x10];
				1695
Tim Wright	133bea0	2017-05-01 17:30:08 +0100	[diff] [blame]	1696	u8 reserved_at_a0[0x80];
				1697
				1698	u8 port_xmit_wait[0x20];
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	1699	};
				1700
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1701	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
				1702	u8 transmit_queue_high[0x20];
				1703
				1704	u8 transmit_queue_low[0x20];
				1705
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1706	u8 reserved_at_40[0x780];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1707	};
				1708
				1709	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
				1710	u8 rx_octets_high[0x20];
				1711
				1712	u8 rx_octets_low[0x20];
				1713
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1714	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1715
				1716	u8 rx_frames_high[0x20];
				1717
				1718	u8 rx_frames_low[0x20];
				1719
				1720	u8 tx_octets_high[0x20];
				1721
				1722	u8 tx_octets_low[0x20];
				1723
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1724	u8 reserved_at_180[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1725
				1726	u8 tx_frames_high[0x20];
				1727
				1728	u8 tx_frames_low[0x20];
				1729
				1730	u8 rx_pause_high[0x20];
				1731
				1732	u8 rx_pause_low[0x20];
				1733
				1734	u8 rx_pause_duration_high[0x20];
				1735
				1736	u8 rx_pause_duration_low[0x20];
				1737
				1738	u8 tx_pause_high[0x20];
				1739
				1740	u8 tx_pause_low[0x20];
				1741
				1742	u8 tx_pause_duration_high[0x20];
				1743
				1744	u8 tx_pause_duration_low[0x20];
				1745
				1746	u8 rx_pause_transition_high[0x20];
				1747
				1748	u8 rx_pause_transition_low[0x20];
				1749
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	1750	u8 reserved_at_3c0[0x40];
				1751
				1752	u8 device_stall_minor_watermark_cnt_high[0x20];
				1753
				1754	u8 device_stall_minor_watermark_cnt_low[0x20];
				1755
				1756	u8 device_stall_critical_watermark_cnt_high[0x20];
				1757
				1758	u8 device_stall_critical_watermark_cnt_low[0x20];
				1759
				1760	u8 reserved_at_480[0x340];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1761	};
				1762
				1763	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
				1764	u8 port_transmit_wait_high[0x20];
				1765
				1766	u8 port_transmit_wait_low[0x20];
				1767
Gal Pressman	2dba079	2017-06-18 14:56:45 +0300	[diff] [blame]	1768	u8 reserved_at_40[0x100];
				1769
				1770	u8 rx_buffer_almost_full_high[0x20];
				1771
				1772	u8 rx_buffer_almost_full_low[0x20];
				1773
				1774	u8 rx_buffer_full_high[0x20];
				1775
				1776	u8 rx_buffer_full_low[0x20];
				1777
Talat Batheesh	0af5107	2018-05-17 11:14:18 +0300	[diff] [blame]	1778	u8 rx_icrc_encapsulated_high[0x20];
				1779
				1780	u8 rx_icrc_encapsulated_low[0x20];
				1781
				1782	u8 reserved_at_200[0x5c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1783	};
				1784
				1785	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
				1786	u8 dot3stats_alignment_errors_high[0x20];
				1787
				1788	u8 dot3stats_alignment_errors_low[0x20];
				1789
				1790	u8 dot3stats_fcs_errors_high[0x20];
				1791
				1792	u8 dot3stats_fcs_errors_low[0x20];
				1793
				1794	u8 dot3stats_single_collision_frames_high[0x20];
				1795
				1796	u8 dot3stats_single_collision_frames_low[0x20];
				1797
				1798	u8 dot3stats_multiple_collision_frames_high[0x20];
				1799
				1800	u8 dot3stats_multiple_collision_frames_low[0x20];
				1801
				1802	u8 dot3stats_sqe_test_errors_high[0x20];
				1803
				1804	u8 dot3stats_sqe_test_errors_low[0x20];
				1805
				1806	u8 dot3stats_deferred_transmissions_high[0x20];
				1807
				1808	u8 dot3stats_deferred_transmissions_low[0x20];
				1809
				1810	u8 dot3stats_late_collisions_high[0x20];
				1811
				1812	u8 dot3stats_late_collisions_low[0x20];
				1813
				1814	u8 dot3stats_excessive_collisions_high[0x20];
				1815
				1816	u8 dot3stats_excessive_collisions_low[0x20];
				1817
				1818	u8 dot3stats_internal_mac_transmit_errors_high[0x20];
				1819
				1820	u8 dot3stats_internal_mac_transmit_errors_low[0x20];
				1821
				1822	u8 dot3stats_carrier_sense_errors_high[0x20];
				1823
				1824	u8 dot3stats_carrier_sense_errors_low[0x20];
				1825
				1826	u8 dot3stats_frame_too_longs_high[0x20];
				1827
				1828	u8 dot3stats_frame_too_longs_low[0x20];
				1829
				1830	u8 dot3stats_internal_mac_receive_errors_high[0x20];
				1831
				1832	u8 dot3stats_internal_mac_receive_errors_low[0x20];
				1833
				1834	u8 dot3stats_symbol_errors_high[0x20];
				1835
				1836	u8 dot3stats_symbol_errors_low[0x20];
				1837
				1838	u8 dot3control_in_unknown_opcodes_high[0x20];
				1839
				1840	u8 dot3control_in_unknown_opcodes_low[0x20];
				1841
				1842	u8 dot3in_pause_frames_high[0x20];
				1843
				1844	u8 dot3in_pause_frames_low[0x20];
				1845
				1846	u8 dot3out_pause_frames_high[0x20];
				1847
				1848	u8 dot3out_pause_frames_low[0x20];
				1849
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1850	u8 reserved_at_400[0x3c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1851	};
				1852
				1853	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
				1854	u8 ether_stats_drop_events_high[0x20];
				1855
				1856	u8 ether_stats_drop_events_low[0x20];
				1857
				1858	u8 ether_stats_octets_high[0x20];
				1859
				1860	u8 ether_stats_octets_low[0x20];
				1861
				1862	u8 ether_stats_pkts_high[0x20];
				1863
				1864	u8 ether_stats_pkts_low[0x20];
				1865
				1866	u8 ether_stats_broadcast_pkts_high[0x20];
				1867
				1868	u8 ether_stats_broadcast_pkts_low[0x20];
				1869
				1870	u8 ether_stats_multicast_pkts_high[0x20];
				1871
				1872	u8 ether_stats_multicast_pkts_low[0x20];
				1873
				1874	u8 ether_stats_crc_align_errors_high[0x20];
				1875
				1876	u8 ether_stats_crc_align_errors_low[0x20];
				1877
				1878	u8 ether_stats_undersize_pkts_high[0x20];
				1879
				1880	u8 ether_stats_undersize_pkts_low[0x20];
				1881
				1882	u8 ether_stats_oversize_pkts_high[0x20];
				1883
				1884	u8 ether_stats_oversize_pkts_low[0x20];
				1885
				1886	u8 ether_stats_fragments_high[0x20];
				1887
				1888	u8 ether_stats_fragments_low[0x20];
				1889
				1890	u8 ether_stats_jabbers_high[0x20];
				1891
				1892	u8 ether_stats_jabbers_low[0x20];
				1893
				1894	u8 ether_stats_collisions_high[0x20];
				1895
				1896	u8 ether_stats_collisions_low[0x20];
				1897
				1898	u8 ether_stats_pkts64octets_high[0x20];
				1899
				1900	u8 ether_stats_pkts64octets_low[0x20];
				1901
				1902	u8 ether_stats_pkts65to127octets_high[0x20];
				1903
				1904	u8 ether_stats_pkts65to127octets_low[0x20];
				1905
				1906	u8 ether_stats_pkts128to255octets_high[0x20];
				1907
				1908	u8 ether_stats_pkts128to255octets_low[0x20];
				1909
				1910	u8 ether_stats_pkts256to511octets_high[0x20];
				1911
				1912	u8 ether_stats_pkts256to511octets_low[0x20];
				1913
				1914	u8 ether_stats_pkts512to1023octets_high[0x20];
				1915
				1916	u8 ether_stats_pkts512to1023octets_low[0x20];
				1917
				1918	u8 ether_stats_pkts1024to1518octets_high[0x20];
				1919
				1920	u8 ether_stats_pkts1024to1518octets_low[0x20];
				1921
				1922	u8 ether_stats_pkts1519to2047octets_high[0x20];
				1923
				1924	u8 ether_stats_pkts1519to2047octets_low[0x20];
				1925
				1926	u8 ether_stats_pkts2048to4095octets_high[0x20];
				1927
				1928	u8 ether_stats_pkts2048to4095octets_low[0x20];
				1929
				1930	u8 ether_stats_pkts4096to8191octets_high[0x20];
				1931
				1932	u8 ether_stats_pkts4096to8191octets_low[0x20];
				1933
				1934	u8 ether_stats_pkts8192to10239octets_high[0x20];
				1935
				1936	u8 ether_stats_pkts8192to10239octets_low[0x20];
				1937
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1938	u8 reserved_at_540[0x280];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1939	};
				1940
				1941	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
				1942	u8 if_in_octets_high[0x20];
				1943
				1944	u8 if_in_octets_low[0x20];
				1945
				1946	u8 if_in_ucast_pkts_high[0x20];
				1947
				1948	u8 if_in_ucast_pkts_low[0x20];
				1949
				1950	u8 if_in_discards_high[0x20];
				1951
				1952	u8 if_in_discards_low[0x20];
				1953
				1954	u8 if_in_errors_high[0x20];
				1955
				1956	u8 if_in_errors_low[0x20];
				1957
				1958	u8 if_in_unknown_protos_high[0x20];
				1959
				1960	u8 if_in_unknown_protos_low[0x20];
				1961
				1962	u8 if_out_octets_high[0x20];
				1963
				1964	u8 if_out_octets_low[0x20];
				1965
				1966	u8 if_out_ucast_pkts_high[0x20];
				1967
				1968	u8 if_out_ucast_pkts_low[0x20];
				1969
				1970	u8 if_out_discards_high[0x20];
				1971
				1972	u8 if_out_discards_low[0x20];
				1973
				1974	u8 if_out_errors_high[0x20];
				1975
				1976	u8 if_out_errors_low[0x20];
				1977
				1978	u8 if_in_multicast_pkts_high[0x20];
				1979
				1980	u8 if_in_multicast_pkts_low[0x20];
				1981
				1982	u8 if_in_broadcast_pkts_high[0x20];
				1983
				1984	u8 if_in_broadcast_pkts_low[0x20];
				1985
				1986	u8 if_out_multicast_pkts_high[0x20];
				1987
				1988	u8 if_out_multicast_pkts_low[0x20];
				1989
				1990	u8 if_out_broadcast_pkts_high[0x20];
				1991
				1992	u8 if_out_broadcast_pkts_low[0x20];
				1993
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	1994	u8 reserved_at_340[0x480];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	1995	};
				1996
				1997	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
				1998	u8 a_frames_transmitted_ok_high[0x20];
				1999
				2000	u8 a_frames_transmitted_ok_low[0x20];
				2001
				2002	u8 a_frames_received_ok_high[0x20];
				2003
				2004	u8 a_frames_received_ok_low[0x20];
				2005
				2006	u8 a_frame_check_sequence_errors_high[0x20];
				2007
				2008	u8 a_frame_check_sequence_errors_low[0x20];
				2009
				2010	u8 a_alignment_errors_high[0x20];
				2011
				2012	u8 a_alignment_errors_low[0x20];
				2013
				2014	u8 a_octets_transmitted_ok_high[0x20];
				2015
				2016	u8 a_octets_transmitted_ok_low[0x20];
				2017
				2018	u8 a_octets_received_ok_high[0x20];
				2019
				2020	u8 a_octets_received_ok_low[0x20];
				2021
				2022	u8 a_multicast_frames_xmitted_ok_high[0x20];
				2023
				2024	u8 a_multicast_frames_xmitted_ok_low[0x20];
				2025
				2026	u8 a_broadcast_frames_xmitted_ok_high[0x20];
				2027
				2028	u8 a_broadcast_frames_xmitted_ok_low[0x20];
				2029
				2030	u8 a_multicast_frames_received_ok_high[0x20];
				2031
				2032	u8 a_multicast_frames_received_ok_low[0x20];
				2033
				2034	u8 a_broadcast_frames_received_ok_high[0x20];
				2035
				2036	u8 a_broadcast_frames_received_ok_low[0x20];
				2037
				2038	u8 a_in_range_length_errors_high[0x20];
				2039
				2040	u8 a_in_range_length_errors_low[0x20];
				2041
				2042	u8 a_out_of_range_length_field_high[0x20];
				2043
				2044	u8 a_out_of_range_length_field_low[0x20];
				2045
				2046	u8 a_frame_too_long_errors_high[0x20];
				2047
				2048	u8 a_frame_too_long_errors_low[0x20];
				2049
				2050	u8 a_symbol_error_during_carrier_high[0x20];
				2051
				2052	u8 a_symbol_error_during_carrier_low[0x20];
				2053
				2054	u8 a_mac_control_frames_transmitted_high[0x20];
				2055
				2056	u8 a_mac_control_frames_transmitted_low[0x20];
				2057
				2058	u8 a_mac_control_frames_received_high[0x20];
				2059
				2060	u8 a_mac_control_frames_received_low[0x20];
				2061
				2062	u8 a_unsupported_opcodes_received_high[0x20];
				2063
				2064	u8 a_unsupported_opcodes_received_low[0x20];
				2065
				2066	u8 a_pause_mac_ctrl_frames_received_high[0x20];
				2067
				2068	u8 a_pause_mac_ctrl_frames_received_low[0x20];
				2069
				2070	u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
				2071
				2072	u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
				2073
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2074	u8 reserved_at_4c0[0x300];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2075	};
				2076
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	2077	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
				2078	u8 life_time_counter_high[0x20];
				2079
				2080	u8 life_time_counter_low[0x20];
				2081
				2082	u8 rx_errors[0x20];
				2083
				2084	u8 tx_errors[0x20];
				2085
				2086	u8 l0_to_recovery_eieos[0x20];
				2087
				2088	u8 l0_to_recovery_ts[0x20];
				2089
				2090	u8 l0_to_recovery_framing[0x20];
				2091
				2092	u8 l0_to_recovery_retrain[0x20];
				2093
				2094	u8 crc_error_dllp[0x20];
				2095
				2096	u8 crc_error_tlp[0x20];
				2097
Eran Ben Elisha	efae7f7	2017-05-12 02:47:02 +0300	[diff] [blame]	2098	u8 tx_overflow_buffer_pkt_high[0x20];
				2099
				2100	u8 tx_overflow_buffer_pkt_low[0x20];
Gal Pressman	5405fa2	2017-06-15 18:29:23 +0300	[diff] [blame]	2101
				2102	u8 outbound_stalled_reads[0x20];
				2103
				2104	u8 outbound_stalled_writes[0x20];
				2105
				2106	u8 outbound_stalled_reads_events[0x20];
				2107
				2108	u8 outbound_stalled_writes_events[0x20];
				2109
				2110	u8 reserved_at_200[0x5c0];
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	2111	};
				2112
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2113	struct mlx5_ifc_cmd_inter_comp_event_bits {
				2114	u8 command_completion_vector[0x20];
				2115
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2116	u8 reserved_at_20[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2117	};
				2118
				2119	struct mlx5_ifc_stall_vl_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2120	u8 reserved_at_0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2121	u8 port_num[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2122	u8 reserved_at_19[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2123	u8 vl[0x4];
				2124
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2125	u8 reserved_at_20[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2126	};
				2127
				2128	struct mlx5_ifc_db_bf_congestion_event_bits {
				2129	u8 event_subtype[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2130	u8 reserved_at_8[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2131	u8 congestion_level[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2132	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2133
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2134	u8 reserved_at_20[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2135	};
				2136
				2137	struct mlx5_ifc_gpio_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2138	u8 reserved_at_0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2139
				2140	u8 gpio_event_hi[0x20];
				2141
				2142	u8 gpio_event_lo[0x20];
				2143
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2144	u8 reserved_at_a0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2145	};
				2146
				2147	struct mlx5_ifc_port_state_change_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2148	u8 reserved_at_0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2149
				2150	u8 port_num[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2151	u8 reserved_at_44[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2152
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2153	u8 reserved_at_60[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2154	};
				2155
				2156	struct mlx5_ifc_dropped_packet_logged_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2157	u8 reserved_at_0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2158	};
				2159
				2160	enum {
				2161	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
				2162	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
				2163	};
				2164
				2165	struct mlx5_ifc_cq_error_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2166	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2167	u8 cqn[0x18];
				2168
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2169	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2170
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2171	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2172	u8 syndrome[0x8];
				2173
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2174	u8 reserved_at_60[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2175	};
				2176
				2177	struct mlx5_ifc_rdma_page_fault_event_bits {
				2178	u8 bytes_committed[0x20];
				2179
				2180	u8 r_key[0x20];
				2181
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2182	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2183	u8 packet_len[0x10];
				2184
				2185	u8 rdma_op_len[0x20];
				2186
				2187	u8 rdma_va[0x40];
				2188
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2189	u8 reserved_at_c0[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2190	u8 rdma[0x1];
				2191	u8 write[0x1];
				2192	u8 requestor[0x1];
				2193	u8 qp_number[0x18];
				2194	};
				2195
				2196	struct mlx5_ifc_wqe_associated_page_fault_event_bits {
				2197	u8 bytes_committed[0x20];
				2198
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2199	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2200	u8 wqe_index[0x10];
				2201
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2202	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2203	u8 len[0x10];
				2204
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2205	u8 reserved_at_60[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2206
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2207	u8 reserved_at_c0[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2208	u8 rdma[0x1];
				2209	u8 write_read[0x1];
				2210	u8 requestor[0x1];
				2211	u8 qpn[0x18];
				2212	};
				2213
				2214	struct mlx5_ifc_qp_events_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2215	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2216
				2217	u8 type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2218	u8 reserved_at_a8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2219
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2220	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2221	u8 qpn_rqn_sqn[0x18];
				2222	};
				2223
				2224	struct mlx5_ifc_dct_events_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2225	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2226
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2227	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2228	u8 dct_number[0x18];
				2229	};
				2230
				2231	struct mlx5_ifc_comp_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2232	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2233
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2234	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2235	u8 cq_number[0x18];
				2236	};
				2237
				2238	enum {
				2239	MLX5_QPC_STATE_RST = 0x0,
				2240	MLX5_QPC_STATE_INIT = 0x1,
				2241	MLX5_QPC_STATE_RTR = 0x2,
				2242	MLX5_QPC_STATE_RTS = 0x3,
				2243	MLX5_QPC_STATE_SQER = 0x4,
				2244	MLX5_QPC_STATE_ERR = 0x6,
				2245	MLX5_QPC_STATE_SQD = 0x7,
				2246	MLX5_QPC_STATE_SUSPENDED = 0x9,
				2247	};
				2248
				2249	enum {
				2250	MLX5_QPC_ST_RC = 0x0,
				2251	MLX5_QPC_ST_UC = 0x1,
				2252	MLX5_QPC_ST_UD = 0x2,
				2253	MLX5_QPC_ST_XRC = 0x3,
				2254	MLX5_QPC_ST_DCI = 0x5,
				2255	MLX5_QPC_ST_QP0 = 0x7,
				2256	MLX5_QPC_ST_QP1 = 0x8,
				2257	MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
				2258	MLX5_QPC_ST_REG_UMR = 0xc,
				2259	};
				2260
				2261	enum {
				2262	MLX5_QPC_PM_STATE_ARMED = 0x0,
				2263	MLX5_QPC_PM_STATE_REARM = 0x1,
				2264	MLX5_QPC_PM_STATE_RESERVED = 0x2,
				2265	MLX5_QPC_PM_STATE_MIGRATED = 0x3,
				2266	};
				2267
				2268	enum {
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	2269	MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
				2270	};
				2271
				2272	enum {
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2273	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
				2274	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
				2275	};
				2276
				2277	enum {
				2278	MLX5_QPC_MTU_256_BYTES = 0x1,
				2279	MLX5_QPC_MTU_512_BYTES = 0x2,
				2280	MLX5_QPC_MTU_1K_BYTES = 0x3,
				2281	MLX5_QPC_MTU_2K_BYTES = 0x4,
				2282	MLX5_QPC_MTU_4K_BYTES = 0x5,
				2283	MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
				2284	};
				2285
				2286	enum {
				2287	MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
				2288	MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
				2289	MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
				2290	MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
				2291	MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
				2292	MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
				2293	MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
				2294	MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
				2295	};
				2296
				2297	enum {
				2298	MLX5_QPC_CS_REQ_DISABLE = 0x0,
				2299	MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
				2300	MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
				2301	};
				2302
				2303	enum {
				2304	MLX5_QPC_CS_RES_DISABLE = 0x0,
				2305	MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
				2306	MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
				2307	};
				2308
				2309	struct mlx5_ifc_qpc_bits {
				2310	u8 state[0x4];
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	2311	u8 lag_tx_port_affinity[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2312	u8 st[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2313	u8 reserved_at_10[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2314	u8 pm_state[0x2];
Danit Goldberg	3fd3c80	2018-11-30 13:22:04 +0200	[diff] [blame]	2315	u8 reserved_at_15[0x1];
				2316	u8 req_e2e_credit_mode[0x2];
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	2317	u8 offload_type[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2318	u8 end_padding_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2319	u8 reserved_at_1e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2320
				2321	u8 wq_signature[0x1];
				2322	u8 block_lb_mc[0x1];
				2323	u8 atomic_like_write_en[0x1];
				2324	u8 latency_sensitive[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2325	u8 reserved_at_24[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2326	u8 drain_sigerr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2327	u8 reserved_at_26[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2328	u8 pd[0x18];
				2329
				2330	u8 mtu[0x3];
				2331	u8 log_msg_max[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2332	u8 reserved_at_48[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2333	u8 log_rq_size[0x4];
				2334	u8 log_rq_stride[0x3];
				2335	u8 no_sq[0x1];
				2336	u8 log_sq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2337	u8 reserved_at_55[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2338	u8 rlky[0x1];
Erez Shitrit	1015c2e	2016-02-21 16:27:16 +0200	[diff] [blame]	2339	u8 ulp_stateless_offload_mode[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2340
				2341	u8 counter_set_id[0x8];
				2342	u8 uar_page[0x18];
				2343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2344	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2345	u8 user_index[0x18];
				2346
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2347	u8 reserved_at_a0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2348	u8 log_page_size[0x5];
				2349	u8 remote_qpn[0x18];
				2350
				2351	struct mlx5_ifc_ads_bits primary_address_path;
				2352
				2353	struct mlx5_ifc_ads_bits secondary_address_path;
				2354
				2355	u8 log_ack_req_freq[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2356	u8 reserved_at_384[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2357	u8 log_sra_max[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2358	u8 reserved_at_38b[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2359	u8 retry_count[0x3];
				2360	u8 rnr_retry[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2361	u8 reserved_at_393[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2362	u8 fre[0x1];
				2363	u8 cur_rnr_retry[0x3];
				2364	u8 cur_retry_count[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2365	u8 reserved_at_39b[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2366
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2367	u8 reserved_at_3a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2368
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2369	u8 reserved_at_3c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2370	u8 next_send_psn[0x18];
				2371
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2372	u8 reserved_at_3e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2373	u8 cqn_snd[0x18];
				2374
Saeed Mahameed	09a7d9e	2016-07-19 01:17:59 +0300	[diff] [blame]	2375	u8 reserved_at_400[0x8];
				2376	u8 deth_sqpn[0x18];
				2377
				2378	u8 reserved_at_420[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2379
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2380	u8 reserved_at_440[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2381	u8 last_acked_psn[0x18];
				2382
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2383	u8 reserved_at_460[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2384	u8 ssn[0x18];
				2385
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2386	u8 reserved_at_480[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2387	u8 log_rra_max[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2388	u8 reserved_at_48b[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2389	u8 atomic_mode[0x4];
				2390	u8 rre[0x1];
				2391	u8 rwe[0x1];
				2392	u8 rae[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2393	u8 reserved_at_493[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2394	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2395	u8 reserved_at_49a[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2396	u8 cd_slave_receive[0x1];
				2397	u8 cd_slave_send[0x1];
				2398	u8 cd_master[0x1];
				2399
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2400	u8 reserved_at_4a0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2401	u8 min_rnr_nak[0x5];
				2402	u8 next_rcv_psn[0x18];
				2403
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2404	u8 reserved_at_4c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2405	u8 xrcd[0x18];
				2406
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2407	u8 reserved_at_4e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2408	u8 cqn_rcv[0x18];
				2409
				2410	u8 dbr_addr[0x40];
				2411
				2412	u8 q_key[0x20];
				2413
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2414	u8 reserved_at_560[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2415	u8 rq_type[0x3];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2416	u8 srqn_rmpn_xrqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2417
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2418	u8 reserved_at_580[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2419	u8 rmsn[0x18];
				2420
				2421	u8 hw_sq_wqebb_counter[0x10];
				2422	u8 sw_sq_wqebb_counter[0x10];
				2423
				2424	u8 hw_rq_counter[0x20];
				2425
				2426	u8 sw_rq_counter[0x20];
				2427
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2428	u8 reserved_at_600[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2429
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2430	u8 reserved_at_620[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2431	u8 cgs[0x1];
				2432	u8 cs_req[0x8];
				2433	u8 cs_res[0x8];
				2434
				2435	u8 dc_access_key[0x40];
				2436
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	2437	u8 reserved_at_680[0x3];
				2438	u8 dbr_umem_valid[0x1];
				2439
				2440	u8 reserved_at_684[0xbc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2441	};
				2442
				2443	struct mlx5_ifc_roce_addr_layout_bits {
				2444	u8 source_l3_address[16][0x8];
				2445
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2446	u8 reserved_at_80[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2447	u8 vlan_valid[0x1];
				2448	u8 vlan_id[0xc];
				2449	u8 source_mac_47_32[0x10];
				2450
				2451	u8 source_mac_31_0[0x20];
				2452
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2453	u8 reserved_at_c0[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2454	u8 roce_l3_type[0x4];
				2455	u8 roce_version[0x8];
				2456
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2457	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2458	};
				2459
				2460	union mlx5_ifc_hca_cap_union_bits {
				2461	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
				2462	struct mlx5_ifc_odp_cap_bits odp_cap;
				2463	struct mlx5_ifc_atomic_caps_bits atomic_caps;
				2464	struct mlx5_ifc_roce_cap_bits roce_cap;
				2465	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
				2466	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
Saeed Mahameed	495716b	2015-12-01 18:03:19 +0200	[diff] [blame]	2467	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	2468	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
Sagi Grimberg	3f0393a	2016-02-23 10:25:23 +0200	[diff] [blame]	2469	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2470	struct mlx5_ifc_qos_cap_bits qos_cap;
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	2471	struct mlx5_ifc_fpga_cap_bits fpga_cap;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2472	u8 reserved_at_0[0x8000];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2473	};
				2474
				2475	enum {
				2476	MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
				2477	MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
				2478	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2479	MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	2480	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	2481	MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	2482	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2483	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
				2484	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	2485	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
				2486	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2487	};
				2488
				2489	struct mlx5_ifc_vlan_bits {
				2490	u8 ethtype[0x10];
				2491	u8 prio[0x3];
				2492	u8 cfi[0x1];
				2493	u8 vid[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2494	};
				2495
				2496	struct mlx5_ifc_flow_context_bits {
Or Gerlitz	0c06897	2018-01-28 20:14:20 +0200	[diff] [blame]	2497	struct mlx5_ifc_vlan_bits push_vlan;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2498
				2499	u8 group_id[0x20];
				2500
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2501	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2502	u8 flow_tag[0x18];
				2503
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2504	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2505	u8 action[0x10];
				2506
Eli Britstein	1b11549	2018-12-10 13:15:14 -0800	[diff] [blame]	2507	u8 extended_destination[0x1];
				2508	u8 reserved_at_80[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2509	u8 destination_list_size[0x18];
				2510
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2511	u8 reserved_at_a0[0x8];
				2512	u8 flow_counter_list_size[0x18];
				2513
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	2514	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	2515
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	2516	u8 modify_header_id[0x20];
				2517
Jianbo Liu	8da6fe2	2018-07-16 18:35:32 -0700	[diff] [blame]	2518	struct mlx5_ifc_vlan_bits push_vlan_2;
				2519
				2520	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2521
				2522	struct mlx5_ifc_fte_match_param_bits match_value;
				2523
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2524	u8 reserved_at_1200[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2525
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	2526	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2527	};
				2528
				2529	enum {
				2530	MLX5_XRC_SRQC_STATE_GOOD = 0x0,
				2531	MLX5_XRC_SRQC_STATE_ERROR = 0x1,
				2532	};
				2533
				2534	struct mlx5_ifc_xrc_srqc_bits {
				2535	u8 state[0x4];
				2536	u8 log_xrc_srq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2537	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2538
				2539	u8 wq_signature[0x1];
				2540	u8 cont_srq[0x1];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	2541	u8 reserved_at_22[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2542	u8 rlky[0x1];
				2543	u8 basic_cyclic_rcv_wqe[0x1];
				2544	u8 log_rq_stride[0x3];
				2545	u8 xrcd[0x18];
				2546
				2547	u8 page_offset[0x6];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	2548	u8 reserved_at_46[0x1];
				2549	u8 dbr_umem_valid[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2550	u8 cqn[0x18];
				2551
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2552	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2553
				2554	u8 user_index_equal_xrc_srqn[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2555	u8 reserved_at_81[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2556	u8 log_page_size[0x6];
				2557	u8 user_index[0x18];
				2558
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2559	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2560
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2561	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2562	u8 pd[0x18];
				2563
				2564	u8 lwm[0x10];
				2565	u8 wqe_cnt[0x10];
				2566
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2567	u8 reserved_at_100[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2568
				2569	u8 db_record_addr_h[0x20];
				2570
				2571	u8 db_record_addr_l[0x1e];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2572	u8 reserved_at_17e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2573
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2574	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2575	};
				2576
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	2577	struct mlx5_ifc_vnic_diagnostic_statistics_bits {
				2578	u8 counter_error_queues[0x20];
				2579
				2580	u8 total_error_queues[0x20];
				2581
				2582	u8 send_queue_priority_update_flow[0x20];
				2583
				2584	u8 reserved_at_60[0x20];
				2585
				2586	u8 nic_receive_steering_discard[0x40];
				2587
				2588	u8 receive_discard_vport_down[0x40];
				2589
				2590	u8 transmit_discard_vport_down[0x40];
				2591
				2592	u8 reserved_at_140[0xec0];
				2593	};
				2594
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2595	struct mlx5_ifc_traffic_counter_bits {
				2596	u8 packets[0x40];
				2597
				2598	u8 octets[0x40];
				2599	};
				2600
				2601	struct mlx5_ifc_tisc_bits {
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	2602	u8 strict_lag_tx_port_affinity[0x1];
				2603	u8 reserved_at_1[0x3];
				2604	u8 lag_tx_port_affinity[0x04];
				2605
				2606	u8 reserved_at_8[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2607	u8 prio[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2608	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2609
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2610	u8 reserved_at_20[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2611
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2612	u8 reserved_at_120[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2613	u8 transport_domain[0x18];
				2614
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	2615	u8 reserved_at_140[0x8];
				2616	u8 underlay_qpn[0x18];
				2617	u8 reserved_at_160[0x3a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2618	};
				2619
				2620	enum {
				2621	MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
				2622	MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
				2623	};
				2624
				2625	enum {
				2626	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
				2627	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
				2628	};
				2629
				2630	enum {
Saeed Mahameed	2be6967	2015-07-23 23:35:56 +0300	[diff] [blame]	2631	MLX5_RX_HASH_FN_NONE = 0x0,
				2632	MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
				2633	MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2634	};
				2635
				2636	enum {
Mark Bloch	5d773ff	2018-09-17 13:30:46 +0300	[diff] [blame]	2637	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
				2638	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2639	};
				2640
				2641	struct mlx5_ifc_tirc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2642	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2643
				2644	u8 disp_type[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2645	u8 reserved_at_24[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2646
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2647	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2648
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2649	u8 reserved_at_80[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2650	u8 lro_timeout_period_usecs[0x10];
				2651	u8 lro_enable_mask[0x4];
				2652	u8 lro_max_ip_payload_size[0x8];
				2653
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2654	u8 reserved_at_a0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2655
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2656	u8 reserved_at_e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2657	u8 inline_rqn[0x18];
				2658
				2659	u8 rx_hash_symmetric[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2660	u8 reserved_at_101[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2661	u8 tunneled_offload_en[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2662	u8 reserved_at_103[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2663	u8 indirect_table[0x18];
				2664
				2665	u8 rx_hash_fn[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2666	u8 reserved_at_124[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2667	u8 self_lb_block[0x2];
				2668	u8 transport_domain[0x18];
				2669
				2670	u8 rx_hash_toeplitz_key[10][0x20];
				2671
				2672	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
				2673
				2674	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
				2675
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2676	u8 reserved_at_2c0[0x4c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2677	};
				2678
				2679	enum {
				2680	MLX5_SRQC_STATE_GOOD = 0x0,
				2681	MLX5_SRQC_STATE_ERROR = 0x1,
				2682	};
				2683
				2684	struct mlx5_ifc_srqc_bits {
				2685	u8 state[0x4];
				2686	u8 log_srq_size[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2687	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2688
				2689	u8 wq_signature[0x1];
				2690	u8 cont_srq[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2691	u8 reserved_at_22[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2692	u8 rlky[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2693	u8 reserved_at_24[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2694	u8 log_rq_stride[0x3];
				2695	u8 xrcd[0x18];
				2696
				2697	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2698	u8 reserved_at_46[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2699	u8 cqn[0x18];
				2700
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2701	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2702
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2703	u8 reserved_at_80[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2704	u8 log_page_size[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2705	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2706
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2707	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2708
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2709	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2710	u8 pd[0x18];
				2711
				2712	u8 lwm[0x10];
				2713	u8 wqe_cnt[0x10];
				2714
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2715	u8 reserved_at_100[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2716
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	2717	u8 dbr_addr[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2718
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2719	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2720	};
				2721
				2722	enum {
				2723	MLX5_SQC_STATE_RST = 0x0,
				2724	MLX5_SQC_STATE_RDY = 0x1,
				2725	MLX5_SQC_STATE_ERR = 0x3,
				2726	};
				2727
				2728	struct mlx5_ifc_sqc_bits {
				2729	u8 rlky[0x1];
				2730	u8 cd_master[0x1];
				2731	u8 fre[0x1];
				2732	u8 flush_in_error_en[0x1];
Bodong Wang	795b609	2017-08-17 15:52:34 +0300	[diff] [blame]	2733	u8 allow_multi_pkt_send_wqe[0x1];
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	2734	u8 min_wqe_inline_mode[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2735	u8 state[0x4];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	2736	u8 reg_umr[0x1];
Ilan Tayari	547eede	2017-04-18 16:04:28 +0300	[diff] [blame]	2737	u8 allow_swp[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2738	u8 hairpin[0x1];
				2739	u8 reserved_at_f[0x11];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2740
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2741	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2742	u8 user_index[0x18];
				2743
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2744	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2745	u8 cqn[0x18];
				2746
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2747	u8 reserved_at_60[0x8];
				2748	u8 hairpin_peer_rq[0x18];
				2749
				2750	u8 reserved_at_80[0x10];
				2751	u8 hairpin_peer_vhca[0x10];
				2752
				2753	u8 reserved_at_a0[0x50];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2754
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	2755	u8 packet_pacing_rate_limit_index[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2756	u8 tis_lst_sz[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2757	u8 reserved_at_110[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2758
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2759	u8 reserved_at_120[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2760
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2761	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2762	u8 tis_num_0[0x18];
				2763
				2764	struct mlx5_ifc_wq_bits wq;
				2765	};
				2766
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	2767	enum {
				2768	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
				2769	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
				2770	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
				2771	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
				2772	};
				2773
				2774	struct mlx5_ifc_scheduling_context_bits {
				2775	u8 element_type[0x8];
				2776	u8 reserved_at_8[0x18];
				2777
				2778	u8 element_attributes[0x20];
				2779
				2780	u8 parent_element_id[0x20];
				2781
				2782	u8 reserved_at_60[0x40];
				2783
				2784	u8 bw_share[0x20];
				2785
				2786	u8 max_average_bw[0x20];
				2787
				2788	u8 reserved_at_e0[0x120];
				2789	};
				2790
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2791	struct mlx5_ifc_rqtc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2792	u8 reserved_at_0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2794	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2795	u8 rqt_max_size[0x10];
				2796
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2797	u8 reserved_at_c0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2798	u8 rqt_actual_size[0x10];
				2799
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2800	u8 reserved_at_e0[0x6a0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2801
				2802	struct mlx5_ifc_rq_num_bits rq_num[0];
				2803	};
				2804
				2805	enum {
				2806	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
				2807	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
				2808	};
				2809
				2810	enum {
				2811	MLX5_RQC_STATE_RST = 0x0,
				2812	MLX5_RQC_STATE_RDY = 0x1,
				2813	MLX5_RQC_STATE_ERR = 0x3,
				2814	};
				2815
				2816	struct mlx5_ifc_rqc_bits {
				2817	u8 rlky[0x1];
Maor Gottlieb	03404e8	2017-05-30 10:29:13 +0300	[diff] [blame]	2818	u8 delay_drop_en[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	2819	u8 scatter_fcs[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2820	u8 vsd[0x1];
				2821	u8 mem_rq_type[0x4];
				2822	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2823	u8 reserved_at_c[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2824	u8 flush_in_error_en[0x1];
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2825	u8 hairpin[0x1];
				2826	u8 reserved_at_f[0x11];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2827
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2828	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2829	u8 user_index[0x18];
				2830
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2831	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2832	u8 cqn[0x18];
				2833
				2834	u8 counter_set_id[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2835	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2836
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2837	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2838	u8 rmpn[0x18];
				2839
Or Gerlitz	40817cd	2017-06-25 12:38:45 +0300	[diff] [blame]	2840	u8 reserved_at_a0[0x8];
				2841	u8 hairpin_peer_sq[0x18];
				2842
				2843	u8 reserved_at_c0[0x10];
				2844	u8 hairpin_peer_vhca[0x10];
				2845
				2846	u8 reserved_at_e0[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2847
				2848	struct mlx5_ifc_wq_bits wq;
				2849	};
				2850
				2851	enum {
				2852	MLX5_RMPC_STATE_RDY = 0x1,
				2853	MLX5_RMPC_STATE_ERR = 0x3,
				2854	};
				2855
				2856	struct mlx5_ifc_rmpc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2857	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2858	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2859	u8 reserved_at_c[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2860
				2861	u8 basic_cyclic_rcv_wqe[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2862	u8 reserved_at_21[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2863
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2864	u8 reserved_at_40[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2865
				2866	struct mlx5_ifc_wq_bits wq;
				2867	};
				2868
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2869	struct mlx5_ifc_nic_vport_context_bits {
Hadar Hen Zion	cff92d7	2016-07-24 16:12:40 +0300	[diff] [blame]	2870	u8 reserved_at_0[0x5];
				2871	u8 min_wqe_inline_mode[0x3];
Huy Nguyen	bded747	2017-05-30 09:42:53 +0300	[diff] [blame]	2872	u8 reserved_at_8[0x15];
				2873	u8 disable_mc_local_lb[0x1];
				2874	u8 disable_uc_local_lb[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2875	u8 roce_en[0x1];
				2876
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2877	u8 arm_change_event[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2878	u8 reserved_at_21[0x1a];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2879	u8 event_on_mtu[0x1];
				2880	u8 event_on_promisc_change[0x1];
				2881	u8 event_on_vlan_change[0x1];
				2882	u8 event_on_mc_address_change[0x1];
				2883	u8 event_on_uc_address_change[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2884
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	2885	u8 reserved_at_40[0xc];
				2886
				2887	u8 affiliation_criteria[0x4];
				2888	u8 affiliated_vhca_id[0x10];
				2889
				2890	u8 reserved_at_60[0xd0];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2891
				2892	u8 mtu[0x10];
				2893
Achiad Shochat	9efa752	2015-12-23 18:47:20 +0200	[diff] [blame]	2894	u8 system_image_guid[0x40];
				2895	u8 port_guid[0x40];
				2896	u8 node_guid[0x40];
				2897
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2898	u8 reserved_at_200[0x140];
Achiad Shochat	9efa752	2015-12-23 18:47:20 +0200	[diff] [blame]	2899	u8 qkey_violation_counter[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2900	u8 reserved_at_350[0x430];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	2901
				2902	u8 promisc_uc[0x1];
				2903	u8 promisc_mc[0x1];
				2904	u8 promisc_all[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2905	u8 reserved_at_783[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2906	u8 allowed_list_type[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2907	u8 reserved_at_788[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2908	u8 allowed_list_size[0xc];
				2909
				2910	struct mlx5_ifc_mac_address_layout_bits permanent_address;
				2911
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2912	u8 reserved_at_7e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2913
				2914	u8 current_uc_mac_address[0][0x40];
				2915	};
				2916
				2917	enum {
				2918	MLX5_MKC_ACCESS_MODE_PA = 0x0,
				2919	MLX5_MKC_ACCESS_MODE_MTT = 0x1,
				2920	MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	2921	MLX5_MKC_ACCESS_MODE_KSM = 0x3,
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2922	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2923	};
				2924
				2925	struct mlx5_ifc_mkc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2926	u8 reserved_at_0[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2927	u8 free[0x1];
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2928	u8 reserved_at_2[0x1];
				2929	u8 access_mode_4_2[0x3];
				2930	u8 reserved_at_6[0x7];
				2931	u8 relaxed_ordering_write[0x1];
				2932	u8 reserved_at_e[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2933	u8 small_fence_on_rdma_read_response[0x1];
				2934	u8 umr_en[0x1];
				2935	u8 a[0x1];
				2936	u8 rw[0x1];
				2937	u8 rr[0x1];
				2938	u8 lw[0x1];
				2939	u8 lr[0x1];
Ariel Levkovich	cdbd0d2	2018-04-05 18:53:28 +0300	[diff] [blame]	2940	u8 access_mode_1_0[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2941	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2942
				2943	u8 qpn[0x18];
				2944	u8 mkey_7_0[0x8];
				2945
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2946	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2947
				2948	u8 length64[0x1];
				2949	u8 bsf_en[0x1];
				2950	u8 sync_umr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2951	u8 reserved_at_63[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2952	u8 expected_sigerr_count[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2953	u8 reserved_at_66[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2954	u8 en_rinval[0x1];
				2955	u8 pd[0x18];
				2956
				2957	u8 start_addr[0x40];
				2958
				2959	u8 len[0x40];
				2960
				2961	u8 bsf_octword_size[0x20];
				2962
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2963	u8 reserved_at_120[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2964
				2965	u8 translations_octword_size[0x20];
				2966
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2967	u8 reserved_at_1c0[0x1b];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2968	u8 log_page_size[0x5];
				2969
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2970	u8 reserved_at_1e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2971	};
				2972
				2973	struct mlx5_ifc_pkey_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2974	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2975	u8 pkey[0x10];
				2976	};
				2977
				2978	struct mlx5_ifc_array128_auto_bits {
				2979	u8 array128_auto[16][0x8];
				2980	};
				2981
				2982	struct mlx5_ifc_hca_vport_context_bits {
				2983	u8 field_select[0x20];
				2984
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2985	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2986
				2987	u8 sm_virt_aware[0x1];
				2988	u8 has_smi[0x1];
				2989	u8 has_raw[0x1];
				2990	u8 grh_required[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2991	u8 reserved_at_104[0xc];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	2992	u8 port_physical_state[0x4];
				2993	u8 vport_state_policy[0x4];
				2994	u8 port_state[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	2995	u8 vport_state[0x4];
				2996
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	2997	u8 reserved_at_120[0x20];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	2998
				2999	u8 system_image_guid[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3000
				3001	u8 port_guid[0x40];
				3002
				3003	u8 node_guid[0x40];
				3004
				3005	u8 cap_mask1[0x20];
				3006
				3007	u8 cap_mask1_field_select[0x20];
				3008
				3009	u8 cap_mask2[0x20];
				3010
				3011	u8 cap_mask2_field_select[0x20];
				3012
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3013	u8 reserved_at_280[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3014
				3015	u8 lid[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3016	u8 reserved_at_310[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3017	u8 init_type_reply[0x4];
				3018	u8 lmc[0x3];
				3019	u8 subnet_timeout[0x5];
				3020
				3021	u8 sm_lid[0x10];
				3022	u8 sm_sl[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3023	u8 reserved_at_334[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3024
				3025	u8 qkey_violation_counter[0x10];
				3026	u8 pkey_violation_counter[0x10];
				3027
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3028	u8 reserved_at_360[0xca0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3029	};
				3030
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3031	struct mlx5_ifc_esw_vport_context_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3032	u8 reserved_at_0[0x3];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3033	u8 vport_svlan_strip[0x1];
				3034	u8 vport_cvlan_strip[0x1];
				3035	u8 vport_svlan_insert[0x1];
				3036	u8 vport_cvlan_insert[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3037	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3038
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3039	u8 reserved_at_20[0x20];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3040
				3041	u8 svlan_cfi[0x1];
				3042	u8 svlan_pcp[0x3];
				3043	u8 svlan_id[0xc];
				3044	u8 cvlan_cfi[0x1];
				3045	u8 cvlan_pcp[0x3];
				3046	u8 cvlan_id[0xc];
				3047
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3048	u8 reserved_at_60[0x7a0];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	3049	};
				3050
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3051	enum {
				3052	MLX5_EQC_STATUS_OK = 0x0,
				3053	MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
				3054	};
				3055
				3056	enum {
				3057	MLX5_EQC_ST_ARMED = 0x9,
				3058	MLX5_EQC_ST_FIRED = 0xa,
				3059	};
				3060
				3061	struct mlx5_ifc_eqc_bits {
				3062	u8 status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3063	u8 reserved_at_4[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3064	u8 ec[0x1];
				3065	u8 oi[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3066	u8 reserved_at_f[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3067	u8 st[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3068	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3069
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3070	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3071
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3072	u8 reserved_at_40[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3073	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3074	u8 reserved_at_5a[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3075
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3076	u8 reserved_at_60[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3077	u8 log_eq_size[0x5];
				3078	u8 uar_page[0x18];
				3079
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3080	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3081
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3082	u8 reserved_at_a0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3083	u8 intr[0x8];
				3084
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3085	u8 reserved_at_c0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3086	u8 log_page_size[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3087	u8 reserved_at_c8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3088
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3089	u8 reserved_at_e0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3090
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3091	u8 reserved_at_140[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3092	u8 consumer_counter[0x18];
				3093
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3094	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3095	u8 producer_counter[0x18];
				3096
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3097	u8 reserved_at_180[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3098	};
				3099
				3100	enum {
				3101	MLX5_DCTC_STATE_ACTIVE = 0x0,
				3102	MLX5_DCTC_STATE_DRAINING = 0x1,
				3103	MLX5_DCTC_STATE_DRAINED = 0x2,
				3104	};
				3105
				3106	enum {
				3107	MLX5_DCTC_CS_RES_DISABLE = 0x0,
				3108	MLX5_DCTC_CS_RES_NA = 0x1,
				3109	MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
				3110	};
				3111
				3112	enum {
				3113	MLX5_DCTC_MTU_256_BYTES = 0x1,
				3114	MLX5_DCTC_MTU_512_BYTES = 0x2,
				3115	MLX5_DCTC_MTU_1K_BYTES = 0x3,
				3116	MLX5_DCTC_MTU_2K_BYTES = 0x4,
				3117	MLX5_DCTC_MTU_4K_BYTES = 0x5,
				3118	};
				3119
				3120	struct mlx5_ifc_dctc_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3121	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3122	u8 state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3123	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3124
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3125	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3126	u8 user_index[0x18];
				3127
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3128	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3129	u8 cqn[0x18];
				3130
				3131	u8 counter_set_id[0x8];
				3132	u8 atomic_mode[0x4];
				3133	u8 rre[0x1];
				3134	u8 rwe[0x1];
				3135	u8 rae[0x1];
				3136	u8 atomic_like_write_en[0x1];
				3137	u8 latency_sensitive[0x1];
				3138	u8 rlky[0x1];
				3139	u8 free_ar[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3140	u8 reserved_at_73[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3141
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3142	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3143	u8 cs_res[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3144	u8 reserved_at_90[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3145	u8 min_rnr_nak[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3146	u8 reserved_at_98[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3147
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3148	u8 reserved_at_a0[0x8];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3149	u8 srqn_xrqn[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3150
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3151	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3152	u8 pd[0x18];
				3153
				3154	u8 tclass[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3155	u8 reserved_at_e8[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3156	u8 flow_label[0x14];
				3157
				3158	u8 dc_access_key[0x40];
				3159
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3160	u8 reserved_at_140[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3161	u8 mtu[0x3];
				3162	u8 port[0x8];
				3163	u8 pkey_index[0x10];
				3164
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3165	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3166	u8 my_addr_index[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3167	u8 reserved_at_170[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3168	u8 hop_limit[0x8];
				3169
				3170	u8 dc_access_key_violation_count[0x20];
				3171
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3172	u8 reserved_at_1a0[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3173	u8 dei_cfi[0x1];
				3174	u8 eth_prio[0x3];
				3175	u8 ecn[0x2];
				3176	u8 dscp[0x6];
				3177
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3178	u8 reserved_at_1c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3179	};
				3180
				3181	enum {
				3182	MLX5_CQC_STATUS_OK = 0x0,
				3183	MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
				3184	MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
				3185	};
				3186
				3187	enum {
				3188	MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
				3189	MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
				3190	};
				3191
				3192	enum {
				3193	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
				3194	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
				3195	MLX5_CQC_ST_FIRED = 0xa,
				3196	};
				3197
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3198	enum {
				3199	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
				3200	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3201	MLX5_CQ_PERIOD_NUM_MODES
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3202	};
				3203
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3204	struct mlx5_ifc_cqc_bits {
				3205	u8 status[0x4];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	3206	u8 reserved_at_4[0x2];
				3207	u8 dbr_umem_valid[0x1];
				3208	u8 reserved_at_7[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3209	u8 cqe_sz[0x3];
				3210	u8 cc[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3211	u8 reserved_at_c[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3212	u8 scqe_break_moderation_en[0x1];
				3213	u8 oi[0x1];
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3214	u8 cq_period_mode[0x2];
				3215	u8 cqe_comp_en[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3216	u8 mini_cqe_res_format[0x2];
				3217	u8 st[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3218	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3219
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3220	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3221
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3222	u8 reserved_at_40[0x14];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3223	u8 page_offset[0x6];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3224	u8 reserved_at_5a[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3225
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3226	u8 reserved_at_60[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3227	u8 log_cq_size[0x5];
				3228	u8 uar_page[0x18];
				3229
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3230	u8 reserved_at_80[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3231	u8 cq_period[0xc];
				3232	u8 cq_max_count[0x10];
				3233
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3234	u8 reserved_at_a0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3235	u8 c_eqn[0x8];
				3236
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3237	u8 reserved_at_c0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3238	u8 log_page_size[0x5];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3239	u8 reserved_at_c8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3240
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3241	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3242
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3243	u8 reserved_at_100[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3244	u8 last_notified_index[0x18];
				3245
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3246	u8 reserved_at_120[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3247	u8 last_solicit_index[0x18];
				3248
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3249	u8 reserved_at_140[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3250	u8 consumer_counter[0x18];
				3251
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3252	u8 reserved_at_160[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3253	u8 producer_counter[0x18];
				3254
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3255	u8 reserved_at_180[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3256
				3257	u8 dbr_addr[0x40];
				3258	};
				3259
				3260	union mlx5_ifc_cong_control_roce_ecn_auto_bits {
				3261	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
				3262	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
				3263	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3264	u8 reserved_at_0[0x800];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3265	};
				3266
				3267	struct mlx5_ifc_query_adapter_param_block_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3268	u8 reserved_at_0[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3269
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3270	u8 reserved_at_c0[0x8];
Majd Dibbiny	211e6c8	2015-06-04 19:30:42 +0300	[diff] [blame]	3271	u8 ieee_vendor_id[0x18];
				3272
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3273	u8 reserved_at_e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3274	u8 vsd_vendor_id[0x10];
				3275
				3276	u8 vsd[208][0x8];
				3277
				3278	u8 vsd_contd_psid[16][0x8];
				3279	};
				3280
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3281	enum {
				3282	MLX5_XRQC_STATE_GOOD = 0x0,
				3283	MLX5_XRQC_STATE_ERROR = 0x1,
				3284	};
				3285
				3286	enum {
				3287	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
				3288	MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
				3289	};
				3290
				3291	enum {
				3292	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
				3293	};
				3294
				3295	struct mlx5_ifc_tag_matching_topology_context_bits {
				3296	u8 log_matching_list_sz[0x4];
				3297	u8 reserved_at_4[0xc];
				3298	u8 append_next_index[0x10];
				3299
				3300	u8 sw_phase_cnt[0x10];
				3301	u8 hw_phase_cnt[0x10];
				3302
				3303	u8 reserved_at_40[0x40];
				3304	};
				3305
				3306	struct mlx5_ifc_xrqc_bits {
				3307	u8 state[0x4];
				3308	u8 rlkey[0x1];
				3309	u8 reserved_at_5[0xf];
				3310	u8 topology[0x4];
				3311	u8 reserved_at_18[0x4];
				3312	u8 offload[0x4];
				3313
				3314	u8 reserved_at_20[0x8];
				3315	u8 user_index[0x18];
				3316
				3317	u8 reserved_at_40[0x8];
				3318	u8 cqn[0x18];
				3319
				3320	u8 reserved_at_60[0xa0];
				3321
				3322	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
				3323
Artemy Kovalyov	6e44636	2017-08-15 11:59:02 +0300	[diff] [blame]	3324	u8 reserved_at_180[0x280];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3325
				3326	struct mlx5_ifc_wq_bits wq;
				3327	};
				3328
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3329	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
				3330	struct mlx5_ifc_modify_field_select_bits modify_field_select;
				3331	struct mlx5_ifc_resize_field_select_bits resize_field_select;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3332	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3333	};
				3334
				3335	union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
				3336	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
				3337	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
				3338	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3339	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3340	};
				3341
				3342	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
				3343	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
				3344	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
				3345	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
				3346	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
				3347	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
				3348	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
				3349	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	3350	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3351	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
Gal Pressman	d8dc050	2016-09-27 17:04:51 +0300	[diff] [blame]	3352	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3353	u8 reserved_at_0[0x7c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3354	};
				3355
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	3356	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
				3357	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
				3358	u8 reserved_at_0[0x7c0];
				3359	};
				3360
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3361	union mlx5_ifc_event_auto_bits {
				3362	struct mlx5_ifc_comp_event_bits comp_event;
				3363	struct mlx5_ifc_dct_events_bits dct_events;
				3364	struct mlx5_ifc_qp_events_bits qp_events;
				3365	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
				3366	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
				3367	struct mlx5_ifc_cq_error_bits cq_error;
				3368	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
				3369	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
				3370	struct mlx5_ifc_gpio_event_bits gpio_event;
				3371	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
				3372	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
				3373	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3374	u8 reserved_at_0[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3375	};
				3376
				3377	struct mlx5_ifc_health_buffer_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3378	u8 reserved_at_0[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3379
				3380	u8 assert_existptr[0x20];
				3381
				3382	u8 assert_callra[0x20];
				3383
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3384	u8 reserved_at_140[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3385
				3386	u8 fw_version[0x20];
				3387
				3388	u8 hw_id[0x20];
				3389
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3390	u8 reserved_at_1c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3391
				3392	u8 irisc_index[0x8];
				3393	u8 synd[0x8];
				3394	u8 ext_synd[0x10];
				3395	};
				3396
				3397	struct mlx5_ifc_register_loopback_control_bits {
				3398	u8 no_lb[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3399	u8 reserved_at_1[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3400	u8 port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3401	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3402
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3403	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3404	};
				3405
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	3406	struct mlx5_ifc_vport_tc_element_bits {
				3407	u8 traffic_class[0x4];
				3408	u8 reserved_at_4[0xc];
				3409	u8 vport_number[0x10];
				3410	};
				3411
				3412	struct mlx5_ifc_vport_element_bits {
				3413	u8 reserved_at_0[0x10];
				3414	u8 vport_number[0x10];
				3415	};
				3416
				3417	enum {
				3418	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
				3419	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
				3420	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
				3421	};
				3422
				3423	struct mlx5_ifc_tsar_element_bits {
				3424	u8 reserved_at_0[0x8];
				3425	u8 tsar_type[0x8];
				3426	u8 reserved_at_10[0x10];
				3427	};
				3428
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3429	enum {
				3430	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
				3431	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
				3432	};
				3433
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3434	struct mlx5_ifc_teardown_hca_out_bits {
				3435	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3436	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3437
				3438	u8 syndrome[0x20];
				3439
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3440	u8 reserved_at_40[0x3f];
				3441
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	3442	u8 state[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3443	};
				3444
				3445	enum {
				3446	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
Majd Dibbiny	8812c24	2017-02-09 14:20:12 +0200	[diff] [blame]	3447	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
Feras Daoud	fcd29ad	2018-08-09 09:55:21 +0300	[diff] [blame]	3448	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3449	};
				3450
				3451	struct mlx5_ifc_teardown_hca_in_bits {
				3452	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3453	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3454
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3455	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3456	u8 op_mod[0x10];
				3457
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3458	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3459	u8 profile[0x10];
				3460
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3461	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3462	};
				3463
				3464	struct mlx5_ifc_sqerr2rts_qp_out_bits {
				3465	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3466	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3467
				3468	u8 syndrome[0x20];
				3469
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3470	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3471	};
				3472
				3473	struct mlx5_ifc_sqerr2rts_qp_in_bits {
				3474	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3475	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3476
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3477	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3478	u8 op_mod[0x10];
				3479
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3480	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3481	u8 qpn[0x18];
				3482
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3483	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3484
				3485	u8 opt_param_mask[0x20];
				3486
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3487	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3488
				3489	struct mlx5_ifc_qpc_bits qpc;
				3490
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3491	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3492	};
				3493
				3494	struct mlx5_ifc_sqd2rts_qp_out_bits {
				3495	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3496	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3497
				3498	u8 syndrome[0x20];
				3499
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3500	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3501	};
				3502
				3503	struct mlx5_ifc_sqd2rts_qp_in_bits {
				3504	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3505	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3506
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3507	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3508	u8 op_mod[0x10];
				3509
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3510	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3511	u8 qpn[0x18];
				3512
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3513	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3514
				3515	u8 opt_param_mask[0x20];
				3516
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3517	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3518
				3519	struct mlx5_ifc_qpc_bits qpc;
				3520
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3521	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3522	};
				3523
				3524	struct mlx5_ifc_set_roce_address_out_bits {
				3525	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3526	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3527
				3528	u8 syndrome[0x20];
				3529
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3530	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3531	};
				3532
				3533	struct mlx5_ifc_set_roce_address_in_bits {
				3534	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3535	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3536
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3537	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3538	u8 op_mod[0x10];
				3539
				3540	u8 roce_address_index[0x10];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	3541	u8 reserved_at_50[0xc];
				3542	u8 vhca_port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3543
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3544	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3545
				3546	struct mlx5_ifc_roce_addr_layout_bits roce_address;
				3547	};
				3548
				3549	struct mlx5_ifc_set_mad_demux_out_bits {
				3550	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3551	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3552
				3553	u8 syndrome[0x20];
				3554
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3555	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3556	};
				3557
				3558	enum {
				3559	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
				3560	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
				3561	};
				3562
				3563	struct mlx5_ifc_set_mad_demux_in_bits {
				3564	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3565	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3566
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3567	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3568	u8 op_mod[0x10];
				3569
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3570	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3571
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3572	u8 reserved_at_60[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3573	u8 demux_mode[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3574	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3575	};
				3576
				3577	struct mlx5_ifc_set_l2_table_entry_out_bits {
				3578	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3579	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3580
				3581	u8 syndrome[0x20];
				3582
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3583	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3584	};
				3585
				3586	struct mlx5_ifc_set_l2_table_entry_in_bits {
				3587	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3588	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3589
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3590	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3591	u8 op_mod[0x10];
				3592
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3593	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3594
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3595	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3596	u8 table_index[0x18];
				3597
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3598	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3599
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3600	u8 reserved_at_e0[0x13];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3601	u8 vlan_valid[0x1];
				3602	u8 vlan[0xc];
				3603
				3604	struct mlx5_ifc_mac_address_layout_bits mac_address;
				3605
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3606	u8 reserved_at_140[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3607	};
				3608
				3609	struct mlx5_ifc_set_issi_out_bits {
				3610	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3611	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3612
				3613	u8 syndrome[0x20];
				3614
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3615	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3616	};
				3617
				3618	struct mlx5_ifc_set_issi_in_bits {
				3619	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3620	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3621
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3622	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3623	u8 op_mod[0x10];
				3624
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3625	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3626	u8 current_issi[0x10];
				3627
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3628	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3629	};
				3630
				3631	struct mlx5_ifc_set_hca_cap_out_bits {
				3632	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3633	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3634
				3635	u8 syndrome[0x20];
				3636
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3637	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3638	};
				3639
				3640	struct mlx5_ifc_set_hca_cap_in_bits {
				3641	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3642	u8 reserved_at_10[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3643
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3644	u8 reserved_at_20[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3645	u8 op_mod[0x10];
				3646
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3647	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	3648
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3649	union mlx5_ifc_hca_cap_union_bits capability;
				3650	};
				3651
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	3652	enum {
				3653	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
				3654	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
				3655	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
				3656	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
				3657	};
				3658
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3659	struct mlx5_ifc_set_fte_out_bits {
				3660	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3661	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3662
				3663	u8 syndrome[0x20];
				3664
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3665	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3666	};
				3667
				3668	struct mlx5_ifc_set_fte_in_bits {
				3669	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3670	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3671
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3672	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3673	u8 op_mod[0x10];
				3674
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	3675	u8 other_vport[0x1];
				3676	u8 reserved_at_41[0xf];
				3677	u8 vport_number[0x10];
				3678
				3679	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3680
				3681	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3682	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3683
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3684	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3685	u8 table_id[0x18];
				3686
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3687	u8 reserved_at_c0[0x18];
Maor Gottlieb	26a8145	2015-12-10 17:12:39 +0200	[diff] [blame]	3688	u8 modify_enable_mask[0x8];
				3689
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3690	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3691
				3692	u8 flow_index[0x20];
				3693
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3694	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3695
				3696	struct mlx5_ifc_flow_context_bits flow_context;
				3697	};
				3698
				3699	struct mlx5_ifc_rts2rts_qp_out_bits {
				3700	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3701	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3702
				3703	u8 syndrome[0x20];
				3704
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3705	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3706	};
				3707
				3708	struct mlx5_ifc_rts2rts_qp_in_bits {
				3709	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3710	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3711
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3712	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3713	u8 op_mod[0x10];
				3714
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3715	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3716	u8 qpn[0x18];
				3717
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3718	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3719
				3720	u8 opt_param_mask[0x20];
				3721
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3722	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3723
				3724	struct mlx5_ifc_qpc_bits qpc;
				3725
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3726	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3727	};
				3728
				3729	struct mlx5_ifc_rtr2rts_qp_out_bits {
				3730	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3731	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3732
				3733	u8 syndrome[0x20];
				3734
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3735	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3736	};
				3737
				3738	struct mlx5_ifc_rtr2rts_qp_in_bits {
				3739	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3740	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3741
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3742	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3743	u8 op_mod[0x10];
				3744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3745	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3746	u8 qpn[0x18];
				3747
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3748	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3749
				3750	u8 opt_param_mask[0x20];
				3751
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3752	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3753
				3754	struct mlx5_ifc_qpc_bits qpc;
				3755
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3756	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3757	};
				3758
				3759	struct mlx5_ifc_rst2init_qp_out_bits {
				3760	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3761	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3762
				3763	u8 syndrome[0x20];
				3764
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3765	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3766	};
				3767
				3768	struct mlx5_ifc_rst2init_qp_in_bits {
				3769	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	3770	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3771
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3772	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3773	u8 op_mod[0x10];
				3774
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3775	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3776	u8 qpn[0x18];
				3777
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3778	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3779
				3780	u8 opt_param_mask[0x20];
				3781
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3782	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3783
				3784	struct mlx5_ifc_qpc_bits qpc;
				3785
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3786	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3787	};
				3788
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	3789	struct mlx5_ifc_query_xrq_out_bits {
				3790	u8 status[0x8];
				3791	u8 reserved_at_8[0x18];
				3792
				3793	u8 syndrome[0x20];
				3794
				3795	u8 reserved_at_40[0x40];
				3796
				3797	struct mlx5_ifc_xrqc_bits xrq_context;
				3798	};
				3799
				3800	struct mlx5_ifc_query_xrq_in_bits {
				3801	u8 opcode[0x10];
				3802	u8 reserved_at_10[0x10];
				3803
				3804	u8 reserved_at_20[0x10];
				3805	u8 op_mod[0x10];
				3806
				3807	u8 reserved_at_40[0x8];
				3808	u8 xrqn[0x18];
				3809
				3810	u8 reserved_at_60[0x20];
				3811	};
				3812
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3813	struct mlx5_ifc_query_xrc_srq_out_bits {
				3814	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3815	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3816
				3817	u8 syndrome[0x20];
				3818
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3819	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3820
				3821	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
				3822
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3823	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3824
				3825	u8 pas[0][0x40];
				3826	};
				3827
				3828	struct mlx5_ifc_query_xrc_srq_in_bits {
				3829	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3830	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3831
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3832	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3833	u8 op_mod[0x10];
				3834
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3835	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3836	u8 xrc_srqn[0x18];
				3837
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3838	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3839	};
				3840
				3841	enum {
				3842	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
				3843	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
				3844	};
				3845
				3846	struct mlx5_ifc_query_vport_state_out_bits {
				3847	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3848	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3849
				3850	u8 syndrome[0x20];
				3851
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3852	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3853
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3854	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3855	u8 admin_state[0x4];
				3856	u8 state[0x4];
				3857	};
				3858
				3859	enum {
Eran Ben Elisha	cc9c82a	2018-08-08 16:23:49 -0700	[diff] [blame]	3860	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
				3861	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3862	};
				3863
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3864	struct mlx5_ifc_arm_monitor_counter_in_bits {
				3865	u8 opcode[0x10];
				3866	u8 uid[0x10];
				3867
				3868	u8 reserved_at_20[0x10];
				3869	u8 op_mod[0x10];
				3870
				3871	u8 reserved_at_40[0x20];
				3872
				3873	u8 reserved_at_60[0x20];
				3874	};
				3875
				3876	struct mlx5_ifc_arm_monitor_counter_out_bits {
				3877	u8 status[0x8];
				3878	u8 reserved_at_8[0x18];
				3879
				3880	u8 syndrome[0x20];
				3881
				3882	u8 reserved_at_40[0x40];
				3883	};
				3884
				3885	enum {
				3886	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
				3887	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
				3888	};
				3889
				3890	enum mlx5_monitor_counter_ppcnt {
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	3891	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
				3892	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
				3893	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
				3894	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
				3895	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
				3896	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3897	};
				3898
				3899	enum {
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	3900	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
Eyal Davidovich	fd4572b	2018-12-10 13:15:12 -0800	[diff] [blame]	3901	};
				3902
				3903	struct mlx5_ifc_monitor_counter_output_bits {
				3904	u8 reserved_at_0[0x4];
				3905	u8 type[0x4];
				3906	u8 reserved_at_8[0x8];
				3907	u8 counter[0x10];
				3908
				3909	u8 counter_group_id[0x20];
				3910	};
				3911
				3912	#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
				3913	#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
				3914	#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
				3915	MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
				3916
				3917	struct mlx5_ifc_set_monitor_counter_in_bits {
				3918	u8 opcode[0x10];
				3919	u8 uid[0x10];
				3920
				3921	u8 reserved_at_20[0x10];
				3922	u8 op_mod[0x10];
				3923
				3924	u8 reserved_at_40[0x10];
				3925	u8 num_of_counters[0x10];
				3926
				3927	u8 reserved_at_60[0x20];
				3928
				3929	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
				3930	};
				3931
				3932	struct mlx5_ifc_set_monitor_counter_out_bits {
				3933	u8 status[0x8];
				3934	u8 reserved_at_8[0x18];
				3935
				3936	u8 syndrome[0x20];
				3937
				3938	u8 reserved_at_40[0x40];
				3939	};
				3940
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3941	struct mlx5_ifc_query_vport_state_in_bits {
				3942	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3943	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3944
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3945	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3946	u8 op_mod[0x10];
				3947
				3948	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3949	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3950	u8 vport_number[0x10];
				3951
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3952	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3953	};
				3954
Moshe Shemesh	61c5b5c	2018-01-07 16:45:27 +0200	[diff] [blame]	3955	struct mlx5_ifc_query_vnic_env_out_bits {
				3956	u8 status[0x8];
				3957	u8 reserved_at_8[0x18];
				3958
				3959	u8 syndrome[0x20];
				3960
				3961	u8 reserved_at_40[0x40];
				3962
				3963	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
				3964	};
				3965
				3966	enum {
				3967	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
				3968	};
				3969
				3970	struct mlx5_ifc_query_vnic_env_in_bits {
				3971	u8 opcode[0x10];
				3972	u8 reserved_at_10[0x10];
				3973
				3974	u8 reserved_at_20[0x10];
				3975	u8 op_mod[0x10];
				3976
				3977	u8 other_vport[0x1];
				3978	u8 reserved_at_41[0xf];
				3979	u8 vport_number[0x10];
				3980
				3981	u8 reserved_at_60[0x20];
				3982	};
				3983
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3984	struct mlx5_ifc_query_vport_counter_out_bits {
				3985	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3986	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3987
				3988	u8 syndrome[0x20];
				3989
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	3990	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	3991
				3992	struct mlx5_ifc_traffic_counter_bits received_errors;
				3993
				3994	struct mlx5_ifc_traffic_counter_bits transmit_errors;
				3995
				3996	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
				3997
				3998	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
				3999
				4000	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
				4001
				4002	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
				4003
				4004	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
				4005
				4006	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
				4007
				4008	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
				4009
				4010	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
				4011
				4012	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
				4013
				4014	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
				4015
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4016	u8 reserved_at_680[0xa00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4017	};
				4018
				4019	enum {
				4020	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
				4021	};
				4022
				4023	struct mlx5_ifc_query_vport_counter_in_bits {
				4024	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4025	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4026
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4027	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4028	u8 op_mod[0x10];
				4029
				4030	u8 other_vport[0x1];
Meny Yossefi	b54ba27	2016-02-18 18:14:59 +0200	[diff] [blame]	4031	u8 reserved_at_41[0xb];
				4032	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4033	u8 vport_number[0x10];
				4034
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4035	u8 reserved_at_60[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4036
				4037	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4038	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4039
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4040	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4041	};
				4042
				4043	struct mlx5_ifc_query_tis_out_bits {
				4044	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4045	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4046
				4047	u8 syndrome[0x20];
				4048
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4049	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4050
				4051	struct mlx5_ifc_tisc_bits tis_context;
				4052	};
				4053
				4054	struct mlx5_ifc_query_tis_in_bits {
				4055	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4056	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4057
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4058	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4059	u8 op_mod[0x10];
				4060
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4061	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4062	u8 tisn[0x18];
				4063
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4064	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4065	};
				4066
				4067	struct mlx5_ifc_query_tir_out_bits {
				4068	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4069	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4070
				4071	u8 syndrome[0x20];
				4072
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4073	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4074
				4075	struct mlx5_ifc_tirc_bits tir_context;
				4076	};
				4077
				4078	struct mlx5_ifc_query_tir_in_bits {
				4079	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4080	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4081
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4082	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4083	u8 op_mod[0x10];
				4084
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4085	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4086	u8 tirn[0x18];
				4087
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4088	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4089	};
				4090
				4091	struct mlx5_ifc_query_srq_out_bits {
				4092	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4093	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4094
				4095	u8 syndrome[0x20];
				4096
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4097	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4098
				4099	struct mlx5_ifc_srqc_bits srq_context_entry;
				4100
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4101	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4102
				4103	u8 pas[0][0x40];
				4104	};
				4105
				4106	struct mlx5_ifc_query_srq_in_bits {
				4107	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4108	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4109
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4110	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4111	u8 op_mod[0x10];
				4112
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4113	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4114	u8 srqn[0x18];
				4115
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4116	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4117	};
				4118
				4119	struct mlx5_ifc_query_sq_out_bits {
				4120	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4121	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4122
				4123	u8 syndrome[0x20];
				4124
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4125	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4126
				4127	struct mlx5_ifc_sqc_bits sq_context;
				4128	};
				4129
				4130	struct mlx5_ifc_query_sq_in_bits {
				4131	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4132	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4133
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4134	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4135	u8 op_mod[0x10];
				4136
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4137	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4138	u8 sqn[0x18];
				4139
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4140	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4141	};
				4142
				4143	struct mlx5_ifc_query_special_contexts_out_bits {
				4144	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4145	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4146
				4147	u8 syndrome[0x20];
				4148
Saeed Mahameed	ec22eb5	2016-07-16 06:28:36 +0300	[diff] [blame]	4149	u8 dump_fill_mkey[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4150
				4151	u8 resd_lkey[0x20];
Artemy Kovalyov	bcda1ac	2017-01-02 11:37:41 +0200	[diff] [blame]	4152
				4153	u8 null_mkey[0x20];
				4154
				4155	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4156	};
				4157
				4158	struct mlx5_ifc_query_special_contexts_in_bits {
				4159	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4160	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4161
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4162	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4163	u8 op_mod[0x10];
				4164
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4165	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4166	};
				4167
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	4168	struct mlx5_ifc_query_scheduling_element_out_bits {
				4169	u8 opcode[0x10];
				4170	u8 reserved_at_10[0x10];
				4171
				4172	u8 reserved_at_20[0x10];
				4173	u8 op_mod[0x10];
				4174
				4175	u8 reserved_at_40[0xc0];
				4176
				4177	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				4178
				4179	u8 reserved_at_300[0x100];
				4180	};
				4181
				4182	enum {
				4183	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
				4184	};
				4185
				4186	struct mlx5_ifc_query_scheduling_element_in_bits {
				4187	u8 opcode[0x10];
				4188	u8 reserved_at_10[0x10];
				4189
				4190	u8 reserved_at_20[0x10];
				4191	u8 op_mod[0x10];
				4192
				4193	u8 scheduling_hierarchy[0x8];
				4194	u8 reserved_at_48[0x18];
				4195
				4196	u8 scheduling_element_id[0x20];
				4197
				4198	u8 reserved_at_80[0x180];
				4199	};
				4200
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4201	struct mlx5_ifc_query_rqt_out_bits {
				4202	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4203	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4204
				4205	u8 syndrome[0x20];
				4206
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4207	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4208
				4209	struct mlx5_ifc_rqtc_bits rqt_context;
				4210	};
				4211
				4212	struct mlx5_ifc_query_rqt_in_bits {
				4213	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4214	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4215
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4216	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4217	u8 op_mod[0x10];
				4218
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4219	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4220	u8 rqtn[0x18];
				4221
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4222	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4223	};
				4224
				4225	struct mlx5_ifc_query_rq_out_bits {
				4226	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4227	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4228
				4229	u8 syndrome[0x20];
				4230
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4231	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4232
				4233	struct mlx5_ifc_rqc_bits rq_context;
				4234	};
				4235
				4236	struct mlx5_ifc_query_rq_in_bits {
				4237	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4238	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4239
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4240	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4241	u8 op_mod[0x10];
				4242
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4243	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4244	u8 rqn[0x18];
				4245
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4246	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4247	};
				4248
				4249	struct mlx5_ifc_query_roce_address_out_bits {
				4250	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4251	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4252
				4253	u8 syndrome[0x20];
				4254
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4255	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4256
				4257	struct mlx5_ifc_roce_addr_layout_bits roce_address;
				4258	};
				4259
				4260	struct mlx5_ifc_query_roce_address_in_bits {
				4261	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4262	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4263
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4264	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4265	u8 op_mod[0x10];
				4266
				4267	u8 roce_address_index[0x10];
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	4268	u8 reserved_at_50[0xc];
				4269	u8 vhca_port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4270
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4271	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4272	};
				4273
				4274	struct mlx5_ifc_query_rmp_out_bits {
				4275	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4276	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4277
				4278	u8 syndrome[0x20];
				4279
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4280	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4281
				4282	struct mlx5_ifc_rmpc_bits rmp_context;
				4283	};
				4284
				4285	struct mlx5_ifc_query_rmp_in_bits {
				4286	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4287	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4288
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4289	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4290	u8 op_mod[0x10];
				4291
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4292	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4293	u8 rmpn[0x18];
				4294
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4295	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4296	};
				4297
				4298	struct mlx5_ifc_query_qp_out_bits {
				4299	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4300	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4301
				4302	u8 syndrome[0x20];
				4303
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4304	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4305
				4306	u8 opt_param_mask[0x20];
				4307
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4308	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4309
				4310	struct mlx5_ifc_qpc_bits qpc;
				4311
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4312	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4313
				4314	u8 pas[0][0x40];
				4315	};
				4316
				4317	struct mlx5_ifc_query_qp_in_bits {
				4318	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4319	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4320
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4321	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4322	u8 op_mod[0x10];
				4323
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4324	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4325	u8 qpn[0x18];
				4326
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4327	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4328	};
				4329
				4330	struct mlx5_ifc_query_q_counter_out_bits {
				4331	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4332	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4333
				4334	u8 syndrome[0x20];
				4335
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4336	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4337
				4338	u8 rx_write_requests[0x20];
				4339
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4340	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4341
				4342	u8 rx_read_requests[0x20];
				4343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4344	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4345
				4346	u8 rx_atomic_requests[0x20];
				4347
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4348	u8 reserved_at_120[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4349
				4350	u8 rx_dct_connect[0x20];
				4351
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4352	u8 reserved_at_160[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4353
				4354	u8 out_of_buffer[0x20];
				4355
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4356	u8 reserved_at_1a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4357
				4358	u8 out_of_sequence[0x20];
				4359
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	4360	u8 reserved_at_1e0[0x20];
				4361
				4362	u8 duplicate_request[0x20];
				4363
				4364	u8 reserved_at_220[0x20];
				4365
				4366	u8 rnr_nak_retry_err[0x20];
				4367
				4368	u8 reserved_at_260[0x20];
				4369
				4370	u8 packet_seq_err[0x20];
				4371
				4372	u8 reserved_at_2a0[0x20];
				4373
				4374	u8 implied_nak_seq_err[0x20];
				4375
				4376	u8 reserved_at_2e0[0x20];
				4377
				4378	u8 local_ack_timeout_err[0x20];
				4379
Parav Pandit	58dcb60	2017-06-19 07:19:37 +0300	[diff] [blame]	4380	u8 reserved_at_320[0xa0];
				4381
				4382	u8 resp_local_length_error[0x20];
				4383
				4384	u8 req_local_length_error[0x20];
				4385
				4386	u8 resp_local_qp_error[0x20];
				4387
				4388	u8 local_operation_error[0x20];
				4389
				4390	u8 resp_local_protection[0x20];
				4391
				4392	u8 req_local_protection[0x20];
				4393
				4394	u8 resp_cqe_error[0x20];
				4395
				4396	u8 req_cqe_error[0x20];
				4397
				4398	u8 req_mw_binding[0x20];
				4399
				4400	u8 req_bad_response[0x20];
				4401
				4402	u8 req_remote_invalid_request[0x20];
				4403
				4404	u8 resp_remote_invalid_request[0x20];
				4405
				4406	u8 req_remote_access_errors[0x20];
				4407
				4408	u8 resp_remote_access_errors[0x20];
				4409
				4410	u8 req_remote_operation_errors[0x20];
				4411
				4412	u8 req_transport_retries_exceeded[0x20];
				4413
				4414	u8 cq_overflow[0x20];
				4415
				4416	u8 resp_cqe_flush_error[0x20];
				4417
				4418	u8 req_cqe_flush_error[0x20];
				4419
				4420	u8 reserved_at_620[0x1e0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4421	};
				4422
				4423	struct mlx5_ifc_query_q_counter_in_bits {
				4424	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4425	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4426
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4427	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4428	u8 op_mod[0x10];
				4429
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4430	u8 reserved_at_40[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4431
				4432	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4433	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4434
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4435	u8 reserved_at_e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4436	u8 counter_set_id[0x8];
				4437	};
				4438
				4439	struct mlx5_ifc_query_pages_out_bits {
				4440	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4441	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4442
				4443	u8 syndrome[0x20];
				4444
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	4445	u8 embedded_cpu_function[0x1];
				4446	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4447	u8 function_id[0x10];
				4448
				4449	u8 num_pages[0x20];
				4450	};
				4451
				4452	enum {
				4453	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
				4454	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
				4455	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
				4456	};
				4457
				4458	struct mlx5_ifc_query_pages_in_bits {
				4459	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4460	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4461
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4462	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4463	u8 op_mod[0x10];
				4464
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	4465	u8 embedded_cpu_function[0x1];
				4466	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4467	u8 function_id[0x10];
				4468
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4469	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4470	};
				4471
				4472	struct mlx5_ifc_query_nic_vport_context_out_bits {
				4473	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4474	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4475
				4476	u8 syndrome[0x20];
				4477
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4478	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4479
				4480	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
				4481	};
				4482
				4483	struct mlx5_ifc_query_nic_vport_context_in_bits {
				4484	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4485	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4486
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4487	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4488	u8 op_mod[0x10];
				4489
				4490	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4491	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4492	u8 vport_number[0x10];
				4493
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4494	u8 reserved_at_60[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4495	u8 allowed_list_type[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4496	u8 reserved_at_68[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4497	};
				4498
				4499	struct mlx5_ifc_query_mkey_out_bits {
				4500	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4501	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4502
				4503	u8 syndrome[0x20];
				4504
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4505	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4506
				4507	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
				4508
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4509	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4510
				4511	u8 bsf0_klm0_pas_mtt0_1[16][0x8];
				4512
				4513	u8 bsf1_klm1_pas_mtt2_3[16][0x8];
				4514	};
				4515
				4516	struct mlx5_ifc_query_mkey_in_bits {
				4517	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4518	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4519
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4520	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4521	u8 op_mod[0x10];
				4522
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4523	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4524	u8 mkey_index[0x18];
				4525
				4526	u8 pg_access[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4527	u8 reserved_at_61[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4528	};
				4529
				4530	struct mlx5_ifc_query_mad_demux_out_bits {
				4531	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4532	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4533
				4534	u8 syndrome[0x20];
				4535
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4536	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4537
				4538	u8 mad_dumux_parameters_block[0x20];
				4539	};
				4540
				4541	struct mlx5_ifc_query_mad_demux_in_bits {
				4542	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4543	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4544
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4545	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4546	u8 op_mod[0x10];
				4547
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4548	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4549	};
				4550
				4551	struct mlx5_ifc_query_l2_table_entry_out_bits {
				4552	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4553	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4554
				4555	u8 syndrome[0x20];
				4556
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4557	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4558
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4559	u8 reserved_at_e0[0x13];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4560	u8 vlan_valid[0x1];
				4561	u8 vlan[0xc];
				4562
				4563	struct mlx5_ifc_mac_address_layout_bits mac_address;
				4564
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4565	u8 reserved_at_140[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4566	};
				4567
				4568	struct mlx5_ifc_query_l2_table_entry_in_bits {
				4569	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4570	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4571
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4572	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4573	u8 op_mod[0x10];
				4574
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4575	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4576
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4577	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4578	u8 table_index[0x18];
				4579
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4580	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4581	};
				4582
				4583	struct mlx5_ifc_query_issi_out_bits {
				4584	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4585	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4586
				4587	u8 syndrome[0x20];
				4588
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4589	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4590	u8 current_issi[0x10];
				4591
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4592	u8 reserved_at_60[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4593
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4594	u8 reserved_at_100[76][0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4595	u8 supported_issi_dw0[0x20];
				4596	};
				4597
				4598	struct mlx5_ifc_query_issi_in_bits {
				4599	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4600	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4601
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4602	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4603	u8 op_mod[0x10];
				4604
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4605	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4606	};
				4607
Saeed Mahameed	0dbc6fe	2016-11-17 13:45:59 +0200	[diff] [blame]	4608	struct mlx5_ifc_set_driver_version_out_bits {
				4609	u8 status[0x8];
				4610	u8 reserved_0[0x18];
				4611
				4612	u8 syndrome[0x20];
				4613	u8 reserved_1[0x40];
				4614	};
				4615
				4616	struct mlx5_ifc_set_driver_version_in_bits {
				4617	u8 opcode[0x10];
				4618	u8 reserved_0[0x10];
				4619
				4620	u8 reserved_1[0x10];
				4621	u8 op_mod[0x10];
				4622
				4623	u8 reserved_2[0x40];
				4624	u8 driver_version[64][0x8];
				4625	};
				4626
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4627	struct mlx5_ifc_query_hca_vport_pkey_out_bits {
				4628	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4629	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4630
				4631	u8 syndrome[0x20];
				4632
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4633	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4634
				4635	struct mlx5_ifc_pkey_bits pkey[0];
				4636	};
				4637
				4638	struct mlx5_ifc_query_hca_vport_pkey_in_bits {
				4639	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4640	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4641
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4642	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4643	u8 op_mod[0x10];
				4644
				4645	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4646	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4647	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4648	u8 vport_number[0x10];
				4649
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4650	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4651	u8 pkey_index[0x10];
				4652	};
				4653
Eli Cohen	eff901d	2016-03-11 22:58:42 +0200	[diff] [blame]	4654	enum {
				4655	MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
				4656	MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
				4657	MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
				4658	};
				4659
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4660	struct mlx5_ifc_query_hca_vport_gid_out_bits {
				4661	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4662	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4663
				4664	u8 syndrome[0x20];
				4665
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4666	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4667
				4668	u8 gids_num[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4669	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4670
				4671	struct mlx5_ifc_array128_auto_bits gid[0];
				4672	};
				4673
				4674	struct mlx5_ifc_query_hca_vport_gid_in_bits {
				4675	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4676	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4677
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4678	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4679	u8 op_mod[0x10];
				4680
				4681	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4682	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4683	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4684	u8 vport_number[0x10];
				4685
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4686	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4687	u8 gid_index[0x10];
				4688	};
				4689
				4690	struct mlx5_ifc_query_hca_vport_context_out_bits {
				4691	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4692	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4693
				4694	u8 syndrome[0x20];
				4695
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4696	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4697
				4698	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
				4699	};
				4700
				4701	struct mlx5_ifc_query_hca_vport_context_in_bits {
				4702	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4703	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4704
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4705	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4706	u8 op_mod[0x10];
				4707
				4708	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4709	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	4710	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4711	u8 vport_number[0x10];
				4712
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4713	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4714	};
				4715
				4716	struct mlx5_ifc_query_hca_cap_out_bits {
				4717	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4718	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4719
				4720	u8 syndrome[0x20];
				4721
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4722	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4723
				4724	union mlx5_ifc_hca_cap_union_bits capability;
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4725	};
				4726
				4727	struct mlx5_ifc_query_hca_cap_in_bits {
				4728	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4729	u8 reserved_at_10[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4730
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4731	u8 reserved_at_20[0x10];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4732	u8 op_mod[0x10];
				4733
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4734	u8 reserved_at_40[0x40];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4735	};
				4736
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4737	struct mlx5_ifc_query_flow_table_out_bits {
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4738	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4739	u8 reserved_at_8[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4740
				4741	u8 syndrome[0x20];
				4742
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4743	u8 reserved_at_40[0x80];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4745	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4746	u8 level[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4747	u8 reserved_at_d0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4748	u8 log_size[0x8];
				4749
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4750	u8 reserved_at_e0[0x120];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4751	};
				4752
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4753	struct mlx5_ifc_query_flow_table_in_bits {
				4754	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4755	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4756
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4757	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4758	u8 op_mod[0x10];
				4759
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4760	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4761
				4762	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4763	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4764
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4765	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4766	u8 table_id[0x18];
				4767
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4768	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4769	};
				4770
				4771	struct mlx5_ifc_query_fte_out_bits {
				4772	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4773	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4774
				4775	u8 syndrome[0x20];
				4776
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4777	u8 reserved_at_40[0x1c0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4778
				4779	struct mlx5_ifc_flow_context_bits flow_context;
				4780	};
				4781
				4782	struct mlx5_ifc_query_fte_in_bits {
				4783	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4784	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4785
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4786	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4787	u8 op_mod[0x10];
				4788
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4789	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4790
				4791	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4792	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4794	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4795	u8 table_id[0x18];
				4796
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4797	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4798
				4799	u8 flow_index[0x20];
				4800
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4801	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4802	};
				4803
				4804	enum {
				4805	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
				4806	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
				4807	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
Saeed Mahameed	4c8b851	2018-12-12 19:11:36 -0800	[diff] [blame]	4808	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4809	};
				4810
				4811	struct mlx5_ifc_query_flow_group_out_bits {
				4812	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4813	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4814
				4815	u8 syndrome[0x20];
				4816
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4817	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4818
				4819	u8 start_flow_index[0x20];
				4820
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4821	u8 reserved_at_100[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4822
				4823	u8 end_flow_index[0x20];
				4824
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4825	u8 reserved_at_140[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4826
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4827	u8 reserved_at_1e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4828	u8 match_criteria_enable[0x8];
				4829
				4830	struct mlx5_ifc_fte_match_param_bits match_criteria;
				4831
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4832	u8 reserved_at_1200[0xe00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4833	};
				4834
				4835	struct mlx5_ifc_query_flow_group_in_bits {
				4836	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4837	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4838
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4839	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4840	u8 op_mod[0x10];
				4841
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4842	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4843
				4844	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4845	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4846
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4847	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4848	u8 table_id[0x18];
				4849
				4850	u8 group_id[0x20];
				4851
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4852	u8 reserved_at_e0[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4853	};
				4854
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	4855	struct mlx5_ifc_query_flow_counter_out_bits {
				4856	u8 status[0x8];
				4857	u8 reserved_at_8[0x18];
				4858
				4859	u8 syndrome[0x20];
				4860
				4861	u8 reserved_at_40[0x40];
				4862
				4863	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
				4864	};
				4865
				4866	struct mlx5_ifc_query_flow_counter_in_bits {
				4867	u8 opcode[0x10];
				4868	u8 reserved_at_10[0x10];
				4869
				4870	u8 reserved_at_20[0x10];
				4871	u8 op_mod[0x10];
				4872
				4873	u8 reserved_at_40[0x80];
				4874
				4875	u8 clear[0x1];
				4876	u8 reserved_at_c1[0xf];
				4877	u8 num_of_counters[0x10];
				4878
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	4879	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	4880	};
				4881
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4882	struct mlx5_ifc_query_esw_vport_context_out_bits {
				4883	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4884	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4885
				4886	u8 syndrome[0x20];
				4887
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4888	u8 reserved_at_40[0x40];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4889
				4890	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
				4891	};
				4892
				4893	struct mlx5_ifc_query_esw_vport_context_in_bits {
				4894	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4895	u8 reserved_at_10[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4896
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4897	u8 reserved_at_20[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4898	u8 op_mod[0x10];
				4899
				4900	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4901	u8 reserved_at_41[0xf];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4902	u8 vport_number[0x10];
				4903
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4904	u8 reserved_at_60[0x20];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4905	};
				4906
				4907	struct mlx5_ifc_modify_esw_vport_context_out_bits {
				4908	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4909	u8 reserved_at_8[0x18];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4910
				4911	u8 syndrome[0x20];
				4912
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4913	u8 reserved_at_40[0x40];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4914	};
				4915
				4916	struct mlx5_ifc_esw_vport_context_fields_select_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4917	u8 reserved_at_0[0x1c];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4918	u8 vport_cvlan_insert[0x1];
				4919	u8 vport_svlan_insert[0x1];
				4920	u8 vport_cvlan_strip[0x1];
				4921	u8 vport_svlan_strip[0x1];
				4922	};
				4923
				4924	struct mlx5_ifc_modify_esw_vport_context_in_bits {
				4925	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4926	u8 reserved_at_10[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4927
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4928	u8 reserved_at_20[0x10];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4929	u8 op_mod[0x10];
				4930
				4931	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4932	u8 reserved_at_41[0xf];
Saeed Mahameed	d666675	2015-12-01 18:03:22 +0200	[diff] [blame]	4933	u8 vport_number[0x10];
				4934
				4935	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
				4936
				4937	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
				4938	};
				4939
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4940	struct mlx5_ifc_query_eq_out_bits {
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4941	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4942	u8 reserved_at_8[0x18];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	4943
				4944	u8 syndrome[0x20];
				4945
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4946	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4947
				4948	struct mlx5_ifc_eqc_bits eq_context_entry;
				4949
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4950	u8 reserved_at_280[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4951
				4952	u8 event_bitmask[0x40];
				4953
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4954	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4955
				4956	u8 pas[0][0x40];
				4957	};
				4958
				4959	struct mlx5_ifc_query_eq_in_bits {
				4960	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4961	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4962
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4963	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4964	u8 op_mod[0x10];
				4965
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4966	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4967	u8 eq_number[0x8];
				4968
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	4969	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	4970	};
				4971
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4972	struct mlx5_ifc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4973	u8 reserved_at_0[0x5];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4974	u8 reformat_type[0x3];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4975	u8 reserved_at_8[0xe];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4976	u8 reformat_data_size[0xa];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4977
				4978	u8 reserved_at_20[0x10];
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4979	u8 reformat_data[2][0x8];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4980
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4981	u8 more_reformat_data[0][0x8];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4982	};
				4983
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4984	struct mlx5_ifc_query_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4985	u8 status[0x8];
				4986	u8 reserved_at_8[0x18];
				4987
				4988	u8 syndrome[0x20];
				4989
				4990	u8 reserved_at_40[0xa0];
				4991
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4992	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4993	};
				4994
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	4995	struct mlx5_ifc_query_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	4996	u8 opcode[0x10];
				4997	u8 reserved_at_10[0x10];
				4998
				4999	u8 reserved_at_20[0x10];
				5000	u8 op_mod[0x10];
				5001
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5002	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5003
				5004	u8 reserved_at_60[0xa0];
				5005	};
				5006
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5007	struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5008	u8 status[0x8];
				5009	u8 reserved_at_8[0x18];
				5010
				5011	u8 syndrome[0x20];
				5012
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5013	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5014
				5015	u8 reserved_at_60[0x20];
				5016	};
				5017
Mark Bloch	e0e7a38	2018-08-28 14:18:45 +0300	[diff] [blame]	5018	enum {
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5019	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
				5020	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
Mark Bloch	bea4e1f	2018-08-28 14:18:47 +0300	[diff] [blame]	5021	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
				5022	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
				5023	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
Mark Bloch	e0e7a38	2018-08-28 14:18:45 +0300	[diff] [blame]	5024	};
				5025
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5026	struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5027	u8 opcode[0x10];
				5028	u8 reserved_at_10[0x10];
				5029
				5030	u8 reserved_at_20[0x10];
				5031	u8 op_mod[0x10];
				5032
				5033	u8 reserved_at_40[0xa0];
				5034
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5035	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5036	};
				5037
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5038	struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5039	u8 status[0x8];
				5040	u8 reserved_at_8[0x18];
				5041
				5042	u8 syndrome[0x20];
				5043
				5044	u8 reserved_at_40[0x40];
				5045	};
				5046
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5047	struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5048	u8 opcode[0x10];
				5049	u8 reserved_at_10[0x10];
				5050
				5051	u8 reserved_20[0x10];
				5052	u8 op_mod[0x10];
				5053
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	5054	u8 packet_reformat_id[0x20];
Hadar Hen Zion	7adbde2	2016-08-03 15:08:33 +0300	[diff] [blame]	5055
				5056	u8 reserved_60[0x20];
				5057	};
				5058
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	5059	struct mlx5_ifc_set_action_in_bits {
				5060	u8 action_type[0x4];
				5061	u8 field[0xc];
				5062	u8 reserved_at_10[0x3];
				5063	u8 offset[0x5];
				5064	u8 reserved_at_18[0x3];
				5065	u8 length[0x5];
				5066
				5067	u8 data[0x20];
				5068	};
				5069
				5070	struct mlx5_ifc_add_action_in_bits {
				5071	u8 action_type[0x4];
				5072	u8 field[0xc];
				5073	u8 reserved_at_10[0x10];
				5074
				5075	u8 data[0x20];
				5076	};
				5077
				5078	union mlx5_ifc_set_action_in_add_action_in_auto_bits {
				5079	struct mlx5_ifc_set_action_in_bits set_action_in;
				5080	struct mlx5_ifc_add_action_in_bits add_action_in;
				5081	u8 reserved_at_0[0x40];
				5082	};
				5083
				5084	enum {
				5085	MLX5_ACTION_TYPE_SET = 0x1,
				5086	MLX5_ACTION_TYPE_ADD = 0x2,
				5087	};
				5088
				5089	enum {
				5090	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
				5091	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
				5092	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
				5093	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
				5094	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
				5095	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
				5096	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
				5097	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
				5098	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
				5099	MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
				5100	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
				5101	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
				5102	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
				5103	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
				5104	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
				5105	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
				5106	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
				5107	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
				5108	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
				5109	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
				5110	MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
				5111	MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
Or Gerlitz	0c0316f	2017-06-13 11:09:57 +0300	[diff] [blame]	5112	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
Or Gerlitz	2a69cb9	2017-01-19 19:31:25 +0200	[diff] [blame]	5113	};
				5114
				5115	struct mlx5_ifc_alloc_modify_header_context_out_bits {
				5116	u8 status[0x8];
				5117	u8 reserved_at_8[0x18];
				5118
				5119	u8 syndrome[0x20];
				5120
				5121	u8 modify_header_id[0x20];
				5122
				5123	u8 reserved_at_60[0x20];
				5124	};
				5125
				5126	struct mlx5_ifc_alloc_modify_header_context_in_bits {
				5127	u8 opcode[0x10];
				5128	u8 reserved_at_10[0x10];
				5129
				5130	u8 reserved_at_20[0x10];
				5131	u8 op_mod[0x10];
				5132
				5133	u8 reserved_at_40[0x20];
				5134
				5135	u8 table_type[0x8];
				5136	u8 reserved_at_68[0x10];
				5137	u8 num_of_actions[0x8];
				5138
				5139	union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
				5140	};
				5141
				5142	struct mlx5_ifc_dealloc_modify_header_context_out_bits {
				5143	u8 status[0x8];
				5144	u8 reserved_at_8[0x18];
				5145
				5146	u8 syndrome[0x20];
				5147
				5148	u8 reserved_at_40[0x40];
				5149	};
				5150
				5151	struct mlx5_ifc_dealloc_modify_header_context_in_bits {
				5152	u8 opcode[0x10];
				5153	u8 reserved_at_10[0x10];
				5154
				5155	u8 reserved_at_20[0x10];
				5156	u8 op_mod[0x10];
				5157
				5158	u8 modify_header_id[0x20];
				5159
				5160	u8 reserved_at_60[0x20];
				5161	};
				5162
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5163	struct mlx5_ifc_query_dct_out_bits {
				5164	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5165	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5166
				5167	u8 syndrome[0x20];
				5168
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5169	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5170
				5171	struct mlx5_ifc_dctc_bits dct_context_entry;
				5172
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5173	u8 reserved_at_280[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5174	};
				5175
				5176	struct mlx5_ifc_query_dct_in_bits {
				5177	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5178	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5179
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5180	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5181	u8 op_mod[0x10];
				5182
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5183	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5184	u8 dctn[0x18];
				5185
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5186	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5187	};
				5188
				5189	struct mlx5_ifc_query_cq_out_bits {
				5190	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5191	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5192
				5193	u8 syndrome[0x20];
				5194
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5195	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5196
				5197	struct mlx5_ifc_cqc_bits cq_context;
				5198
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5199	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5200
				5201	u8 pas[0][0x40];
				5202	};
				5203
				5204	struct mlx5_ifc_query_cq_in_bits {
				5205	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5206	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5207
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5208	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5209	u8 op_mod[0x10];
				5210
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5211	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5212	u8 cqn[0x18];
				5213
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5214	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5215	};
				5216
				5217	struct mlx5_ifc_query_cong_status_out_bits {
				5218	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5219	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5220
				5221	u8 syndrome[0x20];
				5222
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5223	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5224
				5225	u8 enable[0x1];
				5226	u8 tag_enable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5227	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5228	};
				5229
				5230	struct mlx5_ifc_query_cong_status_in_bits {
				5231	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5232	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5233
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5234	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5235	u8 op_mod[0x10];
				5236
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5237	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5238	u8 priority[0x4];
				5239	u8 cong_protocol[0x4];
				5240
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5241	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5242	};
				5243
				5244	struct mlx5_ifc_query_cong_statistics_out_bits {
				5245	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5246	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5247
				5248	u8 syndrome[0x20];
				5249
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5250	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5251
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5252	u8 rp_cur_flows[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5253
				5254	u8 sum_flows[0x20];
				5255
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5256	u8 rp_cnp_ignored_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5257
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5258	u8 rp_cnp_ignored_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5259
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5260	u8 rp_cnp_handled_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5261
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5262	u8 rp_cnp_handled_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5263
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5264	u8 reserved_at_140[0x100];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5265
				5266	u8 time_stamp_high[0x20];
				5267
				5268	u8 time_stamp_low[0x20];
				5269
				5270	u8 accumulators_period[0x20];
				5271
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5272	u8 np_ecn_marked_roce_packets_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5273
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5274	u8 np_ecn_marked_roce_packets_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5275
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5276	u8 np_cnp_sent_high[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5277
Parav Pandit	e1f24a7	2017-04-16 07:29:29 +0300	[diff] [blame]	5278	u8 np_cnp_sent_low[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5279
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5280	u8 reserved_at_320[0x560];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5281	};
				5282
				5283	struct mlx5_ifc_query_cong_statistics_in_bits {
				5284	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5285	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5286
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5287	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5288	u8 op_mod[0x10];
				5289
				5290	u8 clear[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5291	u8 reserved_at_41[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5292
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5293	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5294	};
				5295
				5296	struct mlx5_ifc_query_cong_params_out_bits {
				5297	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5298	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5299
				5300	u8 syndrome[0x20];
				5301
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5302	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5303
				5304	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
				5305	};
				5306
				5307	struct mlx5_ifc_query_cong_params_in_bits {
				5308	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5309	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5310
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5311	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5312	u8 op_mod[0x10];
				5313
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5314	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5315	u8 cong_protocol[0x4];
				5316
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5317	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5318	};
				5319
				5320	struct mlx5_ifc_query_adapter_out_bits {
				5321	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5322	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5323
				5324	u8 syndrome[0x20];
				5325
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5326	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5327
				5328	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
				5329	};
				5330
				5331	struct mlx5_ifc_query_adapter_in_bits {
				5332	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5333	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5334
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5335	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5336	u8 op_mod[0x10];
				5337
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5338	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5339	};
				5340
				5341	struct mlx5_ifc_qp_2rst_out_bits {
				5342	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5343	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5344
				5345	u8 syndrome[0x20];
				5346
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5347	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5348	};
				5349
				5350	struct mlx5_ifc_qp_2rst_in_bits {
				5351	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5352	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5353
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5354	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5355	u8 op_mod[0x10];
				5356
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5357	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5358	u8 qpn[0x18];
				5359
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5360	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5361	};
				5362
				5363	struct mlx5_ifc_qp_2err_out_bits {
				5364	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5365	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5366
				5367	u8 syndrome[0x20];
				5368
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5369	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5370	};
				5371
				5372	struct mlx5_ifc_qp_2err_in_bits {
				5373	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5374	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5375
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5376	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5377	u8 op_mod[0x10];
				5378
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5379	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5380	u8 qpn[0x18];
				5381
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5382	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5383	};
				5384
				5385	struct mlx5_ifc_page_fault_resume_out_bits {
				5386	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5387	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5388
				5389	u8 syndrome[0x20];
				5390
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5391	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5392	};
				5393
				5394	struct mlx5_ifc_page_fault_resume_in_bits {
				5395	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5396	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5397
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5398	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5399	u8 op_mod[0x10];
				5400
				5401	u8 error[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5402	u8 reserved_at_41[0x4];
Artemy Kovalyov	223cdc7	2017-01-02 11:37:45 +0200	[diff] [blame]	5403	u8 page_fault_type[0x3];
				5404	u8 wq_number[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5405
Artemy Kovalyov	223cdc7	2017-01-02 11:37:45 +0200	[diff] [blame]	5406	u8 reserved_at_60[0x8];
				5407	u8 token[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5408	};
				5409
				5410	struct mlx5_ifc_nop_out_bits {
				5411	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5412	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5413
				5414	u8 syndrome[0x20];
				5415
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5416	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5417	};
				5418
				5419	struct mlx5_ifc_nop_in_bits {
				5420	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5421	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5422
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5423	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5424	u8 op_mod[0x10];
				5425
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5426	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5427	};
				5428
				5429	struct mlx5_ifc_modify_vport_state_out_bits {
				5430	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5431	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5432
				5433	u8 syndrome[0x20];
				5434
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5435	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5436	};
				5437
				5438	struct mlx5_ifc_modify_vport_state_in_bits {
				5439	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5440	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5441
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5442	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5443	u8 op_mod[0x10];
				5444
				5445	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5446	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5447	u8 vport_number[0x10];
				5448
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5449	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5450	u8 admin_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5451	u8 reserved_at_7c[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5452	};
				5453
				5454	struct mlx5_ifc_modify_tis_out_bits {
				5455	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5456	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5457
				5458	u8 syndrome[0x20];
				5459
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5460	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5461	};
				5462
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5463	struct mlx5_ifc_modify_tis_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5464	u8 reserved_at_0[0x20];
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5465
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	5466	u8 reserved_at_20[0x1d];
				5467	u8 lag_tx_port_affinity[0x1];
				5468	u8 strict_lag_tx_port_affinity[0x1];
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5469	u8 prio[0x1];
				5470	};
				5471
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5472	struct mlx5_ifc_modify_tis_in_bits {
				5473	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5474	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5475
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5476	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5477	u8 op_mod[0x10];
				5478
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5479	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5480	u8 tisn[0x18];
				5481
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5482	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5483
majd@mellanox.com	75850d0	2016-01-14 19:13:06 +0200	[diff] [blame]	5484	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5485
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5486	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5487
				5488	struct mlx5_ifc_tisc_bits ctx;
				5489	};
				5490
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5491	struct mlx5_ifc_modify_tir_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5492	u8 reserved_at_0[0x20];
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5493
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5494	u8 reserved_at_20[0x1b];
Tariq Toukan	6618996	2015-11-12 19:35:26 +0200	[diff] [blame]	5495	u8 self_lb_en[0x1];
Tariq Toukan	bdfc028	2016-02-29 21:17:12 +0200	[diff] [blame]	5496	u8 reserved_at_3c[0x1];
				5497	u8 hash[0x1];
				5498	u8 reserved_at_3e[0x1];
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5499	u8 lro[0x1];
				5500	};
				5501
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5502	struct mlx5_ifc_modify_tir_out_bits {
				5503	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5504	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5505
				5506	u8 syndrome[0x20];
				5507
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5508	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5509	};
				5510
				5511	struct mlx5_ifc_modify_tir_in_bits {
				5512	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5513	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5514
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5515	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5516	u8 op_mod[0x10];
				5517
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5518	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5519	u8 tirn[0x18];
				5520
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5521	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5522
Achiad Shochat	d9eea40	2015-08-04 14:05:42 +0300	[diff] [blame]	5523	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5524
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5525	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5526
				5527	struct mlx5_ifc_tirc_bits ctx;
				5528	};
				5529
				5530	struct mlx5_ifc_modify_sq_out_bits {
				5531	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5532	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5533
				5534	u8 syndrome[0x20];
				5535
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5536	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5537	};
				5538
				5539	struct mlx5_ifc_modify_sq_in_bits {
				5540	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	5541	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5542
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5543	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5544	u8 op_mod[0x10];
				5545
				5546	u8 sq_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5547	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5548	u8 sqn[0x18];
				5549
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5550	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5551
				5552	u8 modify_bitmask[0x40];
				5553
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5554	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5555
				5556	struct mlx5_ifc_sqc_bits ctx;
				5557	};
				5558
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	5559	struct mlx5_ifc_modify_scheduling_element_out_bits {
				5560	u8 status[0x8];
				5561	u8 reserved_at_8[0x18];
				5562
				5563	u8 syndrome[0x20];
				5564
				5565	u8 reserved_at_40[0x1c0];
				5566	};
				5567
				5568	enum {
				5569	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
				5570	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
				5571	};
				5572
				5573	struct mlx5_ifc_modify_scheduling_element_in_bits {
				5574	u8 opcode[0x10];
				5575	u8 reserved_at_10[0x10];
				5576
				5577	u8 reserved_at_20[0x10];
				5578	u8 op_mod[0x10];
				5579
				5580	u8 scheduling_hierarchy[0x8];
				5581	u8 reserved_at_48[0x18];
				5582
				5583	u8 scheduling_element_id[0x20];
				5584
				5585	u8 reserved_at_80[0x20];
				5586
				5587	u8 modify_bitmask[0x20];
				5588
				5589	u8 reserved_at_c0[0x40];
				5590
				5591	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				5592
				5593	u8 reserved_at_300[0x100];
				5594	};
				5595
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5596	struct mlx5_ifc_modify_rqt_out_bits {
				5597	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5598	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5599
				5600	u8 syndrome[0x20];
				5601
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5602	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5603	};
				5604
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5605	struct mlx5_ifc_rqt_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5606	u8 reserved_at_0[0x20];
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5607
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5608	u8 reserved_at_20[0x1f];
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5609	u8 rqn_list[0x1];
				5610	};
				5611
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5612	struct mlx5_ifc_modify_rqt_in_bits {
				5613	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5614	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5615
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5616	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5617	u8 op_mod[0x10];
				5618
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5619	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5620	u8 rqtn[0x18];
				5621
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5622	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5623
Achiad Shochat	5c50368	2015-08-04 14:05:43 +0300	[diff] [blame]	5624	struct mlx5_ifc_rqt_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5625
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5626	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5627
				5628	struct mlx5_ifc_rqtc_bits ctx;
				5629	};
				5630
				5631	struct mlx5_ifc_modify_rq_out_bits {
				5632	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5633	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5634
				5635	u8 syndrome[0x20];
				5636
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5637	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5638	};
				5639
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	5640	enum {
				5641	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
Guy Ergas	102722f	2017-02-20 16:18:17 +0200	[diff] [blame]	5642	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
Majd Dibbiny	23a6964	2017-01-18 15:25:10 +0200	[diff] [blame]	5643	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
Alex Vesker	83b502a	2016-08-04 17:32:02 +0300	[diff] [blame]	5644	};
				5645
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5646	struct mlx5_ifc_modify_rq_in_bits {
				5647	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	5648	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5649
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5650	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5651	u8 op_mod[0x10];
				5652
				5653	u8 rq_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5654	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5655	u8 rqn[0x18];
				5656
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5657	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5658
				5659	u8 modify_bitmask[0x40];
				5660
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5661	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5662
				5663	struct mlx5_ifc_rqc_bits ctx;
				5664	};
				5665
				5666	struct mlx5_ifc_modify_rmp_out_bits {
				5667	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5668	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5669
				5670	u8 syndrome[0x20];
				5671
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5672	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5673	};
				5674
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5675	struct mlx5_ifc_rmp_bitmask_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5676	u8 reserved_at_0[0x20];
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5677
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5678	u8 reserved_at_20[0x1f];
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5679	u8 lwm[0x1];
				5680	};
				5681
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5682	struct mlx5_ifc_modify_rmp_in_bits {
				5683	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	5684	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5685
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5686	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5687	u8 op_mod[0x10];
				5688
				5689	u8 rmp_state[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5690	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5691	u8 rmpn[0x18];
				5692
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5693	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5694
Haggai Abramonvsky	01949d0	2015-06-04 19:30:38 +0300	[diff] [blame]	5695	struct mlx5_ifc_rmp_bitmask_bits bitmask;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5696
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5697	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5698
				5699	struct mlx5_ifc_rmpc_bits ctx;
				5700	};
				5701
				5702	struct mlx5_ifc_modify_nic_vport_context_out_bits {
				5703	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5704	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5705
				5706	u8 syndrome[0x20];
				5707
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5708	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5709	};
				5710
				5711	struct mlx5_ifc_modify_nic_vport_field_select_bits {
Daniel Jurgens	32f69e4	2018-01-04 17:25:36 +0200	[diff] [blame]	5712	u8 reserved_at_0[0x12];
				5713	u8 affiliation[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	5714	u8 reserved_at_13[0x1];
Huy Nguyen	bded747	2017-05-30 09:42:53 +0300	[diff] [blame]	5715	u8 disable_uc_local_lb[0x1];
				5716	u8 disable_mc_local_lb[0x1];
Noa Osherovich	23898c7	2016-06-10 00:07:37 +0300	[diff] [blame]	5717	u8 node_guid[0x1];
				5718	u8 port_guid[0x1];
Hadar Hen Zion	9def712	2016-08-03 17:27:30 +0300	[diff] [blame]	5719	u8 min_inline[0x1];
Saeed Mahameed	d82b731	2015-12-01 18:03:14 +0200	[diff] [blame]	5720	u8 mtu[0x1];
				5721	u8 change_event[0x1];
				5722	u8 promisc[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5723	u8 permanent_address[0x1];
				5724	u8 addresses_list[0x1];
				5725	u8 roce_en[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5726	u8 reserved_at_1f[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5727	};
				5728
				5729	struct mlx5_ifc_modify_nic_vport_context_in_bits {
				5730	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5731	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5732
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5733	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5734	u8 op_mod[0x10];
				5735
				5736	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5737	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5738	u8 vport_number[0x10];
				5739
				5740	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
				5741
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5742	u8 reserved_at_80[0x780];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5743
				5744	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
				5745	};
				5746
				5747	struct mlx5_ifc_modify_hca_vport_context_out_bits {
				5748	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5749	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5750
				5751	u8 syndrome[0x20];
				5752
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5753	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5754	};
				5755
				5756	struct mlx5_ifc_modify_hca_vport_context_in_bits {
				5757	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5758	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5759
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5760	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5761	u8 op_mod[0x10];
				5762
				5763	u8 other_vport[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5764	u8 reserved_at_41[0xb];
Majd Dibbiny	707c460	2015-06-04 19:30:41 +0300	[diff] [blame]	5765	u8 port_num[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5766	u8 vport_number[0x10];
				5767
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5768	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5769
				5770	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
				5771	};
				5772
				5773	struct mlx5_ifc_modify_cq_out_bits {
				5774	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5775	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5776
				5777	u8 syndrome[0x20];
				5778
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5779	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5780	};
				5781
				5782	enum {
				5783	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
				5784	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
				5785	};
				5786
				5787	struct mlx5_ifc_modify_cq_in_bits {
				5788	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	5789	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5790
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5791	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5792	u8 op_mod[0x10];
				5793
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5794	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5795	u8 cqn[0x18];
				5796
				5797	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
				5798
				5799	struct mlx5_ifc_cqc_bits cq_context;
				5800
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	5801	u8 reserved_at_280[0x40];
				5802
				5803	u8 cq_umem_valid[0x1];
				5804	u8 reserved_at_2c1[0x5bf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5805
				5806	u8 pas[0][0x40];
				5807	};
				5808
				5809	struct mlx5_ifc_modify_cong_status_out_bits {
				5810	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5811	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5812
				5813	u8 syndrome[0x20];
				5814
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5815	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5816	};
				5817
				5818	struct mlx5_ifc_modify_cong_status_in_bits {
				5819	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5820	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5821
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5822	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5823	u8 op_mod[0x10];
				5824
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5825	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5826	u8 priority[0x4];
				5827	u8 cong_protocol[0x4];
				5828
				5829	u8 enable[0x1];
				5830	u8 tag_enable[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5831	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5832	};
				5833
				5834	struct mlx5_ifc_modify_cong_params_out_bits {
				5835	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5836	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5837
				5838	u8 syndrome[0x20];
				5839
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5840	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5841	};
				5842
				5843	struct mlx5_ifc_modify_cong_params_in_bits {
				5844	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5845	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5846
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5847	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5848	u8 op_mod[0x10];
				5849
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5850	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5851	u8 cong_protocol[0x4];
				5852
				5853	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
				5854
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5855	u8 reserved_at_80[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5856
				5857	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
				5858	};
				5859
				5860	struct mlx5_ifc_manage_pages_out_bits {
				5861	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5862	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5863
				5864	u8 syndrome[0x20];
				5865
				5866	u8 output_num_entries[0x20];
				5867
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5868	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5869
				5870	u8 pas[0][0x40];
				5871	};
				5872
				5873	enum {
				5874	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
				5875	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
				5876	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
				5877	};
				5878
				5879	struct mlx5_ifc_manage_pages_in_bits {
				5880	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5881	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5882
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5883	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5884	u8 op_mod[0x10];
				5885
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	5886	u8 embedded_cpu_function[0x1];
				5887	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5888	u8 function_id[0x10];
				5889
				5890	u8 input_num_entries[0x20];
				5891
				5892	u8 pas[0][0x40];
				5893	};
				5894
				5895	struct mlx5_ifc_mad_ifc_out_bits {
				5896	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5897	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5898
				5899	u8 syndrome[0x20];
				5900
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5901	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5902
				5903	u8 response_mad_packet[256][0x8];
				5904	};
				5905
				5906	struct mlx5_ifc_mad_ifc_in_bits {
				5907	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5908	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5909
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5910	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5911	u8 op_mod[0x10];
				5912
				5913	u8 remote_lid[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5914	u8 reserved_at_50[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5915	u8 port[0x8];
				5916
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5917	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5918
				5919	u8 mad[256][0x8];
				5920	};
				5921
				5922	struct mlx5_ifc_init_hca_out_bits {
				5923	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5924	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5925
				5926	u8 syndrome[0x20];
				5927
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5928	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5929	};
				5930
				5931	struct mlx5_ifc_init_hca_in_bits {
				5932	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5933	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5934
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5935	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5936	u8 op_mod[0x10];
				5937
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5938	u8 reserved_at_40[0x40];
Daniel Jurgens	8737f81	2018-01-04 17:25:32 +0200	[diff] [blame]	5939	u8 sw_owner_id[4][0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5940	};
				5941
				5942	struct mlx5_ifc_init2rtr_qp_out_bits {
				5943	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5944	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5945
				5946	u8 syndrome[0x20];
				5947
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5948	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5949	};
				5950
				5951	struct mlx5_ifc_init2rtr_qp_in_bits {
				5952	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5953	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5954
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5955	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5956	u8 op_mod[0x10];
				5957
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5958	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5959	u8 qpn[0x18];
				5960
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5961	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5962
				5963	u8 opt_param_mask[0x20];
				5964
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5965	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5966
				5967	struct mlx5_ifc_qpc_bits qpc;
				5968
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5969	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5970	};
				5971
				5972	struct mlx5_ifc_init2init_qp_out_bits {
				5973	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5974	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5975
				5976	u8 syndrome[0x20];
				5977
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5978	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5979	};
				5980
				5981	struct mlx5_ifc_init2init_qp_in_bits {
				5982	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	5983	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5984
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5985	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5986	u8 op_mod[0x10];
				5987
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5988	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5989	u8 qpn[0x18];
				5990
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5991	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5992
				5993	u8 opt_param_mask[0x20];
				5994
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5995	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	5996
				5997	struct mlx5_ifc_qpc_bits qpc;
				5998
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	5999	u8 reserved_at_800[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6000	};
				6001
				6002	struct mlx5_ifc_get_dropped_packet_log_out_bits {
				6003	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6004	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6005
				6006	u8 syndrome[0x20];
				6007
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6008	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6009
				6010	u8 packet_headers_log[128][0x8];
				6011
				6012	u8 packet_syndrome[64][0x8];
				6013	};
				6014
				6015	struct mlx5_ifc_get_dropped_packet_log_in_bits {
				6016	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6017	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6018
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6019	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6020	u8 op_mod[0x10];
				6021
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6022	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6023	};
				6024
				6025	struct mlx5_ifc_gen_eqe_in_bits {
				6026	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6027	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6028
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6029	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6030	u8 op_mod[0x10];
				6031
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6032	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6033	u8 eq_number[0x8];
				6034
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6035	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6036
				6037	u8 eqe[64][0x8];
				6038	};
				6039
				6040	struct mlx5_ifc_gen_eq_out_bits {
				6041	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6042	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6043
				6044	u8 syndrome[0x20];
				6045
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6046	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6047	};
				6048
				6049	struct mlx5_ifc_enable_hca_out_bits {
				6050	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6051	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6052
				6053	u8 syndrome[0x20];
				6054
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6055	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6056	};
				6057
				6058	struct mlx5_ifc_enable_hca_in_bits {
				6059	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6060	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6061
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6062	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6063	u8 op_mod[0x10];
				6064
Bodong Wang	22e939a	2019-02-12 22:55:36 -0800	[diff] [blame]	6065	u8 embedded_cpu_function[0x1];
				6066	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6067	u8 function_id[0x10];
				6068
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6069	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6070	};
				6071
				6072	struct mlx5_ifc_drain_dct_out_bits {
				6073	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6074	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6075
				6076	u8 syndrome[0x20];
				6077
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6078	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6079	};
				6080
				6081	struct mlx5_ifc_drain_dct_in_bits {
				6082	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	6083	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6084
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6085	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6086	u8 op_mod[0x10];
				6087
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6088	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6089	u8 dctn[0x18];
				6090
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6091	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6092	};
				6093
				6094	struct mlx5_ifc_disable_hca_out_bits {
				6095	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6096	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6097
				6098	u8 syndrome[0x20];
				6099
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6100	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6101	};
				6102
				6103	struct mlx5_ifc_disable_hca_in_bits {
				6104	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6105	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6106
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6107	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6108	u8 op_mod[0x10];
				6109
Bodong Wang	22e939a	2019-02-12 22:55:36 -0800	[diff] [blame]	6110	u8 embedded_cpu_function[0x1];
				6111	u8 reserved_at_41[0xf];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6112	u8 function_id[0x10];
				6113
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6114	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6115	};
				6116
				6117	struct mlx5_ifc_detach_from_mcg_out_bits {
				6118	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6119	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6120
				6121	u8 syndrome[0x20];
				6122
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6123	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6124	};
				6125
				6126	struct mlx5_ifc_detach_from_mcg_in_bits {
				6127	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6128	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6129
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6130	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6131	u8 op_mod[0x10];
				6132
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6133	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6134	u8 qpn[0x18];
				6135
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6136	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6137
				6138	u8 multicast_gid[16][0x8];
				6139	};
				6140
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6141	struct mlx5_ifc_destroy_xrq_out_bits {
				6142	u8 status[0x8];
				6143	u8 reserved_at_8[0x18];
				6144
				6145	u8 syndrome[0x20];
				6146
				6147	u8 reserved_at_40[0x40];
				6148	};
				6149
				6150	struct mlx5_ifc_destroy_xrq_in_bits {
				6151	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6152	u8 uid[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6153
				6154	u8 reserved_at_20[0x10];
				6155	u8 op_mod[0x10];
				6156
				6157	u8 reserved_at_40[0x8];
				6158	u8 xrqn[0x18];
				6159
				6160	u8 reserved_at_60[0x20];
				6161	};
				6162
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6163	struct mlx5_ifc_destroy_xrc_srq_out_bits {
				6164	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6165	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6166
				6167	u8 syndrome[0x20];
				6168
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6169	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6170	};
				6171
				6172	struct mlx5_ifc_destroy_xrc_srq_in_bits {
				6173	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6174	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6175
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6176	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6177	u8 op_mod[0x10];
				6178
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6179	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6180	u8 xrc_srqn[0x18];
				6181
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6182	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6183	};
				6184
				6185	struct mlx5_ifc_destroy_tis_out_bits {
				6186	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6187	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6188
				6189	u8 syndrome[0x20];
				6190
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6191	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6192	};
				6193
				6194	struct mlx5_ifc_destroy_tis_in_bits {
				6195	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6196	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6197
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6198	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6199	u8 op_mod[0x10];
				6200
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6201	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6202	u8 tisn[0x18];
				6203
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6204	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6205	};
				6206
				6207	struct mlx5_ifc_destroy_tir_out_bits {
				6208	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6209	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6210
				6211	u8 syndrome[0x20];
				6212
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6213	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6214	};
				6215
				6216	struct mlx5_ifc_destroy_tir_in_bits {
				6217	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6218	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6219
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6220	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6221	u8 op_mod[0x10];
				6222
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6223	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6224	u8 tirn[0x18];
				6225
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6226	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6227	};
				6228
				6229	struct mlx5_ifc_destroy_srq_out_bits {
				6230	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6231	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6232
				6233	u8 syndrome[0x20];
				6234
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6235	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6236	};
				6237
				6238	struct mlx5_ifc_destroy_srq_in_bits {
				6239	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6240	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6241
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6242	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6243	u8 op_mod[0x10];
				6244
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6245	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6246	u8 srqn[0x18];
				6247
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6248	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6249	};
				6250
				6251	struct mlx5_ifc_destroy_sq_out_bits {
				6252	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6253	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6254
				6255	u8 syndrome[0x20];
				6256
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6257	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6258	};
				6259
				6260	struct mlx5_ifc_destroy_sq_in_bits {
				6261	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	6262	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6263
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6264	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6265	u8 op_mod[0x10];
				6266
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6267	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6268	u8 sqn[0x18];
				6269
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6270	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6271	};
				6272
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	6273	struct mlx5_ifc_destroy_scheduling_element_out_bits {
				6274	u8 status[0x8];
				6275	u8 reserved_at_8[0x18];
				6276
				6277	u8 syndrome[0x20];
				6278
				6279	u8 reserved_at_40[0x1c0];
				6280	};
				6281
				6282	struct mlx5_ifc_destroy_scheduling_element_in_bits {
				6283	u8 opcode[0x10];
				6284	u8 reserved_at_10[0x10];
				6285
				6286	u8 reserved_at_20[0x10];
				6287	u8 op_mod[0x10];
				6288
				6289	u8 scheduling_hierarchy[0x8];
				6290	u8 reserved_at_48[0x18];
				6291
				6292	u8 scheduling_element_id[0x20];
				6293
				6294	u8 reserved_at_80[0x180];
				6295	};
				6296
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6297	struct mlx5_ifc_destroy_rqt_out_bits {
				6298	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6299	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6300
				6301	u8 syndrome[0x20];
				6302
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6303	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6304	};
				6305
				6306	struct mlx5_ifc_destroy_rqt_in_bits {
				6307	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6308	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6309
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6310	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6311	u8 op_mod[0x10];
				6312
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6313	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6314	u8 rqtn[0x18];
				6315
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6316	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6317	};
				6318
				6319	struct mlx5_ifc_destroy_rq_out_bits {
				6320	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6321	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6322
				6323	u8 syndrome[0x20];
				6324
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6325	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6326	};
				6327
				6328	struct mlx5_ifc_destroy_rq_in_bits {
				6329	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	6330	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6331
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6332	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6333	u8 op_mod[0x10];
				6334
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6335	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6336	u8 rqn[0x18];
				6337
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6338	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6339	};
				6340
Maor Gottlieb	c1e0bfc	2017-05-30 10:29:11 +0300	[diff] [blame]	6341	struct mlx5_ifc_set_delay_drop_params_in_bits {
				6342	u8 opcode[0x10];
				6343	u8 reserved_at_10[0x10];
				6344
				6345	u8 reserved_at_20[0x10];
				6346	u8 op_mod[0x10];
				6347
				6348	u8 reserved_at_40[0x20];
				6349
				6350	u8 reserved_at_60[0x10];
				6351	u8 delay_drop_timeout[0x10];
				6352	};
				6353
				6354	struct mlx5_ifc_set_delay_drop_params_out_bits {
				6355	u8 status[0x8];
				6356	u8 reserved_at_8[0x18];
				6357
				6358	u8 syndrome[0x20];
				6359
				6360	u8 reserved_at_40[0x40];
				6361	};
				6362
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6363	struct mlx5_ifc_destroy_rmp_out_bits {
				6364	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6365	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6366
				6367	u8 syndrome[0x20];
				6368
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6369	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6370	};
				6371
				6372	struct mlx5_ifc_destroy_rmp_in_bits {
				6373	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6374	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6375
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6376	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6377	u8 op_mod[0x10];
				6378
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6379	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6380	u8 rmpn[0x18];
				6381
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6382	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6383	};
				6384
				6385	struct mlx5_ifc_destroy_qp_out_bits {
				6386	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6387	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6388
				6389	u8 syndrome[0x20];
				6390
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6391	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6392	};
				6393
				6394	struct mlx5_ifc_destroy_qp_in_bits {
				6395	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	6396	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6397
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6398	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6399	u8 op_mod[0x10];
				6400
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6401	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6402	u8 qpn[0x18];
				6403
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6404	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6405	};
				6406
				6407	struct mlx5_ifc_destroy_psv_out_bits {
				6408	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6409	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6410
				6411	u8 syndrome[0x20];
				6412
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6413	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6414	};
				6415
				6416	struct mlx5_ifc_destroy_psv_in_bits {
				6417	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6418	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6419
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6420	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6421	u8 op_mod[0x10];
				6422
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6423	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6424	u8 psvn[0x18];
				6425
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6426	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6427	};
				6428
				6429	struct mlx5_ifc_destroy_mkey_out_bits {
				6430	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6431	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6432
				6433	u8 syndrome[0x20];
				6434
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6435	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6436	};
				6437
				6438	struct mlx5_ifc_destroy_mkey_in_bits {
				6439	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6440	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6441
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6442	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6443	u8 op_mod[0x10];
				6444
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6445	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6446	u8 mkey_index[0x18];
				6447
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6448	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6449	};
				6450
				6451	struct mlx5_ifc_destroy_flow_table_out_bits {
				6452	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6453	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6454
				6455	u8 syndrome[0x20];
				6456
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6457	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6458	};
				6459
				6460	struct mlx5_ifc_destroy_flow_table_in_bits {
				6461	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6462	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6463
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6464	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6465	u8 op_mod[0x10];
				6466
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6467	u8 other_vport[0x1];
				6468	u8 reserved_at_41[0xf];
				6469	u8 vport_number[0x10];
				6470
				6471	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6472
				6473	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6474	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6475
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6476	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6477	u8 table_id[0x18];
				6478
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6479	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6480	};
				6481
				6482	struct mlx5_ifc_destroy_flow_group_out_bits {
				6483	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6484	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6485
				6486	u8 syndrome[0x20];
				6487
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6488	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6489	};
				6490
				6491	struct mlx5_ifc_destroy_flow_group_in_bits {
				6492	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6493	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6494
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6495	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6496	u8 op_mod[0x10];
				6497
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6498	u8 other_vport[0x1];
				6499	u8 reserved_at_41[0xf];
				6500	u8 vport_number[0x10];
				6501
				6502	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6503
				6504	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6505	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6506
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6507	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6508	u8 table_id[0x18];
				6509
				6510	u8 group_id[0x20];
				6511
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6512	u8 reserved_at_e0[0x120];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6513	};
				6514
				6515	struct mlx5_ifc_destroy_eq_out_bits {
				6516	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6517	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6518
				6519	u8 syndrome[0x20];
				6520
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6521	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6522	};
				6523
				6524	struct mlx5_ifc_destroy_eq_in_bits {
				6525	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6526	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6527
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6528	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6529	u8 op_mod[0x10];
				6530
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6531	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6532	u8 eq_number[0x8];
				6533
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6534	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6535	};
				6536
				6537	struct mlx5_ifc_destroy_dct_out_bits {
				6538	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6539	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6540
				6541	u8 syndrome[0x20];
				6542
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6543	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6544	};
				6545
				6546	struct mlx5_ifc_destroy_dct_in_bits {
				6547	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	6548	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6549
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6550	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6551	u8 op_mod[0x10];
				6552
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6553	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6554	u8 dctn[0x18];
				6555
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6556	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6557	};
				6558
				6559	struct mlx5_ifc_destroy_cq_out_bits {
				6560	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6561	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6562
				6563	u8 syndrome[0x20];
				6564
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6565	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6566	};
				6567
				6568	struct mlx5_ifc_destroy_cq_in_bits {
				6569	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	6570	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6571
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6572	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6573	u8 op_mod[0x10];
				6574
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6575	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6576	u8 cqn[0x18];
				6577
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6578	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6579	};
				6580
				6581	struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
				6582	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6583	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6584
				6585	u8 syndrome[0x20];
				6586
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6587	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6588	};
				6589
				6590	struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
				6591	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6592	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6593
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6594	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6595	u8 op_mod[0x10];
				6596
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6597	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6598
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6599	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6600	u8 vxlan_udp_port[0x10];
				6601	};
				6602
				6603	struct mlx5_ifc_delete_l2_table_entry_out_bits {
				6604	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6605	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6606
				6607	u8 syndrome[0x20];
				6608
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6609	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6610	};
				6611
				6612	struct mlx5_ifc_delete_l2_table_entry_in_bits {
				6613	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6614	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6615
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6616	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6617	u8 op_mod[0x10];
				6618
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6619	u8 reserved_at_40[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6620
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6621	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6622	u8 table_index[0x18];
				6623
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6624	u8 reserved_at_c0[0x140];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6625	};
				6626
				6627	struct mlx5_ifc_delete_fte_out_bits {
				6628	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6629	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6630
				6631	u8 syndrome[0x20];
				6632
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6633	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6634	};
				6635
				6636	struct mlx5_ifc_delete_fte_in_bits {
				6637	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6638	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6639
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6640	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6641	u8 op_mod[0x10];
				6642
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	6643	u8 other_vport[0x1];
				6644	u8 reserved_at_41[0xf];
				6645	u8 vport_number[0x10];
				6646
				6647	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6648
				6649	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6650	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6651
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6652	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6653	u8 table_id[0x18];
				6654
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6655	u8 reserved_at_c0[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6656
				6657	u8 flow_index[0x20];
				6658
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6659	u8 reserved_at_120[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6660	};
				6661
				6662	struct mlx5_ifc_dealloc_xrcd_out_bits {
				6663	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6664	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6665
				6666	u8 syndrome[0x20];
				6667
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6668	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6669	};
				6670
				6671	struct mlx5_ifc_dealloc_xrcd_in_bits {
				6672	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6673	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6674
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6675	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6676	u8 op_mod[0x10];
				6677
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6678	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6679	u8 xrcd[0x18];
				6680
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6681	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6682	};
				6683
				6684	struct mlx5_ifc_dealloc_uar_out_bits {
				6685	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6686	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6687
				6688	u8 syndrome[0x20];
				6689
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6690	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6691	};
				6692
				6693	struct mlx5_ifc_dealloc_uar_in_bits {
				6694	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6695	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6696
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6697	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6698	u8 op_mod[0x10];
				6699
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6700	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6701	u8 uar[0x18];
				6702
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6703	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6704	};
				6705
				6706	struct mlx5_ifc_dealloc_transport_domain_out_bits {
				6707	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6708	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6709
				6710	u8 syndrome[0x20];
				6711
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6712	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6713	};
				6714
				6715	struct mlx5_ifc_dealloc_transport_domain_in_bits {
				6716	u8 opcode[0x10];
Yishai Hadas	71bef2f	2018-12-19 16:28:10 +0200	[diff] [blame]	6717	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6718
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6719	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6720	u8 op_mod[0x10];
				6721
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6722	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6723	u8 transport_domain[0x18];
				6724
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6725	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6726	};
				6727
				6728	struct mlx5_ifc_dealloc_q_counter_out_bits {
				6729	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6730	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6731
				6732	u8 syndrome[0x20];
				6733
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6734	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6735	};
				6736
				6737	struct mlx5_ifc_dealloc_q_counter_in_bits {
				6738	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6739	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6740
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6741	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6742	u8 op_mod[0x10];
				6743
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6744	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6745	u8 counter_set_id[0x8];
				6746
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6747	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6748	};
				6749
				6750	struct mlx5_ifc_dealloc_pd_out_bits {
				6751	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6752	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6753
				6754	u8 syndrome[0x20];
				6755
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6756	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6757	};
				6758
				6759	struct mlx5_ifc_dealloc_pd_in_bits {
				6760	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6761	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6762
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6763	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6764	u8 op_mod[0x10];
				6765
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6766	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6767	u8 pd[0x18];
				6768
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6769	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6770	};
				6771
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	6772	struct mlx5_ifc_dealloc_flow_counter_out_bits {
				6773	u8 status[0x8];
				6774	u8 reserved_at_8[0x18];
				6775
				6776	u8 syndrome[0x20];
				6777
				6778	u8 reserved_at_40[0x40];
				6779	};
				6780
				6781	struct mlx5_ifc_dealloc_flow_counter_in_bits {
				6782	u8 opcode[0x10];
				6783	u8 reserved_at_10[0x10];
				6784
				6785	u8 reserved_at_20[0x10];
				6786	u8 op_mod[0x10];
				6787
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	6788	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	6789
				6790	u8 reserved_at_60[0x20];
				6791	};
				6792
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6793	struct mlx5_ifc_create_xrq_out_bits {
				6794	u8 status[0x8];
				6795	u8 reserved_at_8[0x18];
				6796
				6797	u8 syndrome[0x20];
				6798
				6799	u8 reserved_at_40[0x8];
				6800	u8 xrqn[0x18];
				6801
				6802	u8 reserved_at_60[0x20];
				6803	};
				6804
				6805	struct mlx5_ifc_create_xrq_in_bits {
				6806	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6807	u8 uid[0x10];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	6808
				6809	u8 reserved_at_20[0x10];
				6810	u8 op_mod[0x10];
				6811
				6812	u8 reserved_at_40[0x40];
				6813
				6814	struct mlx5_ifc_xrqc_bits xrq_context;
				6815	};
				6816
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6817	struct mlx5_ifc_create_xrc_srq_out_bits {
				6818	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6819	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6820
				6821	u8 syndrome[0x20];
				6822
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6823	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6824	u8 xrc_srqn[0x18];
				6825
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6826	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6827	};
				6828
				6829	struct mlx5_ifc_create_xrc_srq_in_bits {
				6830	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6831	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6832
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6833	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6834	u8 op_mod[0x10];
				6835
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6836	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6837
				6838	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
				6839
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	6840	u8 reserved_at_280[0x60];
				6841
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6842	u8 xrc_srq_umem_valid[0x1];
Yishai Hadas	99b77fe	2018-10-31 12:20:28 +0200	[diff] [blame]	6843	u8 reserved_at_2e1[0x1f];
				6844
				6845	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6846
				6847	u8 pas[0][0x40];
				6848	};
				6849
				6850	struct mlx5_ifc_create_tis_out_bits {
				6851	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6852	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6853
				6854	u8 syndrome[0x20];
				6855
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6856	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6857	u8 tisn[0x18];
				6858
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6859	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6860	};
				6861
				6862	struct mlx5_ifc_create_tis_in_bits {
				6863	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6864	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6865
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6866	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6867	u8 op_mod[0x10];
				6868
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6869	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6870
				6871	struct mlx5_ifc_tisc_bits ctx;
				6872	};
				6873
				6874	struct mlx5_ifc_create_tir_out_bits {
				6875	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6876	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6877
				6878	u8 syndrome[0x20];
				6879
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6880	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6881	u8 tirn[0x18];
				6882
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6883	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6884	};
				6885
				6886	struct mlx5_ifc_create_tir_in_bits {
				6887	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6888	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6889
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6890	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6891	u8 op_mod[0x10];
				6892
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6893	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6894
				6895	struct mlx5_ifc_tirc_bits ctx;
				6896	};
				6897
				6898	struct mlx5_ifc_create_srq_out_bits {
				6899	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6900	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6901
				6902	u8 syndrome[0x20];
				6903
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6904	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6905	u8 srqn[0x18];
				6906
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6907	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6908	};
				6909
				6910	struct mlx5_ifc_create_srq_in_bits {
				6911	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	6912	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6913
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6914	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6915	u8 op_mod[0x10];
				6916
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6917	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6918
				6919	struct mlx5_ifc_srqc_bits srq_context_entry;
				6920
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6921	u8 reserved_at_280[0x600];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6922
				6923	u8 pas[0][0x40];
				6924	};
				6925
				6926	struct mlx5_ifc_create_sq_out_bits {
				6927	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6928	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6929
				6930	u8 syndrome[0x20];
				6931
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6932	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6933	u8 sqn[0x18];
				6934
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6935	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6936	};
				6937
				6938	struct mlx5_ifc_create_sq_in_bits {
				6939	u8 opcode[0x10];
Yishai Hadas	430ae0d5	2018-09-20 21:35:23 +0300	[diff] [blame]	6940	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6941
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6942	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6943	u8 op_mod[0x10];
				6944
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6945	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6946
				6947	struct mlx5_ifc_sqc_bits ctx;
				6948	};
				6949
Mohamad Haj Yahia	813f854	2016-08-11 11:21:39 +0300	[diff] [blame]	6950	struct mlx5_ifc_create_scheduling_element_out_bits {
				6951	u8 status[0x8];
				6952	u8 reserved_at_8[0x18];
				6953
				6954	u8 syndrome[0x20];
				6955
				6956	u8 reserved_at_40[0x40];
				6957
				6958	u8 scheduling_element_id[0x20];
				6959
				6960	u8 reserved_at_a0[0x160];
				6961	};
				6962
				6963	struct mlx5_ifc_create_scheduling_element_in_bits {
				6964	u8 opcode[0x10];
				6965	u8 reserved_at_10[0x10];
				6966
				6967	u8 reserved_at_20[0x10];
				6968	u8 op_mod[0x10];
				6969
				6970	u8 scheduling_hierarchy[0x8];
				6971	u8 reserved_at_48[0x18];
				6972
				6973	u8 reserved_at_60[0xa0];
				6974
				6975	struct mlx5_ifc_scheduling_context_bits scheduling_context;
				6976
				6977	u8 reserved_at_300[0x100];
				6978	};
				6979
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6980	struct mlx5_ifc_create_rqt_out_bits {
				6981	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6982	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6983
				6984	u8 syndrome[0x20];
				6985
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6986	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6987	u8 rqtn[0x18];
				6988
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6989	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6990	};
				6991
				6992	struct mlx5_ifc_create_rqt_in_bits {
				6993	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	6994	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6995
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6996	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	6997	u8 op_mod[0x10];
				6998
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	6999	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7000
				7001	struct mlx5_ifc_rqtc_bits rqt_context;
				7002	};
				7003
				7004	struct mlx5_ifc_create_rq_out_bits {
				7005	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7006	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7007
				7008	u8 syndrome[0x20];
				7009
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7010	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7011	u8 rqn[0x18];
				7012
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7013	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7014	};
				7015
				7016	struct mlx5_ifc_create_rq_in_bits {
				7017	u8 opcode[0x10];
Yishai Hadas	d269b3a	2018-09-20 21:35:22 +0300	[diff] [blame]	7018	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7019
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7020	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7021	u8 op_mod[0x10];
				7022
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7023	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7024
				7025	struct mlx5_ifc_rqc_bits ctx;
				7026	};
				7027
				7028	struct mlx5_ifc_create_rmp_out_bits {
				7029	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7030	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7031
				7032	u8 syndrome[0x20];
				7033
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7034	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7035	u8 rmpn[0x18];
				7036
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7037	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7038	};
				7039
				7040	struct mlx5_ifc_create_rmp_in_bits {
				7041	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7042	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7043
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7044	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7045	u8 op_mod[0x10];
				7046
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7047	u8 reserved_at_40[0xc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7048
				7049	struct mlx5_ifc_rmpc_bits ctx;
				7050	};
				7051
				7052	struct mlx5_ifc_create_qp_out_bits {
				7053	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7054	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7055
				7056	u8 syndrome[0x20];
				7057
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7058	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7059	u8 qpn[0x18];
				7060
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7061	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7062	};
				7063
				7064	struct mlx5_ifc_create_qp_in_bits {
				7065	u8 opcode[0x10];
Yishai Hadas	4ac63ec	2018-09-20 21:35:21 +0300	[diff] [blame]	7066	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7067
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7068	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7069	u8 op_mod[0x10];
				7070
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7071	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7072
				7073	u8 opt_param_mask[0x20];
				7074
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7075	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7076
				7077	struct mlx5_ifc_qpc_bits qpc;
				7078
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7079	u8 reserved_at_800[0x60];
				7080
				7081	u8 wq_umem_valid[0x1];
				7082	u8 reserved_at_861[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7083
				7084	u8 pas[0][0x40];
				7085	};
				7086
				7087	struct mlx5_ifc_create_psv_out_bits {
				7088	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7089	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7090
				7091	u8 syndrome[0x20];
				7092
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7093	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7094
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7095	u8 reserved_at_80[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7096	u8 psv0_index[0x18];
				7097
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7098	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7099	u8 psv1_index[0x18];
				7100
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7101	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7102	u8 psv2_index[0x18];
				7103
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7104	u8 reserved_at_e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7105	u8 psv3_index[0x18];
				7106	};
				7107
				7108	struct mlx5_ifc_create_psv_in_bits {
				7109	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7110	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7111
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7112	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7113	u8 op_mod[0x10];
				7114
				7115	u8 num_psv[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7116	u8 reserved_at_44[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7117	u8 pd[0x18];
				7118
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7119	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7120	};
				7121
				7122	struct mlx5_ifc_create_mkey_out_bits {
				7123	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7124	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7125
				7126	u8 syndrome[0x20];
				7127
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7128	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7129	u8 mkey_index[0x18];
				7130
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7131	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7132	};
				7133
				7134	struct mlx5_ifc_create_mkey_in_bits {
				7135	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7136	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7137
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7138	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7139	u8 op_mod[0x10];
				7140
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7141	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7142
				7143	u8 pg_access[0x1];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7144	u8 mkey_umem_valid[0x1];
				7145	u8 reserved_at_62[0x1e];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7146
				7147	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
				7148
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7149	u8 reserved_at_280[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7150
				7151	u8 translations_octword_actual_size[0x20];
				7152
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7153	u8 reserved_at_320[0x560];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7154
				7155	u8 klm_pas_mtt[0][0x20];
				7156	};
				7157
				7158	struct mlx5_ifc_create_flow_table_out_bits {
				7159	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7160	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7161
				7162	u8 syndrome[0x20];
				7163
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7164	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7165	u8 table_id[0x18];
				7166
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7167	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7168	};
				7169
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7170	struct mlx5_ifc_flow_table_context_bits {
Mark Bloch	60786f0	2018-08-28 14:18:46 +0300	[diff] [blame]	7171	u8 reformat_en[0x1];
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7172	u8 decap_en[0x1];
				7173	u8 reserved_at_2[0x2];
				7174	u8 table_miss_action[0x4];
				7175	u8 level[0x8];
				7176	u8 reserved_at_10[0x8];
				7177	u8 log_size[0x8];
				7178
				7179	u8 reserved_at_20[0x8];
				7180	u8 table_miss_id[0x18];
				7181
				7182	u8 reserved_at_40[0x8];
				7183	u8 lag_master_next_table_id[0x18];
				7184
				7185	u8 reserved_at_60[0xe0];
				7186	};
				7187
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7188	struct mlx5_ifc_create_flow_table_in_bits {
				7189	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7190	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7191
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7192	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7193	u8 op_mod[0x10];
				7194
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7195	u8 other_vport[0x1];
				7196	u8 reserved_at_41[0xf];
				7197	u8 vport_number[0x10];
				7198
				7199	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7200
				7201	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7202	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7203
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7204	u8 reserved_at_a0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7205
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	7206	struct mlx5_ifc_flow_table_context_bits flow_table_context;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7207	};
				7208
				7209	struct mlx5_ifc_create_flow_group_out_bits {
				7210	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7211	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7212
				7213	u8 syndrome[0x20];
				7214
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7215	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7216	u8 group_id[0x18];
				7217
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7218	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7219	};
				7220
				7221	enum {
Ariel Levkovich	71c6e86	2018-05-13 14:33:34 +0300	[diff] [blame]	7222	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
				7223	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
				7224	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
				7225	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7226	};
				7227
				7228	struct mlx5_ifc_create_flow_group_in_bits {
				7229	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7230	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7231
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7232	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7233	u8 op_mod[0x10];
				7234
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7235	u8 other_vport[0x1];
				7236	u8 reserved_at_41[0xf];
				7237	u8 vport_number[0x10];
				7238
				7239	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7240
				7241	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7242	u8 reserved_at_88[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7243
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7244	u8 reserved_at_a0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7245	u8 table_id[0x18];
				7246
Shahar Klein	3e99df8	2018-03-18 09:02:06 +0200	[diff] [blame]	7247	u8 source_eswitch_owner_vhca_id_valid[0x1];
				7248
				7249	u8 reserved_at_c1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7250
				7251	u8 start_flow_index[0x20];
				7252
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7253	u8 reserved_at_100[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7254
				7255	u8 end_flow_index[0x20];
				7256
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7257	u8 reserved_at_140[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7258
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7259	u8 reserved_at_1e0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7260	u8 match_criteria_enable[0x8];
				7261
				7262	struct mlx5_ifc_fte_match_param_bits match_criteria;
				7263
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7264	u8 reserved_at_1200[0xe00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7265	};
				7266
				7267	struct mlx5_ifc_create_eq_out_bits {
				7268	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7269	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7270
				7271	u8 syndrome[0x20];
				7272
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7273	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7274	u8 eq_number[0x8];
				7275
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7276	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7277	};
				7278
				7279	struct mlx5_ifc_create_eq_in_bits {
				7280	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7281	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7282
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7283	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7284	u8 op_mod[0x10];
				7285
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7286	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7287
				7288	struct mlx5_ifc_eqc_bits eq_context_entry;
				7289
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7290	u8 reserved_at_280[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7291
				7292	u8 event_bitmask[0x40];
				7293
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7294	u8 reserved_at_300[0x580];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7295
				7296	u8 pas[0][0x40];
				7297	};
				7298
				7299	struct mlx5_ifc_create_dct_out_bits {
				7300	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7301	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7302
				7303	u8 syndrome[0x20];
				7304
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7305	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7306	u8 dctn[0x18];
				7307
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7308	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7309	};
				7310
				7311	struct mlx5_ifc_create_dct_in_bits {
				7312	u8 opcode[0x10];
Yishai Hadas	774ea6e	2018-09-20 21:35:25 +0300	[diff] [blame]	7313	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7314
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7315	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7316	u8 op_mod[0x10];
				7317
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7318	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7319
				7320	struct mlx5_ifc_dctc_bits dct_context_entry;
				7321
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7322	u8 reserved_at_280[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7323	};
				7324
				7325	struct mlx5_ifc_create_cq_out_bits {
				7326	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7327	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7328
				7329	u8 syndrome[0x20];
				7330
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7331	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7332	u8 cqn[0x18];
				7333
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7334	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7335	};
				7336
				7337	struct mlx5_ifc_create_cq_in_bits {
				7338	u8 opcode[0x10];
Yishai Hadas	9ba481e2eb	2018-09-20 21:35:20 +0300	[diff] [blame]	7339	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7340
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7341	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7342	u8 op_mod[0x10];
				7343
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7344	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7345
				7346	struct mlx5_ifc_cqc_bits cq_context;
				7347
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7348	u8 reserved_at_280[0x60];
				7349
				7350	u8 cq_umem_valid[0x1];
				7351	u8 reserved_at_2e1[0x59f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7352
				7353	u8 pas[0][0x40];
				7354	};
				7355
				7356	struct mlx5_ifc_config_int_moderation_out_bits {
				7357	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7358	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7359
				7360	u8 syndrome[0x20];
				7361
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7362	u8 reserved_at_40[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7363	u8 min_delay[0xc];
				7364	u8 int_vector[0x10];
				7365
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7366	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7367	};
				7368
				7369	enum {
				7370	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
				7371	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
				7372	};
				7373
				7374	struct mlx5_ifc_config_int_moderation_in_bits {
				7375	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7376	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7377
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7378	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7379	u8 op_mod[0x10];
				7380
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7381	u8 reserved_at_40[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7382	u8 min_delay[0xc];
				7383	u8 int_vector[0x10];
				7384
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7385	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7386	};
				7387
				7388	struct mlx5_ifc_attach_to_mcg_out_bits {
				7389	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7390	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7391
				7392	u8 syndrome[0x20];
				7393
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7394	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7395	};
				7396
				7397	struct mlx5_ifc_attach_to_mcg_in_bits {
				7398	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7399	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7400
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7401	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7402	u8 op_mod[0x10];
				7403
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7404	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7405	u8 qpn[0x18];
				7406
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7407	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7408
				7409	u8 multicast_gid[16][0x8];
				7410	};
				7411
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7412	struct mlx5_ifc_arm_xrq_out_bits {
				7413	u8 status[0x8];
				7414	u8 reserved_at_8[0x18];
				7415
				7416	u8 syndrome[0x20];
				7417
				7418	u8 reserved_at_40[0x40];
				7419	};
				7420
				7421	struct mlx5_ifc_arm_xrq_in_bits {
				7422	u8 opcode[0x10];
				7423	u8 reserved_at_10[0x10];
				7424
				7425	u8 reserved_at_20[0x10];
				7426	u8 op_mod[0x10];
				7427
				7428	u8 reserved_at_40[0x8];
				7429	u8 xrqn[0x18];
				7430
				7431	u8 reserved_at_60[0x10];
				7432	u8 lwm[0x10];
				7433	};
				7434
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7435	struct mlx5_ifc_arm_xrc_srq_out_bits {
				7436	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7437	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7438
				7439	u8 syndrome[0x20];
				7440
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7441	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7442	};
				7443
				7444	enum {
				7445	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
				7446	};
				7447
				7448	struct mlx5_ifc_arm_xrc_srq_in_bits {
				7449	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7450	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7451
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7452	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7453	u8 op_mod[0x10];
				7454
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7455	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7456	u8 xrc_srqn[0x18];
				7457
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7458	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7459	u8 lwm[0x10];
				7460	};
				7461
				7462	struct mlx5_ifc_arm_rq_out_bits {
				7463	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7464	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7465
				7466	u8 syndrome[0x20];
				7467
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7468	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7469	};
				7470
				7471	enum {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7472	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
				7473	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7474	};
				7475
				7476	struct mlx5_ifc_arm_rq_in_bits {
				7477	u8 opcode[0x10];
Yishai Hadas	a0d8c05	2018-09-20 21:35:24 +0300	[diff] [blame]	7478	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7479
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7480	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7481	u8 op_mod[0x10];
				7482
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7483	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7484	u8 srq_number[0x18];
				7485
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7486	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7487	u8 lwm[0x10];
				7488	};
				7489
				7490	struct mlx5_ifc_arm_dct_out_bits {
				7491	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7492	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7493
				7494	u8 syndrome[0x20];
				7495
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7496	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7497	};
				7498
				7499	struct mlx5_ifc_arm_dct_in_bits {
				7500	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7501	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7502
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7503	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7504	u8 op_mod[0x10];
				7505
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7506	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7507	u8 dct_number[0x18];
				7508
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7509	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7510	};
				7511
				7512	struct mlx5_ifc_alloc_xrcd_out_bits {
				7513	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7514	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7515
				7516	u8 syndrome[0x20];
				7517
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7518	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7519	u8 xrcd[0x18];
				7520
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7521	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7522	};
				7523
				7524	struct mlx5_ifc_alloc_xrcd_in_bits {
				7525	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7526	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7527
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7528	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7529	u8 op_mod[0x10];
				7530
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7531	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7532	};
				7533
				7534	struct mlx5_ifc_alloc_uar_out_bits {
				7535	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7536	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7537
				7538	u8 syndrome[0x20];
				7539
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7540	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7541	u8 uar[0x18];
				7542
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7543	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7544	};
				7545
				7546	struct mlx5_ifc_alloc_uar_in_bits {
				7547	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7548	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7549
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7550	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7551	u8 op_mod[0x10];
				7552
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7553	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7554	};
				7555
				7556	struct mlx5_ifc_alloc_transport_domain_out_bits {
				7557	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7558	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7559
				7560	u8 syndrome[0x20];
				7561
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7562	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7563	u8 transport_domain[0x18];
				7564
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7565	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7566	};
				7567
				7568	struct mlx5_ifc_alloc_transport_domain_in_bits {
				7569	u8 opcode[0x10];
Yishai Hadas	71bef2f	2018-12-19 16:28:10 +0200	[diff] [blame]	7570	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7571
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7572	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7573	u8 op_mod[0x10];
				7574
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7575	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7576	};
				7577
				7578	struct mlx5_ifc_alloc_q_counter_out_bits {
				7579	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7580	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7581
				7582	u8 syndrome[0x20];
				7583
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7584	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7585	u8 counter_set_id[0x8];
				7586
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7587	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7588	};
				7589
				7590	struct mlx5_ifc_alloc_q_counter_in_bits {
				7591	u8 opcode[0x10];
Leon Romanovsky	2acc795	2018-12-06 14:40:11 +0200	[diff] [blame]	7592	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7593
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7594	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7595	u8 op_mod[0x10];
				7596
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7597	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7598	};
				7599
				7600	struct mlx5_ifc_alloc_pd_out_bits {
				7601	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7602	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7603
				7604	u8 syndrome[0x20];
				7605
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7606	u8 reserved_at_40[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7607	u8 pd[0x18];
				7608
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7609	u8 reserved_at_60[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7610	};
				7611
				7612	struct mlx5_ifc_alloc_pd_in_bits {
				7613	u8 opcode[0x10];
Leon Romanovsky	bd37197	2018-09-20 21:35:26 +0300	[diff] [blame]	7614	u8 uid[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7615
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7616	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7617	u8 op_mod[0x10];
				7618
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7619	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7620	};
				7621
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	7622	struct mlx5_ifc_alloc_flow_counter_out_bits {
				7623	u8 status[0x8];
				7624	u8 reserved_at_8[0x18];
				7625
				7626	u8 syndrome[0x20];
				7627
Rabie Loulou	a8ffcc7	2017-07-09 13:39:30 +0300	[diff] [blame]	7628	u8 flow_counter_id[0x20];
Amir Vadai	9dc0b28	2016-05-13 12:55:39 +0000	[diff] [blame]	7629
				7630	u8 reserved_at_60[0x20];
				7631	};
				7632
				7633	struct mlx5_ifc_alloc_flow_counter_in_bits {
				7634	u8 opcode[0x10];
				7635	u8 reserved_at_10[0x10];
				7636
				7637	u8 reserved_at_20[0x10];
				7638	u8 op_mod[0x10];
				7639
				7640	u8 reserved_at_40[0x40];
				7641	};
				7642
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7643	struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
				7644	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7645	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7646
				7647	u8 syndrome[0x20];
				7648
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7649	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7650	};
				7651
				7652	struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
				7653	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7654	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7655
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7656	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7657	u8 op_mod[0x10];
				7658
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7659	u8 reserved_at_40[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7660
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7661	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7662	u8 vxlan_udp_port[0x10];
				7663	};
				7664
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7665	struct mlx5_ifc_set_pp_rate_limit_out_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7666	u8 status[0x8];
				7667	u8 reserved_at_8[0x18];
				7668
				7669	u8 syndrome[0x20];
				7670
				7671	u8 reserved_at_40[0x40];
				7672	};
				7673
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7674	struct mlx5_ifc_set_pp_rate_limit_in_bits {
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7675	u8 opcode[0x10];
				7676	u8 reserved_at_10[0x10];
				7677
				7678	u8 reserved_at_20[0x10];
				7679	u8 op_mod[0x10];
				7680
				7681	u8 reserved_at_40[0x10];
				7682	u8 rate_limit_index[0x10];
				7683
				7684	u8 reserved_at_60[0x20];
				7685
				7686	u8 rate_limit[0x20];
Eran Ben Elisha	37e92a9	2017-11-13 10:11:27 +0200	[diff] [blame]	7687
Bodong Wang	05d3ac9	2018-03-19 15:10:29 +0200	[diff] [blame]	7688	u8 burst_upper_bound[0x20];
				7689
				7690	u8 reserved_at_c0[0x10];
				7691	u8 typical_packet_size[0x10];
				7692
				7693	u8 reserved_at_e0[0x120];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7694	};
				7695
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7696	struct mlx5_ifc_access_register_out_bits {
				7697	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7698	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7699
				7700	u8 syndrome[0x20];
				7701
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7702	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7703
				7704	u8 register_data[0][0x20];
				7705	};
				7706
				7707	enum {
				7708	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
				7709	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
				7710	};
				7711
				7712	struct mlx5_ifc_access_register_in_bits {
				7713	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7714	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7715
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7716	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7717	u8 op_mod[0x10];
				7718
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7719	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7720	u8 register_id[0x10];
				7721
				7722	u8 argument[0x20];
				7723
				7724	u8 register_data[0][0x20];
				7725	};
				7726
				7727	struct mlx5_ifc_sltp_reg_bits {
				7728	u8 status[0x4];
				7729	u8 version[0x4];
				7730	u8 local_port[0x8];
				7731	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7732	u8 reserved_at_12[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7733	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7734	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7735
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7736	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7737
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7738	u8 reserved_at_40[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7739	u8 polarity[0x1];
				7740	u8 ob_tap0[0x8];
				7741	u8 ob_tap1[0x8];
				7742	u8 ob_tap2[0x8];
				7743
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7744	u8 reserved_at_60[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7745	u8 ob_preemp_mode[0x4];
				7746	u8 ob_reg[0x8];
				7747	u8 ob_bias[0x8];
				7748
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7749	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7750	};
				7751
				7752	struct mlx5_ifc_slrg_reg_bits {
				7753	u8 status[0x4];
				7754	u8 version[0x4];
				7755	u8 local_port[0x8];
				7756	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7757	u8 reserved_at_12[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7758	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7759	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7760
				7761	u8 time_to_link_up[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7762	u8 reserved_at_30[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7763	u8 grade_lane_speed[0x4];
				7764
				7765	u8 grade_version[0x8];
				7766	u8 grade[0x18];
				7767
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7768	u8 reserved_at_60[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7769	u8 height_grade_type[0x4];
				7770	u8 height_grade[0x18];
				7771
				7772	u8 height_dz[0x10];
				7773	u8 height_dv[0x10];
				7774
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7775	u8 reserved_at_a0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7776	u8 height_sigma[0x10];
				7777
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7778	u8 reserved_at_c0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7779
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7780	u8 reserved_at_e0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7781	u8 phase_grade_type[0x4];
				7782	u8 phase_grade[0x18];
				7783
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7784	u8 reserved_at_100[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7785	u8 phase_eo_pos[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7786	u8 reserved_at_110[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7787	u8 phase_eo_neg[0x8];
				7788
				7789	u8 ffe_set_tested[0x10];
				7790	u8 test_errors_per_lane[0x10];
				7791	};
				7792
				7793	struct mlx5_ifc_pvlc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7794	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7795	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7796	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7797
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7798	u8 reserved_at_20[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7799	u8 vl_hw_cap[0x4];
				7800
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7801	u8 reserved_at_40[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7802	u8 vl_admin[0x4];
				7803
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7804	u8 reserved_at_60[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7805	u8 vl_operational[0x4];
				7806	};
				7807
				7808	struct mlx5_ifc_pude_reg_bits {
				7809	u8 swid[0x8];
				7810	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7811	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7812	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7813	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7814	u8 oper_status[0x4];
				7815
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7816	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7817	};
				7818
				7819	struct mlx5_ifc_ptys_reg_bits {
Bodong Wang	e7e31ca	2016-09-07 19:07:58 +0300	[diff] [blame]	7820	u8 reserved_at_0[0x1];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7821	u8 an_disable_admin[0x1];
Bodong Wang	e7e31ca	2016-09-07 19:07:58 +0300	[diff] [blame]	7822	u8 an_disable_cap[0x1];
				7823	u8 reserved_at_3[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7824	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7825	u8 reserved_at_10[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7826	u8 proto_mask[0x3];
				7827
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	7828	u8 an_status[0x4];
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame^]	7829	u8 reserved_at_24[0x1c];
				7830
				7831	u8 ext_eth_proto_capability[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7832
				7833	u8 eth_proto_capability[0x20];
				7834
				7835	u8 ib_link_width_capability[0x10];
				7836	u8 ib_proto_capability[0x10];
				7837
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame^]	7838	u8 ext_eth_proto_admin[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7839
				7840	u8 eth_proto_admin[0x20];
				7841
				7842	u8 ib_link_width_admin[0x10];
				7843	u8 ib_proto_admin[0x10];
				7844
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame^]	7845	u8 ext_eth_proto_oper[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7846
				7847	u8 eth_proto_oper[0x20];
				7848
				7849	u8 ib_link_width_oper[0x10];
				7850	u8 ib_proto_oper[0x10];
				7851
Eran Ben Elisha	5b4793f	2017-02-13 14:00:59 +0200	[diff] [blame]	7852	u8 reserved_at_160[0x1c];
				7853	u8 connector_type[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7854
				7855	u8 eth_proto_lp_advertise[0x20];
				7856
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7857	u8 reserved_at_1a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7858	};
				7859
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	7860	struct mlx5_ifc_mlcr_reg_bits {
				7861	u8 reserved_at_0[0x8];
				7862	u8 local_port[0x8];
				7863	u8 reserved_at_10[0x20];
				7864
				7865	u8 beacon_duration[0x10];
				7866	u8 reserved_at_40[0x10];
				7867
				7868	u8 beacon_remain[0x10];
				7869	};
				7870
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7871	struct mlx5_ifc_ptas_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7872	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7873
				7874	u8 algorithm_options[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7875	u8 reserved_at_30[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7876	u8 repetitions_mode[0x4];
				7877	u8 num_of_repetitions[0x8];
				7878
				7879	u8 grade_version[0x8];
				7880	u8 height_grade_type[0x4];
				7881	u8 phase_grade_type[0x4];
				7882	u8 height_grade_weight[0x8];
				7883	u8 phase_grade_weight[0x8];
				7884
				7885	u8 gisim_measure_bits[0x10];
				7886	u8 adaptive_tap_measure_bits[0x10];
				7887
				7888	u8 ber_bath_high_error_threshold[0x10];
				7889	u8 ber_bath_mid_error_threshold[0x10];
				7890
				7891	u8 ber_bath_low_error_threshold[0x10];
				7892	u8 one_ratio_high_threshold[0x10];
				7893
				7894	u8 one_ratio_high_mid_threshold[0x10];
				7895	u8 one_ratio_low_mid_threshold[0x10];
				7896
				7897	u8 one_ratio_low_threshold[0x10];
				7898	u8 ndeo_error_threshold[0x10];
				7899
				7900	u8 mixer_offset_step_size[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7901	u8 reserved_at_110[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7902	u8 mix90_phase_for_voltage_bath[0x8];
				7903
				7904	u8 mixer_offset_start[0x10];
				7905	u8 mixer_offset_end[0x10];
				7906
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7907	u8 reserved_at_140[0x15];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7908	u8 ber_test_time[0xb];
				7909	};
				7910
				7911	struct mlx5_ifc_pspa_reg_bits {
				7912	u8 swid[0x8];
				7913	u8 local_port[0x8];
				7914	u8 sub_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7915	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7916
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7917	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7918	};
				7919
				7920	struct mlx5_ifc_pqdr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7921	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7922	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7923	u8 reserved_at_10[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7924	u8 prio[0x3];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7925	u8 reserved_at_18[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7926	u8 mode[0x2];
				7927
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7928	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7929
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7930	u8 reserved_at_40[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7931	u8 min_threshold[0x10];
				7932
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7933	u8 reserved_at_60[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7934	u8 max_threshold[0x10];
				7935
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7936	u8 reserved_at_80[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7937	u8 mark_probability_denominator[0x10];
				7938
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7939	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7940	};
				7941
				7942	struct mlx5_ifc_ppsc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7943	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7944	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7945	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7946
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7947	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7948
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7949	u8 reserved_at_80[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7950	u8 wrps_admin[0x4];
				7951
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7952	u8 reserved_at_a0[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7953	u8 wrps_status[0x4];
				7954
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7955	u8 reserved_at_c0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7956	u8 up_threshold[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7957	u8 reserved_at_d0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7958	u8 down_threshold[0x8];
				7959
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7960	u8 reserved_at_e0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7961
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7962	u8 reserved_at_100[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7963	u8 srps_admin[0x4];
				7964
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7965	u8 reserved_at_120[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7966	u8 srps_status[0x4];
				7967
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7968	u8 reserved_at_140[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7969	};
				7970
				7971	struct mlx5_ifc_pplr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7972	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7973	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7974	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7975
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7976	u8 reserved_at_20[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7977	u8 lb_cap[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7978	u8 reserved_at_30[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7979	u8 lb_en[0x8];
				7980	};
				7981
				7982	struct mlx5_ifc_pplm_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	7983	u8 reserved_at_0[0x8];
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	7984	u8 local_port[0x8];
				7985	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7986
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	7987	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7988
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	7989	u8 port_profile_mode[0x8];
				7990	u8 static_port_profile[0x8];
				7991	u8 active_port_profile[0x8];
				7992	u8 reserved_at_58[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7993
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	7994	u8 retransmission_active[0x8];
				7995	u8 fec_mode_active[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	7996
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	7997	u8 rs_fec_correction_bypass_cap[0x4];
				7998	u8 reserved_at_84[0x8];
				7999	u8 fec_override_cap_56g[0x4];
				8000	u8 fec_override_cap_100g[0x4];
				8001	u8 fec_override_cap_50g[0x4];
				8002	u8 fec_override_cap_25g[0x4];
				8003	u8 fec_override_cap_10g_40g[0x4];
				8004
				8005	u8 rs_fec_correction_bypass_admin[0x4];
				8006	u8 reserved_at_a4[0x8];
				8007	u8 fec_override_admin_56g[0x4];
				8008	u8 fec_override_admin_100g[0x4];
				8009	u8 fec_override_admin_50g[0x4];
				8010	u8 fec_override_admin_25g[0x4];
				8011	u8 fec_override_admin_10g_40g[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8012	};
				8013
				8014	struct mlx5_ifc_ppcnt_reg_bits {
				8015	u8 swid[0x8];
				8016	u8 local_port[0x8];
				8017	u8 pnat[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8018	u8 reserved_at_12[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8019	u8 grp[0x6];
				8020
				8021	u8 clr[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8022	u8 reserved_at_21[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8023	u8 prio_tc[0x3];
				8024
				8025	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
				8026	};
				8027
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	8028	struct mlx5_ifc_mpcnt_reg_bits {
				8029	u8 reserved_at_0[0x8];
				8030	u8 pcie_index[0x8];
				8031	u8 reserved_at_10[0xa];
				8032	u8 grp[0x6];
				8033
				8034	u8 clr[0x1];
				8035	u8 reserved_at_21[0x1f];
				8036
				8037	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
				8038	};
				8039
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8040	struct mlx5_ifc_ppad_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8041	u8 reserved_at_0[0x3];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8042	u8 single_mac[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8043	u8 reserved_at_4[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8044	u8 local_port[0x8];
				8045	u8 mac_47_32[0x10];
				8046
				8047	u8 mac_31_0[0x20];
				8048
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8049	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8050	};
				8051
				8052	struct mlx5_ifc_pmtu_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8053	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8054	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8055	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8056
				8057	u8 max_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8058	u8 reserved_at_30[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8059
				8060	u8 admin_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8061	u8 reserved_at_50[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8062
				8063	u8 oper_mtu[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8064	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8065	};
				8066
				8067	struct mlx5_ifc_pmpr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8068	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8069	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8070	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8071
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8072	u8 reserved_at_20[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8073	u8 attenuation_5g[0x8];
				8074
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8075	u8 reserved_at_40[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8076	u8 attenuation_7g[0x8];
				8077
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8078	u8 reserved_at_60[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8079	u8 attenuation_12g[0x8];
				8080	};
				8081
				8082	struct mlx5_ifc_pmpe_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8083	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8084	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8085	u8 reserved_at_10[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8086	u8 module_status[0x4];
				8087
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8088	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8089	};
				8090
				8091	struct mlx5_ifc_pmpc_reg_bits {
				8092	u8 module_state_updated[32][0x8];
				8093	};
				8094
				8095	struct mlx5_ifc_pmlpn_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8096	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8097	u8 mlpn_status[0x4];
				8098	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8099	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8100
				8101	u8 e[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8102	u8 reserved_at_21[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8103	};
				8104
				8105	struct mlx5_ifc_pmlp_reg_bits {
				8106	u8 rxtx[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8107	u8 reserved_at_1[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8108	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8109	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8110	u8 width[0x8];
				8111
				8112	u8 lane0_module_mapping[0x20];
				8113
				8114	u8 lane1_module_mapping[0x20];
				8115
				8116	u8 lane2_module_mapping[0x20];
				8117
				8118	u8 lane3_module_mapping[0x20];
				8119
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8120	u8 reserved_at_a0[0x160];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8121	};
				8122
				8123	struct mlx5_ifc_pmaos_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8124	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8125	u8 module[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8126	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8127	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8128	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8129	u8 oper_status[0x4];
				8130
				8131	u8 ase[0x1];
				8132	u8 ee[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8133	u8 reserved_at_22[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8134	u8 e[0x2];
				8135
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8136	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8137	};
				8138
				8139	struct mlx5_ifc_plpc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8140	u8 reserved_at_0[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8141	u8 profile_id[0xc];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8142	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8143	u8 proto_mask[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8144	u8 reserved_at_18[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8145
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8146	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8147	u8 lane_speed[0x10];
				8148
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8149	u8 reserved_at_40[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8150	u8 lpbf[0x1];
				8151	u8 fec_mode_policy[0x8];
				8152
				8153	u8 retransmission_capability[0x8];
				8154	u8 fec_mode_capability[0x18];
				8155
				8156	u8 retransmission_support_admin[0x8];
				8157	u8 fec_mode_support_admin[0x18];
				8158
				8159	u8 retransmission_request_admin[0x8];
				8160	u8 fec_mode_request_admin[0x18];
				8161
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8162	u8 reserved_at_c0[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8163	};
				8164
				8165	struct mlx5_ifc_plib_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8166	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8167	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8168	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8169	u8 ib_port[0x8];
				8170
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8171	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8172	};
				8173
				8174	struct mlx5_ifc_plbf_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8175	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8176	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8177	u8 reserved_at_10[0xd];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8178	u8 lbf_mode[0x3];
				8179
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8180	u8 reserved_at_20[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8181	};
				8182
				8183	struct mlx5_ifc_pipg_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8184	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8185	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8186	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8187
				8188	u8 dic[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8189	u8 reserved_at_21[0x19];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8190	u8 ipg[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8191	u8 reserved_at_3e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8192	};
				8193
				8194	struct mlx5_ifc_pifr_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8195	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8196	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8197	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8198
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8199	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8200
				8201	u8 port_filter[8][0x20];
				8202
				8203	u8 port_filter_update_en[8][0x20];
				8204	};
				8205
				8206	struct mlx5_ifc_pfcc_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8207	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8208	u8 local_port[0x8];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8209	u8 reserved_at_10[0xb];
				8210	u8 ppan_mask_n[0x1];
				8211	u8 minor_stall_mask[0x1];
				8212	u8 critical_stall_mask[0x1];
				8213	u8 reserved_at_1e[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8214
				8215	u8 ppan[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8216	u8 reserved_at_24[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8217	u8 prio_mask_tx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8218	u8 reserved_at_30[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8219	u8 prio_mask_rx[0x8];
				8220
				8221	u8 pptx[0x1];
				8222	u8 aptx[0x1];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8223	u8 pptx_mask_n[0x1];
				8224	u8 reserved_at_43[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8225	u8 pfctx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8226	u8 reserved_at_50[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8227
				8228	u8 pprx[0x1];
				8229	u8 aprx[0x1];
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8230	u8 pprx_mask_n[0x1];
				8231	u8 reserved_at_63[0x5];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8232	u8 pfcrx[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8233	u8 reserved_at_70[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8234
Inbar Karmy	2afa609	2017-11-20 18:06:20 +0200	[diff] [blame]	8235	u8 device_stall_minor_watermark[0x10];
				8236	u8 device_stall_critical_watermark[0x10];
				8237
				8238	u8 reserved_at_a0[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8239	};
				8240
				8241	struct mlx5_ifc_pelc_reg_bits {
				8242	u8 op[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8243	u8 reserved_at_4[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8244	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8245	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8246
				8247	u8 op_admin[0x8];
				8248	u8 op_capability[0x8];
				8249	u8 op_request[0x8];
				8250	u8 op_active[0x8];
				8251
				8252	u8 admin[0x40];
				8253
				8254	u8 capability[0x40];
				8255
				8256	u8 request[0x40];
				8257
				8258	u8 active[0x40];
				8259
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8260	u8 reserved_at_140[0x80];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8261	};
				8262
				8263	struct mlx5_ifc_peir_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8264	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8265	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8266	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8267
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8268	u8 reserved_at_20[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8269	u8 error_count[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8270	u8 reserved_at_30[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8271
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8272	u8 reserved_at_40[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8273	u8 lane[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8274	u8 reserved_at_50[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8275	u8 error_type[0x8];
				8276	};
				8277
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8278	struct mlx5_ifc_mpegc_reg_bits {
				8279	u8 reserved_at_0[0x30];
				8280	u8 field_select[0x10];
				8281
				8282	u8 tx_overflow_sense[0x1];
				8283	u8 mark_cqe[0x1];
				8284	u8 mark_cnp[0x1];
				8285	u8 reserved_at_43[0x1b];
				8286	u8 tx_lossy_overflow_oper[0x2];
				8287
				8288	u8 reserved_at_60[0x100];
				8289	};
				8290
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8291	struct mlx5_ifc_pcam_enhanced_features_bits {
Talat Batheesh	0af5107	2018-05-17 11:14:18 +0300	[diff] [blame]	8292	u8 reserved_at_0[0x6d];
				8293	u8 rx_icrc_encapsulated_counter[0x1];
Aya Levin	a0a8998	2019-02-12 22:55:44 -0800	[diff] [blame^]	8294	u8 reserved_at_6e[0x4];
				8295	u8 ptys_extended_ethernet[0x1];
				8296	u8 reserved_at_73[0x3];
Inbar Karmy	2fcb12d	2017-08-17 16:39:47 +0300	[diff] [blame]	8297	u8 pfcc_mask[0x1];
Shay Agroskin	67daf11	2018-09-30 09:58:08 +0300	[diff] [blame]	8298	u8 reserved_at_77[0x3];
				8299	u8 per_lane_error_counters[0x1];
Gal Pressman	2dba079	2017-06-18 14:56:45 +0300	[diff] [blame]	8300	u8 rx_buffer_fullness_counters[0x1];
Eran Ben Elisha	5b4793f	2017-02-13 14:00:59 +0200	[diff] [blame]	8301	u8 ptys_connector_type[0x1];
				8302	u8 reserved_at_7d[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8303	u8 ppcnt_discard_group[0x1];
				8304	u8 ppcnt_statistical_group[0x1];
				8305	};
				8306
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8307	struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
				8308	u8 port_access_reg_cap_mask_127_to_96[0x20];
				8309	u8 port_access_reg_cap_mask_95_to_64[0x20];
Shay Agroskin	4b5b9c7	2018-10-09 14:16:43 +0300	[diff] [blame]	8310
				8311	u8 port_access_reg_cap_mask_63_to_36[0x1c];
				8312	u8 pplm[0x1];
				8313	u8 port_access_reg_cap_mask_34_to_32[0x3];
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8314
				8315	u8 port_access_reg_cap_mask_31_to_13[0x13];
				8316	u8 pbmc[0x1];
				8317	u8 pptb[0x1];
Eyal Davidovich	75370eb	2018-10-07 15:18:37 +0300	[diff] [blame]	8318	u8 port_access_reg_cap_mask_10_to_09[0x2];
				8319	u8 ppcnt[0x1];
				8320	u8 port_access_reg_cap_mask_07_to_00[0x8];
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8321	};
				8322
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8323	struct mlx5_ifc_pcam_reg_bits {
				8324	u8 reserved_at_0[0x8];
				8325	u8 feature_group[0x8];
				8326	u8 reserved_at_10[0x8];
				8327	u8 access_reg_group[0x8];
				8328
				8329	u8 reserved_at_20[0x20];
				8330
				8331	union {
Huy Nguyen	df5f136	2018-02-28 14:16:47 -0600	[diff] [blame]	8332	struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8333	u8 reserved_at_0[0x80];
				8334	} port_access_reg_cap_mask;
				8335
				8336	u8 reserved_at_c0[0x80];
				8337
				8338	union {
				8339	struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
				8340	u8 reserved_at_0[0x80];
				8341	} feature_cap_mask;
				8342
				8343	u8 reserved_at_1c0[0xc0];
				8344	};
				8345
				8346	struct mlx5_ifc_mcam_enhanced_features_bits {
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8347	u8 reserved_at_0[0x74];
				8348	u8 mark_tx_action_cnp[0x1];
				8349	u8 mark_tx_action_cqe[0x1];
				8350	u8 dynamic_tx_overflow[0x1];
				8351	u8 reserved_at_77[0x4];
Gal Pressman	5405fa2	2017-06-15 18:29:23 +0300	[diff] [blame]	8352	u8 pcie_outbound_stalled[0x1];
Eran Ben Elisha	efae7f7	2017-05-12 02:47:02 +0300	[diff] [blame]	8353	u8 tx_overflow_buffer_pkt[0x1];
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8354	u8 mtpps_enh_out_per_adj[0x1];
				8355	u8 mtpps_fs[0x1];
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8356	u8 pcie_performance_group[0x1];
				8357	};
				8358
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8359	struct mlx5_ifc_mcam_access_reg_bits {
				8360	u8 reserved_at_0[0x1c];
				8361	u8 mcda[0x1];
				8362	u8 mcc[0x1];
				8363	u8 mcqi[0x1];
				8364	u8 reserved_at_1f[0x1];
				8365
Eran Ben Elisha	5e022dd	2018-07-16 18:35:31 -0700	[diff] [blame]	8366	u8 regs_95_to_87[0x9];
				8367	u8 mpegc[0x1];
				8368	u8 regs_85_to_68[0x12];
Feras Daoud	eff8ea8	2018-07-16 18:35:30 -0700	[diff] [blame]	8369	u8 tracer_registers[0x4];
				8370
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8371	u8 regs_63_to_32[0x20];
				8372	u8 regs_31_to_0[0x20];
				8373	};
				8374
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8375	struct mlx5_ifc_mcam_reg_bits {
				8376	u8 reserved_at_0[0x8];
				8377	u8 feature_group[0x8];
				8378	u8 reserved_at_10[0x8];
				8379	u8 access_reg_group[0x8];
				8380
				8381	u8 reserved_at_20[0x20];
				8382
				8383	union {
Or Gerlitz	0ab8774	2017-06-11 15:25:38 +0300	[diff] [blame]	8384	struct mlx5_ifc_mcam_access_reg_bits access_regs;
Gal Pressman	cfdcbcea	2016-12-08 15:52:00 +0200	[diff] [blame]	8385	u8 reserved_at_0[0x80];
				8386	} mng_access_reg_cap_mask;
				8387
				8388	u8 reserved_at_c0[0x80];
				8389
				8390	union {
				8391	struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
				8392	u8 reserved_at_0[0x80];
				8393	} mng_feature_cap_mask;
				8394
				8395	u8 reserved_at_1c0[0x80];
				8396	};
				8397
Huy Nguyen	c02762e	2017-07-18 16:03:17 -0500	[diff] [blame]	8398	struct mlx5_ifc_qcam_access_reg_cap_mask {
				8399	u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
				8400	u8 qpdpm[0x1];
				8401	u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
				8402	u8 qdpm[0x1];
				8403	u8 qpts[0x1];
				8404	u8 qcap[0x1];
				8405	u8 qcam_access_reg_cap_mask_0[0x1];
				8406	};
				8407
				8408	struct mlx5_ifc_qcam_qos_feature_cap_mask {
				8409	u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
				8410	u8 qpts_trust_both[0x1];
				8411	};
				8412
				8413	struct mlx5_ifc_qcam_reg_bits {
				8414	u8 reserved_at_0[0x8];
				8415	u8 feature_group[0x8];
				8416	u8 reserved_at_10[0x8];
				8417	u8 access_reg_group[0x8];
				8418	u8 reserved_at_20[0x20];
				8419
				8420	union {
				8421	struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
				8422	u8 reserved_at_0[0x80];
				8423	} qos_access_reg_cap_mask;
				8424
				8425	u8 reserved_at_c0[0x80];
				8426
				8427	union {
				8428	struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
				8429	u8 reserved_at_0[0x80];
				8430	} qos_feature_cap_mask;
				8431
				8432	u8 reserved_at_1c0[0x80];
				8433	};
				8434
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8435	struct mlx5_ifc_pcap_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8436	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8437	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8438	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8439
				8440	u8 port_capability_mask[4][0x20];
				8441	};
				8442
				8443	struct mlx5_ifc_paos_reg_bits {
				8444	u8 swid[0x8];
				8445	u8 local_port[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8446	u8 reserved_at_10[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8447	u8 admin_status[0x4];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8448	u8 reserved_at_18[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8449	u8 oper_status[0x4];
				8450
				8451	u8 ase[0x1];
				8452	u8 ee[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8453	u8 reserved_at_22[0x1c];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8454	u8 e[0x2];
				8455
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8456	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8457	};
				8458
				8459	struct mlx5_ifc_pamp_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8460	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8461	u8 opamp_group[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8462	u8 reserved_at_10[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8463	u8 opamp_group_type[0x4];
				8464
				8465	u8 start_index[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8466	u8 reserved_at_30[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8467	u8 num_of_indices[0xc];
				8468
				8469	u8 index_data[18][0x10];
				8470	};
				8471
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8472	struct mlx5_ifc_pcmr_reg_bits {
				8473	u8 reserved_at_0[0x8];
				8474	u8 local_port[0x8];
				8475	u8 reserved_at_10[0x2e];
				8476	u8 fcs_cap[0x1];
				8477	u8 reserved_at_3f[0x1f];
				8478	u8 fcs_chk[0x1];
				8479	u8 reserved_at_5f[0x1];
				8480	};
				8481
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8482	struct mlx5_ifc_lane_2_module_mapping_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8483	u8 reserved_at_0[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8484	u8 rx_lane[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8485	u8 reserved_at_8[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8486	u8 tx_lane[0x2];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8487	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8488	u8 module[0x8];
				8489	};
				8490
				8491	struct mlx5_ifc_bufferx_reg_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8492	u8 reserved_at_0[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8493	u8 lossy[0x1];
				8494	u8 epsb[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8495	u8 reserved_at_8[0xc];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8496	u8 size[0xc];
				8497
				8498	u8 xoff_threshold[0x10];
				8499	u8 xon_threshold[0x10];
				8500	};
				8501
				8502	struct mlx5_ifc_set_node_in_bits {
				8503	u8 node_description[64][0x8];
				8504	};
				8505
				8506	struct mlx5_ifc_register_power_settings_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8507	u8 reserved_at_0[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8508	u8 power_settings_level[0x8];
				8509
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8510	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8511	};
				8512
				8513	struct mlx5_ifc_register_host_endianness_bits {
				8514	u8 he[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8515	u8 reserved_at_1[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8516
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8517	u8 reserved_at_20[0x60];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8518	};
				8519
				8520	struct mlx5_ifc_umr_pointer_desc_argument_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8521	u8 reserved_at_0[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8522
				8523	u8 mkey[0x20];
				8524
				8525	u8 addressh_63_32[0x20];
				8526
				8527	u8 addressl_31_0[0x20];
				8528	};
				8529
				8530	struct mlx5_ifc_ud_adrs_vector_bits {
				8531	u8 dc_key[0x40];
				8532
				8533	u8 ext[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8534	u8 reserved_at_41[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8535	u8 destination_qp_dct[0x18];
				8536
				8537	u8 static_rate[0x4];
				8538	u8 sl_eth_prio[0x4];
				8539	u8 fl[0x1];
				8540	u8 mlid[0x7];
				8541	u8 rlid_udp_sport[0x10];
				8542
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8543	u8 reserved_at_80[0x20];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8544
				8545	u8 rmac_47_16[0x20];
				8546
				8547	u8 rmac_15_0[0x10];
				8548	u8 tclass[0x8];
				8549	u8 hop_limit[0x8];
				8550
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8551	u8 reserved_at_e0[0x1];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8552	u8 grh[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8553	u8 reserved_at_e2[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8554	u8 src_addr_index[0x8];
				8555	u8 flow_label[0x14];
				8556
				8557	u8 rgid_rip[16][0x8];
				8558	};
				8559
				8560	struct mlx5_ifc_pages_req_event_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8561	u8 reserved_at_0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8562	u8 function_id[0x10];
				8563
				8564	u8 num_pages[0x20];
				8565
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8566	u8 reserved_at_40[0xa0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8567	};
				8568
				8569	struct mlx5_ifc_eqe_bits {
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8570	u8 reserved_at_0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8571	u8 event_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8572	u8 reserved_at_10[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8573	u8 event_sub_type[0x8];
				8574
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8575	u8 reserved_at_20[0xe0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8576
				8577	union mlx5_ifc_event_auto_bits event_data;
				8578
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8579	u8 reserved_at_1e0[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8580	u8 signature[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8581	u8 reserved_at_1f8[0x7];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8582	u8 owner[0x1];
				8583	};
				8584
				8585	enum {
				8586	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
				8587	};
				8588
				8589	struct mlx5_ifc_cmd_queue_entry_bits {
				8590	u8 type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8591	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8592
				8593	u8 input_length[0x20];
				8594
				8595	u8 input_mailbox_pointer_63_32[0x20];
				8596
				8597	u8 input_mailbox_pointer_31_9[0x17];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8598	u8 reserved_at_77[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8599
				8600	u8 command_input_inline_data[16][0x8];
				8601
				8602	u8 command_output_inline_data[16][0x8];
				8603
				8604	u8 output_mailbox_pointer_63_32[0x20];
				8605
				8606	u8 output_mailbox_pointer_31_9[0x17];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8607	u8 reserved_at_1b7[0x9];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8608
				8609	u8 output_length[0x20];
				8610
				8611	u8 token[0x8];
				8612	u8 signature[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8613	u8 reserved_at_1f0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8614	u8 status[0x7];
				8615	u8 ownership[0x1];
				8616	};
				8617
				8618	struct mlx5_ifc_cmd_out_bits {
				8619	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8620	u8 reserved_at_8[0x18];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8621
				8622	u8 syndrome[0x20];
				8623
				8624	u8 command_output[0x20];
				8625	};
				8626
				8627	struct mlx5_ifc_cmd_in_bits {
				8628	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8629	u8 reserved_at_10[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8630
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8631	u8 reserved_at_20[0x10];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8632	u8 op_mod[0x10];
				8633
				8634	u8 command[0][0x20];
				8635	};
				8636
				8637	struct mlx5_ifc_cmd_if_box_bits {
				8638	u8 mailbox_data[512][0x8];
				8639
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8640	u8 reserved_at_1000[0x180];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8641
				8642	u8 next_pointer_63_32[0x20];
				8643
				8644	u8 next_pointer_31_10[0x16];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8645	u8 reserved_at_11b6[0xa];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8646
				8647	u8 block_number[0x20];
				8648
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8649	u8 reserved_at_11e0[0x8];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8650	u8 token[0x8];
				8651	u8 ctrl_signature[0x8];
				8652	u8 signature[0x8];
				8653	};
				8654
				8655	struct mlx5_ifc_mtt_bits {
				8656	u8 ptag_63_32[0x20];
				8657
				8658	u8 ptag_31_8[0x18];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8659	u8 reserved_at_38[0x6];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8660	u8 wr_en[0x1];
				8661	u8 rd_en[0x1];
				8662	};
				8663
Tariq Toukan	928cfe8	2016-02-22 18:17:29 +0200	[diff] [blame]	8664	struct mlx5_ifc_query_wol_rol_out_bits {
				8665	u8 status[0x8];
				8666	u8 reserved_at_8[0x18];
				8667
				8668	u8 syndrome[0x20];
				8669
				8670	u8 reserved_at_40[0x10];
				8671	u8 rol_mode[0x8];
				8672	u8 wol_mode[0x8];
				8673
				8674	u8 reserved_at_60[0x20];
				8675	};
				8676
				8677	struct mlx5_ifc_query_wol_rol_in_bits {
				8678	u8 opcode[0x10];
				8679	u8 reserved_at_10[0x10];
				8680
				8681	u8 reserved_at_20[0x10];
				8682	u8 op_mod[0x10];
				8683
				8684	u8 reserved_at_40[0x40];
				8685	};
				8686
				8687	struct mlx5_ifc_set_wol_rol_out_bits {
				8688	u8 status[0x8];
				8689	u8 reserved_at_8[0x18];
				8690
				8691	u8 syndrome[0x20];
				8692
				8693	u8 reserved_at_40[0x40];
				8694	};
				8695
				8696	struct mlx5_ifc_set_wol_rol_in_bits {
				8697	u8 opcode[0x10];
				8698	u8 reserved_at_10[0x10];
				8699
				8700	u8 reserved_at_20[0x10];
				8701	u8 op_mod[0x10];
				8702
				8703	u8 rol_mode_valid[0x1];
				8704	u8 wol_mode_valid[0x1];
				8705	u8 reserved_at_42[0xe];
				8706	u8 rol_mode[0x8];
				8707	u8 wol_mode[0x8];
				8708
				8709	u8 reserved_at_60[0x20];
				8710	};
				8711
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8712	enum {
				8713	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
				8714	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
				8715	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
				8716	};
				8717
				8718	enum {
				8719	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
				8720	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
				8721	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
				8722	};
				8723
				8724	enum {
				8725	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
				8726	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
				8727	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
				8728	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
				8729	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
				8730	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
				8731	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
				8732	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
				8733	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
				8734	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
				8735	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
				8736	};
				8737
				8738	struct mlx5_ifc_initial_seg_bits {
				8739	u8 fw_rev_minor[0x10];
				8740	u8 fw_rev_major[0x10];
				8741
				8742	u8 cmd_interface_rev[0x10];
				8743	u8 fw_rev_subminor[0x10];
				8744
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8745	u8 reserved_at_40[0x40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8746
				8747	u8 cmdq_phy_addr_63_32[0x20];
				8748
				8749	u8 cmdq_phy_addr_31_12[0x14];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8750	u8 reserved_at_b4[0x2];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8751	u8 nic_interface[0x2];
				8752	u8 log_cmdq_size[0x4];
				8753	u8 log_cmdq_stride[0x4];
				8754
				8755	u8 command_doorbell_vector[0x20];
				8756
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8757	u8 reserved_at_e0[0xf00];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8758
				8759	u8 initializing[0x1];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8760	u8 reserved_at_fe1[0x4];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8761	u8 nic_interface_supported[0x3];
Bodong Wang	591905b	2019-02-12 22:55:35 -0800	[diff] [blame]	8762	u8 embedded_cpu[0x1];
				8763	u8 reserved_at_fe9[0x17];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8764
				8765	struct mlx5_ifc_health_buffer_bits health_buffer;
				8766
				8767	u8 no_dram_nic_offset[0x20];
				8768
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8769	u8 reserved_at_1220[0x6e40];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8770
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8771	u8 reserved_at_8060[0x1f];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8772	u8 clear_int[0x1];
				8773
				8774	u8 health_syndrome[0x8];
				8775	u8 health_counter[0x18];
				8776
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8777	u8 reserved_at_80a0[0x17fc0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8778	};
				8779
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8780	struct mlx5_ifc_mtpps_reg_bits {
				8781	u8 reserved_at_0[0xc];
				8782	u8 cap_number_of_pps_pins[0x4];
				8783	u8 reserved_at_10[0x4];
				8784	u8 cap_max_num_of_pps_in_pins[0x4];
				8785	u8 reserved_at_18[0x4];
				8786	u8 cap_max_num_of_pps_out_pins[0x4];
				8787
				8788	u8 reserved_at_20[0x24];
				8789	u8 cap_pin_3_mode[0x4];
				8790	u8 reserved_at_48[0x4];
				8791	u8 cap_pin_2_mode[0x4];
				8792	u8 reserved_at_50[0x4];
				8793	u8 cap_pin_1_mode[0x4];
				8794	u8 reserved_at_58[0x4];
				8795	u8 cap_pin_0_mode[0x4];
				8796
				8797	u8 reserved_at_60[0x4];
				8798	u8 cap_pin_7_mode[0x4];
				8799	u8 reserved_at_68[0x4];
				8800	u8 cap_pin_6_mode[0x4];
				8801	u8 reserved_at_70[0x4];
				8802	u8 cap_pin_5_mode[0x4];
				8803	u8 reserved_at_78[0x4];
				8804	u8 cap_pin_4_mode[0x4];
				8805
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8806	u8 field_select[0x20];
				8807	u8 reserved_at_a0[0x60];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8808
				8809	u8 enable[0x1];
				8810	u8 reserved_at_101[0xb];
				8811	u8 pattern[0x4];
				8812	u8 reserved_at_110[0x4];
				8813	u8 pin_mode[0x4];
				8814	u8 pin[0x8];
				8815
				8816	u8 reserved_at_120[0x20];
				8817
				8818	u8 time_stamp[0x40];
				8819
				8820	u8 out_pulse_duration[0x10];
				8821	u8 out_periodic_adjustment[0x10];
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8822	u8 enhanced_out_periodic_adjustment[0x20];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8823
Eugenia Emantayev	fa36768	2017-05-25 16:09:34 +0300	[diff] [blame]	8824	u8 reserved_at_1c0[0x20];
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8825	};
				8826
				8827	struct mlx5_ifc_mtppse_reg_bits {
				8828	u8 reserved_at_0[0x18];
				8829	u8 pin[0x8];
				8830	u8 event_arm[0x1];
				8831	u8 reserved_at_21[0x1b];
				8832	u8 event_generation_mode[0x4];
				8833	u8 reserved_at_40[0x40];
				8834	};
				8835
Or Gerlitz	4717628	2017-04-18 13:35:39 +0300	[diff] [blame]	8836	struct mlx5_ifc_mcqi_cap_bits {
				8837	u8 supported_info_bitmask[0x20];
				8838
				8839	u8 component_size[0x20];
				8840
				8841	u8 max_component_size[0x20];
				8842
				8843	u8 log_mcda_word_size[0x4];
				8844	u8 reserved_at_64[0xc];
				8845	u8 mcda_max_write_size[0x10];
				8846
				8847	u8 rd_en[0x1];
				8848	u8 reserved_at_81[0x1];
				8849	u8 match_chip_id[0x1];
				8850	u8 match_psid[0x1];
				8851	u8 check_user_timestamp[0x1];
				8852	u8 match_base_guid_mac[0x1];
				8853	u8 reserved_at_86[0x1a];
				8854	};
				8855
				8856	struct mlx5_ifc_mcqi_reg_bits {
				8857	u8 read_pending_component[0x1];
				8858	u8 reserved_at_1[0xf];
				8859	u8 component_index[0x10];
				8860
				8861	u8 reserved_at_20[0x20];
				8862
				8863	u8 reserved_at_40[0x1b];
				8864	u8 info_type[0x5];
				8865
				8866	u8 info_size[0x20];
				8867
				8868	u8 offset[0x20];
				8869
				8870	u8 reserved_at_a0[0x10];
				8871	u8 data_size[0x10];
				8872
				8873	u8 data[0][0x20];
				8874	};
				8875
				8876	struct mlx5_ifc_mcc_reg_bits {
				8877	u8 reserved_at_0[0x4];
				8878	u8 time_elapsed_since_last_cmd[0xc];
				8879	u8 reserved_at_10[0x8];
				8880	u8 instruction[0x8];
				8881
				8882	u8 reserved_at_20[0x10];
				8883	u8 component_index[0x10];
				8884
				8885	u8 reserved_at_40[0x8];
				8886	u8 update_handle[0x18];
				8887
				8888	u8 handle_owner_type[0x4];
				8889	u8 handle_owner_host_id[0x4];
				8890	u8 reserved_at_68[0x1];
				8891	u8 control_progress[0x7];
				8892	u8 error_code[0x8];
				8893	u8 reserved_at_78[0x4];
				8894	u8 control_state[0x4];
				8895
				8896	u8 component_size[0x20];
				8897
				8898	u8 reserved_at_a0[0x60];
				8899	};
				8900
				8901	struct mlx5_ifc_mcda_reg_bits {
				8902	u8 reserved_at_0[0x8];
				8903	u8 update_handle[0x18];
				8904
				8905	u8 offset[0x20];
				8906
				8907	u8 reserved_at_40[0x10];
				8908	u8 size[0x10];
				8909
				8910	u8 reserved_at_60[0x20];
				8911
				8912	u8 data[0][0x20];
				8913	};
				8914
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8915	union mlx5_ifc_ports_control_registers_document_bits {
				8916	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
				8917	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
				8918	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
				8919	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
				8920	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
				8921	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
				8922	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
				8923	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
				8924	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
				8925	struct mlx5_ifc_pamp_reg_bits pamp_reg;
				8926	struct mlx5_ifc_paos_reg_bits paos_reg;
				8927	struct mlx5_ifc_pcap_reg_bits pcap_reg;
				8928	struct mlx5_ifc_peir_reg_bits peir_reg;
				8929	struct mlx5_ifc_pelc_reg_bits pelc_reg;
				8930	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
Meny Yossefi	1c64bf6	2016-02-18 18:15:00 +0200	[diff] [blame]	8931	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8932	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
				8933	struct mlx5_ifc_pifr_reg_bits pifr_reg;
				8934	struct mlx5_ifc_pipg_reg_bits pipg_reg;
				8935	struct mlx5_ifc_plbf_reg_bits plbf_reg;
				8936	struct mlx5_ifc_plib_reg_bits plib_reg;
				8937	struct mlx5_ifc_plpc_reg_bits plpc_reg;
				8938	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
				8939	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
				8940	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
				8941	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
				8942	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
				8943	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
				8944	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
				8945	struct mlx5_ifc_ppad_reg_bits ppad_reg;
				8946	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
Gal Pressman	8ed1a63	2016-11-17 13:46:01 +0200	[diff] [blame]	8947	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8948	struct mlx5_ifc_pplm_reg_bits pplm_reg;
				8949	struct mlx5_ifc_pplr_reg_bits pplr_reg;
				8950	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
				8951	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
				8952	struct mlx5_ifc_pspa_reg_bits pspa_reg;
				8953	struct mlx5_ifc_ptas_reg_bits ptas_reg;
				8954	struct mlx5_ifc_ptys_reg_bits ptys_reg;
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8955	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8956	struct mlx5_ifc_pude_reg_bits pude_reg;
				8957	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
				8958	struct mlx5_ifc_slrg_reg_bits slrg_reg;
				8959	struct mlx5_ifc_sltp_reg_bits sltp_reg;
Eugenia Emantayev	f9a1ef7	2016-10-10 16:05:53 +0300	[diff] [blame]	8960	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
				8961	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
Ilan Tayari	a9956d3	2017-04-18 13:10:41 +0300	[diff] [blame]	8962	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
Ilan Tayari	e29341f	2017-03-13 20:05:45 +0200	[diff] [blame]	8963	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
				8964	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
Or Gerlitz	4717628	2017-04-18 13:35:39 +0300	[diff] [blame]	8965	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
				8966	struct mlx5_ifc_mcc_reg_bits mcc_reg;
				8967	struct mlx5_ifc_mcda_reg_bits mcda_reg;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8968	u8 reserved_at_0[0x60e0];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8969	};
				8970
				8971	union mlx5_ifc_debug_enhancements_document_bits {
				8972	struct mlx5_ifc_health_buffer_bits health_buffer;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8973	u8 reserved_at_0[0x200];
Saeed Mahameed	e281682	2015-05-28 22:28:40 +0300	[diff] [blame]	8974	};
				8975
				8976	union mlx5_ifc_uplink_pci_interface_document_bits {
				8977	struct mlx5_ifc_initial_seg_bits initial_seg;
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8978	u8 reserved_at_0[0x20060];
Eli Cohen	b775516	2014-10-02 12:19:44 +0300	[diff] [blame]	8979	};
				8980
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	8981	struct mlx5_ifc_set_flow_table_root_out_bits {
				8982	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8983	u8 reserved_at_8[0x18];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	8984
				8985	u8 syndrome[0x20];
				8986
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8987	u8 reserved_at_40[0x40];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	8988	};
				8989
				8990	struct mlx5_ifc_set_flow_table_root_in_bits {
				8991	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8992	u8 reserved_at_10[0x10];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	8993
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	8994	u8 reserved_at_20[0x10];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	8995	u8 op_mod[0x10];
				8996
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	8997	u8 other_vport[0x1];
				8998	u8 reserved_at_41[0xf];
				8999	u8 vport_number[0x10];
				9000
				9001	u8 reserved_at_60[0x20];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9002
				9003	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9004	u8 reserved_at_88[0x18];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9005
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9006	u8 reserved_at_a0[0x8];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9007	u8 table_id[0x18];
				9008
Erez Shitrit	500a3d0	2017-04-13 06:36:51 +0300	[diff] [blame]	9009	u8 reserved_at_c0[0x8];
				9010	u8 underlay_qpn[0x18];
				9011	u8 reserved_at_e0[0x120];
Maor Gottlieb	2cc43b4	2016-01-11 10:25:59 +0200	[diff] [blame]	9012	};
				9013
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9014	enum {
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	9015	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
				9016	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9017	};
				9018
				9019	struct mlx5_ifc_modify_flow_table_out_bits {
				9020	u8 status[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9021	u8 reserved_at_8[0x18];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9022
				9023	u8 syndrome[0x20];
				9024
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9025	u8 reserved_at_40[0x40];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9026	};
				9027
				9028	struct mlx5_ifc_modify_flow_table_in_bits {
				9029	u8 opcode[0x10];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9030	u8 reserved_at_10[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9031
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9032	u8 reserved_at_20[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9033	u8 op_mod[0x10];
				9034
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9035	u8 other_vport[0x1];
				9036	u8 reserved_at_41[0xf];
				9037	u8 vport_number[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9038
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9039	u8 reserved_at_60[0x10];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9040	u8 modify_field_select[0x10];
				9041
				9042	u8 table_type[0x8];
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9043	u8 reserved_at_88[0x18];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9044
Matan Barak	b4ff3a3	2016-02-09 14:57:42 +0200	[diff] [blame]	9045	u8 reserved_at_a0[0x8];
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9046	u8 table_id[0x18];
				9047
Maor Gottlieb	0c90e9c	2017-03-12 11:35:23 +0200	[diff] [blame]	9048	struct mlx5_ifc_flow_table_context_bits flow_table_context;
Maor Gottlieb	34a40e6	2016-01-11 10:26:00 +0200	[diff] [blame]	9049	};
				9050
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	9051	struct mlx5_ifc_ets_tcn_config_reg_bits {
				9052	u8 g[0x1];
				9053	u8 b[0x1];
				9054	u8 r[0x1];
				9055	u8 reserved_at_3[0x9];
				9056	u8 group[0x4];
				9057	u8 reserved_at_10[0x9];
				9058	u8 bw_allocation[0x7];
				9059
				9060	u8 reserved_at_20[0xc];
				9061	u8 max_bw_units[0x4];
				9062	u8 reserved_at_30[0x8];
				9063	u8 max_bw_value[0x8];
				9064	};
				9065
				9066	struct mlx5_ifc_ets_global_config_reg_bits {
				9067	u8 reserved_at_0[0x2];
				9068	u8 r[0x1];
				9069	u8 reserved_at_3[0x1d];
				9070
				9071	u8 reserved_at_20[0xc];
				9072	u8 max_bw_units[0x4];
				9073	u8 reserved_at_30[0x8];
				9074	u8 max_bw_value[0x8];
				9075	};
				9076
				9077	struct mlx5_ifc_qetc_reg_bits {
				9078	u8 reserved_at_0[0x8];
				9079	u8 port_number[0x8];
				9080	u8 reserved_at_10[0x30];
				9081
				9082	struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
				9083	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
				9084	};
				9085
Huy Nguyen	415a64a	2017-07-18 16:08:46 -0500	[diff] [blame]	9086	struct mlx5_ifc_qpdpm_dscp_reg_bits {
				9087	u8 e[0x1];
				9088	u8 reserved_at_01[0x0b];
				9089	u8 prio[0x04];
				9090	};
				9091
				9092	struct mlx5_ifc_qpdpm_reg_bits {
				9093	u8 reserved_at_0[0x8];
				9094	u8 local_port[0x8];
				9095	u8 reserved_at_10[0x10];
				9096	struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
				9097	};
				9098
				9099	struct mlx5_ifc_qpts_reg_bits {
				9100	u8 reserved_at_0[0x8];
				9101	u8 local_port[0x8];
				9102	u8 reserved_at_10[0x2d];
				9103	u8 trust_state[0x3];
				9104	};
				9105
Huy Nguyen	50b4a3c	2018-03-02 15:47:01 -0600	[diff] [blame]	9106	struct mlx5_ifc_pptb_reg_bits {
				9107	u8 reserved_at_0[0x2];
				9108	u8 mm[0x2];
				9109	u8 reserved_at_4[0x4];
				9110	u8 local_port[0x8];
				9111	u8 reserved_at_10[0x6];
				9112	u8 cm[0x1];
				9113	u8 um[0x1];
				9114	u8 pm[0x8];
				9115
				9116	u8 prio_x_buff[0x20];
				9117
				9118	u8 pm_msb[0x8];
				9119	u8 reserved_at_48[0x10];
				9120	u8 ctrl_buff[0x4];
				9121	u8 untagged_buff[0x4];
				9122	};
				9123
				9124	struct mlx5_ifc_pbmc_reg_bits {
				9125	u8 reserved_at_0[0x8];
				9126	u8 local_port[0x8];
				9127	u8 reserved_at_10[0x10];
				9128
				9129	u8 xoff_timer_value[0x10];
				9130	u8 xoff_refresh[0x10];
				9131
				9132	u8 reserved_at_40[0x9];
				9133	u8 fullness_threshold[0x7];
				9134	u8 port_buffer_size[0x10];
				9135
				9136	struct mlx5_ifc_bufferx_reg_bits buffer[10];
				9137
				9138	u8 reserved_at_2e0[0x40];
				9139	};
				9140
Saeed Mahameed	4f3961e	2016-02-22 18:17:25 +0200	[diff] [blame]	9141	struct mlx5_ifc_qtct_reg_bits {
				9142	u8 reserved_at_0[0x8];
				9143	u8 port_number[0x8];
				9144	u8 reserved_at_10[0xd];
				9145	u8 prio[0x3];
				9146
				9147	u8 reserved_at_20[0x1d];
				9148	u8 tclass[0x3];
				9149	};
				9150
Saeed Mahameed	7d5e142	2016-04-11 23:10:22 +0300	[diff] [blame]	9151	struct mlx5_ifc_mcia_reg_bits {
				9152	u8 l[0x1];
				9153	u8 reserved_at_1[0x7];
				9154	u8 module[0x8];
				9155	u8 reserved_at_10[0x8];
				9156	u8 status[0x8];
				9157
				9158	u8 i2c_device_address[0x8];
				9159	u8 page_number[0x8];
				9160	u8 device_address[0x10];
				9161
				9162	u8 reserved_at_40[0x10];
				9163	u8 size[0x10];
				9164
				9165	u8 reserved_at_60[0x20];
				9166
				9167	u8 dword_0[0x20];
				9168	u8 dword_1[0x20];
				9169	u8 dword_2[0x20];
				9170	u8 dword_3[0x20];
				9171	u8 dword_4[0x20];
				9172	u8 dword_5[0x20];
				9173	u8 dword_6[0x20];
				9174	u8 dword_7[0x20];
				9175	u8 dword_8[0x20];
				9176	u8 dword_9[0x20];
				9177	u8 dword_10[0x20];
				9178	u8 dword_11[0x20];
				9179	};
				9180
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	9181	struct mlx5_ifc_dcbx_param_bits {
				9182	u8 dcbx_cee_cap[0x1];
				9183	u8 dcbx_ieee_cap[0x1];
				9184	u8 dcbx_standby_cap[0x1];
Gal Pressman	c74d90c	2018-11-07 20:31:37 +0200	[diff] [blame]	9185	u8 reserved_at_3[0x5];
Saeed Mahameed	7486216	2016-06-09 15:11:34 +0300	[diff] [blame]	9186	u8 port_number[0x8];
				9187	u8 reserved_at_10[0xa];
				9188	u8 max_application_table_size[6];
				9189	u8 reserved_at_20[0x15];
				9190	u8 version_oper[0x3];
				9191	u8 reserved_at_38[5];
				9192	u8 version_admin[0x3];
				9193	u8 willing_admin[0x1];
				9194	u8 reserved_at_41[0x3];
				9195	u8 pfc_cap_oper[0x4];
				9196	u8 reserved_at_48[0x4];
				9197	u8 pfc_cap_admin[0x4];
				9198	u8 reserved_at_50[0x4];
				9199	u8 num_of_tc_oper[0x4];
				9200	u8 reserved_at_58[0x4];
				9201	u8 num_of_tc_admin[0x4];
				9202	u8 remote_willing[0x1];
				9203	u8 reserved_at_61[3];
				9204	u8 remote_pfc_cap[4];
				9205	u8 reserved_at_68[0x14];
				9206	u8 remote_num_of_tc[0x4];
				9207	u8 reserved_at_80[0x18];
				9208	u8 error[0x8];
				9209	u8 reserved_at_a0[0x160];
				9210	};
Aviv Heller	84df61e	2016-05-10 13:47:50 +0300	[diff] [blame]	9211
				9212	struct mlx5_ifc_lagc_bits {
				9213	u8 reserved_at_0[0x1d];
				9214	u8 lag_state[0x3];
				9215
				9216	u8 reserved_at_20[0x14];
				9217	u8 tx_remap_affinity_2[0x4];
				9218	u8 reserved_at_38[0x4];
				9219	u8 tx_remap_affinity_1[0x4];
				9220	};
				9221
				9222	struct mlx5_ifc_create_lag_out_bits {
				9223	u8 status[0x8];
				9224	u8 reserved_at_8[0x18];
				9225
				9226	u8 syndrome[0x20];
				9227
				9228	u8 reserved_at_40[0x40];
				9229	};
				9230
				9231	struct mlx5_ifc_create_lag_in_bits {
				9232	u8 opcode[0x10];
				9233	u8 reserved_at_10[0x10];
				9234
				9235	u8 reserved_at_20[0x10];
				9236	u8 op_mod[0x10];
				9237
				9238	struct mlx5_ifc_lagc_bits ctx;
				9239	};
				9240
				9241	struct mlx5_ifc_modify_lag_out_bits {
				9242	u8 status[0x8];
				9243	u8 reserved_at_8[0x18];
				9244
				9245	u8 syndrome[0x20];
				9246
				9247	u8 reserved_at_40[0x40];
				9248	};
				9249
				9250	struct mlx5_ifc_modify_lag_in_bits {
				9251	u8 opcode[0x10];
				9252	u8 reserved_at_10[0x10];
				9253
				9254	u8 reserved_at_20[0x10];
				9255	u8 op_mod[0x10];
				9256
				9257	u8 reserved_at_40[0x20];
				9258	u8 field_select[0x20];
				9259
				9260	struct mlx5_ifc_lagc_bits ctx;
				9261	};
				9262
				9263	struct mlx5_ifc_query_lag_out_bits {
				9264	u8 status[0x8];
				9265	u8 reserved_at_8[0x18];
				9266
				9267	u8 syndrome[0x20];
				9268
				9269	u8 reserved_at_40[0x40];
				9270
				9271	struct mlx5_ifc_lagc_bits ctx;
				9272	};
				9273
				9274	struct mlx5_ifc_query_lag_in_bits {
				9275	u8 opcode[0x10];
				9276	u8 reserved_at_10[0x10];
				9277
				9278	u8 reserved_at_20[0x10];
				9279	u8 op_mod[0x10];
				9280
				9281	u8 reserved_at_40[0x40];
				9282	};
				9283
				9284	struct mlx5_ifc_destroy_lag_out_bits {
				9285	u8 status[0x8];
				9286	u8 reserved_at_8[0x18];
				9287
				9288	u8 syndrome[0x20];
				9289
				9290	u8 reserved_at_40[0x40];
				9291	};
				9292
				9293	struct mlx5_ifc_destroy_lag_in_bits {
				9294	u8 opcode[0x10];
				9295	u8 reserved_at_10[0x10];
				9296
				9297	u8 reserved_at_20[0x10];
				9298	u8 op_mod[0x10];
				9299
				9300	u8 reserved_at_40[0x40];
				9301	};
				9302
				9303	struct mlx5_ifc_create_vport_lag_out_bits {
				9304	u8 status[0x8];
				9305	u8 reserved_at_8[0x18];
				9306
				9307	u8 syndrome[0x20];
				9308
				9309	u8 reserved_at_40[0x40];
				9310	};
				9311
				9312	struct mlx5_ifc_create_vport_lag_in_bits {
				9313	u8 opcode[0x10];
				9314	u8 reserved_at_10[0x10];
				9315
				9316	u8 reserved_at_20[0x10];
				9317	u8 op_mod[0x10];
				9318
				9319	u8 reserved_at_40[0x40];
				9320	};
				9321
				9322	struct mlx5_ifc_destroy_vport_lag_out_bits {
				9323	u8 status[0x8];
				9324	u8 reserved_at_8[0x18];
				9325
				9326	u8 syndrome[0x20];
				9327
				9328	u8 reserved_at_40[0x40];
				9329	};
				9330
				9331	struct mlx5_ifc_destroy_vport_lag_in_bits {
				9332	u8 opcode[0x10];
				9333	u8 reserved_at_10[0x10];
				9334
				9335	u8 reserved_at_20[0x10];
				9336	u8 op_mod[0x10];
				9337
				9338	u8 reserved_at_40[0x40];
				9339	};
				9340
Ariel Levkovich	24da001	2018-04-05 18:53:27 +0300	[diff] [blame]	9341	struct mlx5_ifc_alloc_memic_in_bits {
				9342	u8 opcode[0x10];
				9343	u8 reserved_at_10[0x10];
				9344
				9345	u8 reserved_at_20[0x10];
				9346	u8 op_mod[0x10];
				9347
				9348	u8 reserved_at_30[0x20];
				9349
				9350	u8 reserved_at_40[0x18];
				9351	u8 log_memic_addr_alignment[0x8];
				9352
				9353	u8 range_start_addr[0x40];
				9354
				9355	u8 range_size[0x20];
				9356
				9357	u8 memic_size[0x20];
				9358	};
				9359
				9360	struct mlx5_ifc_alloc_memic_out_bits {
				9361	u8 status[0x8];
				9362	u8 reserved_at_8[0x18];
				9363
				9364	u8 syndrome[0x20];
				9365
				9366	u8 memic_start_addr[0x40];
				9367	};
				9368
				9369	struct mlx5_ifc_dealloc_memic_in_bits {
				9370	u8 opcode[0x10];
				9371	u8 reserved_at_10[0x10];
				9372
				9373	u8 reserved_at_20[0x10];
				9374	u8 op_mod[0x10];
				9375
				9376	u8 reserved_at_40[0x40];
				9377
				9378	u8 memic_start_addr[0x40];
				9379
				9380	u8 memic_size[0x20];
				9381
				9382	u8 reserved_at_e0[0x20];
				9383	};
				9384
				9385	struct mlx5_ifc_dealloc_memic_out_bits {
				9386	u8 status[0x8];
				9387	u8 reserved_at_8[0x18];
				9388
				9389	u8 syndrome[0x20];
				9390
				9391	u8 reserved_at_40[0x40];
				9392	};
				9393
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9394	struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
				9395	u8 opcode[0x10];
				9396	u8 uid[0x10];
				9397
				9398	u8 reserved_at_20[0x10];
				9399	u8 obj_type[0x10];
				9400
				9401	u8 obj_id[0x20];
				9402
				9403	u8 reserved_at_60[0x20];
				9404	};
				9405
				9406	struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
				9407	u8 status[0x8];
				9408	u8 reserved_at_8[0x18];
				9409
				9410	u8 syndrome[0x20];
				9411
				9412	u8 obj_id[0x20];
				9413
				9414	u8 reserved_at_60[0x20];
				9415	};
				9416
				9417	struct mlx5_ifc_umem_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9418	u8 reserved_at_0[0x80];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9419
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9420	u8 reserved_at_80[0x1b];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9421	u8 log_page_size[0x5];
				9422
				9423	u8 page_offset[0x20];
				9424
				9425	u8 num_of_mtt[0x40];
				9426
				9427	struct mlx5_ifc_mtt_bits mtt[0];
				9428	};
				9429
				9430	struct mlx5_ifc_uctx_bits {
Yishai Hadas	9d43faa	2018-11-26 08:28:32 +0200	[diff] [blame]	9431	u8 cap[0x20];
				9432
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9433	u8 reserved_at_20[0x160];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9434	};
				9435
				9436	struct mlx5_ifc_create_umem_in_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9437	u8 opcode[0x10];
				9438	u8 uid[0x10];
				9439
				9440	u8 reserved_at_20[0x10];
				9441	u8 op_mod[0x10];
				9442
				9443	u8 reserved_at_40[0x40];
				9444
				9445	struct mlx5_ifc_umem_bits umem;
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9446	};
				9447
				9448	struct mlx5_ifc_create_uctx_in_bits {
Yishai Hadas	6e3722b	2018-12-19 16:28:15 +0200	[diff] [blame]	9449	u8 opcode[0x10];
				9450	u8 reserved_at_10[0x10];
				9451
				9452	u8 reserved_at_20[0x10];
				9453	u8 op_mod[0x10];
				9454
				9455	u8 reserved_at_40[0x40];
				9456
				9457	struct mlx5_ifc_uctx_bits uctx;
				9458	};
				9459
				9460	struct mlx5_ifc_destroy_uctx_in_bits {
				9461	u8 opcode[0x10];
				9462	u8 reserved_at_10[0x10];
				9463
				9464	u8 reserved_at_20[0x10];
				9465	u8 op_mod[0x10];
				9466
				9467	u8 reserved_at_40[0x10];
				9468	u8 uid[0x10];
				9469
				9470	u8 reserved_at_60[0x20];
Yishai Hadas	38b7ca9	2018-03-08 14:36:27 +0200	[diff] [blame]	9471	};
				9472
Feras Daoud	eff8ea8	2018-07-16 18:35:30 -0700	[diff] [blame]	9473	struct mlx5_ifc_mtrc_string_db_param_bits {
				9474	u8 string_db_base_address[0x20];
				9475
				9476	u8 reserved_at_20[0x8];
				9477	u8 string_db_size[0x18];
				9478	};
				9479
				9480	struct mlx5_ifc_mtrc_cap_bits {
				9481	u8 trace_owner[0x1];
				9482	u8 trace_to_memory[0x1];
				9483	u8 reserved_at_2[0x4];
				9484	u8 trc_ver[0x2];
				9485	u8 reserved_at_8[0x14];
				9486	u8 num_string_db[0x4];
				9487
				9488	u8 first_string_trace[0x8];
				9489	u8 num_string_trace[0x8];
				9490	u8 reserved_at_30[0x28];
				9491
				9492	u8 log_max_trace_buffer_size[0x8];
				9493
				9494	u8 reserved_at_60[0x20];
				9495
				9496	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
				9497
				9498	u8 reserved_at_280[0x180];
				9499	};
				9500
				9501	struct mlx5_ifc_mtrc_conf_bits {
				9502	u8 reserved_at_0[0x1c];
				9503	u8 trace_mode[0x4];
				9504	u8 reserved_at_20[0x18];
				9505	u8 log_trace_buffer_size[0x8];
				9506	u8 trace_mkey[0x20];
				9507	u8 reserved_at_60[0x3a0];
				9508	};
				9509
				9510	struct mlx5_ifc_mtrc_stdb_bits {
				9511	u8 string_db_index[0x4];
				9512	u8 reserved_at_4[0x4];
				9513	u8 read_size[0x18];
				9514	u8 start_offset[0x20];
				9515	u8 string_db_data[0];
				9516	};
				9517
				9518	struct mlx5_ifc_mtrc_ctrl_bits {
				9519	u8 trace_status[0x2];
				9520	u8 reserved_at_2[0x2];
				9521	u8 arm_event[0x1];
				9522	u8 reserved_at_5[0xb];
				9523	u8 modify_field_select[0x10];
				9524	u8 reserved_at_20[0x2b];
				9525	u8 current_timestamp52_32[0x15];
				9526	u8 current_timestamp31_0[0x20];
				9527	u8 reserved_at_80[0x180];
				9528	};
				9529
Bodong Wang	c3a4e9f	2019-02-12 22:55:37 -0800	[diff] [blame]	9530	struct mlx5_ifc_host_params_context_bits {
				9531	u8 host_number[0x8];
				9532	u8 reserved_at_8[0x8];
				9533	u8 host_num_of_vfs[0x10];
				9534
				9535	u8 reserved_at_20[0x10];
				9536	u8 host_pci_bus[0x10];
				9537
				9538	u8 reserved_at_40[0x10];
				9539	u8 host_pci_device[0x10];
				9540
				9541	u8 reserved_at_60[0x10];
				9542	u8 host_pci_function[0x10];
				9543
				9544	u8 reserved_at_80[0x180];
				9545	};
				9546
				9547	struct mlx5_ifc_query_host_params_in_bits {
				9548	u8 opcode[0x10];
				9549	u8 reserved_at_10[0x10];
				9550
				9551	u8 reserved_at_20[0x10];
				9552	u8 op_mod[0x10];
				9553
				9554	u8 reserved_at_40[0x40];
				9555	};
				9556
				9557	struct mlx5_ifc_query_host_params_out_bits {
				9558	u8 status[0x8];
				9559	u8 reserved_at_8[0x18];
				9560
				9561	u8 syndrome[0x20];
				9562
				9563	u8 reserved_at_40[0x40];
				9564
				9565	struct mlx5_ifc_host_params_context_bits host_params_context;
				9566
				9567	u8 reserved_at_280[0x180];
				9568	};
				9569
Eli Cohen	d29b796	2014-10-02 12:19:43 +0300	[diff] [blame]	9570	#endif /* MLX5_IFC_H */