blob: b1cb2627548f6a93d58a05254f811bfb6a1930b8 [file] [log] [blame]
Dave Airlief453ba02008-11-07 14:05:41 -08001/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
Adam Jackson61e57a82010-03-29 21:43:18 +00005 * Copyright 2010 Red Hat, Inc.
Dave Airlief453ba02008-11-07 14:05:41 -08006 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Thierry Reding10a85122012-11-21 15:31:35 +010032#include <linux/hdmi.h>
Dave Airlief453ba02008-11-07 14:05:41 -080033#include <linux/i2c.h>
Adam Jackson47819ba2012-05-30 16:42:39 -040034#include <linux/module.h>
Lukas Wunner5cb8eaa22016-01-11 20:09:20 +010035#include <linux/vga_switcheroo.h>
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/drmP.h>
37#include <drm/drm_edid.h>
Laurent Pinchart93382032016-11-28 20:51:09 +020038#include <drm/drm_encoder.h>
Dave Airlie40d9b042014-10-20 16:29:33 +100039#include <drm/drm_displayid.h>
Shashank Sharma62c58af2017-03-13 16:54:02 +053040#include <drm/drm_scdc_helper.h>
Dave Airlief453ba02008-11-07 14:05:41 -080041
Takashi Iwai969218f2017-01-17 17:43:29 +010042#include "drm_crtc_internal.h"
43
Adam Jackson13931572010-08-03 14:38:19 -040044#define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
Dave Airlief453ba02008-11-07 14:05:41 -080047
Adam Jacksond1ff6402010-03-29 21:43:26 +000048#define EDID_EST_TIMINGS 16
49#define EDID_STD_TIMINGS 8
50#define EDID_DETAILED_TIMINGS 4
Dave Airlief453ba02008-11-07 14:05:41 -080051
52/*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59/* First detailed mode wrong, use largest 60Hz mode */
60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61/* Reported 135MHz pixel clock is too high, needs adjustment */
62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63/* Prefer the largest mode at 75 Hz */
64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65/* Detail timing is in cm not mm */
66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67/* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71/* Monitor forgot to set the first detailed is preferred bit. */
72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73/* use +hsync +vsync for detailed mode */
74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
Adam Jacksonbc42aab2012-05-23 16:26:54 -040075/* Force reduced-blanking timings for detailed modes */
76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
Rafał Miłecki49d45a312013-12-07 13:22:42 +010077/* Force 8bpc */
78#define EDID_QUIRK_FORCE_8BPC (1 << 8)
Mario Kleinerbc5b9642014-05-23 21:40:55 +020079/* Force 12bpc */
80#define EDID_QUIRK_FORCE_12BPC (1 << 9)
Mario Kleinere10aec62016-07-06 12:05:44 +020081/* Force 6bpc */
82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
Mario Kleinere345da82017-04-21 17:05:08 +020083/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
Dave Airlie66660d42017-10-16 05:08:09 +010085/* Non desktop display (i.e. HMD) */
86#define EDID_QUIRK_NON_DESKTOP (1 << 12)
Alex Deucher3c537882010-02-05 04:21:19 -050087
Adam Jackson13931572010-08-03 14:38:19 -040088struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94};
Dave Airlief453ba02008-11-07 14:05:41 -080095
Zhao Yakui5c612592009-06-22 13:17:10 +080096#define LEVEL_DMT 0
97#define LEVEL_GTF 1
Adam Jackson7a374352010-03-29 21:43:30 +000098#define LEVEL_GTF2 2
99#define LEVEL_CVT 3
Zhao Yakui5c612592009-06-22 13:17:10 +0800100
Jani Nikula23c4cfb2016-12-28 13:06:26 +0200101static const struct edid_quirk {
Ian Pilcherc51a3fd62012-04-22 11:40:26 -0500102 char vendor[4];
Dave Airlief453ba02008-11-07 14:05:41 -0800103 int product_id;
104 u32 quirks;
105} edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
Mario Kleinere10aec62016-07-06 12:05:44 +0200113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
Dave Airlief453ba02008-11-07 14:05:41 -0800116 /* Belinea 10 15 55 */
117 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
118 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
119
120 /* Envision Peripherals, Inc. EN-7100e */
121 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
Adam Jacksonba1163d2010-04-06 16:11:00 +0000122 /* Envision EN2028 */
123 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
Dave Airlief453ba02008-11-07 14:05:41 -0800124
125 /* Funai Electronics PM36B */
126 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
127 EDID_QUIRK_DETAILED_IN_CM },
128
Mario Kleinere345da82017-04-21 17:05:08 +0200129 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
130 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
131
Dave Airlief453ba02008-11-07 14:05:41 -0800132 /* LG Philips LCD LP154W01-A5 */
133 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
134 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
135
136 /* Philips 107p5 CRT */
137 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
138
139 /* Proview AY765C */
140 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
141
142 /* Samsung SyncMaster 205BW. Note: irony */
143 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
144 /* Samsung SyncMaster 22[5-6]BW */
145 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
146 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
Adam Jacksonbc42aab2012-05-23 16:26:54 -0400147
Mario Kleinerbc5b9642014-05-23 21:40:55 +0200148 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
149 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
150
Adam Jacksonbc42aab2012-05-23 16:26:54 -0400151 /* ViewSonic VA2026w */
152 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
Alex Deucher118bdbd2013-08-12 11:04:29 -0400153
154 /* Medion MD 30217 PG */
155 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
Rafał Miłecki49d45a312013-12-07 13:22:42 +0100156
157 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
158 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
Tomeu Vizoso36fc5792017-02-20 16:25:45 +0100159
160 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
161 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
Dave Airlieacb1d8e2017-10-16 05:26:19 +0100162
163 /* HTC Vive VR Headset */
164 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
Dave Airlief453ba02008-11-07 14:05:41 -0800165};
166
Thierry Redinga6b21832012-11-23 15:01:42 +0100167/*
168 * Autogenerated from the DMT spec.
169 * This table is copied from xfree86/modes/xf86EdidModes.c.
170 */
171static const struct drm_display_mode drm_dmt_modes[] = {
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300172 /* 0x01 - 640x350@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100173 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
174 736, 832, 0, 350, 382, 385, 445, 0,
175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300176 /* 0x02 - 640x400@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100177 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
178 736, 832, 0, 400, 401, 404, 445, 0,
179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300180 /* 0x03 - 720x400@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100181 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
182 828, 936, 0, 400, 401, 404, 446, 0,
183 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300184 /* 0x04 - 640x480@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100185 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
Ville Syrjäläfcf22d02015-04-02 17:02:09 +0300186 752, 800, 0, 480, 490, 492, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300188 /* 0x05 - 640x480@72Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100189 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
190 704, 832, 0, 480, 489, 492, 520, 0,
191 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300192 /* 0x06 - 640x480@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100193 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
194 720, 840, 0, 480, 481, 484, 500, 0,
195 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300196 /* 0x07 - 640x480@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100197 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
198 752, 832, 0, 480, 481, 484, 509, 0,
199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300200 /* 0x08 - 800x600@56Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
202 896, 1024, 0, 600, 601, 603, 625, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300204 /* 0x09 - 800x600@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100205 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
206 968, 1056, 0, 600, 601, 605, 628, 0,
207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300208 /* 0x0a - 800x600@72Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100209 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
210 976, 1040, 0, 600, 637, 643, 666, 0,
211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300212 /* 0x0b - 800x600@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100213 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
214 896, 1056, 0, 600, 601, 604, 625, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300216 /* 0x0c - 800x600@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100217 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
218 896, 1048, 0, 600, 601, 604, 631, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300220 /* 0x0d - 800x600@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100221 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
222 880, 960, 0, 600, 603, 607, 636, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300224 /* 0x0e - 848x480@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100225 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
226 976, 1088, 0, 480, 486, 494, 517, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300228 /* 0x0f - 1024x768@43Hz, interlace */
Thierry Redinga6b21832012-11-23 15:01:42 +0100229 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
Paul Parsons735b1002016-04-04 20:36:34 +0100230 1208, 1264, 0, 768, 768, 776, 817, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
Ville Syrjäläfcf22d02015-04-02 17:02:09 +0300232 DRM_MODE_FLAG_INTERLACE) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300233 /* 0x10 - 1024x768@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100234 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
235 1184, 1344, 0, 768, 771, 777, 806, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300237 /* 0x11 - 1024x768@70Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100238 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
239 1184, 1328, 0, 768, 771, 777, 806, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300241 /* 0x12 - 1024x768@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100242 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
243 1136, 1312, 0, 768, 769, 772, 800, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300245 /* 0x13 - 1024x768@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100246 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
247 1168, 1376, 0, 768, 769, 772, 808, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300249 /* 0x14 - 1024x768@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100250 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
251 1104, 1184, 0, 768, 771, 775, 813, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300253 /* 0x15 - 1152x864@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100254 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
255 1344, 1600, 0, 864, 865, 868, 900, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300257 /* 0x55 - 1280x720@60Hz */
258 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
259 1430, 1650, 0, 720, 725, 730, 750, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300261 /* 0x16 - 1280x768@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100262 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
263 1360, 1440, 0, 768, 771, 778, 790, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300265 /* 0x17 - 1280x768@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100266 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
267 1472, 1664, 0, 768, 771, 778, 798, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300269 /* 0x18 - 1280x768@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100270 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
271 1488, 1696, 0, 768, 771, 778, 805, 0,
Ville Syrjäläfcf22d02015-04-02 17:02:09 +0300272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300273 /* 0x19 - 1280x768@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100274 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
275 1496, 1712, 0, 768, 771, 778, 809, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300277 /* 0x1a - 1280x768@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100278 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
279 1360, 1440, 0, 768, 771, 778, 813, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300281 /* 0x1b - 1280x800@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100282 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
283 1360, 1440, 0, 800, 803, 809, 823, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300285 /* 0x1c - 1280x800@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100286 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
287 1480, 1680, 0, 800, 803, 809, 831, 0,
Ville Syrjäläfcf22d02015-04-02 17:02:09 +0300288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300289 /* 0x1d - 1280x800@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100290 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
291 1488, 1696, 0, 800, 803, 809, 838, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300293 /* 0x1e - 1280x800@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100294 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
295 1496, 1712, 0, 800, 803, 809, 843, 0,
296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300297 /* 0x1f - 1280x800@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100298 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
299 1360, 1440, 0, 800, 803, 809, 847, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300301 /* 0x20 - 1280x960@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100302 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
303 1488, 1800, 0, 960, 961, 964, 1000, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300305 /* 0x21 - 1280x960@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100306 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
307 1504, 1728, 0, 960, 961, 964, 1011, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300309 /* 0x22 - 1280x960@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100310 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
311 1360, 1440, 0, 960, 963, 967, 1017, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300313 /* 0x23 - 1280x1024@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100314 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
315 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300317 /* 0x24 - 1280x1024@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100318 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
319 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300321 /* 0x25 - 1280x1024@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100322 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
323 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300325 /* 0x26 - 1280x1024@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100326 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
327 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300329 /* 0x27 - 1360x768@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100330 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
331 1536, 1792, 0, 768, 771, 777, 795, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300333 /* 0x28 - 1360x768@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100334 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
335 1440, 1520, 0, 768, 771, 776, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300337 /* 0x51 - 1366x768@60Hz */
338 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
339 1579, 1792, 0, 768, 771, 774, 798, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x56 - 1366x768@60Hz */
342 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
343 1436, 1500, 0, 768, 769, 772, 800, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300345 /* 0x29 - 1400x1050@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100346 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
347 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300349 /* 0x2a - 1400x1050@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100350 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
351 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300353 /* 0x2b - 1400x1050@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100354 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
355 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300357 /* 0x2c - 1400x1050@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100358 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
359 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300361 /* 0x2d - 1400x1050@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100362 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
363 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300365 /* 0x2e - 1440x900@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100366 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
367 1520, 1600, 0, 900, 903, 909, 926, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300369 /* 0x2f - 1440x900@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100370 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
371 1672, 1904, 0, 900, 903, 909, 934, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300373 /* 0x30 - 1440x900@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100374 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
375 1688, 1936, 0, 900, 903, 909, 942, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300377 /* 0x31 - 1440x900@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100378 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
379 1696, 1952, 0, 900, 903, 909, 948, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300381 /* 0x32 - 1440x900@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100382 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
383 1520, 1600, 0, 900, 903, 909, 953, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300385 /* 0x53 - 1600x900@60Hz */
386 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
387 1704, 1800, 0, 900, 901, 904, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300389 /* 0x33 - 1600x1200@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
391 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300393 /* 0x34 - 1600x1200@65Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100394 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
395 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300397 /* 0x35 - 1600x1200@70Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100398 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
399 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300401 /* 0x36 - 1600x1200@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100402 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
403 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300405 /* 0x37 - 1600x1200@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100406 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
407 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300409 /* 0x38 - 1600x1200@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100410 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
411 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300413 /* 0x39 - 1680x1050@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100414 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
415 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300417 /* 0x3a - 1680x1050@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100418 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
419 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300421 /* 0x3b - 1680x1050@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100422 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
423 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300425 /* 0x3c - 1680x1050@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100426 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
427 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300429 /* 0x3d - 1680x1050@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100430 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
431 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300433 /* 0x3e - 1792x1344@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100434 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
435 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300437 /* 0x3f - 1792x1344@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100438 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
439 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300441 /* 0x40 - 1792x1344@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100442 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
443 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300445 /* 0x41 - 1856x1392@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100446 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
447 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300449 /* 0x42 - 1856x1392@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100450 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
Ville Syrjäläfcf22d02015-04-02 17:02:09 +0300451 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300453 /* 0x43 - 1856x1392@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100454 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
455 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300457 /* 0x52 - 1920x1080@60Hz */
458 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
459 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300461 /* 0x44 - 1920x1200@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100462 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
463 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300465 /* 0x45 - 1920x1200@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100466 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
467 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300469 /* 0x46 - 1920x1200@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100470 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
471 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300473 /* 0x47 - 1920x1200@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100474 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
475 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300477 /* 0x48 - 1920x1200@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100478 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
479 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300481 /* 0x49 - 1920x1440@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100482 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
483 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300485 /* 0x4a - 1920x1440@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100486 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
487 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300489 /* 0x4b - 1920x1440@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100490 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
491 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300493 /* 0x54 - 2048x1152@60Hz */
494 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
495 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300497 /* 0x4c - 2560x1600@60Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100498 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
499 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300501 /* 0x4d - 2560x1600@60Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100502 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
503 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300505 /* 0x4e - 2560x1600@75Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100506 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
507 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300509 /* 0x4f - 2560x1600@85Hz */
Thierry Redinga6b21832012-11-23 15:01:42 +0100510 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
511 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
Ville Syrjälä24b856b2015-04-02 17:02:10 +0300513 /* 0x50 - 2560x1600@120Hz RB */
Thierry Redinga6b21832012-11-23 15:01:42 +0100514 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
515 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Ville Syrjäläbfcd74d2015-04-02 17:02:11 +0300517 /* 0x57 - 4096x2160@60Hz RB */
518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
519 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
521 /* 0x58 - 4096x2160@59.94Hz RB */
522 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
523 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
Thierry Redinga6b21832012-11-23 15:01:42 +0100525};
526
Ville Syrjäläe7bfa5c2013-10-14 16:44:27 +0300527/*
528 * These more or less come from the DMT spec. The 720x400 modes are
529 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
530 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
531 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
532 * mode.
533 *
534 * The DMT modes have been fact-checked; the rest are mild guesses.
535 */
Thierry Redinga6b21832012-11-23 15:01:42 +0100536static const struct drm_display_mode edid_est_modes[] = {
537 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
538 968, 1056, 0, 600, 601, 605, 628, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
541 896, 1024, 0, 600, 601, 603, 625, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
543 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
544 720, 840, 0, 480, 481, 484, 500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
Paul Parsons87707cf2016-04-02 11:08:06 +0100547 704, 832, 0, 480, 489, 492, 520, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
550 768, 864, 0, 480, 483, 486, 525, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
Paul Parsons87707cf2016-04-02 11:08:06 +0100552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
Thierry Redinga6b21832012-11-23 15:01:42 +0100553 752, 800, 0, 480, 490, 492, 525, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
555 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
556 846, 900, 0, 400, 421, 423, 449, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
559 846, 900, 0, 400, 412, 414, 449, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
561 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
562 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
Paul Parsons87707cf2016-04-02 11:08:06 +0100564 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
Thierry Redinga6b21832012-11-23 15:01:42 +0100565 1136, 1312, 0, 768, 769, 772, 800, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
568 1184, 1328, 0, 768, 771, 777, 806, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
571 1184, 1344, 0, 768, 771, 777, 806, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
573 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
574 1208, 1264, 0, 768, 768, 776, 817, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
576 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
577 928, 1152, 0, 624, 625, 628, 667, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
579 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
580 896, 1056, 0, 600, 601, 604, 625, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
583 976, 1040, 0, 600, 637, 643, 666, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
585 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
586 1344, 1600, 0, 864, 865, 868, 900, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
588};
589
590struct minimode {
591 short w;
592 short h;
593 short r;
594 short rb;
595};
596
597static const struct minimode est3_modes[] = {
598 /* byte 6 */
599 { 640, 350, 85, 0 },
600 { 640, 400, 85, 0 },
601 { 720, 400, 85, 0 },
602 { 640, 480, 85, 0 },
603 { 848, 480, 60, 0 },
604 { 800, 600, 85, 0 },
605 { 1024, 768, 85, 0 },
606 { 1152, 864, 75, 0 },
607 /* byte 7 */
608 { 1280, 768, 60, 1 },
609 { 1280, 768, 60, 0 },
610 { 1280, 768, 75, 0 },
611 { 1280, 768, 85, 0 },
612 { 1280, 960, 60, 0 },
613 { 1280, 960, 85, 0 },
614 { 1280, 1024, 60, 0 },
615 { 1280, 1024, 85, 0 },
616 /* byte 8 */
617 { 1360, 768, 60, 0 },
618 { 1440, 900, 60, 1 },
619 { 1440, 900, 60, 0 },
620 { 1440, 900, 75, 0 },
621 { 1440, 900, 85, 0 },
622 { 1400, 1050, 60, 1 },
623 { 1400, 1050, 60, 0 },
624 { 1400, 1050, 75, 0 },
625 /* byte 9 */
626 { 1400, 1050, 85, 0 },
627 { 1680, 1050, 60, 1 },
628 { 1680, 1050, 60, 0 },
629 { 1680, 1050, 75, 0 },
630 { 1680, 1050, 85, 0 },
631 { 1600, 1200, 60, 0 },
632 { 1600, 1200, 65, 0 },
633 { 1600, 1200, 70, 0 },
634 /* byte 10 */
635 { 1600, 1200, 75, 0 },
636 { 1600, 1200, 85, 0 },
637 { 1792, 1344, 60, 0 },
Ville Syrjäläc068b322013-10-14 16:44:25 +0300638 { 1792, 1344, 75, 0 },
Thierry Redinga6b21832012-11-23 15:01:42 +0100639 { 1856, 1392, 60, 0 },
640 { 1856, 1392, 75, 0 },
641 { 1920, 1200, 60, 1 },
642 { 1920, 1200, 60, 0 },
643 /* byte 11 */
644 { 1920, 1200, 75, 0 },
645 { 1920, 1200, 85, 0 },
646 { 1920, 1440, 60, 0 },
647 { 1920, 1440, 75, 0 },
648};
649
650static const struct minimode extra_modes[] = {
651 { 1024, 576, 60, 0 },
652 { 1366, 768, 60, 0 },
653 { 1600, 900, 60, 0 },
654 { 1680, 945, 60, 0 },
655 { 1920, 1080, 60, 0 },
656 { 2048, 1152, 60, 0 },
657 { 2048, 1536, 60, 0 },
658};
659
660/*
661 * Probably taken from CEA-861 spec.
662 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
Jani Nikulad9278b42016-01-08 13:21:51 +0200663 *
664 * Index using the VIC.
Thierry Redinga6b21832012-11-23 15:01:42 +0100665 */
666static const struct drm_display_mode edid_cea_modes[] = {
Jani Nikulad9278b42016-01-08 13:21:51 +0200667 /* 0 - dummy, VICs start at 1 */
668 { },
Thierry Redinga6b21832012-11-23 15:01:42 +0100669 /* 1 - 640x480@60Hz */
670 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
671 752, 800, 0, 480, 490, 492, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100674 /* 2 - 720x480@60Hz */
675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
676 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100679 /* 3 - 720x480@60Hz */
680 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
681 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100684 /* 4 - 1280x720@60Hz */
685 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
686 1430, 1650, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100689 /* 5 - 1920x1080i@60Hz */
690 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
691 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300693 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700695 /* 6 - 720(1440)x480i@60Hz */
696 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
697 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300699 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700701 /* 7 - 720(1440)x480i@60Hz */
702 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
703 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300705 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700707 /* 8 - 720(1440)x240@60Hz */
708 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
709 801, 858, 0, 240, 244, 247, 262, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300711 DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530712 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700713 /* 9 - 720(1440)x240@60Hz */
714 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
715 801, 858, 0, 240, 244, 247, 262, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300717 DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100719 /* 10 - 2880x480i@60Hz */
720 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
721 3204, 3432, 0, 480, 488, 494, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300723 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100725 /* 11 - 2880x480i@60Hz */
726 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
727 3204, 3432, 0, 480, 488, 494, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300729 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100731 /* 12 - 2880x240@60Hz */
732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
733 3204, 3432, 0, 240, 244, 247, 262, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100736 /* 13 - 2880x240@60Hz */
737 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
738 3204, 3432, 0, 240, 244, 247, 262, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100741 /* 14 - 1440x480@60Hz */
742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
743 1596, 1716, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100746 /* 15 - 1440x480@60Hz */
747 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
748 1596, 1716, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100751 /* 16 - 1920x1080@60Hz */
752 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
753 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100756 /* 17 - 720x576@50Hz */
757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
758 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100761 /* 18 - 720x576@50Hz */
762 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
763 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100766 /* 19 - 1280x720@50Hz */
767 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
768 1760, 1980, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100771 /* 20 - 1920x1080i@50Hz */
772 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
773 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300775 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700777 /* 21 - 720(1440)x576i@50Hz */
778 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
779 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300781 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700783 /* 22 - 720(1440)x576i@50Hz */
784 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
785 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300787 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700789 /* 23 - 720(1440)x288@50Hz */
790 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
791 795, 864, 0, 288, 290, 293, 312, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300793 DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530794 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700795 /* 24 - 720(1440)x288@50Hz */
796 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
797 795, 864, 0, 288, 290, 293, 312, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300799 DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530800 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100801 /* 25 - 2880x576i@50Hz */
802 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
803 3180, 3456, 0, 576, 580, 586, 625, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300805 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100807 /* 26 - 2880x576i@50Hz */
808 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
809 3180, 3456, 0, 576, 580, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300811 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100813 /* 27 - 2880x288@50Hz */
814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
815 3180, 3456, 0, 288, 290, 293, 312, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100818 /* 28 - 2880x288@50Hz */
819 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
820 3180, 3456, 0, 288, 290, 293, 312, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100823 /* 29 - 1440x576@50Hz */
824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
825 1592, 1728, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100828 /* 30 - 1440x576@50Hz */
829 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
830 1592, 1728, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100833 /* 31 - 1920x1080@50Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
835 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100838 /* 32 - 1920x1080@24Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
840 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530842 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100843 /* 33 - 1920x1080@25Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530847 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100848 /* 34 - 1920x1080@30Hz */
849 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
850 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530852 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100853 /* 35 - 2880x480@60Hz */
854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
855 3192, 3432, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530857 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100858 /* 36 - 2880x480@60Hz */
859 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
860 3192, 3432, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530862 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100863 /* 37 - 2880x576@50Hz */
864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
865 3184, 3456, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100868 /* 38 - 2880x576@50Hz */
869 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
870 3184, 3456, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530872 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100873 /* 39 - 1920x1080i@50Hz */
874 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
875 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300877 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100879 /* 40 - 1920x1080i@100Hz */
880 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
881 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300883 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100885 /* 41 - 1280x720@100Hz */
886 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
887 1760, 1980, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100890 /* 42 - 720x576@100Hz */
891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
892 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100895 /* 43 - 720x576@100Hz */
896 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
897 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530899 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700900 /* 44 - 720(1440)x576i@100Hz */
901 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
902 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Clint Taylor5a11f7f2014-09-26 09:55:24 -0700904 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530905 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700906 /* 45 - 720(1440)x576i@100Hz */
907 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
908 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100909 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Clint Taylor5a11f7f2014-09-26 09:55:24 -0700910 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530911 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100912 /* 46 - 1920x1080i@120Hz */
913 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
914 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300916 DRM_MODE_FLAG_INTERLACE),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100918 /* 47 - 1280x720@120Hz */
919 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
920 1430, 1650, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100923 /* 48 - 720x480@120Hz */
924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
925 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100928 /* 49 - 720x480@120Hz */
929 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
930 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530932 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700933 /* 50 - 720(1440)x480i@120Hz */
934 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
935 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300937 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530938 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700939 /* 51 - 720(1440)x480i@120Hz */
940 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
941 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300943 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530944 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100945 /* 52 - 720x576@200Hz */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100950 /* 53 - 720x576@200Hz */
951 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
952 796, 864, 0, 576, 581, 586, 625, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530954 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700955 /* 54 - 720(1440)x576i@200Hz */
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530960 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Clint Taylorfb01d282014-09-02 17:03:35 -0700961 /* 55 - 720(1440)x576i@200Hz */
962 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
963 795, 864, 0, 576, 580, 586, 625, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530966 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100967 /* 56 - 720x480@240Hz */
968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
969 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100972 /* 57 - 720x480@240Hz */
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530976 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Ville Syrjäläe5878032016-11-03 14:53:28 +0200977 /* 58 - 720(1440)x480i@240Hz */
Clint Taylorfb01d282014-09-02 17:03:35 -0700978 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
979 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300981 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530982 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
Ville Syrjäläe5878032016-11-03 14:53:28 +0200983 /* 59 - 720(1440)x480i@240Hz */
Clint Taylorfb01d282014-09-02 17:03:35 -0700984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
Thierry Redinga6b21832012-11-23 15:01:42 +0100986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530988 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100989 /* 60 - 1280x720@24Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
991 3080, 3300, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530993 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100994 /* 61 - 1280x720@25Hz */
995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
996 3740, 3960, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +0300997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +0530998 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +0100999 /* 62 - 1280x720@30Hz */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1001 3080, 3300, 0, 720, 725, 730, 750, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +03001002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +05301003 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +01001004 /* 63 - 1920x1080@120Hz */
1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1006 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +03001007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +05301008 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Thierry Redinga6b21832012-11-23 15:01:42 +01001009 /* 64 - 1920x1080@100Hz */
1010 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
Clint Taylor8f0e4902016-08-15 10:31:28 -07001011 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
Ville Syrjäläee7925b2013-04-24 19:07:17 +03001012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
Vandana Kannan985e5dc2013-12-19 15:34:07 +05301013 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
Shashank Sharma8ec6e072017-07-13 21:03:08 +05301014 /* 65 - 1280x720@24Hz */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1016 3080, 3300, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1019 /* 66 - 1280x720@25Hz */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1021 3740, 3960, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1024 /* 67 - 1280x720@30Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1026 3080, 3300, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 68 - 1280x720@50Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1031 1760, 1980, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 69 - 1280x720@60Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1036 1430, 1650, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 70 - 1280x720@100Hz */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1041 1760, 1980, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 71 - 1280x720@120Hz */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1046 1430, 1650, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 72 - 1920x1080@24Hz */
1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1051 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 73 - 1920x1080@25Hz */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1056 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 74 - 1920x1080@30Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1061 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 75 - 1920x1080@50Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1066 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 76 - 1920x1080@60Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 77 - 1920x1080@100Hz */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 78 - 1920x1080@120Hz */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1081 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 79 - 1680x720@24Hz */
1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1086 3080, 3300, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 80 - 1680x720@25Hz */
1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1091 2948, 3168, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 81 - 1680x720@30Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1096 2420, 2640, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 82 - 1680x720@50Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1101 1980, 2200, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 83 - 1680x720@60Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1106 1980, 2200, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 84 - 1680x720@100Hz */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1111 1780, 2000, 0, 720, 725, 730, 825, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 85 - 1680x720@120Hz */
1115 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1116 1780, 2000, 0, 720, 725, 730, 825, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 86 - 2560x1080@24Hz */
1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1121 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 87 - 2560x1080@25Hz */
1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1126 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 88 - 2560x1080@30Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1131 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 89 - 2560x1080@50Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1136 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 90 - 2560x1080@60Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1141 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 91 - 2560x1080@100Hz */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1146 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 92 - 2560x1080@120Hz */
1150 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1151 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 93 - 3840x2160p@24Hz 16:9 */
1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1156 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1159 /* 94 - 3840x2160p@25Hz 16:9 */
1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1161 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1164 /* 95 - 3840x2160p@30Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1166 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1169 /* 96 - 3840x2160p@50Hz 16:9 */
1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1171 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1174 /* 97 - 3840x2160p@60Hz 16:9 */
1175 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1176 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1179 /* 98 - 4096x2160p@24Hz 256:135 */
1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1181 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1184 /* 99 - 4096x2160p@25Hz 256:135 */
1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1186 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1189 /* 100 - 4096x2160p@30Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1191 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1194 /* 101 - 4096x2160p@50Hz 256:135 */
1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1196 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1199 /* 102 - 4096x2160p@60Hz 256:135 */
1200 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1201 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1204 /* 103 - 3840x2160p@24Hz 64:27 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 104 - 3840x2160p@25Hz 64:27 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 105 - 3840x2160p@30Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 106 - 3840x2160p@50Hz 64:27 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 107 - 3840x2160p@60Hz 64:27 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
Thierry Redinga6b21832012-11-23 15:01:42 +01001229};
1230
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01001231/*
Jani Nikulad9278b42016-01-08 13:21:51 +02001232 * HDMI 1.4 4k modes. Index using the VIC.
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01001233 */
1234static const struct drm_display_mode edid_4k_modes[] = {
Jani Nikulad9278b42016-01-08 13:21:51 +02001235 /* 0 - dummy, VICs start at 1 */
1236 { },
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01001237 /* 1 - 3840x2160@30Hz */
1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1239 3840, 4016, 4104, 4400, 0,
1240 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, },
1243 /* 2 - 3840x2160@25Hz */
1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1245 3840, 4896, 4984, 5280, 0,
1246 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .vrefresh = 25, },
1249 /* 3 - 3840x2160@24Hz */
1250 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1251 3840, 5116, 5204, 5500, 0,
1252 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 24, },
1255 /* 4 - 4096x2160@24Hz (SMPTE) */
1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1257 4096, 5116, 5204, 5500, 0,
1258 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .vrefresh = 24, },
1261};
1262
Adam Jackson61e57a82010-03-29 21:43:18 +00001263/*** DDC fetch and block validation ***/
Dave Airlief453ba02008-11-07 14:05:41 -08001264
Adam Jackson083ae052009-09-23 17:30:45 -04001265static const u8 edid_header[] = {
1266 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1267};
Dave Airlief453ba02008-11-07 14:05:41 -08001268
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001269/**
1270 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1271 * @raw_edid: pointer to raw base EDID block
1272 *
1273 * Sanity check the header of the base EDID block.
1274 *
1275 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
Thomas Reim051963d2011-07-29 14:28:57 +00001276 */
1277int drm_edid_header_is_valid(const u8 *raw_edid)
1278{
1279 int i, score = 0;
1280
1281 for (i = 0; i < sizeof(edid_header); i++)
1282 if (raw_edid[i] == edid_header[i])
1283 score++;
1284
1285 return score;
1286}
1287EXPORT_SYMBOL(drm_edid_header_is_valid);
1288
Adam Jackson47819ba2012-05-30 16:42:39 -04001289static int edid_fixup __read_mostly = 6;
1290module_param_named(edid_fixup, edid_fixup, int, 0400);
1291MODULE_PARM_DESC(edid_fixup,
1292 "Minimum number of valid EDID header bytes (0-8, default 6)");
Thomas Reim051963d2011-07-29 14:28:57 +00001293
Dave Airlie40d9b042014-10-20 16:29:33 +10001294static void drm_get_displayid(struct drm_connector *connector,
1295 struct edid *edid);
Dave Airlieda9df2f2014-12-11 10:12:57 +10001296
Stefan Brünsc465bbc2014-11-30 19:57:43 +01001297static int drm_edid_block_checksum(const u8 *raw_edid)
1298{
1299 int i;
1300 u8 csum = 0;
1301 for (i = 0; i < EDID_LENGTH; i++)
1302 csum += raw_edid[i];
1303
1304 return csum;
1305}
1306
Stefan Brünsd6885d62014-11-30 19:57:41 +01001307static bool drm_edid_is_zero(const u8 *in_edid, int length)
1308{
1309 if (memchr_inv(in_edid, 0, length))
1310 return false;
1311
1312 return true;
1313}
1314
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001315/**
1316 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1317 * @raw_edid: pointer to raw EDID block
1318 * @block: type of block to validate (0 for base, extension otherwise)
1319 * @print_bad_edid: if true, dump bad EDID blocks to the console
Todd Previte6ba2bd32015-04-21 11:09:41 -07001320 * @edid_corrupt: if true, the header or checksum is invalid
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001321 *
1322 * Validate a base or extension EDID block and optionally dump bad blocks to
1323 * the console.
1324 *
1325 * Return: True if the block is valid, false otherwise.
Dave Airlief453ba02008-11-07 14:05:41 -08001326 */
Todd Previte6ba2bd32015-04-21 11:09:41 -07001327bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1328 bool *edid_corrupt)
Dave Airlief453ba02008-11-07 14:05:41 -08001329{
Stefan Brünsc465bbc2014-11-30 19:57:43 +01001330 u8 csum;
Adam Jackson61e57a82010-03-29 21:43:18 +00001331 struct edid *edid = (struct edid *)raw_edid;
Dave Airlief453ba02008-11-07 14:05:41 -08001332
Seung-Woo Kimfe2ef782013-07-02 17:57:04 +09001333 if (WARN_ON(!raw_edid))
1334 return false;
1335
Adam Jackson47819ba2012-05-30 16:42:39 -04001336 if (edid_fixup > 8 || edid_fixup < 0)
1337 edid_fixup = 6;
1338
Adam Jacksonf89ec8a2012-04-16 10:40:08 -04001339 if (block == 0) {
Thomas Reim051963d2011-07-29 14:28:57 +00001340 int score = drm_edid_header_is_valid(raw_edid);
Todd Previte6ba2bd32015-04-21 11:09:41 -07001341 if (score == 8) {
1342 if (edid_corrupt)
Daniel Vetterac6f2e22015-05-08 16:15:41 +02001343 *edid_corrupt = false;
Todd Previte6ba2bd32015-04-21 11:09:41 -07001344 } else if (score >= edid_fixup) {
1345 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1346 * The corrupt flag needs to be set here otherwise, the
1347 * fix-up code here will correct the problem, the
1348 * checksum is correct and the test fails
1349 */
1350 if (edid_corrupt)
Daniel Vetterac6f2e22015-05-08 16:15:41 +02001351 *edid_corrupt = true;
Adam Jackson61e57a82010-03-29 21:43:18 +00001352 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1353 memcpy(raw_edid, edid_header, sizeof(edid_header));
1354 } else {
Todd Previte6ba2bd32015-04-21 11:09:41 -07001355 if (edid_corrupt)
Daniel Vetterac6f2e22015-05-08 16:15:41 +02001356 *edid_corrupt = true;
Adam Jackson61e57a82010-03-29 21:43:18 +00001357 goto bad;
1358 }
1359 }
Dave Airlief453ba02008-11-07 14:05:41 -08001360
Stefan Brünsc465bbc2014-11-30 19:57:43 +01001361 csum = drm_edid_block_checksum(raw_edid);
Dave Airlief453ba02008-11-07 14:05:41 -08001362 if (csum) {
Todd Previte6ba2bd32015-04-21 11:09:41 -07001363 if (edid_corrupt)
Daniel Vetterac6f2e22015-05-08 16:15:41 +02001364 *edid_corrupt = true;
Todd Previte6ba2bd32015-04-21 11:09:41 -07001365
Adam Jackson4a638b42010-05-25 16:33:09 -04001366 /* allow CEA to slide through, switches mangle this */
Tomeu Vizoso82d75352016-12-08 14:11:56 +01001367 if (raw_edid[0] == CEA_EXT) {
1368 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1369 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1370 } else {
1371 if (print_bad_edid)
Chris Wilson813a7872017-02-10 19:59:13 +00001372 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
Tomeu Vizoso82d75352016-12-08 14:11:56 +01001373
Adam Jackson4a638b42010-05-25 16:33:09 -04001374 goto bad;
Tomeu Vizoso82d75352016-12-08 14:11:56 +01001375 }
Dave Airlief453ba02008-11-07 14:05:41 -08001376 }
1377
Adam Jackson61e57a82010-03-29 21:43:18 +00001378 /* per-block-type checks */
1379 switch (raw_edid[0]) {
1380 case 0: /* base */
1381 if (edid->version != 1) {
Chris Wilson813a7872017-02-10 19:59:13 +00001382 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
Adam Jackson61e57a82010-03-29 21:43:18 +00001383 goto bad;
1384 }
Adam Jackson862b89c2009-11-23 14:23:06 -05001385
Adam Jackson61e57a82010-03-29 21:43:18 +00001386 if (edid->revision > 4)
1387 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1388 break;
1389
1390 default:
1391 break;
1392 }
Adam Jackson47ee4ccf2009-11-23 14:23:05 -05001393
Seung-Woo Kimfe2ef782013-07-02 17:57:04 +09001394 return true;
Dave Airlief453ba02008-11-07 14:05:41 -08001395
1396bad:
Seung-Woo Kimfe2ef782013-07-02 17:57:04 +09001397 if (print_bad_edid) {
Stefan Brünsda4c07b2014-11-30 19:57:42 +01001398 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
Joe Perches499447d2017-02-28 04:55:53 -08001399 pr_notice("EDID block is all zeroes\n");
Stefan Brünsda4c07b2014-11-30 19:57:42 +01001400 } else {
Joe Perches499447d2017-02-28 04:55:53 -08001401 pr_notice("Raw EDID:\n");
Chris Wilson813a7872017-02-10 19:59:13 +00001402 print_hex_dump(KERN_NOTICE,
1403 " \t", DUMP_PREFIX_NONE, 16, 1,
1404 raw_edid, EDID_LENGTH, false);
Stefan Brünsda4c07b2014-11-30 19:57:42 +01001405 }
Dave Airlief453ba02008-11-07 14:05:41 -08001406 }
Seung-Woo Kimfe2ef782013-07-02 17:57:04 +09001407 return false;
Dave Airlief453ba02008-11-07 14:05:41 -08001408}
Carsten Emdeda0df922012-03-18 22:37:33 +01001409EXPORT_SYMBOL(drm_edid_block_valid);
Adam Jackson61e57a82010-03-29 21:43:18 +00001410
1411/**
1412 * drm_edid_is_valid - sanity check EDID data
1413 * @edid: EDID data
1414 *
1415 * Sanity-check an entire EDID record (including extensions)
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001416 *
1417 * Return: True if the EDID data is valid, false otherwise.
Adam Jackson61e57a82010-03-29 21:43:18 +00001418 */
1419bool drm_edid_is_valid(struct edid *edid)
1420{
1421 int i;
1422 u8 *raw = (u8 *)edid;
1423
1424 if (!edid)
1425 return false;
1426
1427 for (i = 0; i <= edid->extensions; i++)
Todd Previte6ba2bd32015-04-21 11:09:41 -07001428 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
Adam Jackson61e57a82010-03-29 21:43:18 +00001429 return false;
1430
1431 return true;
1432}
Alex Deucher3c537882010-02-05 04:21:19 -05001433EXPORT_SYMBOL(drm_edid_is_valid);
Dave Airlief453ba02008-11-07 14:05:41 -08001434
Adam Jackson61e57a82010-03-29 21:43:18 +00001435#define DDC_SEGMENT_ADDR 0x30
1436/**
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001437 * drm_do_probe_ddc_edid() - get EDID information via I2C
Thierry Reding7c58e872014-12-03 16:52:18 +01001438 * @data: I2C device adapter
Daniel Vetterfc668112014-01-21 12:02:26 +01001439 * @buf: EDID data buffer to be filled
1440 * @block: 128 byte EDID block to start fetching from
1441 * @len: EDID data buffer length to fetch
1442 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001443 * Try to fetch EDID information by calling I2C driver functions.
Daniel Vetterfc668112014-01-21 12:02:26 +01001444 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001445 * Return: 0 on success or -1 on failure.
Adam Jackson61e57a82010-03-29 21:43:18 +00001446 */
1447static int
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001448drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
Adam Jackson61e57a82010-03-29 21:43:18 +00001449{
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001450 struct i2c_adapter *adapter = data;
Adam Jackson61e57a82010-03-29 21:43:18 +00001451 unsigned char start = block * EDID_LENGTH;
Shirish Scd004b32012-08-30 07:04:06 +00001452 unsigned char segment = block >> 1;
1453 unsigned char xfers = segment ? 3 : 2;
Chris Wilson4819d2e2011-03-15 11:04:41 +00001454 int ret, retries = 5;
Adam Jackson61e57a82010-03-29 21:43:18 +00001455
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001456 /*
1457 * The core I2C driver will automatically retry the transfer if the
Chris Wilson4819d2e2011-03-15 11:04:41 +00001458 * adapter reports EAGAIN. However, we find that bit-banging transfers
1459 * are susceptible to errors under a heavily loaded machine and
1460 * generate spurious NAKs and timeouts. Retrying the transfer
1461 * of the individual block a few times seems to overcome this.
1462 */
1463 do {
1464 struct i2c_msg msgs[] = {
1465 {
Shirish Scd004b32012-08-30 07:04:06 +00001466 .addr = DDC_SEGMENT_ADDR,
1467 .flags = 0,
1468 .len = 1,
1469 .buf = &segment,
1470 }, {
Chris Wilson4819d2e2011-03-15 11:04:41 +00001471 .addr = DDC_ADDR,
1472 .flags = 0,
1473 .len = 1,
1474 .buf = &start,
1475 }, {
1476 .addr = DDC_ADDR,
1477 .flags = I2C_M_RD,
1478 .len = len,
1479 .buf = buf,
1480 }
1481 };
Shirish Scd004b32012-08-30 07:04:06 +00001482
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001483 /*
1484 * Avoid sending the segment addr to not upset non-compliant
1485 * DDC monitors.
1486 */
Shirish Scd004b32012-08-30 07:04:06 +00001487 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1488
Eugeni Dodonov9292f372012-01-05 09:34:28 -02001489 if (ret == -ENXIO) {
1490 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1491 adapter->name);
1492 break;
1493 }
Shirish Scd004b32012-08-30 07:04:06 +00001494 } while (ret != xfers && --retries);
Adam Jackson61e57a82010-03-29 21:43:18 +00001495
Shirish Scd004b32012-08-30 07:04:06 +00001496 return ret == xfers ? 0 : -1;
Adam Jackson61e57a82010-03-29 21:43:18 +00001497}
1498
Chris Wilson14544d02016-10-24 12:38:21 +01001499static void connector_bad_edid(struct drm_connector *connector,
1500 u8 *edid, int num_blocks)
1501{
1502 int i;
1503
1504 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1505 return;
1506
1507 dev_warn(connector->dev->dev,
1508 "%s: EDID is invalid:\n",
1509 connector->name);
1510 for (i = 0; i < num_blocks; i++) {
1511 u8 *block = edid + i * EDID_LENGTH;
1512 char prefix[20];
1513
1514 if (drm_edid_is_zero(block, EDID_LENGTH))
1515 sprintf(prefix, "\t[%02x] ZERO ", i);
1516 else if (!drm_edid_block_valid(block, i, false, NULL))
1517 sprintf(prefix, "\t[%02x] BAD ", i);
1518 else
1519 sprintf(prefix, "\t[%02x] GOOD ", i);
1520
1521 print_hex_dump(KERN_WARNING,
1522 prefix, DUMP_PREFIX_NONE, 16, 1,
1523 block, EDID_LENGTH, false);
1524 }
1525}
1526
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001527/**
1528 * drm_do_get_edid - get EDID data using a custom EDID block read function
1529 * @connector: connector we're probing
1530 * @get_edid_block: EDID block read function
1531 * @data: private data passed to the block read function
1532 *
1533 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1534 * exposes a different interface to read EDID blocks this function can be used
1535 * to get EDID data using a custom block read function.
1536 *
1537 * As in the general case the DDC bus is accessible by the kernel at the I2C
1538 * level, drivers must make all reasonable efforts to expose it as an I2C
1539 * adapter and use drm_get_edid() instead of abusing this function.
1540 *
Jani Nikula53fd40a2017-09-12 11:19:26 +03001541 * The EDID may be overridden using debugfs override_edid or firmare EDID
1542 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1543 * order. Having either of them bypasses actual EDID reads.
1544 *
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001545 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1546 */
1547struct edid *drm_do_get_edid(struct drm_connector *connector,
1548 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1549 size_t len),
1550 void *data)
Adam Jackson61e57a82010-03-29 21:43:18 +00001551{
Sam Tygier0ea75e22010-09-23 10:11:01 +01001552 int i, j = 0, valid_extensions = 0;
Chris Wilsonf14f3682016-10-17 09:35:12 +01001553 u8 *edid, *new;
Jani Nikula53fd40a2017-09-12 11:19:26 +03001554 struct edid *override = NULL;
1555
1556 if (connector->override_edid)
1557 override = drm_edid_duplicate((const struct edid *)
1558 connector->edid_blob_ptr->data);
1559
1560 if (!override)
1561 override = drm_load_edid_firmware(connector);
1562
1563 if (!IS_ERR_OR_NULL(override))
1564 return override;
Adam Jackson61e57a82010-03-29 21:43:18 +00001565
Chris Wilsonf14f3682016-10-17 09:35:12 +01001566 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
Adam Jackson61e57a82010-03-29 21:43:18 +00001567 return NULL;
1568
1569 /* base block fetch */
1570 for (i = 0; i < 4; i++) {
Chris Wilsonf14f3682016-10-17 09:35:12 +01001571 if (get_edid_block(data, edid, 0, EDID_LENGTH))
Adam Jackson61e57a82010-03-29 21:43:18 +00001572 goto out;
Chris Wilson14544d02016-10-24 12:38:21 +01001573 if (drm_edid_block_valid(edid, 0, false,
Todd Previte6ba2bd32015-04-21 11:09:41 -07001574 &connector->edid_corrupt))
Adam Jackson61e57a82010-03-29 21:43:18 +00001575 break;
Chris Wilsonf14f3682016-10-17 09:35:12 +01001576 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
Dave Airlie4a9a8b72011-06-14 06:13:55 +00001577 connector->null_edid_counter++;
1578 goto carp;
1579 }
Adam Jackson61e57a82010-03-29 21:43:18 +00001580 }
1581 if (i == 4)
1582 goto carp;
1583
1584 /* if there's no extensions, we're done */
Chris Wilson14544d02016-10-24 12:38:21 +01001585 valid_extensions = edid[0x7e];
1586 if (valid_extensions == 0)
Chris Wilsonf14f3682016-10-17 09:35:12 +01001587 return (struct edid *)edid;
Adam Jackson61e57a82010-03-29 21:43:18 +00001588
Chris Wilson14544d02016-10-24 12:38:21 +01001589 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
Adam Jackson61e57a82010-03-29 21:43:18 +00001590 if (!new)
1591 goto out;
Chris Wilsonf14f3682016-10-17 09:35:12 +01001592 edid = new;
Adam Jackson61e57a82010-03-29 21:43:18 +00001593
Chris Wilsonf14f3682016-10-17 09:35:12 +01001594 for (j = 1; j <= edid[0x7e]; j++) {
Chris Wilson14544d02016-10-24 12:38:21 +01001595 u8 *block = edid + j * EDID_LENGTH;
Chris Wilsona28187c2016-10-17 09:35:13 +01001596
Adam Jackson61e57a82010-03-29 21:43:18 +00001597 for (i = 0; i < 4; i++) {
Chris Wilsona28187c2016-10-17 09:35:13 +01001598 if (get_edid_block(data, block, j, EDID_LENGTH))
Adam Jackson61e57a82010-03-29 21:43:18 +00001599 goto out;
Chris Wilson14544d02016-10-24 12:38:21 +01001600 if (drm_edid_block_valid(block, j, false, NULL))
Adam Jackson61e57a82010-03-29 21:43:18 +00001601 break;
1602 }
Maarten Lankhorstf934ec8c2013-01-29 14:27:39 +01001603
Chris Wilson14544d02016-10-24 12:38:21 +01001604 if (i == 4)
1605 valid_extensions--;
Sam Tygier0ea75e22010-09-23 10:11:01 +01001606 }
1607
Chris Wilsonf14f3682016-10-17 09:35:12 +01001608 if (valid_extensions != edid[0x7e]) {
Chris Wilson14544d02016-10-24 12:38:21 +01001609 u8 *base;
1610
1611 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1612
Chris Wilsonf14f3682016-10-17 09:35:12 +01001613 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1614 edid[0x7e] = valid_extensions;
Chris Wilson14544d02016-10-24 12:38:21 +01001615
1616 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
Sam Tygier0ea75e22010-09-23 10:11:01 +01001617 if (!new)
1618 goto out;
Chris Wilson14544d02016-10-24 12:38:21 +01001619
1620 base = new;
1621 for (i = 0; i <= edid[0x7e]; i++) {
1622 u8 *block = edid + i * EDID_LENGTH;
1623
1624 if (!drm_edid_block_valid(block, i, false, NULL))
1625 continue;
1626
1627 memcpy(base, block, EDID_LENGTH);
1628 base += EDID_LENGTH;
1629 }
1630
1631 kfree(edid);
Chris Wilsonf14f3682016-10-17 09:35:12 +01001632 edid = new;
Adam Jackson61e57a82010-03-29 21:43:18 +00001633 }
1634
Chris Wilsonf14f3682016-10-17 09:35:12 +01001635 return (struct edid *)edid;
Adam Jackson61e57a82010-03-29 21:43:18 +00001636
1637carp:
Chris Wilson14544d02016-10-24 12:38:21 +01001638 connector_bad_edid(connector, edid, 1);
Adam Jackson61e57a82010-03-29 21:43:18 +00001639out:
Chris Wilsonf14f3682016-10-17 09:35:12 +01001640 kfree(edid);
Adam Jackson61e57a82010-03-29 21:43:18 +00001641 return NULL;
1642}
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001643EXPORT_SYMBOL_GPL(drm_do_get_edid);
Adam Jackson61e57a82010-03-29 21:43:18 +00001644
1645/**
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001646 * drm_probe_ddc() - probe DDC presence
1647 * @adapter: I2C adapter to probe
Adam Jackson61e57a82010-03-29 21:43:18 +00001648 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001649 * Return: True on success, false on failure.
Adam Jackson61e57a82010-03-29 21:43:18 +00001650 */
Adam Jacksonfbff4692012-09-18 10:58:47 -04001651bool
Adam Jackson61e57a82010-03-29 21:43:18 +00001652drm_probe_ddc(struct i2c_adapter *adapter)
1653{
1654 unsigned char out;
1655
1656 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1657}
Adam Jacksonfbff4692012-09-18 10:58:47 -04001658EXPORT_SYMBOL(drm_probe_ddc);
Adam Jackson61e57a82010-03-29 21:43:18 +00001659
1660/**
1661 * drm_get_edid - get EDID data, if available
1662 * @connector: connector we're probing
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001663 * @adapter: I2C adapter to use for DDC
Adam Jackson61e57a82010-03-29 21:43:18 +00001664 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001665 * Poke the given I2C channel to grab EDID data if possible. If found,
Adam Jackson61e57a82010-03-29 21:43:18 +00001666 * attach it to the connector.
1667 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001668 * Return: Pointer to valid EDID or NULL if we couldn't find any.
Adam Jackson61e57a82010-03-29 21:43:18 +00001669 */
1670struct edid *drm_get_edid(struct drm_connector *connector,
1671 struct i2c_adapter *adapter)
1672{
Dave Airlie40d9b042014-10-20 16:29:33 +10001673 struct edid *edid;
1674
Jani Nikula15f080f2017-02-17 17:20:53 +02001675 if (connector->force == DRM_FORCE_OFF)
1676 return NULL;
1677
1678 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
Lars-Peter Clausen18df89f2012-04-27 11:11:58 +02001679 return NULL;
Adam Jackson61e57a82010-03-29 21:43:18 +00001680
Dave Airlie40d9b042014-10-20 16:29:33 +10001681 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1682 if (edid)
1683 drm_get_displayid(connector, edid);
1684 return edid;
Adam Jackson61e57a82010-03-29 21:43:18 +00001685}
1686EXPORT_SYMBOL(drm_get_edid);
1687
Jani Nikula51f8da52013-09-27 15:08:27 +03001688/**
Lukas Wunner5cb8eaa22016-01-11 20:09:20 +01001689 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1690 * @connector: connector we're probing
1691 * @adapter: I2C adapter to use for DDC
1692 *
1693 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1694 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1695 * switch DDC to the GPU which is retrieving EDID.
1696 *
1697 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1698 */
1699struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1700 struct i2c_adapter *adapter)
1701{
1702 struct pci_dev *pdev = connector->dev->pdev;
1703 struct edid *edid;
1704
1705 vga_switcheroo_lock_ddc(pdev);
1706 edid = drm_get_edid(connector, adapter);
1707 vga_switcheroo_unlock_ddc(pdev);
1708
1709 return edid;
1710}
1711EXPORT_SYMBOL(drm_get_edid_switcheroo);
1712
1713/**
Jani Nikula51f8da52013-09-27 15:08:27 +03001714 * drm_edid_duplicate - duplicate an EDID and the extensions
1715 * @edid: EDID to duplicate
1716 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001717 * Return: Pointer to duplicated EDID or NULL on allocation failure.
Jani Nikula51f8da52013-09-27 15:08:27 +03001718 */
1719struct edid *drm_edid_duplicate(const struct edid *edid)
1720{
1721 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1722}
1723EXPORT_SYMBOL(drm_edid_duplicate);
1724
Adam Jackson61e57a82010-03-29 21:43:18 +00001725/*** EDID parsing ***/
1726
Dave Airlief453ba02008-11-07 14:05:41 -08001727/**
1728 * edid_vendor - match a string against EDID's obfuscated vendor field
1729 * @edid: EDID to match
1730 * @vendor: vendor string
1731 *
1732 * Returns true if @vendor is in @edid, false otherwise
1733 */
Keith Packard170178f2017-12-13 00:44:26 -08001734static bool edid_vendor(const struct edid *edid, const char *vendor)
Dave Airlief453ba02008-11-07 14:05:41 -08001735{
1736 char edid_vendor[3];
1737
1738 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1739 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1740 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
Dave Airlie16456c82009-04-03 09:10:33 +10001741 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
Dave Airlief453ba02008-11-07 14:05:41 -08001742
1743 return !strncmp(edid_vendor, vendor, 3);
1744}
1745
1746/**
1747 * edid_get_quirks - return quirk flags for a given EDID
1748 * @edid: EDID to process
1749 *
1750 * This tells subsequent routines what fixes they need to apply.
1751 */
Keith Packard170178f2017-12-13 00:44:26 -08001752static u32 edid_get_quirks(const struct edid *edid)
Dave Airlief453ba02008-11-07 14:05:41 -08001753{
Jani Nikula23c4cfb2016-12-28 13:06:26 +02001754 const struct edid_quirk *quirk;
Dave Airlief453ba02008-11-07 14:05:41 -08001755 int i;
1756
1757 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1758 quirk = &edid_quirk_list[i];
1759
1760 if (edid_vendor(edid, quirk->vendor) &&
1761 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1762 return quirk->quirks;
1763 }
1764
1765 return 0;
1766}
1767
1768#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
Alex Deucher339d2022013-08-15 11:42:14 -04001769#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
Dave Airlief453ba02008-11-07 14:05:41 -08001770
Dave Airlief453ba02008-11-07 14:05:41 -08001771/**
1772 * edid_fixup_preferred - set preferred modes based on quirk list
1773 * @connector: has mode list to fix up
1774 * @quirks: quirks list
1775 *
1776 * Walk the mode list for @connector, clearing the preferred status
1777 * on existing modes and setting it anew for the right mode ala @quirks.
1778 */
1779static void edid_fixup_preferred(struct drm_connector *connector,
1780 u32 quirks)
1781{
1782 struct drm_display_mode *t, *cur_mode, *preferred_mode;
Dave Airlief8906072008-12-18 16:59:02 +10001783 int target_refresh = 0;
Alex Deucher339d2022013-08-15 11:42:14 -04001784 int cur_vrefresh, preferred_vrefresh;
Dave Airlief453ba02008-11-07 14:05:41 -08001785
1786 if (list_empty(&connector->probed_modes))
1787 return;
1788
1789 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1790 target_refresh = 60;
1791 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1792 target_refresh = 75;
1793
1794 preferred_mode = list_first_entry(&connector->probed_modes,
1795 struct drm_display_mode, head);
1796
1797 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1798 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1799
1800 if (cur_mode == preferred_mode)
1801 continue;
1802
1803 /* Largest mode is preferred */
1804 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1805 preferred_mode = cur_mode;
1806
Alex Deucher339d2022013-08-15 11:42:14 -04001807 cur_vrefresh = cur_mode->vrefresh ?
1808 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1809 preferred_vrefresh = preferred_mode->vrefresh ?
1810 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
Dave Airlief453ba02008-11-07 14:05:41 -08001811 /* At a given size, try to get closest to target refresh */
1812 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
Alex Deucher339d2022013-08-15 11:42:14 -04001813 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1814 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
Dave Airlief453ba02008-11-07 14:05:41 -08001815 preferred_mode = cur_mode;
1816 }
1817 }
1818
1819 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1820}
1821
Adam Jacksonf6e252b2012-04-13 16:33:31 -04001822static bool
1823mode_is_rb(const struct drm_display_mode *mode)
1824{
1825 return (mode->htotal - mode->hdisplay == 160) &&
1826 (mode->hsync_end - mode->hdisplay == 80) &&
1827 (mode->hsync_end - mode->hsync_start == 32) &&
1828 (mode->vsync_start - mode->vdisplay == 3);
1829}
1830
Adam Jackson33c75312012-04-13 16:33:29 -04001831/*
1832 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1833 * @dev: Device to duplicate against
1834 * @hsize: Mode width
1835 * @vsize: Mode height
1836 * @fresh: Mode refresh rate
Adam Jacksonf6e252b2012-04-13 16:33:31 -04001837 * @rb: Mode reduced-blanking-ness
Adam Jackson33c75312012-04-13 16:33:29 -04001838 *
1839 * Walk the DMT mode list looking for a match for the given parameters.
Thierry Redingdb6cf8332014-04-29 11:44:34 +02001840 *
1841 * Return: A newly allocated copy of the mode, or NULL if not found.
Adam Jackson33c75312012-04-13 16:33:29 -04001842 */
Dave Airlie1d42bbc2010-05-07 05:02:30 +00001843struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
Adam Jacksonf6e252b2012-04-13 16:33:31 -04001844 int hsize, int vsize, int fresh,
1845 bool rb)
Zhao Yakui559ee212009-09-03 09:33:47 +08001846{
Adam Jackson07a5e632009-12-03 17:44:38 -05001847 int i;
Zhao Yakui559ee212009-09-03 09:33:47 +08001848
Thierry Redinga6b21832012-11-23 15:01:42 +01001849 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
Chris Wilsonb1f559e2011-01-26 09:49:47 +00001850 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
Adam Jacksonf8b46a02012-04-13 16:33:30 -04001851 if (hsize != ptr->hdisplay)
1852 continue;
1853 if (vsize != ptr->vdisplay)
1854 continue;
1855 if (fresh != drm_mode_vrefresh(ptr))
1856 continue;
Adam Jacksonf6e252b2012-04-13 16:33:31 -04001857 if (rb != mode_is_rb(ptr))
1858 continue;
Adam Jacksonf8b46a02012-04-13 16:33:30 -04001859
1860 return drm_mode_duplicate(dev, ptr);
Zhao Yakui559ee212009-09-03 09:33:47 +08001861 }
Adam Jacksonf8b46a02012-04-13 16:33:30 -04001862
1863 return NULL;
Zhao Yakui559ee212009-09-03 09:33:47 +08001864}
Dave Airlie1d42bbc2010-05-07 05:02:30 +00001865EXPORT_SYMBOL(drm_mode_find_dmt);
Adam Jackson23425ca2009-09-23 17:30:58 -04001866
Adam Jacksond1ff6402010-03-29 21:43:26 +00001867typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1868
1869static void
Adam Jackson4d76a222010-08-03 14:38:17 -04001870cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1871{
1872 int i, n = 0;
Christian Schmidt4966b2a2011-12-19 20:03:43 +01001873 u8 d = ext[0x02];
Adam Jackson4d76a222010-08-03 14:38:17 -04001874 u8 *det_base = ext + d;
1875
Christian Schmidt4966b2a2011-12-19 20:03:43 +01001876 n = (127 - d) / 18;
Adam Jackson4d76a222010-08-03 14:38:17 -04001877 for (i = 0; i < n; i++)
1878 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1879}
1880
1881static void
Adam Jacksoncbba98f2010-08-03 14:38:18 -04001882vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1883{
1884 unsigned int i, n = min((int)ext[0x02], 6);
1885 u8 *det_base = ext + 5;
1886
1887 if (ext[0x01] != 1)
1888 return; /* unknown version */
1889
1890 for (i = 0; i < n; i++)
1891 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1892}
1893
1894static void
Adam Jacksond1ff6402010-03-29 21:43:26 +00001895drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1896{
1897 int i;
1898 struct edid *edid = (struct edid *)raw_edid;
1899
1900 if (edid == NULL)
1901 return;
1902
1903 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1904 cb(&(edid->detailed_timings[i]), closure);
1905
Adam Jackson4d76a222010-08-03 14:38:17 -04001906 for (i = 1; i <= raw_edid[0x7e]; i++) {
1907 u8 *ext = raw_edid + (i * EDID_LENGTH);
1908 switch (*ext) {
1909 case CEA_EXT:
1910 cea_for_each_detailed_block(ext, cb, closure);
1911 break;
Adam Jacksoncbba98f2010-08-03 14:38:18 -04001912 case VTB_EXT:
1913 vtb_for_each_detailed_block(ext, cb, closure);
1914 break;
Adam Jackson4d76a222010-08-03 14:38:17 -04001915 default:
1916 break;
1917 }
1918 }
Adam Jacksond1ff6402010-03-29 21:43:26 +00001919}
1920
1921static void
1922is_rb(struct detailed_timing *t, void *data)
1923{
1924 u8 *r = (u8 *)t;
1925 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1926 if (r[15] & 0x10)
1927 *(bool *)data = true;
1928}
1929
1930/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1931static bool
1932drm_monitor_supports_rb(struct edid *edid)
1933{
1934 if (edid->revision >= 4) {
Daniel Vetterb196a492012-06-19 11:33:06 +02001935 bool ret = false;
Adam Jacksond1ff6402010-03-29 21:43:26 +00001936 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1937 return ret;
1938 }
1939
1940 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1941}
1942
Adam Jackson7a374352010-03-29 21:43:30 +00001943static void
1944find_gtf2(struct detailed_timing *t, void *data)
1945{
1946 u8 *r = (u8 *)t;
1947 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1948 *(u8 **)data = r;
1949}
1950
1951/* Secondary GTF curve kicks in above some break frequency */
1952static int
1953drm_gtf2_hbreak(struct edid *edid)
1954{
1955 u8 *r = NULL;
1956 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1957 return r ? (r[12] * 2) : 0;
1958}
1959
1960static int
1961drm_gtf2_2c(struct edid *edid)
1962{
1963 u8 *r = NULL;
1964 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1965 return r ? r[13] : 0;
1966}
1967
1968static int
1969drm_gtf2_m(struct edid *edid)
1970{
1971 u8 *r = NULL;
1972 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1973 return r ? (r[15] << 8) + r[14] : 0;
1974}
1975
1976static int
1977drm_gtf2_k(struct edid *edid)
1978{
1979 u8 *r = NULL;
1980 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1981 return r ? r[16] : 0;
1982}
1983
1984static int
1985drm_gtf2_2j(struct edid *edid)
1986{
1987 u8 *r = NULL;
1988 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1989 return r ? r[17] : 0;
1990}
1991
1992/**
1993 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1994 * @edid: EDID block to scan
1995 */
1996static int standard_timing_level(struct edid *edid)
1997{
1998 if (edid->revision >= 2) {
1999 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2000 return LEVEL_CVT;
2001 if (drm_gtf2_hbreak(edid))
2002 return LEVEL_GTF2;
2003 return LEVEL_GTF;
2004 }
2005 return LEVEL_DMT;
2006}
2007
Adam Jackson23425ca2009-09-23 17:30:58 -04002008/*
2009 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2010 * monitors fill with ascii space (0x20) instead.
2011 */
2012static int
2013bad_std_timing(u8 a, u8 b)
2014{
2015 return (a == 0x00 && b == 0x00) ||
2016 (a == 0x01 && b == 0x01) ||
2017 (a == 0x20 && b == 0x20);
2018}
2019
Dave Airlief453ba02008-11-07 14:05:41 -08002020/**
2021 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
Daniel Vetterfc668112014-01-21 12:02:26 +01002022 * @connector: connector of for the EDID block
2023 * @edid: EDID block to scan
Dave Airlief453ba02008-11-07 14:05:41 -08002024 * @t: standard timing params
2025 *
2026 * Take the standard timing params (in this case width, aspect, and refresh)
Zhao Yakui5c612592009-06-22 13:17:10 +08002027 * and convert them into a real mode using CVT/GTF/DMT.
Dave Airlief453ba02008-11-07 14:05:41 -08002028 */
Adam Jackson7ca6adb2010-03-29 21:43:29 +00002029static struct drm_display_mode *
Adam Jackson7a374352010-03-29 21:43:30 +00002030drm_mode_std(struct drm_connector *connector, struct edid *edid,
Thierry Reding464fdec2014-04-29 11:44:33 +02002031 struct std_timing *t)
Dave Airlief453ba02008-11-07 14:05:41 -08002032{
Adam Jackson7ca6adb2010-03-29 21:43:29 +00002033 struct drm_device *dev = connector->dev;
2034 struct drm_display_mode *m, *mode = NULL;
Zhao Yakui5c612592009-06-22 13:17:10 +08002035 int hsize, vsize;
2036 int vrefresh_rate;
Michel Dänzer0454bea2009-06-15 16:56:07 +02002037 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2038 >> EDID_TIMING_ASPECT_SHIFT;
Zhao Yakui5c612592009-06-22 13:17:10 +08002039 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2040 >> EDID_TIMING_VFREQ_SHIFT;
Adam Jackson7a374352010-03-29 21:43:30 +00002041 int timing_level = standard_timing_level(edid);
Dave Airlief453ba02008-11-07 14:05:41 -08002042
Adam Jackson23425ca2009-09-23 17:30:58 -04002043 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2044 return NULL;
2045
Zhao Yakui5c612592009-06-22 13:17:10 +08002046 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2047 hsize = t->hsize * 8 + 248;
2048 /* vrefresh_rate = vfreq + 60 */
2049 vrefresh_rate = vfreq + 60;
2050 /* the vdisplay is calculated based on the aspect ratio */
Adam Jacksonf066a172009-09-23 17:31:21 -04002051 if (aspect_ratio == 0) {
Thierry Reding464fdec2014-04-29 11:44:33 +02002052 if (edid->revision < 3)
Adam Jacksonf066a172009-09-23 17:31:21 -04002053 vsize = hsize;
2054 else
2055 vsize = (hsize * 10) / 16;
2056 } else if (aspect_ratio == 1)
Dave Airlief453ba02008-11-07 14:05:41 -08002057 vsize = (hsize * 3) / 4;
Michel Dänzer0454bea2009-06-15 16:56:07 +02002058 else if (aspect_ratio == 2)
Dave Airlief453ba02008-11-07 14:05:41 -08002059 vsize = (hsize * 4) / 5;
2060 else
2061 vsize = (hsize * 9) / 16;
Adam Jacksona0910c82010-03-29 21:43:28 +00002062
2063 /* HDTV hack, part 1 */
2064 if (vrefresh_rate == 60 &&
2065 ((hsize == 1360 && vsize == 765) ||
2066 (hsize == 1368 && vsize == 769))) {
2067 hsize = 1366;
2068 vsize = 768;
2069 }
2070
Adam Jackson7ca6adb2010-03-29 21:43:29 +00002071 /*
2072 * If this connector already has a mode for this size and refresh
2073 * rate (because it came from detailed or CVT info), use that
2074 * instead. This way we don't have to guess at interlace or
2075 * reduced blanking.
2076 */
Adam Jackson522032d2010-04-09 16:52:49 +00002077 list_for_each_entry(m, &connector->probed_modes, head)
Adam Jackson7ca6adb2010-03-29 21:43:29 +00002078 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2079 drm_mode_vrefresh(m) == vrefresh_rate)
2080 return NULL;
2081
Adam Jacksona0910c82010-03-29 21:43:28 +00002082 /* HDTV hack, part 2 */
2083 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2084 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
Dave Airlied50ba252009-09-23 14:44:08 +10002085 false);
Zhao Yakui559ee212009-09-03 09:33:47 +08002086 mode->hdisplay = 1366;
Adam Jacksona4967de62010-07-28 07:40:32 +10002087 mode->hsync_start = mode->hsync_start - 1;
2088 mode->hsync_end = mode->hsync_end - 1;
Zhao Yakui559ee212009-09-03 09:33:47 +08002089 return mode;
2090 }
Adam Jacksona0910c82010-03-29 21:43:28 +00002091
Zhao Yakui559ee212009-09-03 09:33:47 +08002092 /* check whether it can be found in default mode table */
Adam Jacksonf6e252b2012-04-13 16:33:31 -04002093 if (drm_monitor_supports_rb(edid)) {
2094 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2095 true);
2096 if (mode)
2097 return mode;
2098 }
2099 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
Zhao Yakui559ee212009-09-03 09:33:47 +08002100 if (mode)
2101 return mode;
2102
Adam Jacksonf6e252b2012-04-13 16:33:31 -04002103 /* okay, generate it */
Zhao Yakui5c612592009-06-22 13:17:10 +08002104 switch (timing_level) {
2105 case LEVEL_DMT:
Zhao Yakui5c612592009-06-22 13:17:10 +08002106 break;
2107 case LEVEL_GTF:
2108 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2109 break;
Adam Jackson7a374352010-03-29 21:43:30 +00002110 case LEVEL_GTF2:
2111 /*
2112 * This is potentially wrong if there's ever a monitor with
2113 * more than one ranges section, each claiming a different
2114 * secondary GTF curve. Please don't do that.
2115 */
2116 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
Takashi Iwaifc48f162012-04-20 12:59:33 +01002117 if (!mode)
2118 return NULL;
Adam Jackson7a374352010-03-29 21:43:30 +00002119 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
Sascha Haueraefd3302012-02-01 11:38:21 +01002120 drm_mode_destroy(dev, mode);
Adam Jackson7a374352010-03-29 21:43:30 +00002121 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2122 vrefresh_rate, 0, 0,
2123 drm_gtf2_m(edid),
2124 drm_gtf2_2c(edid),
2125 drm_gtf2_k(edid),
2126 drm_gtf2_2j(edid));
2127 }
2128 break;
Zhao Yakui5c612592009-06-22 13:17:10 +08002129 case LEVEL_CVT:
Dave Airlied50ba252009-09-23 14:44:08 +10002130 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2131 false);
Zhao Yakui5c612592009-06-22 13:17:10 +08002132 break;
2133 }
Dave Airlief453ba02008-11-07 14:05:41 -08002134 return mode;
2135}
2136
Adam Jacksonb58db2c2010-02-15 22:15:39 +00002137/*
2138 * EDID is delightfully ambiguous about how interlaced modes are to be
2139 * encoded. Our internal representation is of frame height, but some
2140 * HDTV detailed timings are encoded as field height.
2141 *
2142 * The format list here is from CEA, in frame size. Technically we
2143 * should be checking refresh rate too. Whatever.
2144 */
2145static void
2146drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2147 struct detailed_pixel_timing *pt)
2148{
2149 int i;
2150 static const struct {
2151 int w, h;
2152 } cea_interlaced[] = {
2153 { 1920, 1080 },
2154 { 720, 480 },
2155 { 1440, 480 },
2156 { 2880, 480 },
2157 { 720, 576 },
2158 { 1440, 576 },
2159 { 2880, 576 },
2160 };
Adam Jacksonb58db2c2010-02-15 22:15:39 +00002161
2162 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2163 return;
2164
Kulikov Vasiliy3c581412010-06-28 15:54:52 +04002165 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
Adam Jacksonb58db2c2010-02-15 22:15:39 +00002166 if ((mode->hdisplay == cea_interlaced[i].w) &&
2167 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2168 mode->vdisplay *= 2;
2169 mode->vsync_start *= 2;
2170 mode->vsync_end *= 2;
2171 mode->vtotal *= 2;
2172 mode->vtotal |= 1;
2173 }
2174 }
2175
2176 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2177}
2178
Dave Airlief453ba02008-11-07 14:05:41 -08002179/**
2180 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2181 * @dev: DRM device (needed to create new mode)
2182 * @edid: EDID block
2183 * @timing: EDID detailed timing info
2184 * @quirks: quirks to apply
2185 *
2186 * An EDID detailed timing block contains enough info for us to create and
2187 * return a new struct drm_display_mode.
2188 */
2189static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2190 struct edid *edid,
2191 struct detailed_timing *timing,
2192 u32 quirks)
2193{
2194 struct drm_display_mode *mode;
2195 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
Michel Dänzer0454bea2009-06-15 16:56:07 +02002196 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2197 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2198 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2199 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
Michel Dänzere14cbee2009-06-23 12:36:32 +02002200 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2201 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
Torsten Duwe16dad1d2013-03-23 15:38:22 +01002202 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
Michel Dänzere14cbee2009-06-23 12:36:32 +02002203 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
Dave Airlief453ba02008-11-07 14:05:41 -08002204
Adam Jacksonfc438962009-06-04 10:20:34 +10002205 /* ignore tiny modes */
Michel Dänzer0454bea2009-06-15 16:56:07 +02002206 if (hactive < 64 || vactive < 64)
Adam Jacksonfc438962009-06-04 10:20:34 +10002207 return NULL;
2208
Michel Dänzer0454bea2009-06-15 16:56:07 +02002209 if (pt->misc & DRM_EDID_PT_STEREO) {
Egbert Eichc7d015f32013-06-13 21:01:19 +02002210 DRM_DEBUG_KMS("stereo mode not supported\n");
Dave Airlief453ba02008-11-07 14:05:41 -08002211 return NULL;
2212 }
Michel Dänzer0454bea2009-06-15 16:56:07 +02002213 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
Egbert Eichc7d015f32013-06-13 21:01:19 +02002214 DRM_DEBUG_KMS("composite sync not supported\n");
Dave Airlief453ba02008-11-07 14:05:41 -08002215 }
2216
Zhao Yakuifcb45612009-10-14 09:11:25 +08002217 /* it is incorrect if hsync/vsync width is zero */
2218 if (!hsync_pulse_width || !vsync_pulse_width) {
2219 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2220 "Wrong Hsync/Vsync pulse width\n");
2221 return NULL;
2222 }
Adam Jacksonbc42aab2012-05-23 16:26:54 -04002223
2224 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2225 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2226 if (!mode)
2227 return NULL;
2228
2229 goto set_size;
2230 }
2231
Dave Airlief453ba02008-11-07 14:05:41 -08002232 mode = drm_mode_create(dev);
2233 if (!mode)
2234 return NULL;
2235
Dave Airlief453ba02008-11-07 14:05:41 -08002236 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
Michel Dänzer0454bea2009-06-15 16:56:07 +02002237 timing->pixel_clock = cpu_to_le16(1088);
Dave Airlief453ba02008-11-07 14:05:41 -08002238
Michel Dänzer0454bea2009-06-15 16:56:07 +02002239 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
Dave Airlief453ba02008-11-07 14:05:41 -08002240
Michel Dänzer0454bea2009-06-15 16:56:07 +02002241 mode->hdisplay = hactive;
2242 mode->hsync_start = mode->hdisplay + hsync_offset;
2243 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2244 mode->htotal = mode->hdisplay + hblank;
Dave Airlief453ba02008-11-07 14:05:41 -08002245
Michel Dänzer0454bea2009-06-15 16:56:07 +02002246 mode->vdisplay = vactive;
2247 mode->vsync_start = mode->vdisplay + vsync_offset;
2248 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2249 mode->vtotal = mode->vdisplay + vblank;
Dave Airlief453ba02008-11-07 14:05:41 -08002250
Jesse Barnes7064fef2009-11-05 10:12:54 -08002251 /* Some EDIDs have bogus h/vtotal values */
2252 if (mode->hsync_end > mode->htotal)
2253 mode->htotal = mode->hsync_end + 1;
2254 if (mode->vsync_end > mode->vtotal)
2255 mode->vtotal = mode->vsync_end + 1;
2256
Adam Jacksonb58db2c2010-02-15 22:15:39 +00002257 drm_mode_do_interlace_quirk(mode, pt);
Dave Airlief453ba02008-11-07 14:05:41 -08002258
2259 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
Michel Dänzer0454bea2009-06-15 16:56:07 +02002260 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
Dave Airlief453ba02008-11-07 14:05:41 -08002261 }
2262
Michel Dänzer0454bea2009-06-15 16:56:07 +02002263 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2264 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2265 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2266 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
Dave Airlief453ba02008-11-07 14:05:41 -08002267
Adam Jacksonbc42aab2012-05-23 16:26:54 -04002268set_size:
Michel Dänzere14cbee2009-06-23 12:36:32 +02002269 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2270 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
Dave Airlief453ba02008-11-07 14:05:41 -08002271
2272 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2273 mode->width_mm *= 10;
2274 mode->height_mm *= 10;
2275 }
2276
2277 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2278 mode->width_mm = edid->width_cm * 10;
2279 mode->height_mm = edid->height_cm * 10;
2280 }
2281
Adam Jacksonbc42aab2012-05-23 16:26:54 -04002282 mode->type = DRM_MODE_TYPE_DRIVER;
Torsten Duwec19b3b0f2013-03-23 15:39:34 +01002283 mode->vrefresh = drm_mode_vrefresh(mode);
Adam Jacksonbc42aab2012-05-23 16:26:54 -04002284 drm_mode_set_name(mode);
2285
Dave Airlief453ba02008-11-07 14:05:41 -08002286 return mode;
2287}
2288
Adam Jackson07a5e632009-12-03 17:44:38 -05002289static bool
Chris Wilsonb1f559e2011-01-26 09:49:47 +00002290mode_in_hsync_range(const struct drm_display_mode *mode,
2291 struct edid *edid, u8 *t)
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002292{
2293 int hsync, hmin, hmax;
Adam Jackson07a5e632009-12-03 17:44:38 -05002294
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002295 hmin = t[7];
2296 if (edid->revision >= 4)
2297 hmin += ((t[4] & 0x04) ? 255 : 0);
2298 hmax = t[8];
2299 if (edid->revision >= 4)
2300 hmax += ((t[4] & 0x08) ? 255 : 0);
Adam Jackson07a5e632009-12-03 17:44:38 -05002301 hsync = drm_mode_hsync(mode);
Adam Jackson07a5e632009-12-03 17:44:38 -05002302
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002303 return (hsync <= hmax && hsync >= hmin);
2304}
2305
2306static bool
Chris Wilsonb1f559e2011-01-26 09:49:47 +00002307mode_in_vsync_range(const struct drm_display_mode *mode,
2308 struct edid *edid, u8 *t)
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002309{
2310 int vsync, vmin, vmax;
2311
2312 vmin = t[5];
2313 if (edid->revision >= 4)
2314 vmin += ((t[4] & 0x01) ? 255 : 0);
2315 vmax = t[6];
2316 if (edid->revision >= 4)
2317 vmax += ((t[4] & 0x02) ? 255 : 0);
2318 vsync = drm_mode_vrefresh(mode);
2319
2320 return (vsync <= vmax && vsync >= vmin);
2321}
2322
2323static u32
2324range_pixel_clock(struct edid *edid, u8 *t)
2325{
2326 /* unspecified */
2327 if (t[9] == 0 || t[9] == 255)
2328 return 0;
2329
2330 /* 1.4 with CVT support gives us real precision, yay */
2331 if (edid->revision >= 4 && t[10] == 0x04)
2332 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2333
2334 /* 1.3 is pathetic, so fuzz up a bit */
2335 return t[9] * 10000 + 5001;
2336}
2337
Adam Jackson07a5e632009-12-03 17:44:38 -05002338static bool
Chris Wilsonb1f559e2011-01-26 09:49:47 +00002339mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002340 struct detailed_timing *timing)
Adam Jackson07a5e632009-12-03 17:44:38 -05002341{
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002342 u32 max_clock;
2343 u8 *t = (u8 *)timing;
Adam Jackson07a5e632009-12-03 17:44:38 -05002344
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002345 if (!mode_in_hsync_range(mode, edid, t))
Adam Jackson07a5e632009-12-03 17:44:38 -05002346 return false;
2347
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002348 if (!mode_in_vsync_range(mode, edid, t))
Adam Jackson07a5e632009-12-03 17:44:38 -05002349 return false;
2350
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002351 if ((max_clock = range_pixel_clock(edid, t)))
Adam Jackson07a5e632009-12-03 17:44:38 -05002352 if (mode->clock > max_clock)
2353 return false;
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002354
2355 /* 1.4 max horizontal check */
2356 if (edid->revision >= 4 && t[10] == 0x04)
2357 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2358 return false;
2359
2360 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2361 return false;
Adam Jackson07a5e632009-12-03 17:44:38 -05002362
2363 return true;
2364}
2365
Takashi Iwai7b668eb2012-07-03 11:22:11 +02002366static bool valid_inferred_mode(const struct drm_connector *connector,
2367 const struct drm_display_mode *mode)
2368{
Ville Syrjälä85f8fcd2015-09-07 18:22:56 +03002369 const struct drm_display_mode *m;
Takashi Iwai7b668eb2012-07-03 11:22:11 +02002370 bool ok = false;
2371
2372 list_for_each_entry(m, &connector->probed_modes, head) {
2373 if (mode->hdisplay == m->hdisplay &&
2374 mode->vdisplay == m->vdisplay &&
2375 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2376 return false; /* duplicated */
2377 if (mode->hdisplay <= m->hdisplay &&
2378 mode->vdisplay <= m->vdisplay)
2379 ok = true;
2380 }
2381 return ok;
2382}
2383
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002384static int
Adam Jacksoncd4cd3d2012-04-13 16:33:33 -04002385drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
Adam Jacksonb17e52e2010-03-29 21:43:27 +00002386 struct detailed_timing *timing)
Adam Jackson07a5e632009-12-03 17:44:38 -05002387{
2388 int i, modes = 0;
2389 struct drm_display_mode *newmode;
2390 struct drm_device *dev = connector->dev;
2391
Thierry Redinga6b21832012-11-23 15:01:42 +01002392 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
Takashi Iwai7b668eb2012-07-03 11:22:11 +02002393 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2394 valid_inferred_mode(connector, drm_dmt_modes + i)) {
Adam Jackson07a5e632009-12-03 17:44:38 -05002395 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2396 if (newmode) {
2397 drm_mode_probed_add(connector, newmode);
2398 modes++;
2399 }
2400 }
2401 }
2402
2403 return modes;
2404}
2405
Takashi Iwaic09dedb2012-04-23 17:40:33 +01002406/* fix up 1366x768 mode from 1368x768;
2407 * GFT/CVT can't express 1366 width which isn't dividable by 8
2408 */
Takashi Iwai969218f2017-01-17 17:43:29 +01002409void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
Takashi Iwaic09dedb2012-04-23 17:40:33 +01002410{
2411 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2412 mode->hdisplay = 1366;
2413 mode->hsync_start--;
2414 mode->hsync_end--;
2415 drm_mode_set_name(mode);
2416 }
2417}
2418
Adam Jacksonb309bd32012-04-13 16:33:40 -04002419static int
2420drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2421 struct detailed_timing *timing)
2422{
2423 int i, modes = 0;
2424 struct drm_display_mode *newmode;
2425 struct drm_device *dev = connector->dev;
2426
Thierry Redinga6b21832012-11-23 15:01:42 +01002427 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
Adam Jacksonb309bd32012-04-13 16:33:40 -04002428 const struct minimode *m = &extra_modes[i];
2429 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
Takashi Iwaifc48f162012-04-20 12:59:33 +01002430 if (!newmode)
2431 return modes;
Adam Jacksonb309bd32012-04-13 16:33:40 -04002432
Takashi Iwai969218f2017-01-17 17:43:29 +01002433 drm_mode_fixup_1366x768(newmode);
Takashi Iwai7b668eb2012-07-03 11:22:11 +02002434 if (!mode_in_range(newmode, edid, timing) ||
2435 !valid_inferred_mode(connector, newmode)) {
Adam Jacksonb309bd32012-04-13 16:33:40 -04002436 drm_mode_destroy(dev, newmode);
2437 continue;
2438 }
2439
2440 drm_mode_probed_add(connector, newmode);
2441 modes++;
2442 }
2443
2444 return modes;
2445}
2446
2447static int
2448drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2449 struct detailed_timing *timing)
2450{
2451 int i, modes = 0;
2452 struct drm_display_mode *newmode;
2453 struct drm_device *dev = connector->dev;
2454 bool rb = drm_monitor_supports_rb(edid);
2455
Thierry Redinga6b21832012-11-23 15:01:42 +01002456 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
Adam Jacksonb309bd32012-04-13 16:33:40 -04002457 const struct minimode *m = &extra_modes[i];
2458 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
Takashi Iwaifc48f162012-04-20 12:59:33 +01002459 if (!newmode)
2460 return modes;
Adam Jacksonb309bd32012-04-13 16:33:40 -04002461
Takashi Iwai969218f2017-01-17 17:43:29 +01002462 drm_mode_fixup_1366x768(newmode);
Takashi Iwai7b668eb2012-07-03 11:22:11 +02002463 if (!mode_in_range(newmode, edid, timing) ||
2464 !valid_inferred_mode(connector, newmode)) {
Adam Jacksonb309bd32012-04-13 16:33:40 -04002465 drm_mode_destroy(dev, newmode);
2466 continue;
2467 }
2468
2469 drm_mode_probed_add(connector, newmode);
2470 modes++;
2471 }
2472
2473 return modes;
2474}
2475
Adam Jackson13931572010-08-03 14:38:19 -04002476static void
2477do_inferred_modes(struct detailed_timing *timing, void *c)
Adam Jackson9340d8c2009-12-03 17:44:40 -05002478{
Adam Jackson13931572010-08-03 14:38:19 -04002479 struct detailed_mode_closure *closure = c;
2480 struct detailed_non_pixel *data = &timing->data.other_data;
Adam Jacksonb309bd32012-04-13 16:33:40 -04002481 struct detailed_data_monitor_range *range = &data->data.range;
Adam Jackson9340d8c2009-12-03 17:44:40 -05002482
Adam Jacksoncb21aaf2012-04-13 16:33:36 -04002483 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2484 return;
2485
2486 closure->modes += drm_dmt_modes_for_range(closure->connector,
2487 closure->edid,
2488 timing);
Adam Jacksonb309bd32012-04-13 16:33:40 -04002489
2490 if (!version_greater(closure->edid, 1, 1))
2491 return; /* GTF not defined yet */
2492
2493 switch (range->flags) {
2494 case 0x02: /* secondary gtf, XXX could do more */
2495 case 0x00: /* default gtf */
2496 closure->modes += drm_gtf_modes_for_range(closure->connector,
2497 closure->edid,
2498 timing);
2499 break;
2500 case 0x04: /* cvt, only in 1.4+ */
2501 if (!version_greater(closure->edid, 1, 3))
2502 break;
2503
2504 closure->modes += drm_cvt_modes_for_range(closure->connector,
2505 closure->edid,
2506 timing);
2507 break;
2508 case 0x01: /* just the ranges, no formula */
2509 default:
2510 break;
2511 }
Adam Jackson9340d8c2009-12-03 17:44:40 -05002512}
2513
Adam Jackson13931572010-08-03 14:38:19 -04002514static int
2515add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2516{
2517 struct detailed_mode_closure closure = {
Julia Lawalld456ea22014-08-23 18:09:56 +02002518 .connector = connector,
2519 .edid = edid,
Adam Jackson13931572010-08-03 14:38:19 -04002520 };
2521
2522 if (version_greater(edid, 1, 0))
2523 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2524 &closure);
2525
2526 return closure.modes;
2527}
2528
Adam Jackson2255be12010-03-29 21:43:22 +00002529static int
2530drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2531{
2532 int i, j, m, modes = 0;
2533 struct drm_display_mode *mode;
Paul Parsonsf3a32d72016-03-26 13:18:38 +00002534 u8 *est = ((u8 *)timing) + 6;
Adam Jackson2255be12010-03-29 21:43:22 +00002535
2536 for (i = 0; i < 6; i++) {
Ville Syrjälä891a7462013-10-14 16:44:26 +03002537 for (j = 7; j >= 0; j--) {
Adam Jackson2255be12010-03-29 21:43:22 +00002538 m = (i * 8) + (7 - j);
Linus Torvaldsaa9f56b2010-08-12 09:21:39 -07002539 if (m >= ARRAY_SIZE(est3_modes))
Adam Jackson2255be12010-03-29 21:43:22 +00002540 break;
2541 if (est[i] & (1 << j)) {
Dave Airlie1d42bbc2010-05-07 05:02:30 +00002542 mode = drm_mode_find_dmt(connector->dev,
2543 est3_modes[m].w,
2544 est3_modes[m].h,
Adam Jacksonf6e252b2012-04-13 16:33:31 -04002545 est3_modes[m].r,
2546 est3_modes[m].rb);
Adam Jackson2255be12010-03-29 21:43:22 +00002547 if (mode) {
2548 drm_mode_probed_add(connector, mode);
2549 modes++;
2550 }
2551 }
2552 }
2553 }
2554
2555 return modes;
2556}
2557
Adam Jackson13931572010-08-03 14:38:19 -04002558static void
2559do_established_modes(struct detailed_timing *timing, void *c)
Adam Jackson9cf00972009-12-03 17:44:36 -05002560{
Adam Jackson13931572010-08-03 14:38:19 -04002561 struct detailed_mode_closure *closure = c;
Adam Jackson9cf00972009-12-03 17:44:36 -05002562 struct detailed_non_pixel *data = &timing->data.other_data;
Adam Jackson13931572010-08-03 14:38:19 -04002563
2564 if (data->type == EDID_DETAIL_EST_TIMINGS)
2565 closure->modes += drm_est3_modes(closure->connector, timing);
2566}
2567
2568/**
2569 * add_established_modes - get est. modes from EDID and add them
Thierry Redingdb6cf8332014-04-29 11:44:34 +02002570 * @connector: connector to add mode(s) to
Adam Jackson13931572010-08-03 14:38:19 -04002571 * @edid: EDID block to scan
2572 *
2573 * Each EDID block contains a bitmap of the supported "established modes" list
2574 * (defined above). Tease them out and add them to the global modes list.
2575 */
2576static int
2577add_established_modes(struct drm_connector *connector, struct edid *edid)
2578{
Adam Jackson9cf00972009-12-03 17:44:36 -05002579 struct drm_device *dev = connector->dev;
Adam Jackson13931572010-08-03 14:38:19 -04002580 unsigned long est_bits = edid->established_timings.t1 |
2581 (edid->established_timings.t2 << 8) |
2582 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2583 int i, modes = 0;
2584 struct detailed_mode_closure closure = {
Julia Lawalld456ea22014-08-23 18:09:56 +02002585 .connector = connector,
2586 .edid = edid,
Adam Jackson13931572010-08-03 14:38:19 -04002587 };
Adam Jackson9cf00972009-12-03 17:44:36 -05002588
Adam Jackson13931572010-08-03 14:38:19 -04002589 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2590 if (est_bits & (1<<i)) {
2591 struct drm_display_mode *newmode;
2592 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2593 if (newmode) {
2594 drm_mode_probed_add(connector, newmode);
2595 modes++;
2596 }
2597 }
Adam Jackson9cf00972009-12-03 17:44:36 -05002598 }
2599
Adam Jackson13931572010-08-03 14:38:19 -04002600 if (version_greater(edid, 1, 0))
2601 drm_for_each_detailed_block((u8 *)edid,
2602 do_established_modes, &closure);
2603
2604 return modes + closure.modes;
2605}
2606
2607static void
2608do_standard_modes(struct detailed_timing *timing, void *c)
2609{
2610 struct detailed_mode_closure *closure = c;
2611 struct detailed_non_pixel *data = &timing->data.other_data;
2612 struct drm_connector *connector = closure->connector;
2613 struct edid *edid = closure->edid;
2614
2615 if (data->type == EDID_DETAIL_STD_MODES) {
2616 int i;
Adam Jackson9cf00972009-12-03 17:44:36 -05002617 for (i = 0; i < 6; i++) {
2618 struct std_timing *std;
2619 struct drm_display_mode *newmode;
2620
2621 std = &data->data.timings[i];
Thierry Reding464fdec2014-04-29 11:44:33 +02002622 newmode = drm_mode_std(connector, edid, std);
Adam Jackson9cf00972009-12-03 17:44:36 -05002623 if (newmode) {
2624 drm_mode_probed_add(connector, newmode);
Adam Jackson13931572010-08-03 14:38:19 -04002625 closure->modes++;
Adam Jackson9cf00972009-12-03 17:44:36 -05002626 }
2627 }
Adam Jackson13931572010-08-03 14:38:19 -04002628 }
2629}
2630
2631/**
2632 * add_standard_modes - get std. modes from EDID and add them
Thierry Redingdb6cf8332014-04-29 11:44:34 +02002633 * @connector: connector to add mode(s) to
Adam Jackson13931572010-08-03 14:38:19 -04002634 * @edid: EDID block to scan
2635 *
2636 * Standard modes can be calculated using the appropriate standard (DMT,
2637 * GTF or CVT. Grab them from @edid and add them to the list.
2638 */
2639static int
2640add_standard_modes(struct drm_connector *connector, struct edid *edid)
2641{
2642 int i, modes = 0;
2643 struct detailed_mode_closure closure = {
Julia Lawalld456ea22014-08-23 18:09:56 +02002644 .connector = connector,
2645 .edid = edid,
Adam Jackson13931572010-08-03 14:38:19 -04002646 };
2647
2648 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2649 struct drm_display_mode *newmode;
2650
2651 newmode = drm_mode_std(connector, edid,
Thierry Reding464fdec2014-04-29 11:44:33 +02002652 &edid->standard_timings[i]);
Adam Jackson13931572010-08-03 14:38:19 -04002653 if (newmode) {
2654 drm_mode_probed_add(connector, newmode);
2655 modes++;
2656 }
2657 }
2658
2659 if (version_greater(edid, 1, 0))
2660 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2661 &closure);
2662
2663 /* XXX should also look for standard codes in VTB blocks */
2664
2665 return modes + closure.modes;
2666}
2667
Dave Airlief453ba02008-11-07 14:05:41 -08002668static int drm_cvt_modes(struct drm_connector *connector,
2669 struct detailed_timing *timing)
2670{
2671 int i, j, modes = 0;
2672 struct drm_display_mode *newmode;
2673 struct drm_device *dev = connector->dev;
Zhao Yakui5c612592009-06-22 13:17:10 +08002674 struct cvt_timing *cvt;
2675 const int rates[] = { 60, 85, 75, 60, 50 };
2676 const u8 empty[3] = { 0, 0, 0 };
Dave Airlief453ba02008-11-07 14:05:41 -08002677
2678 for (i = 0; i < 4; i++) {
2679 int uninitialized_var(width), height;
2680 cvt = &(timing->data.other_data.data.cvt[i]);
2681
2682 if (!memcmp(cvt->code, empty, 3))
Michel Dänzer0454bea2009-06-15 16:56:07 +02002683 continue;
Dave Airlief453ba02008-11-07 14:05:41 -08002684
2685 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
Zhao Yakui5c612592009-06-22 13:17:10 +08002686 switch (cvt->code[1] & 0x0c) {
Adam Jacksonf066a172009-09-23 17:31:21 -04002687 case 0x00:
Dave Airlief453ba02008-11-07 14:05:41 -08002688 width = height * 4 / 3;
2689 break;
2690 case 0x04:
2691 width = height * 16 / 9;
2692 break;
2693 case 0x08:
2694 width = height * 16 / 10;
2695 break;
2696 case 0x0c:
Dave Airlief453ba02008-11-07 14:05:41 -08002697 width = height * 15 / 9;
2698 break;
2699 }
2700
2701 for (j = 1; j < 5; j++) {
2702 if (cvt->code[2] & (1 << j)) {
2703 newmode = drm_cvt_mode(dev, width, height,
2704 rates[j], j == 0,
2705 false, false);
2706 if (newmode) {
2707 drm_mode_probed_add(connector, newmode);
2708 modes++;
2709 }
2710 }
2711 }
2712 }
2713
2714 return modes;
2715}
2716
Adam Jackson13931572010-08-03 14:38:19 -04002717static void
2718do_cvt_mode(struct detailed_timing *timing, void *c)
2719{
2720 struct detailed_mode_closure *closure = c;
2721 struct detailed_non_pixel *data = &timing->data.other_data;
2722
2723 if (data->type == EDID_DETAIL_CVT_3BYTE)
2724 closure->modes += drm_cvt_modes(closure->connector, timing);
2725}
Adam Jackson9cf00972009-12-03 17:44:36 -05002726
2727static int
Adam Jackson13931572010-08-03 14:38:19 -04002728add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2729{
2730 struct detailed_mode_closure closure = {
Julia Lawalld456ea22014-08-23 18:09:56 +02002731 .connector = connector,
2732 .edid = edid,
Adam Jackson13931572010-08-03 14:38:19 -04002733 };
Adam Jackson9cf00972009-12-03 17:44:36 -05002734
Adam Jackson13931572010-08-03 14:38:19 -04002735 if (version_greater(edid, 1, 2))
2736 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
Dave Airlief453ba02008-11-07 14:05:41 -08002737
Adam Jackson13931572010-08-03 14:38:19 -04002738 /* XXX should also look for CVT codes in VTB blocks */
2739
2740 return closure.modes;
Dave Airlief453ba02008-11-07 14:05:41 -08002741}
2742
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03002743static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2744
Adam Jackson13931572010-08-03 14:38:19 -04002745static void
2746do_detailed_mode(struct detailed_timing *timing, void *c)
Dave Airlief453ba02008-11-07 14:05:41 -08002747{
Adam Jackson13931572010-08-03 14:38:19 -04002748 struct detailed_mode_closure *closure = c;
Dave Airlief453ba02008-11-07 14:05:41 -08002749 struct drm_display_mode *newmode;
Adam Jackson9cf00972009-12-03 17:44:36 -05002750
2751 if (timing->pixel_clock) {
Adam Jackson13931572010-08-03 14:38:19 -04002752 newmode = drm_mode_detailed(closure->connector->dev,
2753 closure->edid, timing,
2754 closure->quirks);
Dave Airlief453ba02008-11-07 14:05:41 -08002755 if (!newmode)
Adam Jackson13931572010-08-03 14:38:19 -04002756 return;
Adam Jackson9cf00972009-12-03 17:44:36 -05002757
Adam Jackson13931572010-08-03 14:38:19 -04002758 if (closure->preferred)
Dave Airlief453ba02008-11-07 14:05:41 -08002759 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2760
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03002761 /*
2762 * Detailed modes are limited to 10kHz pixel clock resolution,
2763 * so fix up anything that looks like CEA/HDMI mode, but the clock
2764 * is just slightly off.
2765 */
2766 fixup_detailed_cea_mode_clock(newmode);
2767
Adam Jackson13931572010-08-03 14:38:19 -04002768 drm_mode_probed_add(closure->connector, newmode);
2769 closure->modes++;
Gustavo A. R. Silvac2925bd2018-01-30 04:05:28 -06002770 closure->preferred = false;
Zhao Yakui882f0212009-08-26 18:20:49 +08002771 }
Ma Ling167f3a02009-03-20 14:09:48 +08002772}
2773
Adam Jackson13931572010-08-03 14:38:19 -04002774/*
2775 * add_detailed_modes - Add modes from detailed timings
Dave Airlief453ba02008-11-07 14:05:41 -08002776 * @connector: attached connector
2777 * @edid: EDID block to scan
2778 * @quirks: quirks to apply
Dave Airlief453ba02008-11-07 14:05:41 -08002779 */
Adam Jackson13931572010-08-03 14:38:19 -04002780static int
2781add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2782 u32 quirks)
Dave Airlief453ba02008-11-07 14:05:41 -08002783{
Adam Jackson13931572010-08-03 14:38:19 -04002784 struct detailed_mode_closure closure = {
Julia Lawalld456ea22014-08-23 18:09:56 +02002785 .connector = connector,
2786 .edid = edid,
Gustavo A. R. Silvac2925bd2018-01-30 04:05:28 -06002787 .preferred = true,
Julia Lawalld456ea22014-08-23 18:09:56 +02002788 .quirks = quirks,
Adam Jackson13931572010-08-03 14:38:19 -04002789 };
Dave Airlief453ba02008-11-07 14:05:41 -08002790
Adam Jackson13931572010-08-03 14:38:19 -04002791 if (closure.preferred && !version_greater(edid, 1, 3))
2792 closure.preferred =
2793 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
Adam Jacksona327f6b2010-03-29 21:43:25 +00002794
Adam Jackson13931572010-08-03 14:38:19 -04002795 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
Dave Airlief453ba02008-11-07 14:05:41 -08002796
Adam Jackson13931572010-08-03 14:38:19 -04002797 return closure.modes;
Zhao Yakui882f0212009-08-26 18:20:49 +08002798}
Dave Airlief453ba02008-11-07 14:05:41 -08002799
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002800#define AUDIO_BLOCK 0x01
Christian Schmidt54ac76f2011-12-19 14:53:16 +00002801#define VIDEO_BLOCK 0x02
Ma Lingf23c20c2009-03-26 19:26:23 +08002802#define VENDOR_BLOCK 0x03
Wu Fengguang76adaa342011-09-05 14:23:20 +08002803#define SPEAKER_BLOCK 0x04
Shashank Sharma87563fc2017-07-13 21:03:10 +05302804#define USE_EXTENDED_TAG 0x07
2805#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
Shashank Sharma832d4f22017-07-14 16:03:46 +05302806#define EXT_VIDEO_DATA_BLOCK_420 0x0E
2807#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002808#define EDID_BASIC_AUDIO (1 << 6)
Lars-Peter Clausena988bc72012-04-16 15:16:19 +02002809#define EDID_CEA_YCRCB444 (1 << 5)
2810#define EDID_CEA_YCRCB422 (1 << 4)
Ville Syrjäläb1edd6a2013-01-17 16:31:30 +02002811#define EDID_CEA_VCDB_QS (1 << 6)
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002812
Lespiau, Damiend4e4a312013-08-19 16:58:52 +01002813/*
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002814 * Search EDID for CEA extension block.
2815 */
Keith Packard170178f2017-12-13 00:44:26 -08002816static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002817{
2818 u8 *edid_ext = NULL;
2819 int i;
2820
2821 /* No EDID or EDID extensions */
2822 if (edid == NULL || edid->extensions == 0)
2823 return NULL;
2824
2825 /* Find CEA extension */
2826 for (i = 0; i < edid->extensions; i++) {
2827 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
Dave Airlie40d9b042014-10-20 16:29:33 +10002828 if (edid_ext[0] == ext_id)
Zhenyu Wang8fe97902010-09-19 14:27:28 +08002829 break;
2830 }
2831
2832 if (i == edid->extensions)
2833 return NULL;
2834
2835 return edid_ext;
2836}
2837
Keith Packard170178f2017-12-13 00:44:26 -08002838static u8 *drm_find_cea_extension(const struct edid *edid)
Dave Airlie40d9b042014-10-20 16:29:33 +10002839{
2840 return drm_find_edid_extension(edid, CEA_EXT);
2841}
2842
Keith Packard170178f2017-12-13 00:44:26 -08002843static u8 *drm_find_displayid_extension(const struct edid *edid)
Dave Airlie40d9b042014-10-20 16:29:33 +10002844{
2845 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2846}
2847
Ville Syrjäläe6e79202013-05-31 15:23:41 +03002848/*
2849 * Calculate the alternate clock for the CEA mode
2850 * (60Hz vs. 59.94Hz etc.)
2851 */
2852static unsigned int
2853cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2854{
2855 unsigned int clock = cea_mode->clock;
2856
2857 if (cea_mode->vrefresh % 6 != 0)
2858 return clock;
2859
2860 /*
2861 * edid_cea_modes contains the 59.94Hz
2862 * variant for 240 and 480 line modes,
2863 * and the 60Hz variant otherwise.
2864 */
2865 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
Ville Syrjälä9afd8082015-10-08 11:43:33 +03002866 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
Ville Syrjäläe6e79202013-05-31 15:23:41 +03002867 else
Ville Syrjälä9afd8082015-10-08 11:43:33 +03002868 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
Ville Syrjäläe6e79202013-05-31 15:23:41 +03002869
2870 return clock;
2871}
2872
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002873static bool
2874cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2875{
2876 /*
2877 * For certain VICs the spec allows the vertical
2878 * front porch to vary by one or two lines.
2879 *
2880 * cea_modes[] stores the variant with the shortest
2881 * vertical front porch. We can adjust the mode to
2882 * get the other variants by simply increasing the
2883 * vertical front porch length.
2884 */
2885 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2886 edid_cea_modes[9].vtotal != 262 ||
2887 edid_cea_modes[12].vtotal != 262 ||
2888 edid_cea_modes[13].vtotal != 262 ||
2889 edid_cea_modes[23].vtotal != 312 ||
2890 edid_cea_modes[24].vtotal != 312 ||
2891 edid_cea_modes[27].vtotal != 312 ||
2892 edid_cea_modes[28].vtotal != 312);
2893
2894 if (((vic == 8 || vic == 9 ||
2895 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2896 ((vic == 23 || vic == 24 ||
2897 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2898 mode->vsync_start++;
2899 mode->vsync_end++;
2900 mode->vtotal++;
2901
2902 return true;
2903 }
2904
2905 return false;
2906}
2907
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02002908static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2909 unsigned int clock_tolerance)
2910{
Jani Nikulad9278b42016-01-08 13:21:51 +02002911 u8 vic;
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02002912
2913 if (!to_match->clock)
2914 return 0;
2915
Jani Nikulad9278b42016-01-08 13:21:51 +02002916 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002917 struct drm_display_mode cea_mode = edid_cea_modes[vic];
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02002918 unsigned int clock1, clock2;
2919
2920 /* Check both 60Hz and 59.94Hz */
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002921 clock1 = cea_mode.clock;
2922 clock2 = cea_mode_alternate_clock(&cea_mode);
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02002923
2924 if (abs(to_match->clock - clock1) > clock_tolerance &&
2925 abs(to_match->clock - clock2) > clock_tolerance)
2926 continue;
2927
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002928 do {
2929 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2930 return vic;
2931 } while (cea_mode_alternate_timings(vic, &cea_mode));
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02002932 }
2933
2934 return 0;
2935}
2936
Thierry Reding18316c82012-12-20 15:41:44 +01002937/**
2938 * drm_match_cea_mode - look for a CEA mode matching given mode
2939 * @to_match: display mode
2940 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02002941 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
Thierry Reding18316c82012-12-20 15:41:44 +01002942 * mode.
Stephane Marchesina4799032012-11-09 16:21:05 +00002943 */
Thierry Reding18316c82012-12-20 15:41:44 +01002944u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
Stephane Marchesina4799032012-11-09 16:21:05 +00002945{
Jani Nikulad9278b42016-01-08 13:21:51 +02002946 u8 vic;
Stephane Marchesina4799032012-11-09 16:21:05 +00002947
Ville Syrjäläa90b5902013-04-24 19:07:18 +03002948 if (!to_match->clock)
2949 return 0;
Stephane Marchesina4799032012-11-09 16:21:05 +00002950
Jani Nikulad9278b42016-01-08 13:21:51 +02002951 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002952 struct drm_display_mode cea_mode = edid_cea_modes[vic];
Ville Syrjäläa90b5902013-04-24 19:07:18 +03002953 unsigned int clock1, clock2;
2954
Ville Syrjäläa90b5902013-04-24 19:07:18 +03002955 /* Check both 60Hz and 59.94Hz */
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002956 clock1 = cea_mode.clock;
2957 clock2 = cea_mode_alternate_clock(&cea_mode);
Ville Syrjäläa90b5902013-04-24 19:07:18 +03002958
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002959 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2960 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2961 continue;
2962
2963 do {
2964 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2965 return vic;
2966 } while (cea_mode_alternate_timings(vic, &cea_mode));
Stephane Marchesina4799032012-11-09 16:21:05 +00002967 }
Ville Syrjäläc45a4e42016-11-03 14:53:29 +02002968
Stephane Marchesina4799032012-11-09 16:21:05 +00002969 return 0;
2970}
2971EXPORT_SYMBOL(drm_match_cea_mode);
2972
Jani Nikulad9278b42016-01-08 13:21:51 +02002973static bool drm_valid_cea_vic(u8 vic)
2974{
2975 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2976}
2977
Vandana Kannan0967e6a2014-04-01 16:26:59 +05302978/**
2979 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2980 * the input VIC from the CEA mode list
2981 * @video_code: ID given to each of the CEA modes
2982 *
2983 * Returns picture aspect ratio
2984 */
2985enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2986{
Jani Nikulad9278b42016-01-08 13:21:51 +02002987 return edid_cea_modes[video_code].picture_aspect_ratio;
Vandana Kannan0967e6a2014-04-01 16:26:59 +05302988}
2989EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2990
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01002991/*
2992 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2993 * specific block).
2994 *
2995 * It's almost like cea_mode_alternate_clock(), we just need to add an
2996 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2997 * one.
2998 */
2999static unsigned int
3000hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3001{
3002 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3003 return hdmi_mode->clock;
3004
3005 return cea_mode_alternate_clock(hdmi_mode);
3006}
3007
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02003008static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3009 unsigned int clock_tolerance)
3010{
Jani Nikulad9278b42016-01-08 13:21:51 +02003011 u8 vic;
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02003012
3013 if (!to_match->clock)
3014 return 0;
3015
Jani Nikulad9278b42016-01-08 13:21:51 +02003016 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3017 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02003018 unsigned int clock1, clock2;
3019
3020 /* Make sure to also match alternate clocks */
3021 clock1 = hdmi_mode->clock;
3022 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3023
3024 if (abs(to_match->clock - clock1) > clock_tolerance &&
3025 abs(to_match->clock - clock2) > clock_tolerance)
3026 continue;
3027
3028 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
Jani Nikulad9278b42016-01-08 13:21:51 +02003029 return vic;
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02003030 }
3031
3032 return 0;
3033}
3034
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003035/*
3036 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3037 * @to_match: display mode
3038 *
3039 * An HDMI mode is one defined in the HDMI vendor specific block.
3040 *
3041 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3042 */
3043static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3044{
Jani Nikulad9278b42016-01-08 13:21:51 +02003045 u8 vic;
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003046
3047 if (!to_match->clock)
3048 return 0;
3049
Jani Nikulad9278b42016-01-08 13:21:51 +02003050 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3051 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003052 unsigned int clock1, clock2;
3053
3054 /* Make sure to also match alternate clocks */
3055 clock1 = hdmi_mode->clock;
3056 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3057
3058 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3059 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
Damien Lespiauf2ecf2e32013-09-25 16:45:27 +01003060 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
Jani Nikulad9278b42016-01-08 13:21:51 +02003061 return vic;
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003062 }
3063 return 0;
3064}
3065
Jani Nikulad9278b42016-01-08 13:21:51 +02003066static bool drm_valid_hdmi_vic(u8 vic)
3067{
3068 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3069}
3070
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003071static int
3072add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3073{
3074 struct drm_device *dev = connector->dev;
3075 struct drm_display_mode *mode, *tmp;
3076 LIST_HEAD(list);
3077 int modes = 0;
3078
3079 /* Don't add CEA modes if the CEA extension block is missing */
3080 if (!drm_find_cea_extension(edid))
3081 return 0;
3082
3083 /*
3084 * Go through all probed modes and create a new mode
3085 * with the alternate clock for certain CEA modes.
3086 */
3087 list_for_each_entry(mode, &connector->probed_modes, head) {
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003088 const struct drm_display_mode *cea_mode = NULL;
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003089 struct drm_display_mode *newmode;
Jani Nikulad9278b42016-01-08 13:21:51 +02003090 u8 vic = drm_match_cea_mode(mode);
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003091 unsigned int clock1, clock2;
3092
Jani Nikulad9278b42016-01-08 13:21:51 +02003093 if (drm_valid_cea_vic(vic)) {
3094 cea_mode = &edid_cea_modes[vic];
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003095 clock2 = cea_mode_alternate_clock(cea_mode);
3096 } else {
Jani Nikulad9278b42016-01-08 13:21:51 +02003097 vic = drm_match_hdmi_mode(mode);
3098 if (drm_valid_hdmi_vic(vic)) {
3099 cea_mode = &edid_4k_modes[vic];
Lespiau, Damien3f2f6532013-08-19 16:58:55 +01003100 clock2 = hdmi_mode_alternate_clock(cea_mode);
3101 }
3102 }
3103
3104 if (!cea_mode)
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003105 continue;
3106
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003107 clock1 = cea_mode->clock;
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003108
3109 if (clock1 == clock2)
3110 continue;
3111
3112 if (mode->clock != clock1 && mode->clock != clock2)
3113 continue;
3114
3115 newmode = drm_mode_duplicate(dev, cea_mode);
3116 if (!newmode)
3117 continue;
3118
Damien Lespiau27130212013-09-25 16:45:28 +01003119 /* Carry over the stereo flags */
3120 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3121
Ville Syrjäläe6e79202013-05-31 15:23:41 +03003122 /*
3123 * The current mode could be either variant. Make
3124 * sure to pick the "other" clock for the new mode.
3125 */
3126 if (mode->clock != clock1)
3127 newmode->clock = clock1;
3128 else
3129 newmode->clock = clock2;
3130
3131 list_add_tail(&newmode->head, &list);
3132 }
3133
3134 list_for_each_entry_safe(mode, tmp, &list, head) {
3135 list_del(&mode->head);
3136 drm_mode_probed_add(connector, mode);
3137 modes++;
3138 }
3139
3140 return modes;
3141}
Stephane Marchesina4799032012-11-09 16:21:05 +00003142
Shashank Sharma8ec6e072017-07-13 21:03:08 +05303143static u8 svd_to_vic(u8 svd)
3144{
3145 /* 0-6 bit vic, 7th bit native mode indicator */
3146 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3147 return svd & 127;
3148
3149 return svd;
3150}
3151
Thomas Woodaff04ac2013-11-29 15:33:27 +00003152static struct drm_display_mode *
3153drm_display_mode_from_vic_index(struct drm_connector *connector,
3154 const u8 *video_db, u8 video_len,
3155 u8 video_index)
3156{
3157 struct drm_device *dev = connector->dev;
3158 struct drm_display_mode *newmode;
Jani Nikulad9278b42016-01-08 13:21:51 +02003159 u8 vic;
Thomas Woodaff04ac2013-11-29 15:33:27 +00003160
3161 if (video_db == NULL || video_index >= video_len)
3162 return NULL;
3163
3164 /* CEA modes are numbered 1..127 */
Shashank Sharma8ec6e072017-07-13 21:03:08 +05303165 vic = svd_to_vic(video_db[video_index]);
Jani Nikulad9278b42016-01-08 13:21:51 +02003166 if (!drm_valid_cea_vic(vic))
Thomas Woodaff04ac2013-11-29 15:33:27 +00003167 return NULL;
3168
Jani Nikulad9278b42016-01-08 13:21:51 +02003169 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
Damien Lespiau409bbf12014-03-03 23:59:07 +00003170 if (!newmode)
3171 return NULL;
3172
Thomas Woodaff04ac2013-11-29 15:33:27 +00003173 newmode->vrefresh = 0;
3174
3175 return newmode;
3176}
3177
Shashank Sharma832d4f22017-07-14 16:03:46 +05303178/*
3179 * do_y420vdb_modes - Parse YCBCR 420 only modes
3180 * @connector: connector corresponding to the HDMI sink
3181 * @svds: start of the data block of CEA YCBCR 420 VDB
3182 * @len: length of the CEA YCBCR 420 VDB
3183 *
3184 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3185 * which contains modes which can be supported in YCBCR 420
3186 * output format only.
3187 */
3188static int do_y420vdb_modes(struct drm_connector *connector,
3189 const u8 *svds, u8 svds_len)
3190{
3191 int modes = 0, i;
3192 struct drm_device *dev = connector->dev;
3193 struct drm_display_info *info = &connector->display_info;
3194 struct drm_hdmi_info *hdmi = &info->hdmi;
3195
3196 for (i = 0; i < svds_len; i++) {
3197 u8 vic = svd_to_vic(svds[i]);
3198 struct drm_display_mode *newmode;
3199
3200 if (!drm_valid_cea_vic(vic))
3201 continue;
3202
3203 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3204 if (!newmode)
3205 break;
3206 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3207 drm_mode_probed_add(connector, newmode);
3208 modes++;
3209 }
3210
3211 if (modes > 0)
3212 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3213 return modes;
3214}
3215
3216/*
3217 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3218 * @connector: connector corresponding to the HDMI sink
3219 * @vic: CEA vic for the video mode to be added in the map
3220 *
3221 * Makes an entry for a videomode in the YCBCR 420 bitmap
3222 */
3223static void
3224drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3225{
3226 u8 vic = svd_to_vic(svd);
3227 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3228
3229 if (!drm_valid_cea_vic(vic))
3230 return;
3231
3232 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3233}
3234
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003235static int
Lespiau, Damien13ac3f52013-08-19 16:58:53 +01003236do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003237{
Thomas Woodaff04ac2013-11-29 15:33:27 +00003238 int i, modes = 0;
Shashank Sharma832d4f22017-07-14 16:03:46 +05303239 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003240
Thomas Woodaff04ac2013-11-29 15:33:27 +00003241 for (i = 0; i < len; i++) {
3242 struct drm_display_mode *mode;
3243 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3244 if (mode) {
Shashank Sharma832d4f22017-07-14 16:03:46 +05303245 /*
3246 * YCBCR420 capability block contains a bitmap which
3247 * gives the index of CEA modes from CEA VDB, which
3248 * can support YCBCR 420 sampling output also (apart
3249 * from RGB/YCBCR444 etc).
3250 * For example, if the bit 0 in bitmap is set,
3251 * first mode in VDB can support YCBCR420 output too.
3252 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3253 */
3254 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3255 drm_add_cmdb_modes(connector, db[i]);
3256
Thomas Woodaff04ac2013-11-29 15:33:27 +00003257 drm_mode_probed_add(connector, mode);
3258 modes++;
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003259 }
3260 }
3261
3262 return modes;
3263}
3264
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003265struct stereo_mandatory_mode {
3266 int width, height, vrefresh;
3267 unsigned int flags;
3268};
3269
3270static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003271 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3272 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003273 { 1920, 1080, 50,
3274 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3275 { 1920, 1080, 60,
3276 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003277 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3278 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3279 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3280 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003281};
3282
3283static bool
3284stereo_match_mandatory(const struct drm_display_mode *mode,
3285 const struct stereo_mandatory_mode *stereo_mode)
3286{
3287 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3288
3289 return mode->hdisplay == stereo_mode->width &&
3290 mode->vdisplay == stereo_mode->height &&
3291 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3292 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3293}
3294
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003295static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3296{
3297 struct drm_device *dev = connector->dev;
3298 const struct drm_display_mode *mode;
3299 struct list_head stereo_modes;
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003300 int modes = 0, i;
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003301
3302 INIT_LIST_HEAD(&stereo_modes);
3303
3304 list_for_each_entry(mode, &connector->probed_modes, head) {
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003305 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3306 const struct stereo_mandatory_mode *mandatory;
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003307 struct drm_display_mode *new_mode;
3308
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003309 if (!stereo_match_mandatory(mode,
3310 &stereo_mandatory_modes[i]))
3311 continue;
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003312
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003313 mandatory = &stereo_mandatory_modes[i];
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003314 new_mode = drm_mode_duplicate(dev, mode);
3315 if (!new_mode)
3316 continue;
3317
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003318 new_mode->flags |= mandatory->flags;
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003319 list_add_tail(&new_mode->head, &stereo_modes);
3320 modes++;
Damien Lespiauf7e121b2013-09-27 12:11:48 +01003321 }
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003322 }
3323
3324 list_splice_tail(&stereo_modes, &connector->probed_modes);
3325
3326 return modes;
3327}
3328
Damien Lespiau1deee8d2013-09-25 16:45:24 +01003329static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3330{
3331 struct drm_device *dev = connector->dev;
3332 struct drm_display_mode *newmode;
3333
Jani Nikulad9278b42016-01-08 13:21:51 +02003334 if (!drm_valid_hdmi_vic(vic)) {
Damien Lespiau1deee8d2013-09-25 16:45:24 +01003335 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3336 return 0;
3337 }
3338
3339 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3340 if (!newmode)
3341 return 0;
3342
3343 drm_mode_probed_add(connector, newmode);
3344
3345 return 1;
3346}
3347
Thomas Woodfbf46022013-10-16 15:58:50 +01003348static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3349 const u8 *video_db, u8 video_len, u8 video_index)
3350{
Thomas Woodfbf46022013-10-16 15:58:50 +01003351 struct drm_display_mode *newmode;
3352 int modes = 0;
Thomas Woodfbf46022013-10-16 15:58:50 +01003353
3354 if (structure & (1 << 0)) {
Thomas Woodaff04ac2013-11-29 15:33:27 +00003355 newmode = drm_display_mode_from_vic_index(connector, video_db,
3356 video_len,
3357 video_index);
Thomas Woodfbf46022013-10-16 15:58:50 +01003358 if (newmode) {
3359 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3360 drm_mode_probed_add(connector, newmode);
3361 modes++;
3362 }
3363 }
3364 if (structure & (1 << 6)) {
Thomas Woodaff04ac2013-11-29 15:33:27 +00003365 newmode = drm_display_mode_from_vic_index(connector, video_db,
3366 video_len,
3367 video_index);
Thomas Woodfbf46022013-10-16 15:58:50 +01003368 if (newmode) {
3369 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3370 drm_mode_probed_add(connector, newmode);
3371 modes++;
3372 }
3373 }
3374 if (structure & (1 << 8)) {
Thomas Woodaff04ac2013-11-29 15:33:27 +00003375 newmode = drm_display_mode_from_vic_index(connector, video_db,
3376 video_len,
3377 video_index);
Thomas Woodfbf46022013-10-16 15:58:50 +01003378 if (newmode) {
Thomas Wood89570ee2013-11-28 15:35:04 +00003379 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
Thomas Woodfbf46022013-10-16 15:58:50 +01003380 drm_mode_probed_add(connector, newmode);
3381 modes++;
3382 }
3383 }
3384
3385 return modes;
3386}
3387
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003388/*
3389 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3390 * @connector: connector corresponding to the HDMI sink
3391 * @db: start of the CEA vendor specific block
3392 * @len: length of the CEA block payload, ie. one can access up to db[len]
3393 *
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003394 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3395 * also adds the stereo 3d modes when applicable.
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003396 */
3397static int
Thomas Woodfbf46022013-10-16 15:58:50 +01003398do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3399 const u8 *video_db, u8 video_len)
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003400{
Ville Syrjäläf1781e92017-11-13 19:04:19 +02003401 struct drm_display_info *info = &connector->display_info;
Thomas Wood0e5083aa2013-11-29 18:18:58 +00003402 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
Thomas Woodfbf46022013-10-16 15:58:50 +01003403 u8 vic_len, hdmi_3d_len = 0;
3404 u16 mask;
3405 u16 structure_all;
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003406
3407 if (len < 8)
3408 goto out;
3409
3410 /* no HDMI_Video_Present */
3411 if (!(db[8] & (1 << 5)))
3412 goto out;
3413
3414 /* Latency_Fields_Present */
3415 if (db[8] & (1 << 7))
3416 offset += 2;
3417
3418 /* I_Latency_Fields_Present */
3419 if (db[8] & (1 << 6))
3420 offset += 2;
3421
3422 /* the declared length is not long enough for the 2 first bytes
3423 * of additional video format capabilities */
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003424 if (len < (8 + offset + 2))
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003425 goto out;
3426
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003427 /* 3D_Present */
3428 offset++;
Thomas Woodfbf46022013-10-16 15:58:50 +01003429 if (db[8 + offset] & (1 << 7)) {
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003430 modes += add_hdmi_mandatory_stereo_modes(connector);
3431
Thomas Woodfbf46022013-10-16 15:58:50 +01003432 /* 3D_Multi_present */
3433 multi_present = (db[8 + offset] & 0x60) >> 5;
3434 }
3435
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003436 offset++;
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003437 vic_len = db[8 + offset] >> 5;
Thomas Woodfbf46022013-10-16 15:58:50 +01003438 hdmi_3d_len = db[8 + offset] & 0x1f;
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003439
3440 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003441 u8 vic;
3442
3443 vic = db[9 + offset + i];
Damien Lespiau1deee8d2013-09-25 16:45:24 +01003444 modes += add_hdmi_mode(connector, vic);
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003445 }
Thomas Woodfbf46022013-10-16 15:58:50 +01003446 offset += 1 + vic_len;
3447
Thomas Wood0e5083aa2013-11-29 18:18:58 +00003448 if (multi_present == 1)
3449 multi_len = 2;
3450 else if (multi_present == 2)
3451 multi_len = 4;
Thomas Woodfbf46022013-10-16 15:58:50 +01003452 else
Thomas Wood0e5083aa2013-11-29 18:18:58 +00003453 multi_len = 0;
Thomas Woodfbf46022013-10-16 15:58:50 +01003454
Thomas Wood0e5083aa2013-11-29 18:18:58 +00003455 if (len < (8 + offset + hdmi_3d_len - 1))
3456 goto out;
3457
3458 if (hdmi_3d_len < multi_len)
3459 goto out;
3460
3461 if (multi_present == 1 || multi_present == 2) {
3462 /* 3D_Structure_ALL */
3463 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3464
3465 /* check if 3D_MASK is present */
3466 if (multi_present == 2)
3467 mask = (db[10 + offset] << 8) | db[11 + offset];
3468 else
3469 mask = 0xffff;
3470
3471 for (i = 0; i < 16; i++) {
3472 if (mask & (1 << i))
3473 modes += add_3d_struct_modes(connector,
3474 structure_all,
3475 video_db,
3476 video_len, i);
3477 }
3478 }
3479
3480 offset += multi_len;
3481
3482 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3483 int vic_index;
3484 struct drm_display_mode *newmode = NULL;
3485 unsigned int newflag = 0;
3486 bool detail_present;
3487
3488 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3489
3490 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3491 break;
3492
3493 /* 2D_VIC_order_X */
3494 vic_index = db[8 + offset + i] >> 4;
3495
3496 /* 3D_Structure_X */
3497 switch (db[8 + offset + i] & 0x0f) {
3498 case 0:
3499 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3500 break;
3501 case 6:
3502 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3503 break;
3504 case 8:
3505 /* 3D_Detail_X */
3506 if ((db[9 + offset + i] >> 4) == 1)
3507 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3508 break;
3509 }
3510
3511 if (newflag != 0) {
3512 newmode = drm_display_mode_from_vic_index(connector,
3513 video_db,
3514 video_len,
3515 vic_index);
3516
3517 if (newmode) {
3518 newmode->flags |= newflag;
3519 drm_mode_probed_add(connector, newmode);
3520 modes++;
3521 }
3522 }
3523
3524 if (detail_present)
3525 i++;
Thomas Woodfbf46022013-10-16 15:58:50 +01003526 }
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003527
3528out:
Ville Syrjäläf1781e92017-11-13 19:04:19 +02003529 if (modes > 0)
3530 info->has_hdmi_infoframe = true;
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003531 return modes;
3532}
3533
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003534static int
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003535cea_db_payload_len(const u8 *db)
3536{
3537 return db[0] & 0x1f;
3538}
3539
3540static int
Shashank Sharma87563fc2017-07-13 21:03:10 +05303541cea_db_extended_tag(const u8 *db)
3542{
3543 return db[1];
3544}
3545
3546static int
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003547cea_db_tag(const u8 *db)
3548{
3549 return db[0] >> 5;
3550}
3551
3552static int
3553cea_revision(const u8 *cea)
3554{
3555 return cea[1];
3556}
3557
3558static int
3559cea_db_offsets(const u8 *cea, int *start, int *end)
3560{
3561 /* Data block offset in CEA extension block */
3562 *start = 4;
3563 *end = cea[2];
3564 if (*end == 0)
3565 *end = 127;
3566 if (*end < 4 || *end > 127)
3567 return -ERANGE;
3568 return 0;
3569}
3570
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003571static bool cea_db_is_hdmi_vsdb(const u8 *db)
3572{
3573 int hdmi_id;
3574
3575 if (cea_db_tag(db) != VENDOR_BLOCK)
3576 return false;
3577
3578 if (cea_db_payload_len(db) < 5)
3579 return false;
3580
3581 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3582
Lespiau, Damien6cb3b7f2013-08-19 16:59:05 +01003583 return hdmi_id == HDMI_IEEE_OUI;
Lespiau, Damien7ebe1962013-08-19 16:58:54 +01003584}
3585
Thierry Reding50dd1bd2017-03-13 16:54:00 +05303586static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3587{
3588 unsigned int oui;
3589
3590 if (cea_db_tag(db) != VENDOR_BLOCK)
3591 return false;
3592
3593 if (cea_db_payload_len(db) < 7)
3594 return false;
3595
3596 oui = db[3] << 16 | db[2] << 8 | db[1];
3597
3598 return oui == HDMI_FORUM_IEEE_OUI;
3599}
3600
Shashank Sharma832d4f22017-07-14 16:03:46 +05303601static bool cea_db_is_y420cmdb(const u8 *db)
3602{
3603 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3604 return false;
3605
3606 if (!cea_db_payload_len(db))
3607 return false;
3608
3609 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3610 return false;
3611
3612 return true;
3613}
3614
3615static bool cea_db_is_y420vdb(const u8 *db)
3616{
3617 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3618 return false;
3619
3620 if (!cea_db_payload_len(db))
3621 return false;
3622
3623 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3624 return false;
3625
3626 return true;
3627}
3628
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003629#define for_each_cea_db(cea, i, start, end) \
3630 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3631
Shashank Sharma832d4f22017-07-14 16:03:46 +05303632static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3633 const u8 *db)
3634{
3635 struct drm_display_info *info = &connector->display_info;
3636 struct drm_hdmi_info *hdmi = &info->hdmi;
3637 u8 map_len = cea_db_payload_len(db) - 1;
3638 u8 count;
3639 u64 map = 0;
3640
3641 if (map_len == 0) {
3642 /* All CEA modes support ycbcr420 sampling also.*/
3643 hdmi->y420_cmdb_map = U64_MAX;
3644 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3645 return;
3646 }
3647
3648 /*
3649 * This map indicates which of the existing CEA block modes
3650 * from VDB can support YCBCR420 output too. So if bit=0 is
3651 * set, first mode from VDB can support YCBCR420 output too.
3652 * We will parse and keep this map, before parsing VDB itself
3653 * to avoid going through the same block again and again.
3654 *
3655 * Spec is not clear about max possible size of this block.
3656 * Clamping max bitmap block size at 8 bytes. Every byte can
3657 * address 8 CEA modes, in this way this map can address
3658 * 8*8 = first 64 SVDs.
3659 */
3660 if (WARN_ON_ONCE(map_len > 8))
3661 map_len = 8;
3662
3663 for (count = 0; count < map_len; count++)
3664 map |= (u64)db[2 + count] << (8 * count);
3665
3666 if (map)
3667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3668
3669 hdmi->y420_cmdb_map = map;
3670}
3671
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003672static int
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003673add_cea_modes(struct drm_connector *connector, struct edid *edid)
3674{
Lespiau, Damien13ac3f52013-08-19 16:58:53 +01003675 const u8 *cea = drm_find_cea_extension(edid);
Thomas Woodfbf46022013-10-16 15:58:50 +01003676 const u8 *db, *hdmi = NULL, *video = NULL;
3677 u8 dbl, hdmi_len, video_len = 0;
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003678 int modes = 0;
3679
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003680 if (cea && cea_revision(cea) >= 3) {
3681 int i, start, end;
3682
3683 if (cea_db_offsets(cea, &start, &end))
3684 return 0;
3685
3686 for_each_cea_db(cea, i, start, end) {
3687 db = &cea[i];
3688 dbl = cea_db_payload_len(db);
3689
Thomas Woodfbf46022013-10-16 15:58:50 +01003690 if (cea_db_tag(db) == VIDEO_BLOCK) {
3691 video = db + 1;
3692 video_len = dbl;
3693 modes += do_cea_modes(connector, video, dbl);
Shashank Sharma832d4f22017-07-14 16:03:46 +05303694 } else if (cea_db_is_hdmi_vsdb(db)) {
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003695 hdmi = db;
3696 hdmi_len = dbl;
Shashank Sharma832d4f22017-07-14 16:03:46 +05303697 } else if (cea_db_is_y420vdb(db)) {
3698 const u8 *vdb420 = &db[2];
3699
3700 /* Add 4:2:0(only) modes present in EDID */
3701 modes += do_y420vdb_modes(connector,
3702 vdb420,
3703 dbl - 1);
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003704 }
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003705 }
3706 }
3707
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003708 /*
3709 * We parse the HDMI VSDB after having added the cea modes as we will
3710 * be patching their flags when the sink supports stereo 3D.
3711 */
3712 if (hdmi)
Thomas Woodfbf46022013-10-16 15:58:50 +01003713 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3714 video_len);
Damien Lespiauc858cfc2013-09-25 16:45:23 +01003715
Christian Schmidt54ac76f2011-12-19 14:53:16 +00003716 return modes;
3717}
3718
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003719static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3720{
3721 const struct drm_display_mode *cea_mode;
3722 int clock1, clock2, clock;
Jani Nikulad9278b42016-01-08 13:21:51 +02003723 u8 vic;
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003724 const char *type;
3725
Ville Syrjälä4c6bcf42015-11-16 21:05:12 +02003726 /*
3727 * allow 5kHz clock difference either way to account for
3728 * the 10kHz clock resolution limit of detailed timings.
3729 */
Jani Nikulad9278b42016-01-08 13:21:51 +02003730 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3731 if (drm_valid_cea_vic(vic)) {
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003732 type = "CEA";
Jani Nikulad9278b42016-01-08 13:21:51 +02003733 cea_mode = &edid_cea_modes[vic];
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003734 clock1 = cea_mode->clock;
3735 clock2 = cea_mode_alternate_clock(cea_mode);
3736 } else {
Jani Nikulad9278b42016-01-08 13:21:51 +02003737 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3738 if (drm_valid_hdmi_vic(vic)) {
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003739 type = "HDMI";
Jani Nikulad9278b42016-01-08 13:21:51 +02003740 cea_mode = &edid_4k_modes[vic];
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003741 clock1 = cea_mode->clock;
3742 clock2 = hdmi_mode_alternate_clock(cea_mode);
3743 } else {
3744 return;
3745 }
3746 }
3747
3748 /* pick whichever is closest */
3749 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3750 clock = clock1;
3751 else
3752 clock = clock2;
3753
3754 if (mode->clock == clock)
3755 return;
3756
3757 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
Jani Nikulad9278b42016-01-08 13:21:51 +02003758 type, vic, mode->clock, clock);
Ville Syrjäläfa3a7342015-10-08 11:43:32 +03003759 mode->clock = clock;
3760}
3761
Wu Fengguang76adaa342011-09-05 14:23:20 +08003762static void
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03003763drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
Wu Fengguang76adaa342011-09-05 14:23:20 +08003764{
Ville Syrjälä85040722012-08-16 14:55:05 +00003765 u8 len = cea_db_payload_len(db);
Wu Fengguang76adaa342011-09-05 14:23:20 +08003766
Jani Nikulaf7da77852017-11-01 16:20:57 +02003767 if (len >= 6 && (db[6] & (1 << 7)))
3768 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
Ville Syrjälä85040722012-08-16 14:55:05 +00003769 if (len >= 8) {
3770 connector->latency_present[0] = db[8] >> 7;
3771 connector->latency_present[1] = (db[8] >> 6) & 1;
3772 }
3773 if (len >= 9)
3774 connector->video_latency[0] = db[9];
3775 if (len >= 10)
3776 connector->audio_latency[0] = db[10];
3777 if (len >= 11)
3778 connector->video_latency[1] = db[11];
3779 if (len >= 12)
3780 connector->audio_latency[1] = db[12];
Wu Fengguang76adaa342011-09-05 14:23:20 +08003781
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03003782 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3783 "video latency %d %d, "
3784 "audio latency %d %d\n",
3785 connector->latency_present[0],
3786 connector->latency_present[1],
3787 connector->video_latency[0],
3788 connector->video_latency[1],
3789 connector->audio_latency[0],
3790 connector->audio_latency[1]);
Wu Fengguang76adaa342011-09-05 14:23:20 +08003791}
3792
3793static void
3794monitor_name(struct detailed_timing *t, void *data)
3795{
3796 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3797 *(u8 **)data = t->data.other_data.data.str.str;
3798}
3799
Jim Bride59f7c0f2016-04-14 10:18:35 -07003800static int get_monitor_name(struct edid *edid, char name[13])
3801{
3802 char *edid_name = NULL;
3803 int mnl;
3804
3805 if (!edid || !name)
3806 return 0;
3807
3808 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3809 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3810 if (edid_name[mnl] == 0x0a)
3811 break;
3812
3813 name[mnl] = edid_name[mnl];
3814 }
3815
3816 return mnl;
3817}
3818
3819/**
3820 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3821 * @edid: monitor EDID information
3822 * @name: pointer to a character array to hold the name of the monitor
3823 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3824 *
3825 */
3826void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3827{
3828 int name_length;
3829 char buf[13];
3830
3831 if (bufsize <= 0)
3832 return;
3833
3834 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3835 memcpy(name, buf, name_length);
3836 name[name_length] = '\0';
3837}
3838EXPORT_SYMBOL(drm_edid_get_monitor_name);
3839
Jani Nikula42750d32017-11-01 16:21:00 +02003840static void clear_eld(struct drm_connector *connector)
3841{
3842 memset(connector->eld, 0, sizeof(connector->eld));
3843
3844 connector->latency_present[0] = false;
3845 connector->latency_present[1] = false;
3846 connector->video_latency[0] = 0;
3847 connector->audio_latency[0] = 0;
3848 connector->video_latency[1] = 0;
3849 connector->audio_latency[1] = 0;
3850}
3851
Jani Nikula79436a12017-11-01 16:21:03 +02003852/*
Wu Fengguang76adaa342011-09-05 14:23:20 +08003853 * drm_edid_to_eld - build ELD from EDID
3854 * @connector: connector corresponding to the HDMI/DP sink
3855 * @edid: EDID to parse
3856 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02003857 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
Jani Nikula1d1c3662017-11-01 16:20:58 +02003858 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
Wu Fengguang76adaa342011-09-05 14:23:20 +08003859 */
Jani Nikula79436a12017-11-01 16:21:03 +02003860static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
Wu Fengguang76adaa342011-09-05 14:23:20 +08003861{
3862 uint8_t *eld = connector->eld;
3863 u8 *cea;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003864 u8 *db;
Ville Syrjälä7c018782016-03-09 22:07:46 +02003865 int total_sad_count = 0;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003866 int mnl;
3867 int dbl;
3868
Jani Nikula42750d32017-11-01 16:21:00 +02003869 clear_eld(connector);
Ville Syrjälä85c91582016-09-28 16:51:34 +03003870
Jani Nikulae9bd0b82017-02-17 17:20:52 +02003871 if (!edid)
3872 return;
3873
Wu Fengguang76adaa342011-09-05 14:23:20 +08003874 cea = drm_find_cea_extension(edid);
3875 if (!cea) {
3876 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3877 return;
3878 }
3879
Jani Nikulaf7da77852017-11-01 16:20:57 +02003880 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3881 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
Jim Bride59f7c0f2016-04-14 10:18:35 -07003882
Jani Nikulaf7da77852017-11-01 16:20:57 +02003883 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3884 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003885
Jani Nikulaf7da77852017-11-01 16:20:57 +02003886 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003887
Jani Nikulaf7da77852017-11-01 16:20:57 +02003888 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3889 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3890 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3891 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
Wu Fengguang76adaa342011-09-05 14:23:20 +08003892
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003893 if (cea_revision(cea) >= 3) {
3894 int i, start, end;
3895
3896 if (cea_db_offsets(cea, &start, &end)) {
3897 start = 0;
3898 end = 0;
3899 }
3900
3901 for_each_cea_db(cea, i, start, end) {
3902 db = &cea[i];
3903 dbl = cea_db_payload_len(db);
3904
3905 switch (cea_db_tag(db)) {
Ville Syrjälä7c018782016-03-09 22:07:46 +02003906 int sad_count;
3907
Christian Schmidta0ab7342011-12-19 20:03:38 +01003908 case AUDIO_BLOCK:
3909 /* Audio Data Block, contains SADs */
Ville Syrjälä7c018782016-03-09 22:07:46 +02003910 sad_count = min(dbl / 3, 15 - total_sad_count);
3911 if (sad_count >= 1)
Jani Nikulaf7da77852017-11-01 16:20:57 +02003912 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
Ville Syrjälä7c018782016-03-09 22:07:46 +02003913 &db[1], sad_count * 3);
3914 total_sad_count += sad_count;
Christian Schmidta0ab7342011-12-19 20:03:38 +01003915 break;
3916 case SPEAKER_BLOCK:
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003917 /* Speaker Allocation Data Block */
3918 if (dbl >= 1)
Jani Nikulaf7da77852017-11-01 16:20:57 +02003919 eld[DRM_ELD_SPEAKER] = db[1];
Christian Schmidta0ab7342011-12-19 20:03:38 +01003920 break;
3921 case VENDOR_BLOCK:
3922 /* HDMI Vendor-Specific Data Block */
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00003923 if (cea_db_is_hdmi_vsdb(db))
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03003924 drm_parse_hdmi_vsdb_audio(connector, db);
Christian Schmidta0ab7342011-12-19 20:03:38 +01003925 break;
3926 default:
3927 break;
3928 }
Wu Fengguang76adaa342011-09-05 14:23:20 +08003929 }
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00003930 }
Jani Nikulaf7da77852017-11-01 16:20:57 +02003931 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003932
Jani Nikula1d1c3662017-11-01 16:20:58 +02003933 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3934 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3935 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3936 else
3937 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
Wu Fengguang76adaa342011-09-05 14:23:20 +08003938
Jani Nikula938fd8a2014-10-28 16:20:48 +02003939 eld[DRM_ELD_BASELINE_ELD_LEN] =
3940 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3941
3942 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
Ville Syrjälä7c018782016-03-09 22:07:46 +02003943 drm_eld_size(eld), total_sad_count);
Wu Fengguang76adaa342011-09-05 14:23:20 +08003944}
Wu Fengguang76adaa342011-09-05 14:23:20 +08003945
3946/**
Rafał Miłeckife214162013-04-19 19:01:25 +02003947 * drm_edid_to_sad - extracts SADs from EDID
3948 * @edid: EDID to parse
3949 * @sads: pointer that will be set to the extracted SADs
3950 *
3951 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
Rafał Miłeckife214162013-04-19 19:01:25 +02003952 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02003953 * Note: The returned pointer needs to be freed using kfree().
3954 *
3955 * Return: The number of found SADs or negative number on error.
Rafał Miłeckife214162013-04-19 19:01:25 +02003956 */
3957int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3958{
3959 int count = 0;
3960 int i, start, end, dbl;
3961 u8 *cea;
3962
3963 cea = drm_find_cea_extension(edid);
3964 if (!cea) {
3965 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3966 return -ENOENT;
3967 }
3968
3969 if (cea_revision(cea) < 3) {
3970 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3971 return -ENOTSUPP;
3972 }
3973
3974 if (cea_db_offsets(cea, &start, &end)) {
3975 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3976 return -EPROTO;
3977 }
3978
3979 for_each_cea_db(cea, i, start, end) {
3980 u8 *db = &cea[i];
3981
3982 if (cea_db_tag(db) == AUDIO_BLOCK) {
3983 int j;
3984 dbl = cea_db_payload_len(db);
3985
3986 count = dbl / 3; /* SAD is 3B */
3987 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3988 if (!*sads)
3989 return -ENOMEM;
3990 for (j = 0; j < count; j++) {
3991 u8 *sad = &db[1 + j * 3];
3992
3993 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3994 (*sads)[j].channels = sad[0] & 0x7;
3995 (*sads)[j].freq = sad[1] & 0x7F;
3996 (*sads)[j].byte2 = sad[2];
3997 }
3998 break;
3999 }
4000 }
4001
4002 return count;
4003}
4004EXPORT_SYMBOL(drm_edid_to_sad);
4005
4006/**
Alex Deucherd105f472013-07-25 15:55:32 -04004007 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4008 * @edid: EDID to parse
4009 * @sadb: pointer to the speaker block
4010 *
4011 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
Alex Deucherd105f472013-07-25 15:55:32 -04004012 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004013 * Note: The returned pointer needs to be freed using kfree().
4014 *
4015 * Return: The number of found Speaker Allocation Blocks or negative number on
4016 * error.
Alex Deucherd105f472013-07-25 15:55:32 -04004017 */
4018int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4019{
4020 int count = 0;
4021 int i, start, end, dbl;
4022 const u8 *cea;
4023
4024 cea = drm_find_cea_extension(edid);
4025 if (!cea) {
4026 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4027 return -ENOENT;
4028 }
4029
4030 if (cea_revision(cea) < 3) {
4031 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4032 return -ENOTSUPP;
4033 }
4034
4035 if (cea_db_offsets(cea, &start, &end)) {
4036 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4037 return -EPROTO;
4038 }
4039
4040 for_each_cea_db(cea, i, start, end) {
4041 const u8 *db = &cea[i];
4042
4043 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4044 dbl = cea_db_payload_len(db);
4045
4046 /* Speaker Allocation Data Block */
4047 if (dbl == 3) {
Benoit Taine89086bc2014-05-26 17:21:22 +02004048 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
Alex Deucher618e3772013-09-27 18:46:09 -04004049 if (!*sadb)
4050 return -ENOMEM;
Alex Deucherd105f472013-07-25 15:55:32 -04004051 count = dbl;
4052 break;
4053 }
4054 }
4055 }
4056
4057 return count;
4058}
4059EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4060
4061/**
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004062 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
Wu Fengguang76adaa342011-09-05 14:23:20 +08004063 * @connector: connector associated with the HDMI/DP sink
4064 * @mode: the display mode
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004065 *
4066 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4067 * the sink doesn't support audio or video.
Wu Fengguang76adaa342011-09-05 14:23:20 +08004068 */
4069int drm_av_sync_delay(struct drm_connector *connector,
Ville Syrjälä3a818d32015-09-07 18:22:58 +03004070 const struct drm_display_mode *mode)
Wu Fengguang76adaa342011-09-05 14:23:20 +08004071{
4072 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4073 int a, v;
4074
4075 if (!connector->latency_present[0])
4076 return 0;
4077 if (!connector->latency_present[1])
4078 i = 0;
4079
4080 a = connector->audio_latency[i];
4081 v = connector->video_latency[i];
4082
4083 /*
4084 * HDMI/DP sink doesn't support audio or video?
4085 */
4086 if (a == 255 || v == 255)
4087 return 0;
4088
4089 /*
4090 * Convert raw EDID values to millisecond.
4091 * Treat unknown latency as 0ms.
4092 */
4093 if (a)
4094 a = min(2 * (a - 1), 500);
4095 if (v)
4096 v = min(2 * (v - 1), 500);
4097
4098 return max(v - a, 0);
4099}
4100EXPORT_SYMBOL(drm_av_sync_delay);
4101
4102/**
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004103 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
Ma Lingf23c20c2009-03-26 19:26:23 +08004104 * @edid: monitor EDID information
4105 *
4106 * Parse the CEA extension according to CEA-861-B.
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004107 *
4108 * Return: True if the monitor is HDMI, false if not or unknown.
Ma Lingf23c20c2009-03-26 19:26:23 +08004109 */
4110bool drm_detect_hdmi_monitor(struct edid *edid)
4111{
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004112 u8 *edid_ext;
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00004113 int i;
Ma Lingf23c20c2009-03-26 19:26:23 +08004114 int start_offset, end_offset;
Ma Lingf23c20c2009-03-26 19:26:23 +08004115
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004116 edid_ext = drm_find_cea_extension(edid);
4117 if (!edid_ext)
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00004118 return false;
Ma Lingf23c20c2009-03-26 19:26:23 +08004119
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00004120 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00004121 return false;
Ma Lingf23c20c2009-03-26 19:26:23 +08004122
4123 /*
4124 * Because HDMI identifier is in Vendor Specific Block,
4125 * search it from all data blocks of CEA extension.
4126 */
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00004127 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00004128 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4129 return true;
Ma Lingf23c20c2009-03-26 19:26:23 +08004130 }
4131
Ville Syrjälä14f77fd2012-08-16 14:55:06 +00004132 return false;
Ma Lingf23c20c2009-03-26 19:26:23 +08004133}
4134EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4135
Dave Airlief453ba02008-11-07 14:05:41 -08004136/**
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004137 * drm_detect_monitor_audio - check monitor audio capability
Daniel Vetterfc668112014-01-21 12:02:26 +01004138 * @edid: EDID block to scan
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004139 *
4140 * Monitor should have CEA extension block.
4141 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4142 * audio' only. If there is any audio extension block and supported
4143 * audio format, assume at least 'basic audio' support, even if 'basic
4144 * audio' is not defined in EDID.
4145 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004146 * Return: True if the monitor supports audio, false otherwise.
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004147 */
4148bool drm_detect_monitor_audio(struct edid *edid)
4149{
4150 u8 *edid_ext;
4151 int i, j;
4152 bool has_audio = false;
4153 int start_offset, end_offset;
4154
4155 edid_ext = drm_find_cea_extension(edid);
4156 if (!edid_ext)
4157 goto end;
4158
4159 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4160
4161 if (has_audio) {
4162 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4163 goto end;
4164 }
4165
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00004166 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4167 goto end;
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004168
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00004169 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4170 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004171 has_audio = true;
Ville Syrjälä9e50b9d2012-08-16 14:55:04 +00004172 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
Zhenyu Wang8fe97902010-09-19 14:27:28 +08004173 DRM_DEBUG_KMS("CEA audio format %d\n",
4174 (edid_ext[i + j] >> 3) & 0xf);
4175 goto end;
4176 }
4177 }
4178end:
4179 return has_audio;
4180}
4181EXPORT_SYMBOL(drm_detect_monitor_audio);
4182
4183/**
Ville Syrjäläb1edd6a2013-01-17 16:31:30 +02004184 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
Daniel Vetterfc668112014-01-21 12:02:26 +01004185 * @edid: EDID block to scan
Ville Syrjäläb1edd6a2013-01-17 16:31:30 +02004186 *
4187 * Check whether the monitor reports the RGB quantization range selection
4188 * as supported. The AVI infoframe can then be used to inform the monitor
4189 * which quantization range (full or limited) is used.
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004190 *
4191 * Return: True if the RGB quantization range is selectable, false otherwise.
Ville Syrjäläb1edd6a2013-01-17 16:31:30 +02004192 */
4193bool drm_rgb_quant_range_selectable(struct edid *edid)
4194{
4195 u8 *edid_ext;
4196 int i, start, end;
4197
4198 edid_ext = drm_find_cea_extension(edid);
4199 if (!edid_ext)
4200 return false;
4201
4202 if (cea_db_offsets(edid_ext, &start, &end))
4203 return false;
4204
4205 for_each_cea_db(edid_ext, i, start, end) {
Shashank Sharma87563fc2017-07-13 21:03:10 +05304206 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4207 cea_db_payload_len(&edid_ext[i]) == 2 &&
4208 cea_db_extended_tag(&edid_ext[i]) ==
4209 EXT_VIDEO_CAPABILITY_BLOCK) {
Ville Syrjäläb1edd6a2013-01-17 16:31:30 +02004210 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4211 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4212 }
4213 }
4214
4215 return false;
4216}
4217EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4218
Ville Syrjäläc8127cf02017-01-11 16:18:35 +02004219/**
4220 * drm_default_rgb_quant_range - default RGB quantization range
4221 * @mode: display mode
4222 *
4223 * Determine the default RGB quantization range for the mode,
4224 * as specified in CEA-861.
4225 *
4226 * Return: The default RGB quantization range for the mode
4227 */
4228enum hdmi_quantization_range
4229drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4230{
4231 /* All CEA modes other than VIC 1 use limited quantization range. */
4232 return drm_match_cea_mode(mode) > 1 ?
4233 HDMI_QUANTIZATION_RANGE_LIMITED :
4234 HDMI_QUANTIZATION_RANGE_FULL;
4235}
4236EXPORT_SYMBOL(drm_default_rgb_quant_range);
4237
Shashank Sharmae6a9a2c2017-07-13 21:03:13 +05304238static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4239 const u8 *db)
4240{
4241 u8 dc_mask;
4242 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4243
4244 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4245 hdmi->y420_dc_modes |= dc_mask;
4246}
4247
Shashank Sharmaafa1c762017-03-13 16:54:01 +05304248static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4249 const u8 *hf_vsdb)
4250{
Shashank Sharma62c58af2017-03-13 16:54:02 +05304251 struct drm_display_info *display = &connector->display_info;
4252 struct drm_hdmi_info *hdmi = &display->hdmi;
Shashank Sharmaafa1c762017-03-13 16:54:01 +05304253
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004254 display->has_hdmi_infoframe = true;
4255
Shashank Sharmaafa1c762017-03-13 16:54:01 +05304256 if (hf_vsdb[6] & 0x80) {
4257 hdmi->scdc.supported = true;
4258 if (hf_vsdb[6] & 0x40)
4259 hdmi->scdc.read_request = true;
4260 }
Shashank Sharma62c58af2017-03-13 16:54:02 +05304261
4262 /*
4263 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4264 * And as per the spec, three factors confirm this:
4265 * * Availability of a HF-VSDB block in EDID (check)
4266 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4267 * * SCDC support available (let's check)
4268 * Lets check it out.
4269 */
4270
4271 if (hf_vsdb[5]) {
4272 /* max clock is 5000 KHz times block value */
4273 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4274 struct drm_scdc *scdc = &hdmi->scdc;
4275
4276 if (max_tmds_clock > 340000) {
4277 display->max_tmds_clock = max_tmds_clock;
4278 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4279 display->max_tmds_clock);
4280 }
4281
4282 if (scdc->supported) {
4283 scdc->scrambling.supported = true;
4284
4285 /* Few sinks support scrambling for cloks < 340M */
4286 if ((hf_vsdb[6] & 0x8))
4287 scdc->scrambling.low_rates = true;
4288 }
4289 }
Shashank Sharmae6a9a2c2017-07-13 21:03:13 +05304290
4291 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
Shashank Sharmaafa1c762017-03-13 16:54:01 +05304292}
4293
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004294static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4295 const u8 *hdmi)
Mario Kleinerd0c94692014-03-27 19:59:39 +01004296{
Ville Syrjälä18267502016-09-28 16:51:38 +03004297 struct drm_display_info *info = &connector->display_info;
Mario Kleinerd0c94692014-03-27 19:59:39 +01004298 unsigned int dc_bpc = 0;
4299
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004300 /* HDMI supports at least 8 bpc */
4301 info->bpc = 8;
4302
4303 if (cea_db_payload_len(hdmi) < 6)
4304 return;
4305
4306 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4307 dc_bpc = 10;
4308 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4309 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4310 connector->name);
4311 }
4312
4313 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4314 dc_bpc = 12;
4315 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4316 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4317 connector->name);
4318 }
4319
4320 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4321 dc_bpc = 16;
4322 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4323 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4324 connector->name);
4325 }
4326
4327 if (dc_bpc == 0) {
4328 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4329 connector->name);
4330 return;
4331 }
4332
4333 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4334 connector->name, dc_bpc);
4335 info->bpc = dc_bpc;
4336
4337 /*
4338 * Deep color support mandates RGB444 support for all video
4339 * modes and forbids YCRCB422 support for all video modes per
4340 * HDMI 1.3 spec.
4341 */
4342 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4343
4344 /* YCRCB444 is optional according to spec. */
4345 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4346 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4347 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4348 connector->name);
4349 }
4350
4351 /*
4352 * Spec says that if any deep color mode is supported at all,
4353 * then deep color 36 bit must be supported.
4354 */
4355 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4356 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4357 connector->name);
4358 }
4359}
4360
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03004361static void
4362drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4363{
4364 struct drm_display_info *info = &connector->display_info;
4365 u8 len = cea_db_payload_len(db);
4366
4367 if (len >= 6)
4368 info->dvi_dual = db[6] & 1;
4369 if (len >= 7)
4370 info->max_tmds_clock = db[7] * 5000;
4371
4372 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4373 "max TMDS clock %d kHz\n",
4374 info->dvi_dual,
4375 info->max_tmds_clock);
4376
4377 drm_parse_hdmi_deep_color_info(connector, db);
4378}
4379
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004380static void drm_parse_cea_ext(struct drm_connector *connector,
Keith Packard170178f2017-12-13 00:44:26 -08004381 const struct edid *edid)
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004382{
4383 struct drm_display_info *info = &connector->display_info;
4384 const u8 *edid_ext;
4385 int i, start, end;
4386
Mario Kleinerd0c94692014-03-27 19:59:39 +01004387 edid_ext = drm_find_cea_extension(edid);
4388 if (!edid_ext)
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004389 return;
Mario Kleinerd0c94692014-03-27 19:59:39 +01004390
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004391 info->cea_rev = edid_ext[1];
Mario Kleinerd0c94692014-03-27 19:59:39 +01004392
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004393 /* The existence of a CEA block should imply RGB support */
4394 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4395 if (edid_ext[3] & EDID_CEA_YCRCB444)
4396 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4397 if (edid_ext[3] & EDID_CEA_YCRCB422)
4398 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
Mario Kleinerd0c94692014-03-27 19:59:39 +01004399
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004400 if (cea_db_offsets(edid_ext, &start, &end))
4401 return;
Mario Kleinerd0c94692014-03-27 19:59:39 +01004402
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004403 for_each_cea_db(edid_ext, i, start, end) {
4404 const u8 *db = &edid_ext[i];
Mario Kleinerd0c94692014-03-27 19:59:39 +01004405
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03004406 if (cea_db_is_hdmi_vsdb(db))
4407 drm_parse_hdmi_vsdb_video(connector, db);
Shashank Sharmaafa1c762017-03-13 16:54:01 +05304408 if (cea_db_is_hdmi_forum_vsdb(db))
4409 drm_parse_hdmi_forum_vsdb(connector, db);
Shashank Sharma832d4f22017-07-14 16:03:46 +05304410 if (cea_db_is_y420cmdb(db))
4411 drm_parse_y420cmdb_bitmap(connector, db);
Mario Kleinerd0c94692014-03-27 19:59:39 +01004412 }
Mario Kleinerd0c94692014-03-27 19:59:39 +01004413}
4414
Keith Packard170178f2017-12-13 00:44:26 -08004415/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4416 * all of the values which would have been set from EDID
4417 */
4418void
4419drm_reset_display_info(struct drm_connector *connector)
Jesse Barnes3b112282011-04-15 12:49:23 -07004420{
Ville Syrjälä18267502016-09-28 16:51:38 +03004421 struct drm_display_info *info = &connector->display_info;
Jesse Barnesebec9a7b2011-08-03 09:22:54 -07004422
Keith Packard170178f2017-12-13 00:44:26 -08004423 info->width_mm = 0;
4424 info->height_mm = 0;
4425
4426 info->bpc = 0;
4427 info->color_formats = 0;
4428 info->cea_rev = 0;
4429 info->max_tmds_clock = 0;
4430 info->dvi_dual = false;
4431 info->has_hdmi_infoframe = false;
4432
4433 info->non_desktop = 0;
4434}
4435EXPORT_SYMBOL_GPL(drm_reset_display_info);
4436
4437u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4438{
4439 struct drm_display_info *info = &connector->display_info;
4440
4441 u32 quirks = edid_get_quirks(edid);
4442
Jesse Barnes3b112282011-04-15 12:49:23 -07004443 info->width_mm = edid->width_cm * 10;
4444 info->height_mm = edid->height_cm * 10;
4445
4446 /* driver figures it out in this case */
4447 info->bpc = 0;
Jesse Barnesda05a5a72011-04-15 13:48:57 -07004448 info->color_formats = 0;
Ville Syrjälä011acce2016-09-28 16:51:40 +03004449 info->cea_rev = 0;
Ville Syrjälä23ebf8b2016-09-28 16:51:41 +03004450 info->max_tmds_clock = 0;
4451 info->dvi_dual = false;
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004452 info->has_hdmi_infoframe = false;
Jesse Barnes3b112282011-04-15 12:49:23 -07004453
Dave Airlie66660d42017-10-16 05:08:09 +01004454 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4455
Keith Packard170178f2017-12-13 00:44:26 -08004456 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4457
Lars-Peter Clausena988bc72012-04-16 15:16:19 +02004458 if (edid->revision < 3)
Keith Packard170178f2017-12-13 00:44:26 -08004459 return quirks;
Jesse Barnes3b112282011-04-15 12:49:23 -07004460
4461 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
Keith Packard170178f2017-12-13 00:44:26 -08004462 return quirks;
Jesse Barnes3b112282011-04-15 12:49:23 -07004463
Ville Syrjälä1cea1462016-09-28 16:51:39 +03004464 drm_parse_cea_ext(connector, edid);
Mario Kleinerd0c94692014-03-27 19:59:39 +01004465
Mario Kleiner210a0212016-07-06 12:05:48 +02004466 /*
4467 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4468 *
4469 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4470 * tells us to assume 8 bpc color depth if the EDID doesn't have
4471 * extensions which tell otherwise.
4472 */
4473 if ((info->bpc == 0) && (edid->revision < 4) &&
4474 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4475 info->bpc = 8;
4476 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4477 connector->name, info->bpc);
4478 }
4479
Lars-Peter Clausena988bc72012-04-16 15:16:19 +02004480 /* Only defined for 1.4 with digital displays */
4481 if (edid->revision < 4)
Keith Packard170178f2017-12-13 00:44:26 -08004482 return quirks;
Lars-Peter Clausena988bc72012-04-16 15:16:19 +02004483
Jesse Barnes3b112282011-04-15 12:49:23 -07004484 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4485 case DRM_EDID_DIGITAL_DEPTH_6:
4486 info->bpc = 6;
4487 break;
4488 case DRM_EDID_DIGITAL_DEPTH_8:
4489 info->bpc = 8;
4490 break;
4491 case DRM_EDID_DIGITAL_DEPTH_10:
4492 info->bpc = 10;
4493 break;
4494 case DRM_EDID_DIGITAL_DEPTH_12:
4495 info->bpc = 12;
4496 break;
4497 case DRM_EDID_DIGITAL_DEPTH_14:
4498 info->bpc = 14;
4499 break;
4500 case DRM_EDID_DIGITAL_DEPTH_16:
4501 info->bpc = 16;
4502 break;
4503 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4504 default:
4505 info->bpc = 0;
4506 break;
4507 }
Jesse Barnesda05a5a72011-04-15 13:48:57 -07004508
Mario Kleinerd0c94692014-03-27 19:59:39 +01004509 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
Jani Nikula25933822014-06-03 14:56:20 +03004510 connector->name, info->bpc);
Mario Kleinerd0c94692014-03-27 19:59:39 +01004511
Lars-Peter Clausena988bc72012-04-16 15:16:19 +02004512 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
Lars-Peter Clausenee588082012-04-16 15:16:18 +02004513 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4514 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4515 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4516 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
Keith Packard170178f2017-12-13 00:44:26 -08004517 return quirks;
Jesse Barnes3b112282011-04-15 12:49:23 -07004518}
Keith Packard170178f2017-12-13 00:44:26 -08004519EXPORT_SYMBOL_GPL(drm_add_display_info);
Jesse Barnes3b112282011-04-15 12:49:23 -07004520
Dave Airliec97291772016-05-03 15:38:37 +10004521static int validate_displayid(u8 *displayid, int length, int idx)
4522{
4523 int i;
4524 u8 csum = 0;
4525 struct displayid_hdr *base;
4526
4527 base = (struct displayid_hdr *)&displayid[idx];
4528
4529 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4530 base->rev, base->bytes, base->prod_id, base->ext_count);
4531
4532 if (base->bytes + 5 > length - idx)
4533 return -EINVAL;
4534 for (i = idx; i <= base->bytes + 5; i++) {
4535 csum += displayid[i];
4536 }
4537 if (csum) {
Chris Wilson813a7872017-02-10 19:59:13 +00004538 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
Dave Airliec97291772016-05-03 15:38:37 +10004539 return -EINVAL;
4540 }
4541 return 0;
4542}
4543
Dave Airliea39ed682016-05-02 08:35:05 +10004544static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4545 struct displayid_detailed_timings_1 *timings)
4546{
4547 struct drm_display_mode *mode;
4548 unsigned pixel_clock = (timings->pixel_clock[0] |
4549 (timings->pixel_clock[1] << 8) |
4550 (timings->pixel_clock[2] << 16));
4551 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4552 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4553 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4554 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4555 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4556 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4557 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4558 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4559 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4560 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4561 mode = drm_mode_create(dev);
4562 if (!mode)
4563 return NULL;
4564
4565 mode->clock = pixel_clock * 10;
4566 mode->hdisplay = hactive;
4567 mode->hsync_start = mode->hdisplay + hsync;
4568 mode->hsync_end = mode->hsync_start + hsync_width;
4569 mode->htotal = mode->hdisplay + hblank;
4570
4571 mode->vdisplay = vactive;
4572 mode->vsync_start = mode->vdisplay + vsync;
4573 mode->vsync_end = mode->vsync_start + vsync_width;
4574 mode->vtotal = mode->vdisplay + vblank;
4575
4576 mode->flags = 0;
4577 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4578 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4579 mode->type = DRM_MODE_TYPE_DRIVER;
4580
4581 if (timings->flags & 0x80)
4582 mode->type |= DRM_MODE_TYPE_PREFERRED;
4583 mode->vrefresh = drm_mode_vrefresh(mode);
4584 drm_mode_set_name(mode);
4585
4586 return mode;
4587}
4588
4589static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4590 struct displayid_block *block)
4591{
4592 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4593 int i;
4594 int num_timings;
4595 struct drm_display_mode *newmode;
4596 int num_modes = 0;
4597 /* blocks must be multiple of 20 bytes length */
4598 if (block->num_bytes % 20)
4599 return 0;
4600
4601 num_timings = block->num_bytes / 20;
4602 for (i = 0; i < num_timings; i++) {
4603 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4604
4605 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4606 if (!newmode)
4607 continue;
4608
4609 drm_mode_probed_add(connector, newmode);
4610 num_modes++;
4611 }
4612 return num_modes;
4613}
4614
4615static int add_displayid_detailed_modes(struct drm_connector *connector,
4616 struct edid *edid)
4617{
4618 u8 *displayid;
4619 int ret;
4620 int idx = 1;
4621 int length = EDID_LENGTH;
4622 struct displayid_block *block;
4623 int num_modes = 0;
4624
4625 displayid = drm_find_displayid_extension(edid);
4626 if (!displayid)
4627 return 0;
4628
4629 ret = validate_displayid(displayid, length, idx);
4630 if (ret)
4631 return 0;
4632
4633 idx += sizeof(struct displayid_hdr);
4634 while (block = (struct displayid_block *)&displayid[idx],
4635 idx + sizeof(struct displayid_block) <= length &&
4636 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4637 block->num_bytes > 0) {
4638 idx += block->num_bytes + sizeof(struct displayid_block);
4639 switch (block->tag) {
4640 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4641 num_modes += add_displayid_detailed_1_modes(connector, block);
4642 break;
4643 }
4644 }
4645 return num_modes;
4646}
4647
Jesse Barnes3b112282011-04-15 12:49:23 -07004648/**
Dave Airlief453ba02008-11-07 14:05:41 -08004649 * drm_add_edid_modes - add modes from EDID data, if available
4650 * @connector: connector we're probing
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004651 * @edid: EDID data
Dave Airlief453ba02008-11-07 14:05:41 -08004652 *
Daniel Vetterb3c6c8b2016-08-12 22:48:55 +02004653 * Add the specified modes to the connector's mode list. Also fills out the
Jani Nikulac945b8c2017-11-01 16:21:01 +02004654 * &drm_display_info structure and ELD in @connector with any information which
4655 * can be derived from the edid.
Dave Airlief453ba02008-11-07 14:05:41 -08004656 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004657 * Return: The number of modes added or 0 if we couldn't find any.
Dave Airlief453ba02008-11-07 14:05:41 -08004658 */
4659int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4660{
4661 int num_modes = 0;
4662 u32 quirks;
4663
4664 if (edid == NULL) {
Jani Nikulac945b8c2017-11-01 16:21:01 +02004665 clear_eld(connector);
Dave Airlief453ba02008-11-07 14:05:41 -08004666 return 0;
4667 }
Alex Deucher3c537882010-02-05 04:21:19 -05004668 if (!drm_edid_is_valid(edid)) {
Jani Nikulac945b8c2017-11-01 16:21:01 +02004669 clear_eld(connector);
Jordan Crousedcdb1672010-05-27 13:40:25 -06004670 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
Jani Nikula25933822014-06-03 14:56:20 +03004671 connector->name);
Dave Airlief453ba02008-11-07 14:05:41 -08004672 return 0;
4673 }
4674
Jani Nikulac945b8c2017-11-01 16:21:01 +02004675 drm_edid_to_eld(connector, edid);
4676
Adam Jacksonc867df72010-03-29 21:43:21 +00004677 /*
Shashank Sharma0f0f8702017-07-13 21:03:09 +05304678 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4679 * To avoid multiple parsing of same block, lets parse that map
4680 * from sink info, before parsing CEA modes.
4681 */
Keith Packard170178f2017-12-13 00:44:26 -08004682 quirks = drm_add_display_info(connector, edid);
Shashank Sharma0f0f8702017-07-13 21:03:09 +05304683
4684 /*
Adam Jacksonc867df72010-03-29 21:43:21 +00004685 * EDID spec says modes should be preferred in this order:
4686 * - preferred detailed mode
4687 * - other detailed modes from base block
4688 * - detailed modes from extension blocks
4689 * - CVT 3-byte code modes
4690 * - standard timing codes
4691 * - established timing codes
4692 * - modes inferred from GTF or CVT range information
4693 *
Adam Jackson13931572010-08-03 14:38:19 -04004694 * We get this pretty much right.
Adam Jacksonc867df72010-03-29 21:43:21 +00004695 *
4696 * XXX order for additional mode types in extension blocks?
4697 */
Adam Jackson13931572010-08-03 14:38:19 -04004698 num_modes += add_detailed_modes(connector, edid, quirks);
4699 num_modes += add_cvt_modes(connector, edid);
Adam Jacksonc867df72010-03-29 21:43:21 +00004700 num_modes += add_standard_modes(connector, edid);
4701 num_modes += add_established_modes(connector, edid);
Christian Schmidt54ac76f2011-12-19 14:53:16 +00004702 num_modes += add_cea_modes(connector, edid);
Ville Syrjäläe6e79202013-05-31 15:23:41 +03004703 num_modes += add_alternate_cea_modes(connector, edid);
Dave Airliea39ed682016-05-02 08:35:05 +10004704 num_modes += add_displayid_detailed_modes(connector, edid);
Ville Syrjälä4d53dc02015-05-08 17:45:07 +03004705 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4706 num_modes += add_inferred_modes(connector, edid);
Dave Airlief453ba02008-11-07 14:05:41 -08004707
4708 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4709 edid_fixup_preferred(connector, quirks);
4710
Mario Kleinere10aec62016-07-06 12:05:44 +02004711 if (quirks & EDID_QUIRK_FORCE_6BPC)
4712 connector->display_info.bpc = 6;
4713
Rafał Miłecki49d45a312013-12-07 13:22:42 +01004714 if (quirks & EDID_QUIRK_FORCE_8BPC)
4715 connector->display_info.bpc = 8;
4716
Mario Kleinere345da82017-04-21 17:05:08 +02004717 if (quirks & EDID_QUIRK_FORCE_10BPC)
4718 connector->display_info.bpc = 10;
4719
Mario Kleinerbc5b9642014-05-23 21:40:55 +02004720 if (quirks & EDID_QUIRK_FORCE_12BPC)
4721 connector->display_info.bpc = 12;
4722
Dave Airlief453ba02008-11-07 14:05:41 -08004723 return num_modes;
4724}
4725EXPORT_SYMBOL(drm_add_edid_modes);
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004726
4727/**
4728 * drm_add_modes_noedid - add modes for the connectors without EDID
4729 * @connector: connector we're probing
4730 * @hdisplay: the horizontal display limit
4731 * @vdisplay: the vertical display limit
4732 *
4733 * Add the specified modes to the connector's mode list. Only when the
4734 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4735 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004736 * Return: The number of modes added or 0 if we couldn't find any.
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004737 */
4738int drm_add_modes_noedid(struct drm_connector *connector,
4739 int hdisplay, int vdisplay)
4740{
4741 int i, count, num_modes = 0;
Chris Wilsonb1f559e2011-01-26 09:49:47 +00004742 struct drm_display_mode *mode;
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004743 struct drm_device *dev = connector->dev;
4744
Daniel Vetterfbb40b22015-08-10 11:55:37 +02004745 count = ARRAY_SIZE(drm_dmt_modes);
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004746 if (hdisplay < 0)
4747 hdisplay = 0;
4748 if (vdisplay < 0)
4749 vdisplay = 0;
4750
4751 for (i = 0; i < count; i++) {
Chris Wilsonb1f559e2011-01-26 09:49:47 +00004752 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004753 if (hdisplay && vdisplay) {
4754 /*
4755 * Only when two are valid, they will be used to check
4756 * whether the mode should be added to the mode list of
4757 * the connector.
4758 */
4759 if (ptr->hdisplay > hdisplay ||
4760 ptr->vdisplay > vdisplay)
4761 continue;
4762 }
Adam Jacksonf985ded2009-11-23 14:23:04 -05004763 if (drm_mode_vrefresh(ptr) > 61)
4764 continue;
Zhao Yakuif0fda0a2009-09-03 09:33:48 +08004765 mode = drm_mode_duplicate(dev, ptr);
4766 if (mode) {
4767 drm_mode_probed_add(connector, mode);
4768 num_modes++;
4769 }
4770 }
4771 return num_modes;
4772}
4773EXPORT_SYMBOL(drm_add_modes_noedid);
Thierry Reding10a85122012-11-21 15:31:35 +01004774
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004775/**
4776 * drm_set_preferred_mode - Sets the preferred mode of a connector
4777 * @connector: connector whose mode list should be processed
4778 * @hpref: horizontal resolution of preferred mode
4779 * @vpref: vertical resolution of preferred mode
4780 *
4781 * Marks a mode as preferred if it matches the resolution specified by @hpref
4782 * and @vpref.
4783 */
Gerd Hoffmann3cf70da2013-10-11 10:01:08 +02004784void drm_set_preferred_mode(struct drm_connector *connector,
4785 int hpref, int vpref)
4786{
4787 struct drm_display_mode *mode;
4788
4789 list_for_each_entry(mode, &connector->probed_modes, head) {
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004790 if (mode->hdisplay == hpref &&
Daniel Vetter9d3de132014-01-23 16:27:56 +01004791 mode->vdisplay == vpref)
Gerd Hoffmann3cf70da2013-10-11 10:01:08 +02004792 mode->type |= DRM_MODE_TYPE_PREFERRED;
4793 }
4794}
4795EXPORT_SYMBOL(drm_set_preferred_mode);
4796
Thierry Reding10a85122012-11-21 15:31:35 +01004797/**
4798 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4799 * data from a DRM display mode
4800 * @frame: HDMI AVI infoframe
4801 * @mode: DRM display mode
Shashank Sharma0c1f5282017-07-13 21:03:07 +05304802 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
Thierry Reding10a85122012-11-21 15:31:35 +01004803 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004804 * Return: 0 on success or a negative error code on failure.
Thierry Reding10a85122012-11-21 15:31:35 +01004805 */
4806int
4807drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
Shashank Sharma0c1f5282017-07-13 21:03:07 +05304808 const struct drm_display_mode *mode,
4809 bool is_hdmi2_sink)
Thierry Reding10a85122012-11-21 15:31:35 +01004810{
4811 int err;
4812
4813 if (!frame || !mode)
4814 return -EINVAL;
4815
4816 err = hdmi_avi_infoframe_init(frame);
4817 if (err < 0)
4818 return err;
4819
Damien Lespiaubf02db92013-08-06 20:32:22 +01004820 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4821 frame->pixel_repeat = 1;
4822
Thierry Reding10a85122012-11-21 15:31:35 +01004823 frame->video_code = drm_match_cea_mode(mode);
Thierry Reding10a85122012-11-21 15:31:35 +01004824
Shashank Sharma0c1f5282017-07-13 21:03:07 +05304825 /*
4826 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4827 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4828 * have to make sure we dont break HDMI 1.4 sinks.
4829 */
4830 if (!is_hdmi2_sink && frame->video_code > 64)
4831 frame->video_code = 0;
4832
4833 /*
4834 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4835 * we should send its VIC in vendor infoframes, else send the
4836 * VIC in AVI infoframes. Lets check if this mode is present in
4837 * HDMI 1.4b 4K modes
4838 */
4839 if (frame->video_code) {
4840 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4841 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4842
4843 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4844 frame->video_code = 0;
4845 }
4846
Thierry Reding10a85122012-11-21 15:31:35 +01004847 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
Vandana Kannan0967e6a2014-04-01 16:26:59 +05304848
Vandana Kannan69ab6d32014-06-05 14:45:29 +05304849 /*
4850 * Populate picture aspect ratio from either
4851 * user input (if specified) or from the CEA mode list.
4852 */
4853 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4854 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4855 frame->picture_aspect = mode->picture_aspect_ratio;
4856 else if (frame->video_code > 0)
Vandana Kannan0967e6a2014-04-01 16:26:59 +05304857 frame->picture_aspect = drm_get_cea_aspect_ratio(
4858 frame->video_code);
4859
Thierry Reding10a85122012-11-21 15:31:35 +01004860 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
Daniel Drake24d018052014-02-27 09:19:30 -06004861 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
Thierry Reding10a85122012-11-21 15:31:35 +01004862
4863 return 0;
4864}
4865EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004866
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004867/**
4868 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4869 * quantization range information
4870 * @frame: HDMI AVI infoframe
Ville Syrjälä779c4c22017-01-11 14:57:24 +02004871 * @mode: DRM display mode
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004872 * @rgb_quant_range: RGB quantization range (Q)
4873 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
Daniel Vetter7cdeb372017-12-14 21:30:50 +01004874 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4875 *
4876 * Note that @is_hdmi2_sink can be derived by looking at the
4877 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4878 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004879 */
4880void
4881drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
Ville Syrjälä779c4c22017-01-11 14:57:24 +02004882 const struct drm_display_mode *mode,
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004883 enum hdmi_quantization_range rgb_quant_range,
Ville Syrjälä9271c0c2017-11-08 17:25:04 +02004884 bool rgb_quant_range_selectable,
4885 bool is_hdmi2_sink)
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004886{
4887 /*
4888 * CEA-861:
4889 * "A Source shall not send a non-zero Q value that does not correspond
4890 * to the default RGB Quantization Range for the transmitted Picture
4891 * unless the Sink indicates support for the Q bit in a Video
4892 * Capabilities Data Block."
Ville Syrjälä779c4c22017-01-11 14:57:24 +02004893 *
4894 * HDMI 2.0 recommends sending non-zero Q when it does match the
4895 * default RGB quantization range for the mode, even when QS=0.
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004896 */
Ville Syrjälä779c4c22017-01-11 14:57:24 +02004897 if (rgb_quant_range_selectable ||
4898 rgb_quant_range == drm_default_rgb_quant_range(mode))
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004899 frame->quantization_range = rgb_quant_range;
4900 else
4901 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
Ville Syrjäläfcc8a222017-01-11 14:57:25 +02004902
4903 /*
4904 * CEA-861-F:
4905 * "When transmitting any RGB colorimetry, the Source should set the
4906 * YQ-field to match the RGB Quantization Range being transmitted
4907 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4908 * set YQ=1) and the Sink shall ignore the YQ-field."
Ville Syrjälä9271c0c2017-11-08 17:25:04 +02004909 *
4910 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4911 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4912 * good way to tell which version of CEA-861 the sink supports, so
4913 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4914 * on on CEA-861-F.
Ville Syrjäläfcc8a222017-01-11 14:57:25 +02004915 */
Ville Syrjälä9271c0c2017-11-08 17:25:04 +02004916 if (!is_hdmi2_sink ||
4917 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
Ville Syrjäläfcc8a222017-01-11 14:57:25 +02004918 frame->ycc_quantization_range =
4919 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4920 else
4921 frame->ycc_quantization_range =
4922 HDMI_YCC_QUANTIZATION_RANGE_FULL;
Ville Syrjäläa2ce26f2017-01-11 14:57:23 +02004923}
4924EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4925
Damien Lespiau4eed4a02013-09-25 16:45:26 +01004926static enum hdmi_3d_structure
4927s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4928{
4929 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4930
4931 switch (layout) {
4932 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4933 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4934 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4935 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4936 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4937 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4938 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4939 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4940 case DRM_MODE_FLAG_3D_L_DEPTH:
4941 return HDMI_3D_STRUCTURE_L_DEPTH;
4942 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4943 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4944 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4945 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4946 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4947 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4948 default:
4949 return HDMI_3D_STRUCTURE_INVALID;
4950 }
4951}
4952
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004953/**
4954 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4955 * data from a DRM display mode
4956 * @frame: HDMI vendor infoframe
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004957 * @connector: the connector
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004958 * @mode: DRM display mode
4959 *
4960 * Note that there's is a need to send HDMI vendor infoframes only when using a
4961 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4962 * function will return -EINVAL, error that can be safely ignored.
4963 *
Thierry Redingdb6cf8332014-04-29 11:44:34 +02004964 * Return: 0 on success or a negative error code on failure.
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004965 */
4966int
4967drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004968 struct drm_connector *connector,
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004969 const struct drm_display_mode *mode)
4970{
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004971 /*
4972 * FIXME: sil-sii8620 doesn't have a connector around when
4973 * we need one, so we have to be prepared for a NULL connector.
4974 */
4975 bool has_hdmi_infoframe = connector ?
4976 connector->display_info.has_hdmi_infoframe : false;
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004977 int err;
Damien Lespiau4eed4a02013-09-25 16:45:26 +01004978 u32 s3d_flags;
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004979 u8 vic;
4980
4981 if (!frame || !mode)
4982 return -EINVAL;
4983
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004984 if (!has_hdmi_infoframe)
4985 return -EINVAL;
4986
Lespiau, Damien83dd0002013-08-19 16:59:03 +01004987 vic = drm_match_hdmi_mode(mode);
Damien Lespiau4eed4a02013-09-25 16:45:26 +01004988 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4989
Ville Syrjäläf1781e92017-11-13 19:04:19 +02004990 /*
4991 * Even if it's not absolutely necessary to send the infoframe
4992 * (ie.vic==0 and s3d_struct==0) we will still send it if we
4993 * know that the sink can handle it. This is based on a
4994 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
4995 * have trouble realizing that they shuld switch from 3D to 2D
4996 * mode if the source simply stops sending the infoframe when
4997 * it wants to switch from 3D to 2D.
4998 */
Damien Lespiau4eed4a02013-09-25 16:45:26 +01004999
5000 if (vic && s3d_flags)
Lespiau, Damien83dd0002013-08-19 16:59:03 +01005001 return -EINVAL;
5002
5003 err = hdmi_vendor_infoframe_init(frame);
5004 if (err < 0)
5005 return err;
5006
Ville Syrjäläf1781e92017-11-13 19:04:19 +02005007 frame->vic = vic;
5008 frame->s3d_struct = s3d_structure_from_display_mode(mode);
Lespiau, Damien83dd0002013-08-19 16:59:03 +01005009
5010 return 0;
5011}
5012EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
Dave Airlie40d9b042014-10-20 16:29:33 +10005013
Dave Airlie5e546cd2016-05-03 15:31:12 +10005014static int drm_parse_tiled_block(struct drm_connector *connector,
5015 struct displayid_block *block)
5016{
5017 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5018 u16 w, h;
5019 u8 tile_v_loc, tile_h_loc;
5020 u8 num_v_tile, num_h_tile;
5021 struct drm_tile_group *tg;
5022
5023 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5024 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5025
5026 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5027 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5028 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5029 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5030
5031 connector->has_tile = true;
5032 if (tile->tile_cap & 0x80)
5033 connector->tile_is_single_monitor = true;
5034
5035 connector->num_h_tile = num_h_tile + 1;
5036 connector->num_v_tile = num_v_tile + 1;
5037 connector->tile_h_loc = tile_h_loc;
5038 connector->tile_v_loc = tile_v_loc;
5039 connector->tile_h_size = w + 1;
5040 connector->tile_v_size = h + 1;
5041
5042 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5043 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5044 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5045 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5046 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5047
5048 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5049 if (!tg) {
5050 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5051 }
5052 if (!tg)
5053 return -ENOMEM;
5054
5055 if (connector->tile_group != tg) {
5056 /* if we haven't got a pointer,
5057 take the reference, drop ref to old tile group */
5058 if (connector->tile_group) {
5059 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5060 }
5061 connector->tile_group = tg;
5062 } else
5063 /* if same tile group, then release the ref we just took. */
5064 drm_mode_put_tile_group(connector->dev, tg);
5065 return 0;
5066}
5067
Dave Airlie40d9b042014-10-20 16:29:33 +10005068static int drm_parse_display_id(struct drm_connector *connector,
5069 u8 *displayid, int length,
5070 bool is_edid_extension)
5071{
5072 /* if this is an EDID extension the first byte will be 0x70 */
5073 int idx = 0;
Dave Airlie40d9b042014-10-20 16:29:33 +10005074 struct displayid_block *block;
Dave Airlie5e546cd2016-05-03 15:31:12 +10005075 int ret;
Dave Airlie40d9b042014-10-20 16:29:33 +10005076
5077 if (is_edid_extension)
5078 idx = 1;
5079
Dave Airliec97291772016-05-03 15:38:37 +10005080 ret = validate_displayid(displayid, length, idx);
5081 if (ret)
5082 return ret;
Dave Airlie40d9b042014-10-20 16:29:33 +10005083
Tomas Bzatek3a4a2ea2016-05-01 15:02:45 +02005084 idx += sizeof(struct displayid_hdr);
5085 while (block = (struct displayid_block *)&displayid[idx],
5086 idx + sizeof(struct displayid_block) <= length &&
5087 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5088 block->num_bytes > 0) {
5089 idx += block->num_bytes + sizeof(struct displayid_block);
5090 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5091 block->tag, block->rev, block->num_bytes);
Dave Airlie40d9b042014-10-20 16:29:33 +10005092
Tomas Bzatek3a4a2ea2016-05-01 15:02:45 +02005093 switch (block->tag) {
5094 case DATA_BLOCK_TILED_DISPLAY:
5095 ret = drm_parse_tiled_block(connector, block);
5096 if (ret)
5097 return ret;
5098 break;
Dave Airliea39ed682016-05-02 08:35:05 +10005099 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5100 /* handled in mode gathering code. */
5101 break;
Tomas Bzatek3a4a2ea2016-05-01 15:02:45 +02005102 default:
5103 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5104 break;
5105 }
Dave Airlie40d9b042014-10-20 16:29:33 +10005106 }
5107 return 0;
5108}
5109
5110static void drm_get_displayid(struct drm_connector *connector,
5111 struct edid *edid)
5112{
5113 void *displayid = NULL;
5114 int ret;
5115 connector->has_tile = false;
5116 displayid = drm_find_displayid_extension(edid);
5117 if (!displayid) {
5118 /* drop reference to any tile group we had */
5119 goto out_drop_ref;
5120 }
5121
5122 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5123 if (ret < 0)
5124 goto out_drop_ref;
5125 if (!connector->has_tile)
5126 goto out_drop_ref;
5127 return;
5128out_drop_ref:
5129 if (connector->tile_group) {
5130 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5131 connector->tile_group = NULL;
5132 }
5133 return;
5134}