blob: bf0048ebbda356a7b03e7f3f56849718ac7ca54d [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Will Newtonf95f3852011-01-02 01:11:59 -05002/*
3 * Synopsys DesignWare Multimedia Card Interface driver
4 * (Based on NXP driver for lpc 31xx)
5 *
6 * Copyright (C) 2009 NXP Semiconductors
7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
Will Newtonf95f3852011-01-02 01:11:59 -05008 */
9
10#include <linux/blkdev.h>
11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/device.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
Shawn Linb6d2d812017-02-17 10:56:39 +080018#include <linux/iopoll.h>
Will Newtonf95f3852011-01-02 01:11:59 -050019#include <linux/ioport.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
Douglas Andersona6db2c82017-04-11 15:55:43 -070022#include <linux/pm_runtime.h>
Will Newtonf95f3852011-01-02 01:11:59 -050023#include <linux/seq_file.h>
24#include <linux/slab.h>
25#include <linux/stat.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
Doug Andersonb24c8b22014-12-02 15:42:46 -080028#include <linux/mmc/card.h>
Will Newtonf95f3852011-01-02 01:11:59 -050029#include <linux/mmc/host.h>
30#include <linux/mmc/mmc.h>
Doug Anderson01730552014-08-22 19:17:51 +053031#include <linux/mmc/sd.h>
Seungwon Jeon90c21432013-08-31 00:14:05 +090032#include <linux/mmc/sdio.h>
Will Newtonf95f3852011-01-02 01:11:59 -050033#include <linux/bitops.h>
Jaehoon Chungc07946a2011-02-25 11:08:14 +090034#include <linux/regulator/consumer.h>
Thomas Abrahamc91eab42012-09-17 18:16:40 +000035#include <linux/of.h>
Doug Anderson55a6ceb2013-01-11 17:03:53 +000036#include <linux/of_gpio.h>
Zhangfei Gaobf626e52014-01-09 22:35:10 +080037#include <linux/mmc/slot-gpio.h>
Will Newtonf95f3852011-01-02 01:11:59 -050038
39#include "dw_mmc.h"
40
41/* Common flag combinations */
Jaehoon Chung3f7eec62013-05-27 13:47:57 +090042#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
Will Newtonf95f3852011-01-02 01:11:59 -050043 SDMMC_INT_HTO | SDMMC_INT_SBE | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070044 SDMMC_INT_EBE | SDMMC_INT_HLE)
Will Newtonf95f3852011-01-02 01:11:59 -050045#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070046 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
Will Newtonf95f3852011-01-02 01:11:59 -050047#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070048 DW_MCI_CMD_ERROR_FLAGS)
Will Newtonf95f3852011-01-02 01:11:59 -050049#define DW_MCI_SEND_STATUS 1
50#define DW_MCI_RECV_STATUS 2
51#define DW_MCI_DMA_THRESHOLD 16
52
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +090053#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
Jaehoon Chung72e83572016-11-17 16:40:35 +090054#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +090055
Joonyoung Shimfc79a4d2013-04-26 15:35:22 +090056#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
57 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
58 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
59 SDMMC_IDMAC_INT_TI)
60
Shawn Lincc190d42016-09-02 12:14:39 +080061#define DESC_RING_BUF_SZ PAGE_SIZE
62
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +000063struct idmac_desc_64addr {
64 u32 des0; /* Control Descriptor */
Shawn Linb6d2d812017-02-17 10:56:39 +080065#define IDMAC_OWN_CLR64(x) \
66 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +000067
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
Ben Dooks6687c422015-03-25 11:27:51 +000072 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +000074
75 u32 des3; /* Reserved */
76
77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79
80 u32 des6; /* Lower 32-bits of Next Descriptor Address */
81 u32 des7; /* Upper 32-bits of Next Descriptor Address */
82};
83
Will Newtonf95f3852011-01-02 01:11:59 -050084struct idmac_desc {
Ben Dooks6687c422015-03-25 11:27:51 +000085 __le32 des0; /* Control Descriptor */
Will Newtonf95f3852011-01-02 01:11:59 -050086#define IDMAC_DES0_DIC BIT(1)
87#define IDMAC_DES0_LD BIT(2)
88#define IDMAC_DES0_FD BIT(3)
89#define IDMAC_DES0_CH BIT(4)
90#define IDMAC_DES0_ER BIT(5)
91#define IDMAC_DES0_CES BIT(30)
92#define IDMAC_DES0_OWN BIT(31)
93
Ben Dooks6687c422015-03-25 11:27:51 +000094 __le32 des1; /* Buffer sizes */
Will Newtonf95f3852011-01-02 01:11:59 -050095#define IDMAC_SET_BUFFER1_SIZE(d, s) \
Ben Dookse5306c32016-06-07 14:37:19 +010096 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
Will Newtonf95f3852011-01-02 01:11:59 -050097
Ben Dooks6687c422015-03-25 11:27:51 +000098 __le32 des2; /* buffer 1 physical address */
Will Newtonf95f3852011-01-02 01:11:59 -050099
Ben Dooks6687c422015-03-25 11:27:51 +0000100 __le32 des3; /* buffer 2 physical address */
Will Newtonf95f3852011-01-02 01:11:59 -0500101};
Alexey Brodkin5959b322015-06-25 11:25:07 +0300102
103/* Each descriptor can transfer up to 4KB of data in chained mode */
104#define DW_MCI_DESC_DATA_LENGTH 0x1000
Will Newtonf95f3852011-01-02 01:11:59 -0500105
Will Newtonf95f3852011-01-02 01:11:59 -0500106#if defined(CONFIG_DEBUG_FS)
107static int dw_mci_req_show(struct seq_file *s, void *v)
108{
109 struct dw_mci_slot *slot = s->private;
110 struct mmc_request *mrq;
111 struct mmc_command *cmd;
112 struct mmc_command *stop;
113 struct mmc_data *data;
114
115 /* Make sure we get a consistent snapshot */
116 spin_lock_bh(&slot->host->lock);
117 mrq = slot->mrq;
118
119 if (mrq) {
120 cmd = mrq->cmd;
121 data = mrq->data;
122 stop = mrq->stop;
123
124 if (cmd)
125 seq_printf(s,
126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127 cmd->opcode, cmd->arg, cmd->flags,
128 cmd->resp[0], cmd->resp[1], cmd->resp[2],
129 cmd->resp[2], cmd->error);
130 if (data)
131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132 data->bytes_xfered, data->blocks,
133 data->blksz, data->flags, data->error);
134 if (stop)
135 seq_printf(s,
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 stop->opcode, stop->arg, stop->flags,
138 stop->resp[0], stop->resp[1], stop->resp[2],
139 stop->resp[2], stop->error);
140 }
141
142 spin_unlock_bh(&slot->host->lock);
143
144 return 0;
145}
Shawn Lin64c1412b2018-02-23 16:47:26 +0800146DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
Will Newtonf95f3852011-01-02 01:11:59 -0500147
148static int dw_mci_regs_show(struct seq_file *s, void *v)
149{
Jaehoon Chung21657ebd2016-11-17 16:40:33 +0900150 struct dw_mci *host = s->private;
151
Shawn Lin5b43df82018-02-23 16:47:25 +0800152 pm_runtime_get_sync(host->dev);
153
Jaehoon Chung21657ebd2016-11-17 16:40:33 +0900154 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
155 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
156 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
157 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
158 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
159 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
Will Newtonf95f3852011-01-02 01:11:59 -0500160
Shawn Lin5b43df82018-02-23 16:47:25 +0800161 pm_runtime_put_autosuspend(host->dev);
162
Will Newtonf95f3852011-01-02 01:11:59 -0500163 return 0;
164}
Shawn Lin64c1412b2018-02-23 16:47:26 +0800165DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
Will Newtonf95f3852011-01-02 01:11:59 -0500166
167static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
168{
169 struct mmc_host *mmc = slot->mmc;
170 struct dw_mci *host = slot->host;
171 struct dentry *root;
Will Newtonf95f3852011-01-02 01:11:59 -0500172
173 root = mmc->debugfs_root;
174 if (!root)
175 return;
176
Greg Kroah-Hartmanfcac1522019-06-12 10:25:30 +0200177 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
178 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
179 debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
180 debugfs_create_x32("pending_events", S_IRUSR, root,
181 (u32 *)&host->pending_events);
182 debugfs_create_x32("completed_events", S_IRUSR, root,
183 (u32 *)&host->completed_events);
Will Newtonf95f3852011-01-02 01:11:59 -0500184}
185#endif /* defined(CONFIG_DEBUG_FS) */
186
Shawn Lin8e6db1f2017-02-17 10:56:41 +0800187static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
188{
189 u32 ctrl;
190
191 ctrl = mci_readl(host, CTRL);
192 ctrl |= reset;
193 mci_writel(host, CTRL, ctrl);
194
195 /* wait till resets clear */
196 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
197 !(ctrl & reset),
198 1, 500 * USEC_PER_MSEC)) {
199 dev_err(host->dev,
200 "Timeout resetting block (ctrl reset %#x)\n",
201 ctrl & reset);
202 return false;
203 }
204
205 return true;
206}
Doug Anderson01730552014-08-22 19:17:51 +0530207
Shawn Lin4dba18d2017-02-17 10:59:44 +0800208static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
209{
210 u32 status;
211
212 /*
213 * Databook says that before issuing a new data transfer command
214 * we need to check to see if the card is busy. Data transfer commands
215 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
216 *
217 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
218 * expected.
219 */
220 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
221 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
222 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
223 status,
224 !(status & SDMMC_STATUS_BUSY),
225 10, 500 * USEC_PER_MSEC))
226 dev_err(host->dev, "Busy; trying anyway\n");
227 }
228}
229
230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
231{
232 struct dw_mci *host = slot->host;
233 unsigned int cmd_status = 0;
234
235 mci_writel(host, CMDARG, arg);
236 wmb(); /* drain writebuffer */
237 dw_mci_wait_while_busy(host, cmd);
238 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
239
240 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
241 !(cmd_status & SDMMC_CMD_START),
242 1, 500 * USEC_PER_MSEC))
243 dev_err(&slot->mmc->class_dev,
244 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
245 cmd, arg, cmd_status);
246}
247
Will Newtonf95f3852011-01-02 01:11:59 -0500248static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
249{
Thomas Abraham800d78b2012-09-17 18:16:42 +0000250 struct dw_mci_slot *slot = mmc_priv(mmc);
Doug Anderson01730552014-08-22 19:17:51 +0530251 struct dw_mci *host = slot->host;
Will Newtonf95f3852011-01-02 01:11:59 -0500252 u32 cmdr;
Will Newtonf95f3852011-01-02 01:11:59 -0500253
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800254 cmd->error = -EINPROGRESS;
Will Newtonf95f3852011-01-02 01:11:59 -0500255 cmdr = cmd->opcode;
256
Seungwon Jeon90c21432013-08-31 00:14:05 +0900257 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
258 cmd->opcode == MMC_GO_IDLE_STATE ||
259 cmd->opcode == MMC_GO_INACTIVE_STATE ||
260 (cmd->opcode == SD_IO_RW_DIRECT &&
261 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
Will Newtonf95f3852011-01-02 01:11:59 -0500262 cmdr |= SDMMC_CMD_STOP;
Jaehoon Chung4a1b27a2014-03-03 11:36:44 +0900263 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
264 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
Will Newtonf95f3852011-01-02 01:11:59 -0500265
Doug Anderson01730552014-08-22 19:17:51 +0530266 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
267 u32 clk_en_a;
268
269 /* Special bit makes CMD11 not die */
270 cmdr |= SDMMC_CMD_VOLT_SWITCH;
271
272 /* Change state to continue to handle CMD11 weirdness */
273 WARN_ON(slot->host->state != STATE_SENDING_CMD);
274 slot->host->state = STATE_SENDING_CMD11;
275
276 /*
277 * We need to disable low power mode (automatic clock stop)
278 * while doing voltage switch so we don't confuse the card,
279 * since stopping the clock is a specific part of the UHS
280 * voltage change dance.
281 *
282 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
283 * unconditionally turned back on in dw_mci_setup_bus() if it's
284 * ever called with a non-zero clock. That shouldn't happen
285 * until the voltage change is all done.
286 */
287 clk_en_a = mci_readl(host, CLKENA);
288 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
289 mci_writel(host, CLKENA, clk_en_a);
290 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
291 SDMMC_CMD_PRV_DAT_WAIT, 0);
292 }
293
Will Newtonf95f3852011-01-02 01:11:59 -0500294 if (cmd->flags & MMC_RSP_PRESENT) {
295 /* We expect a response, so set this bit */
296 cmdr |= SDMMC_CMD_RESP_EXP;
297 if (cmd->flags & MMC_RSP_136)
298 cmdr |= SDMMC_CMD_RESP_LONG;
299 }
300
301 if (cmd->flags & MMC_RSP_CRC)
302 cmdr |= SDMMC_CMD_RESP_CRC;
303
Jaehoon Chung0349c082016-11-17 16:40:39 +0900304 if (cmd->data) {
Will Newtonf95f3852011-01-02 01:11:59 -0500305 cmdr |= SDMMC_CMD_DAT_EXP;
Jaehoon Chung0349c082016-11-17 16:40:39 +0900306 if (cmd->data->flags & MMC_DATA_WRITE)
Will Newtonf95f3852011-01-02 01:11:59 -0500307 cmdr |= SDMMC_CMD_DAT_WR;
308 }
309
Jaehoon Chungaaaaeb72016-01-21 11:01:06 +0900310 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
311 cmdr |= SDMMC_CMD_USE_HOLD_REG;
Thomas Abraham800d78b2012-09-17 18:16:42 +0000312
Will Newtonf95f3852011-01-02 01:11:59 -0500313 return cmdr;
314}
315
Seungwon Jeon90c21432013-08-31 00:14:05 +0900316static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
317{
318 struct mmc_command *stop;
319 u32 cmdr;
320
321 if (!cmd->data)
322 return 0;
323
324 stop = &host->stop_abort;
325 cmdr = cmd->opcode;
326 memset(stop, 0, sizeof(struct mmc_command));
327
328 if (cmdr == MMC_READ_SINGLE_BLOCK ||
329 cmdr == MMC_READ_MULTIPLE_BLOCK ||
330 cmdr == MMC_WRITE_BLOCK ||
Ulf Hansson6c2c6502014-12-01 16:13:39 +0100331 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
332 cmdr == MMC_SEND_TUNING_BLOCK ||
333 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
Seungwon Jeon90c21432013-08-31 00:14:05 +0900334 stop->opcode = MMC_STOP_TRANSMISSION;
335 stop->arg = 0;
336 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
337 } else if (cmdr == SD_IO_RW_EXTENDED) {
338 stop->opcode = SD_IO_RW_DIRECT;
339 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
340 ((cmd->arg >> 28) & 0x7);
341 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
342 } else {
343 return 0;
344 }
345
346 cmdr = stop->opcode | SDMMC_CMD_STOP |
347 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
348
Jaehoon Chung42f989c2017-06-05 13:41:34 +0900349 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
Jaehoon Chung8c005b42016-11-17 16:40:36 +0900350 cmdr |= SDMMC_CMD_USE_HOLD_REG;
351
Seungwon Jeon90c21432013-08-31 00:14:05 +0900352 return cmdr;
353}
354
Addy Ke03de1922017-07-11 17:38:37 +0800355static inline void dw_mci_set_cto(struct dw_mci *host)
356{
357 unsigned int cto_clks;
Douglas Anderson4c2357f2017-10-12 13:11:15 -0700358 unsigned int cto_div;
Addy Ke03de1922017-07-11 17:38:37 +0800359 unsigned int cto_ms;
Douglas Anderson8892b702017-10-12 13:11:16 -0700360 unsigned long irqflags;
Addy Ke03de1922017-07-11 17:38:37 +0800361
362 cto_clks = mci_readl(host, TMOUT) & 0xff;
Douglas Anderson4c2357f2017-10-12 13:11:15 -0700363 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
364 if (cto_div == 0)
365 cto_div = 1;
Evgeniy Didinc7151602018-02-28 14:53:18 +0300366
367 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
368 host->bus_hz);
Addy Ke03de1922017-07-11 17:38:37 +0800369
370 /* add a bit spare time */
371 cto_ms += 10;
372
Douglas Anderson8892b702017-10-12 13:11:16 -0700373 /*
374 * The durations we're working with are fairly short so we have to be
375 * extra careful about synchronization here. Specifically in hardware a
376 * command timeout is _at most_ 5.1 ms, so that means we expect an
377 * interrupt (either command done or timeout) to come rather quickly
378 * after the mci_writel. ...but just in case we have a long interrupt
379 * latency let's add a bit of paranoia.
380 *
381 * In general we'll assume that at least an interrupt will be asserted
382 * in hardware by the time the cto_timer runs. ...and if it hasn't
383 * been asserted in hardware by that time then we'll assume it'll never
384 * come.
385 */
386 spin_lock_irqsave(&host->irq_lock, irqflags);
387 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
388 mod_timer(&host->cto_timer,
389 jiffies + msecs_to_jiffies(cto_ms) + 1);
390 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Addy Ke03de1922017-07-11 17:38:37 +0800391}
392
Will Newtonf95f3852011-01-02 01:11:59 -0500393static void dw_mci_start_command(struct dw_mci *host,
394 struct mmc_command *cmd, u32 cmd_flags)
395{
396 host->cmd = cmd;
Thomas Abraham4a909202012-09-17 18:16:35 +0000397 dev_vdbg(host->dev,
Will Newtonf95f3852011-01-02 01:11:59 -0500398 "start command: ARGR=0x%08x CMDR=0x%08x\n",
399 cmd->arg, cmd_flags);
400
401 mci_writel(host, CMDARG, cmd->arg);
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800402 wmb(); /* drain writebuffer */
Doug Anderson0bdbd0e2015-02-20 12:31:56 -0800403 dw_mci_wait_while_busy(host, cmd_flags);
Will Newtonf95f3852011-01-02 01:11:59 -0500404
Douglas Anderson8892b702017-10-12 13:11:16 -0700405 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
406
Addy Ke03de1922017-07-11 17:38:37 +0800407 /* response expected command only */
408 if (cmd_flags & SDMMC_CMD_RESP_EXP)
409 dw_mci_set_cto(host);
Will Newtonf95f3852011-01-02 01:11:59 -0500410}
411
Seungwon Jeon90c21432013-08-31 00:14:05 +0900412static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
Will Newtonf95f3852011-01-02 01:11:59 -0500413{
Jaehoon Chunge13c3c02016-11-17 16:40:37 +0900414 struct mmc_command *stop = &host->stop_abort;
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800415
Seungwon Jeon90c21432013-08-31 00:14:05 +0900416 dw_mci_start_command(host, stop, host->stop_cmdr);
Will Newtonf95f3852011-01-02 01:11:59 -0500417}
418
419/* DMA interface functions */
420static void dw_mci_stop_dma(struct dw_mci *host)
421{
James Hogan03e8cb52011-06-29 09:28:43 +0100422 if (host->using_dma) {
Will Newtonf95f3852011-01-02 01:11:59 -0500423 host->dma_ops->stop(host);
424 host->dma_ops->cleanup(host);
Will Newtonf95f3852011-01-02 01:11:59 -0500425 }
Seungwon Jeonaa50f252013-08-31 00:14:38 +0900426
427 /* Data transfer was stopped by the interrupt handler */
428 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
Will Newtonf95f3852011-01-02 01:11:59 -0500429}
430
Will Newtonf95f3852011-01-02 01:11:59 -0500431static void dw_mci_dma_cleanup(struct dw_mci *host)
432{
433 struct mmc_data *data = host->data;
434
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900435 if (data && data->host_cookie == COOKIE_MAPPED) {
436 dma_unmap_sg(host->dev,
437 data->sg,
438 data->sg_len,
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200439 mmc_get_dma_dir(data));
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900440 data->host_cookie = COOKIE_UNMAPPED;
441 }
Will Newtonf95f3852011-01-02 01:11:59 -0500442}
443
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900444static void dw_mci_idmac_reset(struct dw_mci *host)
445{
446 u32 bmod = mci_readl(host, BMOD);
447 /* Software reset of DMA */
448 bmod |= SDMMC_IDMAC_SWRESET;
449 mci_writel(host, BMOD, bmod);
450}
451
Will Newtonf95f3852011-01-02 01:11:59 -0500452static void dw_mci_idmac_stop_dma(struct dw_mci *host)
453{
454 u32 temp;
455
456 /* Disable and reset the IDMAC interface */
457 temp = mci_readl(host, CTRL);
458 temp &= ~SDMMC_CTRL_USE_IDMAC;
459 temp |= SDMMC_CTRL_DMA_RESET;
460 mci_writel(host, CTRL, temp);
461
462 /* Stop the IDMAC running */
463 temp = mci_readl(host, BMOD);
Jaehoon Chunga5289a42011-02-25 11:08:13 +0900464 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900465 temp |= SDMMC_IDMAC_SWRESET;
Will Newtonf95f3852011-01-02 01:11:59 -0500466 mci_writel(host, BMOD, temp);
467}
468
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800469static void dw_mci_dmac_complete_dma(void *arg)
Will Newtonf95f3852011-01-02 01:11:59 -0500470{
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800471 struct dw_mci *host = arg;
Will Newtonf95f3852011-01-02 01:11:59 -0500472 struct mmc_data *data = host->data;
473
Thomas Abraham4a909202012-09-17 18:16:35 +0000474 dev_vdbg(host->dev, "DMA complete\n");
Will Newtonf95f3852011-01-02 01:11:59 -0500475
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800476 if ((host->use_dma == TRANS_MODE_EDMAC) &&
477 data && (data->flags & MMC_DATA_READ))
478 /* Invalidate cache after read */
Jaehoon Chung42f989c2017-06-05 13:41:34 +0900479 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800480 data->sg,
481 data->sg_len,
482 DMA_FROM_DEVICE);
483
Will Newtonf95f3852011-01-02 01:11:59 -0500484 host->dma_ops->cleanup(host);
485
486 /*
487 * If the card was removed, data will be NULL. No point in trying to
488 * send the stop command or waiting for NBUSY in this case.
489 */
490 if (data) {
491 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
492 tasklet_schedule(&host->tasklet);
493 }
494}
495
Will Newtonf95f3852011-01-02 01:11:59 -0500496static int dw_mci_idmac_init(struct dw_mci *host)
497{
Seungwon Jeon897b69e2012-09-19 13:58:31 +0800498 int i;
Will Newtonf95f3852011-01-02 01:11:59 -0500499
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000500 if (host->dma_64bit_address == 1) {
501 struct idmac_desc_64addr *p;
502 /* Number of descriptors in the ring buffer */
Shawn Lincc190d42016-09-02 12:14:39 +0800503 host->ring_size =
504 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
Will Newtonf95f3852011-01-02 01:11:59 -0500505
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000506 /* Forward link the descriptor list */
507 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
508 i++, p++) {
509 p->des6 = (host->sg_dma +
510 (sizeof(struct idmac_desc_64addr) *
511 (i + 1))) & 0xffffffff;
Will Newtonf95f3852011-01-02 01:11:59 -0500512
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000513 p->des7 = (u64)(host->sg_dma +
514 (sizeof(struct idmac_desc_64addr) *
515 (i + 1))) >> 32;
516 /* Initialize reserved and buffer size fields to "0" */
Evgeniy Didin47b7de22018-03-14 22:30:51 +0300517 p->des0 = 0;
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000518 p->des1 = 0;
519 p->des2 = 0;
520 p->des3 = 0;
521 }
522
523 /* Set the last descriptor as the end-of-ring descriptor */
524 p->des6 = host->sg_dma & 0xffffffff;
525 p->des7 = (u64)host->sg_dma >> 32;
526 p->des0 = IDMAC_DES0_ER;
527
528 } else {
529 struct idmac_desc *p;
530 /* Number of descriptors in the ring buffer */
Shawn Lincc190d42016-09-02 12:14:39 +0800531 host->ring_size =
532 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000533
534 /* Forward link the descriptor list */
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800535 for (i = 0, p = host->sg_cpu;
536 i < host->ring_size - 1;
537 i++, p++) {
Ben Dooks6687c422015-03-25 11:27:51 +0000538 p->des3 = cpu_to_le32(host->sg_dma +
539 (sizeof(struct idmac_desc) * (i + 1)));
Evgeniy Didin47b7de22018-03-14 22:30:51 +0300540 p->des0 = 0;
Zhangfei Gao4b244722015-04-30 22:16:28 +0800541 p->des1 = 0;
542 }
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000543
544 /* Set the last descriptor as the end-of-ring descriptor */
Ben Dooks6687c422015-03-25 11:27:51 +0000545 p->des3 = cpu_to_le32(host->sg_dma);
546 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000547 }
Will Newtonf95f3852011-01-02 01:11:59 -0500548
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900549 dw_mci_idmac_reset(host);
Seungwon Jeon141a7122012-05-22 13:01:03 +0900550
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000551 if (host->dma_64bit_address == 1) {
552 /* Mask out interrupts - get Tx & Rx complete only */
553 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
554 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
555 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
Will Newtonf95f3852011-01-02 01:11:59 -0500556
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000557 /* Set the descriptor base address */
558 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
559 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
560
561 } else {
562 /* Mask out interrupts - get Tx & Rx complete only */
563 mci_writel(host, IDSTS, IDMAC_INT_CLR);
564 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
565 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
566
567 /* Set the descriptor base address */
568 mci_writel(host, DBADDR, host->sg_dma);
569 }
570
Will Newtonf95f3852011-01-02 01:11:59 -0500571 return 0;
572}
573
Shawn Lin3b2a0672016-09-02 12:14:37 +0800574static inline int dw_mci_prepare_desc64(struct dw_mci *host,
575 struct mmc_data *data,
576 unsigned int sg_len)
577{
578 unsigned int desc_len;
579 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
Shawn Linb6d2d812017-02-17 10:56:39 +0800580 u32 val;
Shawn Lin3b2a0672016-09-02 12:14:37 +0800581 int i;
582
583 desc_first = desc_last = desc = host->sg_cpu;
584
585 for (i = 0; i < sg_len; i++) {
586 unsigned int length = sg_dma_len(&data->sg[i]);
587
588 u64 mem_addr = sg_dma_address(&data->sg[i]);
589
590 for ( ; length ; desc++) {
591 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
592 length : DW_MCI_DESC_DATA_LENGTH;
593
594 length -= desc_len;
595
596 /*
597 * Wait for the former clear OWN bit operation
598 * of IDMAC to make sure that this descriptor
599 * isn't still owned by IDMAC as IDMAC's write
600 * ops and CPU's read ops are asynchronous.
601 */
Shawn Linb6d2d812017-02-17 10:56:39 +0800602 if (readl_poll_timeout_atomic(&desc->des0, val,
603 !(val & IDMAC_DES0_OWN),
604 10, 100 * USEC_PER_MSEC))
605 goto err_own_bit;
Shawn Lin3b2a0672016-09-02 12:14:37 +0800606
607 /*
608 * Set the OWN bit and disable interrupts
609 * for this descriptor
610 */
611 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
612 IDMAC_DES0_CH;
613
614 /* Buffer length */
615 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
616
617 /* Physical address to DMA to/from */
618 desc->des4 = mem_addr & 0xffffffff;
619 desc->des5 = mem_addr >> 32;
620
621 /* Update physical address for the next desc */
622 mem_addr += desc_len;
623
624 /* Save pointer to the last descriptor */
625 desc_last = desc;
626 }
627 }
628
629 /* Set first descriptor */
630 desc_first->des0 |= IDMAC_DES0_FD;
631
632 /* Set last descriptor */
633 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
634 desc_last->des0 |= IDMAC_DES0_LD;
635
636 return 0;
637err_own_bit:
638 /* restore the descriptor chain as it's polluted */
Colin Ian King26be9d72016-11-16 18:55:01 +0000639 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
Shawn Lincc190d42016-09-02 12:14:39 +0800640 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
Shawn Lin3b2a0672016-09-02 12:14:37 +0800641 dw_mci_idmac_init(host);
642 return -EINVAL;
643}
644
645
646static inline int dw_mci_prepare_desc32(struct dw_mci *host,
647 struct mmc_data *data,
648 unsigned int sg_len)
649{
650 unsigned int desc_len;
651 struct idmac_desc *desc_first, *desc_last, *desc;
Shawn Linb6d2d812017-02-17 10:56:39 +0800652 u32 val;
Shawn Lin3b2a0672016-09-02 12:14:37 +0800653 int i;
654
655 desc_first = desc_last = desc = host->sg_cpu;
656
657 for (i = 0; i < sg_len; i++) {
658 unsigned int length = sg_dma_len(&data->sg[i]);
659
660 u32 mem_addr = sg_dma_address(&data->sg[i]);
661
662 for ( ; length ; desc++) {
663 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
664 length : DW_MCI_DESC_DATA_LENGTH;
665
666 length -= desc_len;
667
668 /*
669 * Wait for the former clear OWN bit operation
670 * of IDMAC to make sure that this descriptor
671 * isn't still owned by IDMAC as IDMAC's write
672 * ops and CPU's read ops are asynchronous.
673 */
Shawn Linb6d2d812017-02-17 10:56:39 +0800674 if (readl_poll_timeout_atomic(&desc->des0, val,
675 IDMAC_OWN_CLR64(val),
676 10,
677 100 * USEC_PER_MSEC))
678 goto err_own_bit;
Shawn Lin3b2a0672016-09-02 12:14:37 +0800679
680 /*
681 * Set the OWN bit and disable interrupts
682 * for this descriptor
683 */
684 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
685 IDMAC_DES0_DIC |
686 IDMAC_DES0_CH);
687
688 /* Buffer length */
689 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
690
691 /* Physical address to DMA to/from */
692 desc->des2 = cpu_to_le32(mem_addr);
693
694 /* Update physical address for the next desc */
695 mem_addr += desc_len;
696
697 /* Save pointer to the last descriptor */
698 desc_last = desc;
699 }
700 }
701
702 /* Set first descriptor */
703 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
704
705 /* Set last descriptor */
706 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
707 IDMAC_DES0_DIC));
708 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
709
710 return 0;
711err_own_bit:
712 /* restore the descriptor chain as it's polluted */
Colin Ian King26be9d72016-11-16 18:55:01 +0000713 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
Shawn Lincc190d42016-09-02 12:14:39 +0800714 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
Shawn Lin3b2a0672016-09-02 12:14:37 +0800715 dw_mci_idmac_init(host);
716 return -EINVAL;
717}
718
719static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
720{
721 u32 temp;
722 int ret;
723
724 if (host->dma_64bit_address == 1)
725 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
726 else
727 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
728
729 if (ret)
730 goto out;
731
732 /* drain writebuffer */
733 wmb();
734
735 /* Make sure to reset DMA in case we did PIO before this */
736 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
737 dw_mci_idmac_reset(host);
738
739 /* Select IDMAC interface */
740 temp = mci_readl(host, CTRL);
741 temp |= SDMMC_CTRL_USE_IDMAC;
742 mci_writel(host, CTRL, temp);
743
744 /* drain writebuffer */
745 wmb();
746
747 /* Enable the IDMAC */
748 temp = mci_readl(host, BMOD);
749 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
750 mci_writel(host, BMOD, temp);
751
752 /* Start it running */
753 mci_writel(host, PLDMND, 1);
754
755out:
756 return ret;
757}
758
Arnd Bergmann8e2b36e2012-11-06 22:55:31 +0100759static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900760 .init = dw_mci_idmac_init,
761 .start = dw_mci_idmac_start_dma,
762 .stop = dw_mci_idmac_stop_dma,
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800763 .complete = dw_mci_dmac_complete_dma,
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900764 .cleanup = dw_mci_dma_cleanup,
765};
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800766
767static void dw_mci_edmac_stop_dma(struct dw_mci *host)
768{
Shawn Linab925a32016-03-09 10:34:46 +0800769 dmaengine_terminate_async(host->dms->ch);
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800770}
771
772static int dw_mci_edmac_start_dma(struct dw_mci *host,
773 unsigned int sg_len)
774{
775 struct dma_slave_config cfg;
776 struct dma_async_tx_descriptor *desc = NULL;
777 struct scatterlist *sgl = host->data->sg;
Colin Ian King27d70d362017-09-03 14:39:50 +0100778 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800779 u32 sg_elems = host->data->sg_len;
780 u32 fifoth_val;
781 u32 fifo_offset = host->fifo_reg - host->regs;
782 int ret = 0;
783
784 /* Set external dma config: burst size, burst width */
Arnd Bergmann260b3162015-11-12 15:14:23 +0100785 cfg.dst_addr = host->phy_regs + fifo_offset;
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800786 cfg.src_addr = cfg.dst_addr;
787 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
788 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
789
790 /* Match burst msize with external dma config */
791 fifoth_val = mci_readl(host, FIFOTH);
792 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
793 cfg.src_maxburst = cfg.dst_maxburst;
794
795 if (host->data->flags & MMC_DATA_WRITE)
796 cfg.direction = DMA_MEM_TO_DEV;
797 else
798 cfg.direction = DMA_DEV_TO_MEM;
799
800 ret = dmaengine_slave_config(host->dms->ch, &cfg);
801 if (ret) {
802 dev_err(host->dev, "Failed to config edmac.\n");
803 return -EBUSY;
804 }
805
806 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
807 sg_len, cfg.direction,
808 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
809 if (!desc) {
810 dev_err(host->dev, "Can't prepare slave sg.\n");
811 return -EBUSY;
812 }
813
814 /* Set dw_mci_dmac_complete_dma as callback */
815 desc->callback = dw_mci_dmac_complete_dma;
816 desc->callback_param = (void *)host;
817 dmaengine_submit(desc);
818
819 /* Flush cache before write */
820 if (host->data->flags & MMC_DATA_WRITE)
Jaehoon Chung42f989c2017-06-05 13:41:34 +0900821 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800822 sg_elems, DMA_TO_DEVICE);
823
824 dma_async_issue_pending(host->dms->ch);
825
826 return 0;
827}
828
829static int dw_mci_edmac_init(struct dw_mci *host)
830{
831 /* Request external dma channel */
832 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
833 if (!host->dms)
834 return -ENOMEM;
835
836 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
837 if (!host->dms->ch) {
Dan Carpenter4539d362015-10-22 22:53:46 +0300838 dev_err(host->dev, "Failed to get external DMA channel.\n");
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800839 kfree(host->dms);
840 host->dms = NULL;
841 return -ENXIO;
842 }
843
844 return 0;
845}
846
847static void dw_mci_edmac_exit(struct dw_mci *host)
848{
849 if (host->dms) {
850 if (host->dms->ch) {
851 dma_release_channel(host->dms->ch);
852 host->dms->ch = NULL;
853 }
854 kfree(host->dms);
855 host->dms = NULL;
856 }
857}
858
859static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
860 .init = dw_mci_edmac_init,
861 .exit = dw_mci_edmac_exit,
862 .start = dw_mci_edmac_start_dma,
863 .stop = dw_mci_edmac_stop_dma,
864 .complete = dw_mci_dmac_complete_dma,
865 .cleanup = dw_mci_dma_cleanup,
866};
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900867
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900868static int dw_mci_pre_dma_transfer(struct dw_mci *host,
869 struct mmc_data *data,
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900870 int cookie)
Will Newtonf95f3852011-01-02 01:11:59 -0500871{
872 struct scatterlist *sg;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900873 unsigned int i, sg_len;
Will Newtonf95f3852011-01-02 01:11:59 -0500874
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900875 if (data->host_cookie == COOKIE_PRE_MAPPED)
876 return data->sg_len;
Will Newtonf95f3852011-01-02 01:11:59 -0500877
878 /*
879 * We don't do DMA on "complex" transfers, i.e. with
880 * non-word-aligned buffers or lengths. Also, we don't bother
881 * with all the DMA setup overhead for short transfers.
882 */
883 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
884 return -EINVAL;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900885
Will Newtonf95f3852011-01-02 01:11:59 -0500886 if (data->blksz & 3)
887 return -EINVAL;
888
889 for_each_sg(data->sg, sg, data->sg_len, i) {
890 if (sg->offset & 3 || sg->length & 3)
891 return -EINVAL;
892 }
893
Thomas Abraham4a909202012-09-17 18:16:35 +0000894 sg_len = dma_map_sg(host->dev,
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900895 data->sg,
896 data->sg_len,
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200897 mmc_get_dma_dir(data));
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900898 if (sg_len == 0)
899 return -EINVAL;
900
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900901 data->host_cookie = cookie;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900902
903 return sg_len;
904}
905
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900906static void dw_mci_pre_req(struct mmc_host *mmc,
Linus Walleijd3c6aac2016-11-23 11:02:24 +0100907 struct mmc_request *mrq)
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900908{
909 struct dw_mci_slot *slot = mmc_priv(mmc);
910 struct mmc_data *data = mrq->data;
911
912 if (!slot->host->use_dma || !data)
913 return;
914
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900915 /* This data might be unmapped at this time */
916 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900917
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900918 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
919 COOKIE_PRE_MAPPED) < 0)
920 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900921}
922
923static void dw_mci_post_req(struct mmc_host *mmc,
924 struct mmc_request *mrq,
925 int err)
926{
927 struct dw_mci_slot *slot = mmc_priv(mmc);
928 struct mmc_data *data = mrq->data;
929
930 if (!slot->host->use_dma || !data)
931 return;
932
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900933 if (data->host_cookie != COOKIE_UNMAPPED)
Thomas Abraham4a909202012-09-17 18:16:35 +0000934 dma_unmap_sg(slot->host->dev,
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900935 data->sg,
936 data->sg_len,
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200937 mmc_get_dma_dir(data));
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900938 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900939}
940
Shawn Lin671fa142017-02-17 10:56:42 +0800941static int dw_mci_get_cd(struct mmc_host *mmc)
942{
943 int present;
944 struct dw_mci_slot *slot = mmc_priv(mmc);
945 struct dw_mci *host = slot->host;
946 int gpio_cd = mmc_gpio_get_cd(mmc);
947
948 /* Use platform get_cd function, else try onboard card detect */
949 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
950 || !mmc_card_is_removable(mmc))) {
951 present = 1;
952
953 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
954 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
955 dev_info(&mmc->class_dev,
956 "card is polling.\n");
957 } else {
958 dev_info(&mmc->class_dev,
959 "card is non-removable.\n");
960 }
961 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
962 }
963
964 return present;
965 } else if (gpio_cd >= 0)
966 present = gpio_cd;
967 else
968 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
969 == 0 ? 1 : 0;
970
971 spin_lock_bh(&host->lock);
972 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
973 dev_dbg(&mmc->class_dev, "card is present\n");
974 else if (!present &&
975 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
976 dev_dbg(&mmc->class_dev, "card is not present\n");
977 spin_unlock_bh(&host->lock);
978
979 return present;
980}
981
Seungwon Jeon52426892013-08-31 00:13:42 +0900982static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
983{
Seungwon Jeon52426892013-08-31 00:13:42 +0900984 unsigned int blksz = data->blksz;
Colin Ian King27d70d362017-09-03 14:39:50 +0100985 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
Seungwon Jeon52426892013-08-31 00:13:42 +0900986 u32 fifo_width = 1 << host->data_shift;
987 u32 blksz_depth = blksz / fifo_width, fifoth_val;
988 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800989 int idx = ARRAY_SIZE(mszs) - 1;
Seungwon Jeon52426892013-08-31 00:13:42 +0900990
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800991 /* pio should ship this scenario */
992 if (!host->use_dma)
993 return;
994
Seungwon Jeon52426892013-08-31 00:13:42 +0900995 tx_wmark = (host->fifo_depth) / 2;
996 tx_wmark_invers = host->fifo_depth - tx_wmark;
997
998 /*
999 * MSIZE is '1',
1000 * if blksz is not a multiple of the FIFO width
1001 */
Shawn Lin20753562016-09-21 10:40:25 +08001002 if (blksz % fifo_width)
Seungwon Jeon52426892013-08-31 00:13:42 +09001003 goto done;
Seungwon Jeon52426892013-08-31 00:13:42 +09001004
1005 do {
1006 if (!((blksz_depth % mszs[idx]) ||
1007 (tx_wmark_invers % mszs[idx]))) {
1008 msize = idx;
1009 rx_wmark = mszs[idx] - 1;
1010 break;
1011 }
1012 } while (--idx > 0);
1013 /*
1014 * If idx is '0', it won't be tried
1015 * Thus, initial values are uesed
1016 */
1017done:
1018 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1019 mci_writel(host, FIFOTH, fifoth_val);
Seungwon Jeon52426892013-08-31 00:13:42 +09001020}
1021
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001022static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001023{
1024 unsigned int blksz = data->blksz;
1025 u32 blksz_depth, fifo_depth;
1026 u16 thld_size;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001027 u8 enable;
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001028
James Hogan66dfd102014-11-17 17:49:05 +00001029 /*
1030 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1031 * in the FIFO region, so we really shouldn't access it).
1032 */
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001033 if (host->verid < DW_MMC_240A ||
1034 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
James Hogan66dfd102014-11-17 17:49:05 +00001035 return;
1036
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001037 /*
1038 * Card write Threshold is introduced since 2.80a
1039 * It's used when HS400 mode is enabled.
1040 */
1041 if (data->flags & MMC_DATA_WRITE &&
x002701707a6b9f4d2018-07-03 15:06:27 +08001042 host->timing != MMC_TIMING_MMC_HS400)
1043 goto disable;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001044
1045 if (data->flags & MMC_DATA_WRITE)
1046 enable = SDMMC_CARD_WR_THR_EN;
1047 else
1048 enable = SDMMC_CARD_RD_THR_EN;
1049
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001050 if (host->timing != MMC_TIMING_MMC_HS200 &&
x002701707a6b9f4d2018-07-03 15:06:27 +08001051 host->timing != MMC_TIMING_UHS_SDR104 &&
1052 host->timing != MMC_TIMING_MMC_HS400)
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001053 goto disable;
1054
1055 blksz_depth = blksz / (1 << host->data_shift);
1056 fifo_depth = host->fifo_depth;
1057
1058 if (blksz_depth > fifo_depth)
1059 goto disable;
1060
1061 /*
1062 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1063 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1064 * Currently just choose blksz.
1065 */
1066 thld_size = blksz;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001067 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001068 return;
1069
1070disable:
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001071 mci_writel(host, CDTHRCTL, 0);
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001072}
1073
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001074static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1075{
Doug Andersonf8c58c12014-12-02 15:42:47 -08001076 unsigned long irqflags;
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001077 int sg_len;
1078 u32 temp;
1079
1080 host->using_dma = 0;
1081
1082 /* If we don't have a channel, we can't do DMA */
1083 if (!host->use_dma)
1084 return -ENODEV;
1085
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +09001086 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
Seungwon Jeona99aa9b2012-04-10 09:53:32 +09001087 if (sg_len < 0) {
1088 host->dma_ops->stop(host);
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001089 return sg_len;
Seungwon Jeona99aa9b2012-04-10 09:53:32 +09001090 }
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001091
James Hogan03e8cb52011-06-29 09:28:43 +01001092 host->using_dma = 1;
1093
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001094 if (host->use_dma == TRANS_MODE_IDMAC)
1095 dev_vdbg(host->dev,
1096 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1097 (unsigned long)host->sg_cpu,
1098 (unsigned long)host->sg_dma,
1099 sg_len);
Will Newtonf95f3852011-01-02 01:11:59 -05001100
Seungwon Jeon52426892013-08-31 00:13:42 +09001101 /*
1102 * Decide the MSIZE and RX/TX Watermark.
1103 * If current block size is same with previous size,
1104 * no need to update fifoth.
1105 */
1106 if (host->prev_blksz != data->blksz)
1107 dw_mci_adjust_fifoth(host, data);
1108
Will Newtonf95f3852011-01-02 01:11:59 -05001109 /* Enable the DMA interface */
1110 temp = mci_readl(host, CTRL);
1111 temp |= SDMMC_CTRL_DMA_ENABLE;
1112 mci_writel(host, CTRL, temp);
1113
1114 /* Disable RX/TX IRQs, let DMA handle it */
Doug Andersonf8c58c12014-12-02 15:42:47 -08001115 spin_lock_irqsave(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001116 temp = mci_readl(host, INTMASK);
1117 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1118 mci_writel(host, INTMASK, temp);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001119 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001120
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001121 if (host->dma_ops->start(host, sg_len)) {
Jaehoon Chung647f80a2016-11-21 10:51:48 +09001122 host->dma_ops->stop(host);
Shawn Lind12d0cb2016-09-02 12:14:38 +08001123 /* We can't do DMA, try PIO for this one */
1124 dev_dbg(host->dev,
1125 "%s: fall back to PIO mode for current transfer\n",
1126 __func__);
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001127 return -ENODEV;
1128 }
Will Newtonf95f3852011-01-02 01:11:59 -05001129
1130 return 0;
1131}
1132
1133static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1134{
Doug Andersonf8c58c12014-12-02 15:42:47 -08001135 unsigned long irqflags;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001136 int flags = SG_MITER_ATOMIC;
Will Newtonf95f3852011-01-02 01:11:59 -05001137 u32 temp;
1138
1139 data->error = -EINPROGRESS;
1140
1141 WARN_ON(host->data);
1142 host->sg = NULL;
1143 host->data = data;
1144
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001145 if (data->flags & MMC_DATA_READ)
James Hogan55c5efbc2011-06-29 09:29:58 +01001146 host->dir_status = DW_MCI_RECV_STATUS;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001147 else
James Hogan55c5efbc2011-06-29 09:29:58 +01001148 host->dir_status = DW_MCI_SEND_STATUS;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001149
1150 dw_mci_ctrl_thld(host, data);
James Hogan55c5efbc2011-06-29 09:29:58 +01001151
Will Newtonf95f3852011-01-02 01:11:59 -05001152 if (dw_mci_submit_data_dma(host, data)) {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09001153 if (host->data->flags & MMC_DATA_READ)
1154 flags |= SG_MITER_TO_SG;
1155 else
1156 flags |= SG_MITER_FROM_SG;
1157
1158 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
Will Newtonf95f3852011-01-02 01:11:59 -05001159 host->sg = data->sg;
James Hogan34b664a2011-06-24 13:57:56 +01001160 host->part_buf_start = 0;
1161 host->part_buf_count = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001162
James Hoganb40af3a2011-06-24 13:54:06 +01001163 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001164
1165 spin_lock_irqsave(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001166 temp = mci_readl(host, INTMASK);
1167 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1168 mci_writel(host, INTMASK, temp);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001169 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001170
1171 temp = mci_readl(host, CTRL);
1172 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1173 mci_writel(host, CTRL, temp);
Seungwon Jeon52426892013-08-31 00:13:42 +09001174
1175 /*
Jun Nied6fced82017-01-11 15:37:26 +09001176 * Use the initial fifoth_val for PIO mode. If wm_algined
1177 * is set, we set watermark same as data size.
Seungwon Jeon52426892013-08-31 00:13:42 +09001178 * If next issued data may be transfered by DMA mode,
1179 * prev_blksz should be invalidated.
1180 */
Jun Nied6fced82017-01-11 15:37:26 +09001181 if (host->wm_aligned)
1182 dw_mci_adjust_fifoth(host, data);
1183 else
1184 mci_writel(host, FIFOTH, host->fifoth_val);
Seungwon Jeon52426892013-08-31 00:13:42 +09001185 host->prev_blksz = 0;
1186 } else {
1187 /*
1188 * Keep the current block size.
1189 * It will be used to decide whether to update
1190 * fifoth register next time.
1191 */
1192 host->prev_blksz = data->blksz;
Will Newtonf95f3852011-01-02 01:11:59 -05001193 }
1194}
1195
Abhilash Kesavanab269122012-11-19 10:26:21 +05301196static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
Will Newtonf95f3852011-01-02 01:11:59 -05001197{
1198 struct dw_mci *host = slot->host;
Doug Andersonfdf492a2013-08-31 00:11:43 +09001199 unsigned int clock = slot->clock;
Will Newtonf95f3852011-01-02 01:11:59 -05001200 u32 div;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001201 u32 clk_en_a;
Doug Anderson01730552014-08-22 19:17:51 +05301202 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1203
1204 /* We must continue to set bit 28 in CMD until the change is complete */
1205 if (host->state == STATE_WAITING_CMD11_DONE)
1206 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
Will Newtonf95f3852011-01-02 01:11:59 -05001207
Shawn Linff178982018-03-26 17:26:25 +08001208 slot->mmc->actual_clock = 0;
1209
Doug Andersonfdf492a2013-08-31 00:11:43 +09001210 if (!clock) {
1211 mci_writel(host, CLKENA, 0);
Doug Anderson01730552014-08-22 19:17:51 +05301212 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Doug Andersonfdf492a2013-08-31 00:11:43 +09001213 } else if (clock != host->current_speed || force_clkinit) {
1214 div = host->bus_hz / clock;
1215 if (host->bus_hz % clock && host->bus_hz > clock)
Will Newtonf95f3852011-01-02 01:11:59 -05001216 /*
1217 * move the + 1 after the divide to prevent
1218 * over-clocking the card.
1219 */
Seungwon Jeone4199902012-05-22 13:01:21 +09001220 div += 1;
1221
Doug Andersonfdf492a2013-08-31 00:11:43 +09001222 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001223
Jaehoon Chunge6cd7a82016-11-24 20:04:42 +09001224 if ((clock != slot->__clk_old &&
1225 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1226 force_clkinit) {
Shawn Lince69e2f2017-01-17 09:22:55 +08001227 /* Silent the verbose log if calling from PM context */
1228 if (!force_clkinit)
1229 dev_info(&slot->mmc->class_dev,
1230 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1231 slot->id, host->bus_hz, clock,
1232 div ? ((host->bus_hz / div) >> 1) :
1233 host->bus_hz, div);
Will Newtonf95f3852011-01-02 01:11:59 -05001234
Jaehoon Chunge6cd7a82016-11-24 20:04:42 +09001235 /*
1236 * If card is polling, display the message only
1237 * one time at boot time.
1238 */
1239 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1240 slot->mmc->f_min == clock)
1241 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1242 }
1243
Will Newtonf95f3852011-01-02 01:11:59 -05001244 /* disable clock */
1245 mci_writel(host, CLKENA, 0);
1246 mci_writel(host, CLKSRC, 0);
1247
1248 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301249 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Will Newtonf95f3852011-01-02 01:11:59 -05001250
1251 /* set clock to desired speed */
1252 mci_writel(host, CLKDIV, div);
1253
1254 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301255 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Will Newtonf95f3852011-01-02 01:11:59 -05001256
Doug Anderson9623b5b2012-07-25 08:33:17 -07001257 /* enable clock; only low power if no SDIO */
1258 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
Doug Andersonb24c8b22014-12-02 15:42:46 -08001259 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
Doug Anderson9623b5b2012-07-25 08:33:17 -07001260 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1261 mci_writel(host, CLKENA, clk_en_a);
Will Newtonf95f3852011-01-02 01:11:59 -05001262
1263 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301264 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Jaehoon Chung005d6752016-09-22 14:12:00 +09001265
1266 /* keep the last clock value that was requested from core */
1267 slot->__clk_old = clock;
Shawn Linff178982018-03-26 17:26:25 +08001268 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1269 host->bus_hz;
Will Newtonf95f3852011-01-02 01:11:59 -05001270 }
1271
Doug Andersonfdf492a2013-08-31 00:11:43 +09001272 host->current_speed = clock;
1273
Will Newtonf95f3852011-01-02 01:11:59 -05001274 /* Set the current slot bus width */
Seungwon Jeon1d56c452011-06-20 17:23:53 +09001275 mci_writel(host, CTYPE, (slot->ctype << slot->id));
Will Newtonf95f3852011-01-02 01:11:59 -05001276}
1277
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001278static void __dw_mci_start_request(struct dw_mci *host,
1279 struct dw_mci_slot *slot,
1280 struct mmc_command *cmd)
Will Newtonf95f3852011-01-02 01:11:59 -05001281{
1282 struct mmc_request *mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001283 struct mmc_data *data;
1284 u32 cmdflags;
1285
1286 mrq = slot->mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001287
Will Newtonf95f3852011-01-02 01:11:59 -05001288 host->mrq = mrq;
1289
1290 host->pending_events = 0;
1291 host->completed_events = 0;
Seungwon Jeone352c812013-08-31 00:14:17 +09001292 host->cmd_status = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001293 host->data_status = 0;
Seungwon Jeone352c812013-08-31 00:14:17 +09001294 host->dir_status = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001295
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001296 data = cmd->data;
Will Newtonf95f3852011-01-02 01:11:59 -05001297 if (data) {
Jaehoon Chungf16afa82014-03-03 11:36:45 +09001298 mci_writel(host, TMOUT, 0xFFFFFFFF);
Will Newtonf95f3852011-01-02 01:11:59 -05001299 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1300 mci_writel(host, BLKSIZ, data->blksz);
1301 }
1302
Will Newtonf95f3852011-01-02 01:11:59 -05001303 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1304
1305 /* this is the first command, send the initialization clock */
1306 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1307 cmdflags |= SDMMC_CMD_INIT;
1308
1309 if (data) {
1310 dw_mci_submit_data(host, data);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001311 wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05001312 }
1313
1314 dw_mci_start_command(host, cmd, cmdflags);
1315
Doug Anderson5c935162015-03-09 16:18:21 -07001316 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
Doug Anderson49ba0302015-04-03 11:13:07 -07001317 unsigned long irqflags;
1318
Doug Anderson5c935162015-03-09 16:18:21 -07001319 /*
Doug Anderson8886a6f2015-04-03 11:13:05 -07001320 * Databook says to fail after 2ms w/ no response, but evidence
1321 * shows that sometimes the cmd11 interrupt takes over 130ms.
1322 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1323 * is just about to roll over.
Doug Anderson49ba0302015-04-03 11:13:07 -07001324 *
1325 * We do this whole thing under spinlock and only if the
1326 * command hasn't already completed (indicating the the irq
1327 * already ran so we don't want the timeout).
Doug Anderson5c935162015-03-09 16:18:21 -07001328 */
Doug Anderson49ba0302015-04-03 11:13:07 -07001329 spin_lock_irqsave(&host->irq_lock, irqflags);
1330 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1331 mod_timer(&host->cmd11_timer,
1332 jiffies + msecs_to_jiffies(500) + 1);
1333 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Doug Anderson5c935162015-03-09 16:18:21 -07001334 }
1335
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09001336 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
Will Newtonf95f3852011-01-02 01:11:59 -05001337}
1338
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001339static void dw_mci_start_request(struct dw_mci *host,
1340 struct dw_mci_slot *slot)
1341{
1342 struct mmc_request *mrq = slot->mrq;
1343 struct mmc_command *cmd;
1344
1345 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1346 __dw_mci_start_request(host, slot, cmd);
1347}
1348
James Hogan7456caa2011-06-24 13:55:10 +01001349/* must be called with host->lock held */
Will Newtonf95f3852011-01-02 01:11:59 -05001350static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1351 struct mmc_request *mrq)
1352{
1353 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1354 host->state);
1355
Will Newtonf95f3852011-01-02 01:11:59 -05001356 slot->mrq = mrq;
1357
Doug Anderson01730552014-08-22 19:17:51 +05301358 if (host->state == STATE_WAITING_CMD11_DONE) {
1359 dev_warn(&slot->mmc->class_dev,
1360 "Voltage change didn't complete\n");
1361 /*
1362 * this case isn't expected to happen, so we can
1363 * either crash here or just try to continue on
1364 * in the closest possible state
1365 */
1366 host->state = STATE_IDLE;
1367 }
1368
Will Newtonf95f3852011-01-02 01:11:59 -05001369 if (host->state == STATE_IDLE) {
1370 host->state = STATE_SENDING_CMD;
1371 dw_mci_start_request(host, slot);
1372 } else {
1373 list_add_tail(&slot->queue_node, &host->queue);
1374 }
Will Newtonf95f3852011-01-02 01:11:59 -05001375}
1376
1377static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1378{
1379 struct dw_mci_slot *slot = mmc_priv(mmc);
1380 struct dw_mci *host = slot->host;
1381
1382 WARN_ON(slot->mrq);
1383
James Hogan7456caa2011-06-24 13:55:10 +01001384 /*
1385 * The check for card presence and queueing of the request must be
1386 * atomic, otherwise the card could be removed in between and the
1387 * request wouldn't fail until another card was inserted.
1388 */
James Hogan7456caa2011-06-24 13:55:10 +01001389
Shawn Lin56f69112016-05-27 14:37:05 +08001390 if (!dw_mci_get_cd(mmc)) {
Will Newtonf95f3852011-01-02 01:11:59 -05001391 mrq->cmd->error = -ENOMEDIUM;
1392 mmc_request_done(mmc, mrq);
1393 return;
1394 }
1395
Shawn Lin56f69112016-05-27 14:37:05 +08001396 spin_lock_bh(&host->lock);
1397
Will Newtonf95f3852011-01-02 01:11:59 -05001398 dw_mci_queue_request(host, slot, mrq);
James Hogan7456caa2011-06-24 13:55:10 +01001399
1400 spin_unlock_bh(&host->lock);
Will Newtonf95f3852011-01-02 01:11:59 -05001401}
1402
1403static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1404{
1405 struct dw_mci_slot *slot = mmc_priv(mmc);
Arnd Bergmanne95baf12012-11-08 14:26:11 +00001406 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
Jaehoon Chung41babf72011-02-24 13:46:11 +09001407 u32 regs;
Yuvaraj CD51da2242014-08-22 19:17:50 +05301408 int ret;
Will Newtonf95f3852011-01-02 01:11:59 -05001409
Will Newtonf95f3852011-01-02 01:11:59 -05001410 switch (ios->bus_width) {
Will Newtonf95f3852011-01-02 01:11:59 -05001411 case MMC_BUS_WIDTH_4:
1412 slot->ctype = SDMMC_CTYPE_4BIT;
1413 break;
Jaehoon Chungc9b2a062011-02-17 16:12:38 +09001414 case MMC_BUS_WIDTH_8:
1415 slot->ctype = SDMMC_CTYPE_8BIT;
1416 break;
Jaehoon Chungb2f7cb42012-11-08 17:35:31 +09001417 default:
1418 /* set default 1 bit mode */
1419 slot->ctype = SDMMC_CTYPE_1BIT;
Will Newtonf95f3852011-01-02 01:11:59 -05001420 }
1421
Seungwon Jeon3f514292012-01-02 16:00:02 +09001422 regs = mci_readl(slot->host, UHS_REG);
1423
Jaehoon Chung41babf72011-02-24 13:46:11 +09001424 /* DDR mode set */
Seungwon Jeon80113132015-01-29 08:11:57 +05301425 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
Jaehoon Chung7cc8d582015-10-21 19:49:42 +09001426 ios->timing == MMC_TIMING_UHS_DDR50 ||
Seungwon Jeon80113132015-01-29 08:11:57 +05301427 ios->timing == MMC_TIMING_MMC_HS400)
Hyeonsu Kimc69042a2013-02-22 09:32:46 +09001428 regs |= ((0x1 << slot->id) << 16);
Seungwon Jeon3f514292012-01-02 16:00:02 +09001429 else
Hyeonsu Kimc69042a2013-02-22 09:32:46 +09001430 regs &= ~((0x1 << slot->id) << 16);
Seungwon Jeon3f514292012-01-02 16:00:02 +09001431
1432 mci_writel(slot->host, UHS_REG, regs);
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001433 slot->host->timing = ios->timing;
Jaehoon Chung41babf72011-02-24 13:46:11 +09001434
Doug Andersonfdf492a2013-08-31 00:11:43 +09001435 /*
1436 * Use mirror of ios->clock to prevent race with mmc
1437 * core ios update when finding the minimum.
1438 */
1439 slot->clock = ios->clock;
Will Newtonf95f3852011-01-02 01:11:59 -05001440
James Hogancb27a842012-10-16 09:43:08 +01001441 if (drv_data && drv_data->set_ios)
1442 drv_data->set_ios(slot->host, ios);
Thomas Abraham800d78b2012-09-17 18:16:42 +00001443
Will Newtonf95f3852011-01-02 01:11:59 -05001444 switch (ios->power_mode) {
1445 case MMC_POWER_UP:
Yuvaraj CD51da2242014-08-22 19:17:50 +05301446 if (!IS_ERR(mmc->supply.vmmc)) {
1447 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1448 ios->vdd);
1449 if (ret) {
1450 dev_err(slot->host->dev,
1451 "failed to enable vmmc regulator\n");
1452 /*return, if failed turn on vmmc*/
1453 return;
1454 }
1455 }
Doug Anderson29d0d162015-01-13 15:58:44 -08001456 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1457 regs = mci_readl(slot->host, PWREN);
1458 regs |= (1 << slot->id);
1459 mci_writel(slot->host, PWREN, regs);
1460 break;
1461 case MMC_POWER_ON:
Doug Andersond1f1dd82015-02-20 10:57:19 -08001462 if (!slot->host->vqmmc_enabled) {
1463 if (!IS_ERR(mmc->supply.vqmmc)) {
1464 ret = regulator_enable(mmc->supply.vqmmc);
1465 if (ret < 0)
1466 dev_err(slot->host->dev,
1467 "failed to enable vqmmc\n");
1468 else
1469 slot->host->vqmmc_enabled = true;
1470
1471 } else {
1472 /* Keep track so we don't reset again */
Yuvaraj CD51da2242014-08-22 19:17:50 +05301473 slot->host->vqmmc_enabled = true;
Doug Andersond1f1dd82015-02-20 10:57:19 -08001474 }
1475
1476 /* Reset our state machine after powering on */
1477 dw_mci_ctrl_reset(slot->host,
1478 SDMMC_CTRL_ALL_RESET_FLAGS);
Yuvaraj CD51da2242014-08-22 19:17:50 +05301479 }
Doug Anderson655babb2015-02-20 10:57:18 -08001480
1481 /* Adjust clock / bus width after power is up */
1482 dw_mci_setup_bus(slot, false);
1483
James Hogane6f34e22013-03-12 10:43:32 +00001484 break;
1485 case MMC_POWER_OFF:
Doug Anderson655babb2015-02-20 10:57:18 -08001486 /* Turn clock off before power goes down */
1487 dw_mci_setup_bus(slot, false);
1488
Yuvaraj CD51da2242014-08-22 19:17:50 +05301489 if (!IS_ERR(mmc->supply.vmmc))
1490 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1491
Doug Andersond1f1dd82015-02-20 10:57:19 -08001492 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
Yuvaraj CD51da2242014-08-22 19:17:50 +05301493 regulator_disable(mmc->supply.vqmmc);
Doug Andersond1f1dd82015-02-20 10:57:19 -08001494 slot->host->vqmmc_enabled = false;
Yuvaraj CD51da2242014-08-22 19:17:50 +05301495
Jaehoon Chung4366dcc2013-03-26 21:36:14 +09001496 regs = mci_readl(slot->host, PWREN);
1497 regs &= ~(1 << slot->id);
1498 mci_writel(slot->host, PWREN, regs);
Will Newtonf95f3852011-01-02 01:11:59 -05001499 break;
1500 default:
1501 break;
1502 }
Doug Anderson655babb2015-02-20 10:57:18 -08001503
1504 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1505 slot->host->state = STATE_IDLE;
Will Newtonf95f3852011-01-02 01:11:59 -05001506}
1507
Doug Anderson01730552014-08-22 19:17:51 +05301508static int dw_mci_card_busy(struct mmc_host *mmc)
1509{
1510 struct dw_mci_slot *slot = mmc_priv(mmc);
1511 u32 status;
1512
1513 /*
1514 * Check the busy bit which is low when DAT[3:0]
1515 * (the data lines) are 0000
1516 */
1517 status = mci_readl(slot->host, STATUS);
1518
1519 return !!(status & SDMMC_STATUS_BUSY);
1520}
1521
1522static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1523{
1524 struct dw_mci_slot *slot = mmc_priv(mmc);
1525 struct dw_mci *host = slot->host;
Zhangfei Gao8f7849c2015-05-14 16:45:18 +08001526 const struct dw_mci_drv_data *drv_data = host->drv_data;
Doug Anderson01730552014-08-22 19:17:51 +05301527 u32 uhs;
1528 u32 v18 = SDMMC_UHS_18V << slot->id;
Doug Anderson01730552014-08-22 19:17:51 +05301529 int ret;
1530
Zhangfei Gao8f7849c2015-05-14 16:45:18 +08001531 if (drv_data && drv_data->switch_voltage)
1532 return drv_data->switch_voltage(mmc, ios);
1533
Doug Anderson01730552014-08-22 19:17:51 +05301534 /*
1535 * Program the voltage. Note that some instances of dw_mmc may use
1536 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1537 * does no harm but you need to set the regulator directly. Try both.
1538 */
1539 uhs = mci_readl(host, UHS_REG);
Douglas Andersone0848f52015-10-12 14:48:26 +02001540 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
Doug Anderson01730552014-08-22 19:17:51 +05301541 uhs &= ~v18;
Douglas Andersone0848f52015-10-12 14:48:26 +02001542 else
Doug Anderson01730552014-08-22 19:17:51 +05301543 uhs |= v18;
Douglas Andersone0848f52015-10-12 14:48:26 +02001544
Doug Anderson01730552014-08-22 19:17:51 +05301545 if (!IS_ERR(mmc->supply.vqmmc)) {
Douglas Andersone0848f52015-10-12 14:48:26 +02001546 ret = mmc_regulator_set_vqmmc(mmc, ios);
Doug Anderson01730552014-08-22 19:17:51 +05301547
1548 if (ret) {
Doug Andersonb19caf32014-10-10 21:16:16 -07001549 dev_dbg(&mmc->class_dev,
Douglas Andersone0848f52015-10-12 14:48:26 +02001550 "Regulator set error %d - %s V\n",
1551 ret, uhs & v18 ? "1.8" : "3.3");
Doug Anderson01730552014-08-22 19:17:51 +05301552 return ret;
1553 }
1554 }
1555 mci_writel(host, UHS_REG, uhs);
1556
1557 return 0;
1558}
1559
Will Newtonf95f3852011-01-02 01:11:59 -05001560static int dw_mci_get_ro(struct mmc_host *mmc)
1561{
1562 int read_only;
1563 struct dw_mci_slot *slot = mmc_priv(mmc);
Jaehoon Chung9795a842014-03-03 11:36:46 +09001564 int gpio_ro = mmc_gpio_get_ro(mmc);
Will Newtonf95f3852011-01-02 01:11:59 -05001565
1566 /* Use platform get_ro function, else try on board write protect */
Arnd Bergmann287980e2016-05-27 23:23:25 +02001567 if (gpio_ro >= 0)
Jaehoon Chung9795a842014-03-03 11:36:46 +09001568 read_only = gpio_ro;
Will Newtonf95f3852011-01-02 01:11:59 -05001569 else
1570 read_only =
1571 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1572
1573 dev_dbg(&mmc->class_dev, "card is %s\n",
1574 read_only ? "read-only" : "read-write");
1575
1576 return read_only;
1577}
1578
Shawn Lin935a6652016-01-14 09:08:02 +08001579static void dw_mci_hw_reset(struct mmc_host *mmc)
1580{
1581 struct dw_mci_slot *slot = mmc_priv(mmc);
1582 struct dw_mci *host = slot->host;
1583 int reset;
1584
1585 if (host->use_dma == TRANS_MODE_IDMAC)
1586 dw_mci_idmac_reset(host);
1587
1588 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1589 SDMMC_CTRL_FIFO_RESET))
1590 return;
1591
1592 /*
1593 * According to eMMC spec, card reset procedure:
1594 * tRstW >= 1us: RST_n pulse width
1595 * tRSCA >= 200us: RST_n to Command time
1596 * tRSTH >= 1us: RST_n high period
1597 */
1598 reset = mci_readl(host, RST_N);
1599 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1600 mci_writel(host, RST_N, reset);
1601 usleep_range(1, 2);
1602 reset |= SDMMC_RST_HWACTIVE << slot->id;
1603 mci_writel(host, RST_N, reset);
1604 usleep_range(200, 300);
1605}
1606
Doug Andersonb24c8b22014-12-02 15:42:46 -08001607static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
Doug Anderson9623b5b2012-07-25 08:33:17 -07001608{
Doug Andersonb24c8b22014-12-02 15:42:46 -08001609 struct dw_mci_slot *slot = mmc_priv(mmc);
Doug Anderson9623b5b2012-07-25 08:33:17 -07001610 struct dw_mci *host = slot->host;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001611
Doug Andersonb24c8b22014-12-02 15:42:46 -08001612 /*
1613 * Low power mode will stop the card clock when idle. According to the
1614 * description of the CLKENA register we should disable low power mode
1615 * for SDIO cards if we need SDIO interrupts to work.
1616 */
1617 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1618 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1619 u32 clk_en_a_old;
1620 u32 clk_en_a;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001621
Doug Andersonb24c8b22014-12-02 15:42:46 -08001622 clk_en_a_old = mci_readl(host, CLKENA);
1623
1624 if (card->type == MMC_TYPE_SDIO ||
1625 card->type == MMC_TYPE_SD_COMBO) {
Ulf Hansson0eebf9b92017-04-19 22:41:43 +02001626 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
Doug Andersonb24c8b22014-12-02 15:42:46 -08001627 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1628 } else {
Ulf Hansson0eebf9b92017-04-19 22:41:43 +02001629 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
Doug Andersonb24c8b22014-12-02 15:42:46 -08001630 clk_en_a = clk_en_a_old | clken_low_pwr;
1631 }
1632
1633 if (clk_en_a != clk_en_a_old) {
1634 mci_writel(host, CLKENA, clk_en_a);
1635 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1636 SDMMC_CMD_PRV_DAT_WAIT, 0);
1637 }
Doug Anderson9623b5b2012-07-25 08:33:17 -07001638 }
1639}
1640
Ulf Hansson32dba732017-04-18 13:29:20 +02001641static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301642{
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301643 struct dw_mci *host = slot->host;
Doug Andersonf8c58c12014-12-02 15:42:47 -08001644 unsigned long irqflags;
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301645 u32 int_mask;
1646
Doug Andersonf8c58c12014-12-02 15:42:47 -08001647 spin_lock_irqsave(&host->irq_lock, irqflags);
1648
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301649 /* Enable/disable Slot Specific SDIO interrupt */
1650 int_mask = mci_readl(host, INTMASK);
Doug Andersonb24c8b22014-12-02 15:42:46 -08001651 if (enb)
1652 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1653 else
1654 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1655 mci_writel(host, INTMASK, int_mask);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001656
1657 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301658}
1659
Ulf Hansson32dba732017-04-18 13:29:20 +02001660static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1661{
1662 struct dw_mci_slot *slot = mmc_priv(mmc);
Ulf Hanssonca8971c2017-04-18 13:37:32 +02001663 struct dw_mci *host = slot->host;
Ulf Hansson32dba732017-04-18 13:29:20 +02001664
1665 __dw_mci_enable_sdio_irq(slot, enb);
Ulf Hanssonca8971c2017-04-18 13:37:32 +02001666
1667 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1668 if (enb)
1669 pm_runtime_get_noresume(host->dev);
1670 else
1671 pm_runtime_put_noidle(host->dev);
Ulf Hansson32dba732017-04-18 13:29:20 +02001672}
1673
1674static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1675{
1676 struct dw_mci_slot *slot = mmc_priv(mmc);
1677
1678 __dw_mci_enable_sdio_irq(slot, 1);
1679}
1680
Seungwon Jeon0976f162013-08-31 00:12:42 +09001681static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1682{
1683 struct dw_mci_slot *slot = mmc_priv(mmc);
1684 struct dw_mci *host = slot->host;
1685 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001686 int err = -EINVAL;
Seungwon Jeon0976f162013-08-31 00:12:42 +09001687
Seungwon Jeon0976f162013-08-31 00:12:42 +09001688 if (drv_data && drv_data->execute_tuning)
Chaotian Jing9979dbe2015-10-27 14:24:28 +08001689 err = drv_data->execute_tuning(slot, opcode);
Seungwon Jeon0976f162013-08-31 00:12:42 +09001690 return err;
1691}
1692
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001693static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1694 struct mmc_ios *ios)
Seungwon Jeon80113132015-01-29 08:11:57 +05301695{
1696 struct dw_mci_slot *slot = mmc_priv(mmc);
1697 struct dw_mci *host = slot->host;
1698 const struct dw_mci_drv_data *drv_data = host->drv_data;
1699
1700 if (drv_data && drv_data->prepare_hs400_tuning)
1701 return drv_data->prepare_hs400_tuning(host, ios);
1702
1703 return 0;
1704}
1705
Shawn Lin4e7392b2017-02-17 10:56:40 +08001706static bool dw_mci_reset(struct dw_mci *host)
1707{
1708 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1709 bool ret = false;
Shawn Linbc2dcc12017-02-17 10:59:52 +08001710 u32 status = 0;
Shawn Lin4e7392b2017-02-17 10:56:40 +08001711
1712 /*
1713 * Resetting generates a block interrupt, hence setting
1714 * the scatter-gather pointer to NULL.
1715 */
1716 if (host->sg) {
1717 sg_miter_stop(&host->sg_miter);
1718 host->sg = NULL;
1719 }
1720
1721 if (host->use_dma)
1722 flags |= SDMMC_CTRL_DMA_RESET;
1723
1724 if (dw_mci_ctrl_reset(host, flags)) {
1725 /*
Shawn Linbc2dcc12017-02-17 10:59:52 +08001726 * In all cases we clear the RAWINTS
1727 * register to clear any interrupts.
Shawn Lin4e7392b2017-02-17 10:56:40 +08001728 */
1729 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1730
Shawn Linbc2dcc12017-02-17 10:59:52 +08001731 if (!host->use_dma) {
1732 ret = true;
1733 goto ciu_out;
Shawn Lin4e7392b2017-02-17 10:56:40 +08001734 }
Shawn Linbc2dcc12017-02-17 10:59:52 +08001735
1736 /* Wait for dma_req to be cleared */
1737 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1738 status,
1739 !(status & SDMMC_STATUS_DMA_REQ),
1740 1, 500 * USEC_PER_MSEC)) {
1741 dev_err(host->dev,
1742 "%s: Timeout waiting for dma_req to be cleared\n",
1743 __func__);
1744 goto ciu_out;
1745 }
1746
1747 /* when using DMA next we reset the fifo again */
1748 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1749 goto ciu_out;
Shawn Lin4e7392b2017-02-17 10:56:40 +08001750 } else {
1751 /* if the controller reset bit did clear, then set clock regs */
1752 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1753 dev_err(host->dev,
1754 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1755 __func__);
1756 goto ciu_out;
1757 }
1758 }
1759
1760 if (host->use_dma == TRANS_MODE_IDMAC)
Evgeniy Didin47b7de22018-03-14 22:30:51 +03001761 /* It is also required that we reinit idmac */
1762 dw_mci_idmac_init(host);
Shawn Lin4e7392b2017-02-17 10:56:40 +08001763
1764 ret = true;
1765
1766ciu_out:
1767 /* After a CTRL reset we need to have CIU set clock registers */
Jaehoon Chung42f989c2017-06-05 13:41:34 +09001768 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
Shawn Lin4e7392b2017-02-17 10:56:40 +08001769
1770 return ret;
1771}
1772
Will Newtonf95f3852011-01-02 01:11:59 -05001773static const struct mmc_host_ops dw_mci_ops = {
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301774 .request = dw_mci_request,
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001775 .pre_req = dw_mci_pre_req,
1776 .post_req = dw_mci_post_req,
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301777 .set_ios = dw_mci_set_ios,
1778 .get_ro = dw_mci_get_ro,
1779 .get_cd = dw_mci_get_cd,
Shawn Lin935a6652016-01-14 09:08:02 +08001780 .hw_reset = dw_mci_hw_reset,
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301781 .enable_sdio_irq = dw_mci_enable_sdio_irq,
Ulf Hansson32dba732017-04-18 13:29:20 +02001782 .ack_sdio_irq = dw_mci_ack_sdio_irq,
Seungwon Jeon0976f162013-08-31 00:12:42 +09001783 .execute_tuning = dw_mci_execute_tuning,
Doug Anderson01730552014-08-22 19:17:51 +05301784 .card_busy = dw_mci_card_busy,
1785 .start_signal_voltage_switch = dw_mci_switch_voltage,
Doug Andersonb24c8b22014-12-02 15:42:46 -08001786 .init_card = dw_mci_init_card,
Seungwon Jeon80113132015-01-29 08:11:57 +05301787 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
Will Newtonf95f3852011-01-02 01:11:59 -05001788};
1789
1790static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1791 __releases(&host->lock)
1792 __acquires(&host->lock)
1793{
1794 struct dw_mci_slot *slot;
Jaehoon Chung42f989c2017-06-05 13:41:34 +09001795 struct mmc_host *prev_mmc = host->slot->mmc;
Will Newtonf95f3852011-01-02 01:11:59 -05001796
1797 WARN_ON(host->cmd || host->data);
1798
Jaehoon Chung42f989c2017-06-05 13:41:34 +09001799 host->slot->mrq = NULL;
Will Newtonf95f3852011-01-02 01:11:59 -05001800 host->mrq = NULL;
1801 if (!list_empty(&host->queue)) {
1802 slot = list_entry(host->queue.next,
1803 struct dw_mci_slot, queue_node);
1804 list_del(&slot->queue_node);
Thomas Abraham4a909202012-09-17 18:16:35 +00001805 dev_vdbg(host->dev, "list not empty: %s is next\n",
Will Newtonf95f3852011-01-02 01:11:59 -05001806 mmc_hostname(slot->mmc));
1807 host->state = STATE_SENDING_CMD;
1808 dw_mci_start_request(host, slot);
1809 } else {
Thomas Abraham4a909202012-09-17 18:16:35 +00001810 dev_vdbg(host->dev, "list empty\n");
Doug Anderson01730552014-08-22 19:17:51 +05301811
1812 if (host->state == STATE_SENDING_CMD11)
1813 host->state = STATE_WAITING_CMD11_DONE;
1814 else
1815 host->state = STATE_IDLE;
Will Newtonf95f3852011-01-02 01:11:59 -05001816 }
1817
1818 spin_unlock(&host->lock);
1819 mmc_request_done(prev_mmc, mrq);
1820 spin_lock(&host->lock);
1821}
1822
Seungwon Jeone352c812013-08-31 00:14:17 +09001823static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
Will Newtonf95f3852011-01-02 01:11:59 -05001824{
1825 u32 status = host->cmd_status;
1826
1827 host->cmd_status = 0;
1828
1829 /* Read the response from the card (up to 16 bytes) */
1830 if (cmd->flags & MMC_RSP_PRESENT) {
1831 if (cmd->flags & MMC_RSP_136) {
1832 cmd->resp[3] = mci_readl(host, RESP0);
1833 cmd->resp[2] = mci_readl(host, RESP1);
1834 cmd->resp[1] = mci_readl(host, RESP2);
1835 cmd->resp[0] = mci_readl(host, RESP3);
1836 } else {
1837 cmd->resp[0] = mci_readl(host, RESP0);
1838 cmd->resp[1] = 0;
1839 cmd->resp[2] = 0;
1840 cmd->resp[3] = 0;
1841 }
1842 }
1843
1844 if (status & SDMMC_INT_RTO)
1845 cmd->error = -ETIMEDOUT;
1846 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1847 cmd->error = -EILSEQ;
1848 else if (status & SDMMC_INT_RESP_ERR)
1849 cmd->error = -EIO;
1850 else
1851 cmd->error = 0;
1852
Seungwon Jeone352c812013-08-31 00:14:17 +09001853 return cmd->error;
1854}
1855
1856static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1857{
Seungwon Jeon31bff452013-08-31 00:14:23 +09001858 u32 status = host->data_status;
Seungwon Jeone352c812013-08-31 00:14:17 +09001859
1860 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1861 if (status & SDMMC_INT_DRTO) {
1862 data->error = -ETIMEDOUT;
1863 } else if (status & SDMMC_INT_DCRC) {
1864 data->error = -EILSEQ;
1865 } else if (status & SDMMC_INT_EBE) {
1866 if (host->dir_status ==
1867 DW_MCI_SEND_STATUS) {
1868 /*
1869 * No data CRC status was returned.
1870 * The number of bytes transferred
1871 * will be exaggerated in PIO mode.
1872 */
1873 data->bytes_xfered = 0;
1874 data->error = -ETIMEDOUT;
1875 } else if (host->dir_status ==
1876 DW_MCI_RECV_STATUS) {
Shawn Line7a1dec2016-08-22 10:57:16 +08001877 data->error = -EILSEQ;
Seungwon Jeone352c812013-08-31 00:14:17 +09001878 }
1879 } else {
1880 /* SDMMC_INT_SBE is included */
Shawn Line7a1dec2016-08-22 10:57:16 +08001881 data->error = -EILSEQ;
Seungwon Jeone352c812013-08-31 00:14:17 +09001882 }
1883
Doug Andersone6cc0122014-04-22 16:51:21 -07001884 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
Seungwon Jeone352c812013-08-31 00:14:17 +09001885
1886 /*
1887 * After an error, there may be data lingering
Seungwon Jeon31bff452013-08-31 00:14:23 +09001888 * in the FIFO
Seungwon Jeone352c812013-08-31 00:14:17 +09001889 */
Sonny Rao3a33a942014-08-04 18:19:50 -07001890 dw_mci_reset(host);
Seungwon Jeone352c812013-08-31 00:14:17 +09001891 } else {
1892 data->bytes_xfered = data->blocks * data->blksz;
1893 data->error = 0;
1894 }
1895
1896 return data->error;
Will Newtonf95f3852011-01-02 01:11:59 -05001897}
1898
Addy Ke57e10482015-08-11 01:27:18 +09001899static void dw_mci_set_drto(struct dw_mci *host)
1900{
1901 unsigned int drto_clks;
Douglas Anderson9d9491a2017-10-12 13:11:17 -07001902 unsigned int drto_div;
Addy Ke57e10482015-08-11 01:27:18 +09001903 unsigned int drto_ms;
Douglas Anderson93c23ae2017-10-12 13:11:18 -07001904 unsigned long irqflags;
Addy Ke57e10482015-08-11 01:27:18 +09001905
1906 drto_clks = mci_readl(host, TMOUT) >> 8;
Douglas Anderson9d9491a2017-10-12 13:11:17 -07001907 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1908 if (drto_div == 0)
1909 drto_div = 1;
Evgeniy Didinc7151602018-02-28 14:53:18 +03001910
1911 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1912 host->bus_hz);
Addy Ke57e10482015-08-11 01:27:18 +09001913
1914 /* add a bit spare time */
1915 drto_ms += 10;
1916
Douglas Anderson93c23ae2017-10-12 13:11:18 -07001917 spin_lock_irqsave(&host->irq_lock, irqflags);
1918 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1919 mod_timer(&host->dto_timer,
1920 jiffies + msecs_to_jiffies(drto_ms));
1921 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Addy Ke57e10482015-08-11 01:27:18 +09001922}
1923
Douglas Anderson8892b702017-10-12 13:11:16 -07001924static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1925{
1926 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1927 return false;
1928
1929 /*
1930 * Really be certain that the timer has stopped. This is a bit of
1931 * paranoia and could only really happen if we had really bad
1932 * interrupt latency and the interrupt routine and timeout were
1933 * running concurrently so that the del_timer() in the interrupt
1934 * handler couldn't run.
1935 */
1936 WARN_ON(del_timer_sync(&host->cto_timer));
1937 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1938
1939 return true;
1940}
1941
Douglas Anderson93c23ae2017-10-12 13:11:18 -07001942static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1943{
1944 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1945 return false;
1946
1947 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1948 WARN_ON(del_timer_sync(&host->dto_timer));
1949 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1950
1951 return true;
1952}
1953
Will Newtonf95f3852011-01-02 01:11:59 -05001954static void dw_mci_tasklet_func(unsigned long priv)
1955{
1956 struct dw_mci *host = (struct dw_mci *)priv;
1957 struct mmc_data *data;
1958 struct mmc_command *cmd;
Seungwon Jeone352c812013-08-31 00:14:17 +09001959 struct mmc_request *mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001960 enum dw_mci_state state;
1961 enum dw_mci_state prev_state;
Seungwon Jeone352c812013-08-31 00:14:17 +09001962 unsigned int err;
Will Newtonf95f3852011-01-02 01:11:59 -05001963
1964 spin_lock(&host->lock);
1965
1966 state = host->state;
1967 data = host->data;
Seungwon Jeone352c812013-08-31 00:14:17 +09001968 mrq = host->mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001969
1970 do {
1971 prev_state = state;
1972
1973 switch (state) {
1974 case STATE_IDLE:
Doug Anderson01730552014-08-22 19:17:51 +05301975 case STATE_WAITING_CMD11_DONE:
Will Newtonf95f3852011-01-02 01:11:59 -05001976 break;
1977
Doug Anderson01730552014-08-22 19:17:51 +05301978 case STATE_SENDING_CMD11:
Will Newtonf95f3852011-01-02 01:11:59 -05001979 case STATE_SENDING_CMD:
Douglas Anderson8892b702017-10-12 13:11:16 -07001980 if (!dw_mci_clear_pending_cmd_complete(host))
Will Newtonf95f3852011-01-02 01:11:59 -05001981 break;
1982
1983 cmd = host->cmd;
1984 host->cmd = NULL;
1985 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
Seungwon Jeone352c812013-08-31 00:14:17 +09001986 err = dw_mci_command_complete(host, cmd);
1987 if (cmd == mrq->sbc && !err) {
Jaehoon Chung42f989c2017-06-05 13:41:34 +09001988 __dw_mci_start_request(host, host->slot,
Seungwon Jeone352c812013-08-31 00:14:17 +09001989 mrq->cmd);
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001990 goto unlock;
1991 }
1992
Seungwon Jeone352c812013-08-31 00:14:17 +09001993 if (cmd->data && err) {
Doug Anderson46d17952016-04-26 10:03:58 +02001994 /*
1995 * During UHS tuning sequence, sending the stop
1996 * command after the response CRC error would
1997 * throw the system into a confused state
1998 * causing all future tuning phases to report
1999 * failure.
2000 *
2001 * In such case controller will move into a data
2002 * transfer state after a response error or
2003 * response CRC error. Let's let that finish
2004 * before trying to send a stop, so we'll go to
2005 * STATE_SENDING_DATA.
2006 *
2007 * Although letting the data transfer take place
2008 * will waste a bit of time (we already know
2009 * the command was bad), it can't cause any
2010 * errors since it's possible it would have
2011 * taken place anyway if this tasklet got
2012 * delayed. Allowing the transfer to take place
2013 * avoids races and keeps things simple.
2014 */
Douglas Andersonba2d1392019-07-08 12:56:13 -07002015 if (err != -ETIMEDOUT) {
Doug Anderson46d17952016-04-26 10:03:58 +02002016 state = STATE_SENDING_DATA;
2017 continue;
2018 }
2019
Seungwon Jeon71abb132013-08-31 00:13:59 +09002020 dw_mci_stop_dma(host);
Seungwon Jeon90c21432013-08-31 00:14:05 +09002021 send_stop_abort(host, data);
2022 state = STATE_SENDING_STOP;
2023 break;
Seungwon Jeon71abb132013-08-31 00:13:59 +09002024 }
2025
Seungwon Jeone352c812013-08-31 00:14:17 +09002026 if (!cmd->data || err) {
2027 dw_mci_request_end(host, mrq);
Will Newtonf95f3852011-01-02 01:11:59 -05002028 goto unlock;
2029 }
2030
2031 prev_state = state = STATE_SENDING_DATA;
2032 /* fall through */
2033
2034 case STATE_SENDING_DATA:
Doug Anderson2aa35462014-08-13 08:13:43 -07002035 /*
2036 * We could get a data error and never a transfer
2037 * complete so we'd better check for it here.
2038 *
2039 * Note that we don't really care if we also got a
2040 * transfer complete; stopping the DMA and sending an
2041 * abort won't hurt.
2042 */
Will Newtonf95f3852011-01-02 01:11:59 -05002043 if (test_and_clear_bit(EVENT_DATA_ERROR,
2044 &host->pending_events)) {
2045 dw_mci_stop_dma(host);
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09002046 if (!(host->data_status & (SDMMC_INT_DRTO |
addy kebdb9a902015-02-20 10:55:25 +08002047 SDMMC_INT_EBE)))
2048 send_stop_abort(host, data);
Will Newtonf95f3852011-01-02 01:11:59 -05002049 state = STATE_DATA_ERROR;
2050 break;
2051 }
2052
2053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
Addy Ke57e10482015-08-11 01:27:18 +09002054 &host->pending_events)) {
2055 /*
2056 * If all data-related interrupts don't come
2057 * within the given time in reading data state.
2058 */
Jaehoon Chung16a34572016-06-21 14:35:37 +09002059 if (host->dir_status == DW_MCI_RECV_STATUS)
Addy Ke57e10482015-08-11 01:27:18 +09002060 dw_mci_set_drto(host);
Will Newtonf95f3852011-01-02 01:11:59 -05002061 break;
Addy Ke57e10482015-08-11 01:27:18 +09002062 }
Will Newtonf95f3852011-01-02 01:11:59 -05002063
2064 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
Doug Anderson2aa35462014-08-13 08:13:43 -07002065
2066 /*
2067 * Handle an EVENT_DATA_ERROR that might have shown up
2068 * before the transfer completed. This might not have
2069 * been caught by the check above because the interrupt
2070 * could have gone off between the previous check and
2071 * the check for transfer complete.
2072 *
2073 * Technically this ought not be needed assuming we
2074 * get a DATA_COMPLETE eventually (we'll notice the
2075 * error and end the request), but it shouldn't hurt.
2076 *
2077 * This has the advantage of sending the stop command.
2078 */
2079 if (test_and_clear_bit(EVENT_DATA_ERROR,
2080 &host->pending_events)) {
2081 dw_mci_stop_dma(host);
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09002082 if (!(host->data_status & (SDMMC_INT_DRTO |
addy kebdb9a902015-02-20 10:55:25 +08002083 SDMMC_INT_EBE)))
2084 send_stop_abort(host, data);
Doug Anderson2aa35462014-08-13 08:13:43 -07002085 state = STATE_DATA_ERROR;
2086 break;
2087 }
Will Newtonf95f3852011-01-02 01:11:59 -05002088 prev_state = state = STATE_DATA_BUSY;
Doug Anderson2aa35462014-08-13 08:13:43 -07002089
Will Newtonf95f3852011-01-02 01:11:59 -05002090 /* fall through */
2091
2092 case STATE_DATA_BUSY:
Douglas Anderson93c23ae2017-10-12 13:11:18 -07002093 if (!dw_mci_clear_pending_data_complete(host)) {
Addy Ke57e10482015-08-11 01:27:18 +09002094 /*
2095 * If data error interrupt comes but data over
2096 * interrupt doesn't come within the given time.
2097 * in reading data state.
2098 */
Jaehoon Chung16a34572016-06-21 14:35:37 +09002099 if (host->dir_status == DW_MCI_RECV_STATUS)
Addy Ke57e10482015-08-11 01:27:18 +09002100 dw_mci_set_drto(host);
Will Newtonf95f3852011-01-02 01:11:59 -05002101 break;
Addy Ke57e10482015-08-11 01:27:18 +09002102 }
Will Newtonf95f3852011-01-02 01:11:59 -05002103
2104 host->data = NULL;
2105 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
Seungwon Jeone352c812013-08-31 00:14:17 +09002106 err = dw_mci_data_complete(host, data);
Will Newtonf95f3852011-01-02 01:11:59 -05002107
Seungwon Jeone352c812013-08-31 00:14:17 +09002108 if (!err) {
2109 if (!data->stop || mrq->sbc) {
Sachin Kamat17c8bc82014-02-25 15:18:28 +05302110 if (mrq->sbc && data->stop)
Seungwon Jeone352c812013-08-31 00:14:17 +09002111 data->stop->error = 0;
2112 dw_mci_request_end(host, mrq);
2113 goto unlock;
Will Newtonf95f3852011-01-02 01:11:59 -05002114 }
Will Newtonf95f3852011-01-02 01:11:59 -05002115
Seungwon Jeon90c21432013-08-31 00:14:05 +09002116 /* stop command for open-ended transfer*/
Seungwon Jeone352c812013-08-31 00:14:17 +09002117 if (data->stop)
2118 send_stop_abort(host, data);
Doug Anderson2aa35462014-08-13 08:13:43 -07002119 } else {
2120 /*
2121 * If we don't have a command complete now we'll
2122 * never get one since we just reset everything;
2123 * better end the request.
2124 *
2125 * If we do have a command complete we'll fall
2126 * through to the SENDING_STOP command and
2127 * everything will be peachy keen.
2128 */
2129 if (!test_bit(EVENT_CMD_COMPLETE,
2130 &host->pending_events)) {
2131 host->cmd = NULL;
2132 dw_mci_request_end(host, mrq);
2133 goto unlock;
2134 }
Seungwon Jeon90c21432013-08-31 00:14:05 +09002135 }
Seungwon Jeone352c812013-08-31 00:14:17 +09002136
2137 /*
2138 * If err has non-zero,
2139 * stop-abort command has been already issued.
2140 */
2141 prev_state = state = STATE_SENDING_STOP;
2142
Will Newtonf95f3852011-01-02 01:11:59 -05002143 /* fall through */
2144
2145 case STATE_SENDING_STOP:
Douglas Anderson8892b702017-10-12 13:11:16 -07002146 if (!dw_mci_clear_pending_cmd_complete(host))
Will Newtonf95f3852011-01-02 01:11:59 -05002147 break;
2148
Seungwon Jeon71abb132013-08-31 00:13:59 +09002149 /* CMD error in data command */
Seungwon Jeon31bff452013-08-31 00:14:23 +09002150 if (mrq->cmd->error && mrq->data)
Sonny Rao3a33a942014-08-04 18:19:50 -07002151 dw_mci_reset(host);
Seungwon Jeon71abb132013-08-31 00:13:59 +09002152
Will Newtonf95f3852011-01-02 01:11:59 -05002153 host->cmd = NULL;
Seungwon Jeon71abb132013-08-31 00:13:59 +09002154 host->data = NULL;
Seungwon Jeon90c21432013-08-31 00:14:05 +09002155
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09002156 if (!mrq->sbc && mrq->stop)
Seungwon Jeone352c812013-08-31 00:14:17 +09002157 dw_mci_command_complete(host, mrq->stop);
Seungwon Jeon90c21432013-08-31 00:14:05 +09002158 else
2159 host->cmd_status = 0;
2160
Seungwon Jeone352c812013-08-31 00:14:17 +09002161 dw_mci_request_end(host, mrq);
Will Newtonf95f3852011-01-02 01:11:59 -05002162 goto unlock;
2163
2164 case STATE_DATA_ERROR:
2165 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2166 &host->pending_events))
2167 break;
2168
2169 state = STATE_DATA_BUSY;
2170 break;
2171 }
2172 } while (state != prev_state);
2173
2174 host->state = state;
2175unlock:
2176 spin_unlock(&host->lock);
2177
2178}
2179
James Hogan34b664a2011-06-24 13:57:56 +01002180/* push final bytes to part_buf, only use during push */
2181static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2182{
2183 memcpy((void *)&host->part_buf, buf, cnt);
2184 host->part_buf_count = cnt;
2185}
2186
2187/* append bytes to part_buf, only use during push */
2188static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2189{
2190 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2191 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2192 host->part_buf_count += cnt;
2193 return cnt;
2194}
2195
2196/* pull first bytes from part_buf, only use during pull */
2197static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2198{
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002199 cnt = min_t(int, cnt, host->part_buf_count);
James Hogan34b664a2011-06-24 13:57:56 +01002200 if (cnt) {
2201 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2202 cnt);
2203 host->part_buf_count -= cnt;
2204 host->part_buf_start += cnt;
2205 }
2206 return cnt;
2207}
2208
2209/* pull final bytes from the part_buf, assuming it's just been filled */
2210static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2211{
2212 memcpy(buf, &host->part_buf, cnt);
2213 host->part_buf_start = cnt;
2214 host->part_buf_count = (1 << host->data_shift) - cnt;
2215}
2216
Will Newtonf95f3852011-01-02 01:11:59 -05002217static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2218{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002219 struct mmc_data *data = host->data;
2220 int init_cnt = cnt;
2221
James Hogan34b664a2011-06-24 13:57:56 +01002222 /* try and push anything in the part_buf */
2223 if (unlikely(host->part_buf_count)) {
2224 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002225
James Hogan34b664a2011-06-24 13:57:56 +01002226 buf += len;
2227 cnt -= len;
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002228 if (host->part_buf_count == 2) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002229 mci_fifo_writew(host->fifo_reg, host->part_buf16);
James Hogan34b664a2011-06-24 13:57:56 +01002230 host->part_buf_count = 0;
2231 }
2232 }
2233#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2234 if (unlikely((unsigned long)buf & 0x1)) {
2235 while (cnt >= 2) {
2236 u16 aligned_buf[64];
2237 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2238 int items = len >> 1;
2239 int i;
2240 /* memcpy from input buffer into aligned buffer */
2241 memcpy(aligned_buf, buf, len);
2242 buf += len;
2243 cnt -= len;
2244 /* push data from aligned buffer into fifo */
2245 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002246 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002247 }
2248 } else
2249#endif
2250 {
2251 u16 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002252
James Hogan34b664a2011-06-24 13:57:56 +01002253 for (; cnt >= 2; cnt -= 2)
Ben Dooks76184ac2015-03-25 11:27:52 +00002254 mci_fifo_writew(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002255 buf = pdata;
2256 }
2257 /* put anything remaining in the part_buf */
2258 if (cnt) {
2259 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002260 /* Push data if we have reached the expected data length */
2261 if ((data->bytes_xfered + init_cnt) ==
2262 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002263 mci_fifo_writew(host->fifo_reg, host->part_buf16);
Will Newtonf95f3852011-01-02 01:11:59 -05002264 }
2265}
2266
2267static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2268{
James Hogan34b664a2011-06-24 13:57:56 +01002269#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2270 if (unlikely((unsigned long)buf & 0x1)) {
2271 while (cnt >= 2) {
2272 /* pull data from fifo into aligned buffer */
2273 u16 aligned_buf[64];
2274 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2275 int items = len >> 1;
2276 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002277
James Hogan34b664a2011-06-24 13:57:56 +01002278 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002279 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002280 /* memcpy from aligned buffer into output buffer */
2281 memcpy(buf, aligned_buf, len);
2282 buf += len;
2283 cnt -= len;
2284 }
2285 } else
2286#endif
2287 {
2288 u16 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002289
James Hogan34b664a2011-06-24 13:57:56 +01002290 for (; cnt >= 2; cnt -= 2)
Ben Dooks76184ac2015-03-25 11:27:52 +00002291 *pdata++ = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002292 buf = pdata;
2293 }
2294 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002295 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002296 dw_mci_pull_final_bytes(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002297 }
2298}
2299
2300static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2301{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002302 struct mmc_data *data = host->data;
2303 int init_cnt = cnt;
2304
James Hogan34b664a2011-06-24 13:57:56 +01002305 /* try and push anything in the part_buf */
2306 if (unlikely(host->part_buf_count)) {
2307 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002308
James Hogan34b664a2011-06-24 13:57:56 +01002309 buf += len;
2310 cnt -= len;
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002311 if (host->part_buf_count == 4) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002312 mci_fifo_writel(host->fifo_reg, host->part_buf32);
James Hogan34b664a2011-06-24 13:57:56 +01002313 host->part_buf_count = 0;
2314 }
2315 }
2316#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2317 if (unlikely((unsigned long)buf & 0x3)) {
2318 while (cnt >= 4) {
2319 u32 aligned_buf[32];
2320 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2321 int items = len >> 2;
2322 int i;
2323 /* memcpy from input buffer into aligned buffer */
2324 memcpy(aligned_buf, buf, len);
2325 buf += len;
2326 cnt -= len;
2327 /* push data from aligned buffer into fifo */
2328 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002329 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002330 }
2331 } else
2332#endif
2333 {
2334 u32 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002335
James Hogan34b664a2011-06-24 13:57:56 +01002336 for (; cnt >= 4; cnt -= 4)
Ben Dooks76184ac2015-03-25 11:27:52 +00002337 mci_fifo_writel(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002338 buf = pdata;
2339 }
2340 /* put anything remaining in the part_buf */
2341 if (cnt) {
2342 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002343 /* Push data if we have reached the expected data length */
2344 if ((data->bytes_xfered + init_cnt) ==
2345 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002346 mci_fifo_writel(host->fifo_reg, host->part_buf32);
Will Newtonf95f3852011-01-02 01:11:59 -05002347 }
2348}
2349
2350static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2351{
James Hogan34b664a2011-06-24 13:57:56 +01002352#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2353 if (unlikely((unsigned long)buf & 0x3)) {
2354 while (cnt >= 4) {
2355 /* pull data from fifo into aligned buffer */
2356 u32 aligned_buf[32];
2357 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2358 int items = len >> 2;
2359 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002360
James Hogan34b664a2011-06-24 13:57:56 +01002361 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002362 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002363 /* memcpy from aligned buffer into output buffer */
2364 memcpy(buf, aligned_buf, len);
2365 buf += len;
2366 cnt -= len;
2367 }
2368 } else
2369#endif
2370 {
2371 u32 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002372
James Hogan34b664a2011-06-24 13:57:56 +01002373 for (; cnt >= 4; cnt -= 4)
Ben Dooks76184ac2015-03-25 11:27:52 +00002374 *pdata++ = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002375 buf = pdata;
2376 }
2377 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002378 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002379 dw_mci_pull_final_bytes(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002380 }
2381}
2382
2383static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2384{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002385 struct mmc_data *data = host->data;
2386 int init_cnt = cnt;
2387
James Hogan34b664a2011-06-24 13:57:56 +01002388 /* try and push anything in the part_buf */
2389 if (unlikely(host->part_buf_count)) {
2390 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002391
James Hogan34b664a2011-06-24 13:57:56 +01002392 buf += len;
2393 cnt -= len;
Seungwon Jeonc09fbd72013-03-25 16:28:22 +09002394
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002395 if (host->part_buf_count == 8) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002396 mci_fifo_writeq(host->fifo_reg, host->part_buf);
James Hogan34b664a2011-06-24 13:57:56 +01002397 host->part_buf_count = 0;
2398 }
2399 }
2400#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2401 if (unlikely((unsigned long)buf & 0x7)) {
2402 while (cnt >= 8) {
2403 u64 aligned_buf[16];
2404 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2405 int items = len >> 3;
2406 int i;
2407 /* memcpy from input buffer into aligned buffer */
2408 memcpy(aligned_buf, buf, len);
2409 buf += len;
2410 cnt -= len;
2411 /* push data from aligned buffer into fifo */
2412 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002413 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002414 }
2415 } else
2416#endif
2417 {
2418 u64 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002419
James Hogan34b664a2011-06-24 13:57:56 +01002420 for (; cnt >= 8; cnt -= 8)
Ben Dooks76184ac2015-03-25 11:27:52 +00002421 mci_fifo_writeq(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002422 buf = pdata;
2423 }
2424 /* put anything remaining in the part_buf */
2425 if (cnt) {
2426 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002427 /* Push data if we have reached the expected data length */
2428 if ((data->bytes_xfered + init_cnt) ==
2429 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002430 mci_fifo_writeq(host->fifo_reg, host->part_buf);
Will Newtonf95f3852011-01-02 01:11:59 -05002431 }
2432}
2433
2434static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2435{
James Hogan34b664a2011-06-24 13:57:56 +01002436#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2437 if (unlikely((unsigned long)buf & 0x7)) {
2438 while (cnt >= 8) {
2439 /* pull data from fifo into aligned buffer */
2440 u64 aligned_buf[16];
2441 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2442 int items = len >> 3;
2443 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002444
James Hogan34b664a2011-06-24 13:57:56 +01002445 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002446 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2447
James Hogan34b664a2011-06-24 13:57:56 +01002448 /* memcpy from aligned buffer into output buffer */
2449 memcpy(buf, aligned_buf, len);
2450 buf += len;
2451 cnt -= len;
2452 }
2453 } else
2454#endif
2455 {
2456 u64 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002457
James Hogan34b664a2011-06-24 13:57:56 +01002458 for (; cnt >= 8; cnt -= 8)
Ben Dooks76184ac2015-03-25 11:27:52 +00002459 *pdata++ = mci_fifo_readq(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002460 buf = pdata;
Will Newtonf95f3852011-01-02 01:11:59 -05002461 }
James Hogan34b664a2011-06-24 13:57:56 +01002462 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002463 host->part_buf = mci_fifo_readq(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002464 dw_mci_pull_final_bytes(host, buf, cnt);
2465 }
2466}
2467
2468static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2469{
2470 int len;
2471
2472 /* get remaining partial bytes */
2473 len = dw_mci_pull_part_bytes(host, buf, cnt);
2474 if (unlikely(len == cnt))
2475 return;
2476 buf += len;
2477 cnt -= len;
2478
2479 /* get the rest of the data */
2480 host->pull_data(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002481}
2482
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002483static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
Will Newtonf95f3852011-01-02 01:11:59 -05002484{
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002485 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2486 void *buf;
2487 unsigned int offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002488 struct mmc_data *data = host->data;
2489 int shift = host->data_shift;
2490 u32 status;
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002491 unsigned int len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002492 unsigned int remain, fcnt;
Will Newtonf95f3852011-01-02 01:11:59 -05002493
2494 do {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002495 if (!sg_miter_next(sg_miter))
2496 goto done;
Will Newtonf95f3852011-01-02 01:11:59 -05002497
Imre Deak4225fc82013-02-27 17:02:57 -08002498 host->sg = sg_miter->piter.sg;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002499 buf = sg_miter->addr;
2500 remain = sg_miter->length;
2501 offset = 0;
2502
2503 do {
2504 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2505 << shift) + host->part_buf_count;
2506 len = min(remain, fcnt);
2507 if (!len)
2508 break;
2509 dw_mci_pull_data(host, (void *)(buf + offset), len);
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002510 data->bytes_xfered += len;
Will Newtonf95f3852011-01-02 01:11:59 -05002511 offset += len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002512 remain -= len;
2513 } while (remain);
Will Newtonf95f3852011-01-02 01:11:59 -05002514
Seungwon Jeone74f3a92012-08-01 09:30:46 +09002515 sg_miter->consumed = offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002516 status = mci_readl(host, MINTSTS);
2517 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002518 /* if the RXDR is ready read again */
2519 } while ((status & SDMMC_INT_RXDR) ||
2520 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002521
2522 if (!remain) {
2523 if (!sg_miter_next(sg_miter))
2524 goto done;
2525 sg_miter->consumed = 0;
2526 }
2527 sg_miter_stop(sg_miter);
Will Newtonf95f3852011-01-02 01:11:59 -05002528 return;
2529
2530done:
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002531 sg_miter_stop(sg_miter);
2532 host->sg = NULL;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002533 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002534 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2535}
2536
2537static void dw_mci_write_data_pio(struct dw_mci *host)
2538{
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002539 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2540 void *buf;
2541 unsigned int offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002542 struct mmc_data *data = host->data;
2543 int shift = host->data_shift;
2544 u32 status;
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002545 unsigned int len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002546 unsigned int fifo_depth = host->fifo_depth;
2547 unsigned int remain, fcnt;
Will Newtonf95f3852011-01-02 01:11:59 -05002548
2549 do {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002550 if (!sg_miter_next(sg_miter))
2551 goto done;
Will Newtonf95f3852011-01-02 01:11:59 -05002552
Imre Deak4225fc82013-02-27 17:02:57 -08002553 host->sg = sg_miter->piter.sg;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002554 buf = sg_miter->addr;
2555 remain = sg_miter->length;
2556 offset = 0;
2557
2558 do {
2559 fcnt = ((fifo_depth -
2560 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2561 << shift) - host->part_buf_count;
2562 len = min(remain, fcnt);
2563 if (!len)
2564 break;
2565 host->push_data(host, (void *)(buf + offset), len);
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002566 data->bytes_xfered += len;
Will Newtonf95f3852011-01-02 01:11:59 -05002567 offset += len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002568 remain -= len;
2569 } while (remain);
Will Newtonf95f3852011-01-02 01:11:59 -05002570
Seungwon Jeone74f3a92012-08-01 09:30:46 +09002571 sg_miter->consumed = offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002572 status = mci_readl(host, MINTSTS);
2573 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
Will Newtonf95f3852011-01-02 01:11:59 -05002574 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002575
2576 if (!remain) {
2577 if (!sg_miter_next(sg_miter))
2578 goto done;
2579 sg_miter->consumed = 0;
2580 }
2581 sg_miter_stop(sg_miter);
Will Newtonf95f3852011-01-02 01:11:59 -05002582 return;
2583
2584done:
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002585 sg_miter_stop(sg_miter);
2586 host->sg = NULL;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002587 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002588 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2589}
2590
2591static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2592{
Douglas Anderson0363b122017-10-12 13:11:14 -07002593 del_timer(&host->cto_timer);
2594
Will Newtonf95f3852011-01-02 01:11:59 -05002595 if (!host->cmd_status)
2596 host->cmd_status = status;
2597
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002598 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002599
2600 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2601 tasklet_schedule(&host->tasklet);
2602}
2603
Doug Anderson6130e7a2014-10-14 09:33:09 -07002604static void dw_mci_handle_cd(struct dw_mci *host)
2605{
Jaehoon Chungb23475f2017-06-05 13:41:32 +09002606 struct dw_mci_slot *slot = host->slot;
Doug Anderson6130e7a2014-10-14 09:33:09 -07002607
Jaehoon Chung58870242017-06-05 13:41:31 +09002608 if (slot->mmc->ops->card_event)
2609 slot->mmc->ops->card_event(slot->mmc);
2610 mmc_detect_change(slot->mmc,
2611 msecs_to_jiffies(host->pdata->detect_delay_ms));
Doug Anderson6130e7a2014-10-14 09:33:09 -07002612}
2613
Will Newtonf95f3852011-01-02 01:11:59 -05002614static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2615{
2616 struct dw_mci *host = dev_id;
Seungwon Jeon182c9082012-08-01 09:30:30 +09002617 u32 pending;
Jaehoon Chungb23475f2017-06-05 13:41:32 +09002618 struct dw_mci_slot *slot = host->slot;
Douglas Anderson8892b702017-10-12 13:11:16 -07002619 unsigned long irqflags;
Will Newtonf95f3852011-01-02 01:11:59 -05002620
Markos Chandras1fb5f682013-03-12 10:53:11 +00002621 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2622
2623 if (pending) {
Doug Anderson01730552014-08-22 19:17:51 +05302624 /* Check volt switch first, since it can look like an error */
2625 if ((host->state == STATE_SENDING_CMD11) &&
2626 (pending & SDMMC_INT_VOLT_SWITCH)) {
2627 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2628 pending &= ~SDMMC_INT_VOLT_SWITCH;
Doug Anderson49ba0302015-04-03 11:13:07 -07002629
2630 /*
2631 * Hold the lock; we know cmd11_timer can't be kicked
2632 * off after the lock is released, so safe to delete.
2633 */
2634 spin_lock_irqsave(&host->irq_lock, irqflags);
Doug Anderson01730552014-08-22 19:17:51 +05302635 dw_mci_cmd_interrupt(host, pending);
Doug Anderson49ba0302015-04-03 11:13:07 -07002636 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2637
2638 del_timer(&host->cmd11_timer);
Doug Anderson01730552014-08-22 19:17:51 +05302639 }
2640
Will Newtonf95f3852011-01-02 01:11:59 -05002641 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
Douglas Anderson8892b702017-10-12 13:11:16 -07002642 spin_lock_irqsave(&host->irq_lock, irqflags);
2643
Addy Ke03de1922017-07-11 17:38:37 +08002644 del_timer(&host->cto_timer);
Will Newtonf95f3852011-01-02 01:11:59 -05002645 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002646 host->cmd_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002647 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002648 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
Douglas Anderson8892b702017-10-12 13:11:16 -07002649
2650 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05002651 }
2652
2653 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2654 /* if there is an error report DATA_ERROR */
2655 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002656 host->data_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002657 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002658 set_bit(EVENT_DATA_ERROR, &host->pending_events);
Seungwon Jeon9b2026a2012-08-01 09:30:40 +09002659 tasklet_schedule(&host->tasklet);
Will Newtonf95f3852011-01-02 01:11:59 -05002660 }
2661
2662 if (pending & SDMMC_INT_DATA_OVER) {
Douglas Anderson93c23ae2017-10-12 13:11:18 -07002663 spin_lock_irqsave(&host->irq_lock, irqflags);
2664
Jaehoon Chung16a34572016-06-21 14:35:37 +09002665 del_timer(&host->dto_timer);
Addy Ke57e10482015-08-11 01:27:18 +09002666
Will Newtonf95f3852011-01-02 01:11:59 -05002667 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2668 if (!host->data_status)
Seungwon Jeon182c9082012-08-01 09:30:30 +09002669 host->data_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002670 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002671 if (host->dir_status == DW_MCI_RECV_STATUS) {
2672 if (host->sg != NULL)
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002673 dw_mci_read_data_pio(host, true);
Will Newtonf95f3852011-01-02 01:11:59 -05002674 }
2675 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2676 tasklet_schedule(&host->tasklet);
Douglas Anderson93c23ae2017-10-12 13:11:18 -07002677
2678 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05002679 }
2680
2681 if (pending & SDMMC_INT_RXDR) {
2682 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
James Hoganb40af3a2011-06-24 13:54:06 +01002683 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002684 dw_mci_read_data_pio(host, false);
Will Newtonf95f3852011-01-02 01:11:59 -05002685 }
2686
2687 if (pending & SDMMC_INT_TXDR) {
2688 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
James Hoganb40af3a2011-06-24 13:54:06 +01002689 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
Will Newtonf95f3852011-01-02 01:11:59 -05002690 dw_mci_write_data_pio(host);
2691 }
2692
2693 if (pending & SDMMC_INT_CMD_DONE) {
Douglas Anderson8892b702017-10-12 13:11:16 -07002694 spin_lock_irqsave(&host->irq_lock, irqflags);
2695
Will Newtonf95f3852011-01-02 01:11:59 -05002696 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002697 dw_mci_cmd_interrupt(host, pending);
Douglas Anderson8892b702017-10-12 13:11:16 -07002698
2699 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05002700 }
2701
2702 if (pending & SDMMC_INT_CD) {
2703 mci_writel(host, RINTSTS, SDMMC_INT_CD);
Doug Anderson6130e7a2014-10-14 09:33:09 -07002704 dw_mci_handle_cd(host);
Will Newtonf95f3852011-01-02 01:11:59 -05002705 }
2706
Jaehoon Chung58870242017-06-05 13:41:31 +09002707 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2708 mci_writel(host, RINTSTS,
2709 SDMMC_INT_SDIO(slot->sdio_id));
2710 __dw_mci_enable_sdio_irq(slot, 0);
2711 sdio_signal_irq(slot->mmc);
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05302712 }
2713
Markos Chandras1fb5f682013-03-12 10:53:11 +00002714 }
Will Newtonf95f3852011-01-02 01:11:59 -05002715
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002716 if (host->use_dma != TRANS_MODE_IDMAC)
2717 return IRQ_HANDLED;
2718
2719 /* Handle IDMA interrupts */
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002720 if (host->dma_64bit_address == 1) {
2721 pending = mci_readl(host, IDSTS64);
2722 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2723 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2724 SDMMC_IDMAC_INT_RI);
2725 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
Shawn Linfaecf412016-06-24 15:39:52 +08002726 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2727 host->dma_ops->complete((void *)host);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002728 }
2729 } else {
2730 pending = mci_readl(host, IDSTS);
2731 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2732 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2733 SDMMC_IDMAC_INT_RI);
2734 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
Shawn Linfaecf412016-06-24 15:39:52 +08002735 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2736 host->dma_ops->complete((void *)host);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002737 }
Will Newtonf95f3852011-01-02 01:11:59 -05002738 }
Will Newtonf95f3852011-01-02 01:11:59 -05002739
2740 return IRQ_HANDLED;
2741}
2742
Shawn Lina4faa492018-02-24 14:17:22 +08002743static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2744{
2745 struct dw_mci *host = slot->host;
2746 const struct dw_mci_drv_data *drv_data = host->drv_data;
2747 struct mmc_host *mmc = slot->mmc;
2748 int ctrl_id;
2749
2750 if (host->pdata->caps)
2751 mmc->caps = host->pdata->caps;
2752
2753 /*
2754 * Support MMC_CAP_ERASE by default.
2755 * It needs to use trim/discard/erase commands.
2756 */
2757 mmc->caps |= MMC_CAP_ERASE;
2758
2759 if (host->pdata->pm_caps)
2760 mmc->pm_caps = host->pdata->pm_caps;
2761
2762 if (host->dev->of_node) {
2763 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2764 if (ctrl_id < 0)
2765 ctrl_id = 0;
2766 } else {
2767 ctrl_id = to_platform_device(host->dev)->id;
2768 }
Shawn Lin0d84b9e2018-02-24 14:17:23 +08002769
2770 if (drv_data && drv_data->caps) {
2771 if (ctrl_id >= drv_data->num_caps) {
2772 dev_err(host->dev, "invalid controller id %d\n",
2773 ctrl_id);
2774 return -EINVAL;
2775 }
Shawn Lina4faa492018-02-24 14:17:22 +08002776 mmc->caps |= drv_data->caps[ctrl_id];
Shawn Lin0d84b9e2018-02-24 14:17:23 +08002777 }
Shawn Lina4faa492018-02-24 14:17:22 +08002778
2779 if (host->pdata->caps2)
2780 mmc->caps2 = host->pdata->caps2;
2781
Jaehoon Chung86b93a42018-02-23 15:41:33 +09002782 mmc->f_min = DW_MCI_FREQ_MIN;
2783 if (!mmc->f_max)
2784 mmc->f_max = DW_MCI_FREQ_MAX;
2785
Shawn Lina4faa492018-02-24 14:17:22 +08002786 /* Process SDIO IRQs through the sdio_irq_work. */
2787 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2788 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2789
2790 return 0;
2791}
2792
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09002793static int dw_mci_init_slot(struct dw_mci *host)
Will Newtonf95f3852011-01-02 01:11:59 -05002794{
2795 struct mmc_host *mmc;
2796 struct dw_mci_slot *slot;
Shawn Lina4faa492018-02-24 14:17:22 +08002797 int ret;
Will Newtonf95f3852011-01-02 01:11:59 -05002798
Thomas Abraham4a909202012-09-17 18:16:35 +00002799 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
Will Newtonf95f3852011-01-02 01:11:59 -05002800 if (!mmc)
2801 return -ENOMEM;
2802
2803 slot = mmc_priv(mmc);
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09002804 slot->id = 0;
2805 slot->sdio_id = host->sdio_id0 + slot->id;
Will Newtonf95f3852011-01-02 01:11:59 -05002806 slot->mmc = mmc;
2807 slot->host = host;
Jaehoon Chungb23475f2017-06-05 13:41:32 +09002808 host->slot = slot;
Will Newtonf95f3852011-01-02 01:11:59 -05002809
2810 mmc->ops = &dw_mci_ops;
Will Newtonf95f3852011-01-02 01:11:59 -05002811
Yuvaraj CD51da2242014-08-22 19:17:50 +05302812 /*if there are external regulators, get them*/
2813 ret = mmc_regulator_get_supply(mmc);
Wolfram Sang0f3a47b2017-10-14 21:17:11 +02002814 if (ret)
Doug Anderson3cf890f2014-08-25 11:19:04 -07002815 goto err_host_allocated;
Yuvaraj CD51da2242014-08-22 19:17:50 +05302816
2817 if (!mmc->ocr_avail)
2818 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
Will Newtonf95f3852011-01-02 01:11:59 -05002819
Doug Anderson3cf890f2014-08-25 11:19:04 -07002820 ret = mmc_of_parse(mmc);
2821 if (ret)
2822 goto err_host_allocated;
Will Newtonf95f3852011-01-02 01:11:59 -05002823
Shawn Lina4faa492018-02-24 14:17:22 +08002824 ret = dw_mci_init_slot_caps(slot);
2825 if (ret)
2826 goto err_host_allocated;
Ulf Hansson32dba732017-04-18 13:29:20 +02002827
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002828 /* Useful defaults if platform data is unset. */
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002829 if (host->use_dma == TRANS_MODE_IDMAC) {
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002830 mmc->max_segs = host->ring_size;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002831 mmc->max_blk_size = 65535;
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002832 mmc->max_seg_size = 0x1000;
2833 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2834 mmc->max_blk_count = mmc->max_req_size / 512;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002835 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2836 mmc->max_segs = 64;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002837 mmc->max_blk_size = 65535;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002838 mmc->max_blk_count = 65535;
2839 mmc->max_req_size =
2840 mmc->max_blk_size * mmc->max_blk_count;
2841 mmc->max_seg_size = mmc->max_req_size;
Will Newtonf95f3852011-01-02 01:11:59 -05002842 } else {
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002843 /* TRANS_MODE_PIO */
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002844 mmc->max_segs = 64;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002845 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002846 mmc->max_blk_count = 512;
2847 mmc->max_req_size = mmc->max_blk_size *
2848 mmc->max_blk_count;
2849 mmc->max_seg_size = mmc->max_req_size;
Jaehoon Chunga39e5742012-02-04 17:00:27 -05002850 }
Will Newtonf95f3852011-01-02 01:11:59 -05002851
Shawn Linc0834a52016-05-27 14:36:40 +08002852 dw_mci_get_cd(mmc);
Jaehoon Chungae0eb342014-03-03 11:36:48 +09002853
Jaehoon Chung0cea5292013-02-15 23:45:45 +09002854 ret = mmc_add_host(mmc);
2855 if (ret)
Doug Anderson3cf890f2014-08-25 11:19:04 -07002856 goto err_host_allocated;
Will Newtonf95f3852011-01-02 01:11:59 -05002857
2858#if defined(CONFIG_DEBUG_FS)
2859 dw_mci_init_debugfs(slot);
2860#endif
2861
Will Newtonf95f3852011-01-02 01:11:59 -05002862 return 0;
Thomas Abraham800d78b2012-09-17 18:16:42 +00002863
Doug Anderson3cf890f2014-08-25 11:19:04 -07002864err_host_allocated:
Thomas Abraham800d78b2012-09-17 18:16:42 +00002865 mmc_free_host(mmc);
Yuvaraj CD51da2242014-08-22 19:17:50 +05302866 return ret;
Will Newtonf95f3852011-01-02 01:11:59 -05002867}
2868
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09002869static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
Will Newtonf95f3852011-01-02 01:11:59 -05002870{
Will Newtonf95f3852011-01-02 01:11:59 -05002871 /* Debugfs stuff is cleaned up by mmc core */
2872 mmc_remove_host(slot->mmc);
Jaehoon Chungb23475f2017-06-05 13:41:32 +09002873 slot->host->slot = NULL;
Will Newtonf95f3852011-01-02 01:11:59 -05002874 mmc_free_host(slot->mmc);
2875}
2876
2877static void dw_mci_init_dma(struct dw_mci *host)
2878{
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002879 int addr_config;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002880 struct device *dev = host->dev;
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002881
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002882 /*
2883 * Check tansfer mode from HCON[17:16]
2884 * Clear the ambiguous description of dw_mmc databook:
2885 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2886 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2887 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2888 * 2b'11: Non DW DMA Interface -> pio only
2889 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2890 * simpler request/acknowledge handshake mechanism and both of them
2891 * are regarded as external dma master for dw_mmc.
2892 */
2893 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2894 if (host->use_dma == DMA_INTERFACE_IDMA) {
2895 host->use_dma = TRANS_MODE_IDMAC;
2896 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2897 host->use_dma == DMA_INTERFACE_GDMA) {
2898 host->use_dma = TRANS_MODE_EDMAC;
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002899 } else {
Will Newtonf95f3852011-01-02 01:11:59 -05002900 goto no_dma;
2901 }
2902
2903 /* Determine which DMA interface to use */
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002904 if (host->use_dma == TRANS_MODE_IDMAC) {
2905 /*
2906 * Check ADDR_CONFIG bit in HCON to find
2907 * IDMAC address bus width
2908 */
Shawn Lin70692752015-09-16 14:41:37 +08002909 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
Will Newtonf95f3852011-01-02 01:11:59 -05002910
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002911 if (addr_config == 1) {
2912 /* host supports IDMAC in 64-bit address mode */
2913 host->dma_64bit_address = 1;
2914 dev_info(host->dev,
2915 "IDMAC supports 64-bit address mode.\n");
2916 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2917 dma_set_coherent_mask(host->dev,
2918 DMA_BIT_MASK(64));
2919 } else {
2920 /* host supports IDMAC in 32-bit address mode */
2921 host->dma_64bit_address = 0;
2922 dev_info(host->dev,
2923 "IDMAC supports 32-bit address mode.\n");
2924 }
2925
2926 /* Alloc memory for sg translation */
Shawn Lincc190d42016-09-02 12:14:39 +08002927 host->sg_cpu = dmam_alloc_coherent(host->dev,
2928 DESC_RING_BUF_SZ,
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002929 &host->sg_dma, GFP_KERNEL);
2930 if (!host->sg_cpu) {
2931 dev_err(host->dev,
2932 "%s: could not alloc DMA memory\n",
2933 __func__);
2934 goto no_dma;
2935 }
2936
2937 host->dma_ops = &dw_mci_idmac_ops;
2938 dev_info(host->dev, "Using internal DMA controller.\n");
2939 } else {
2940 /* TRANS_MODE_EDMAC: check dma bindings again */
David Woods852ff5f2017-05-26 17:53:20 -04002941 if ((device_property_read_string_array(dev, "dma-names",
2942 NULL, 0) < 0) ||
2943 !device_property_present(dev, "dmas")) {
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002944 goto no_dma;
2945 }
2946 host->dma_ops = &dw_mci_edmac_ops;
2947 dev_info(host->dev, "Using external DMA controller.\n");
2948 }
Will Newtonf95f3852011-01-02 01:11:59 -05002949
Jaehoon Chunge1631f92012-04-18 15:42:31 +09002950 if (host->dma_ops->init && host->dma_ops->start &&
2951 host->dma_ops->stop && host->dma_ops->cleanup) {
Will Newtonf95f3852011-01-02 01:11:59 -05002952 if (host->dma_ops->init(host)) {
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002953 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2954 __func__);
Will Newtonf95f3852011-01-02 01:11:59 -05002955 goto no_dma;
2956 }
2957 } else {
Thomas Abraham4a909202012-09-17 18:16:35 +00002958 dev_err(host->dev, "DMA initialization not found.\n");
Will Newtonf95f3852011-01-02 01:11:59 -05002959 goto no_dma;
2960 }
2961
Will Newtonf95f3852011-01-02 01:11:59 -05002962 return;
2963
2964no_dma:
Thomas Abraham4a909202012-09-17 18:16:35 +00002965 dev_info(host->dev, "Using PIO mode.\n");
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002966 host->use_dma = TRANS_MODE_PIO;
Will Newtonf95f3852011-01-02 01:11:59 -05002967}
2968
Kees Cook37977722017-10-30 14:45:00 -07002969static void dw_mci_cmd11_timer(struct timer_list *t)
Doug Anderson5c935162015-03-09 16:18:21 -07002970{
Kees Cook37977722017-10-30 14:45:00 -07002971 struct dw_mci *host = from_timer(host, t, cmd11_timer);
Doug Anderson5c935162015-03-09 16:18:21 -07002972
Doug Andersonfd674192015-04-03 11:13:06 -07002973 if (host->state != STATE_SENDING_CMD11) {
2974 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2975 return;
2976 }
Doug Anderson5c935162015-03-09 16:18:21 -07002977
2978 host->cmd_status = SDMMC_INT_RTO;
2979 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2980 tasklet_schedule(&host->tasklet);
2981}
2982
Kees Cook37977722017-10-30 14:45:00 -07002983static void dw_mci_cto_timer(struct timer_list *t)
Addy Ke03de1922017-07-11 17:38:37 +08002984{
Kees Cook37977722017-10-30 14:45:00 -07002985 struct dw_mci *host = from_timer(host, t, cto_timer);
Douglas Anderson8892b702017-10-12 13:11:16 -07002986 unsigned long irqflags;
2987 u32 pending;
Addy Ke03de1922017-07-11 17:38:37 +08002988
Douglas Anderson8892b702017-10-12 13:11:16 -07002989 spin_lock_irqsave(&host->irq_lock, irqflags);
2990
2991 /*
2992 * If somehow we have very bad interrupt latency it's remotely possible
2993 * that the timer could fire while the interrupt is still pending or
2994 * while the interrupt is midway through running. Let's be paranoid
2995 * and detect those two cases. Note that this is paranoia is somewhat
2996 * justified because in this function we don't actually cancel the
2997 * pending command in the controller--we just assume it will never come.
2998 */
2999 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3000 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3001 /* The interrupt should fire; no need to act but we can warn */
3002 dev_warn(host->dev, "Unexpected interrupt latency\n");
3003 goto exit;
3004 }
3005 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3006 /* Presumably interrupt handler couldn't delete the timer */
3007 dev_warn(host->dev, "CTO timeout when already completed\n");
3008 goto exit;
3009 }
3010
3011 /*
3012 * Continued paranoia to make sure we're in the state we expect.
3013 * This paranoia isn't really justified but it seems good to be safe.
3014 */
Addy Ke03de1922017-07-11 17:38:37 +08003015 switch (host->state) {
3016 case STATE_SENDING_CMD11:
3017 case STATE_SENDING_CMD:
3018 case STATE_SENDING_STOP:
3019 /*
3020 * If CMD_DONE interrupt does NOT come in sending command
3021 * state, we should notify the driver to terminate current
3022 * transfer and report a command timeout to the core.
3023 */
3024 host->cmd_status = SDMMC_INT_RTO;
3025 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3026 tasklet_schedule(&host->tasklet);
3027 break;
3028 default:
3029 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3030 host->state);
3031 break;
3032 }
Douglas Anderson8892b702017-10-12 13:11:16 -07003033
3034exit:
3035 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Addy Ke03de1922017-07-11 17:38:37 +08003036}
3037
Kees Cook37977722017-10-30 14:45:00 -07003038static void dw_mci_dto_timer(struct timer_list *t)
Addy Ke57e10482015-08-11 01:27:18 +09003039{
Kees Cook37977722017-10-30 14:45:00 -07003040 struct dw_mci *host = from_timer(host, t, dto_timer);
Douglas Anderson93c23ae2017-10-12 13:11:18 -07003041 unsigned long irqflags;
3042 u32 pending;
Addy Ke57e10482015-08-11 01:27:18 +09003043
Douglas Anderson93c23ae2017-10-12 13:11:18 -07003044 spin_lock_irqsave(&host->irq_lock, irqflags);
3045
3046 /*
3047 * The DTO timer is much longer than the CTO timer, so it's even less
3048 * likely that we'll these cases, but it pays to be paranoid.
3049 */
3050 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3051 if (pending & SDMMC_INT_DATA_OVER) {
3052 /* The interrupt should fire; no need to act but we can warn */
3053 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3054 goto exit;
3055 }
3056 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3057 /* Presumably interrupt handler couldn't delete the timer */
3058 dev_warn(host->dev, "DTO timeout when already completed\n");
3059 goto exit;
3060 }
3061
3062 /*
3063 * Continued paranoia to make sure we're in the state we expect.
3064 * This paranoia isn't really justified but it seems good to be safe.
3065 */
Addy Ke57e10482015-08-11 01:27:18 +09003066 switch (host->state) {
3067 case STATE_SENDING_DATA:
3068 case STATE_DATA_BUSY:
3069 /*
3070 * If DTO interrupt does NOT come in sending data state,
3071 * we should notify the driver to terminate current transfer
3072 * and report a data timeout to the core.
3073 */
3074 host->data_status = SDMMC_INT_DRTO;
3075 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3076 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3077 tasklet_schedule(&host->tasklet);
3078 break;
3079 default:
Douglas Anderson93c23ae2017-10-12 13:11:18 -07003080 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3081 host->state);
Addy Ke57e10482015-08-11 01:27:18 +09003082 break;
3083 }
Douglas Anderson93c23ae2017-10-12 13:11:18 -07003084
3085exit:
3086 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Addy Ke57e10482015-08-11 01:27:18 +09003087}
3088
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003089#ifdef CONFIG_OF
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003090static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3091{
3092 struct dw_mci_board *pdata;
3093 struct device *dev = host->dev;
Arnd Bergmanne95baf12012-11-08 14:26:11 +00003094 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shawn Line8cc37b2016-01-21 14:52:52 +08003095 int ret;
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003096 u32 clock_frequency;
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003097
3098 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
Beomho Seobf3707e2014-12-23 21:07:33 +09003099 if (!pdata)
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003100 return ERR_PTR(-ENOMEM);
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003101
Guodong Xud6786fe2016-08-12 16:51:26 +08003102 /* find reset controller when exist */
Philipp Zabela93d6f32017-07-19 17:25:42 +02003103 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
Guodong Xud6786fe2016-08-12 16:51:26 +08003104 if (IS_ERR(pdata->rstc)) {
3105 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3106 return ERR_PTR(-EPROBE_DEFER);
3107 }
3108
David Woods852ff5f2017-05-26 17:53:20 -04003109 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003110 dev_info(dev,
3111 "fifo-depth property not found, using value of FIFOTH register as default\n");
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003112
David Woods852ff5f2017-05-26 17:53:20 -04003113 device_property_read_u32(dev, "card-detect-delay",
3114 &pdata->detect_delay_ms);
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003115
David Woods852ff5f2017-05-26 17:53:20 -04003116 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
Jun Niea0361c12017-01-11 15:35:35 +09003117
David Woods852ff5f2017-05-26 17:53:20 -04003118 if (device_property_present(dev, "fifo-watermark-aligned"))
Jun Nied6fced82017-01-11 15:37:26 +09003119 host->wm_aligned = true;
3120
David Woods852ff5f2017-05-26 17:53:20 -04003121 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003122 pdata->bus_hz = clock_frequency;
3123
James Hogancb27a842012-10-16 09:43:08 +01003124 if (drv_data && drv_data->parse_dt) {
3125 ret = drv_data->parse_dt(host);
Thomas Abraham800d78b2012-09-17 18:16:42 +00003126 if (ret)
3127 return ERR_PTR(ret);
3128 }
3129
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003130 return pdata;
3131}
3132
3133#else /* CONFIG_OF */
3134static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3135{
3136 return ERR_PTR(-EINVAL);
3137}
3138#endif /* CONFIG_OF */
3139
Doug Andersonfa0c3282015-02-25 10:11:51 -08003140static void dw_mci_enable_cd(struct dw_mci *host)
3141{
Doug Andersonfa0c3282015-02-25 10:11:51 -08003142 unsigned long irqflags;
3143 u32 temp;
Doug Andersonfa0c3282015-02-25 10:11:51 -08003144
Shawn Line8cc37b2016-01-21 14:52:52 +08003145 /*
3146 * No need for CD if all slots have a non-error GPIO
3147 * as well as broken card detection is found.
3148 */
Jaehoon Chunge47c0b92017-06-05 13:41:35 +09003149 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
Doug Andersonfa0c3282015-02-25 10:11:51 -08003150 return;
3151
Jaehoon Chunge47c0b92017-06-05 13:41:35 +09003152 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
Jaehoon Chung58870242017-06-05 13:41:31 +09003153 spin_lock_irqsave(&host->irq_lock, irqflags);
3154 temp = mci_readl(host, INTMASK);
3155 temp |= SDMMC_INT_CD;
3156 mci_writel(host, INTMASK, temp);
3157 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3158 }
Doug Andersonfa0c3282015-02-25 10:11:51 -08003159}
3160
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303161int dw_mci_probe(struct dw_mci *host)
Will Newtonf95f3852011-01-02 01:11:59 -05003162{
Arnd Bergmanne95baf12012-11-08 14:26:11 +00003163 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303164 int width, i, ret = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05003165 u32 fifo_size;
3166
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003167 if (!host->pdata) {
3168 host->pdata = dw_mci_parse_dt(host);
Guodong Xud6786fe2016-08-12 16:51:26 +08003169 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3170 return -EPROBE_DEFER;
3171 } else if (IS_ERR(host->pdata)) {
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003172 dev_err(host->dev, "platform data not available\n");
3173 return -EINVAL;
3174 }
Will Newtonf95f3852011-01-02 01:11:59 -05003175 }
3176
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003177 host->biu_clk = devm_clk_get(host->dev, "biu");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003178 if (IS_ERR(host->biu_clk)) {
3179 dev_dbg(host->dev, "biu clock not available\n");
3180 } else {
3181 ret = clk_prepare_enable(host->biu_clk);
3182 if (ret) {
3183 dev_err(host->dev, "failed to enable biu clock\n");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003184 return ret;
3185 }
Will Newtonf95f3852011-01-02 01:11:59 -05003186 }
3187
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003188 host->ciu_clk = devm_clk_get(host->dev, "ciu");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003189 if (IS_ERR(host->ciu_clk)) {
3190 dev_dbg(host->dev, "ciu clock not available\n");
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003191 host->bus_hz = host->pdata->bus_hz;
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003192 } else {
3193 ret = clk_prepare_enable(host->ciu_clk);
3194 if (ret) {
3195 dev_err(host->dev, "failed to enable ciu clock\n");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003196 goto err_clk_biu;
3197 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003198
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003199 if (host->pdata->bus_hz) {
3200 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3201 if (ret)
3202 dev_warn(host->dev,
Jaehoon Chung612de4c2014-03-03 11:36:42 +09003203 "Unable to set bus rate to %uHz\n",
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003204 host->pdata->bus_hz);
3205 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003206 host->bus_hz = clk_get_rate(host->ciu_clk);
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003207 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003208
Jaehoon Chung612de4c2014-03-03 11:36:42 +09003209 if (!host->bus_hz) {
3210 dev_err(host->dev,
3211 "Platform data must supply bus speed\n");
3212 ret = -ENODEV;
3213 goto err_clk_ciu;
3214 }
3215
liwei941e3722017-08-11 16:06:23 +08003216 if (!IS_ERR(host->pdata->rstc)) {
3217 reset_control_assert(host->pdata->rstc);
3218 usleep_range(10, 50);
3219 reset_control_deassert(host->pdata->rstc);
3220 }
3221
Yuvaraj Kumar C D002f0d52013-08-31 00:12:19 +09003222 if (drv_data && drv_data->init) {
3223 ret = drv_data->init(host);
3224 if (ret) {
3225 dev_err(host->dev,
3226 "implementation specific init failed\n");
3227 goto err_clk_ciu;
3228 }
3229 }
3230
Kees Cook37977722017-10-30 14:45:00 -07003231 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3232 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3233 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
Addy Ke57e10482015-08-11 01:27:18 +09003234
Will Newtonf95f3852011-01-02 01:11:59 -05003235 spin_lock_init(&host->lock);
Doug Andersonf8c58c12014-12-02 15:42:47 -08003236 spin_lock_init(&host->irq_lock);
Will Newtonf95f3852011-01-02 01:11:59 -05003237 INIT_LIST_HEAD(&host->queue);
3238
Will Newtonf95f3852011-01-02 01:11:59 -05003239 /*
3240 * Get the host data width - this assumes that HCON has been set with
3241 * the correct values.
3242 */
Shawn Lin70692752015-09-16 14:41:37 +08003243 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
Will Newtonf95f3852011-01-02 01:11:59 -05003244 if (!i) {
3245 host->push_data = dw_mci_push_data16;
3246 host->pull_data = dw_mci_pull_data16;
3247 width = 16;
3248 host->data_shift = 1;
3249 } else if (i == 2) {
3250 host->push_data = dw_mci_push_data64;
3251 host->pull_data = dw_mci_pull_data64;
3252 width = 64;
3253 host->data_shift = 3;
3254 } else {
3255 /* Check for a reserved value, and warn if it is */
3256 WARN((i != 1),
3257 "HCON reports a reserved host data width!\n"
3258 "Defaulting to 32-bit access.\n");
3259 host->push_data = dw_mci_push_data32;
3260 host->pull_data = dw_mci_pull_data32;
3261 width = 32;
3262 host->data_shift = 2;
3263 }
3264
3265 /* Reset all blocks */
Shawn Lin37444152016-01-22 15:43:12 +08003266 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3267 ret = -ENODEV;
3268 goto err_clk_ciu;
3269 }
Seungwon Jeon141a7122012-05-22 13:01:03 +09003270
3271 host->dma_ops = host->pdata->dma_ops;
3272 dw_mci_init_dma(host);
Will Newtonf95f3852011-01-02 01:11:59 -05003273
3274 /* Clear the interrupts for the host controller */
3275 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3276 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3277
3278 /* Put in max timeout */
3279 mci_writel(host, TMOUT, 0xFFFFFFFF);
3280
3281 /*
3282 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3283 * Tx Mark = fifo_size / 2 DMA Size = 8
3284 */
James Hoganb86d8252011-06-24 13:57:18 +01003285 if (!host->pdata->fifo_depth) {
3286 /*
3287 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3288 * have been overwritten by the bootloader, just like we're
3289 * about to do, so if you know the value for your hardware, you
3290 * should put it in the platform data.
3291 */
3292 fifo_size = mci_readl(host, FIFOTH);
Jaehoon Chung8234e862012-01-11 09:28:21 +00003293 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
James Hoganb86d8252011-06-24 13:57:18 +01003294 } else {
3295 fifo_size = host->pdata->fifo_depth;
3296 }
3297 host->fifo_depth = fifo_size;
Seungwon Jeon52426892013-08-31 00:13:42 +09003298 host->fifoth_val =
3299 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003300 mci_writel(host, FIFOTH, host->fifoth_val);
Will Newtonf95f3852011-01-02 01:11:59 -05003301
3302 /* disable clock to CIU */
3303 mci_writel(host, CLKENA, 0);
3304 mci_writel(host, CLKSRC, 0);
3305
James Hogan63008762013-03-12 10:43:54 +00003306 /*
3307 * In 2.40a spec, Data offset is changed.
3308 * Need to check the version-id and set data-offset for DATA register.
3309 */
3310 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3311 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3312
Jun Niea0361c12017-01-11 15:35:35 +09003313 if (host->data_addr_override)
3314 host->fifo_reg = host->regs + host->data_addr_override;
3315 else if (host->verid < DW_MMC_240A)
Ben Dooks76184ac2015-03-25 11:27:52 +00003316 host->fifo_reg = host->regs + DATA_OFFSET;
James Hogan63008762013-03-12 10:43:54 +00003317 else
Ben Dooks76184ac2015-03-25 11:27:52 +00003318 host->fifo_reg = host->regs + DATA_240A_OFFSET;
James Hogan63008762013-03-12 10:43:54 +00003319
Will Newtonf95f3852011-01-02 01:11:59 -05003320 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003321 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3322 host->irq_flags, "dw-mci", host);
Will Newtonf95f3852011-01-02 01:11:59 -05003323 if (ret)
Doug Anderson6130e7a2014-10-14 09:33:09 -07003324 goto err_dmaunmap;
Will Newtonf95f3852011-01-02 01:11:59 -05003325
Jaehoon Chungd30a8f72017-06-05 13:41:30 +09003326 /*
Doug Andersonfa0c3282015-02-25 10:11:51 -08003327 * Enable interrupts for command done, data over, data empty,
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303328 * receive ready and error such as transmit, receive timeout, crc error
3329 */
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303330 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3331 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
Doug Andersonfa0c3282015-02-25 10:11:51 -08003332 DW_MCI_ERROR_FLAGS);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003333 /* Enable mci interrupt */
3334 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303335
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003336 dev_info(host->dev,
3337 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303338 host->irq, width, fifo_size);
3339
Will Newtonf95f3852011-01-02 01:11:59 -05003340 /* We need at least one slot to succeed */
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09003341 ret = dw_mci_init_slot(host);
Jaehoon Chung58870242017-06-05 13:41:31 +09003342 if (ret) {
3343 dev_dbg(host->dev, "slot %d init failed\n", i);
Doug Anderson6130e7a2014-10-14 09:33:09 -07003344 goto err_dmaunmap;
Will Newtonf95f3852011-01-02 01:11:59 -05003345 }
3346
Doug Andersonb793f652015-03-11 15:15:14 -07003347 /* Now that slots are all setup, we can enable card detect */
3348 dw_mci_enable_cd(host);
3349
Will Newtonf95f3852011-01-02 01:11:59 -05003350 return 0;
3351
Will Newtonf95f3852011-01-02 01:11:59 -05003352err_dmaunmap:
3353 if (host->use_dma && host->dma_ops->exit)
3354 host->dma_ops->exit(host);
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003355
Guodong Xud6786fe2016-08-12 16:51:26 +08003356 if (!IS_ERR(host->pdata->rstc))
3357 reset_control_assert(host->pdata->rstc);
3358
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003359err_clk_ciu:
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003360 clk_disable_unprepare(host->ciu_clk);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003361
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003362err_clk_biu:
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003363 clk_disable_unprepare(host->biu_clk);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003364
Will Newtonf95f3852011-01-02 01:11:59 -05003365 return ret;
3366}
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303367EXPORT_SYMBOL(dw_mci_probe);
Will Newtonf95f3852011-01-02 01:11:59 -05003368
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303369void dw_mci_remove(struct dw_mci *host)
Will Newtonf95f3852011-01-02 01:11:59 -05003370{
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09003371 dev_dbg(host->dev, "remove slot\n");
Jaehoon Chungb23475f2017-06-05 13:41:32 +09003372 if (host->slot)
Jaehoon Chunge4a65ef72017-06-05 13:41:33 +09003373 dw_mci_cleanup_slot(host->slot);
Will Newtonf95f3852011-01-02 01:11:59 -05003374
Prabu Thangamuthu048fd7e2015-05-28 12:21:06 +00003375 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3376 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3377
Will Newtonf95f3852011-01-02 01:11:59 -05003378 /* disable clock to CIU */
3379 mci_writel(host, CLKENA, 0);
3380 mci_writel(host, CLKSRC, 0);
3381
Will Newtonf95f3852011-01-02 01:11:59 -05003382 if (host->use_dma && host->dma_ops->exit)
3383 host->dma_ops->exit(host);
3384
Guodong Xud6786fe2016-08-12 16:51:26 +08003385 if (!IS_ERR(host->pdata->rstc))
3386 reset_control_assert(host->pdata->rstc);
3387
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003388 clk_disable_unprepare(host->ciu_clk);
3389 clk_disable_unprepare(host->biu_clk);
Will Newtonf95f3852011-01-02 01:11:59 -05003390}
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303391EXPORT_SYMBOL(dw_mci_remove);
3392
3393
Will Newtonf95f3852011-01-02 01:11:59 -05003394
Shawn Line9ed8832016-10-12 10:50:35 +08003395#ifdef CONFIG_PM
Shawn Lined24e1f2016-10-12 10:56:55 +08003396int dw_mci_runtime_suspend(struct device *dev)
Will Newtonf95f3852011-01-02 01:11:59 -05003397{
Shawn Lined24e1f2016-10-12 10:56:55 +08003398 struct dw_mci *host = dev_get_drvdata(dev);
3399
Shawn Lin3fc7eae2015-09-16 14:41:23 +08003400 if (host->use_dma && host->dma_ops->exit)
3401 host->dma_ops->exit(host);
3402
Shawn Lined24e1f2016-10-12 10:56:55 +08003403 clk_disable_unprepare(host->ciu_clk);
3404
Jaehoon Chung42f989c2017-06-05 13:41:34 +09003405 if (host->slot &&
3406 (mmc_can_gpio_cd(host->slot->mmc) ||
3407 !mmc_card_is_removable(host->slot->mmc)))
Shawn Lined24e1f2016-10-12 10:56:55 +08003408 clk_disable_unprepare(host->biu_clk);
3409
Will Newtonf95f3852011-01-02 01:11:59 -05003410 return 0;
3411}
Shawn Lined24e1f2016-10-12 10:56:55 +08003412EXPORT_SYMBOL(dw_mci_runtime_suspend);
Will Newtonf95f3852011-01-02 01:11:59 -05003413
Shawn Lined24e1f2016-10-12 10:56:55 +08003414int dw_mci_runtime_resume(struct device *dev)
Will Newtonf95f3852011-01-02 01:11:59 -05003415{
Jaehoon Chungb23475f2017-06-05 13:41:32 +09003416 int ret = 0;
Shawn Lined24e1f2016-10-12 10:56:55 +08003417 struct dw_mci *host = dev_get_drvdata(dev);
Will Newtonf95f3852011-01-02 01:11:59 -05003418
Jaehoon Chung42f989c2017-06-05 13:41:34 +09003419 if (host->slot &&
3420 (mmc_can_gpio_cd(host->slot->mmc) ||
3421 !mmc_card_is_removable(host->slot->mmc))) {
Shawn Lined24e1f2016-10-12 10:56:55 +08003422 ret = clk_prepare_enable(host->biu_clk);
3423 if (ret)
3424 return ret;
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003425 }
3426
Shawn Lined24e1f2016-10-12 10:56:55 +08003427 ret = clk_prepare_enable(host->ciu_clk);
3428 if (ret)
Joonyoung Shimdf9bcc22016-11-25 12:47:15 +09003429 goto err;
3430
3431 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3432 clk_disable_unprepare(host->ciu_clk);
3433 ret = -ENODEV;
3434 goto err;
3435 }
Shawn Lined24e1f2016-10-12 10:56:55 +08003436
Jonathan Kliegman3bfe6192012-06-14 13:31:55 -04003437 if (host->use_dma && host->dma_ops->init)
Seungwon Jeon141a7122012-05-22 13:01:03 +09003438 host->dma_ops->init(host);
3439
Seungwon Jeon52426892013-08-31 00:13:42 +09003440 /*
3441 * Restore the initial value at FIFOTH register
3442 * And Invalidate the prev_blksz with zero
3443 */
Colin Ian King6b62e122019-09-22 13:54:43 +02003444 mci_writel(host, FIFOTH, host->fifoth_val);
3445 host->prev_blksz = 0;
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003446
Doug Anderson2eb29442013-08-31 00:11:49 +09003447 /* Put in max timeout */
3448 mci_writel(host, TMOUT, 0xFFFFFFFF);
3449
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003450 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3451 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3452 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
Doug Andersonfa0c3282015-02-25 10:11:51 -08003453 DW_MCI_ERROR_FLAGS);
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003454 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3455
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003456
Jaehoon Chunge47c0b92017-06-05 13:41:35 +09003457 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3458 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
Ziyuan Xue9748e02017-01-17 09:22:56 +08003459
Jaehoon Chung58870242017-06-05 13:41:31 +09003460 /* Force setup bus to guarantee available clock output */
Jaehoon Chunge47c0b92017-06-05 13:41:35 +09003461 dw_mci_setup_bus(host->slot, true);
Doug Andersonfa0c3282015-02-25 10:11:51 -08003462
Ulf Hansson7c526602019-09-08 12:12:27 +02003463 /* Re-enable SDIO interrupts. */
3464 if (sdio_irq_claimed(host->slot->mmc))
3465 __dw_mci_enable_sdio_irq(host->slot, 1);
3466
Doug Andersonfa0c3282015-02-25 10:11:51 -08003467 /* Now that slots are all setup, we can enable card detect */
3468 dw_mci_enable_cd(host);
3469
Joonyoung Shimdf9bcc22016-11-25 12:47:15 +09003470 return 0;
3471
3472err:
Jaehoon Chung42f989c2017-06-05 13:41:34 +09003473 if (host->slot &&
3474 (mmc_can_gpio_cd(host->slot->mmc) ||
3475 !mmc_card_is_removable(host->slot->mmc)))
Joonyoung Shimdf9bcc22016-11-25 12:47:15 +09003476 clk_disable_unprepare(host->biu_clk);
3477
Shawn Lined24e1f2016-10-12 10:56:55 +08003478 return ret;
Shawn Line9ed8832016-10-12 10:50:35 +08003479}
3480EXPORT_SYMBOL(dw_mci_runtime_resume);
3481#endif /* CONFIG_PM */
Jaehoon Chung6fe88902011-12-08 19:23:03 +09003482
Will Newtonf95f3852011-01-02 01:11:59 -05003483static int __init dw_mci_init(void)
3484{
Sachin Kamat8e1c4e42013-04-04 11:25:11 +05303485 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303486 return 0;
Will Newtonf95f3852011-01-02 01:11:59 -05003487}
3488
3489static void __exit dw_mci_exit(void)
3490{
Will Newtonf95f3852011-01-02 01:11:59 -05003491}
3492
3493module_init(dw_mci_init);
3494module_exit(dw_mci_exit);
3495
3496MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3497MODULE_AUTHOR("NXP Semiconductor VietNam");
3498MODULE_AUTHOR("Imagination Technologies Ltd");
3499MODULE_LICENSE("GPL v2");