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Bjorn Helgaas7328c8f2018-01-26 11:45:16 -06001// SPDX-License-Identifier: GPL-2.0
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
Bjorn Helgaasdf62ab52018-03-09 16:36:33 -06003 * PCI detection and setup code
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
Krzysztof Wilczynskibbd8810d2019-09-03 13:30:59 +020010#include <linux/msi.h>
Suthikulpanit, Suravee50230712015-10-28 15:50:53 -070011#include <linux/of_device.h>
Murali Karicheride335bb42015-03-03 12:52:13 -050012#include <linux/of_pci.h>
Bjorn Helgaas589fcc22014-09-12 20:02:00 -060013#include <linux/pci_hotplug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
Taku Izumib07461a2015-09-17 10:09:37 -050017#include <linux/aer.h>
Suthikulpanit, Suravee29dbe1f2015-10-28 15:50:54 -070018#include <linux/acpi.h>
Jan Kiszka690f4302018-03-07 08:39:13 +010019#include <linux/hypervisor.h>
Jake Oshins788858e2016-02-16 21:56:22 +000020#include <linux/irqdomain.h>
Mika Westerbergd963f652016-06-02 11:17:13 +030021#include <linux/pm_runtime.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090022#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Stephen Hemminger0b950f02014-01-10 17:14:48 -070027static struct resource busn_resource = {
Yinghai Lu67cdc822012-05-17 18:51:12 -070028 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
Yinghai Lu5cc62c22012-05-17 18:51:11 -070038static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070068/*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -060069 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080071 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070072 */
73int no_pci_devices(void)
74{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080075 struct device *dev;
76 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070077
Suzuki K Poulose6bf85ba2019-07-23 23:18:37 +010078 dev = bus_find_next_device(&pci_bus_type, NULL);
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080079 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070083EXPORT_SYMBOL(no_pci_devices);
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 * PCI Bus Class
87 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040088static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070089{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040090 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
Markus Elfringff0387c2014-11-10 21:02:17 -070092 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070093 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100094 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 kfree(pci_bus);
96}
97
98static struct class pcibus_class = {
99 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400100 .dev_release = &release_pcibus_dev,
Greg Kroah-Hartman56039e62013-07-24 15:05:17 -0700101 .dev_groups = pcibus_groups,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800111{
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
Bjorn Helgaas3e466e22017-11-30 10:58:14 -0600116 /*
117 * Get the lowest of them to find the decode size, and from that
118 * the extent.
119 */
Du Changbin01b37f82018-10-13 08:49:19 +0800120 size = size & ~(size-1);
Yinghai Lu07eddf32006-11-29 13:53:10 -0800121
Bjorn Helgaas3e466e22017-11-30 10:58:14 -0600122 /*
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
125 */
Du Changbin01b37f82018-10-13 08:49:19 +0800126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800127 return 0;
128
129 return size;
130}
131
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800133{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600134 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600135 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600136
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400141 }
142
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400147
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600153 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600156 flags |= IORESOURCE_MEM_64;
157 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600158 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600159 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600160 break;
161 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600162 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400163}
164
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
Yu Zhao0b400c72008-11-22 02:40:40 +0800167/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -0600168 * pci_read_base - Read a PCI BAR
Yu Zhao0b400c72008-11-22 02:40:40 +0800169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
173 *
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400175 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400177 struct resource *res, unsigned int pos)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400178{
Marc Gonzalezdc5205e2017-04-10 19:46:54 +0200179 u32 l = 0, sz = 0, mask;
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600180 u64 l64, sz64, mask64;
Jacob Pan253d2e52010-07-16 10:19:22 -0700181 u16 orig_cmd;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800182 struct pci_bus_region region, inverted_region;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400183
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400185
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600186 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 }
Jacob Pan253d2e52010-07-16 10:19:22 -0700193 }
194
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400195 res->name = pci_name(dev);
196
197 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200198 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
201
202 /*
203 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600204 * If the BAR isn't implemented, all bits must be 0. If it's a
205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400207 */
Myron Stowef795d862014-10-30 11:54:43 -0600208 if (sz == 0xffffffff)
209 sz = 0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400210
211 /*
212 * I don't know how l can have all bits set. Copied from old code.
213 * Maybe it fixes a bug on some ancient platform.
214 */
215 if (l == 0xffffffff)
216 l = 0;
217
218 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
Myron Stowef795d862014-10-30 11:54:43 -0600222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400225 } else {
Myron Stowef795d862014-10-30 11:54:43 -0600226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400229 }
230 } else {
Bjorn Helgaas7a6d3122016-11-28 17:21:02 -0600231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
Myron Stowef795d862014-10-30 11:54:43 -0600233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
Matthias Kaehlcke76dc52682017-04-14 13:38:02 -0700235 mask64 = PCI_ROM_ADDRESS_MASK;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400236 }
237
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600238 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
Myron Stowef795d862014-10-30 11:54:43 -0600246 mask64 |= ((u64)~0 << 32);
247 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400248
Myron Stowef795d862014-10-30 11:54:43 -0600249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400251
Myron Stowef795d862014-10-30 11:54:43 -0600252 if (!sz64)
253 goto fail;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400254
Myron Stowef795d862014-10-30 11:54:43 -0600255 sz64 = pci_size(l64, sz64, mask64);
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600256 if (!sz64) {
Frederick Lawler7506dc72018-01-18 12:55:24 -0600257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600258 pos);
Myron Stowef795d862014-10-30 11:54:43 -0600259 goto fail;
Myron Stowe7e79c5f2014-10-30 11:54:50 -0600260 }
Myron Stowef795d862014-10-30 11:54:43 -0600261
262 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
Frederick Lawler7506dc72018-01-18 12:55:24 -0600268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
Myron Stowef795d862014-10-30 11:54:43 -0600269 pos, (unsigned long long)sz64);
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600270 goto out;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600271 }
272
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600274 /* Above 32-bit boundary; try to reallocate */
Bjorn Helgaasc83bd902014-02-26 11:26:00 -0700275 res->flags |= IORESOURCE_UNSET;
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600276 res->start = 0;
Du Changbin01b37f82018-10-13 08:49:19 +0800277 res->end = sz64 - 1;
Frederick Lawler7506dc72018-01-18 12:55:24 -0600278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
Myron Stowef795d862014-10-30 11:54:43 -0600279 pos, (unsigned long long)l64);
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600280 goto out;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400281 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400282 }
283
Myron Stowef795d862014-10-30 11:54:43 -0600284 region.start = l64;
Du Changbin01b37f82018-10-13 08:49:19 +0800285 region.end = l64 + sz64 - 1;
Myron Stowef795d862014-10-30 11:54:43 -0600286
Yinghai Lufc279852013-12-09 22:54:40 -0800287 pcibios_bus_to_resource(dev->bus, res, &region);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800302 res->flags |= IORESOURCE_UNSET;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800303 res->start = 0;
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600304 res->end = region.end - region.start;
Frederick Lawler7506dc72018-01-18 12:55:24 -0600305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
Myron Stowef795d862014-10-30 11:54:43 -0600306 pos, (unsigned long long)region.start);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800307 }
Kevin Hao96ddef22013-05-25 19:36:26 +0800308
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600315 if (res->flags)
Mohan Kumar34c6b712019-04-20 07:07:20 +0300316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600317
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800319}
320
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400323 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324
Prarit Bhargavaad67b432016-05-11 12:27:16 -0400325 if (dev->non_compliant_bars)
326 return;
327
KarimAllah Ahmedbf4447f2018-03-03 05:33:10 +0100328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
329 if (dev->is_virtfn)
330 return;
331
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400337
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
Dan Williams92b19ff2015-08-10 23:07:06 -0400342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400343 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 }
345}
346
Bjorn Helgaas51c48b32019-01-19 11:35:04 -0600347static void pci_read_bridge_windows(struct pci_dev *bridge)
348{
349 u16 io;
350 u32 pmem, tmp;
351
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 if (!io) {
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357 }
358 if (io)
359 bridge->io_window = 1;
360
361 /*
362 * DECchip 21050 pass 2 errata: the bridge may miss an address
363 * disconnect boundary by one PCI data phase. Workaround: do not
364 * use prefetching on this device.
365 */
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367 return;
368
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 if (!pmem) {
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 0xffe0fff0);
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375 }
376 if (!pmem)
377 return;
378
379 bridge->pref_window = 1;
380
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
383 /*
384 * Bridge claims to have a 64-bit prefetchable memory
385 * window; verify that the upper bits are actually
386 * writable.
387 */
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 0xffffffff);
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 if (tmp)
394 bridge->pref_64_window = 1;
395 }
396}
397
Bill Pemberton15856ad2012-11-21 15:35:00 -0500398static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399{
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600402 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700403 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600404 struct resource *res;
405
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409 /* Support 1K I/O space granularity */
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
412 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600422
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 }
428
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600429 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700431 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600432 region.end = limit + io_granularity - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800433 pcibios_bus_to_resource(dev->bus, res, &region);
Mohan Kumar34c6b712019-04-20 07:07:20 +0300434 pci_info(dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700436}
437
Bill Pemberton15856ad2012-11-21 15:35:00 -0500438static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700439{
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700443 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700444 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600451 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700453 region.start = base;
454 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800455 pcibios_bus_to_resource(dev->bus, res, &region);
Mohan Kumar34c6b712019-04-20 07:07:20 +0300456 pci_info(dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700458}
459
Bill Pemberton15856ad2012-11-21 15:35:00 -0500460static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700461{
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700464 u64 base64, limit64;
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700465 pci_bus_addr_t base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700466 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700467 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600477
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
480
481 /*
482 * Some bridges set the base > limit by default, and some
483 * (broken) BIOSes do not initialize them. If we find
484 * this, just assume they are not being used.
485 */
486 if (mem_base_hi <= mem_limit_hi) {
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 }
490 }
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700491
Yinghai Lu3a9ad0b2015-05-27 17:23:51 -0700492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700494
495 if (base != base64) {
Frederick Lawler7506dc72018-01-18 12:55:24 -0600496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700497 (unsigned long long) base64);
498 return;
499 }
500
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600501 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700506 region.start = base;
507 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800508 pcibios_bus_to_resource(dev->bus, res, &region);
Mohan Kumar34c6b712019-04-20 07:07:20 +0300509 pci_info(dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 }
511}
512
Bill Pemberton15856ad2012-11-21 15:35:00 -0500513void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700514{
515 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700516 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700517 int i;
518
519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
520 return;
521
Frederick Lawler7506dc72018-01-18 12:55:24 -0600522 pci_info(dev, "PCI bridge to %pR%s\n",
Yinghai Lub918c622012-05-17 18:51:11 -0700523 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700524 dev->transparent ? " (subtractive decode)" : "");
525
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
529
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700533
534 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700535 pci_bus_for_each_resource(child->parent, res, i) {
Bjorn Helgaasd739a092014-04-14 16:10:54 -0600536 if (res && res->flags) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
Mohan Kumar34c6b712019-04-20 07:07:20 +0300539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700540 res);
541 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700542 }
543 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700544}
545
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100546static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547{
548 struct pci_bus *b;
549
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100550 b = kzalloc(sizeof(*b), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600551 if (!b)
552 return NULL;
553
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100561#ifdef CONFIG_PCI_DOMAINS_GENERIC
562 if (parent)
563 b->domain_nr = parent->domain_nr;
564#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 return b;
566}
567
Rob Herring98854402020-05-13 17:38:59 -0500568static void pci_release_host_bridge_dev(struct device *dev)
Jiang Liu70efde22013-06-07 16:16:51 -0600569{
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
571
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
Jan Kiszka3bbce532018-05-15 11:07:01 +0200574
575 pci_free_resource_list(&bridge->windows);
Rob Herring76081582019-10-07 20:23:25 -0500576 pci_free_resource_list(&bridge->dma_ranges);
Rob Herring98854402020-05-13 17:38:59 -0500577 kfree(bridge);
Jiang Liu70efde22013-06-07 16:16:51 -0600578}
579
Jean-Philippe Brucker6302bf32019-03-18 16:07:18 +0000580static void pci_init_host_bridge(struct pci_host_bridge *bridge)
Yinghai Lu7b543662012-04-02 18:31:53 -0700581{
Bjorn Helgaas05013482013-06-05 14:22:11 -0600582 INIT_LIST_HEAD(&bridge->windows);
Srinath Manname80a91a2019-05-03 19:35:32 +0530583 INIT_LIST_HEAD(&bridge->dma_ranges);
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100584
Bjorn Helgaas02bfeb42018-03-09 11:21:25 -0600585 /*
586 * We assume we can manage these PCIe features. Some systems may
587 * reserve these for use by the platform itself, e.g., an ACPI BIOS
588 * may implement its own AER handling and use _OSC to prevent the
589 * OS from interfering.
590 */
591 bridge->native_aer = 1;
Mika Westerberg9310f0d2018-05-23 17:22:19 -0500592 bridge->native_pcie_hotplug = 1;
Mika Westerberg1df81a62018-05-23 17:40:23 -0500593 bridge->native_shpc_hotplug = 1;
Bjorn Helgaas02bfeb42018-03-09 11:21:25 -0600594 bridge->native_pme = 1;
Bjorn Helgaasaf8bb9f2018-04-17 10:58:09 -0500595 bridge->native_ltr = 1;
Kuppuswamy Sathyanarayananac1c8e32020-03-23 17:26:07 -0700596 bridge->native_dpc = 1;
Rob Herring98854402020-05-13 17:38:59 -0500597
598 device_initialize(&bridge->dev);
Jean-Philippe Brucker6302bf32019-03-18 16:07:18 +0000599}
600
601struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
602{
603 struct pci_host_bridge *bridge;
604
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
606 if (!bridge)
607 return NULL;
608
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
Bjorn Helgaas02bfeb42018-03-09 11:21:25 -0600611
Yinghai Lu7b543662012-04-02 18:31:53 -0700612 return bridge;
613}
Thierry Redinga52d1442016-11-25 11:57:11 +0100614EXPORT_SYMBOL(pci_alloc_host_bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -0700615
Rob Herring98854402020-05-13 17:38:59 -0500616static void devm_pci_alloc_host_bridge_release(void *data)
617{
618 pci_free_host_bridge(data);
619}
620
Lorenzo Pieralisi5c3f18c2017-06-28 15:13:53 -0500621struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
622 size_t priv)
623{
Rob Herring98854402020-05-13 17:38:59 -0500624 int ret;
Lorenzo Pieralisi5c3f18c2017-06-28 15:13:53 -0500625 struct pci_host_bridge *bridge;
626
Rob Herring98854402020-05-13 17:38:59 -0500627 bridge = pci_alloc_host_bridge(priv);
Lorenzo Pieralisi5c3f18c2017-06-28 15:13:53 -0500628 if (!bridge)
629 return NULL;
630
Rob Herring98854402020-05-13 17:38:59 -0500631 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
632 bridge);
633 if (ret)
634 return NULL;
Lorenzo Pieralisi5c3f18c2017-06-28 15:13:53 -0500635
636 return bridge;
637}
638EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
639
Lorenzo Pieralisidff79b92017-06-28 15:13:52 -0500640void pci_free_host_bridge(struct pci_host_bridge *bridge)
641{
Rob Herring98854402020-05-13 17:38:59 -0500642 put_device(&bridge->dev);
Lorenzo Pieralisidff79b92017-06-28 15:13:52 -0500643}
644EXPORT_SYMBOL(pci_free_host_bridge);
645
Bjorn Helgaase56faff2020-02-28 15:02:03 -0600646/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
Stephen Hemminger0b950f02014-01-10 17:14:48 -0700647static const unsigned char pcix_bus_speed[] = {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500648 PCI_SPEED_UNKNOWN, /* 0 */
649 PCI_SPEED_66MHz_PCIX, /* 1 */
650 PCI_SPEED_100MHz_PCIX, /* 2 */
651 PCI_SPEED_133MHz_PCIX, /* 3 */
652 PCI_SPEED_UNKNOWN, /* 4 */
653 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
654 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
655 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
656 PCI_SPEED_UNKNOWN, /* 8 */
657 PCI_SPEED_66MHz_PCIX_266, /* 9 */
658 PCI_SPEED_100MHz_PCIX_266, /* A */
659 PCI_SPEED_133MHz_PCIX_266, /* B */
660 PCI_SPEED_UNKNOWN, /* C */
661 PCI_SPEED_66MHz_PCIX_533, /* D */
662 PCI_SPEED_100MHz_PCIX_533, /* E */
663 PCI_SPEED_133MHz_PCIX_533 /* F */
664};
665
Bjorn Helgaase56faff2020-02-28 15:02:03 -0600666/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
Jacob Keller343e51a2013-07-31 06:53:16 +0000667const unsigned char pcie_link_speed[] = {
Matthew Wilcox3749c512009-12-13 08:11:32 -0500668 PCI_SPEED_UNKNOWN, /* 0 */
669 PCIE_SPEED_2_5GT, /* 1 */
670 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500671 PCIE_SPEED_8_0GT, /* 3 */
Jay Fang1acfb9b2018-03-12 17:13:32 +0800672 PCIE_SPEED_16_0GT, /* 4 */
Gustavo Pimentelde76cda2019-06-04 18:24:43 +0200673 PCIE_SPEED_32_0GT, /* 5 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500674 PCI_SPEED_UNKNOWN, /* 6 */
675 PCI_SPEED_UNKNOWN, /* 7 */
676 PCI_SPEED_UNKNOWN, /* 8 */
677 PCI_SPEED_UNKNOWN, /* 9 */
678 PCI_SPEED_UNKNOWN, /* A */
679 PCI_SPEED_UNKNOWN, /* B */
680 PCI_SPEED_UNKNOWN, /* C */
681 PCI_SPEED_UNKNOWN, /* D */
682 PCI_SPEED_UNKNOWN, /* E */
683 PCI_SPEED_UNKNOWN /* F */
684};
Bjorn Helgaase56faff2020-02-28 15:02:03 -0600685EXPORT_SYMBOL_GPL(pcie_link_speed);
686
687const char *pci_speed_string(enum pci_bus_speed speed)
688{
689 /* Indexed by the pci_bus_speed enum */
690 static const char *speed_strings[] = {
691 "33 MHz PCI", /* 0x00 */
692 "66 MHz PCI", /* 0x01 */
693 "66 MHz PCI-X", /* 0x02 */
694 "100 MHz PCI-X", /* 0x03 */
695 "133 MHz PCI-X", /* 0x04 */
696 NULL, /* 0x05 */
697 NULL, /* 0x06 */
698 NULL, /* 0x07 */
699 NULL, /* 0x08 */
700 "66 MHz PCI-X 266", /* 0x09 */
701 "100 MHz PCI-X 266", /* 0x0a */
702 "133 MHz PCI-X 266", /* 0x0b */
703 "Unknown AGP", /* 0x0c */
704 "1x AGP", /* 0x0d */
705 "2x AGP", /* 0x0e */
706 "4x AGP", /* 0x0f */
707 "8x AGP", /* 0x10 */
708 "66 MHz PCI-X 533", /* 0x11 */
709 "100 MHz PCI-X 533", /* 0x12 */
710 "133 MHz PCI-X 533", /* 0x13 */
711 "2.5 GT/s PCIe", /* 0x14 */
712 "5.0 GT/s PCIe", /* 0x15 */
713 "8.0 GT/s PCIe", /* 0x16 */
714 "16.0 GT/s PCIe", /* 0x17 */
715 "32.0 GT/s PCIe", /* 0x18 */
716 };
717
718 if (speed < ARRAY_SIZE(speed_strings))
719 return speed_strings[speed];
720 return "Unknown";
721}
722EXPORT_SYMBOL_GPL(pci_speed_string);
Matthew Wilcox3749c512009-12-13 08:11:32 -0500723
724void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
725{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700726 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500727}
728EXPORT_SYMBOL_GPL(pcie_update_link_speed);
729
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500730static unsigned char agp_speeds[] = {
731 AGP_UNKNOWN,
732 AGP_1X,
733 AGP_2X,
734 AGP_4X,
735 AGP_8X
736};
737
738static enum pci_bus_speed agp_speed(int agp3, int agpstat)
739{
740 int index = 0;
741
742 if (agpstat & 4)
743 index = 3;
744 else if (agpstat & 2)
745 index = 2;
746 else if (agpstat & 1)
747 index = 1;
748 else
749 goto out;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700750
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500751 if (agp3) {
752 index += 2;
753 if (index == 5)
754 index = 0;
755 }
756
757 out:
758 return agp_speeds[index];
759}
760
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500761static void pci_set_bus_speed(struct pci_bus *bus)
762{
763 struct pci_dev *bridge = bus->self;
764 int pos;
765
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500766 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
767 if (!pos)
768 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
769 if (pos) {
770 u32 agpstat, agpcmd;
771
772 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
773 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
774
775 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
776 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
777 }
778
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500779 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
780 if (pos) {
781 u16 status;
782 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500783
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700784 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
785 &status);
786
787 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500788 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700789 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500790 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700791 } else if (status & PCI_X_SSTATUS_133MHZ) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400792 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500793 max = PCI_SPEED_133MHz_PCIX_ECC;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400794 else
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500795 max = PCI_SPEED_133MHz_PCIX;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500796 } else {
797 max = PCI_SPEED_66MHz_PCIX;
798 }
799
800 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700801 bus->cur_bus_speed = pcix_bus_speed[
802 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500803
804 return;
805 }
806
Yijing Wangfdfe1512013-09-05 15:55:29 +0800807 if (pci_is_pcie(bridge)) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500808 u32 linkcap;
809 u16 linksta;
810
Jiang Liu59875ae2012-07-24 17:20:06 +0800811 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700812 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Keith Buschf0157162018-09-20 10:27:17 -0600813 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500814
Jiang Liu59875ae2012-07-24 17:20:06 +0800815 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500816 pcie_update_link_speed(bus, linksta);
817 }
818}
819
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100820static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
821{
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100822 struct irq_domain *d;
823
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100824 /*
825 * Any firmware interface that can resolve the msi_domain
826 * should be called from here.
827 */
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100828 d = pci_host_bridge_of_msi_domain(bus);
Suravee Suthikulpanit471036b2015-12-10 08:55:27 -0800829 if (!d)
830 d = pci_host_bridge_acpi_msi_domain(bus);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100831
Jake Oshins788858e2016-02-16 21:56:22 +0000832#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
833 /*
834 * If no IRQ domain was found via the OF tree, try looking it up
835 * directly through the fwnode_handle.
836 */
837 if (!d) {
838 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
839
840 if (fwnode)
841 d = irq_find_matching_fwnode(fwnode,
842 DOMAIN_BUS_PCI_MSI);
843 }
844#endif
845
Marc Zyngierb165e2b2015-07-28 14:46:12 +0100846 return d;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100847}
848
849static void pci_set_bus_msi_domain(struct pci_bus *bus)
850{
851 struct irq_domain *d;
Alex Williamson38ea72b2015-09-18 15:08:54 -0600852 struct pci_bus *b;
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100853
854 /*
Alex Williamson38ea72b2015-09-18 15:08:54 -0600855 * The bus can be a root bus, a subordinate bus, or a virtual bus
856 * created by an SR-IOV device. Walk up to the first bridge device
857 * found or derive the domain from the host bridge.
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100858 */
Alex Williamson38ea72b2015-09-18 15:08:54 -0600859 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
860 if (b->self)
861 d = dev_get_msi_domain(&b->self->dev);
862 }
863
864 if (!d)
865 d = pci_host_bridge_msi_domain(b);
Marc Zyngier44aa0c62015-07-28 14:46:11 +0100866
867 dev_set_msi_domain(&bus->dev, d);
868}
869
Lorenzo Pieralisicea9bc02017-06-28 15:13:55 -0500870static int pci_register_host_bridge(struct pci_host_bridge *bridge)
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100871{
872 struct device *parent = bridge->dev.parent;
873 struct resource_entry *window, *n;
874 struct pci_bus *bus, *b;
875 resource_size_t offset;
876 LIST_HEAD(resources);
877 struct resource *res;
878 char addr[64], *fmt;
879 const char *name;
880 int err;
881
882 bus = pci_alloc_bus(NULL);
883 if (!bus)
884 return -ENOMEM;
885
886 bridge->bus = bus;
887
Bjorn Helgaas3e466e22017-11-30 10:58:14 -0600888 /* Temporarily move resources off the list */
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100889 list_splice_init(&bridge->windows, &resources);
890 bus->sysdata = bridge->sysdata;
891 bus->msi = bridge->msi;
892 bus->ops = bridge->ops;
893 bus->number = bus->busn_res.start = bridge->busnr;
894#ifdef CONFIG_PCI_DOMAINS_GENERIC
895 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
896#endif
897
898 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
899 if (b) {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -0600900 /* Ignore it if we already got here via a different bridge */
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100901 dev_dbg(&b->dev, "bus already known\n");
902 err = -EEXIST;
903 goto free;
904 }
905
906 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
907 bridge->busnr);
908
909 err = pcibios_root_bridge_prepare(bridge);
910 if (err)
911 goto free;
912
Rob Herring98854402020-05-13 17:38:59 -0500913 err = device_add(&bridge->dev);
Rob Herring1b54ae82020-05-13 17:38:58 -0500914 if (err) {
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100915 put_device(&bridge->dev);
Rob Herring1b54ae82020-05-13 17:38:58 -0500916 goto free;
917 }
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100918 bus->bridge = get_device(&bridge->dev);
919 device_enable_async_suspend(bus->bridge);
920 pci_set_bus_of_node(bus);
921 pci_set_bus_msi_domain(bus);
922
923 if (!parent)
924 set_dev_node(bus->bridge, pcibus_to_node(bus));
925
926 bus->dev.class = &pcibus_class;
927 bus->dev.parent = bus->bridge;
928
929 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
930 name = dev_name(&bus->dev);
931
932 err = device_register(&bus->dev);
933 if (err)
934 goto unregister;
935
936 pcibios_add_bus(bus);
937
938 /* Create legacy_io and legacy_mem files for this bus */
939 pci_create_legacy_files(bus);
940
941 if (parent)
942 dev_info(parent, "PCI host bridge to bus %s\n", name);
943 else
944 pr_info("PCI host bridge to bus %s\n", name);
945
Yunsheng Linad508612019-10-19 14:45:43 +0800946 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
947 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
948
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100949 /* Add initial resources to the bus */
950 resource_list_for_each_entry_safe(window, n, &resources) {
951 list_move_tail(&window->node, &bridge->windows);
952 offset = window->offset;
953 res = window->res;
954
955 if (res->flags & IORESOURCE_BUS)
956 pci_bus_insert_busn_res(bus, bus->number, res->end);
957 else
958 pci_bus_add_resource(bus, res, 0);
959
960 if (offset) {
961 if (resource_type(res) == IORESOURCE_IO)
962 fmt = " (bus address [%#06llx-%#06llx])";
963 else
964 fmt = " (bus address [%#010llx-%#010llx])";
965
966 snprintf(addr, sizeof(addr), fmt,
967 (unsigned long long)(res->start - offset),
968 (unsigned long long)(res->end - offset));
969 } else
970 addr[0] = '\0';
971
972 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
973 }
974
975 down_write(&pci_bus_sem);
976 list_add_tail(&bus->node, &pci_root_buses);
977 up_write(&pci_bus_sem);
978
979 return 0;
980
981unregister:
982 put_device(&bridge->dev);
Rob Herring98854402020-05-13 17:38:59 -0500983 device_del(&bridge->dev);
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +0100984
985free:
986 kfree(bus);
987 return err;
988}
989
Gilles Buloz17e8f0d2018-05-03 15:21:44 -0500990static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
991{
992 int pos;
993 u32 status;
994
995 /*
996 * If extended config space isn't accessible on a bridge's primary
997 * bus, we certainly can't access it on the secondary bus.
998 */
999 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1000 return false;
1001
1002 /*
1003 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1004 * extended config space is accessible on the primary, it's also
1005 * accessible on the secondary.
1006 */
1007 if (pci_is_pcie(bridge) &&
1008 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1009 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1010 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1011 return true;
1012
1013 /*
1014 * For the other bridge types:
1015 * - PCI-to-PCI bridges
1016 * - PCIe-to-PCI/PCI-X forward bridges
1017 * - PCI/PCI-X-to-PCIe reverse bridges
1018 * extended config space on the secondary side is only accessible
1019 * if the bridge supports PCI-X Mode 2.
1020 */
1021 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1022 if (!pos)
1023 return false;
1024
1025 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1026 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1027}
1028
Adrian Bunkcbd4e052008-04-18 13:53:55 -07001029static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1030 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031{
1032 struct pci_bus *child;
1033 int i;
Yinghai Lu4f535092013-01-21 13:20:52 -08001034 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001036 /* Allocate a new bus and inherit stuff from the parent */
Catalin Marinas670ba0c2014-09-29 15:29:26 +01001037 child = pci_alloc_bus(parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038 if (!child)
1039 return NULL;
1040
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 child->parent = parent;
1042 child->ops = parent->ops;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +02001043 child->msi = parent->msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +02001045 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001047 /*
1048 * Initialize some portions of the bus device, but don't register
1049 * it now as the parent is not properly set up yet.
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001050 */
1051 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +01001052 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001054 /* Set up the primary, secondary and subordinate bus numbers */
Yinghai Lub918c622012-05-17 18:51:11 -07001055 child->number = child->busn_res.start = busnr;
1056 child->primary = parent->busn_res.start;
1057 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058
Yinghai Lu4f535092013-01-21 13:20:52 -08001059 if (!bridge) {
1060 child->dev.parent = parent->bridge;
1061 goto add_dev;
1062 }
Yu Zhao3789fa82008-11-22 02:41:07 +08001063
1064 child->self = bridge;
1065 child->bridge = get_device(&bridge->dev);
Yinghai Lu4f535092013-01-21 13:20:52 -08001066 child->dev.parent = child->bridge;
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001067 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -05001068 pci_set_bus_speed(child);
1069
Gilles Buloz17e8f0d2018-05-03 15:21:44 -05001070 /*
1071 * Check whether extended config space is accessible on the child
1072 * bus. Note that we currently assume it is always accessible on
1073 * the root bus.
1074 */
1075 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1076 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1077 pci_info(child, "extended config space not accessible\n");
1078 }
1079
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001080 /* Set up default resource pointers and names */
Yu Zhaofde09c62008-11-22 02:39:32 +08001081 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1083 child->resource[i]->name = child->name;
1084 }
1085 bridge->subordinate = child;
1086
Yinghai Lu4f535092013-01-21 13:20:52 -08001087add_dev:
Marc Zyngier44aa0c62015-07-28 14:46:11 +01001088 pci_set_bus_msi_domain(child);
Yinghai Lu4f535092013-01-21 13:20:52 -08001089 ret = device_register(&child->dev);
1090 WARN_ON(ret < 0);
1091
Jiang Liu10a95742013-04-12 05:44:20 +00001092 pcibios_add_bus(child);
1093
Thierry Reding057bd2e2016-02-09 15:30:47 +01001094 if (child->ops->add_bus) {
1095 ret = child->ops->add_bus(child);
1096 if (WARN_ON(ret < 0))
1097 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1098 }
1099
Yinghai Lu4f535092013-01-21 13:20:52 -08001100 /* Create legacy_io and legacy_mem files for this bus */
1101 pci_create_legacy_files(child);
1102
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 return child;
1104}
1105
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001106struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1107 int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108{
1109 struct pci_bus *child;
1110
1111 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -07001112 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +08001113 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001115 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -07001116 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117 return child;
1118}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001119EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120
Rajat Jainf3dbd802014-09-02 16:26:00 -07001121static void pci_enable_crs(struct pci_dev *pdev)
1122{
1123 u16 root_cap = 0;
1124
1125 /* Enable CRS Software Visibility if supported */
1126 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1127 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1128 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1129 PCI_EXP_RTCTL_CRSSVE);
1130}
1131
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001132static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1133 unsigned int available_buses);
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301134/**
1135 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1136 * numbers from EA capability.
1137 * @dev: Bridge
1138 * @sec: updated with secondary bus number from EA
1139 * @sub: updated with subordinate bus number from EA
1140 *
Subbaraya Sundeep73884a72019-11-04 12:27:44 +05301141 * If @dev is a bridge with EA capability that specifies valid secondary
1142 * and subordinate bus numbers, return true with the bus numbers in @sec
1143 * and @sub. Otherwise return false.
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301144 */
1145static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1146{
1147 int ea, offset;
1148 u32 dw;
Subbaraya Sundeep73884a72019-11-04 12:27:44 +05301149 u8 ea_sec, ea_sub;
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301150
1151 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1152 return false;
1153
1154 /* find PCI EA capability in list */
1155 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1156 if (!ea)
1157 return false;
1158
1159 offset = ea + PCI_EA_FIRST_ENT;
1160 pci_read_config_dword(dev, offset, &dw);
Subbaraya Sundeep73884a72019-11-04 12:27:44 +05301161 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1162 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1163 if (ea_sec == 0 || ea_sub < ea_sec)
1164 return false;
1165
1166 *sec = ea_sec;
1167 *sub = ea_sub;
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301168 return true;
1169}
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001170
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171/*
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001172 * pci_scan_bridge_extend() - Scan buses behind a bridge
1173 * @bus: Parent bus the bridge is on
1174 * @dev: Bridge itself
1175 * @max: Starting subordinate number of buses behind this bridge
1176 * @available_buses: Total number of buses available for this bridge and
1177 * the devices below. After the minimal bus space has
1178 * been allocated the remaining buses will be
1179 * distributed equally between hotplug-capable bridges.
1180 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1181 * that need to be reconfigured.
1182 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 * If it's a bridge, configure it and scan the bus behind it.
1184 * For CardBus bridges, we don't scan behind as the devices will
1185 * be handled by the bridge driver itself.
1186 *
1187 * We need to process bridges in two passes -- first we scan those
1188 * already configured by the BIOS and after we are done with all of
1189 * them, we proceed to assigning numbers to the remaining buses in
1190 * order to avoid overlaps between old and new bus numbers.
Mika Westerberg70f78802018-05-28 15:47:56 +03001191 *
1192 * Return: New subordinate number covering all buses behind this bridge.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001194static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1195 int max, unsigned int available_buses,
1196 int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197{
1198 struct pci_bus *child;
1199 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +01001200 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001202 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +11001203 int broken = 0;
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301204 bool fixed_buses;
1205 u8 fixed_sec, fixed_sub;
1206 int next_busnr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207
Mika Westerbergd963f652016-06-02 11:17:13 +03001208 /*
1209 * Make sure the bridge is powered on to be able to access config
1210 * space of devices below it.
1211 */
1212 pm_runtime_get_sync(&dev->dev);
1213
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001215 primary = buses & 0xFF;
1216 secondary = (buses >> 8) & 0xFF;
1217 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218
Frederick Lawler7506dc72018-01-18 12:55:24 -06001219 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001220 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221
Yinghai Lu71f6bd42012-01-30 12:25:24 +01001222 if (!primary && (primary != bus->number) && secondary && subordinate) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06001223 pci_warn(dev, "Primary bus is hard wired to 0\n");
Yinghai Lu71f6bd42012-01-30 12:25:24 +01001224 primary = bus->number;
1225 }
1226
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +11001227 /* Check if setup is sensible at all */
1228 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -07001229 (primary != bus->number || secondary <= bus->number ||
Bjorn Helgaas12d87062014-09-19 11:08:40 -06001230 secondary > subordinate)) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06001231 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
Yinghai Lu1965f662012-09-10 17:19:33 -07001232 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +11001233 broken = 1;
1234 }
1235
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001236 /*
1237 * Disable Master-Abort Mode during probing to avoid reporting of
1238 * bus errors in some architectures.
1239 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1241 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1242 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1243
Rajat Jainf3dbd802014-09-02 16:26:00 -07001244 pci_enable_crs(dev);
1245
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001246 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1247 !is_cardbus && !broken) {
1248 unsigned int cmax;
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001249
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 /*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001251 * Bus already configured by firmware, process it in the
1252 * first pass and just note the configuration.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253 */
1254 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +00001255 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256
1257 /*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001258 * The bus might already exist for two reasons: Either we
1259 * are rescanning the bus or the bus is reachable through
1260 * more than one bridge. The second case can happen with
1261 * the i450NX chipset.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001263 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -06001264 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001265 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -06001266 if (!child)
1267 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -06001268 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -07001269 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -06001270 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271 }
1272
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 cmax = pci_scan_child_bus(child);
Andreas Noeverc95b0bd2014-01-23 21:59:27 +01001274 if (cmax > subordinate)
Frederick Lawler7506dc72018-01-18 12:55:24 -06001275 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
Andreas Noeverc95b0bd2014-01-23 21:59:27 +01001276 subordinate, cmax);
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001277
1278 /* Subordinate should equal child->busn_res.end */
Andreas Noeverc95b0bd2014-01-23 21:59:27 +01001279 if (subordinate > max)
1280 max = subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 } else {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001282
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283 /*
1284 * We need to assign a number to this bus which we always
1285 * do in the second pass.
1286 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001287 if (!pass) {
Andreas Noever619c8c32014-01-23 21:59:23 +01001288 if (pcibios_assign_all_busses() || broken || is_cardbus)
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001289
1290 /*
1291 * Temporarily disable forwarding of the
1292 * configuration cycles on all bridges in
1293 * this bus segment to avoid possible
1294 * conflicts in the second pass between two
1295 * bridges programmed with overlapping bus
1296 * ranges.
1297 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001298 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1299 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +00001300 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -07001301 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302
1303 /* Clear errors */
1304 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1305
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301306 /* Read bus numbers from EA Capability (if present) */
1307 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1308 if (fixed_buses)
1309 next_busnr = fixed_sec;
1310 else
1311 next_busnr = max + 1;
1312
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001313 /*
1314 * Prevent assigning a bus number that already exists.
1315 * This can happen when a bridge is hot-plugged, so in this
1316 * case we only re-scan this bus.
1317 */
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301318 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001319 if (!child) {
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301320 child = pci_add_new_bus(bus, dev, next_busnr);
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001321 if (!child)
1322 goto out;
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301323 pci_bus_insert_busn_res(child, next_busnr,
Mika Westerberga20c7f32017-10-13 21:35:43 +03001324 bus->busn_res.end);
Tiejun Chenb1a98b62011-06-02 11:02:50 +08001325 }
Andreas Noever9a4d7d82014-01-23 21:59:21 +01001326 max++;
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001327 if (available_buses)
1328 available_buses--;
1329
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330 buses = (buses & 0xff000000)
1331 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -07001332 | ((unsigned int)(child->busn_res.start) << 8)
1333 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334
1335 /*
1336 * yenta.c forces a secondary latency timer of 176.
1337 * Copy that behaviour here.
1338 */
1339 if (is_cardbus) {
1340 buses &= ~0xff000000;
1341 buses |= CARDBUS_LATENCY_TIMER << 24;
1342 }
Jesper Juhl7c867c82011-01-24 21:14:33 +01001343
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001344 /* We need to blast all three values with a single write */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1346
1347 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -07001348 child->bridge_ctl = bctl;
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001349 max = pci_scan_child_bus_extend(child, available_buses);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350 } else {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001351
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 /*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001353 * For CardBus bridges, we leave 4 bus numbers as
1354 * cards with a PCI-to-PCI bridge can be inserted
1355 * later.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001357 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
Dominik Brodowski49887942005-12-08 16:53:12 +01001358 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -07001359 if (pci_find_bus(pci_domain_nr(bus),
1360 max+i+1))
1361 break;
Dominik Brodowski49887942005-12-08 16:53:12 +01001362 while (parent->parent) {
1363 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -07001364 (parent->busn_res.end > max) &&
1365 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +01001366 j = 1;
1367 }
1368 parent = parent->parent;
1369 }
1370 if (j) {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001371
Dominik Brodowski49887942005-12-08 16:53:12 +01001372 /*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001373 * Often, there are two CardBus
1374 * bridges -- try to leave one
1375 * valid bus number for each one.
Dominik Brodowski49887942005-12-08 16:53:12 +01001376 */
1377 i /= 2;
1378 break;
1379 }
1380 }
Rajesh Shahcc574502005-04-28 00:25:47 -07001381 max += i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382 }
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001383
Subbaraya Sundeep2dbce592018-11-19 18:44:32 +05301384 /*
1385 * Set subordinate bus number to its real value.
1386 * If fixed subordinate bus number exists from EA
1387 * capability then use it.
1388 */
1389 if (fixed_buses)
1390 max = fixed_sub;
Yinghai Lubc76b732012-05-17 18:51:13 -07001391 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1393 }
1394
Gary Hadecb3576f2008-02-08 14:00:52 -08001395 sprintf(child->name,
1396 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1397 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398
Mika Westerberge412d632018-05-24 13:23:52 -05001399 /* Check that all devices are accessible */
Dominik Brodowski49887942005-12-08 16:53:12 +01001400 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -07001401 if ((child->busn_res.end > bus->busn_res.end) ||
1402 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +01001403 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -07001404 (child->busn_res.end < bus->number)) {
Mika Westerberge412d632018-05-24 13:23:52 -05001405 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1406 &child->busn_res);
1407 break;
Dominik Brodowski49887942005-12-08 16:53:12 +01001408 }
1409 bus = bus->parent;
1410 }
1411
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +00001412out:
1413 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1414
Mika Westerbergd963f652016-06-02 11:17:13 +03001415 pm_runtime_put(&dev->dev);
1416
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417 return max;
1418}
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001419
1420/*
1421 * pci_scan_bridge() - Scan buses behind a bridge
1422 * @bus: Parent bus the bridge is on
1423 * @dev: Bridge itself
1424 * @max: Starting subordinate number of buses behind this bridge
1425 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1426 * that need to be reconfigured.
1427 *
1428 * If it's a bridge, configure it and scan the bus behind it.
1429 * For CardBus bridges, we don't scan behind as the devices will
1430 * be handled by the bridge driver itself.
1431 *
1432 * We need to process bridges in two passes -- first we scan those
1433 * already configured by the BIOS and after we are done with all of
1434 * them, we proceed to assigning numbers to the remaining buses in
1435 * order to avoid overlaps between old and new bus numbers.
Mika Westerberg70f78802018-05-28 15:47:56 +03001436 *
1437 * Return: New subordinate number covering all buses behind this bridge.
Mika Westerberg1c02ea82017-10-13 21:35:44 +03001438 */
1439int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1440{
1441 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1442}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001443EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444
1445/*
1446 * Read interrupt line and base address registers.
1447 * The architecture-dependent code can tweak these, of course.
1448 */
1449static void pci_read_irq(struct pci_dev *dev)
1450{
1451 unsigned char irq;
1452
KarimAllah Ahmedbe20f6b2018-01-17 19:30:29 +01001453 /* VFs are not allowed to use INTx, so skip the config reads */
1454 if (dev->is_virtfn) {
1455 dev->pin = 0;
1456 dev->irq = 0;
1457 return;
1458 }
1459
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -08001461 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 if (irq)
1463 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1464 dev->irq = irq;
1465}
1466
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001467void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +08001468{
1469 int pos;
1470 u16 reg16;
Yijing Wangd0751b92015-05-21 15:05:02 +08001471 int type;
1472 struct pci_dev *parent;
Yu Zhao480b93b2009-03-20 11:25:14 +08001473
1474 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1475 if (!pos)
1476 return;
Bjorn Helgaas51ebfc92017-01-11 09:11:53 -06001477
Kenji Kaneshige0efea002009-11-05 12:05:11 +09001478 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +08001479 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +08001480 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -05001481 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1482 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yijing Wangd0751b92015-05-21 15:05:02 +08001483
Mika Westerbergca784102019-08-22 11:55:53 +03001484 parent = pci_upstream_bridge(pdev);
1485 if (!parent)
1486 return;
1487
Yijing Wangd0751b92015-05-21 15:05:02 +08001488 /*
Mika Westerbergca784102019-08-22 11:55:53 +03001489 * Some systems do not identify their upstream/downstream ports
1490 * correctly so detect impossible configurations here and correct
1491 * the port type accordingly.
Yijing Wangd0751b92015-05-21 15:05:02 +08001492 */
1493 type = pci_pcie_type(pdev);
Mika Westerbergca784102019-08-22 11:55:53 +03001494 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
Yijing Wangb35b1df2015-08-17 18:47:58 +08001495 /*
Mika Westerbergca784102019-08-22 11:55:53 +03001496 * If pdev claims to be downstream port but the parent
1497 * device is also downstream port assume pdev is actually
1498 * upstream port.
Yijing Wangb35b1df2015-08-17 18:47:58 +08001499 */
Mika Westerbergca784102019-08-22 11:55:53 +03001500 if (pcie_downstream_port(parent)) {
1501 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1502 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1503 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1504 }
1505 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1506 /*
1507 * If pdev claims to be upstream port but the parent
1508 * device is also upstream port assume pdev is actually
1509 * downstream port.
1510 */
1511 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1512 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1513 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1514 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1515 }
Yijing Wangd0751b92015-05-21 15:05:02 +08001516 }
Yu Zhao480b93b2009-03-20 11:25:14 +08001517}
1518
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +00001519void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -07001520{
Eric W. Biederman28760482009-09-09 14:09:24 -07001521 u32 reg32;
1522
Jiang Liu59875ae2012-07-24 17:20:06 +08001523 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -07001524 if (reg32 & PCI_EXP_SLTCAP_HPC)
1525 pdev->is_hotplug_bridge = 1;
1526}
1527
Lukas Wunner8531e282017-03-10 21:23:45 +01001528static void set_pcie_thunderbolt(struct pci_dev *dev)
1529{
1530 int vsec = 0;
1531 u32 header;
1532
1533 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1534 PCI_EXT_CAP_ID_VNDR))) {
1535 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1536
1537 /* Is the device part of a Thunderbolt controller? */
1538 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1539 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1540 dev->is_thunderbolt = 1;
1541 return;
1542 }
1543 }
1544}
1545
Mika Westerberg617654a2018-08-16 12:28:48 +03001546static void set_pcie_untrusted(struct pci_dev *dev)
1547{
1548 struct pci_dev *parent;
1549
1550 /*
1551 * If the upstream bridge is untrusted we treat this device
1552 * untrusted as well.
1553 */
1554 parent = pci_upstream_bridge(dev);
1555 if (parent && parent->untrusted)
1556 dev->untrusted = true;
1557}
1558
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001559/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001560 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
Alex Williamson78916b02014-05-05 14:20:51 -06001561 * @dev: PCI device
1562 *
1563 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1564 * when forwarding a type1 configuration request the bridge must check that
1565 * the extended register address field is zero. The bridge is not permitted
1566 * to forward the transactions and must handle it as an Unsupported Request.
1567 * Some bridges do not follow this rule and simply drop the extended register
1568 * bits, resulting in the standard config space being aliased, every 256
1569 * bytes across the entire configuration space. Test for this condition by
1570 * comparing the first dword of each potential alias to the vendor/device ID.
1571 * Known offenders:
1572 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1573 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1574 */
1575static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1576{
1577#ifdef CONFIG_PCI_QUIRKS
1578 int pos;
1579 u32 header, tmp;
1580
1581 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1582
1583 for (pos = PCI_CFG_SPACE_SIZE;
1584 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1585 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1586 || header != tmp)
1587 return false;
1588 }
1589
1590 return true;
1591#else
1592 return false;
1593#endif
1594}
1595
1596/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001597 * pci_cfg_space_size - Get the configuration space size of the PCI device
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001598 * @dev: PCI device
1599 *
1600 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1601 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1602 * access it. Maybe we don't have a way to generate extended config space
1603 * accesses, or the device is behind a reverse Express bridge. So we try
1604 * reading the dword at 0x100 which must either be 0 or a valid extended
1605 * capability header.
1606 */
1607static int pci_cfg_space_size_ext(struct pci_dev *dev)
1608{
1609 u32 status;
1610 int pos = PCI_CFG_SPACE_SIZE;
1611
1612 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001613 return PCI_CFG_SPACE_SIZE;
Alex Williamson78916b02014-05-05 14:20:51 -06001614 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001615 return PCI_CFG_SPACE_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001616
1617 return PCI_CFG_SPACE_EXP_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001618}
1619
1620int pci_cfg_space_size(struct pci_dev *dev)
1621{
1622 int pos;
1623 u32 status;
1624 u16 class;
1625
KarimAllah Ahmed975bb8b2018-10-11 11:49:58 -05001626#ifdef CONFIG_PCI_IOV
Alex Williamson06013b62019-06-13 16:57:20 -06001627 /*
1628 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1629 * implement a PCIe capability and therefore must implement extended
1630 * config space. We can skip the NO_EXTCFG test below and the
1631 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1632 * the fact that the SR-IOV capability on the PF resides in extended
1633 * config space and must be accessible and non-aliased to have enabled
1634 * support for this VF. This is a micro performance optimization for
1635 * systems supporting many VFs.
1636 */
1637 if (dev->is_virtfn)
1638 return PCI_CFG_SPACE_EXP_SIZE;
KarimAllah Ahmed975bb8b2018-10-11 11:49:58 -05001639#endif
1640
Gilles Buloz17e8f0d2018-05-03 15:21:44 -05001641 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1642 return PCI_CFG_SPACE_SIZE;
1643
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001644 class = dev->class >> 8;
1645 if (class == PCI_CLASS_BRIDGE_HOST)
1646 return pci_cfg_space_size_ext(dev);
1647
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001648 if (pci_is_pcie(dev))
1649 return pci_cfg_space_size_ext(dev);
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001650
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001651 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1652 if (!pos)
1653 return PCI_CFG_SPACE_SIZE;
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001654
Bjorn Helgaas8e5a3952015-12-07 18:21:10 -06001655 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1656 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1657 return pci_cfg_space_size_ext(dev);
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001658
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001659 return PCI_CFG_SPACE_SIZE;
1660}
1661
KarimAllah Ahmedcf0921b2018-03-19 21:06:00 +01001662static u32 pci_class(struct pci_dev *dev)
1663{
1664 u32 class;
1665
1666#ifdef CONFIG_PCI_IOV
1667 if (dev->is_virtfn)
1668 return dev->physfn->sriov->class;
1669#endif
1670 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1671 return class;
1672}
1673
1674static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1675{
1676#ifdef CONFIG_PCI_IOV
1677 if (dev->is_virtfn) {
1678 *vendor = dev->physfn->sriov->subsystem_vendor;
1679 *device = dev->physfn->sriov->subsystem_device;
1680 return;
1681 }
1682#endif
1683 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1684 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1685}
1686
1687static u8 pci_hdr_type(struct pci_dev *dev)
1688{
1689 u8 hdr_type;
1690
1691#ifdef CONFIG_PCI_IOV
1692 if (dev->is_virtfn)
1693 return dev->physfn->sriov->hdr_type;
1694#endif
1695 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1696 return hdr_type;
1697}
1698
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +02001699#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -08001700
Guilherme G. Piccolie80e7edc2015-10-21 12:17:35 -02001701static void pci_msi_setup_pci_dev(struct pci_dev *dev)
Michael S. Tsirkin18516172015-05-07 09:52:21 -05001702{
1703 /*
1704 * Disable the MSI hardware to avoid screaming interrupts
1705 * during boot. This is the power on reset default so
1706 * usually this should be a noop.
1707 */
1708 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1709 if (dev->msi_cap)
1710 pci_msi_set_enable(dev, 0);
1711
1712 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1713 if (dev->msix_cap)
1714 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1715}
1716
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001718 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
Piotr Gregor99b3c582017-05-26 22:02:25 +01001719 * @dev: PCI device
1720 *
1721 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1722 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1723 */
1724static int pci_intx_mask_broken(struct pci_dev *dev)
1725{
1726 u16 orig, toggle, new;
1727
1728 pci_read_config_word(dev, PCI_COMMAND, &orig);
1729 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1730 pci_write_config_word(dev, PCI_COMMAND, toggle);
1731 pci_read_config_word(dev, PCI_COMMAND, &new);
1732
1733 pci_write_config_word(dev, PCI_COMMAND, orig);
1734
1735 /*
1736 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1737 * r2.3, so strictly speaking, a device is not *broken* if it's not
1738 * writable. But we'll live with the misnomer for now.
1739 */
1740 if (new != toggle)
1741 return 1;
1742 return 0;
1743}
1744
Sinan Kaya11eb0e02018-06-04 22:16:09 -04001745static void early_dump_pci_device(struct pci_dev *pdev)
1746{
1747 u32 value[256 / 4];
1748 int i;
1749
1750 pci_info(pdev, "config space:\n");
1751
1752 for (i = 0; i < 256; i += 4)
1753 pci_read_config_dword(pdev, i, &value[i / 4]);
1754
1755 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1756 value, 256, false);
1757}
1758
Piotr Gregor99b3c582017-05-26 22:02:25 +01001759/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001760 * pci_setup_device - Fill in class and map information of a device
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761 * @dev: the device structure to fill
1762 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001763 * Initialize the device structure with information about the device's
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001764 * vendor,class,memory and IO-space addresses, IRQ lines etc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +08001766 * Returns 0 on success and negative if unknown type of device (not normal,
1767 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001769int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770{
1771 u32 class;
Bjorn Helgaasb84106b2016-02-25 14:35:57 -06001772 u16 cmd;
Yu Zhao480b93b2009-03-20 11:25:14 +08001773 u8 hdr_type;
Gabe Blackbc577d22009-10-06 10:45:19 -05001774 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001775 struct pci_bus_region region;
1776 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +08001777
KarimAllah Ahmedcf0921b2018-03-19 21:06:00 +01001778 hdr_type = pci_hdr_type(dev);
Yu Zhao480b93b2009-03-20 11:25:14 +08001779
1780 dev->sysdata = dev->bus->sysdata;
1781 dev->dev.parent = dev->bus->bridge;
1782 dev->dev.bus = &pci_bus_type;
1783 dev->hdr_type = hdr_type & 0x7f;
1784 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +08001785 dev->error_state = pci_channel_io_normal;
1786 set_pcie_port_type(dev);
1787
Yijing Wang017ffe62015-07-17 17:16:32 +08001788 pci_dev_assign_slot(dev);
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001789
1790 /*
1791 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1792 * set this higher, assuming the system even supports it.
1793 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001794 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -07001796 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1797 dev->bus->number, PCI_SLOT(dev->devfn),
1798 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001799
KarimAllah Ahmedcf0921b2018-03-19 21:06:00 +01001800 class = pci_class(dev);
1801
Auke Kokb8a3a522007-06-08 15:46:30 -07001802 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001803 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001804
Mohan Kumar34c6b712019-04-20 07:07:20 +03001805 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001806 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001807
Sinan Kaya11eb0e02018-06-04 22:16:09 -04001808 if (pci_early_dump)
1809 early_dump_pci_device(dev);
1810
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001811 /* Need to have dev->class ready */
Yu Zhao853346e2009-03-21 22:05:11 +08001812 dev->cfg_size = pci_cfg_space_size(dev);
1813
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001814 /* Need to have dev->cfg_size ready */
Lukas Wunner8531e282017-03-10 21:23:45 +01001815 set_pcie_thunderbolt(dev);
1816
Mika Westerberg617654a2018-08-16 12:28:48 +03001817 set_pcie_untrusted(dev);
1818
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001820 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821
1822 /* Early fixups, before probing the BARs */
1823 pci_fixup_device(pci_fixup_early, dev);
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001824
1825 /* Device class may be changed after fixup */
Yu Zhaof79b1b12009-05-28 00:25:05 +08001826 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827
Jiaxun Yangb6caa1d2020-05-26 17:21:12 +08001828 if (dev->non_compliant_bars && !dev->mmio_always_on) {
Bjorn Helgaasb84106b2016-02-25 14:35:57 -06001829 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1830 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06001831 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
Bjorn Helgaasb84106b2016-02-25 14:35:57 -06001832 cmd &= ~PCI_COMMAND_IO;
1833 cmd &= ~PCI_COMMAND_MEMORY;
1834 pci_write_config_word(dev, PCI_COMMAND, cmd);
1835 }
1836 }
1837
Piotr Gregor99b3c582017-05-26 22:02:25 +01001838 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1839
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 switch (dev->hdr_type) { /* header type */
1841 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1842 if (class == PCI_CLASS_BRIDGE_PCI)
1843 goto bad;
1844 pci_read_irq(dev);
1845 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
KarimAllah Ahmedcf0921b2018-03-19 21:06:00 +01001846
1847 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001848
1849 /*
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001850 * Do the ugly legacy mode stuff here rather than broken chip
1851 * quirk code. Legacy mode ATA controllers have fixed
1852 * addresses. These are not always echoed in BAR0-3, and
1853 * BAR0-3 in a few cases contain junk!
Alan Cox368c73d2006-10-04 00:41:26 +01001854 */
1855 if (class == PCI_CLASS_STORAGE_IDE) {
1856 u8 progif;
1857 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1858 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001859 region.start = 0x1F0;
1860 region.end = 0x1F7;
1861 res = &dev->resource[0];
1862 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001863 pcibios_bus_to_resource(dev->bus, res, &region);
Frederick Lawler7506dc72018-01-18 12:55:24 -06001864 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001865 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001866 region.start = 0x3F6;
1867 region.end = 0x3F6;
1868 res = &dev->resource[1];
1869 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001870 pcibios_bus_to_resource(dev->bus, res, &region);
Frederick Lawler7506dc72018-01-18 12:55:24 -06001871 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001872 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001873 }
1874 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001875 region.start = 0x170;
1876 region.end = 0x177;
1877 res = &dev->resource[2];
1878 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001879 pcibios_bus_to_resource(dev->bus, res, &region);
Frederick Lawler7506dc72018-01-18 12:55:24 -06001880 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001881 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001882 region.start = 0x376;
1883 region.end = 0x376;
1884 res = &dev->resource[3];
1885 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001886 pcibios_bus_to_resource(dev->bus, res, &region);
Frederick Lawler7506dc72018-01-18 12:55:24 -06001887 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001888 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001889 }
1890 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 break;
1892
1893 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06001894 /*
1895 * The PCI-to-PCI bridge spec requires that subtractive
1896 * decoding (i.e. transparent) bridge must have programming
1897 * interface code of 0x01.
1898 */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001899 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900 dev->transparent = ((dev->class & 0xff) == 1);
1901 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Bjorn Helgaas51c48b32019-01-19 11:35:04 -06001902 pci_read_bridge_windows(dev);
Eric W. Biederman28760482009-09-09 14:09:24 -07001903 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001904 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1905 if (pos) {
1906 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1907 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1908 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909 break;
1910
1911 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1912 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1913 goto bad;
1914 pci_read_irq(dev);
1915 pci_read_bases(dev, 1, 0);
1916 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1917 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1918 break;
1919
1920 default: /* unknown header */
Frederick Lawler7506dc72018-01-18 12:55:24 -06001921 pci_err(dev, "unknown header type %02x, ignoring device\n",
Ryan Desfosses227f0642014-04-18 20:13:50 -04001922 dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001923 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924
1925 bad:
Frederick Lawler7506dc72018-01-18 12:55:24 -06001926 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
Ryan Desfosses227f0642014-04-18 20:13:50 -04001927 dev->class, dev->hdr_type);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05001928 dev->class = PCI_CLASS_NOT_DEFINED << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 }
1930
1931 /* We found a fine healthy device, go go go... */
1932 return 0;
1933}
1934
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001935static void pci_configure_mps(struct pci_dev *dev)
1936{
1937 struct pci_dev *bridge = pci_upstream_bridge(dev);
Myron Stowe9f0e8932018-08-13 12:19:46 -06001938 int mps, mpss, p_mps, rc;
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001939
Ashok Rajaa0ce962020-03-27 14:16:15 -07001940 if (!pci_is_pcie(dev))
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001941 return;
1942
Myron Stowe3dbe97e2018-08-13 12:19:39 -06001943 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1944 if (dev->is_virtfn)
1945 return;
1946
Ashok Rajaa0ce962020-03-27 14:16:15 -07001947 /*
1948 * For Root Complex Integrated Endpoints, program the maximum
1949 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1950 */
1951 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1952 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1953 mps = 128;
1954 else
1955 mps = 128 << dev->pcie_mpss;
1956 rc = pcie_set_mps(dev, mps);
1957 if (rc) {
1958 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1959 mps);
1960 }
1961 return;
1962 }
1963
1964 if (!bridge || !pci_is_pcie(bridge))
1965 return;
1966
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001967 mps = pcie_get_mps(dev);
1968 p_mps = pcie_get_mps(bridge);
1969
1970 if (mps == p_mps)
1971 return;
1972
1973 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06001974 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05001975 mps, pci_name(bridge), p_mps);
1976 return;
1977 }
Keith Busch27d868b2015-08-24 08:48:16 -05001978
1979 /*
1980 * Fancier MPS configuration is done later by
1981 * pcie_bus_configure_settings()
1982 */
1983 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1984 return;
1985
Myron Stowe9f0e8932018-08-13 12:19:46 -06001986 mpss = 128 << dev->pcie_mpss;
1987 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1988 pcie_set_mps(bridge, mpss);
1989 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1990 mpss, p_mps, 128 << bridge->pcie_mpss);
1991 p_mps = pcie_get_mps(bridge);
1992 }
1993
Keith Busch27d868b2015-08-24 08:48:16 -05001994 rc = pcie_set_mps(dev, p_mps);
1995 if (rc) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06001996 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
Keith Busch27d868b2015-08-24 08:48:16 -05001997 p_mps);
1998 return;
1999 }
2000
Frederick Lawler7506dc72018-01-18 12:55:24 -06002001 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
Myron Stowe9f0e8932018-08-13 12:19:46 -06002002 p_mps, mps, mpss);
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05002003}
2004
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002005int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
Sinan Kaya60db3a42017-01-20 09:16:51 -05002006{
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002007 struct pci_host_bridge *host;
2008 u32 cap;
2009 u16 ctl;
Sinan Kaya60db3a42017-01-20 09:16:51 -05002010 int ret;
2011
2012 if (!pci_is_pcie(dev))
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002013 return 0;
Sinan Kaya60db3a42017-01-20 09:16:51 -05002014
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002015 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
Sinan Kaya60db3a42017-01-20 09:16:51 -05002016 if (ret)
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002017 return 0;
Sinan Kaya60db3a42017-01-20 09:16:51 -05002018
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002019 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2020 return 0;
2021
2022 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2023 if (ret)
2024 return 0;
2025
2026 host = pci_find_host_bridge(dev->bus);
2027 if (!host)
2028 return 0;
2029
2030 /*
2031 * If some device in the hierarchy doesn't handle Extended Tags
2032 * correctly, make sure they're disabled.
2033 */
2034 if (host->no_ext_tags) {
2035 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06002036 pci_info(dev, "disabling Extended Tags\n");
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002037 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2038 PCI_EXP_DEVCTL_EXT_TAG);
2039 }
2040 return 0;
2041 }
2042
2043 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06002044 pci_info(dev, "enabling Extended Tags\n");
Sinan Kaya60db3a42017-01-20 09:16:51 -05002045 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2046 PCI_EXP_DEVCTL_EXT_TAG);
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002047 }
2048 return 0;
Sinan Kaya60db3a42017-01-20 09:16:51 -05002049}
2050
dingtianhonga99b6462017-08-15 11:23:23 +08002051/**
2052 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2053 * @dev: PCI device to query
2054 *
2055 * Returns true if the device has enabled relaxed ordering attribute.
2056 */
2057bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2058{
2059 u16 v;
2060
2061 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2062
2063 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2064}
2065EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2066
2067static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2068{
2069 struct pci_dev *root;
2070
2071 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2072 if (dev->is_virtfn)
2073 return;
2074
2075 if (!pcie_relaxed_ordering_enabled(dev))
2076 return;
2077
2078 /*
2079 * For now, we only deal with Relaxed Ordering issues with Root
2080 * Ports. Peer-to-Peer DMA is another can of worms.
2081 */
Yicong Yang6ae72bf2020-05-09 18:19:28 +08002082 root = pcie_find_root_port(dev);
dingtianhonga99b6462017-08-15 11:23:23 +08002083 if (!root)
2084 return;
2085
2086 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2087 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2088 PCI_EXP_DEVCTL_RELAX_EN);
Frederick Lawler7506dc72018-01-18 12:55:24 -06002089 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
dingtianhonga99b6462017-08-15 11:23:23 +08002090 }
2091}
2092
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002093static void pci_configure_ltr(struct pci_dev *dev)
2094{
2095#ifdef CONFIG_PCIEASPM
Bjorn Helgaasaf8bb9f2018-04-17 10:58:09 -05002096 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002097 struct pci_dev *bridge;
Bjorn Helgaas10ecc812019-01-04 17:59:07 -06002098 u32 cap, ctl;
Bjorn Helgaasaf8bb9f2018-04-17 10:58:09 -05002099
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002100 if (!pci_is_pcie(dev))
2101 return;
2102
2103 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2104 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2105 return;
2106
Bjorn Helgaas10ecc812019-01-04 17:59:07 -06002107 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2108 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2109 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2110 dev->ltr_path = 1;
2111 return;
2112 }
2113
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002114 bridge = pci_upstream_bridge(dev);
2115 if (bridge && bridge->ltr_path)
2116 dev->ltr_path = 1;
Bjorn Helgaas10ecc812019-01-04 17:59:07 -06002117
2118 return;
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002119 }
2120
Bjorn Helgaas10ecc812019-01-04 17:59:07 -06002121 if (!host->native_ltr)
2122 return;
2123
2124 /*
2125 * Software must not enable LTR in an Endpoint unless the Root
2126 * Complex and all intermediate Switches indicate support for LTR.
2127 * PCIe r4.0, sec 6.18.
2128 */
2129 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2130 ((bridge = pci_upstream_bridge(dev)) &&
2131 bridge->ltr_path)) {
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002132 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2133 PCI_EXP_DEVCTL2_LTR_EN);
Bjorn Helgaas10ecc812019-01-04 17:59:07 -06002134 dev->ltr_path = 1;
2135 }
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002136#endif
2137}
2138
Sinan Kaya7ce3f912018-06-30 11:24:24 -04002139static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2140{
2141#ifdef CONFIG_PCI_PASID
2142 struct pci_dev *bridge;
Felix Kuehling9d27e39d2018-09-10 15:27:42 -04002143 int pcie_type;
Sinan Kaya7ce3f912018-06-30 11:24:24 -04002144 u32 cap;
2145
2146 if (!pci_is_pcie(dev))
2147 return;
2148
2149 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2150 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2151 return;
2152
Felix Kuehling9d27e39d2018-09-10 15:27:42 -04002153 pcie_type = pci_pcie_type(dev);
2154 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2155 pcie_type == PCI_EXP_TYPE_RC_END)
Sinan Kaya7ce3f912018-06-30 11:24:24 -04002156 dev->eetlp_prefix_path = 1;
2157 else {
2158 bridge = pci_upstream_bridge(dev);
2159 if (bridge && bridge->eetlp_prefix_path)
2160 dev->eetlp_prefix_path = 1;
2161 }
2162#endif
2163}
2164
Bharat Kumar Gogadab4f6dcb2018-11-14 20:17:01 +05302165static void pci_configure_serr(struct pci_dev *dev)
2166{
2167 u16 control;
2168
2169 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2170
2171 /*
2172 * A bridge will not forward ERR_ messages coming from an
2173 * endpoint unless SERR# forwarding is enabled.
2174 */
2175 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2176 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2177 control |= PCI_BRIDGE_CTL_SERR;
2178 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2179 }
2180 }
2181}
2182
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06002183static void pci_configure_device(struct pci_dev *dev)
2184{
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05002185 pci_configure_mps(dev);
Sinan Kaya62ce94a2017-07-12 00:04:14 -04002186 pci_configure_extended_tags(dev, NULL);
dingtianhonga99b6462017-08-15 11:23:23 +08002187 pci_configure_relaxed_ordering(dev);
Bjorn Helgaasc46fd352017-11-28 16:43:50 -06002188 pci_configure_ltr(dev);
Sinan Kaya7ce3f912018-06-30 11:24:24 -04002189 pci_configure_eetlp_prefix(dev);
Bharat Kumar Gogadab4f6dcb2018-11-14 20:17:01 +05302190 pci_configure_serr(dev);
Bjorn Helgaas9dae3a92015-08-20 16:08:27 -05002191
Krzysztof Wilczynski4a2dbed2019-08-27 11:49:51 +02002192 pci_acpi_program_hp_params(dev);
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06002193}
2194
Zhao, Yu201de562008-10-13 19:49:55 +08002195static void pci_release_capabilities(struct pci_dev *dev)
2196{
Rajat Jaindb89ccb2018-06-30 15:07:17 -05002197 pci_aer_exit(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08002198 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08002199 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08002200 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08002201}
2202
Linus Torvalds1da177e2005-04-16 15:20:36 -07002203/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002204 * pci_release_dev - Free a PCI device structure when all users of it are
2205 * finished
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 * @dev: device that's been disconnected
2207 *
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002208 * Will be called only by the device core when all users of this PCI device are
Linus Torvalds1da177e2005-04-16 15:20:36 -07002209 * done.
2210 */
2211static void pci_release_dev(struct device *dev)
2212{
Rafael J. Wysocki04480092014-02-01 15:38:29 +01002213 struct pci_dev *pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214
Rafael J. Wysocki04480092014-02-01 15:38:29 +01002215 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08002216 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10002217 pci_release_of_node(pci_dev);
Sebastian Ott6ae32c52013-06-04 19:18:14 +02002218 pcibios_release_device(pci_dev);
Gu Zheng8b1fce02013-05-25 21:48:31 +08002219 pci_bus_put(pci_dev->bus);
Alex Williamson782a9852014-05-20 08:53:21 -06002220 kfree(pci_dev->driver_override);
Andy Shevchenkoc6635792018-08-30 13:32:36 +03002221 bitmap_free(pci_dev->dma_alias_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002222 kfree(pci_dev);
2223}
2224
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08002225struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
Michael Ellerman65891212007-04-05 17:19:08 +10002226{
2227 struct pci_dev *dev;
2228
2229 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2230 if (!dev)
2231 return NULL;
2232
Michael Ellerman65891212007-04-05 17:19:08 +10002233 INIT_LIST_HEAD(&dev->bus_list);
Brian King88e7b162013-04-08 03:05:07 +00002234 dev->dev.type = &pci_dev_type;
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08002235 dev->bus = pci_bus_get(bus);
Michael Ellerman65891212007-04-05 17:19:08 +10002236
2237 return dev;
2238}
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08002239EXPORT_SYMBOL(pci_alloc_dev);
2240
Sinan Kaya62bc6a62017-08-29 14:45:44 -05002241static bool pci_bus_crs_vendor_id(u32 l)
2242{
2243 return (l & 0xffff) == 0x0001;
2244}
2245
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002246static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2247 int timeout)
Yinghai Luefdc87d2012-01-27 10:55:10 -08002248{
2249 int delay = 1;
2250
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002251 if (!pci_bus_crs_vendor_id(*l))
2252 return true; /* not a CRS completion */
Yinghai Luefdc87d2012-01-27 10:55:10 -08002253
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002254 if (!timeout)
2255 return false; /* CRS, but caller doesn't want to wait */
Yinghai Luefdc87d2012-01-27 10:55:10 -08002256
Rajat Jain89665a6a2014-09-08 14:19:49 -07002257 /*
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002258 * We got the reserved Vendor ID that indicates a completion with
2259 * Configuration Request Retry Status (CRS). Retry until we get a
2260 * valid Vendor ID or we time out.
Rajat Jain89665a6a2014-09-08 14:19:49 -07002261 */
Sinan Kaya62bc6a62017-08-29 14:45:44 -05002262 while (pci_bus_crs_vendor_id(*l)) {
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002263 if (delay > timeout) {
Sinan Kayae78e6612017-08-29 14:45:45 -05002264 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2265 pci_domain_nr(bus), bus->number,
2266 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2267
Yinghai Luefdc87d2012-01-27 10:55:10 -08002268 return false;
2269 }
Sinan Kayae78e6612017-08-29 14:45:45 -05002270 if (delay >= 1000)
2271 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2272 pci_domain_nr(bus), bus->number,
2273 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
Bjorn Helgaas9f982752017-08-29 14:45:43 -05002274
2275 msleep(delay);
2276 delay *= 2;
2277
2278 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2279 return false;
Yinghai Luefdc87d2012-01-27 10:55:10 -08002280 }
2281
Sinan Kayae78e6612017-08-29 14:45:45 -05002282 if (delay >= 1000)
2283 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2284 pci_domain_nr(bus), bus->number,
2285 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2286
Yinghai Luefdc87d2012-01-27 10:55:10 -08002287 return true;
2288}
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002289
James Puthukattukaranaa667c62018-07-09 11:31:25 -04002290bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2291 int timeout)
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002292{
Yinghai Luefdc87d2012-01-27 10:55:10 -08002293 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2294 return false;
2295
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002296 /* Some broken boards return 0 or ~0 if a slot is empty: */
Yinghai Luefdc87d2012-01-27 10:55:10 -08002297 if (*l == 0xffffffff || *l == 0x00000000 ||
2298 *l == 0x0000ffff || *l == 0xffff0000)
2299 return false;
2300
Sinan Kaya6a802ef2017-08-29 14:45:44 -05002301 if (pci_bus_crs_vendor_id(*l))
2302 return pci_bus_wait_crs(bus, devfn, l, timeout);
Yinghai Luefdc87d2012-01-27 10:55:10 -08002303
2304 return true;
2305}
James Puthukattukaranaa667c62018-07-09 11:31:25 -04002306
2307bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2308 int timeout)
2309{
2310#ifdef CONFIG_PCI_QUIRKS
2311 struct pci_dev *bridge = bus->self;
2312
2313 /*
2314 * Certain IDT switches have an issue where they improperly trigger
2315 * ACS Source Validation errors on completions for config reads.
2316 */
2317 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2318 bridge->device == 0x80b5)
2319 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2320#endif
2321
2322 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2323}
Yinghai Luefdc87d2012-01-27 10:55:10 -08002324EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2325
Linus Torvalds1da177e2005-04-16 15:20:36 -07002326/*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002327 * Read the config data for a PCI device, sanity-check it,
2328 * and fill in the dev structure.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07002330static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002331{
2332 struct pci_dev *dev;
2333 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002334
Yinghai Luefdc87d2012-01-27 10:55:10 -08002335 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002336 return NULL;
2337
Gu Zheng8b1fce02013-05-25 21:48:31 +08002338 dev = pci_alloc_dev(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002339 if (!dev)
2340 return NULL;
2341
Linus Torvalds1da177e2005-04-16 15:20:36 -07002342 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002343 dev->vendor = l & 0xffff;
2344 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002345
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10002346 pci_set_of_node(dev);
2347
Yu Zhao480b93b2009-03-20 11:25:14 +08002348 if (pci_setup_device(dev)) {
Gu Zheng8b1fce02013-05-25 21:48:31 +08002349 pci_bus_put(dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002350 kfree(dev);
2351 return NULL;
2352 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002353
2354 return dev;
2355}
2356
Lukas Wunner0fa635a2019-03-20 12:05:30 +01002357void pcie_report_downtraining(struct pci_dev *dev)
Alexandru Gagniuc2d1ce5e2018-08-06 18:25:35 -05002358{
2359 if (!pci_is_pcie(dev))
2360 return;
2361
2362 /* Look from the device up to avoid downstream ports with no devices */
2363 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2364 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2365 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2366 return;
2367
2368 /* Multi-function PCIe devices share the same link/status */
2369 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2370 return;
2371
2372 /* Print link status only if the device is constrained by the fabric */
2373 __pcie_print_link_status(dev, false);
2374}
2375
Zhao, Yu201de562008-10-13 19:49:55 +08002376static void pci_init_capabilities(struct pci_dev *dev)
2377{
Bjorn Helgaas9d8b7382019-10-03 16:28:26 -05002378 pci_ea_init(dev); /* Enhanced Allocation */
Sean O. Stalley938174e2015-10-29 17:35:39 -05002379
Guilherme G. Piccolie80e7edc2015-10-21 12:17:35 -02002380 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2381 pci_msi_setup_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08002382
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002383 /* Buffers for saving PCIe and PCI-X capabilities */
2384 pci_allocate_cap_save_buffers(dev);
2385
Bjorn Helgaas9d8b7382019-10-03 16:28:26 -05002386 pci_pm_init(dev); /* Power Management */
2387 pci_vpd_init(dev); /* Vital Product Data */
2388 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2389 pci_iov_init(dev); /* Single Root I/O Virtualization */
2390 pci_ats_init(dev); /* Address Translation Services */
Bjorn Helgaas7e124c42019-11-28 08:54:55 -06002391 pci_pri_init(dev); /* Page Request Interface */
2392 pci_pasid_init(dev); /* Process Address Space ID */
Rajat Jain52fbf5b2020-07-07 15:46:02 -07002393 pci_acs_init(dev); /* Access Control Services */
Bjorn Helgaas9d8b7382019-10-03 16:28:26 -05002394 pci_ptm_init(dev); /* Precision Time Measurement */
2395 pci_aer_init(dev); /* Advanced Error Reporting */
Kuppuswamy Sathyanarayanan27005612020-03-23 17:26:04 -07002396 pci_dpc_init(dev); /* Downstream Port Containment */
Bjorn Helgaas5b0764c2018-02-16 10:55:38 -06002397
Alexandru Gagniuc2d1ce5e2018-08-06 18:25:35 -05002398 pcie_report_downtraining(dev);
2399
Bjorn Helgaas5b0764c2018-02-16 10:55:38 -06002400 if (pci_probe_reset_function(dev) == 0)
2401 dev->reset_fn = 1;
Zhao, Yu201de562008-10-13 19:49:55 +08002402}
2403
Marc Zyngier098259e2015-10-02 10:19:32 +01002404/*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002405 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
Marc Zyngier098259e2015-10-02 10:19:32 +01002406 * devices. Firmware interfaces that can select the MSI domain on a
2407 * per-device basis should be called from here.
2408 */
2409static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2410{
2411 struct irq_domain *d;
2412
2413 /*
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002414 * If a domain has been set through the pcibios_add_device()
Marc Zyngier098259e2015-10-02 10:19:32 +01002415 * callback, then this is the one (platform code knows best).
2416 */
2417 d = dev_get_msi_domain(&dev->dev);
2418 if (d)
2419 return d;
2420
Marc Zyngier54fa97e2015-10-02 14:43:06 +01002421 /*
2422 * Let's see if we have a firmware interface able to provide
2423 * the domain.
2424 */
2425 d = pci_msi_get_device_domain(dev);
2426 if (d)
2427 return d;
2428
Marc Zyngier098259e2015-10-02 10:19:32 +01002429 return NULL;
2430}
2431
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002432static void pci_set_msi_domain(struct pci_dev *dev)
2433{
Marc Zyngier098259e2015-10-02 10:19:32 +01002434 struct irq_domain *d;
2435
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002436 /*
Marc Zyngier098259e2015-10-02 10:19:32 +01002437 * If the platform or firmware interfaces cannot supply a
2438 * device-specific MSI domain, then inherit the default domain
2439 * from the host bridge itself.
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002440 */
Marc Zyngier098259e2015-10-02 10:19:32 +01002441 d = pci_dev_msi_domain(dev);
2442 if (!d)
2443 d = dev_get_msi_domain(&dev->bus->dev);
2444
2445 dev_set_msi_domain(&dev->dev, d);
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002446}
2447
Sam Ravnborg96bde062007-03-26 21:53:30 -08002448void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002449{
Yinghai Lu4f535092013-01-21 13:20:52 -08002450 int ret;
2451
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06002452 pci_configure_device(dev);
2453
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 device_initialize(&dev->dev);
2455 dev->dev.release = pci_release_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456
Yinghai Lu7629d192013-01-21 13:20:44 -08002457 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002458 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002459 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002460 dev->dev.coherent_dma_mask = 0xffffffffull;
2461
Christoph Hellwigb0da3492018-10-09 16:08:24 +02002462 dma_set_max_seg_size(&dev->dev, 65536);
Christoph Hellwiga6f44cf2018-10-09 16:08:23 +02002463 dma_set_seg_boundary(&dev->dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002464
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465 /* Fix up broken headers */
2466 pci_fixup_device(pci_fixup_header, dev);
2467
Yinghai Lu2069ecf2012-02-15 21:40:31 -08002468 pci_reassigndev_resource_alignment(dev);
2469
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02002470 dev->state_saved = false;
2471
Zhao, Yu201de562008-10-13 19:49:55 +08002472 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002473
Linus Torvalds1da177e2005-04-16 15:20:36 -07002474 /*
2475 * Add the device to our list of discovered devices
2476 * and the bus list for fixup functions, etc.
2477 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08002478 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002479 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08002480 up_write(&pci_bus_sem);
Yinghai Lu4f535092013-01-21 13:20:52 -08002481
Yinghai Lu4f535092013-01-21 13:20:52 -08002482 ret = pcibios_add_device(dev);
2483 WARN_ON(ret < 0);
2484
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002485 /* Set up MSI IRQ domain */
Marc Zyngier44aa0c62015-07-28 14:46:11 +01002486 pci_set_msi_domain(dev);
2487
Yinghai Lu4f535092013-01-21 13:20:52 -08002488 /* Notifier could use PCI capabilities */
2489 dev->match_driver = false;
2490 ret = device_add(&dev->dev);
2491 WARN_ON(ret < 0);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002492}
2493
Bjorn Helgaas10874f5a2014-04-14 16:11:40 -06002494struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002495{
2496 struct pci_dev *dev;
2497
Trent Piepho90bdb312009-03-20 14:56:00 -06002498 dev = pci_get_slot(bus, devfn);
2499 if (dev) {
2500 pci_dev_put(dev);
2501 return dev;
2502 }
2503
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002504 dev = pci_scan_device(bus, devfn);
2505 if (!dev)
2506 return NULL;
2507
2508 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002509
2510 return dev;
2511}
Adrian Bunkb73e9682007-11-21 15:07:11 -08002512EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002513
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002514static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002515{
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002516 int pos;
2517 u16 cap = 0;
2518 unsigned next_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07002519
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002520 if (pci_ari_enabled(bus)) {
2521 if (!dev)
2522 return 0;
2523 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2524 if (!pos)
2525 return 0;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07002526
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002527 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2528 next_fn = PCI_ARI_CAP_NFN(cap);
2529 if (next_fn <= fn)
2530 return 0; /* protect against malformed list */
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002531
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002532 return next_fn;
2533 }
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002534
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002535 /* dev may be NULL for non-contiguous multifunction devices */
2536 if (!dev || dev->multifunction)
2537 return (fn + 1) % 8;
2538
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002539 return 0;
2540}
2541
2542static int only_one_child(struct pci_bus *bus)
2543{
Bjorn Helgaasd57f0b82017-11-30 15:22:39 -06002544 struct pci_dev *bridge = bus->self;
Bjorn Helgaas5bbe0292016-02-05 14:57:47 -06002545
2546 /*
Bjorn Helgaasd57f0b82017-11-30 15:22:39 -06002547 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2548 * we scan for all possible devices, not just Device 0.
Bjorn Helgaas5bbe0292016-02-05 14:57:47 -06002549 */
Bjorn Helgaasd57f0b82017-11-30 15:22:39 -06002550 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2551 return 0;
2552
2553 /*
2554 * A PCIe Downstream Port normally leads to a Link with only Device
2555 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2556 * only for Device 0 in that situation.
Bjorn Helgaasd57f0b82017-11-30 15:22:39 -06002557 */
Mika Westerbergca784102019-08-22 11:55:53 +03002558 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002559 return 1;
Bjorn Helgaasd57f0b82017-11-30 15:22:39 -06002560
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002561 return 0;
2562}
2563
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002565 * pci_scan_slot - Scan a PCI slot on a bus for devices
Linus Torvalds1da177e2005-04-16 15:20:36 -07002566 * @bus: PCI bus to scan
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002567 * @devfn: slot number to scan (must have zero function)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002568 *
2569 * Scan a PCI slot on the specified PCI bus for devices, adding
2570 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08002571 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002572 *
2573 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002574 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08002575int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002576{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002577 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002578 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002579
2580 if (only_one_child(bus) && (devfn > 0))
2581 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002582
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002583 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07002584 if (!dev)
2585 return 0;
Hari Vyas44bda4b2018-07-03 14:35:41 +05302586 if (!pci_dev_is_added(dev))
Trent Piepho1b69dfc2009-03-20 14:56:05 -06002587 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588
Yijing Wangb1bd58e2013-01-25 09:12:31 -07002589 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002590 dev = pci_scan_single_device(bus, devfn + fn);
2591 if (dev) {
Hari Vyas44bda4b2018-07-03 14:35:41 +05302592 if (!pci_dev_is_added(dev))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05002593 nr++;
2594 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002595 }
2596 }
Shaohua Li7d715a62008-02-25 09:46:41 +08002597
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002598 /* Only one slot has PCIe device */
Shaohua Li149e1632008-07-23 10:32:31 +08002599 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08002600 pcie_aspm_init_link_state(bus->self);
2601
Linus Torvalds1da177e2005-04-16 15:20:36 -07002602 return nr;
2603}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002604EXPORT_SYMBOL(pci_scan_slot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002605
Jon Masonb03e7492011-07-20 15:20:54 -05002606static int pcie_find_smpss(struct pci_dev *dev, void *data)
2607{
2608 u8 *smpss = data;
2609
2610 if (!pci_is_pcie(dev))
2611 return 0;
2612
Yijing Wangd4aa68f2013-08-22 11:24:47 +08002613 /*
2614 * We don't have a way to change MPS settings on devices that have
2615 * drivers attached. A hot-added device might support only the minimum
2616 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2617 * where devices may be hot-added, we limit the fabric MPS to 128 so
2618 * hot-added devices will work correctly.
2619 *
2620 * However, if we hot-add a device to a slot directly below a Root
2621 * Port, it's impossible for there to be other existing devices below
2622 * the port. We don't limit the MPS in this case because we can
2623 * reconfigure MPS on both the Root Port and the hot-added device,
2624 * and there are no other devices involved.
2625 *
2626 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
Jon Masonb03e7492011-07-20 15:20:54 -05002627 */
Yijing Wangd4aa68f2013-08-22 11:24:47 +08002628 if (dev->is_hotplug_bridge &&
2629 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
Jon Masonb03e7492011-07-20 15:20:54 -05002630 *smpss = 0;
2631
2632 if (*smpss > dev->pcie_mpss)
2633 *smpss = dev->pcie_mpss;
2634
2635 return 0;
2636}
2637
2638static void pcie_write_mps(struct pci_dev *dev, int mps)
2639{
Jon Mason62f392e2011-10-14 14:56:14 -05002640 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05002641
2642 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05002643 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05002644
Yijing Wang62f87c02012-07-24 17:20:03 +08002645 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2646 dev->bus->self)
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002647
2648 /*
2649 * For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05002650 * downstream communication will never be larger than
2651 * the MRRS. So, the MPS only needs to be configured
2652 * for the upstream communication. This being the case,
2653 * walk from the top down and set the MPS of the child
2654 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05002655 *
2656 * Configure the device MPS with the smaller of the
2657 * device MPSS or the bridge MPS (which is assumed to be
2658 * properly configured at this point to the largest
2659 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05002660 */
Jon Mason62f392e2011-10-14 14:56:14 -05002661 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05002662 }
2663
2664 rc = pcie_set_mps(dev, mps);
2665 if (rc)
Frederick Lawler7506dc72018-01-18 12:55:24 -06002666 pci_err(dev, "Failed attempting to set the MPS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05002667}
2668
Jon Mason62f392e2011-10-14 14:56:14 -05002669static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05002670{
Jon Mason62f392e2011-10-14 14:56:14 -05002671 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05002672
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002673 /*
2674 * In the "safe" case, do not configure the MRRS. There appear to be
Jon Masoned2888e2011-09-08 16:41:18 -05002675 * issues with setting MRRS to 0 on a number of devices.
2676 */
Jon Masoned2888e2011-09-08 16:41:18 -05002677 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2678 return;
Jon Masonb03e7492011-07-20 15:20:54 -05002679
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002680 /*
2681 * For max performance, the MRRS must be set to the largest supported
Jon Masoned2888e2011-09-08 16:41:18 -05002682 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05002683 * device or the bus can support. This should already be properly
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002684 * configured by a prior call to pcie_write_mps().
Jon Masoned2888e2011-09-08 16:41:18 -05002685 */
Jon Mason62f392e2011-10-14 14:56:14 -05002686 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002687
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002688 /*
2689 * MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05002690 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05002691 * If the MRRS value provided is not acceptable (e.g., too large),
2692 * shrink the value until it is acceptable to the HW.
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002693 */
Jon Masonb03e7492011-07-20 15:20:54 -05002694 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2695 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05002696 if (!rc)
2697 break;
Jon Masonb03e7492011-07-20 15:20:54 -05002698
Frederick Lawler7506dc72018-01-18 12:55:24 -06002699 pci_warn(dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05002700 mrrs /= 2;
2701 }
Jon Mason62f392e2011-10-14 14:56:14 -05002702
2703 if (mrrs < 128)
Frederick Lawler7506dc72018-01-18 12:55:24 -06002704 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
Jon Masonb03e7492011-07-20 15:20:54 -05002705}
2706
2707static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2708{
Jon Masona513a99a72011-10-14 14:56:16 -05002709 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05002710
2711 if (!pci_is_pcie(dev))
2712 return 0;
2713
Keith Busch27d868b2015-08-24 08:48:16 -05002714 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2715 pcie_bus_config == PCIE_BUS_DEFAULT)
Yijing Wang5895af72013-08-26 16:33:06 +08002716 return 0;
Yijing Wang5895af72013-08-26 16:33:06 +08002717
Jon Masona513a99a72011-10-14 14:56:16 -05002718 mps = 128 << *(u8 *)data;
2719 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002720
2721 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05002722 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05002723
Frederick Lawler7506dc72018-01-18 12:55:24 -06002724 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
Ryan Desfosses227f0642014-04-18 20:13:50 -04002725 pcie_get_mps(dev), 128 << dev->pcie_mpss,
Jon Masona513a99a72011-10-14 14:56:16 -05002726 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05002727
2728 return 0;
2729}
2730
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002731/*
2732 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05002733 * parents then children fashion. If this changes, then this code will not
2734 * work as designed.
2735 */
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002736void pcie_bus_configure_settings(struct pci_bus *bus)
Jon Masonb03e7492011-07-20 15:20:54 -05002737{
Bjorn Helgaas1e358f92014-04-29 12:51:55 -06002738 u8 smpss = 0;
Jon Masonb03e7492011-07-20 15:20:54 -05002739
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002740 if (!bus->self)
2741 return;
2742
Jon Masonb03e7492011-07-20 15:20:54 -05002743 if (!pci_is_pcie(bus->self))
2744 return;
2745
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002746 /*
2747 * FIXME - Peer to peer DMA is possible, though the endpoint would need
Jon Mason33154722013-08-26 16:33:05 +08002748 * to be aware of the MPS of the destination. To work around this,
Jon Mason5f39e672011-10-03 09:50:20 -05002749 * simply force the MPS of the entire system to the smallest possible.
2750 */
2751 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2752 smpss = 0;
2753
Jon Masonb03e7492011-07-20 15:20:54 -05002754 if (pcie_bus_config == PCIE_BUS_SAFE) {
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08002755 smpss = bus->self->pcie_mpss;
Jon Mason5f39e672011-10-03 09:50:20 -05002756
Jon Masonb03e7492011-07-20 15:20:54 -05002757 pcie_find_smpss(bus->self, &smpss);
2758 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2759 }
2760
2761 pcie_bus_configure_set(bus->self, &smpss);
2762 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2763}
Jon Masondebc3b72011-08-02 00:01:18 -05002764EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05002765
Palmer Dabbeltbccf90d2017-06-23 18:50:42 -07002766/*
2767 * Called after each bus is probed, but before its children are examined. This
2768 * is marked as __weak because multiple architectures define it.
2769 */
2770void __weak pcibios_fixup_bus(struct pci_bus *bus)
2771{
2772 /* nothing to do, expected to be removed in the future */
2773}
2774
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002775/**
2776 * pci_scan_child_bus_extend() - Scan devices below a bus
2777 * @bus: Bus to scan for devices
2778 * @available_buses: Total number of buses available (%0 does not try to
2779 * extend beyond the minimal)
2780 *
2781 * Scans devices below @bus including subordinate buses. Returns new
2782 * subordinate number including all the found devices. Passing
2783 * @available_buses causes the remaining bus space to be distributed
2784 * equally between hotplug-capable bridges to allow future extension of the
2785 * hierarchy.
2786 */
2787static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2788 unsigned int available_buses)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002789{
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002790 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2791 unsigned int start = bus->busn_res.start;
Jan Kiszka690f4302018-03-07 08:39:13 +01002792 unsigned int devfn, fn, cmax, max = start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002793 struct pci_dev *dev;
Jan Kiszka690f4302018-03-07 08:39:13 +01002794 int nr_devs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002795
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002796 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002797
2798 /* Go find them, Rover! */
Jan Kiszka690f4302018-03-07 08:39:13 +01002799 for (devfn = 0; devfn < 256; devfn += 8) {
2800 nr_devs = pci_scan_slot(bus, devfn);
2801
2802 /*
2803 * The Jailhouse hypervisor may pass individual functions of a
2804 * multi-function device to a guest without passing function 0.
2805 * Look for them as well.
2806 */
2807 if (jailhouse_paravirt() && nr_devs == 0) {
2808 for (fn = 1; fn < 8; fn++) {
2809 dev = pci_scan_single_device(bus, devfn + fn);
2810 if (dev)
2811 dev->multifunction = 1;
2812 }
2813 }
2814 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002816 /* Reserve buses for SR-IOV capability */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002817 used_buses = pci_iov_bus_range(bus);
2818 max += used_buses;
Yu Zhaoa28724b2009-03-20 11:25:13 +08002819
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820 /*
2821 * After performing arch-dependent fixup of the bus, look behind
2822 * all PCI-to-PCI bridges on this bus.
2823 */
Alex Chiang74710de2009-03-20 14:56:10 -06002824 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002825 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06002826 pcibios_fixup_bus(bus);
Jiang Liu981cf9e2013-04-12 05:44:16 +00002827 bus->is_added = 1;
Alex Chiang74710de2009-03-20 14:56:10 -06002828 }
2829
Mika Westerberg4147c2f2017-10-13 21:35:42 +03002830 /*
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002831 * Calculate how many hotplug bridges and normal bridges there
2832 * are on this bus. We will distribute the additional available
2833 * buses between hotplug bridges.
2834 */
2835 for_each_pci_bridge(dev, bus) {
2836 if (dev->is_hotplug_bridge)
2837 hotplug_bridges++;
2838 else
2839 normal_bridges++;
2840 }
2841
2842 /*
Mika Westerberg4147c2f2017-10-13 21:35:42 +03002843 * Scan bridges that are already configured. We don't touch them
2844 * unless they are misconfigured (which will be done in the second
2845 * scan below).
2846 */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002847 for_each_pci_bridge(dev, bus) {
2848 cmax = max;
2849 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
Mika Westerberg3374c542018-05-28 15:47:50 +03002850
2851 /*
2852 * Reserve one bus for each bridge now to avoid extending
2853 * hotplug bridges too much during the second scan below.
2854 */
2855 used_buses++;
2856 if (cmax - max > 1)
2857 used_buses += cmax - max - 1;
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002858 }
Mika Westerberg4147c2f2017-10-13 21:35:42 +03002859
2860 /* Scan bridges that need to be reconfigured */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002861 for_each_pci_bridge(dev, bus) {
2862 unsigned int buses = 0;
2863
2864 if (!hotplug_bridges && normal_bridges == 1) {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002865
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002866 /*
2867 * There is only one bridge on the bus (upstream
2868 * port) so it gets all available buses which it
2869 * can then distribute to the possible hotplug
2870 * bridges below.
2871 */
2872 buses = available_buses;
2873 } else if (dev->is_hotplug_bridge) {
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002874
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002875 /*
2876 * Distribute the extra buses between hotplug
2877 * bridges if any.
2878 */
2879 buses = available_buses / hotplug_bridges;
Mika Westerberg3374c542018-05-28 15:47:50 +03002880 buses = min(buses, available_buses - used_buses + 1);
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002881 }
2882
2883 cmax = max;
2884 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
Mika Westerberg3374c542018-05-28 15:47:50 +03002885 /* One bus is already accounted so don't add it again */
2886 if (max - cmax > 1)
2887 used_buses += max - cmax - 1;
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002888 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002889
2890 /*
Keith Busche16b4662016-07-21 21:40:28 -06002891 * Make sure a hotplug bridge has at least the minimum requested
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002892 * number of buses but allow it to grow up to the maximum available
2893 * bus number of there is room.
Keith Busche16b4662016-07-21 21:40:28 -06002894 */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002895 if (bus->self && bus->self->is_hotplug_bridge) {
2896 used_buses = max_t(unsigned int, available_buses,
2897 pci_hotplug_bus_size - 1);
2898 if (max - start < used_buses) {
2899 max = start + used_buses;
Mika Westerberga20c7f32017-10-13 21:35:43 +03002900
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002901 /* Do not allocate more buses than we have room left */
2902 if (max > bus->busn_res.end)
2903 max = bus->busn_res.end;
2904
2905 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2906 &bus->busn_res, max - start);
2907 }
Keith Busche16b4662016-07-21 21:40:28 -06002908 }
2909
2910 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002911 * We've scanned the bus and so we know all about what's on
2912 * the other side of any bridges that may be on this bus plus
2913 * any devices.
2914 *
2915 * Return how far we've got finding sub-buses.
2916 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07002917 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002918 return max;
2919}
Mika Westerberg1c02ea82017-10-13 21:35:44 +03002920
2921/**
2922 * pci_scan_child_bus() - Scan devices below a bus
2923 * @bus: Bus to scan for devices
2924 *
2925 * Scans devices below @bus including subordinate buses. Returns new
2926 * subordinate number including all the found devices.
2927 */
2928unsigned int pci_scan_child_bus(struct pci_bus *bus)
2929{
2930 return pci_scan_child_bus_extend(bus, 0);
2931}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002932EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002933
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002934/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06002935 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2936 * @bridge: Host bridge to set up
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002937 *
2938 * Default empty implementation. Replace with an architecture-specific setup
2939 * routine, if necessary.
2940 */
2941int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2942{
2943 return 0;
2944}
2945
Jiang Liu10a95742013-04-12 05:44:20 +00002946void __weak pcibios_add_bus(struct pci_bus *bus)
2947{
2948}
2949
2950void __weak pcibios_remove_bus(struct pci_bus *bus)
2951{
2952}
2953
Lorenzo Pieralisi9ee8a1c2017-06-28 15:14:01 -05002954struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2955 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002956{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07002957 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07002958 struct pci_host_bridge *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002959
Thierry Reding59094062016-11-25 11:57:10 +01002960 bridge = pci_alloc_host_bridge(0);
Yinghai Lu7b543662012-04-02 18:31:53 -07002961 if (!bridge)
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002962 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -07002963
2964 bridge->dev.parent = parent;
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002965
2966 list_splice_init(resources, &bridge->windows);
2967 bridge->sysdata = sysdata;
2968 bridge->busnr = bus;
2969 bridge->ops = ops;
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002970
2971 error = pci_register_host_bridge(bridge);
2972 if (error < 0)
Jiang Liu343df772013-06-07 01:10:08 +08002973 goto err_out;
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01002974
Arnd Bergmann37d6a0a2016-11-25 11:57:09 +01002975 return bridge->bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976
Yinghai Lu7b543662012-04-02 18:31:53 -07002977err_out:
Rob Herring98854402020-05-13 17:38:59 -05002978 put_device(&bridge->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002979 return NULL;
2980}
Ray Juie6b29de2015-04-08 11:21:33 -07002981EXPORT_SYMBOL_GPL(pci_create_root_bus);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002982
Cyrille Pitchen49b8e3f2018-01-30 21:56:52 +01002983int pci_host_probe(struct pci_host_bridge *bridge)
2984{
2985 struct pci_bus *bus, *child;
2986 int ret;
2987
2988 ret = pci_scan_root_bus_bridge(bridge);
2989 if (ret < 0) {
2990 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2991 return ret;
2992 }
2993
2994 bus = bridge->bus;
2995
2996 /*
2997 * We insert PCI resources into the iomem_resource and
2998 * ioport_resource trees in either pci_bus_claim_resources()
2999 * or pci_bus_assign_resources().
3000 */
3001 if (pci_has_flag(PCI_PROBE_ONLY)) {
3002 pci_bus_claim_resources(bus);
3003 } else {
3004 pci_bus_size_bridges(bus);
3005 pci_bus_assign_resources(bus);
3006
3007 list_for_each_entry(child, &bus->children, node)
3008 pcie_bus_configure_settings(child);
3009 }
3010
3011 pci_bus_add_devices(bus);
3012 return 0;
3013}
3014EXPORT_SYMBOL_GPL(pci_host_probe);
3015
Yinghai Lu98a35832012-05-18 11:35:50 -06003016int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3017{
3018 struct resource *res = &b->busn_res;
3019 struct resource *parent_res, *conflict;
3020
3021 res->start = bus;
3022 res->end = bus_max;
3023 res->flags = IORESOURCE_BUS;
3024
3025 if (!pci_is_root_bus(b))
3026 parent_res = &b->parent->busn_res;
3027 else {
3028 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3029 res->flags |= IORESOURCE_PCI_FIXED;
3030 }
3031
Andreas Noeverced04d12014-01-23 21:59:24 +01003032 conflict = request_resource_conflict(parent_res, res);
Yinghai Lu98a35832012-05-18 11:35:50 -06003033
3034 if (conflict)
Mohan Kumar34c6b712019-04-20 07:07:20 +03003035 dev_info(&b->dev,
Yinghai Lu98a35832012-05-18 11:35:50 -06003036 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3037 res, pci_is_root_bus(b) ? "domain " : "",
3038 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06003039
3040 return conflict == NULL;
3041}
3042
3043int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3044{
3045 struct resource *res = &b->busn_res;
3046 struct resource old_res = *res;
3047 resource_size_t size;
3048 int ret;
3049
3050 if (res->start > bus_max)
3051 return -EINVAL;
3052
3053 size = bus_max - res->start + 1;
3054 ret = adjust_resource(res, res->start, size);
Mohan Kumar34c6b712019-04-20 07:07:20 +03003055 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
Yinghai Lu98a35832012-05-18 11:35:50 -06003056 &old_res, ret ? "can not be" : "is", bus_max);
3057
3058 if (!ret && !res->parent)
3059 pci_bus_insert_busn_res(b, res->start, res->end);
3060
3061 return ret;
3062}
3063
3064void pci_bus_release_busn_res(struct pci_bus *b)
3065{
3066 struct resource *res = &b->busn_res;
3067 int ret;
3068
3069 if (!res->flags || !res->parent)
3070 return;
3071
3072 ret = release_resource(res);
Mohan Kumar34c6b712019-04-20 07:07:20 +03003073 dev_info(&b->dev, "busn_res: %pR %s released\n",
Yinghai Lu98a35832012-05-18 11:35:50 -06003074 res, ret ? "can not be" : "is");
3075}
3076
Lorenzo Pieralisi1228c4b2017-06-28 15:13:55 -05003077int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3078{
3079 struct resource_entry *window;
3080 bool found = false;
3081 struct pci_bus *b;
3082 int max, bus, ret;
3083
3084 if (!bridge)
3085 return -EINVAL;
3086
3087 resource_list_for_each_entry(window, &bridge->windows)
3088 if (window->res->flags & IORESOURCE_BUS) {
3089 found = true;
3090 break;
3091 }
3092
3093 ret = pci_register_host_bridge(bridge);
3094 if (ret < 0)
3095 return ret;
3096
3097 b = bridge->bus;
3098 bus = bridge->busnr;
3099
3100 if (!found) {
3101 dev_info(&b->dev,
3102 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3103 bus);
3104 pci_bus_insert_busn_res(b, bus, 255);
3105 }
3106
3107 max = pci_scan_child_bus(b);
3108
3109 if (!found)
3110 pci_bus_update_busn_res_end(b, max);
3111
3112 return 0;
3113}
3114EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3115
Lorenzo Pieralisi9ee8a1c2017-06-28 15:14:01 -05003116struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3117 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Bjorn Helgaasa2ebb8272011-10-28 16:25:50 -06003118{
Jiang Liu14d76b62015-02-05 13:44:44 +08003119 struct resource_entry *window;
Yinghai Lu4d99f522012-05-17 18:51:12 -07003120 bool found = false;
Bjorn Helgaasa2ebb8272011-10-28 16:25:50 -06003121 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07003122 int max;
3123
Jiang Liu14d76b62015-02-05 13:44:44 +08003124 resource_list_for_each_entry(window, resources)
Yinghai Lu4d99f522012-05-17 18:51:12 -07003125 if (window->res->flags & IORESOURCE_BUS) {
3126 found = true;
3127 break;
3128 }
Bjorn Helgaasa2ebb8272011-10-28 16:25:50 -06003129
Lorenzo Pieralisi9ee8a1c2017-06-28 15:14:01 -05003130 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
Bjorn Helgaasa2ebb8272011-10-28 16:25:50 -06003131 if (!b)
3132 return NULL;
3133
Yinghai Lu4d99f522012-05-17 18:51:12 -07003134 if (!found) {
3135 dev_info(&b->dev,
3136 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3137 bus);
3138 pci_bus_insert_busn_res(b, bus, 255);
3139 }
3140
3141 max = pci_scan_child_bus(b);
3142
3143 if (!found)
3144 pci_bus_update_busn_res_end(b, max);
3145
Bjorn Helgaasa2ebb8272011-10-28 16:25:50 -06003146 return b;
3147}
3148EXPORT_SYMBOL(pci_scan_root_bus);
3149
Bill Pemberton15856ad2012-11-21 15:35:00 -05003150struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06003151 void *sysdata)
3152{
3153 LIST_HEAD(resources);
3154 struct pci_bus *b;
3155
3156 pci_add_resource(&resources, &ioport_resource);
3157 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07003158 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06003159 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3160 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07003161 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06003162 } else {
3163 pci_free_resource_list(&resources);
3164 }
3165 return b;
3166}
3167EXPORT_SYMBOL(pci_scan_bus);
3168
Alex Chiang3ed4fd92009-03-20 14:56:25 -06003169/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06003170 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
Yinghai Lu2f320522012-01-21 02:08:22 -08003171 * @bridge: PCI bridge for the bus to scan
3172 *
3173 * Scan a PCI bus and child buses for new devices, add them,
3174 * and enable them, resizing bridge mmio/io resource if necessary
3175 * and possible. The caller must ensure the child devices are already
3176 * removed for resizing to occur.
3177 *
3178 * Returns the max number of subordinate bus discovered.
3179 */
Bjorn Helgaas10874f5a2014-04-14 16:11:40 -06003180unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
Yinghai Lu2f320522012-01-21 02:08:22 -08003181{
3182 unsigned int max;
3183 struct pci_bus *bus = bridge->subordinate;
3184
3185 max = pci_scan_child_bus(bus);
3186
3187 pci_assign_unassigned_bridge_resources(bridge);
3188
3189 pci_bus_add_devices(bus);
3190
3191 return max;
3192}
3193
Yinghai Lua5213a32012-10-30 14:31:21 -06003194/**
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06003195 * pci_rescan_bus - Scan a PCI bus for devices
Yinghai Lua5213a32012-10-30 14:31:21 -06003196 * @bus: PCI bus to scan
3197 *
Bjorn Helgaas3e466e22017-11-30 10:58:14 -06003198 * Scan a PCI bus and child buses for new devices, add them,
3199 * and enable them.
Yinghai Lua5213a32012-10-30 14:31:21 -06003200 *
3201 * Returns the max number of subordinate bus discovered.
3202 */
Bjorn Helgaas10874f5a2014-04-14 16:11:40 -06003203unsigned int pci_rescan_bus(struct pci_bus *bus)
Yinghai Lua5213a32012-10-30 14:31:21 -06003204{
3205 unsigned int max;
3206
3207 max = pci_scan_child_bus(bus);
3208 pci_assign_unassigned_bus_resources(bus);
3209 pci_bus_add_devices(bus);
3210
3211 return max;
3212}
3213EXPORT_SYMBOL_GPL(pci_rescan_bus);
3214
Rafael J. Wysocki9d169472014-01-10 15:22:18 +01003215/*
3216 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3217 * routines should always be executed under this mutex.
3218 */
3219static DEFINE_MUTEX(pci_rescan_remove_lock);
3220
3221void pci_lock_rescan_remove(void)
3222{
3223 mutex_lock(&pci_rescan_remove_lock);
3224}
3225EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3226
3227void pci_unlock_rescan_remove(void)
3228{
3229 mutex_unlock(&pci_rescan_remove_lock);
3230}
3231EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3232
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003233static int __init pci_sort_bf_cmp(const struct device *d_a,
3234 const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05003235{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05003236 const struct pci_dev *a = to_pci_dev(d_a);
3237 const struct pci_dev *b = to_pci_dev(d_b);
3238
Matt Domsch6b4b78f2006-09-29 15:23:23 -05003239 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3240 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3241
3242 if (a->bus->number < b->bus->number) return -1;
3243 else if (a->bus->number > b->bus->number) return 1;
3244
3245 if (a->devfn < b->devfn) return -1;
3246 else if (a->devfn > b->devfn) return 1;
3247
3248 return 0;
3249}
3250
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08003251void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05003252{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05003253 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05003254}
Mika Westerberg95e3ba92017-10-13 21:35:41 +03003255
3256int pci_hp_add_bridge(struct pci_dev *dev)
3257{
3258 struct pci_bus *parent = dev->bus;
Mika Westerberg4147c2f2017-10-13 21:35:42 +03003259 int busnr, start = parent->busn_res.start;
Mika Westerberg1c02ea82017-10-13 21:35:44 +03003260 unsigned int available_buses = 0;
Mika Westerberg95e3ba92017-10-13 21:35:41 +03003261 int end = parent->busn_res.end;
3262
3263 for (busnr = start; busnr <= end; busnr++) {
3264 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3265 break;
3266 }
3267 if (busnr-- > end) {
Frederick Lawler7506dc72018-01-18 12:55:24 -06003268 pci_err(dev, "No bus number available for hot-added bridge\n");
Mika Westerberg95e3ba92017-10-13 21:35:41 +03003269 return -1;
3270 }
Mika Westerberg4147c2f2017-10-13 21:35:42 +03003271
3272 /* Scan bridges that are already configured */
3273 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3274
Mika Westerberg1c02ea82017-10-13 21:35:44 +03003275 /*
3276 * Distribute the available bus numbers between hotplug-capable
3277 * bridges to make extending the chain later possible.
3278 */
3279 available_buses = end - busnr;
3280
Mika Westerberg4147c2f2017-10-13 21:35:42 +03003281 /* Scan bridges that need to be reconfigured */
Mika Westerberg1c02ea82017-10-13 21:35:44 +03003282 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
Mika Westerberg4147c2f2017-10-13 21:35:42 +03003283
Mika Westerberg95e3ba92017-10-13 21:35:41 +03003284 if (!dev->subordinate)
3285 return -1;
3286
3287 return 0;
3288}
3289EXPORT_SYMBOL_GPL(pci_hp_add_bridge);