blob: 067583ab1bd7f2e4b8cbe0fbab9fdd47ee0d8e85 [file] [log] [blame]
Thomas Gleixner50acfb22019-05-29 07:18:00 -07001// SPDX-License-Identifier: GPL-2.0-only
Palmer Dabbelt76d2a042017-07-10 18:00:26 -07002/*
3 * Copyright (C) 2012 Regents of the University of California
Anup Patel671f9a32019-06-28 13:36:21 -07004 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
Palmer Dabbelt76d2a042017-07-10 18:00:26 -07005 */
6
7#include <linux/init.h>
8#include <linux/mm.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -07009#include <linux/memblock.h>
Mike Rapoport57c8a662018-10-30 15:09:49 -070010#include <linux/initrd.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070011#include <linux/swap.h>
Christoph Hellwig5ec9c4f2018-01-16 09:37:50 +010012#include <linux/sizes.h>
Anup Patel0651c262019-02-21 11:25:49 +053013#include <linux/of_fdt.h>
Albert Ou922b0372019-09-27 16:14:18 -070014#include <linux/libfdt.h>
Zong Lid27c3c92020-03-10 00:55:41 +080015#include <linux/set_memory.h>
Kefeng Wangda815582020-10-31 14:01:12 +080016#include <linux/dma-map-ops.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070017
Anup Patelf2c17aa2019-01-07 20:57:01 +053018#include <asm/fixmap.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070019#include <asm/tlbflush.h>
20#include <asm/sections.h>
Palmer Dabbelt2d268252020-04-14 13:43:24 +090021#include <asm/soc.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070022#include <asm/io.h>
Zong Lib422d282020-06-03 16:03:55 -070023#include <asm/ptdump.h>
Atish Patra4f0e8ee2020-11-18 16:38:29 -080024#include <asm/numa.h>
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070025
Paul Walmsleyffaee272019-10-17 15:00:17 -070026#include "../kernel/head.h"
27
Anup Patel387181d2019-03-26 08:03:47 +000028unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
29 __page_aligned_bss;
30EXPORT_SYMBOL(empty_zero_page);
31
Anup Pateld90d45d2019-06-07 06:01:29 +000032extern char _start[];
Anup Patel8f3a2b42020-09-17 15:37:10 -070033#define DTB_EARLY_BASE_VA PGDIR_SIZE
34void *dtb_early_va __initdata;
35uintptr_t dtb_early_pa __initdata;
Anup Pateld90d45d2019-06-07 06:01:29 +000036
Atish Patrae8dcb612020-09-17 15:37:12 -070037struct pt_alloc_ops {
38 pte_t *(*get_pte_virt)(phys_addr_t pa);
39 phys_addr_t (*alloc_pte)(uintptr_t va);
40#ifndef __PAGETABLE_PMD_FOLDED
41 pmd_t *(*get_pmd_virt)(phys_addr_t pa);
42 phys_addr_t (*alloc_pmd)(uintptr_t va);
43#endif
44};
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070045
Kefeng Wangda815582020-10-31 14:01:12 +080046static phys_addr_t dma32_phys_limit __ro_after_init;
47
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070048static void __init zone_sizes_init(void)
49{
Christoph Hellwig5ec9c4f2018-01-16 09:37:50 +010050 unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070051
Zong Lid5fad482018-06-25 16:49:37 +080052#ifdef CONFIG_ZONE_DMA32
Kefeng Wangda815582020-10-31 14:01:12 +080053 max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit);
Zong Lid5fad482018-06-25 16:49:37 +080054#endif
Christoph Hellwig5ec9c4f2018-01-16 09:37:50 +010055 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
56
Mike Rapoport9691a072020-06-03 15:57:10 -070057 free_area_init(max_zone_pfns);
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070058}
59
Christoph Hellwig6bd33e12019-10-28 13:10:41 +010060static void setup_zero_page(void)
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070061{
62 memset((void *)empty_zero_page, 0, PAGE_SIZE);
63}
64
Kefeng Wang8fa3cdf2020-05-14 19:53:35 +080065#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
Yash Shah2cc6c4a2019-11-18 05:58:34 +000066static inline void print_mlk(char *name, unsigned long b, unsigned long t)
67{
68 pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld kB)\n", name, b, t,
69 (((t) - (b)) >> 10));
70}
71
72static inline void print_mlm(char *name, unsigned long b, unsigned long t)
73{
74 pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld MB)\n", name, b, t,
75 (((t) - (b)) >> 20));
76}
77
78static void print_vm_layout(void)
79{
80 pr_notice("Virtual kernel memory layout:\n");
81 print_mlk("fixmap", (unsigned long)FIXADDR_START,
82 (unsigned long)FIXADDR_TOP);
83 print_mlm("pci io", (unsigned long)PCI_IO_START,
84 (unsigned long)PCI_IO_END);
85 print_mlm("vmemmap", (unsigned long)VMEMMAP_START,
86 (unsigned long)VMEMMAP_END);
87 print_mlm("vmalloc", (unsigned long)VMALLOC_START,
88 (unsigned long)VMALLOC_END);
89 print_mlm("lowmem", (unsigned long)PAGE_OFFSET,
90 (unsigned long)high_memory);
91}
92#else
93static void print_vm_layout(void) { }
94#endif /* CONFIG_DEBUG_VM */
95
Palmer Dabbelt76d2a042017-07-10 18:00:26 -070096void __init mem_init(void)
97{
98#ifdef CONFIG_FLATMEM
99 BUG_ON(!mem_map);
100#endif /* CONFIG_FLATMEM */
101
102 high_memory = (void *)(__va(PFN_PHYS(max_low_pfn)));
Mike Rapoportc6ffc5c2018-10-30 15:09:30 -0700103 memblock_free_all();
Palmer Dabbelt76d2a042017-07-10 18:00:26 -0700104
105 mem_init_print_info(NULL);
Yash Shah2cc6c4a2019-11-18 05:58:34 +0000106 print_vm_layout();
Palmer Dabbelt76d2a042017-07-10 18:00:26 -0700107}
108
Anup Patel0651c262019-02-21 11:25:49 +0530109void __init setup_bootmem(void)
110{
Zong Liac51e002020-01-02 11:12:40 +0800111 phys_addr_t vmlinux_end = __pa_symbol(&_end);
112 phys_addr_t vmlinux_start = __pa_symbol(&_start);
Kefeng Wangdd2d0822021-02-09 09:01:51 +0800113 phys_addr_t dram_end = memblock_end_of_DRAM();
Atish Patraabb8e862021-01-11 15:45:02 -0800114 phys_addr_t max_mapped_addr = __pa(~(ulong)0);
Anup Patel0651c262019-02-21 11:25:49 +0530115
Kefeng Wangdd2d0822021-02-09 09:01:51 +0800116 /* The maximal physical memory size is -PAGE_OFFSET. */
Atish Patrade043da2020-12-18 16:13:56 -0800117 memblock_enforce_memory_limit(-PAGE_OFFSET);
Anup Patel0651c262019-02-21 11:25:49 +0530118
Anup Pateld90d45d2019-06-07 06:01:29 +0000119 /* Reserve from the start of the kernel to the end of the kernel */
120 memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
121
Atish Patraabb8e862021-01-11 15:45:02 -0800122 /*
123 * memblock allocator is not aware of the fact that last 4K bytes of
124 * the addressable memory can not be mapped because of IS_ERR_VALUE
125 * macro. Make sure that last 4k bytes are not usable by memblock
126 * if end of dram is equal to maximum addressable memory.
127 */
128 if (max_mapped_addr == (dram_end - 1))
129 memblock_set_current_limit(max_mapped_addr - 4096);
130
131 max_pfn = PFN_DOWN(dram_end);
Vincent Chenc749bb22020-04-27 14:59:24 +0800132 max_low_pfn = max_pfn;
Kefeng Wangda815582020-10-31 14:01:12 +0800133 dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn));
Guo Ren336e8eb2021-01-21 14:31:17 +0800134 set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET);
Anup Patel0651c262019-02-21 11:25:49 +0530135
Kefeng Wangaec33b52021-01-15 13:46:06 +0800136 reserve_initrd_mem();
Albert Ou922b0372019-09-27 16:14:18 -0700137 /*
Vitaly Woolf105aa92021-01-16 01:49:48 +0200138 * If DTB is built in, no need to reserve its memblock.
139 * Otherwise, do reserve it but avoid using
140 * early_init_fdt_reserve_self() since __pa() does
Albert Ou922b0372019-09-27 16:14:18 -0700141 * not work for DTB pointers that are fixmap addresses
142 */
Vitaly Woolf105aa92021-01-16 01:49:48 +0200143 if (!IS_ENABLED(CONFIG_BUILTIN_DTB))
144 memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
Albert Ou922b0372019-09-27 16:14:18 -0700145
Anup Patel0651c262019-02-21 11:25:49 +0530146 early_init_fdt_scan_reserved_mem();
Kefeng Wangda815582020-10-31 14:01:12 +0800147 dma_contiguous_reserve(dma32_phys_limit);
Anup Patel0651c262019-02-21 11:25:49 +0530148 memblock_allow_resize();
Anup Patel0651c262019-02-21 11:25:49 +0530149}
Anup Patel6f1e9e92019-02-13 16:38:36 +0530150
Christoph Hellwig6bd33e12019-10-28 13:10:41 +0100151#ifdef CONFIG_MMU
Atish Patrae8dcb612020-09-17 15:37:12 -0700152static struct pt_alloc_ops pt_ops;
153
Anup Patel387181d2019-03-26 08:03:47 +0000154unsigned long va_pa_offset;
155EXPORT_SYMBOL(va_pa_offset);
156unsigned long pfn_base;
157EXPORT_SYMBOL(pfn_base);
158
Anup Patel6f1e9e92019-02-13 16:38:36 +0530159pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
Anup Patel671f9a32019-06-28 13:36:21 -0700160pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
Anup Patelf2c17aa2019-01-07 20:57:01 +0530161pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
Anup Patel671f9a32019-06-28 13:36:21 -0700162
Anup Patel671f9a32019-06-28 13:36:21 -0700163pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE);
Anup Patelf2c17aa2019-01-07 20:57:01 +0530164
165void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
166{
167 unsigned long addr = __fix_to_virt(idx);
168 pte_t *ptep;
169
170 BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses);
171
172 ptep = &fixmap_pte[pte_index(addr)];
173
Greentime Hu21190b72020-08-04 11:02:05 +0800174 if (pgprot_val(prot))
Anup Patelf2c17aa2019-01-07 20:57:01 +0530175 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
Greentime Hu21190b72020-08-04 11:02:05 +0800176 else
Anup Patelf2c17aa2019-01-07 20:57:01 +0530177 pte_clear(&init_mm, addr, ptep);
Greentime Hu21190b72020-08-04 11:02:05 +0800178 local_flush_tlb_page(addr);
Anup Patelf2c17aa2019-01-07 20:57:01 +0530179}
180
Atish Patrae8dcb612020-09-17 15:37:12 -0700181static inline pte_t *__init get_pte_virt_early(phys_addr_t pa)
Anup Patel671f9a32019-06-28 13:36:21 -0700182{
Atish Patrae8dcb612020-09-17 15:37:12 -0700183 return (pte_t *)((uintptr_t)pa);
Anup Patel671f9a32019-06-28 13:36:21 -0700184}
185
Atish Patrae8dcb612020-09-17 15:37:12 -0700186static inline pte_t *__init get_pte_virt_fixmap(phys_addr_t pa)
187{
188 clear_fixmap(FIX_PTE);
189 return (pte_t *)set_fixmap_offset(FIX_PTE, pa);
190}
191
192static inline pte_t *get_pte_virt_late(phys_addr_t pa)
193{
194 return (pte_t *) __va(pa);
195}
196
197static inline phys_addr_t __init alloc_pte_early(uintptr_t va)
Anup Patel671f9a32019-06-28 13:36:21 -0700198{
199 /*
200 * We only create PMD or PGD early mappings so we
201 * should never reach here with MMU disabled.
202 */
Atish Patrae8dcb612020-09-17 15:37:12 -0700203 BUG();
204}
Anup Patel671f9a32019-06-28 13:36:21 -0700205
Atish Patrae8dcb612020-09-17 15:37:12 -0700206static inline phys_addr_t __init alloc_pte_fixmap(uintptr_t va)
207{
Anup Patel671f9a32019-06-28 13:36:21 -0700208 return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE);
209}
210
Atish Patrae8dcb612020-09-17 15:37:12 -0700211static phys_addr_t alloc_pte_late(uintptr_t va)
212{
213 unsigned long vaddr;
214
215 vaddr = __get_free_page(GFP_KERNEL);
216 if (!vaddr || !pgtable_pte_page_ctor(virt_to_page(vaddr)))
217 BUG();
218 return __pa(vaddr);
219}
220
Anup Patel671f9a32019-06-28 13:36:21 -0700221static void __init create_pte_mapping(pte_t *ptep,
222 uintptr_t va, phys_addr_t pa,
223 phys_addr_t sz, pgprot_t prot)
224{
Mike Rapoport974b9b22020-06-08 21:33:10 -0700225 uintptr_t pte_idx = pte_index(va);
Anup Patel671f9a32019-06-28 13:36:21 -0700226
227 BUG_ON(sz != PAGE_SIZE);
228
Mike Rapoport974b9b22020-06-08 21:33:10 -0700229 if (pte_none(ptep[pte_idx]))
230 ptep[pte_idx] = pfn_pte(PFN_DOWN(pa), prot);
Anup Patel671f9a32019-06-28 13:36:21 -0700231}
232
233#ifndef __PAGETABLE_PMD_FOLDED
234
235pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss;
236pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss;
Alexandre Ghiti0f02de42021-02-21 09:22:33 -0500237pmd_t early_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE);
Anup Patel1074dd42020-11-04 12:07:13 +0530238pmd_t early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE);
Anup Patel671f9a32019-06-28 13:36:21 -0700239
Atish Patrae8dcb612020-09-17 15:37:12 -0700240static pmd_t *__init get_pmd_virt_early(phys_addr_t pa)
Anup Patel671f9a32019-06-28 13:36:21 -0700241{
Atish Patrae8dcb612020-09-17 15:37:12 -0700242 /* Before MMU is enabled */
243 return (pmd_t *)((uintptr_t)pa);
Anup Patel671f9a32019-06-28 13:36:21 -0700244}
245
Atish Patrae8dcb612020-09-17 15:37:12 -0700246static pmd_t *__init get_pmd_virt_fixmap(phys_addr_t pa)
247{
248 clear_fixmap(FIX_PMD);
249 return (pmd_t *)set_fixmap_offset(FIX_PMD, pa);
250}
251
252static pmd_t *get_pmd_virt_late(phys_addr_t pa)
253{
254 return (pmd_t *) __va(pa);
255}
256
257static phys_addr_t __init alloc_pmd_early(uintptr_t va)
Anup Patel671f9a32019-06-28 13:36:21 -0700258{
Alexandre Ghiti0f02de42021-02-21 09:22:33 -0500259 BUG_ON((va - PAGE_OFFSET) >> PGDIR_SHIFT);
Anup Patel671f9a32019-06-28 13:36:21 -0700260
Alexandre Ghiti0f02de42021-02-21 09:22:33 -0500261 return (uintptr_t)early_pmd;
Anup Patel671f9a32019-06-28 13:36:21 -0700262}
263
Atish Patrae8dcb612020-09-17 15:37:12 -0700264static phys_addr_t __init alloc_pmd_fixmap(uintptr_t va)
265{
266 return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE);
267}
268
269static phys_addr_t alloc_pmd_late(uintptr_t va)
270{
271 unsigned long vaddr;
272
273 vaddr = __get_free_page(GFP_KERNEL);
274 BUG_ON(!vaddr);
275 return __pa(vaddr);
276}
277
Anup Patel671f9a32019-06-28 13:36:21 -0700278static void __init create_pmd_mapping(pmd_t *pmdp,
279 uintptr_t va, phys_addr_t pa,
280 phys_addr_t sz, pgprot_t prot)
281{
282 pte_t *ptep;
283 phys_addr_t pte_phys;
Mike Rapoport974b9b22020-06-08 21:33:10 -0700284 uintptr_t pmd_idx = pmd_index(va);
Anup Patel671f9a32019-06-28 13:36:21 -0700285
286 if (sz == PMD_SIZE) {
Mike Rapoport974b9b22020-06-08 21:33:10 -0700287 if (pmd_none(pmdp[pmd_idx]))
288 pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pa), prot);
Anup Patel671f9a32019-06-28 13:36:21 -0700289 return;
290 }
291
Mike Rapoport974b9b22020-06-08 21:33:10 -0700292 if (pmd_none(pmdp[pmd_idx])) {
Atish Patrae8dcb612020-09-17 15:37:12 -0700293 pte_phys = pt_ops.alloc_pte(va);
Mike Rapoport974b9b22020-06-08 21:33:10 -0700294 pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pte_phys), PAGE_TABLE);
Atish Patrae8dcb612020-09-17 15:37:12 -0700295 ptep = pt_ops.get_pte_virt(pte_phys);
Anup Patel671f9a32019-06-28 13:36:21 -0700296 memset(ptep, 0, PAGE_SIZE);
297 } else {
Mike Rapoport974b9b22020-06-08 21:33:10 -0700298 pte_phys = PFN_PHYS(_pmd_pfn(pmdp[pmd_idx]));
Atish Patrae8dcb612020-09-17 15:37:12 -0700299 ptep = pt_ops.get_pte_virt(pte_phys);
Anup Patel671f9a32019-06-28 13:36:21 -0700300 }
301
302 create_pte_mapping(ptep, va, pa, sz, prot);
303}
304
305#define pgd_next_t pmd_t
Atish Patrae8dcb612020-09-17 15:37:12 -0700306#define alloc_pgd_next(__va) pt_ops.alloc_pmd(__va)
307#define get_pgd_next_virt(__pa) pt_ops.get_pmd_virt(__pa)
Anup Patel671f9a32019-06-28 13:36:21 -0700308#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \
309 create_pmd_mapping(__nextp, __va, __pa, __sz, __prot)
Anup Patel671f9a32019-06-28 13:36:21 -0700310#define fixmap_pgd_next fixmap_pmd
311#else
312#define pgd_next_t pte_t
Atish Patrae8dcb612020-09-17 15:37:12 -0700313#define alloc_pgd_next(__va) pt_ops.alloc_pte(__va)
314#define get_pgd_next_virt(__pa) pt_ops.get_pte_virt(__pa)
Anup Patel671f9a32019-06-28 13:36:21 -0700315#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \
316 create_pte_mapping(__nextp, __va, __pa, __sz, __prot)
Anup Patel671f9a32019-06-28 13:36:21 -0700317#define fixmap_pgd_next fixmap_pte
318#endif
319
Atish Patrab91540d2020-09-17 15:37:15 -0700320void __init create_pgd_mapping(pgd_t *pgdp,
Anup Patel671f9a32019-06-28 13:36:21 -0700321 uintptr_t va, phys_addr_t pa,
322 phys_addr_t sz, pgprot_t prot)
323{
324 pgd_next_t *nextp;
325 phys_addr_t next_phys;
Mike Rapoport974b9b22020-06-08 21:33:10 -0700326 uintptr_t pgd_idx = pgd_index(va);
Anup Patel671f9a32019-06-28 13:36:21 -0700327
328 if (sz == PGDIR_SIZE) {
Mike Rapoport974b9b22020-06-08 21:33:10 -0700329 if (pgd_val(pgdp[pgd_idx]) == 0)
330 pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(pa), prot);
Anup Patel671f9a32019-06-28 13:36:21 -0700331 return;
332 }
333
Mike Rapoport974b9b22020-06-08 21:33:10 -0700334 if (pgd_val(pgdp[pgd_idx]) == 0) {
Anup Patel671f9a32019-06-28 13:36:21 -0700335 next_phys = alloc_pgd_next(va);
Mike Rapoport974b9b22020-06-08 21:33:10 -0700336 pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE);
Anup Patel671f9a32019-06-28 13:36:21 -0700337 nextp = get_pgd_next_virt(next_phys);
338 memset(nextp, 0, PAGE_SIZE);
339 } else {
Mike Rapoport974b9b22020-06-08 21:33:10 -0700340 next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx]));
Anup Patel671f9a32019-06-28 13:36:21 -0700341 nextp = get_pgd_next_virt(next_phys);
342 }
343
344 create_pgd_next_mapping(nextp, va, pa, sz, prot);
345}
346
347static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
348{
Zong Li0fdc6362019-11-08 01:00:40 -0800349 /* Upgrade to PMD_SIZE mappings whenever possible */
350 if ((base & (PMD_SIZE - 1)) || (size & (PMD_SIZE - 1)))
351 return PAGE_SIZE;
Anup Patel671f9a32019-06-28 13:36:21 -0700352
Zong Li0fdc6362019-11-08 01:00:40 -0800353 return PMD_SIZE;
Anup Patel671f9a32019-06-28 13:36:21 -0700354}
355
Anup Patel387181d2019-03-26 08:03:47 +0000356/*
357 * setup_vm() is called from head.S with MMU-off.
358 *
359 * Following requirements should be honoured for setup_vm() to work
360 * correctly:
361 * 1) It should use PC-relative addressing for accessing kernel symbols.
362 * To achieve this we always use GCC cmodel=medany.
363 * 2) The compiler instrumentation for FTRACE will not work for setup_vm()
364 * so disable compiler instrumentation when FTRACE is enabled.
365 *
366 * Currently, the above requirements are honoured by using custom CFLAGS
367 * for init.o in mm/Makefile.
368 */
369
370#ifndef __riscv_cmodel_medany
Paul Walmsley6a527b62019-10-17 14:45:58 -0700371#error "setup_vm() is called from head.S before relocate so it should not use absolute addressing."
Anup Patel387181d2019-03-26 08:03:47 +0000372#endif
373
Anup Patel671f9a32019-06-28 13:36:21 -0700374asmlinkage void __init setup_vm(uintptr_t dtb_pa)
Anup Patel6f1e9e92019-02-13 16:38:36 +0530375{
Anup Patel8f3a2b42020-09-17 15:37:10 -0700376 uintptr_t va, pa, end_va;
Anup Patel671f9a32019-06-28 13:36:21 -0700377 uintptr_t load_pa = (uintptr_t)(&_start);
378 uintptr_t load_sz = (uintptr_t)(&_end) - load_pa;
Alexandre Ghiti0f02de42021-02-21 09:22:33 -0500379 uintptr_t map_size;
Atish Patra6262f662020-09-17 15:37:11 -0700380#ifndef __PAGETABLE_PMD_FOLDED
381 pmd_t fix_bmap_spmd, fix_bmap_epmd;
382#endif
Anup Patel6f1e9e92019-02-13 16:38:36 +0530383
Anup Patel671f9a32019-06-28 13:36:21 -0700384 va_pa_offset = PAGE_OFFSET - load_pa;
385 pfn_base = PFN_DOWN(load_pa);
386
387 /*
388 * Enforce boot alignment requirements of RV32 and
389 * RV64 by only allowing PMD or PGD mappings.
390 */
Alexandre Ghiti0f02de42021-02-21 09:22:33 -0500391 map_size = PMD_SIZE;
Anup Patel6f1e9e92019-02-13 16:38:36 +0530392
393 /* Sanity check alignment and size */
394 BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0);
Anup Patel671f9a32019-06-28 13:36:21 -0700395 BUG_ON((load_pa % map_size) != 0);
Anup Patel671f9a32019-06-28 13:36:21 -0700396
Atish Patrae8dcb612020-09-17 15:37:12 -0700397 pt_ops.alloc_pte = alloc_pte_early;
398 pt_ops.get_pte_virt = get_pte_virt_early;
399#ifndef __PAGETABLE_PMD_FOLDED
400 pt_ops.alloc_pmd = alloc_pmd_early;
401 pt_ops.get_pmd_virt = get_pmd_virt_early;
402#endif
Anup Patel671f9a32019-06-28 13:36:21 -0700403 /* Setup early PGD for fixmap */
404 create_pgd_mapping(early_pg_dir, FIXADDR_START,
405 (uintptr_t)fixmap_pgd_next, PGDIR_SIZE, PAGE_TABLE);
Anup Patel6f1e9e92019-02-13 16:38:36 +0530406
407#ifndef __PAGETABLE_PMD_FOLDED
Anup Patel671f9a32019-06-28 13:36:21 -0700408 /* Setup fixmap PMD */
409 create_pmd_mapping(fixmap_pmd, FIXADDR_START,
410 (uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE);
411 /* Setup trampoline PGD and PMD */
412 create_pgd_mapping(trampoline_pg_dir, PAGE_OFFSET,
413 (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE);
414 create_pmd_mapping(trampoline_pmd, PAGE_OFFSET,
415 load_pa, PMD_SIZE, PAGE_KERNEL_EXEC);
Anup Patel6f1e9e92019-02-13 16:38:36 +0530416#else
Anup Patel671f9a32019-06-28 13:36:21 -0700417 /* Setup trampoline PGD */
418 create_pgd_mapping(trampoline_pg_dir, PAGE_OFFSET,
419 load_pa, PGDIR_SIZE, PAGE_KERNEL_EXEC);
420#endif
Anup Patel6f1e9e92019-02-13 16:38:36 +0530421
Anup Patel671f9a32019-06-28 13:36:21 -0700422 /*
423 * Setup early PGD covering entire kernel which will allows
424 * us to reach paging_init(). We map all memory banks later
425 * in setup_vm_final() below.
426 */
427 end_va = PAGE_OFFSET + load_sz;
428 for (va = PAGE_OFFSET; va < end_va; va += map_size)
429 create_pgd_mapping(early_pg_dir, va,
430 load_pa + (va - PAGE_OFFSET),
431 map_size, PAGE_KERNEL_EXEC);
Anup Patelf2c17aa2019-01-07 20:57:01 +0530432
Anup Patel1074dd42020-11-04 12:07:13 +0530433#ifndef __PAGETABLE_PMD_FOLDED
434 /* Setup early PMD for DTB */
435 create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA,
436 (uintptr_t)early_dtb_pmd, PGDIR_SIZE, PAGE_TABLE);
Vitaly Woolf105aa92021-01-16 01:49:48 +0200437#ifndef CONFIG_BUILTIN_DTB
Anup Patel1074dd42020-11-04 12:07:13 +0530438 /* Create two consecutive PMD mappings for FDT early scan */
439 pa = dtb_pa & ~(PMD_SIZE - 1);
440 create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA,
441 pa, PMD_SIZE, PAGE_KERNEL);
442 create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA + PMD_SIZE,
443 pa + PMD_SIZE, PMD_SIZE, PAGE_KERNEL);
444 dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PMD_SIZE - 1));
Vitaly Woolf105aa92021-01-16 01:49:48 +0200445#else /* CONFIG_BUILTIN_DTB */
446 dtb_early_va = __va(dtb_pa);
447#endif /* CONFIG_BUILTIN_DTB */
Anup Patel1074dd42020-11-04 12:07:13 +0530448#else
Vitaly Woolf105aa92021-01-16 01:49:48 +0200449#ifndef CONFIG_BUILTIN_DTB
Anup Patel8f3a2b42020-09-17 15:37:10 -0700450 /* Create two consecutive PGD mappings for FDT early scan */
451 pa = dtb_pa & ~(PGDIR_SIZE - 1);
452 create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA,
453 pa, PGDIR_SIZE, PAGE_KERNEL);
454 create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA + PGDIR_SIZE,
455 pa + PGDIR_SIZE, PGDIR_SIZE, PAGE_KERNEL);
456 dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PGDIR_SIZE - 1));
Vitaly Woolf105aa92021-01-16 01:49:48 +0200457#else /* CONFIG_BUILTIN_DTB */
458 dtb_early_va = __va(dtb_pa);
459#endif /* CONFIG_BUILTIN_DTB */
Anup Patel1074dd42020-11-04 12:07:13 +0530460#endif
Albert Ou922b0372019-09-27 16:14:18 -0700461 dtb_early_pa = dtb_pa;
Atish Patra6262f662020-09-17 15:37:11 -0700462
463 /*
464 * Bootime fixmap only can handle PMD_SIZE mapping. Thus, boot-ioremap
465 * range can not span multiple pmds.
466 */
467 BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
468 != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
469
470#ifndef __PAGETABLE_PMD_FOLDED
471 /*
472 * Early ioremap fixmap is already created as it lies within first 2MB
473 * of fixmap region. We always map PMD_SIZE. Thus, both FIX_BTMAP_END
474 * FIX_BTMAP_BEGIN should lie in the same pmd. Verify that and warn
475 * the user if not.
476 */
477 fix_bmap_spmd = fixmap_pmd[pmd_index(__fix_to_virt(FIX_BTMAP_BEGIN))];
478 fix_bmap_epmd = fixmap_pmd[pmd_index(__fix_to_virt(FIX_BTMAP_END))];
479 if (pmd_val(fix_bmap_spmd) != pmd_val(fix_bmap_epmd)) {
480 WARN_ON(1);
481 pr_warn("fixmap btmap start [%08lx] != end [%08lx]\n",
482 pmd_val(fix_bmap_spmd), pmd_val(fix_bmap_epmd));
483 pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
484 fix_to_virt(FIX_BTMAP_BEGIN));
485 pr_warn("fix_to_virt(FIX_BTMAP_END): %08lx\n",
486 fix_to_virt(FIX_BTMAP_END));
487
488 pr_warn("FIX_BTMAP_END: %d\n", FIX_BTMAP_END);
489 pr_warn("FIX_BTMAP_BEGIN: %d\n", FIX_BTMAP_BEGIN);
490 }
491#endif
Anup Patel671f9a32019-06-28 13:36:21 -0700492}
493
494static void __init setup_vm_final(void)
495{
496 uintptr_t va, map_size;
497 phys_addr_t pa, start, end;
Mike Rapoportb10d6bc2020-10-13 16:58:08 -0700498 u64 i;
Anup Patel671f9a32019-06-28 13:36:21 -0700499
Atish Patrae8dcb612020-09-17 15:37:12 -0700500 /**
501 * MMU is enabled at this point. But page table setup is not complete yet.
502 * fixmap page table alloc functions should be used at this point
503 */
504 pt_ops.alloc_pte = alloc_pte_fixmap;
505 pt_ops.get_pte_virt = get_pte_virt_fixmap;
506#ifndef __PAGETABLE_PMD_FOLDED
507 pt_ops.alloc_pmd = alloc_pmd_fixmap;
508 pt_ops.get_pmd_virt = get_pmd_virt_fixmap;
509#endif
Anup Patel671f9a32019-06-28 13:36:21 -0700510 /* Setup swapper PGD for fixmap */
511 create_pgd_mapping(swapper_pg_dir, FIXADDR_START,
Zong Liac51e002020-01-02 11:12:40 +0800512 __pa_symbol(fixmap_pgd_next),
Anup Patel671f9a32019-06-28 13:36:21 -0700513 PGDIR_SIZE, PAGE_TABLE);
514
515 /* Map all memory banks */
Mike Rapoportb10d6bc2020-10-13 16:58:08 -0700516 for_each_mem_range(i, &start, &end) {
Anup Patel671f9a32019-06-28 13:36:21 -0700517 if (start >= end)
518 break;
Anup Patel671f9a32019-06-28 13:36:21 -0700519 if (start <= __pa(PAGE_OFFSET) &&
520 __pa(PAGE_OFFSET) < end)
521 start = __pa(PAGE_OFFSET);
522
523 map_size = best_map_size(start, end - start);
524 for (pa = start; pa < end; pa += map_size) {
525 va = (uintptr_t)__va(pa);
526 create_pgd_mapping(swapper_pg_dir, va, pa,
527 map_size, PAGE_KERNEL_EXEC);
528 }
Anup Patel6f1e9e92019-02-13 16:38:36 +0530529 }
Anup Patelf2c17aa2019-01-07 20:57:01 +0530530
Anup Patel671f9a32019-06-28 13:36:21 -0700531 /* Clear fixmap PTE and PMD mappings */
532 clear_fixmap(FIX_PTE);
533 clear_fixmap(FIX_PMD);
534
535 /* Move to swapper page table */
Zong Liac51e002020-01-02 11:12:40 +0800536 csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | SATP_MODE);
Anup Patel671f9a32019-06-28 13:36:21 -0700537 local_flush_tlb_all();
Atish Patrae8dcb612020-09-17 15:37:12 -0700538
539 /* generic page allocation functions must be used to setup page table */
540 pt_ops.alloc_pte = alloc_pte_late;
541 pt_ops.get_pte_virt = get_pte_virt_late;
542#ifndef __PAGETABLE_PMD_FOLDED
543 pt_ops.alloc_pmd = alloc_pmd_late;
544 pt_ops.get_pmd_virt = get_pmd_virt_late;
545#endif
Anup Patel671f9a32019-06-28 13:36:21 -0700546}
Christoph Hellwig6bd33e12019-10-28 13:10:41 +0100547#else
548asmlinkage void __init setup_vm(uintptr_t dtb_pa)
549{
550 dtb_early_va = (void *)dtb_pa;
Atish Patraa78c6f52020-10-01 12:04:56 -0700551 dtb_early_pa = dtb_pa;
Christoph Hellwig6bd33e12019-10-28 13:10:41 +0100552}
553
554static inline void setup_vm_final(void)
555{
556}
557#endif /* CONFIG_MMU */
Anup Patel671f9a32019-06-28 13:36:21 -0700558
Zong Lid27c3c92020-03-10 00:55:41 +0800559#ifdef CONFIG_STRICT_KERNEL_RWX
Atish Patra19a00862020-11-04 16:04:38 -0800560void protect_kernel_text_data(void)
Zong Lid27c3c92020-03-10 00:55:41 +0800561{
Atish Patra19a00862020-11-04 16:04:38 -0800562 unsigned long text_start = (unsigned long)_start;
563 unsigned long init_text_start = (unsigned long)__init_text_begin;
564 unsigned long init_data_start = (unsigned long)__init_data_begin;
Zong Lid27c3c92020-03-10 00:55:41 +0800565 unsigned long rodata_start = (unsigned long)__start_rodata;
566 unsigned long data_start = (unsigned long)_data;
567 unsigned long max_low = (unsigned long)(__va(PFN_PHYS(max_low_pfn)));
568
Atish Patra19a00862020-11-04 16:04:38 -0800569 set_memory_ro(text_start, (init_text_start - text_start) >> PAGE_SHIFT);
570 set_memory_ro(init_text_start, (init_data_start - init_text_start) >> PAGE_SHIFT);
571 set_memory_nx(init_data_start, (rodata_start - init_data_start) >> PAGE_SHIFT);
572 /* rodata section is marked readonly in mark_rodata_ro */
Zong Lid27c3c92020-03-10 00:55:41 +0800573 set_memory_nx(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT);
574 set_memory_nx(data_start, (max_low - data_start) >> PAGE_SHIFT);
Atish Patra19a00862020-11-04 16:04:38 -0800575}
576
577void mark_rodata_ro(void)
578{
579 unsigned long rodata_start = (unsigned long)__start_rodata;
580 unsigned long data_start = (unsigned long)_data;
581
582 set_memory_ro(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT);
Zong Lib422d282020-06-03 16:03:55 -0700583
584 debug_checkwx();
Zong Lid27c3c92020-03-10 00:55:41 +0800585}
586#endif
587
Anup Patel671f9a32019-06-28 13:36:21 -0700588void __init paging_init(void)
589{
590 setup_vm_final();
591 setup_zero_page();
Atish Patracbd34f42020-11-18 16:38:27 -0800592}
593
594void __init misc_mem_init(void)
595{
Atish Patra4f0e8ee2020-11-18 16:38:29 -0800596 arch_numa_init();
Atish Patracbd34f42020-11-18 16:38:27 -0800597 sparse_init();
Anup Patel671f9a32019-06-28 13:36:21 -0700598 zone_sizes_init();
Atish Patra4f0e8ee2020-11-18 16:38:29 -0800599 memblock_dump_all();
Anup Patel6f1e9e92019-02-13 16:38:36 +0530600}
Logan Gunthorped95f1a52019-08-28 15:40:54 -0600601
Kefeng Wang9fe57d82019-10-23 11:23:02 +0800602#ifdef CONFIG_SPARSEMEM_VMEMMAP
Logan Gunthorped95f1a52019-08-28 15:40:54 -0600603int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
604 struct vmem_altmap *altmap)
605{
Anshuman Khandual1d9cfee2020-08-06 23:23:19 -0700606 return vmemmap_populate_basepages(start, end, node, NULL);
Logan Gunthorped95f1a52019-08-28 15:40:54 -0600607}
608#endif