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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnese5747e32014-06-12 08:35:47 -070030#include <linux/acpi.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010031#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/vt.h>
42#include <acpi/video.h>
43
David Howells760285e2012-10-02 18:01:07 +010044#include <drm/drmP.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010045#include <drm/drm_crtc_helper.h>
Maarten Lankhorsta667fb42016-12-15 15:29:44 +010046#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010047#include <drm/i915_drm.h>
Chris Wilson0673ad42016-06-24 14:00:22 +010048
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030050#include "i915_trace.h"
Chris Wilson0673ad42016-06-24 14:00:22 +010051#include "i915_vgpu.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070052#include "intel_drv.h"
Anusha Srivatsa5464cd62017-01-18 08:05:58 -080053#include "intel_uc.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
Kristian Høgsberg112b7152009-01-04 16:55:33 -050055static struct drm_driver driver;
56
Chris Wilson0673ad42016-06-24 14:00:22 +010057static unsigned int i915_load_fail_count;
58
59bool __i915_inject_load_failure(const char *func, int line)
60{
61 if (i915_load_fail_count >= i915.inject_load_failure)
62 return false;
63
64 if (++i915_load_fail_count == i915.inject_load_failure) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915.inject_load_failure, func, line);
67 return true;
68 }
69
70 return false;
71}
72
73#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
76
77void
78__i915_printk(struct drm_i915_private *dev_priv, const char *level,
79 const char *fmt, ...)
80{
81 static bool shown_bug_once;
David Weinehallc49d13e2016-08-22 13:32:42 +030082 struct device *kdev = dev_priv->drm.dev;
Chris Wilson0673ad42016-06-24 14:00:22 +010083 bool is_error = level[1] <= KERN_ERR[1];
84 bool is_debug = level[1] == KERN_DEBUG[1];
85 struct va_format vaf;
86 va_list args;
87
88 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
89 return;
90
91 va_start(args, fmt);
92
93 vaf.fmt = fmt;
94 vaf.va = &args;
95
David Weinehallc49d13e2016-08-22 13:32:42 +030096 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
Chris Wilson0673ad42016-06-24 14:00:22 +010097 __builtin_return_address(0), &vaf);
98
99 if (is_error && !shown_bug_once) {
David Weinehallc49d13e2016-08-22 13:32:42 +0300100 dev_notice(kdev, "%s", FDO_BUG_MSG);
Chris Wilson0673ad42016-06-24 14:00:22 +0100101 shown_bug_once = true;
102 }
103
104 va_end(args);
105}
106
107static bool i915_error_injected(struct drm_i915_private *dev_priv)
108{
109 return i915.inject_load_failure &&
110 i915_load_fail_count == i915.inject_load_failure;
111}
112
113#define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
116 fmt, ##__VA_ARGS__)
117
118
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100119static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
Robert Beckett30c964a2015-08-28 13:10:22 +0100120{
121 enum intel_pch ret = PCH_NOP;
122
123 /*
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
128 */
129
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100130 if (IS_GEN5(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100131 ret = PCH_IBX;
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100133 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100134 ret = PCH_CPT;
135 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100136 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100137 ret = PCH_LPT;
138 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100139 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100140 ret = PCH_SPT;
141 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
142 }
143
144 return ret;
145}
146
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000147static void intel_detect_pch(struct drm_i915_private *dev_priv)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800148{
Imre Deakbcdb72a2014-02-14 20:23:54 +0200149 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800150
Ben Widawskyce1bb322013-04-05 13:12:44 -0700151 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
152 * (which really amounts to a PCH but no South Display).
153 */
Tvrtko Ursulinb7f05d42016-11-09 11:30:45 +0000154 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
Ben Widawskyce1bb322013-04-05 13:12:44 -0700155 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700156 return;
157 }
158
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800159 /*
160 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
161 * make graphics device passthrough work easy for VMM, that only
162 * need to expose ISA bridge to let driver know the real hardware
163 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800164 *
165 * In some virtualized environments (e.g. XEN), there is irrelevant
166 * ISA bridge in the system. To work reliably, we should scan trhough
167 * all the ISA bridge devices and check for the first match, instead
168 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800169 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200170 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800171 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200172 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200173 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800174
Jesse Barnes90711d52011-04-28 14:48:02 -0700175 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
176 dev_priv->pch_type = PCH_IBX;
177 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Tvrtko Ursulin5db94012016-10-13 11:03:10 +0100178 WARN_ON(!IS_GEN5(dev_priv));
Jesse Barnes90711d52011-04-28 14:48:02 -0700179 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800180 dev_priv->pch_type = PCH_CPT;
181 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100182 WARN_ON(!(IS_GEN6(dev_priv) ||
183 IS_IVYBRIDGE(dev_priv)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700184 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
185 /* PantherPoint is CPT compatible */
186 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300187 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100188 WARN_ON(!(IS_GEN6(dev_priv) ||
189 IS_IVYBRIDGE(dev_priv)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300190 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
191 dev_priv->pch_type = PCH_LPT;
192 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100193 WARN_ON(!IS_HASWELL(dev_priv) &&
194 !IS_BROADWELL(dev_priv));
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100195 WARN_ON(IS_HSW_ULT(dev_priv) ||
196 IS_BDW_ULT(dev_priv));
Ben Widawskye76e0632013-11-07 21:40:41 -0800197 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
198 dev_priv->pch_type = PCH_LPT;
199 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100200 WARN_ON(!IS_HASWELL(dev_priv) &&
201 !IS_BROADWELL(dev_priv));
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100202 WARN_ON(!IS_HSW_ULT(dev_priv) &&
203 !IS_BDW_ULT(dev_priv));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530204 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
205 dev_priv->pch_type = PCH_SPT;
206 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
Tvrtko Ursulin08537232016-10-13 11:03:02 +0100207 WARN_ON(!IS_SKYLAKE(dev_priv) &&
208 !IS_KABYLAKE(dev_priv));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530209 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
210 dev_priv->pch_type = PCH_SPT;
211 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
Tvrtko Ursulin08537232016-10-13 11:03:02 +0100212 WARN_ON(!IS_SKYLAKE(dev_priv) &&
213 !IS_KABYLAKE(dev_priv));
Rodrigo Vivi22dea0b2016-07-01 17:07:12 -0700214 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
215 dev_priv->pch_type = PCH_KBP;
216 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
Jani Nikula85327742017-02-01 15:46:09 +0200217 WARN_ON(!IS_SKYLAKE(dev_priv) &&
218 !IS_KABYLAKE(dev_priv));
Gerd Hoffmann39bfcd522015-11-26 12:03:51 +0100219 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
Jesse Barnes1844a662016-03-16 13:31:30 -0700220 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
Gerd Hoffmannf2e30512016-01-25 12:02:28 +0100221 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
Gerd Hoffmann94bb4892016-06-13 14:38:56 +0200222 pch->subsystem_vendor ==
223 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
224 pch->subsystem_device ==
225 PCI_SUBDEVICE_ID_QEMU)) {
Tvrtko Ursulinfd6b8f42016-10-14 10:13:06 +0100226 dev_priv->pch_type =
227 intel_virt_detect_pch(dev_priv);
Imre Deakbcdb72a2014-02-14 20:23:54 +0200228 } else
229 continue;
230
Rui Guo6a9c4b32013-06-19 21:10:23 +0800231 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800232 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800233 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800234 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200235 DRM_DEBUG_KMS("No PCH found.\n");
236
237 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800238}
239
Chris Wilson0673ad42016-06-24 14:00:22 +0100240static int i915_getparam(struct drm_device *dev, void *data,
241 struct drm_file *file_priv)
242{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100243 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +0300244 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100245 drm_i915_getparam_t *param = data;
246 int value;
247
248 switch (param->param) {
249 case I915_PARAM_IRQ_ACTIVE:
250 case I915_PARAM_ALLOW_BATCHBUFFER:
251 case I915_PARAM_LAST_DISPATCH:
Kenneth Graunkeef0f4112017-02-15 01:34:46 -0800252 case I915_PARAM_HAS_EXEC_CONSTANTS:
Chris Wilson0673ad42016-06-24 14:00:22 +0100253 /* Reject all old ums/dri params. */
254 return -ENODEV;
255 case I915_PARAM_CHIPSET_ID:
David Weinehall52a05c32016-08-22 13:32:44 +0300256 value = pdev->device;
Chris Wilson0673ad42016-06-24 14:00:22 +0100257 break;
258 case I915_PARAM_REVISION:
David Weinehall52a05c32016-08-22 13:32:44 +0300259 value = pdev->revision;
Chris Wilson0673ad42016-06-24 14:00:22 +0100260 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100261 case I915_PARAM_NUM_FENCES_AVAIL:
262 value = dev_priv->num_fence_regs;
263 break;
264 case I915_PARAM_HAS_OVERLAY:
265 value = dev_priv->overlay ? 1 : 0;
266 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100267 case I915_PARAM_HAS_BSD:
Akash Goel3b3f1652016-10-13 22:44:48 +0530268 value = !!dev_priv->engine[VCS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100269 break;
270 case I915_PARAM_HAS_BLT:
Akash Goel3b3f1652016-10-13 22:44:48 +0530271 value = !!dev_priv->engine[BCS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100272 break;
273 case I915_PARAM_HAS_VEBOX:
Akash Goel3b3f1652016-10-13 22:44:48 +0530274 value = !!dev_priv->engine[VECS];
Chris Wilson0673ad42016-06-24 14:00:22 +0100275 break;
276 case I915_PARAM_HAS_BSD2:
Akash Goel3b3f1652016-10-13 22:44:48 +0530277 value = !!dev_priv->engine[VCS2];
Chris Wilson0673ad42016-06-24 14:00:22 +0100278 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100279 case I915_PARAM_HAS_LLC:
David Weinehall16162472016-09-02 13:46:17 +0300280 value = HAS_LLC(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100281 break;
282 case I915_PARAM_HAS_WT:
David Weinehall16162472016-09-02 13:46:17 +0300283 value = HAS_WT(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100284 break;
285 case I915_PARAM_HAS_ALIASING_PPGTT:
David Weinehall16162472016-09-02 13:46:17 +0300286 value = USES_PPGTT(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100287 break;
288 case I915_PARAM_HAS_SEMAPHORES:
Chris Wilson39df9192016-07-20 13:31:57 +0100289 value = i915.semaphores;
Chris Wilson0673ad42016-06-24 14:00:22 +0100290 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100291 case I915_PARAM_HAS_SECURE_BATCHES:
292 value = capable(CAP_SYS_ADMIN);
293 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100294 case I915_PARAM_CMD_PARSER_VERSION:
295 value = i915_cmd_parser_get_version(dev_priv);
296 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100297 case I915_PARAM_SUBSLICE_TOTAL:
Imre Deak57ec1712016-08-31 19:13:05 +0300298 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
Chris Wilson0673ad42016-06-24 14:00:22 +0100299 if (!value)
300 return -ENODEV;
301 break;
302 case I915_PARAM_EU_TOTAL:
Imre Deak43b67992016-08-31 19:13:02 +0300303 value = INTEL_INFO(dev_priv)->sseu.eu_total;
Chris Wilson0673ad42016-06-24 14:00:22 +0100304 if (!value)
305 return -ENODEV;
306 break;
307 case I915_PARAM_HAS_GPU_RESET:
308 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
309 break;
310 case I915_PARAM_HAS_RESOURCE_STREAMER:
David Weinehall16162472016-09-02 13:46:17 +0300311 value = HAS_RESOURCE_STREAMER(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100312 break;
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100313 case I915_PARAM_HAS_POOLED_EU:
David Weinehall16162472016-09-02 13:46:17 +0300314 value = HAS_POOLED_EU(dev_priv);
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100315 break;
316 case I915_PARAM_MIN_EU_IN_POOL:
Imre Deak43b67992016-08-31 19:13:02 +0300317 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
arun.siluvery@linux.intel.com37f501a2016-07-01 11:43:02 +0100318 break;
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800319 case I915_PARAM_HUC_STATUS:
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +0530320 intel_runtime_pm_get(dev_priv);
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800321 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +0530322 intel_runtime_pm_put(dev_priv);
Anusha Srivatsa5464cd62017-01-18 08:05:58 -0800323 break;
Chris Wilson4cc69072016-08-25 19:05:19 +0100324 case I915_PARAM_MMAP_GTT_VERSION:
325 /* Though we've started our numbering from 1, and so class all
326 * earlier versions as 0, in effect their value is undefined as
327 * the ioctl will report EINVAL for the unknown param!
328 */
329 value = i915_gem_mmap_gtt_version();
330 break;
Chris Wilson0de91362016-11-14 20:41:01 +0000331 case I915_PARAM_HAS_SCHEDULER:
332 value = dev_priv->engine[RCS] &&
333 dev_priv->engine[RCS]->schedule;
334 break;
David Weinehall16162472016-09-02 13:46:17 +0300335 case I915_PARAM_MMAP_VERSION:
336 /* Remember to bump this if the version changes! */
337 case I915_PARAM_HAS_GEM:
338 case I915_PARAM_HAS_PAGEFLIPPING:
339 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
340 case I915_PARAM_HAS_RELAXED_FENCING:
341 case I915_PARAM_HAS_COHERENT_RINGS:
342 case I915_PARAM_HAS_RELAXED_DELTA:
343 case I915_PARAM_HAS_GEN7_SOL_RESET:
344 case I915_PARAM_HAS_WAIT_TIMEOUT:
345 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
346 case I915_PARAM_HAS_PINNED_BATCHES:
347 case I915_PARAM_HAS_EXEC_NO_RELOC:
348 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
349 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
350 case I915_PARAM_HAS_EXEC_SOFTPIN:
Chris Wilson77ae9952017-01-27 09:40:07 +0000351 case I915_PARAM_HAS_EXEC_ASYNC:
Chris Wilsonfec04452017-01-27 09:40:08 +0000352 case I915_PARAM_HAS_EXEC_FENCE:
Chris Wilsonb0fd47a2017-04-15 10:39:02 +0100353 case I915_PARAM_HAS_EXEC_CAPTURE:
David Weinehall16162472016-09-02 13:46:17 +0300354 /* For the time being all of these are always true;
355 * if some supported hardware does not have one of these
356 * features this value needs to be provided from
357 * INTEL_INFO(), a feature macro, or similar.
358 */
359 value = 1;
360 break;
Chris Wilson0673ad42016-06-24 14:00:22 +0100361 default:
362 DRM_DEBUG("Unknown parameter %d\n", param->param);
363 return -EINVAL;
364 }
365
Chris Wilsondda33002016-06-24 14:00:23 +0100366 if (put_user(value, param->value))
Chris Wilson0673ad42016-06-24 14:00:22 +0100367 return -EFAULT;
Chris Wilson0673ad42016-06-24 14:00:22 +0100368
369 return 0;
370}
371
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000372static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100373{
Chris Wilson0673ad42016-06-24 14:00:22 +0100374 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
375 if (!dev_priv->bridge_dev) {
376 DRM_ERROR("bridge device not found\n");
377 return -1;
378 }
379 return 0;
380}
381
382/* Allocate space for the MCH regs if needed, return nonzero on error */
383static int
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000384intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100385{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000386 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100387 u32 temp_lo, temp_hi = 0;
388 u64 mchbar_addr;
389 int ret;
390
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000391 if (INTEL_GEN(dev_priv) >= 4)
Chris Wilson0673ad42016-06-24 14:00:22 +0100392 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
393 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
394 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
395
396 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
397#ifdef CONFIG_PNP
398 if (mchbar_addr &&
399 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
400 return 0;
401#endif
402
403 /* Get some space for it */
404 dev_priv->mch_res.name = "i915 MCHBAR";
405 dev_priv->mch_res.flags = IORESOURCE_MEM;
406 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
407 &dev_priv->mch_res,
408 MCHBAR_SIZE, MCHBAR_SIZE,
409 PCIBIOS_MIN_MEM,
410 0, pcibios_align_resource,
411 dev_priv->bridge_dev);
412 if (ret) {
413 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
414 dev_priv->mch_res.start = 0;
415 return ret;
416 }
417
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000418 if (INTEL_GEN(dev_priv) >= 4)
Chris Wilson0673ad42016-06-24 14:00:22 +0100419 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
420 upper_32_bits(dev_priv->mch_res.start));
421
422 pci_write_config_dword(dev_priv->bridge_dev, reg,
423 lower_32_bits(dev_priv->mch_res.start));
424 return 0;
425}
426
427/* Setup MCHBAR if possible, return true if we should disable it again */
428static void
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000429intel_setup_mchbar(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100430{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000431 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100432 u32 temp;
433 bool enabled;
434
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100435 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +0100436 return;
437
438 dev_priv->mchbar_need_disable = false;
439
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100440 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100441 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
442 enabled = !!(temp & DEVEN_MCHBAR_EN);
443 } else {
444 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
445 enabled = temp & 1;
446 }
447
448 /* If it's already enabled, don't have to do anything */
449 if (enabled)
450 return;
451
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000452 if (intel_alloc_mchbar_resource(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +0100453 return;
454
455 dev_priv->mchbar_need_disable = true;
456
457 /* Space is allocated or reserved, so enable it. */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100458 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100459 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
460 temp | DEVEN_MCHBAR_EN);
461 } else {
462 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
463 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
464 }
465}
466
467static void
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000468intel_teardown_mchbar(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100469{
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000470 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
Chris Wilson0673ad42016-06-24 14:00:22 +0100471
472 if (dev_priv->mchbar_need_disable) {
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100473 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
Chris Wilson0673ad42016-06-24 14:00:22 +0100474 u32 deven_val;
475
476 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
477 &deven_val);
478 deven_val &= ~DEVEN_MCHBAR_EN;
479 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
480 deven_val);
481 } else {
482 u32 mchbar_val;
483
484 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
485 &mchbar_val);
486 mchbar_val &= ~1;
487 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
488 mchbar_val);
489 }
490 }
491
492 if (dev_priv->mch_res.start)
493 release_resource(&dev_priv->mch_res);
494}
495
496/* true = enable decode, false = disable decoder */
497static unsigned int i915_vga_set_decode(void *cookie, bool state)
498{
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000499 struct drm_i915_private *dev_priv = cookie;
Chris Wilson0673ad42016-06-24 14:00:22 +0100500
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000501 intel_modeset_vga_set_state(dev_priv, state);
Chris Wilson0673ad42016-06-24 14:00:22 +0100502 if (state)
503 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
504 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
505 else
506 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
507}
508
Tvrtko Ursulin7f26cb82016-12-01 14:16:41 +0000509static int i915_resume_switcheroo(struct drm_device *dev);
510static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
511
Chris Wilson0673ad42016-06-24 14:00:22 +0100512static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
513{
514 struct drm_device *dev = pci_get_drvdata(pdev);
515 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
516
517 if (state == VGA_SWITCHEROO_ON) {
518 pr_info("switched on\n");
519 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
520 /* i915 resume handler doesn't set to D0 */
David Weinehall52a05c32016-08-22 13:32:44 +0300521 pci_set_power_state(pdev, PCI_D0);
Chris Wilson0673ad42016-06-24 14:00:22 +0100522 i915_resume_switcheroo(dev);
523 dev->switch_power_state = DRM_SWITCH_POWER_ON;
524 } else {
525 pr_info("switched off\n");
526 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
527 i915_suspend_switcheroo(dev, pmm);
528 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
529 }
530}
531
532static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
533{
534 struct drm_device *dev = pci_get_drvdata(pdev);
535
536 /*
537 * FIXME: open_count is protected by drm_global_mutex but that would lead to
538 * locking inversion with the driver load path. And the access here is
539 * completely racy anyway. So don't bother with locking for now.
540 */
541 return dev->open_count == 0;
542}
543
544static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
545 .set_gpu_state = i915_switcheroo_set_state,
546 .reprobe = NULL,
547 .can_switch = i915_switcheroo_can_switch,
548};
549
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100550static void i915_gem_fini(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100551{
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100552 mutex_lock(&dev_priv->drm.struct_mutex);
Oscar Mateob8991402017-03-28 09:53:47 -0700553 intel_uc_fini_hw(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000554 i915_gem_cleanup_engines(dev_priv);
555 i915_gem_context_fini(dev_priv);
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100556 mutex_unlock(&dev_priv->drm.struct_mutex);
Chris Wilson0673ad42016-06-24 14:00:22 +0100557
Chris Wilsonbdeb9782016-12-23 14:57:56 +0000558 i915_gem_drain_freed_objects(dev_priv);
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100559
560 WARN_ON(!list_empty(&dev_priv->context_list));
Chris Wilson0673ad42016-06-24 14:00:22 +0100561}
562
563static int i915_load_modeset_init(struct drm_device *dev)
564{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100565 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +0300566 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100567 int ret;
568
569 if (i915_inject_load_failure())
570 return -ENODEV;
571
Jani Nikula66578852017-03-10 15:27:57 +0200572 intel_bios_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100573
574 /* If we have > 1 VGA cards, then we need to arbitrate access
575 * to the common VGA resources.
576 *
577 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
578 * then we do not take part in VGA arbitration and the
579 * vga_client_register() fails with -ENODEV.
580 */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000581 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
Chris Wilson0673ad42016-06-24 14:00:22 +0100582 if (ret && ret != -ENODEV)
583 goto out;
584
585 intel_register_dsm_handler();
586
David Weinehall52a05c32016-08-22 13:32:44 +0300587 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
Chris Wilson0673ad42016-06-24 14:00:22 +0100588 if (ret)
589 goto cleanup_vga_client;
590
591 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
592 intel_update_rawclk(dev_priv);
593
594 intel_power_domains_init_hw(dev_priv, false);
595
596 intel_csr_ucode_init(dev_priv);
597
598 ret = intel_irq_install(dev_priv);
599 if (ret)
600 goto cleanup_csr;
601
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000602 intel_setup_gmbus(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100603
604 /* Important: The output setup functions called by modeset_init need
605 * working irqs for e.g. gmbus and dp aux transfers. */
Ville Syrjäläb079bd172016-10-25 18:58:02 +0300606 ret = intel_modeset_init(dev);
607 if (ret)
608 goto cleanup_irq;
Chris Wilson0673ad42016-06-24 14:00:22 +0100609
Arkadiusz Hiler29ad6a32017-03-14 15:28:09 +0100610 intel_uc_init_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100611
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +0000612 ret = i915_gem_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100613 if (ret)
Oscar Mateo3950bf32017-03-22 10:39:46 -0700614 goto cleanup_uc;
Chris Wilson0673ad42016-06-24 14:00:22 +0100615
616 intel_modeset_gem_init(dev);
617
Tvrtko Ursulinb7f05d42016-11-09 11:30:45 +0000618 if (INTEL_INFO(dev_priv)->num_pipes == 0)
Chris Wilson0673ad42016-06-24 14:00:22 +0100619 return 0;
620
621 ret = intel_fbdev_init(dev);
622 if (ret)
623 goto cleanup_gem;
624
625 /* Only enable hotplug handling once the fbdev is fully set up. */
626 intel_hpd_init(dev_priv);
627
628 drm_kms_helper_poll_init(dev);
629
630 return 0;
631
632cleanup_gem:
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +0000633 if (i915_gem_suspend(dev_priv))
Imre Deak1c777c52016-10-12 17:46:37 +0300634 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
Chris Wilsonfbbd37b2016-10-28 13:58:42 +0100635 i915_gem_fini(dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -0700636cleanup_uc:
637 intel_uc_fini_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100638cleanup_irq:
Chris Wilson0673ad42016-06-24 14:00:22 +0100639 drm_irq_uninstall(dev);
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000640 intel_teardown_gmbus(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100641cleanup_csr:
642 intel_csr_ucode_fini(dev_priv);
643 intel_power_domains_fini(dev_priv);
David Weinehall52a05c32016-08-22 13:32:44 +0300644 vga_switcheroo_unregister_client(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +0100645cleanup_vga_client:
David Weinehall52a05c32016-08-22 13:32:44 +0300646 vga_client_register(pdev, NULL, NULL, NULL);
Chris Wilson0673ad42016-06-24 14:00:22 +0100647out:
648 return ret;
649}
650
Chris Wilson0673ad42016-06-24 14:00:22 +0100651static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
652{
653 struct apertures_struct *ap;
Chris Wilson91c8a322016-07-05 10:40:23 +0100654 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100655 struct i915_ggtt *ggtt = &dev_priv->ggtt;
656 bool primary;
657 int ret;
658
659 ap = alloc_apertures(1);
660 if (!ap)
661 return -ENOMEM;
662
663 ap->ranges[0].base = ggtt->mappable_base;
664 ap->ranges[0].size = ggtt->mappable_end;
665
666 primary =
667 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
668
Daniel Vetter44adece2016-08-10 18:52:34 +0200669 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
Chris Wilson0673ad42016-06-24 14:00:22 +0100670
671 kfree(ap);
672
673 return ret;
674}
Chris Wilson0673ad42016-06-24 14:00:22 +0100675
676#if !defined(CONFIG_VGA_CONSOLE)
677static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
678{
679 return 0;
680}
681#elif !defined(CONFIG_DUMMY_CONSOLE)
682static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
683{
684 return -ENODEV;
685}
686#else
687static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
688{
689 int ret = 0;
690
691 DRM_INFO("Replacing VGA console driver\n");
692
693 console_lock();
694 if (con_is_bound(&vga_con))
695 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
696 if (ret == 0) {
697 ret = do_unregister_con_driver(&vga_con);
698
699 /* Ignore "already unregistered". */
700 if (ret == -ENODEV)
701 ret = 0;
702 }
703 console_unlock();
704
705 return ret;
706}
707#endif
708
Chris Wilson0673ad42016-06-24 14:00:22 +0100709static void intel_init_dpio(struct drm_i915_private *dev_priv)
710{
711 /*
712 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
713 * CHV x1 PHY (DP/HDMI D)
714 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
715 */
716 if (IS_CHERRYVIEW(dev_priv)) {
717 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
718 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
719 } else if (IS_VALLEYVIEW(dev_priv)) {
720 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
721 }
722}
723
724static int i915_workqueues_init(struct drm_i915_private *dev_priv)
725{
726 /*
727 * The i915 workqueue is primarily used for batched retirement of
728 * requests (and thus managing bo) once the task has been completed
729 * by the GPU. i915_gem_retire_requests() is called directly when we
730 * need high-priority retirement, such as waiting for an explicit
731 * bo.
732 *
733 * It is also used for periodic low-priority events, such as
734 * idle-timers and recording error state.
735 *
736 * All tasks on the workqueue are expected to acquire the dev mutex
737 * so there is no point in running more than one instance of the
738 * workqueue at any time. Use an ordered one.
739 */
740 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
741 if (dev_priv->wq == NULL)
742 goto out_err;
743
744 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
745 if (dev_priv->hotplug.dp_wq == NULL)
746 goto out_free_wq;
747
Chris Wilson0673ad42016-06-24 14:00:22 +0100748 return 0;
749
Chris Wilson0673ad42016-06-24 14:00:22 +0100750out_free_wq:
751 destroy_workqueue(dev_priv->wq);
752out_err:
753 DRM_ERROR("Failed to allocate workqueues.\n");
754
755 return -ENOMEM;
756}
757
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000758static void i915_engines_cleanup(struct drm_i915_private *i915)
759{
760 struct intel_engine_cs *engine;
761 enum intel_engine_id id;
762
763 for_each_engine(engine, i915, id)
764 kfree(engine);
765}
766
Chris Wilson0673ad42016-06-24 14:00:22 +0100767static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
768{
Chris Wilson0673ad42016-06-24 14:00:22 +0100769 destroy_workqueue(dev_priv->hotplug.dp_wq);
770 destroy_workqueue(dev_priv->wq);
771}
772
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300773/*
774 * We don't keep the workarounds for pre-production hardware, so we expect our
775 * driver to fail on these machines in one way or another. A little warning on
776 * dmesg may help both the user and the bug triagers.
777 */
778static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
779{
Chris Wilson248a1242017-01-30 10:44:56 +0000780 bool pre = false;
781
782 pre |= IS_HSW_EARLY_SDV(dev_priv);
783 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
Chris Wilson0102ba12017-01-30 10:44:58 +0000784 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
Chris Wilson248a1242017-01-30 10:44:56 +0000785
Chris Wilson7c5ff4a2017-01-30 10:44:57 +0000786 if (pre) {
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300787 DRM_ERROR("This is a pre-production stepping. "
788 "It may not be fully functional.\n");
Chris Wilson7c5ff4a2017-01-30 10:44:57 +0000789 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
790 }
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300791}
792
Chris Wilson0673ad42016-06-24 14:00:22 +0100793/**
794 * i915_driver_init_early - setup state not requiring device access
795 * @dev_priv: device private
796 *
797 * Initialize everything that is a "SW-only" state, that is state not
798 * requiring accessing the device or exposing the driver via kernel internal
799 * or userspace interfaces. Example steps belonging here: lock initialization,
800 * system memory allocation, setting up device specific attributes and
801 * function hooks not requiring accessing the device.
802 */
803static int i915_driver_init_early(struct drm_i915_private *dev_priv,
804 const struct pci_device_id *ent)
805{
806 const struct intel_device_info *match_info =
807 (struct intel_device_info *)ent->driver_data;
808 struct intel_device_info *device_info;
809 int ret = 0;
810
811 if (i915_inject_load_failure())
812 return -ENODEV;
813
814 /* Setup the write-once "constant" device info */
Chris Wilson94b4f3b2016-07-05 10:40:20 +0100815 device_info = mkwrite_device_info(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100816 memcpy(device_info, match_info, sizeof(*device_info));
817 device_info->device_id = dev_priv->drm.pdev->device;
818
819 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
820 device_info->gen_mask = BIT(device_info->gen - 1);
821
822 spin_lock_init(&dev_priv->irq_lock);
823 spin_lock_init(&dev_priv->gpu_error.lock);
824 mutex_init(&dev_priv->backlight_lock);
825 spin_lock_init(&dev_priv->uncore.lock);
Lyude317eaa92017-02-03 21:18:25 -0500826
Chris Wilson0673ad42016-06-24 14:00:22 +0100827 spin_lock_init(&dev_priv->mm.object_stat_lock);
828 spin_lock_init(&dev_priv->mmio_flip_lock);
829 mutex_init(&dev_priv->sb_lock);
830 mutex_init(&dev_priv->modeset_restore_lock);
831 mutex_init(&dev_priv->av_mutex);
832 mutex_init(&dev_priv->wm.wm_mutex);
833 mutex_init(&dev_priv->pps_mutex);
834
Arkadiusz Hiler413e8fd2016-11-25 18:59:36 +0100835 intel_uc_init_early(dev_priv);
Chris Wilson0b1de5d2016-08-12 12:39:59 +0100836 i915_memcpy_init_early(dev_priv);
837
Chris Wilson0673ad42016-06-24 14:00:22 +0100838 ret = i915_workqueues_init(dev_priv);
839 if (ret < 0)
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000840 goto err_engines;
Chris Wilson0673ad42016-06-24 14:00:22 +0100841
Chris Wilson0673ad42016-06-24 14:00:22 +0100842 /* This must be called before any calls to HAS_PCH_* */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000843 intel_detect_pch(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100844
Tvrtko Ursulin192aa182016-12-01 14:16:45 +0000845 intel_pm_setup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100846 intel_init_dpio(dev_priv);
847 intel_power_domains_init(dev_priv);
848 intel_irq_init(dev_priv);
Mika Kuoppala3ac168a2016-11-01 18:43:03 +0200849 intel_hangcheck_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100850 intel_init_display_hooks(dev_priv);
851 intel_init_clock_gating_hooks(dev_priv);
852 intel_init_audio_hooks(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000853 ret = i915_gem_load_init(dev_priv);
Chris Wilson73cb9702016-10-28 13:58:46 +0100854 if (ret < 0)
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300855 goto err_irq;
Chris Wilson0673ad42016-06-24 14:00:22 +0100856
David Weinehall36cdd012016-08-22 13:59:31 +0300857 intel_display_crc_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100858
Chris Wilson94b4f3b2016-07-05 10:40:20 +0100859 intel_device_info_dump(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100860
Paulo Zanoni4fc7e842016-09-26 15:07:52 +0300861 intel_detect_preproduction_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100862
Robert Braggeec688e2016-11-07 19:49:47 +0000863 i915_perf_init(dev_priv);
864
Chris Wilson0673ad42016-06-24 14:00:22 +0100865 return 0;
866
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300867err_irq:
868 intel_irq_fini(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100869 i915_workqueues_cleanup(dev_priv);
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000870err_engines:
871 i915_engines_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100872 return ret;
873}
874
875/**
876 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
877 * @dev_priv: device private
878 */
879static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
880{
Robert Braggeec688e2016-11-07 19:49:47 +0000881 i915_perf_fini(dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +0000882 i915_gem_load_cleanup(dev_priv);
Joonas Lahtinencefcff82017-04-28 10:58:39 +0300883 intel_irq_fini(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100884 i915_workqueues_cleanup(dev_priv);
Chris Wilsonbb8f0f52017-01-24 11:01:34 +0000885 i915_engines_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100886}
887
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000888static int i915_mmio_setup(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100889{
David Weinehall52a05c32016-08-22 13:32:44 +0300890 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100891 int mmio_bar;
892 int mmio_size;
893
Tvrtko Ursulin5db94012016-10-13 11:03:10 +0100894 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
Chris Wilson0673ad42016-06-24 14:00:22 +0100895 /*
896 * Before gen4, the registers and the GTT are behind different BARs.
897 * However, from gen4 onwards, the registers and the GTT are shared
898 * in the same BAR, so we want to restrict this ioremap from
899 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
900 * the register BAR remains the same size for all the earlier
901 * generations up to Ironlake.
902 */
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +0000903 if (INTEL_GEN(dev_priv) < 5)
Chris Wilson0673ad42016-06-24 14:00:22 +0100904 mmio_size = 512 * 1024;
905 else
906 mmio_size = 2 * 1024 * 1024;
David Weinehall52a05c32016-08-22 13:32:44 +0300907 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
Chris Wilson0673ad42016-06-24 14:00:22 +0100908 if (dev_priv->regs == NULL) {
909 DRM_ERROR("failed to map registers\n");
910
911 return -EIO;
912 }
913
914 /* Try to make sure MCHBAR is enabled before poking at it */
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000915 intel_setup_mchbar(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100916
917 return 0;
918}
919
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000920static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
Chris Wilson0673ad42016-06-24 14:00:22 +0100921{
David Weinehall52a05c32016-08-22 13:32:44 +0300922 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +0100923
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000924 intel_teardown_mchbar(dev_priv);
David Weinehall52a05c32016-08-22 13:32:44 +0300925 pci_iounmap(pdev, dev_priv->regs);
Chris Wilson0673ad42016-06-24 14:00:22 +0100926}
927
928/**
929 * i915_driver_init_mmio - setup device MMIO
930 * @dev_priv: device private
931 *
932 * Setup minimal device state necessary for MMIO accesses later in the
933 * initialization sequence. The setup here should avoid any other device-wide
934 * side effects or exposing the driver via kernel internal or user space
935 * interfaces.
936 */
937static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
938{
Chris Wilson0673ad42016-06-24 14:00:22 +0100939 int ret;
940
941 if (i915_inject_load_failure())
942 return -ENODEV;
943
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000944 if (i915_get_bridge_dev(dev_priv))
Chris Wilson0673ad42016-06-24 14:00:22 +0100945 return -EIO;
946
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000947 ret = i915_mmio_setup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100948 if (ret < 0)
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +0300949 goto err_bridge;
Chris Wilson0673ad42016-06-24 14:00:22 +0100950
951 intel_uncore_init(dev_priv);
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +0300952
953 ret = intel_engines_init_mmio(dev_priv);
954 if (ret)
955 goto err_uncore;
956
Chris Wilson24145512017-01-24 11:01:35 +0000957 i915_gem_init_mmio(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100958
959 return 0;
960
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +0300961err_uncore:
962 intel_uncore_fini(dev_priv);
963err_bridge:
Chris Wilson0673ad42016-06-24 14:00:22 +0100964 pci_dev_put(dev_priv->bridge_dev);
965
966 return ret;
967}
968
969/**
970 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
971 * @dev_priv: device private
972 */
973static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
974{
Chris Wilson0673ad42016-06-24 14:00:22 +0100975 intel_uncore_fini(dev_priv);
Tvrtko Ursulinda5f53b2016-12-01 14:16:40 +0000976 i915_mmio_cleanup(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +0100977 pci_dev_put(dev_priv->bridge_dev);
978}
979
Chris Wilson94b4f3b2016-07-05 10:40:20 +0100980static void intel_sanitize_options(struct drm_i915_private *dev_priv)
981{
982 i915.enable_execlists =
983 intel_sanitize_enable_execlists(dev_priv,
984 i915.enable_execlists);
985
986 /*
987 * i915.enable_ppgtt is read-only, so do an early pass to validate the
988 * user's requested state against the hardware/driver capabilities. We
989 * do this now so that we can print out any log messages once rather
990 * than every time we check intel_enable_ppgtt().
991 */
992 i915.enable_ppgtt =
993 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
994 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
Chris Wilson39df9192016-07-20 13:31:57 +0100995
996 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
Tvrtko Ursulin784f2f12017-02-20 10:46:57 +0000997 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
Arkadiusz Hilerd2be9f22017-03-14 15:28:10 +0100998
999 intel_uc_sanitize_options(dev_priv);
Chuanxiao Dong67b7f332017-05-27 17:44:17 +08001000
1001 intel_gvt_sanitize_options(dev_priv);
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001002}
1003
Chris Wilson0673ad42016-06-24 14:00:22 +01001004/**
1005 * i915_driver_init_hw - setup state requiring device access
1006 * @dev_priv: device private
1007 *
1008 * Setup state that requires accessing the device, but doesn't require
1009 * exposing the driver via kernel internal or userspace interfaces.
1010 */
1011static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1012{
David Weinehall52a05c32016-08-22 13:32:44 +03001013 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001014 int ret;
1015
1016 if (i915_inject_load_failure())
1017 return -ENODEV;
1018
Chris Wilson94b4f3b2016-07-05 10:40:20 +01001019 intel_device_info_runtime_init(dev_priv);
1020
1021 intel_sanitize_options(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001022
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001023 ret = i915_ggtt_probe_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001024 if (ret)
1025 return ret;
1026
Chris Wilson0673ad42016-06-24 14:00:22 +01001027 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1028 * otherwise the vga fbdev driver falls over. */
1029 ret = i915_kick_out_firmware_fb(dev_priv);
1030 if (ret) {
1031 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1032 goto out_ggtt;
1033 }
1034
1035 ret = i915_kick_out_vgacon(dev_priv);
1036 if (ret) {
1037 DRM_ERROR("failed to remove conflicting VGA console\n");
1038 goto out_ggtt;
1039 }
1040
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001041 ret = i915_ggtt_init_hw(dev_priv);
Chris Wilson0088e522016-08-04 07:52:21 +01001042 if (ret)
1043 return ret;
1044
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001045 ret = i915_ggtt_enable_hw(dev_priv);
Chris Wilson0088e522016-08-04 07:52:21 +01001046 if (ret) {
1047 DRM_ERROR("failed to enable GGTT\n");
1048 goto out_ggtt;
1049 }
1050
David Weinehall52a05c32016-08-22 13:32:44 +03001051 pci_set_master(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001052
1053 /* overlay on gen2 is broken and can't address above 1G */
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01001054 if (IS_GEN2(dev_priv)) {
David Weinehall52a05c32016-08-22 13:32:44 +03001055 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
Chris Wilson0673ad42016-06-24 14:00:22 +01001056 if (ret) {
1057 DRM_ERROR("failed to set DMA mask\n");
1058
1059 goto out_ggtt;
1060 }
1061 }
1062
Chris Wilson0673ad42016-06-24 14:00:22 +01001063 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1064 * using 32bit addressing, overwriting memory if HWS is located
1065 * above 4GB.
1066 *
1067 * The documentation also mentions an issue with undefined
1068 * behaviour if any general state is accessed within a page above 4GB,
1069 * which also needs to be handled carefully.
1070 */
Jani Nikulac0f86832016-12-07 12:13:04 +02001071 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
David Weinehall52a05c32016-08-22 13:32:44 +03001072 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
Chris Wilson0673ad42016-06-24 14:00:22 +01001073
1074 if (ret) {
1075 DRM_ERROR("failed to set DMA mask\n");
1076
1077 goto out_ggtt;
1078 }
1079 }
1080
Chris Wilson0673ad42016-06-24 14:00:22 +01001081 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1082 PM_QOS_DEFAULT_VALUE);
1083
1084 intel_uncore_sanitize(dev_priv);
1085
1086 intel_opregion_setup(dev_priv);
1087
1088 i915_gem_load_init_fences(dev_priv);
1089
1090 /* On the 945G/GM, the chipset reports the MSI capability on the
1091 * integrated graphics even though the support isn't actually there
1092 * according to the published specs. It doesn't appear to function
1093 * correctly in testing on 945G.
1094 * This may be a side effect of MSI having been made available for PEG
1095 * and the registers being closely associated.
1096 *
1097 * According to chipset errata, on the 965GM, MSI interrupts may
1098 * be lost or delayed, but we use them anyways to avoid
1099 * stuck interrupts on some machines.
1100 */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01001101 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
David Weinehall52a05c32016-08-22 13:32:44 +03001102 if (pci_enable_msi(pdev) < 0)
Chris Wilson0673ad42016-06-24 14:00:22 +01001103 DRM_DEBUG_DRIVER("can't enable MSI");
1104 }
1105
Zhenyu Wang26f837e2017-01-13 10:46:09 +08001106 ret = intel_gvt_init(dev_priv);
1107 if (ret)
1108 goto out_ggtt;
1109
Chris Wilson0673ad42016-06-24 14:00:22 +01001110 return 0;
1111
1112out_ggtt:
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001113 i915_ggtt_cleanup_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001114
1115 return ret;
1116}
1117
1118/**
1119 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1120 * @dev_priv: device private
1121 */
1122static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1123{
David Weinehall52a05c32016-08-22 13:32:44 +03001124 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001125
David Weinehall52a05c32016-08-22 13:32:44 +03001126 if (pdev->msi_enabled)
1127 pci_disable_msi(pdev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001128
1129 pm_qos_remove_request(&dev_priv->pm_qos);
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001130 i915_ggtt_cleanup_hw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001131}
1132
1133/**
1134 * i915_driver_register - register the driver with the rest of the system
1135 * @dev_priv: device private
1136 *
1137 * Perform any steps necessary to make the driver available via kernel
1138 * internal or userspace interfaces.
1139 */
1140static void i915_driver_register(struct drm_i915_private *dev_priv)
1141{
Chris Wilson91c8a322016-07-05 10:40:23 +01001142 struct drm_device *dev = &dev_priv->drm;
Chris Wilson0673ad42016-06-24 14:00:22 +01001143
1144 i915_gem_shrinker_init(dev_priv);
1145
1146 /*
1147 * Notify a valid surface after modesetting,
1148 * when running inside a VM.
1149 */
1150 if (intel_vgpu_active(dev_priv))
1151 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1152
1153 /* Reveal our presence to userspace */
1154 if (drm_dev_register(dev, 0) == 0) {
1155 i915_debugfs_register(dev_priv);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +00001156 i915_guc_log_register(dev_priv);
David Weinehall694c2822016-08-22 13:32:43 +03001157 i915_setup_sysfs(dev_priv);
Robert Bragg442b8c02016-11-07 19:49:53 +00001158
1159 /* Depends on sysfs having been initialized */
1160 i915_perf_register(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001161 } else
1162 DRM_ERROR("Failed to register driver for userspace access!\n");
1163
1164 if (INTEL_INFO(dev_priv)->num_pipes) {
1165 /* Must be done after probing outputs */
1166 intel_opregion_register(dev_priv);
1167 acpi_video_register();
1168 }
1169
1170 if (IS_GEN5(dev_priv))
1171 intel_gpu_ips_init(dev_priv);
1172
Jerome Anandeef57322017-01-25 04:27:49 +05301173 intel_audio_init(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001174
1175 /*
1176 * Some ports require correctly set-up hpd registers for detection to
1177 * work properly (leading to ghost connected connector status), e.g. VGA
1178 * on gm45. Hence we can only set up the initial fbdev config after hpd
1179 * irqs are fully enabled. We do it last so that the async config
1180 * cannot run before the connectors are registered.
1181 */
1182 intel_fbdev_initial_config_async(dev);
1183}
1184
1185/**
1186 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1187 * @dev_priv: device private
1188 */
1189static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1190{
Jerome Anandeef57322017-01-25 04:27:49 +05301191 intel_audio_deinit(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001192
1193 intel_gpu_ips_teardown();
1194 acpi_video_unregister();
1195 intel_opregion_unregister(dev_priv);
1196
Robert Bragg442b8c02016-11-07 19:49:53 +00001197 i915_perf_unregister(dev_priv);
1198
David Weinehall694c2822016-08-22 13:32:43 +03001199 i915_teardown_sysfs(dev_priv);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +00001200 i915_guc_log_unregister(dev_priv);
Chris Wilson91c8a322016-07-05 10:40:23 +01001201 drm_dev_unregister(&dev_priv->drm);
Chris Wilson0673ad42016-06-24 14:00:22 +01001202
1203 i915_gem_shrinker_cleanup(dev_priv);
1204}
1205
1206/**
1207 * i915_driver_load - setup chip and create an initial config
Joonas Lahtinend2ad3ae2016-11-10 15:36:34 +02001208 * @pdev: PCI device
1209 * @ent: matching PCI ID entry
Chris Wilson0673ad42016-06-24 14:00:22 +01001210 *
1211 * The driver load routine has to do several things:
1212 * - drive output discovery via intel_modeset_init()
1213 * - initialize the memory manager
1214 * - allocate initial config memory
1215 * - setup the DRM framebuffer with the allocated memory
1216 */
Chris Wilson42f55512016-06-24 14:00:26 +01001217int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
Chris Wilson0673ad42016-06-24 14:00:22 +01001218{
Maarten Lankhorst8d2b47d2017-02-02 08:41:42 +01001219 const struct intel_device_info *match_info =
1220 (struct intel_device_info *)ent->driver_data;
Chris Wilson0673ad42016-06-24 14:00:22 +01001221 struct drm_i915_private *dev_priv;
1222 int ret;
1223
Ville Syrjäläff4c3b72017-03-03 17:19:28 +02001224 /* Enable nuclear pageflip on ILK+ */
1225 if (!i915.nuclear_pageflip && match_info->gen < 5)
Maarten Lankhorst8d2b47d2017-02-02 08:41:42 +01001226 driver.driver_features &= ~DRIVER_ATOMIC;
Chris Wilsona09d0ba2016-06-24 14:00:27 +01001227
Chris Wilson0673ad42016-06-24 14:00:22 +01001228 ret = -ENOMEM;
1229 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1230 if (dev_priv)
1231 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1232 if (ret) {
Tvrtko Ursulin87a67522016-12-06 19:04:13 +00001233 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
Chris Wilsoncad36882017-02-10 16:35:21 +00001234 goto out_free;
Chris Wilson0673ad42016-06-24 14:00:22 +01001235 }
1236
Chris Wilson0673ad42016-06-24 14:00:22 +01001237 dev_priv->drm.pdev = pdev;
1238 dev_priv->drm.dev_private = dev_priv;
Chris Wilson0673ad42016-06-24 14:00:22 +01001239
1240 ret = pci_enable_device(pdev);
1241 if (ret)
Chris Wilsoncad36882017-02-10 16:35:21 +00001242 goto out_fini;
Chris Wilson0673ad42016-06-24 14:00:22 +01001243
1244 pci_set_drvdata(pdev, &dev_priv->drm);
1245
1246 ret = i915_driver_init_early(dev_priv, ent);
1247 if (ret < 0)
1248 goto out_pci_disable;
1249
1250 intel_runtime_pm_get(dev_priv);
1251
1252 ret = i915_driver_init_mmio(dev_priv);
1253 if (ret < 0)
1254 goto out_runtime_pm_put;
1255
1256 ret = i915_driver_init_hw(dev_priv);
1257 if (ret < 0)
1258 goto out_cleanup_mmio;
1259
1260 /*
1261 * TODO: move the vblank init and parts of modeset init steps into one
1262 * of the i915_driver_init_/i915_driver_register functions according
1263 * to the role/effect of the given init step.
1264 */
1265 if (INTEL_INFO(dev_priv)->num_pipes) {
Chris Wilson91c8a322016-07-05 10:40:23 +01001266 ret = drm_vblank_init(&dev_priv->drm,
Chris Wilson0673ad42016-06-24 14:00:22 +01001267 INTEL_INFO(dev_priv)->num_pipes);
1268 if (ret)
1269 goto out_cleanup_hw;
1270 }
1271
Chris Wilson91c8a322016-07-05 10:40:23 +01001272 ret = i915_load_modeset_init(&dev_priv->drm);
Chris Wilson0673ad42016-06-24 14:00:22 +01001273 if (ret < 0)
1274 goto out_cleanup_vblank;
1275
1276 i915_driver_register(dev_priv);
1277
1278 intel_runtime_pm_enable(dev_priv);
1279
Mahesh Kumara3a89862016-12-01 21:19:34 +05301280 dev_priv->ipc_enabled = false;
1281
Chris Wilson0525a062016-10-14 14:27:07 +01001282 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1283 DRM_INFO("DRM_I915_DEBUG enabled\n");
1284 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1285 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
Chris Wilsonbc5ca472016-08-25 08:23:14 +01001286
Chris Wilson0673ad42016-06-24 14:00:22 +01001287 intel_runtime_pm_put(dev_priv);
1288
1289 return 0;
1290
1291out_cleanup_vblank:
Chris Wilson91c8a322016-07-05 10:40:23 +01001292 drm_vblank_cleanup(&dev_priv->drm);
Chris Wilson0673ad42016-06-24 14:00:22 +01001293out_cleanup_hw:
1294 i915_driver_cleanup_hw(dev_priv);
1295out_cleanup_mmio:
1296 i915_driver_cleanup_mmio(dev_priv);
1297out_runtime_pm_put:
1298 intel_runtime_pm_put(dev_priv);
1299 i915_driver_cleanup_early(dev_priv);
1300out_pci_disable:
1301 pci_disable_device(pdev);
Chris Wilsoncad36882017-02-10 16:35:21 +00001302out_fini:
Chris Wilson0673ad42016-06-24 14:00:22 +01001303 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
Chris Wilsoncad36882017-02-10 16:35:21 +00001304 drm_dev_fini(&dev_priv->drm);
1305out_free:
1306 kfree(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001307 return ret;
1308}
1309
Chris Wilson42f55512016-06-24 14:00:26 +01001310void i915_driver_unload(struct drm_device *dev)
Chris Wilson0673ad42016-06-24 14:00:22 +01001311{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001312 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001313 struct pci_dev *pdev = dev_priv->drm.pdev;
Chris Wilson0673ad42016-06-24 14:00:22 +01001314
1315 intel_fbdev_fini(dev);
1316
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001317 if (i915_gem_suspend(dev_priv))
Chris Wilson42f55512016-06-24 14:00:26 +01001318 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
Chris Wilson0673ad42016-06-24 14:00:22 +01001319
1320 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1321
Daniel Vetter18dddad2017-03-21 17:41:49 +01001322 drm_atomic_helper_shutdown(dev);
Maarten Lankhorsta667fb42016-12-15 15:29:44 +01001323
Zhenyu Wang26f837e2017-01-13 10:46:09 +08001324 intel_gvt_cleanup(dev_priv);
1325
Chris Wilson0673ad42016-06-24 14:00:22 +01001326 i915_driver_unregister(dev_priv);
1327
1328 drm_vblank_cleanup(dev);
1329
1330 intel_modeset_cleanup(dev);
1331
1332 /*
1333 * free the memory space allocated for the child device
1334 * config parsed from VBT
1335 */
1336 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1337 kfree(dev_priv->vbt.child_dev);
1338 dev_priv->vbt.child_dev = NULL;
1339 dev_priv->vbt.child_dev_num = 0;
1340 }
1341 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1342 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1343 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1344 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1345
David Weinehall52a05c32016-08-22 13:32:44 +03001346 vga_switcheroo_unregister_client(pdev);
1347 vga_client_register(pdev, NULL, NULL, NULL);
Chris Wilson0673ad42016-06-24 14:00:22 +01001348
1349 intel_csr_ucode_fini(dev_priv);
1350
1351 /* Free error state after interrupts are fully disabled. */
1352 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
Chris Wilson5a4c6f12017-02-14 16:46:11 +00001353 i915_reset_error_state(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001354
1355 /* Flush any outstanding unpin_work. */
Chris Wilsonb7137e02016-07-13 09:10:37 +01001356 drain_workqueue(dev_priv->wq);
Chris Wilson0673ad42016-06-24 14:00:22 +01001357
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01001358 i915_gem_fini(dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -07001359 intel_uc_fini_fw(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001360 intel_fbc_cleanup_cfb(dev_priv);
1361
1362 intel_power_domains_fini(dev_priv);
1363
1364 i915_driver_cleanup_hw(dev_priv);
1365 i915_driver_cleanup_mmio(dev_priv);
1366
1367 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
Chris Wilsoncad36882017-02-10 16:35:21 +00001368}
1369
1370static void i915_driver_release(struct drm_device *dev)
1371{
1372 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson0673ad42016-06-24 14:00:22 +01001373
1374 i915_driver_cleanup_early(dev_priv);
Chris Wilsoncad36882017-02-10 16:35:21 +00001375 drm_dev_fini(&dev_priv->drm);
1376
1377 kfree(dev_priv);
Chris Wilson0673ad42016-06-24 14:00:22 +01001378}
1379
1380static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1381{
1382 int ret;
1383
1384 ret = i915_gem_open(dev, file);
1385 if (ret)
1386 return ret;
1387
1388 return 0;
1389}
1390
1391/**
1392 * i915_driver_lastclose - clean up after all DRM clients have exited
1393 * @dev: DRM device
1394 *
1395 * Take care of cleaning up after all DRM clients have exited. In the
1396 * mode setting case, we want to restore the kernel's initial mode (just
1397 * in case the last client left us in a bad state).
1398 *
1399 * Additionally, in the non-mode setting case, we'll tear down the GTT
1400 * and DMA structures, since the kernel won't be using them, and clea
1401 * up any GEM state.
1402 */
1403static void i915_driver_lastclose(struct drm_device *dev)
1404{
1405 intel_fbdev_restore_mode(dev);
1406 vga_switcheroo_process_delayed_switch();
1407}
1408
Daniel Vetter7d2ec882017-03-08 15:12:45 +01001409static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
Chris Wilson0673ad42016-06-24 14:00:22 +01001410{
Daniel Vetter7d2ec882017-03-08 15:12:45 +01001411 struct drm_i915_file_private *file_priv = file->driver_priv;
1412
Chris Wilson0673ad42016-06-24 14:00:22 +01001413 mutex_lock(&dev->struct_mutex);
1414 i915_gem_context_close(dev, file);
1415 i915_gem_release(dev, file);
1416 mutex_unlock(&dev->struct_mutex);
Chris Wilson0673ad42016-06-24 14:00:22 +01001417
1418 kfree(file_priv);
1419}
1420
Imre Deak07f9cd02014-08-18 14:42:45 +03001421static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1422{
Chris Wilson91c8a322016-07-05 10:40:23 +01001423 struct drm_device *dev = &dev_priv->drm;
Jani Nikula19c80542015-12-16 12:48:16 +02001424 struct intel_encoder *encoder;
Imre Deak07f9cd02014-08-18 14:42:45 +03001425
1426 drm_modeset_lock_all(dev);
Jani Nikula19c80542015-12-16 12:48:16 +02001427 for_each_intel_encoder(dev, encoder)
1428 if (encoder->suspend)
1429 encoder->suspend(encoder);
Imre Deak07f9cd02014-08-18 14:42:45 +03001430 drm_modeset_unlock_all(dev);
1431}
1432
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001433static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1434 bool rpm_resume);
Imre Deak507e1262016-04-20 20:27:54 +03001435static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +05301436
Imre Deakbc872292015-11-18 17:32:30 +02001437static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1438{
1439#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1440 if (acpi_target_system_state() < ACPI_STATE_S3)
1441 return true;
1442#endif
1443 return false;
1444}
Sagar Kambleebc32822014-08-13 23:07:05 +05301445
Imre Deak5e365c32014-10-23 19:23:25 +03001446static int i915_drm_suspend(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001447{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001448 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001449 struct pci_dev *pdev = dev_priv->drm.pdev;
Jesse Barnese5747e32014-06-12 08:35:47 -07001450 pci_power_t opregion_target_state;
Daniel Vetterd5818932015-02-23 12:03:26 +01001451 int error;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +01001452
Zhang Ruib8efb172013-02-05 15:41:53 +08001453 /* ignore lid events during suspend */
1454 mutex_lock(&dev_priv->modeset_restore_lock);
1455 dev_priv->modeset_restore = MODESET_SUSPENDED;
1456 mutex_unlock(&dev_priv->modeset_restore_lock);
1457
Imre Deak1f814da2015-12-16 02:52:19 +02001458 disable_rpm_wakeref_asserts(dev_priv);
1459
Paulo Zanonic67a4702013-08-19 13:18:09 -03001460 /* We do a lot of poking in a lot of registers, make sure they work
1461 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +02001462 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -02001463
Dave Airlie5bcf7192010-12-07 09:20:40 +10001464 drm_kms_helper_poll_disable(dev);
1465
David Weinehall52a05c32016-08-22 13:32:44 +03001466 pci_save_state(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001467
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001468 error = i915_gem_suspend(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001469 if (error) {
David Weinehall52a05c32016-08-22 13:32:44 +03001470 dev_err(&pdev->dev,
Daniel Vetterd5818932015-02-23 12:03:26 +01001471 "GEM idle failed, resume might fail\n");
Imre Deak1f814da2015-12-16 02:52:19 +02001472 goto out;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001473 }
1474
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02001475 intel_display_suspend(dev);
Daniel Vetterd5818932015-02-23 12:03:26 +01001476
1477 intel_dp_mst_suspend(dev);
1478
1479 intel_runtime_pm_disable_interrupts(dev_priv);
1480 intel_hpd_cancel_work(dev_priv);
1481
1482 intel_suspend_encoders(dev_priv);
1483
Ville Syrjälä712bf362016-10-31 22:37:23 +02001484 intel_suspend_hw(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001485
Tvrtko Ursulin275a9912016-11-16 08:55:34 +00001486 i915_gem_suspend_gtt_mappings(dev_priv);
Ben Widawsky828c7902013-10-16 09:21:30 -07001487
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00001488 i915_save_state(dev_priv);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001489
Imre Deakbc872292015-11-18 17:32:30 +02001490 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001491 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
Jesse Barnese5747e32014-06-12 08:35:47 -07001492
Hans de Goede68f60942017-02-10 11:28:01 +01001493 intel_uncore_suspend(dev_priv);
Chris Wilson03d92e42016-05-23 15:08:10 +01001494 intel_opregion_unregister(dev_priv);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001495
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001496 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +01001497
Mika Kuoppala62d5d692014-02-25 17:11:28 +02001498 dev_priv->suspend_count++;
1499
Imre Deakf74ed082016-04-18 14:48:21 +03001500 intel_csr_ucode_suspend(dev_priv);
Imre Deakf514c2d2015-10-28 23:59:06 +02001501
Imre Deak1f814da2015-12-16 02:52:19 +02001502out:
1503 enable_rpm_wakeref_asserts(dev_priv);
1504
1505 return error;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001506}
1507
David Weinehallc49d13e2016-08-22 13:32:42 +03001508static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
Imre Deakc3c09c92014-10-23 19:23:15 +03001509{
David Weinehallc49d13e2016-08-22 13:32:42 +03001510 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001511 struct pci_dev *pdev = dev_priv->drm.pdev;
Imre Deakbc872292015-11-18 17:32:30 +02001512 bool fw_csr;
Imre Deakc3c09c92014-10-23 19:23:15 +03001513 int ret;
1514
Imre Deak1f814da2015-12-16 02:52:19 +02001515 disable_rpm_wakeref_asserts(dev_priv);
1516
Imre Deak4c494a52016-10-13 14:34:06 +03001517 intel_display_set_init_power(dev_priv, false);
1518
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001519 fw_csr = !IS_GEN9_LP(dev_priv) &&
Imre Deaka7c81252016-04-01 16:02:38 +03001520 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
Imre Deakbc872292015-11-18 17:32:30 +02001521 /*
1522 * In case of firmware assisted context save/restore don't manually
1523 * deinit the power domains. This also means the CSR/DMC firmware will
1524 * stay active, it will power down any HW resources as required and
1525 * also enable deeper system power states that would be blocked if the
1526 * firmware was inactive.
1527 */
1528 if (!fw_csr)
1529 intel_power_domains_suspend(dev_priv);
Imre Deak73dfc222015-11-17 17:33:53 +02001530
Imre Deak507e1262016-04-20 20:27:54 +03001531 ret = 0;
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001532 if (IS_GEN9_LP(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +03001533 bxt_enable_dc9(dev_priv);
Imre Deakb8aea3d12016-04-20 20:27:55 +03001534 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +03001535 hsw_enable_pc8(dev_priv);
1536 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1537 ret = vlv_suspend_complete(dev_priv);
Imre Deakc3c09c92014-10-23 19:23:15 +03001538
1539 if (ret) {
1540 DRM_ERROR("Suspend complete failed: %d\n", ret);
Imre Deakbc872292015-11-18 17:32:30 +02001541 if (!fw_csr)
1542 intel_power_domains_init_hw(dev_priv, true);
Imre Deakc3c09c92014-10-23 19:23:15 +03001543
Imre Deak1f814da2015-12-16 02:52:19 +02001544 goto out;
Imre Deakc3c09c92014-10-23 19:23:15 +03001545 }
1546
David Weinehall52a05c32016-08-22 13:32:44 +03001547 pci_disable_device(pdev);
Imre Deakab3be732015-03-02 13:04:41 +02001548 /*
Imre Deak54875572015-06-30 17:06:47 +03001549 * During hibernation on some platforms the BIOS may try to access
Imre Deakab3be732015-03-02 13:04:41 +02001550 * the device even though it's already in D3 and hang the machine. So
1551 * leave the device in D0 on those platforms and hope the BIOS will
Imre Deak54875572015-06-30 17:06:47 +03001552 * power down the device properly. The issue was seen on multiple old
1553 * GENs with different BIOS vendors, so having an explicit blacklist
1554 * is inpractical; apply the workaround on everything pre GEN6. The
1555 * platforms where the issue was seen:
1556 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1557 * Fujitsu FSC S7110
1558 * Acer Aspire 1830T
Imre Deakab3be732015-03-02 13:04:41 +02001559 */
Tvrtko Ursulin514e1d62016-11-04 14:42:48 +00001560 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
David Weinehall52a05c32016-08-22 13:32:44 +03001561 pci_set_power_state(pdev, PCI_D3hot);
Imre Deakc3c09c92014-10-23 19:23:15 +03001562
Imre Deakbc872292015-11-18 17:32:30 +02001563 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1564
Imre Deak1f814da2015-12-16 02:52:19 +02001565out:
1566 enable_rpm_wakeref_asserts(dev_priv);
1567
1568 return ret;
Imre Deakc3c09c92014-10-23 19:23:15 +03001569}
1570
Matthew Aulda9a251c2016-12-02 10:24:11 +00001571static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001572{
1573 int error;
1574
Chris Wilsonded8b072016-07-05 10:40:22 +01001575 if (!dev) {
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001576 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -07001577 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001578 return -ENODEV;
1579 }
1580
Imre Deak0b14cbd2014-09-10 18:16:55 +03001581 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1582 state.event != PM_EVENT_FREEZE))
1583 return -EINVAL;
Dave Airlie5bcf7192010-12-07 09:20:40 +10001584
1585 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1586 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +01001587
Imre Deak5e365c32014-10-23 19:23:25 +03001588 error = i915_drm_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001589 if (error)
1590 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001591
Imre Deakab3be732015-03-02 13:04:41 +02001592 return i915_drm_suspend_late(dev, false);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001593}
1594
Imre Deak5e365c32014-10-23 19:23:25 +03001595static int i915_drm_resume(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001596{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001597 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläac840ae2016-05-06 21:35:55 +03001598 int ret;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001599
Imre Deak1f814da2015-12-16 02:52:19 +02001600 disable_rpm_wakeref_asserts(dev_priv);
Chris Wilsonabc80ab2016-08-24 10:27:01 +01001601 intel_sanitize_gt_powersave(dev_priv);
Imre Deak1f814da2015-12-16 02:52:19 +02001602
Chris Wilson97d6d7a2016-08-04 07:52:22 +01001603 ret = i915_ggtt_enable_hw(dev_priv);
Ville Syrjäläac840ae2016-05-06 21:35:55 +03001604 if (ret)
1605 DRM_ERROR("failed to re-enable GGTT\n");
1606
Imre Deakf74ed082016-04-18 14:48:21 +03001607 intel_csr_ucode_resume(dev_priv);
1608
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001609 i915_gem_resume(dev_priv);
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -03001610
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00001611 i915_restore_state(dev_priv);
Imre Deak8090ba82016-08-10 14:07:33 +03001612 intel_pps_unlock_regs_wa(dev_priv);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001613 intel_opregion_setup(dev_priv);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +01001614
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02001615 intel_init_pch_refclk(dev_priv);
Chris Wilson1833b132012-05-09 11:56:28 +01001616
Peter Antoine364aece2015-05-11 08:50:45 +01001617 /*
1618 * Interrupts have to be enabled before any batches are run. If not the
1619 * GPU will hang. i915_gem_init_hw() will initiate batches to
1620 * update/restore the context.
1621 *
Imre Deak908764f2016-11-29 21:40:29 +02001622 * drm_mode_config_reset() needs AUX interrupts.
1623 *
Peter Antoine364aece2015-05-11 08:50:45 +01001624 * Modeset enabling in intel_modeset_init_hw() also needs working
1625 * interrupts.
1626 */
1627 intel_runtime_pm_enable_interrupts(dev_priv);
1628
Imre Deak908764f2016-11-29 21:40:29 +02001629 drm_mode_config_reset(dev);
1630
Daniel Vetterd5818932015-02-23 12:03:26 +01001631 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001632 if (i915_gem_init_hw(dev_priv)) {
Daniel Vetterd5818932015-02-23 12:03:26 +01001633 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
Chris Wilson821ed7d2016-09-09 14:11:53 +01001634 i915_gem_set_wedged(dev_priv);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08001635 }
Daniel Vetterd5818932015-02-23 12:03:26 +01001636 mutex_unlock(&dev->struct_mutex);
1637
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001638 intel_guc_resume(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07001639
Daniel Vetterd5818932015-02-23 12:03:26 +01001640 intel_modeset_init_hw(dev);
1641
1642 spin_lock_irq(&dev_priv->irq_lock);
1643 if (dev_priv->display.hpd_irq_setup)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001644 dev_priv->display.hpd_irq_setup(dev_priv);
Daniel Vetterd5818932015-02-23 12:03:26 +01001645 spin_unlock_irq(&dev_priv->irq_lock);
1646
Daniel Vetterd5818932015-02-23 12:03:26 +01001647 intel_dp_mst_resume(dev);
1648
Lyudea16b7652016-03-11 10:57:01 -05001649 intel_display_resume(dev);
1650
Lyudee0b70062016-11-01 21:06:30 -04001651 drm_kms_helper_poll_enable(dev);
1652
Daniel Vetterd5818932015-02-23 12:03:26 +01001653 /*
1654 * ... but also need to make sure that hotplug processing
1655 * doesn't cause havoc. Like in the driver load code we don't
1656 * bother with the tiny race here where we might loose hotplug
1657 * notifications.
1658 * */
1659 intel_hpd_init(dev_priv);
Jesse Barnes1daed3f2011-01-05 12:01:25 -08001660
Chris Wilson03d92e42016-05-23 15:08:10 +01001661 intel_opregion_register(dev_priv);
Chris Wilson44834a62010-08-19 16:09:23 +01001662
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001663 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -07001664
Zhang Ruib8efb172013-02-05 15:41:53 +08001665 mutex_lock(&dev_priv->modeset_restore_lock);
1666 dev_priv->modeset_restore = MODESET_DONE;
1667 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001668
Chris Wilson6f9f4b72016-05-23 15:08:09 +01001669 intel_opregion_notify_adapter(dev_priv, PCI_D0);
Jesse Barnese5747e32014-06-12 08:35:47 -07001670
Chris Wilson54b4f682016-07-21 21:16:19 +01001671 intel_autoenable_gt_powersave(dev_priv);
Imre Deakee6f2802014-10-23 19:23:22 +03001672
Imre Deak1f814da2015-12-16 02:52:19 +02001673 enable_rpm_wakeref_asserts(dev_priv);
1674
Chris Wilson074c6ad2014-04-09 09:19:43 +01001675 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001676}
1677
Imre Deak5e365c32014-10-23 19:23:25 +03001678static int i915_drm_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001679{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001680 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehall52a05c32016-08-22 13:32:44 +03001681 struct pci_dev *pdev = dev_priv->drm.pdev;
Imre Deak44410cd2016-04-18 14:45:54 +03001682 int ret;
Imre Deak36d61e62014-10-23 19:23:24 +03001683
Imre Deak76c4b252014-04-01 19:55:22 +03001684 /*
1685 * We have a resume ordering issue with the snd-hda driver also
1686 * requiring our device to be power up. Due to the lack of a
1687 * parent/child relationship we currently solve this with an early
1688 * resume hook.
1689 *
1690 * FIXME: This should be solved with a special hdmi sink device or
1691 * similar so that power domains can be employed.
1692 */
Imre Deak44410cd2016-04-18 14:45:54 +03001693
1694 /*
1695 * Note that we need to set the power state explicitly, since we
1696 * powered off the device during freeze and the PCI core won't power
1697 * it back up for us during thaw. Powering off the device during
1698 * freeze is not a hard requirement though, and during the
1699 * suspend/resume phases the PCI core makes sure we get here with the
1700 * device powered on. So in case we change our freeze logic and keep
1701 * the device powered we can also remove the following set power state
1702 * call.
1703 */
David Weinehall52a05c32016-08-22 13:32:44 +03001704 ret = pci_set_power_state(pdev, PCI_D0);
Imre Deak44410cd2016-04-18 14:45:54 +03001705 if (ret) {
1706 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1707 goto out;
1708 }
1709
1710 /*
1711 * Note that pci_enable_device() first enables any parent bridge
1712 * device and only then sets the power state for this device. The
1713 * bridge enabling is a nop though, since bridge devices are resumed
1714 * first. The order of enabling power and enabling the device is
1715 * imposed by the PCI core as described above, so here we preserve the
1716 * same order for the freeze/thaw phases.
1717 *
1718 * TODO: eventually we should remove pci_disable_device() /
1719 * pci_enable_enable_device() from suspend/resume. Due to how they
1720 * depend on the device enable refcount we can't anyway depend on them
1721 * disabling/enabling the device.
1722 */
David Weinehall52a05c32016-08-22 13:32:44 +03001723 if (pci_enable_device(pdev)) {
Imre Deakbc872292015-11-18 17:32:30 +02001724 ret = -EIO;
1725 goto out;
1726 }
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001727
David Weinehall52a05c32016-08-22 13:32:44 +03001728 pci_set_master(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001729
Imre Deak1f814da2015-12-16 02:52:19 +02001730 disable_rpm_wakeref_asserts(dev_priv);
1731
Wayne Boyer666a4532015-12-09 12:29:35 -08001732 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001733 ret = vlv_resume_prepare(dev_priv, false);
Imre Deak36d61e62014-10-23 19:23:24 +03001734 if (ret)
Damien Lespiauff0b1872015-05-20 14:45:15 +01001735 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1736 ret);
Imre Deak36d61e62014-10-23 19:23:24 +03001737
Hans de Goede68f60942017-02-10 11:28:01 +01001738 intel_uncore_resume_early(dev_priv);
Paulo Zanoniefee8332014-10-27 17:54:33 -02001739
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001740 if (IS_GEN9_LP(dev_priv)) {
Imre Deakda2f41d2016-04-20 20:27:56 +03001741 if (!dev_priv->suspended_to_idle)
1742 gen9_sanitize_dc_state(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03001743 bxt_disable_dc9(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +03001744 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Damien Lespiaua9a6b732015-05-20 14:45:14 +01001745 hsw_disable_pc8(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +03001746 }
Paulo Zanoniefee8332014-10-27 17:54:33 -02001747
Chris Wilsondc979972016-05-10 14:10:04 +01001748 intel_uncore_sanitize(dev_priv);
Imre Deakbc872292015-11-18 17:32:30 +02001749
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02001750 if (IS_GEN9_LP(dev_priv) ||
Imre Deaka7c81252016-04-01 16:02:38 +03001751 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
Imre Deakbc872292015-11-18 17:32:30 +02001752 intel_power_domains_init_hw(dev_priv, true);
1753
Chris Wilson24145512017-01-24 11:01:35 +00001754 i915_gem_sanitize(dev_priv);
1755
Imre Deak6e35e8a2016-04-18 10:04:19 +03001756 enable_rpm_wakeref_asserts(dev_priv);
1757
Imre Deakbc872292015-11-18 17:32:30 +02001758out:
1759 dev_priv->suspended_to_idle = false;
Imre Deak36d61e62014-10-23 19:23:24 +03001760
1761 return ret;
Imre Deak76c4b252014-04-01 19:55:22 +03001762}
1763
Tvrtko Ursulin7f26cb82016-12-01 14:16:41 +00001764static int i915_resume_switcheroo(struct drm_device *dev)
Imre Deak76c4b252014-04-01 19:55:22 +03001765{
Imre Deak50a00722014-10-23 19:23:17 +03001766 int ret;
Imre Deak76c4b252014-04-01 19:55:22 +03001767
Imre Deak097dd832014-10-23 19:23:19 +03001768 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1769 return 0;
1770
Imre Deak5e365c32014-10-23 19:23:25 +03001771 ret = i915_drm_resume_early(dev);
Imre Deak50a00722014-10-23 19:23:17 +03001772 if (ret)
1773 return ret;
1774
Imre Deak5a175142014-10-23 19:23:18 +03001775 return i915_drm_resume(dev);
1776}
1777
Ben Gamari11ed50e2009-09-14 17:48:45 -04001778/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -02001779 * i915_reset - reset chip after a hang
Michel Thierrydf210572017-01-11 20:18:09 -08001780 * @dev_priv: device private to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -04001781 *
Chris Wilson780f2622016-09-09 14:11:52 +01001782 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1783 * on failure.
Ben Gamari11ed50e2009-09-14 17:48:45 -04001784 *
Chris Wilson221fe792016-09-09 14:11:51 +01001785 * Caller must hold the struct_mutex.
1786 *
Ben Gamari11ed50e2009-09-14 17:48:45 -04001787 * Procedure is fairly simple:
1788 * - reset the chip using the reset reg
1789 * - re-init context state
1790 * - re-init hardware status page
1791 * - re-init ring buffer
1792 * - re-init interrupt state
1793 * - re-init display
1794 */
Chris Wilson780f2622016-09-09 14:11:52 +01001795void i915_reset(struct drm_i915_private *dev_priv)
Ben Gamari11ed50e2009-09-14 17:48:45 -04001796{
Chris Wilsond98c52c2016-04-13 17:35:05 +01001797 struct i915_gpu_error *error = &dev_priv->gpu_error;
Kenneth Graunke0573ed42010-09-11 03:17:19 -07001798 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001799
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001800 lockdep_assert_held(&dev_priv->drm.struct_mutex);
Chris Wilson8c185ec2017-03-16 17:13:02 +00001801 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
Chris Wilson221fe792016-09-09 14:11:51 +01001802
Chris Wilson8c185ec2017-03-16 17:13:02 +00001803 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
Chris Wilson780f2622016-09-09 14:11:52 +01001804 return;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001805
Chris Wilsond98c52c2016-04-13 17:35:05 +01001806 /* Clear any previous failed attempts at recovery. Time to try again. */
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001807 if (!i915_gem_unset_wedged(dev_priv))
1808 goto wakeup;
1809
Chris Wilson8af29b02016-09-09 14:11:47 +01001810 error->reset_count++;
Chris Wilsond98c52c2016-04-13 17:35:05 +01001811
Chris Wilson7b4d3a12016-07-04 08:08:37 +01001812 pr_notice("drm/i915: Resetting chip after gpu hang\n");
Chris Wilson4c965542017-01-17 17:59:01 +02001813 disable_irq(dev_priv->drm.irq);
Chris Wilson0e178ae2017-01-17 17:59:06 +02001814 ret = i915_gem_reset_prepare(dev_priv);
1815 if (ret) {
1816 DRM_ERROR("GPU recovery failed\n");
1817 intel_gpu_reset(dev_priv, ALL_ENGINES);
1818 goto error;
1819 }
Chris Wilson9e60ab02016-10-04 21:11:28 +01001820
Chris Wilsondc979972016-05-10 14:10:04 +01001821 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
Kenneth Graunke0573ed42010-09-11 03:17:19 -07001822 if (ret) {
Chris Wilson804e59a2016-04-13 17:35:09 +01001823 if (ret != -ENODEV)
1824 DRM_ERROR("Failed to reset chip: %i\n", ret);
1825 else
1826 DRM_DEBUG_DRIVER("GPU reset disabled\n");
Chris Wilsond98c52c2016-04-13 17:35:05 +01001827 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001828 }
1829
Chris Wilsond8027092017-02-08 14:30:32 +00001830 i915_gem_reset(dev_priv);
Ville Syrjälä1362b772014-11-26 17:07:29 +02001831 intel_overlay_reset(dev_priv);
1832
Ben Gamari11ed50e2009-09-14 17:48:45 -04001833 /* Ok, now get things going again... */
1834
1835 /*
1836 * Everything depends on having the GTT running, so we need to start
1837 * there. Fortunately we don't need to do this unless we reset the
1838 * chip at a PCI level.
1839 *
1840 * Next we need to restore the context, but we don't use those
1841 * yet either...
1842 *
1843 * Ring buffer needs to be re-initialized in the KMS case, or if X
1844 * was running at the time of the reset (i.e. we weren't VT
1845 * switched away).
1846 */
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00001847 ret = i915_gem_init_hw(dev_priv);
Daniel Vetter33d30a92015-02-23 12:03:27 +01001848 if (ret) {
1849 DRM_ERROR("Failed hw init on reset %d\n", ret);
Chris Wilsond98c52c2016-04-13 17:35:05 +01001850 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001851 }
1852
Chris Wilsonc2a126a2016-11-22 14:41:19 +00001853 i915_queue_hangcheck(dev_priv);
1854
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001855finish:
Chris Wilson8d613c52017-02-12 17:19:59 +00001856 i915_gem_reset_finish(dev_priv);
Chris Wilson4c965542017-01-17 17:59:01 +02001857 enable_irq(dev_priv->drm.irq);
Chris Wilson8c185ec2017-03-16 17:13:02 +00001858
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001859wakeup:
Chris Wilson8c185ec2017-03-16 17:13:02 +00001860 clear_bit(I915_RESET_HANDOFF, &error->flags);
1861 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
Chris Wilson780f2622016-09-09 14:11:52 +01001862 return;
Chris Wilsond98c52c2016-04-13 17:35:05 +01001863
1864error:
Chris Wilson821ed7d2016-09-09 14:11:53 +01001865 i915_gem_set_wedged(dev_priv);
Chris Wilson2e8f9d32017-03-16 17:13:04 +00001866 goto finish;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001867}
1868
David Weinehallc49d13e2016-08-22 13:32:42 +03001869static int i915_pm_suspend(struct device *kdev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001870{
David Weinehallc49d13e2016-08-22 13:32:42 +03001871 struct pci_dev *pdev = to_pci_dev(kdev);
1872 struct drm_device *dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001873
David Weinehallc49d13e2016-08-22 13:32:42 +03001874 if (!dev) {
1875 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001876 return -ENODEV;
1877 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001878
David Weinehallc49d13e2016-08-22 13:32:42 +03001879 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Dave Airlie5bcf7192010-12-07 09:20:40 +10001880 return 0;
1881
David Weinehallc49d13e2016-08-22 13:32:42 +03001882 return i915_drm_suspend(dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001883}
1884
David Weinehallc49d13e2016-08-22 13:32:42 +03001885static int i915_pm_suspend_late(struct device *kdev)
Imre Deak76c4b252014-04-01 19:55:22 +03001886{
David Weinehallc49d13e2016-08-22 13:32:42 +03001887 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deak76c4b252014-04-01 19:55:22 +03001888
1889 /*
Damien Lespiauc965d9952015-05-18 19:53:48 +01001890 * We have a suspend ordering issue with the snd-hda driver also
Imre Deak76c4b252014-04-01 19:55:22 +03001891 * requiring our device to be power up. Due to the lack of a
1892 * parent/child relationship we currently solve this with an late
1893 * suspend hook.
1894 *
1895 * FIXME: This should be solved with a special hdmi sink device or
1896 * similar so that power domains can be employed.
1897 */
David Weinehallc49d13e2016-08-22 13:32:42 +03001898 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak76c4b252014-04-01 19:55:22 +03001899 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001900
David Weinehallc49d13e2016-08-22 13:32:42 +03001901 return i915_drm_suspend_late(dev, false);
Imre Deakab3be732015-03-02 13:04:41 +02001902}
1903
David Weinehallc49d13e2016-08-22 13:32:42 +03001904static int i915_pm_poweroff_late(struct device *kdev)
Imre Deakab3be732015-03-02 13:04:41 +02001905{
David Weinehallc49d13e2016-08-22 13:32:42 +03001906 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deakab3be732015-03-02 13:04:41 +02001907
David Weinehallc49d13e2016-08-22 13:32:42 +03001908 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deakab3be732015-03-02 13:04:41 +02001909 return 0;
1910
David Weinehallc49d13e2016-08-22 13:32:42 +03001911 return i915_drm_suspend_late(dev, true);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001912}
1913
David Weinehallc49d13e2016-08-22 13:32:42 +03001914static int i915_pm_resume_early(struct device *kdev)
Imre Deak76c4b252014-04-01 19:55:22 +03001915{
David Weinehallc49d13e2016-08-22 13:32:42 +03001916 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Imre Deak76c4b252014-04-01 19:55:22 +03001917
David Weinehallc49d13e2016-08-22 13:32:42 +03001918 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak097dd832014-10-23 19:23:19 +03001919 return 0;
1920
David Weinehallc49d13e2016-08-22 13:32:42 +03001921 return i915_drm_resume_early(dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001922}
1923
David Weinehallc49d13e2016-08-22 13:32:42 +03001924static int i915_pm_resume(struct device *kdev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001925{
David Weinehallc49d13e2016-08-22 13:32:42 +03001926 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001927
David Weinehallc49d13e2016-08-22 13:32:42 +03001928 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Imre Deak097dd832014-10-23 19:23:19 +03001929 return 0;
1930
David Weinehallc49d13e2016-08-22 13:32:42 +03001931 return i915_drm_resume(dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001932}
1933
Chris Wilson1f19ac22016-05-14 07:26:32 +01001934/* freeze: before creating the hibernation_image */
David Weinehallc49d13e2016-08-22 13:32:42 +03001935static int i915_pm_freeze(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001936{
Chris Wilson6a800ea2016-09-21 14:51:07 +01001937 int ret;
1938
1939 ret = i915_pm_suspend(kdev);
1940 if (ret)
1941 return ret;
1942
1943 ret = i915_gem_freeze(kdev_to_i915(kdev));
1944 if (ret)
1945 return ret;
1946
1947 return 0;
Chris Wilson1f19ac22016-05-14 07:26:32 +01001948}
1949
David Weinehallc49d13e2016-08-22 13:32:42 +03001950static int i915_pm_freeze_late(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001951{
Chris Wilson461fb992016-05-14 07:26:33 +01001952 int ret;
1953
David Weinehallc49d13e2016-08-22 13:32:42 +03001954 ret = i915_pm_suspend_late(kdev);
Chris Wilson461fb992016-05-14 07:26:33 +01001955 if (ret)
1956 return ret;
1957
David Weinehallc49d13e2016-08-22 13:32:42 +03001958 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
Chris Wilson461fb992016-05-14 07:26:33 +01001959 if (ret)
1960 return ret;
1961
1962 return 0;
Chris Wilson1f19ac22016-05-14 07:26:32 +01001963}
1964
1965/* thaw: called after creating the hibernation image, but before turning off. */
David Weinehallc49d13e2016-08-22 13:32:42 +03001966static int i915_pm_thaw_early(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001967{
David Weinehallc49d13e2016-08-22 13:32:42 +03001968 return i915_pm_resume_early(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01001969}
1970
David Weinehallc49d13e2016-08-22 13:32:42 +03001971static int i915_pm_thaw(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001972{
David Weinehallc49d13e2016-08-22 13:32:42 +03001973 return i915_pm_resume(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01001974}
1975
1976/* restore: called after loading the hibernation image. */
David Weinehallc49d13e2016-08-22 13:32:42 +03001977static int i915_pm_restore_early(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001978{
David Weinehallc49d13e2016-08-22 13:32:42 +03001979 return i915_pm_resume_early(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01001980}
1981
David Weinehallc49d13e2016-08-22 13:32:42 +03001982static int i915_pm_restore(struct device *kdev)
Chris Wilson1f19ac22016-05-14 07:26:32 +01001983{
David Weinehallc49d13e2016-08-22 13:32:42 +03001984 return i915_pm_resume(kdev);
Chris Wilson1f19ac22016-05-14 07:26:32 +01001985}
1986
Imre Deakddeea5b2014-05-05 15:19:56 +03001987/*
1988 * Save all Gunit registers that may be lost after a D3 and a subsequent
1989 * S0i[R123] transition. The list of registers needing a save/restore is
1990 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1991 * registers in the following way:
1992 * - Driver: saved/restored by the driver
1993 * - Punit : saved/restored by the Punit firmware
1994 * - No, w/o marking: no need to save/restore, since the register is R/O or
1995 * used internally by the HW in a way that doesn't depend
1996 * keeping the content across a suspend/resume.
1997 * - Debug : used for debugging
1998 *
1999 * We save/restore all registers marked with 'Driver', with the following
2000 * exceptions:
2001 * - Registers out of use, including also registers marked with 'Debug'.
2002 * These have no effect on the driver's operation, so we don't save/restore
2003 * them to reduce the overhead.
2004 * - Registers that are fully setup by an initialization function called from
2005 * the resume path. For example many clock gating and RPS/RC6 registers.
2006 * - Registers that provide the right functionality with their reset defaults.
2007 *
2008 * TODO: Except for registers that based on the above 3 criteria can be safely
2009 * ignored, we save/restore all others, practically treating the HW context as
2010 * a black-box for the driver. Further investigation is needed to reduce the
2011 * saved/restored registers even further, by following the same 3 criteria.
2012 */
2013static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2014{
2015 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2016 int i;
2017
2018 /* GAM 0x4000-0x4770 */
2019 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2020 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2021 s->arb_mode = I915_READ(ARB_MODE);
2022 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2023 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2024
2025 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002026 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03002027
2028 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
Imre Deakb5f1c972015-04-15 16:52:30 -07002029 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
Imre Deakddeea5b2014-05-05 15:19:56 +03002030
2031 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2032 s->ecochk = I915_READ(GAM_ECOCHK);
2033 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2034 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2035
2036 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2037
2038 /* MBC 0x9024-0x91D0, 0x8500 */
2039 s->g3dctl = I915_READ(VLV_G3DCTL);
2040 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2041 s->mbctl = I915_READ(GEN6_MBCTL);
2042
2043 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2044 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2045 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2046 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2047 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2048 s->rstctl = I915_READ(GEN6_RSTCTL);
2049 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2050
2051 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2052 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2053 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2054 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2055 s->ecobus = I915_READ(ECOBUS);
2056 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2057 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2058 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2059 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2060 s->rcedata = I915_READ(VLV_RCEDATA);
2061 s->spare2gh = I915_READ(VLV_SPAREG2H);
2062
2063 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2064 s->gt_imr = I915_READ(GTIMR);
2065 s->gt_ier = I915_READ(GTIER);
2066 s->pm_imr = I915_READ(GEN6_PMIMR);
2067 s->pm_ier = I915_READ(GEN6_PMIER);
2068
2069 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002070 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03002071
2072 /* GT SA CZ domain, 0x100000-0x138124 */
2073 s->tilectl = I915_READ(TILECTL);
2074 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2075 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2076 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2077 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2078
2079 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2080 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2081 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
Jesse Barnes9c252102015-04-01 14:22:57 -07002082 s->pcbr = I915_READ(VLV_PCBR);
Imre Deakddeea5b2014-05-05 15:19:56 +03002083 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2084
2085 /*
2086 * Not saving any of:
2087 * DFT, 0x9800-0x9EC0
2088 * SARB, 0xB000-0xB1FC
2089 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2090 * PCI CFG
2091 */
2092}
2093
2094static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2095{
2096 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2097 u32 val;
2098 int i;
2099
2100 /* GAM 0x4000-0x4770 */
2101 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2102 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2103 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2104 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2105 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2106
2107 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002108 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03002109
2110 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
Imre Deakb5f1c972015-04-15 16:52:30 -07002111 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
Imre Deakddeea5b2014-05-05 15:19:56 +03002112
2113 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2114 I915_WRITE(GAM_ECOCHK, s->ecochk);
2115 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2116 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2117
2118 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2119
2120 /* MBC 0x9024-0x91D0, 0x8500 */
2121 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2122 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2123 I915_WRITE(GEN6_MBCTL, s->mbctl);
2124
2125 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2126 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2127 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2128 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2129 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2130 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2131 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2132
2133 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2134 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2135 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2136 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2137 I915_WRITE(ECOBUS, s->ecobus);
2138 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2139 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2140 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2141 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2142 I915_WRITE(VLV_RCEDATA, s->rcedata);
2143 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2144
2145 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2146 I915_WRITE(GTIMR, s->gt_imr);
2147 I915_WRITE(GTIER, s->gt_ier);
2148 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2149 I915_WRITE(GEN6_PMIER, s->pm_ier);
2150
2151 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03002152 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03002153
2154 /* GT SA CZ domain, 0x100000-0x138124 */
2155 I915_WRITE(TILECTL, s->tilectl);
2156 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2157 /*
2158 * Preserve the GT allow wake and GFX force clock bit, they are not
2159 * be restored, as they are used to control the s0ix suspend/resume
2160 * sequence by the caller.
2161 */
2162 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2163 val &= VLV_GTLC_ALLOWWAKEREQ;
2164 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2165 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2166
2167 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2168 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2169 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2170 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2171
2172 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2173
2174 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2175 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2176 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
Jesse Barnes9c252102015-04-01 14:22:57 -07002177 I915_WRITE(VLV_PCBR, s->pcbr);
Imre Deakddeea5b2014-05-05 15:19:56 +03002178 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2179}
2180
Chris Wilson3dd14c02017-04-21 14:58:15 +01002181static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2182 u32 mask, u32 val)
2183{
2184 /* The HW does not like us polling for PW_STATUS frequently, so
2185 * use the sleeping loop rather than risk the busy spin within
2186 * intel_wait_for_register().
2187 *
2188 * Transitioning between RC6 states should be at most 2ms (see
2189 * valleyview_enable_rps) so use a 3ms timeout.
2190 */
2191 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2192 3);
2193}
2194
Imre Deak650ad972014-04-18 16:35:02 +03002195int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2196{
2197 u32 val;
2198 int err;
2199
Imre Deak650ad972014-04-18 16:35:02 +03002200 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2201 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2202 if (force_on)
2203 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2204 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2205
2206 if (!force_on)
2207 return 0;
2208
Chris Wilsonc6ddc5f2016-06-30 15:32:46 +01002209 err = intel_wait_for_register(dev_priv,
2210 VLV_GTLC_SURVIVABILITY_REG,
2211 VLV_GFX_CLK_STATUS_BIT,
2212 VLV_GFX_CLK_STATUS_BIT,
2213 20);
Imre Deak650ad972014-04-18 16:35:02 +03002214 if (err)
2215 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2216 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2217
2218 return err;
Imre Deak650ad972014-04-18 16:35:02 +03002219}
2220
Imre Deakddeea5b2014-05-05 15:19:56 +03002221static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2222{
Chris Wilson3dd14c02017-04-21 14:58:15 +01002223 u32 mask;
Imre Deakddeea5b2014-05-05 15:19:56 +03002224 u32 val;
Chris Wilson3dd14c02017-04-21 14:58:15 +01002225 int err;
Imre Deakddeea5b2014-05-05 15:19:56 +03002226
2227 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2228 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2229 if (allow)
2230 val |= VLV_GTLC_ALLOWWAKEREQ;
2231 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2232 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2233
Chris Wilson3dd14c02017-04-21 14:58:15 +01002234 mask = VLV_GTLC_ALLOWWAKEACK;
2235 val = allow ? mask : 0;
2236
2237 err = vlv_wait_for_pw_status(dev_priv, mask, val);
Imre Deakddeea5b2014-05-05 15:19:56 +03002238 if (err)
2239 DRM_ERROR("timeout disabling GT waking\n");
Chris Wilsonb2736692016-06-30 15:32:47 +01002240
Imre Deakddeea5b2014-05-05 15:19:56 +03002241 return err;
Imre Deakddeea5b2014-05-05 15:19:56 +03002242}
2243
Chris Wilson3dd14c02017-04-21 14:58:15 +01002244static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2245 bool wait_for_on)
Imre Deakddeea5b2014-05-05 15:19:56 +03002246{
2247 u32 mask;
2248 u32 val;
Imre Deakddeea5b2014-05-05 15:19:56 +03002249
2250 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2251 val = wait_for_on ? mask : 0;
Imre Deakddeea5b2014-05-05 15:19:56 +03002252
2253 /*
2254 * RC6 transitioning can be delayed up to 2 msec (see
2255 * valleyview_enable_rps), use 3 msec for safety.
2256 */
Chris Wilson3dd14c02017-04-21 14:58:15 +01002257 if (vlv_wait_for_pw_status(dev_priv, mask, val))
Imre Deakddeea5b2014-05-05 15:19:56 +03002258 DRM_ERROR("timeout waiting for GT wells to go %s\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02002259 onoff(wait_for_on));
Imre Deakddeea5b2014-05-05 15:19:56 +03002260}
2261
2262static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2263{
2264 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2265 return;
2266
Daniel Vetter6fa283b2016-01-19 21:00:56 +01002267 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
Imre Deakddeea5b2014-05-05 15:19:56 +03002268 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2269}
2270
Sagar Kambleebc32822014-08-13 23:07:05 +05302271static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03002272{
2273 u32 mask;
2274 int err;
2275
2276 /*
2277 * Bspec defines the following GT well on flags as debug only, so
2278 * don't treat them as hard failures.
2279 */
Chris Wilson3dd14c02017-04-21 14:58:15 +01002280 vlv_wait_for_gt_wells(dev_priv, false);
Imre Deakddeea5b2014-05-05 15:19:56 +03002281
2282 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2283 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2284
2285 vlv_check_no_gt_access(dev_priv);
2286
2287 err = vlv_force_gfx_clock(dev_priv, true);
2288 if (err)
2289 goto err1;
2290
2291 err = vlv_allow_gt_wake(dev_priv, false);
2292 if (err)
2293 goto err2;
Deepak S98711162014-12-12 14:18:16 +05302294
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03002295 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05302296 vlv_save_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002297
2298 err = vlv_force_gfx_clock(dev_priv, false);
2299 if (err)
2300 goto err2;
2301
2302 return 0;
2303
2304err2:
2305 /* For safety always re-enable waking and disable gfx clock forcing */
2306 vlv_allow_gt_wake(dev_priv, true);
2307err1:
2308 vlv_force_gfx_clock(dev_priv, false);
2309
2310 return err;
2311}
2312
Sagar Kamble016970b2014-08-13 23:07:06 +05302313static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2314 bool rpm_resume)
Imre Deakddeea5b2014-05-05 15:19:56 +03002315{
Imre Deakddeea5b2014-05-05 15:19:56 +03002316 int err;
2317 int ret;
2318
2319 /*
2320 * If any of the steps fail just try to continue, that's the best we
2321 * can do at this point. Return the first error code (which will also
2322 * leave RPM permanently disabled).
2323 */
2324 ret = vlv_force_gfx_clock(dev_priv, true);
2325
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03002326 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05302327 vlv_restore_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002328
2329 err = vlv_allow_gt_wake(dev_priv, true);
2330 if (!ret)
2331 ret = err;
2332
2333 err = vlv_force_gfx_clock(dev_priv, false);
2334 if (!ret)
2335 ret = err;
2336
2337 vlv_check_no_gt_access(dev_priv);
2338
Chris Wilson7c108fd2016-10-24 13:42:18 +01002339 if (rpm_resume)
Ville Syrjälä46f16e62016-10-31 22:37:22 +02002340 intel_init_clock_gating(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03002341
2342 return ret;
2343}
2344
David Weinehallc49d13e2016-08-22 13:32:42 +03002345static int intel_runtime_suspend(struct device *kdev)
Paulo Zanoni8a187452013-12-06 20:32:13 -02002346{
David Weinehallc49d13e2016-08-22 13:32:42 +03002347 struct pci_dev *pdev = to_pci_dev(kdev);
Paulo Zanoni8a187452013-12-06 20:32:13 -02002348 struct drm_device *dev = pci_get_drvdata(pdev);
Chris Wilsonfac5e232016-07-04 11:34:36 +01002349 struct drm_i915_private *dev_priv = to_i915(dev);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002350 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002351
Chris Wilsondc979972016-05-10 14:10:04 +01002352 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
Imre Deakc6df39b2014-04-14 20:24:29 +03002353 return -ENODEV;
2354
Tvrtko Ursulin6772ffe2016-10-13 11:02:55 +01002355 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
Imre Deak604effb2014-08-26 13:26:56 +03002356 return -ENODEV;
2357
Paulo Zanoni8a187452013-12-06 20:32:13 -02002358 DRM_DEBUG_KMS("Suspending device\n");
2359
Imre Deak1f814da2015-12-16 02:52:19 +02002360 disable_rpm_wakeref_asserts(dev_priv);
2361
Imre Deakd6102972014-05-07 19:57:49 +03002362 /*
2363 * We are safe here against re-faults, since the fault handler takes
2364 * an RPM reference.
2365 */
Chris Wilson7c108fd2016-10-24 13:42:18 +01002366 i915_gem_runtime_suspend(dev_priv);
Imre Deakd6102972014-05-07 19:57:49 +03002367
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00002368 intel_guc_suspend(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07002369
Imre Deak2eb52522014-11-19 15:30:05 +02002370 intel_runtime_pm_disable_interrupts(dev_priv);
Imre Deakb5478bc2014-04-14 20:24:37 +03002371
Imre Deak507e1262016-04-20 20:27:54 +03002372 ret = 0;
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02002373 if (IS_GEN9_LP(dev_priv)) {
Imre Deak507e1262016-04-20 20:27:54 +03002374 bxt_display_core_uninit(dev_priv);
2375 bxt_enable_dc9(dev_priv);
2376 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2377 hsw_enable_pc8(dev_priv);
2378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2379 ret = vlv_suspend_complete(dev_priv);
2380 }
2381
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002382 if (ret) {
2383 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
Daniel Vetterb9632912014-09-30 10:56:44 +02002384 intel_runtime_pm_enable_interrupts(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002385
Imre Deak1f814da2015-12-16 02:52:19 +02002386 enable_rpm_wakeref_asserts(dev_priv);
2387
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002388 return ret;
2389 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03002390
Hans de Goede68f60942017-02-10 11:28:01 +01002391 intel_uncore_suspend(dev_priv);
Imre Deak1f814da2015-12-16 02:52:19 +02002392
2393 enable_rpm_wakeref_asserts(dev_priv);
2394 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002395
Mika Kuoppalabc3b9342016-01-08 15:51:20 +02002396 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002397 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2398
Paulo Zanoni8a187452013-12-06 20:32:13 -02002399 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08002400
2401 /*
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002402 * FIXME: We really should find a document that references the arguments
2403 * used below!
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08002404 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002405 if (IS_BROADWELL(dev_priv)) {
Paulo Zanonid37ae192015-07-30 18:20:29 -03002406 /*
2407 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2408 * being detected, and the call we do at intel_runtime_resume()
2409 * won't be able to restore them. Since PCI_D3hot matches the
2410 * actual specification and appears to be working, use it.
2411 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002412 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
Paulo Zanonid37ae192015-07-30 18:20:29 -03002413 } else {
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002414 /*
2415 * current versions of firmware which depend on this opregion
2416 * notification have repurposed the D1 definition to mean
2417 * "runtime suspended" vs. what you would normally expect (D3)
2418 * to distinguish it from notifications that might be sent via
2419 * the suspend path.
2420 */
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002421 intel_opregion_notify_adapter(dev_priv, PCI_D1);
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03002422 }
Paulo Zanoni8a187452013-12-06 20:32:13 -02002423
Mika Kuoppala59bad942015-01-16 11:34:40 +02002424 assert_forcewakes_inactive(dev_priv);
Chris Wilsondc9fb092015-01-16 11:34:34 +02002425
Ander Conselvan de Oliveira21d6e0b2017-01-20 16:28:43 +02002426 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Lyude19625e82016-06-21 17:03:44 -04002427 intel_hpd_poll_init(dev_priv);
2428
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03002429 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02002430 return 0;
2431}
2432
David Weinehallc49d13e2016-08-22 13:32:42 +03002433static int intel_runtime_resume(struct device *kdev)
Paulo Zanoni8a187452013-12-06 20:32:13 -02002434{
David Weinehallc49d13e2016-08-22 13:32:42 +03002435 struct pci_dev *pdev = to_pci_dev(kdev);
Paulo Zanoni8a187452013-12-06 20:32:13 -02002436 struct drm_device *dev = pci_get_drvdata(pdev);
Chris Wilsonfac5e232016-07-04 11:34:36 +01002437 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002438 int ret = 0;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002439
Tvrtko Ursulin6772ffe2016-10-13 11:02:55 +01002440 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
Imre Deak604effb2014-08-26 13:26:56 +03002441 return -ENODEV;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002442
2443 DRM_DEBUG_KMS("Resuming device\n");
2444
Imre Deak1f814da2015-12-16 02:52:19 +02002445 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2446 disable_rpm_wakeref_asserts(dev_priv);
2447
Chris Wilson6f9f4b72016-05-23 15:08:09 +01002448 intel_opregion_notify_adapter(dev_priv, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02002449 dev_priv->pm.suspended = false;
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02002450 if (intel_uncore_unclaimed_mmio(dev_priv))
2451 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02002452
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00002453 intel_guc_resume(dev_priv);
Alex Daia1c41992015-09-30 09:46:37 -07002454
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002455 if (IS_GEN6(dev_priv))
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02002456 intel_init_pch_refclk(dev_priv);
Suketu Shah31335ce2014-11-24 13:37:45 +05302457
Rodrigo Vivib9fd7992016-12-16 17:42:25 +02002458 if (IS_GEN9_LP(dev_priv)) {
Imre Deak507e1262016-04-20 20:27:54 +03002459 bxt_disable_dc9(dev_priv);
2460 bxt_display_core_init(dev_priv, true);
Imre Deakf62c79b2016-04-20 20:27:57 +03002461 if (dev_priv->csr.dmc_payload &&
2462 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2463 gen9_enable_dc5(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03002464 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002465 hsw_disable_pc8(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03002466 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002467 ret = vlv_resume_prepare(dev_priv, true);
Imre Deak507e1262016-04-20 20:27:54 +03002468 }
Paulo Zanoni1a5df182014-10-27 17:54:32 -02002469
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002470 /*
2471 * No point of rolling back things in case of an error, as the best
2472 * we can do is to hope that things will still work (and disable RPM).
2473 */
Tvrtko Ursulinc6be6072016-11-16 08:55:31 +00002474 i915_gem_init_swizzling(dev_priv);
Chris Wilson83bf6d52017-02-03 12:57:17 +00002475 i915_gem_restore_fences(dev_priv);
Imre Deak92b806d2014-04-14 20:24:39 +03002476
Daniel Vetterb9632912014-09-30 10:56:44 +02002477 intel_runtime_pm_enable_interrupts(dev_priv);
Ville Syrjälä08d8a232015-08-27 23:56:08 +03002478
2479 /*
2480 * On VLV/CHV display interrupts are part of the display
2481 * power well, so hpd is reinitialized from there. For
2482 * everyone else do it here.
2483 */
Wayne Boyer666a4532015-12-09 12:29:35 -08002484 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä08d8a232015-08-27 23:56:08 +03002485 intel_hpd_init(dev_priv);
2486
Imre Deak1f814da2015-12-16 02:52:19 +02002487 enable_rpm_wakeref_asserts(dev_priv);
2488
Imre Deak0ab9cfe2014-04-15 16:39:45 +03002489 if (ret)
2490 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2491 else
2492 DRM_DEBUG_KMS("Device resumed\n");
2493
2494 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002495}
2496
Chris Wilson42f55512016-06-24 14:00:26 +01002497const struct dev_pm_ops i915_pm_ops = {
Imre Deak5545dbb2014-10-23 19:23:28 +03002498 /*
2499 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2500 * PMSG_RESUME]
2501 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002502 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03002503 .suspend_late = i915_pm_suspend_late,
2504 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04002505 .resume = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03002506
2507 /*
2508 * S4 event handlers
2509 * @freeze, @freeze_late : called (1) before creating the
2510 * hibernation image [PMSG_FREEZE] and
2511 * (2) after rebooting, before restoring
2512 * the image [PMSG_QUIESCE]
2513 * @thaw, @thaw_early : called (1) after creating the hibernation
2514 * image, before writing it [PMSG_THAW]
2515 * and (2) after failing to create or
2516 * restore the image [PMSG_RECOVER]
2517 * @poweroff, @poweroff_late: called after writing the hibernation
2518 * image, before rebooting [PMSG_HIBERNATE]
2519 * @restore, @restore_early : called after rebooting and restoring the
2520 * hibernation image [PMSG_RESTORE]
2521 */
Chris Wilson1f19ac22016-05-14 07:26:32 +01002522 .freeze = i915_pm_freeze,
2523 .freeze_late = i915_pm_freeze_late,
2524 .thaw_early = i915_pm_thaw_early,
2525 .thaw = i915_pm_thaw,
Imre Deak36d61e62014-10-23 19:23:24 +03002526 .poweroff = i915_pm_suspend,
Imre Deakab3be732015-03-02 13:04:41 +02002527 .poweroff_late = i915_pm_poweroff_late,
Chris Wilson1f19ac22016-05-14 07:26:32 +01002528 .restore_early = i915_pm_restore_early,
2529 .restore = i915_pm_restore,
Imre Deak5545dbb2014-10-23 19:23:28 +03002530
2531 /* S0ix (via runtime suspend) event handlers */
Paulo Zanoni97bea202014-03-07 20:12:33 -03002532 .runtime_suspend = intel_runtime_suspend,
2533 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08002534};
2535
Laurent Pinchart78b68552012-05-17 13:27:22 +02002536static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08002537 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08002538 .open = drm_gem_vm_open,
2539 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08002540};
2541
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002542static const struct file_operations i915_driver_fops = {
2543 .owner = THIS_MODULE,
2544 .open = drm_open,
2545 .release = drm_release,
2546 .unlocked_ioctl = drm_ioctl,
2547 .mmap = drm_gem_mmap,
2548 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002549 .read = drm_read,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002550 .compat_ioctl = i915_compat_ioctl,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002551 .llseek = noop_llseek,
2552};
2553
Chris Wilson0673ad42016-06-24 14:00:22 +01002554static int
2555i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2556 struct drm_file *file)
2557{
2558 return -ENODEV;
2559}
2560
2561static const struct drm_ioctl_desc i915_ioctls[] = {
2562 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2563 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2564 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2565 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2566 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2567 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2568 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2569 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2570 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2571 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2572 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2573 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2574 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2575 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2576 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2577 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2578 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2579 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2580 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
Chris Wilsonfec04452017-01-27 09:40:08 +00002581 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002582 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2583 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2584 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2585 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2586 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2587 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2588 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2589 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2590 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2591 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2592 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2593 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2594 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2595 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2596 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
Chris Wilson111dbca2017-01-10 12:10:44 +00002597 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2598 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002599 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2600 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2601 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2602 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2603 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2604 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2605 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2606 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2607 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2608 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2609 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2610 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2611 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2612 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2613 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
Robert Braggeec688e2016-11-07 19:49:47 +00002614 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
Chris Wilson0673ad42016-06-24 14:00:22 +01002615};
2616
Linus Torvalds1da177e2005-04-16 15:20:36 -07002617static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00002618 /* Don't use MTRRs here; the Xserver or userspace app should
2619 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11002620 */
Eric Anholt673a3942008-07-30 12:06:12 -07002621 .driver_features =
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02002622 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
Maarten Lankhorst8d2b47d2017-02-02 08:41:42 +01002623 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
Chris Wilsoncad36882017-02-10 16:35:21 +00002624 .release = i915_driver_release,
Eric Anholt673a3942008-07-30 12:06:12 -07002625 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11002626 .lastclose = i915_driver_lastclose,
Eric Anholt673a3942008-07-30 12:06:12 -07002627 .postclose = i915_driver_postclose,
David Herrmann915b4d12014-08-29 12:12:43 +02002628 .set_busid = drm_pci_set_busid,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01002629
Chris Wilsonb1f788c2016-08-04 07:52:45 +01002630 .gem_close_object = i915_gem_close_object,
Chris Wilsonf0cd5182016-10-28 13:58:43 +01002631 .gem_free_object_unlocked = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08002632 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02002633
2634 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2635 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2636 .gem_prime_export = i915_gem_prime_export,
2637 .gem_prime_import = i915_gem_prime_import,
2638
Dave Airlieff72145b2011-02-07 12:16:14 +10002639 .dumb_create = i915_gem_dumb_create,
Dave Airlieda6b51d2014-12-24 13:11:17 +10002640 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02002641 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002642 .ioctls = i915_ioctls,
Chris Wilson0673ad42016-06-24 14:00:22 +01002643 .num_ioctls = ARRAY_SIZE(i915_ioctls),
Arjan van de Vene08e96d2011-10-31 07:28:57 -07002644 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11002645 .name = DRIVER_NAME,
2646 .desc = DRIVER_DESC,
2647 .date = DRIVER_DATE,
2648 .major = DRIVER_MAJOR,
2649 .minor = DRIVER_MINOR,
2650 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002651};
Chris Wilson66d9cb52017-02-13 17:15:17 +00002652
2653#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2654#include "selftests/mock_drm.c"
2655#endif