blob: a9a72574b34abfcb3055cee9b22b052fed173e12 [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050024int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053025 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050028int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053029
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050030int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053031{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050035 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053036 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050042EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053043
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050044int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053045{
46 int i;
47
48 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050049 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053050 return i;
51 }
52
53 pr_warn("Requested row not found, selecting lowest row no: 48\n");
54 return 0;
55}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050056EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053057
Sanyog Kalef8101c72018-04-26 18:38:17 +053058static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050059 struct sdw_slave *slave,
60 struct sdw_transport_params *t_params,
61 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053062{
63 u32 addr1, addr2, addr3, addr4;
64 int ret;
65 u16 wbuf;
66
67 if (bus->params.next_bank) {
68 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
69 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
70 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
71 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
72 } else {
73 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
74 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
75 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
76 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
77 }
78
79 /* Program DPN_OffsetCtrl2 registers */
80 ret = sdw_write(slave, addr1, t_params->offset2);
81 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050082 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053083 return ret;
84 }
85
86 /* Program DPN_BlockCtrl3 register */
87 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
88 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050089 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053090 return ret;
91 }
92
93 /*
94 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053095 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053096 * handled, so bail out if we are not FULL data port type
97 */
98 if (type != SDW_DPN_FULL)
99 return ret;
100
101 /* Program DPN_SampleCtrl2 register */
102 wbuf = (t_params->sample_interval - 1);
103 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
104 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
105
106 ret = sdw_write(slave, addr3, wbuf);
107 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500108 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530109 return ret;
110 }
111
112 /* Program DPN_HCtrl register */
113 wbuf = t_params->hstart;
114 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
115 wbuf |= t_params->hstop;
116
117 ret = sdw_write(slave, addr4, wbuf);
118 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500119 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530120
121 return ret;
122}
123
124static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500125 struct sdw_slave_runtime *s_rt,
126 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530127{
128 struct sdw_transport_params *t_params = &p_rt->transport_params;
129 struct sdw_port_params *p_params = &p_rt->port_params;
130 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
131 u32 addr1, addr2, addr3, addr4, addr5, addr6;
132 struct sdw_dpn_prop *dpn_prop;
133 int ret;
134 u8 wbuf;
135
136 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500137 s_rt->direction,
138 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530139 if (!dpn_prop)
140 return -EINVAL;
141
142 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
143 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
144
145 if (bus->params.next_bank) {
146 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
147 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
148 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
149 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
150
151 } else {
152 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
153 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
154 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
155 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
156 }
157
158 /* Program DPN_PortCtrl register */
159 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
160 wbuf |= p_params->flow_mode;
161
162 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
163 if (ret < 0) {
164 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500165 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530166 t_params->port_num);
167 return ret;
168 }
169
Srinivas Kandagatlaa9107de2020-03-11 11:35:44 +0000170 if (!dpn_prop->read_only_wordlength) {
171 /* Program DPN_BlockCtrl1 register */
172 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
173 if (ret < 0) {
174 dev_err(&s_rt->slave->dev,
175 "DPN_BlockCtrl1 register write failed for port %d\n",
176 t_params->port_num);
177 return ret;
178 }
Sanyog Kalef8101c72018-04-26 18:38:17 +0530179 }
180
181 /* Program DPN_SampleCtrl1 register */
182 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
183 ret = sdw_write(s_rt->slave, addr3, wbuf);
184 if (ret < 0) {
185 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500186 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530187 t_params->port_num);
188 return ret;
189 }
190
191 /* Program DPN_OffsetCtrl1 registers */
192 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
193 if (ret < 0) {
194 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500195 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530196 t_params->port_num);
197 return ret;
198 }
199
200 /* Program DPN_BlockCtrl2 register*/
201 if (t_params->blk_grp_ctrl_valid) {
202 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
203 if (ret < 0) {
204 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500205 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530206 t_params->port_num);
207 return ret;
208 }
209 }
210
211 /* program DPN_LaneCtrl register */
212 if (slave_prop->lane_control_support) {
213 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
214 if (ret < 0) {
215 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500216 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530217 t_params->port_num);
218 return ret;
219 }
220 }
221
222 if (dpn_prop->type != SDW_DPN_SIMPLE) {
223 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500224 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530225 if (ret < 0)
226 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500227 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530228 t_params->port_num);
229 }
230
231 return ret;
232}
233
234static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500235 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530236{
237 int ret;
238
239 /*
240 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530241 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530242 * hstart/stop etc of the data. Port parameters refers to word
243 * length, flow mode etc of the port
244 */
245 ret = bus->port_ops->dpn_set_port_transport_params(bus,
246 &p_rt->transport_params,
247 bus->params.next_bank);
248 if (ret < 0)
249 return ret;
250
251 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500252 &p_rt->port_params,
253 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530254}
255
256/**
257 * sdw_program_port_params() - Programs transport parameters of Master(s)
258 * and Slave(s)
259 *
260 * @m_rt: Master stream runtime
261 */
262static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
263{
264 struct sdw_slave_runtime *s_rt = NULL;
265 struct sdw_bus *bus = m_rt->bus;
266 struct sdw_port_runtime *p_rt;
267 int ret = 0;
268
269 /* Program transport & port parameters for Slave(s) */
270 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
271 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
272 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
273 if (ret < 0)
274 return ret;
275 }
276 }
277
278 /* Program transport & port parameters for Master(s) */
279 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
280 ret = sdw_program_master_port_params(bus, p_rt);
281 if (ret < 0)
282 return ret;
283 }
284
285 return 0;
286}
287
Sanyog Kale89e59052018-04-26 18:38:08 +0530288/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530289 * sdw_enable_disable_slave_ports: Enable/disable slave data port
290 *
291 * @bus: bus instance
292 * @s_rt: slave runtime
293 * @p_rt: port runtime
294 * @en: enable or disable operation
295 *
296 * This function only sets the enable/disable bits in the relevant bank, the
297 * actual enable/disable is done with a bank switch
298 */
299static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500300 struct sdw_slave_runtime *s_rt,
301 struct sdw_port_runtime *p_rt,
302 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530303{
304 struct sdw_transport_params *t_params = &p_rt->transport_params;
305 u32 addr;
306 int ret;
307
308 if (bus->params.next_bank)
309 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
310 else
311 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
312
313 /*
314 * Since bus doesn't support sharing a port across two streams,
315 * it is safe to reset this register
316 */
317 if (en)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000318 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530319 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000320 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530321
322 if (ret < 0)
323 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500324 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530325 ret, t_params->port_num);
326
327 return ret;
328}
329
330static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500331 struct sdw_port_runtime *p_rt,
332 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530333{
334 struct sdw_transport_params *t_params = &p_rt->transport_params;
335 struct sdw_bus *bus = m_rt->bus;
336 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500337 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530338
339 enable_ch.port_num = p_rt->num;
340 enable_ch.ch_mask = p_rt->ch_mask;
341 enable_ch.enable = en;
342
343 /* Perform Master port channel(s) enable/disable */
344 if (bus->port_ops->dpn_port_enable_ch) {
345 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500346 &enable_ch,
347 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530348 if (ret < 0) {
349 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500350 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530351 ret, t_params->port_num);
352 return ret;
353 }
354 } else {
355 dev_err(bus->dev,
356 "dpn_port_enable_ch not supported, %s failed\n",
357 en ? "enable" : "disable");
358 return -EINVAL;
359 }
360
361 return 0;
362}
363
364/**
365 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
366 * Slave(s)
367 *
368 * @m_rt: Master stream runtime
369 * @en: mode (enable/disable)
370 */
371static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
372{
373 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500374 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530375 int ret = 0;
376
377 /* Enable/Disable Slave port(s) */
378 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
379 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
380 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500381 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530382 if (ret < 0)
383 return ret;
384 }
385 }
386
387 /* Enable/Disable Master port(s) */
388 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
389 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
390 if (ret < 0)
391 return ret;
392 }
393
394 return 0;
395}
396
397static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500398 struct sdw_prepare_ch prep_ch,
399 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530400{
401 const struct sdw_slave_ops *ops = s_rt->slave->ops;
402 int ret;
403
404 if (ops->port_prep) {
405 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
406 if (ret < 0) {
407 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530408 "Slave Port Prep cmd %d failed: %d\n",
409 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530410 return ret;
411 }
412 }
413
414 return 0;
415}
416
417static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500418 struct sdw_slave_runtime *s_rt,
419 struct sdw_port_runtime *p_rt,
420 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530421{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500422 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530423 struct sdw_dpn_prop *dpn_prop;
424 struct sdw_prepare_ch prep_ch;
425 unsigned int time_left;
426 bool intr = false;
427 int ret = 0, val;
428 u32 addr;
429
430 prep_ch.num = p_rt->num;
431 prep_ch.ch_mask = p_rt->ch_mask;
432
433 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500434 s_rt->direction,
435 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530436 if (!dpn_prop) {
437 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500438 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530439 return -EINVAL;
440 }
441
442 prep_ch.prepare = prep;
443
444 prep_ch.bank = bus->params.next_bank;
445
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500446 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530447 intr = true;
448
449 /*
450 * Enable interrupt before Port prepare.
451 * For Port de-prepare, it is assumed that port
452 * was prepared earlier
453 */
454 if (prep && intr) {
455 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500456 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530457 if (ret < 0)
458 return ret;
459 }
460
461 /* Inform slave about the impending port prepare */
462 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
463
464 /* Prepare Slave port implementing CP_SM */
465 if (!dpn_prop->simple_ch_prep_sm) {
466 addr = SDW_DPN_PREPARECTRL(p_rt->num);
467
468 if (prep)
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000469 ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530470 else
Srinivas Kandagatla0b43fef2020-03-12 10:01:05 +0000471 ret = sdw_write(s_rt->slave, addr, 0x0);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530472
473 if (ret < 0) {
474 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500475 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530476 return ret;
477 }
478
479 /* Wait for completion on port ready */
480 port_ready = &s_rt->slave->port_ready[prep_ch.num];
481 time_left = wait_for_completion_timeout(port_ready,
482 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
483
484 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
485 val &= p_rt->ch_mask;
486 if (!time_left || val) {
487 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500488 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530489 return -ETIMEDOUT;
490 }
491 }
492
493 /* Inform slaves about ports prepared */
494 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
495
496 /* Disable interrupt after Port de-prepare */
497 if (!prep && intr)
498 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500499 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530500
501 return ret;
502}
503
504static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500505 struct sdw_port_runtime *p_rt,
506 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530507{
508 struct sdw_transport_params *t_params = &p_rt->transport_params;
509 struct sdw_bus *bus = m_rt->bus;
510 const struct sdw_master_port_ops *ops = bus->port_ops;
511 struct sdw_prepare_ch prep_ch;
512 int ret = 0;
513
514 prep_ch.num = p_rt->num;
515 prep_ch.ch_mask = p_rt->ch_mask;
516 prep_ch.prepare = prep; /* Prepare/De-prepare */
517 prep_ch.bank = bus->params.next_bank;
518
519 /* Pre-prepare/Pre-deprepare port(s) */
520 if (ops->dpn_port_prep) {
521 ret = ops->dpn_port_prep(bus, &prep_ch);
522 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500523 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500524 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530525 return ret;
526 }
527 }
528
529 return ret;
530}
531
532/**
533 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
534 * Slave(s)
535 *
536 * @m_rt: Master runtime handle
537 * @prep: Prepare or De-prepare
538 */
539static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
540{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500541 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530542 struct sdw_port_runtime *p_rt;
543 int ret = 0;
544
545 /* Prepare/De-prepare Slave port(s) */
546 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
547 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
548 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500549 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530550 if (ret < 0)
551 return ret;
552 }
553 }
554
555 /* Prepare/De-prepare Master port(s) */
556 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
557 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
558 if (ret < 0)
559 return ret;
560 }
561
562 return ret;
563}
564
565/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530566 * sdw_notify_config() - Notify bus configuration
567 *
568 * @m_rt: Master runtime handle
569 *
570 * This function notifies the Master(s) and Slave(s) of the
571 * new bus configuration.
572 */
573static int sdw_notify_config(struct sdw_master_runtime *m_rt)
574{
575 struct sdw_slave_runtime *s_rt;
576 struct sdw_bus *bus = m_rt->bus;
577 struct sdw_slave *slave;
578 int ret = 0;
579
580 if (bus->ops->set_bus_conf) {
581 ret = bus->ops->set_bus_conf(bus, &bus->params);
582 if (ret < 0)
583 return ret;
584 }
585
586 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
587 slave = s_rt->slave;
588
589 if (slave->ops->bus_config) {
590 ret = slave->ops->bus_config(slave, &bus->params);
Rander Wang60835022020-01-14 17:52:26 -0600591 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500592 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500593 slave->dev_num);
Rander Wang60835022020-01-14 17:52:26 -0600594 return ret;
595 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530596 }
597 }
598
599 return ret;
600}
601
602/**
603 * sdw_program_params() - Program transport and port parameters for Master(s)
604 * and Slave(s)
605 *
606 * @bus: SDW bus instance
Rander Wangbfaa3542020-01-14 17:52:27 -0600607 * @prepare: true if sdw_program_params() is called by _prepare.
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530608 */
Rander Wangbfaa3542020-01-14 17:52:27 -0600609static int sdw_program_params(struct sdw_bus *bus, bool prepare)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530610{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500611 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530612 int ret = 0;
613
614 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
Rander Wangbfaa3542020-01-14 17:52:27 -0600615
616 /*
617 * this loop walks through all master runtimes for a
618 * bus, but the ports can only be configured while
619 * explicitly preparing a stream or handling an
620 * already-prepared stream otherwise.
621 */
622 if (!prepare &&
623 m_rt->stream->state == SDW_STREAM_CONFIGURED)
624 continue;
625
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530626 ret = sdw_program_port_params(m_rt);
627 if (ret < 0) {
628 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500629 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530630 return ret;
631 }
632
633 ret = sdw_notify_config(m_rt);
634 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530635 dev_err(bus->dev,
636 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530637 return ret;
638 }
639
640 /* Enable port(s) on alternate bank for all active streams */
641 if (m_rt->stream->state != SDW_STREAM_ENABLED)
642 continue;
643
644 ret = sdw_enable_disable_ports(m_rt, true);
645 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500646 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530647 return ret;
648 }
649 }
650
651 return ret;
652}
653
Shreyas NCce6e74d2018-07-27 14:44:16 +0530654static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530655{
656 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530657 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530658 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500659 u8 *wbuf;
660 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530661 u16 addr;
662
663 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
664 if (!wr_msg)
665 return -ENOMEM;
666
Shreyas NCce6e74d2018-07-27 14:44:16 +0530667 bus->defer_msg.msg = wr_msg;
668
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530669 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
670 if (!wbuf) {
671 ret = -ENOMEM;
672 goto error_1;
673 }
674
675 /* Get row and column index to program register */
676 col_index = sdw_find_col_index(bus->params.col);
677 row_index = sdw_find_row_index(bus->params.row);
678 wbuf[0] = col_index | (row_index << 3);
679
680 if (bus->params.next_bank)
681 addr = SDW_SCP_FRAMECTRL_B1;
682 else
683 addr = SDW_SCP_FRAMECTRL_B0;
684
685 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500686 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530687 wr_msg->ssp_sync = true;
688
Shreyas NCce6e74d2018-07-27 14:44:16 +0530689 /*
690 * Set the multi_link flag only when both the hardware supports
691 * and there is a stream handled by multiple masters
692 */
693 multi_link = bus->multi_link && (m_rt_count > 1);
694
695 if (multi_link)
696 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
697 else
698 ret = sdw_transfer(bus, wr_msg);
699
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530700 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500701 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530702 goto error;
703 }
704
Shreyas NCce6e74d2018-07-27 14:44:16 +0530705 if (!multi_link) {
706 kfree(wr_msg);
707 kfree(wbuf);
708 bus->defer_msg.msg = NULL;
709 bus->params.curr_bank = !bus->params.curr_bank;
710 bus->params.next_bank = !bus->params.next_bank;
711 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530712
713 return 0;
714
715error:
716 kfree(wbuf);
717error_1:
718 kfree(wr_msg);
719 return ret;
720}
721
Shreyas NCce6e74d2018-07-27 14:44:16 +0530722/**
723 * sdw_ml_sync_bank_switch: Multilink register bank switch
724 *
725 * @bus: SDW bus instance
726 *
727 * Caller function should free the buffers on error
728 */
729static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
730{
731 unsigned long time_left;
732
733 if (!bus->multi_link)
734 return 0;
735
736 /* Wait for completion of transfer */
737 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
738 bus->bank_switch_timeout);
739
740 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500741 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530742 return -ETIMEDOUT;
743 }
744
745 bus->params.curr_bank = !bus->params.curr_bank;
746 bus->params.next_bank = !bus->params.next_bank;
747
748 if (bus->defer_msg.msg) {
749 kfree(bus->defer_msg.msg->buf);
750 kfree(bus->defer_msg.msg);
751 }
752
753 return 0;
754}
755
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530756static int do_bank_switch(struct sdw_stream_runtime *stream)
757{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500758 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530759 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500760 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530761 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530762 int ret = 0;
763
Vinod Koul48949722018-07-27 14:44:14 +0530764 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
765 bus = m_rt->bus;
766 ops = bus->ops;
767
Shreyas NCce6e74d2018-07-27 14:44:16 +0530768 if (bus->multi_link) {
769 multi_link = true;
770 mutex_lock(&bus->msg_lock);
771 }
772
Vinod Koul48949722018-07-27 14:44:14 +0530773 /* Pre-bank switch */
774 if (ops->pre_bank_switch) {
775 ret = ops->pre_bank_switch(bus);
776 if (ret < 0) {
777 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500778 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530779 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530780 }
781 }
782
Shreyas NCce6e74d2018-07-27 14:44:16 +0530783 /*
784 * Perform Bank switch operation.
785 * For multi link cases, the actual bank switch is
786 * synchronized across all Masters and happens later as a
787 * part of post_bank_switch ops.
788 */
789 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530790 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500791 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530792 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530793 }
794 }
795
Shreyas NCce6e74d2018-07-27 14:44:16 +0530796 /*
797 * For multi link cases, it is expected that the bank switch is
798 * triggered by the post_bank_switch for the first Master in the list
799 * and for the other Masters the post_bank_switch() should return doing
800 * nothing.
801 */
Vinod Koul48949722018-07-27 14:44:14 +0530802 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
803 bus = m_rt->bus;
804 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530805
Vinod Koul48949722018-07-27 14:44:14 +0530806 /* Post-bank switch */
807 if (ops->post_bank_switch) {
808 ret = ops->post_bank_switch(bus);
809 if (ret < 0) {
810 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530811 "Post bank switch op failed: %d\n",
812 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530813 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530814 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530815 } else if (bus->multi_link && stream->m_rt_count > 1) {
816 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500817 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530818 goto error;
819 }
820
821 /* Set the bank switch timeout to default, if not set */
822 if (!bus->bank_switch_timeout)
823 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
824
825 /* Check if bank switch was successful */
826 ret = sdw_ml_sync_bank_switch(bus);
827 if (ret < 0) {
828 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500829 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530830 goto error;
831 }
832
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100833 if (bus->multi_link)
834 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530835 }
836
837 return ret;
838
839error:
840 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530841 bus = m_rt->bus;
842
843 kfree(bus->defer_msg.msg->buf);
844 kfree(bus->defer_msg.msg);
845 }
846
847msg_unlock:
848
849 if (multi_link) {
850 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
851 bus = m_rt->bus;
852 if (mutex_is_locked(&bus->msg_lock))
853 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530854 }
855 }
856
857 return ret;
858}
859
860/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530861 * sdw_release_stream() - Free the assigned stream runtime
862 *
863 * @stream: SoundWire stream runtime
864 *
865 * sdw_release_stream should be called only once per stream
866 */
867void sdw_release_stream(struct sdw_stream_runtime *stream)
868{
869 kfree(stream);
870}
871EXPORT_SYMBOL(sdw_release_stream);
872
873/**
874 * sdw_alloc_stream() - Allocate and return stream runtime
875 *
876 * @stream_name: SoundWire stream name
877 *
878 * Allocates a SoundWire stream runtime instance.
879 * sdw_alloc_stream should be called only once per stream. Typically
880 * invoked from ALSA/ASoC machine/platform driver.
881 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100882struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530883{
884 struct sdw_stream_runtime *stream;
885
886 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
887 if (!stream)
888 return NULL;
889
890 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530891 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530892 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530893 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530894
895 return stream;
896}
897EXPORT_SYMBOL(sdw_alloc_stream);
898
Vinod Koul48949722018-07-27 14:44:14 +0530899static struct sdw_master_runtime
900*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500901 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530902{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500903 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530904
905 /* Retrieve Bus handle if already available */
906 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
907 if (m_rt->bus == bus)
908 return m_rt;
909 }
910
911 return NULL;
912}
913
Sanyog Kale89e59052018-04-26 18:38:08 +0530914/**
915 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
916 *
917 * @bus: SDW bus instance
918 * @stream_config: Stream configuration
919 * @stream: Stream runtime handle.
920 *
921 * This function is to be called with bus_lock held.
922 */
923static struct sdw_master_runtime
924*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500925 struct sdw_stream_config *stream_config,
926 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530927{
928 struct sdw_master_runtime *m_rt;
929
Sanyog Kale89e59052018-04-26 18:38:08 +0530930 /*
931 * check if Master is already allocated (as a result of Slave adding
932 * it first), if so skip allocation and go to configure
933 */
Vinod Koul48949722018-07-27 14:44:14 +0530934 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530935 if (m_rt)
936 goto stream_config;
937
938 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
939 if (!m_rt)
940 return NULL;
941
942 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530943 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530944 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530945 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530946
947 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
948
949stream_config:
950 m_rt->ch_count = stream_config->ch_count;
951 m_rt->bus = bus;
952 m_rt->stream = stream;
953 m_rt->direction = stream_config->direction;
954
955 return m_rt;
956}
957
958/**
959 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
960 *
961 * @slave: Slave handle
962 * @stream_config: Stream configuration
963 * @stream: Stream runtime handle
964 *
965 * This function is to be called with bus_lock held.
966 */
967static struct sdw_slave_runtime
968*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500969 struct sdw_stream_config *stream_config,
970 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530971{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500972 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530973
974 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
975 if (!s_rt)
976 return NULL;
977
Sanyog Kalebbe73792018-04-26 18:38:13 +0530978 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530979 s_rt->ch_count = stream_config->ch_count;
980 s_rt->direction = stream_config->direction;
981 s_rt->slave = slave;
982
983 return s_rt;
984}
985
Sanyog Kalebbe73792018-04-26 18:38:13 +0530986static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500987 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530988{
989 struct sdw_port_runtime *p_rt, *_p_rt;
990
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500991 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530992 list_del(&p_rt->port_node);
993 kfree(p_rt);
994 }
995}
996
997static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500998 struct sdw_slave *slave,
999 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301000{
1001 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301002 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +05301003 struct sdw_slave_runtime *s_rt;
1004
Vinod Koul48949722018-07-27 14:44:14 +05301005 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1006 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301007 if (s_rt->slave != slave)
1008 continue;
1009
1010 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001011 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301012 list_del(&p_rt->port_node);
1013 kfree(p_rt);
1014 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301015 }
1016 }
1017}
1018
Sanyog Kale89e59052018-04-26 18:38:08 +05301019/**
1020 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1021 *
1022 * @slave: Slave handle.
1023 * @stream: Stream runtime handle.
1024 *
1025 * This function is to be called with bus_lock held.
1026 */
1027static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001028 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301029{
1030 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301031 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301032
Vinod Koul48949722018-07-27 14:44:14 +05301033 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1034 /* Retrieve Slave runtime handle */
1035 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001036 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301037 if (s_rt->slave == slave) {
1038 list_del(&s_rt->m_rt_node);
1039 kfree(s_rt);
1040 return;
1041 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301042 }
1043 }
1044}
1045
1046/**
1047 * sdw_release_master_stream() - Free Master runtime handle
1048 *
Vinod Koul48949722018-07-27 14:44:14 +05301049 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301050 * @stream: Stream runtime handle.
1051 *
1052 * This function is to be called with bus_lock held
1053 * It frees the Master runtime handle and associated Slave(s) runtime
1054 * handle. If this is called first then sdw_release_slave_stream() will have
1055 * no effect as Slave(s) runtime handle would already be freed up.
1056 */
Vinod Koul48949722018-07-27 14:44:14 +05301057static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001058 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301059{
Sanyog Kale89e59052018-04-26 18:38:08 +05301060 struct sdw_slave_runtime *s_rt, *_s_rt;
1061
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301062 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1063 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1064 sdw_release_slave_stream(s_rt->slave, stream);
1065 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301066
Vinod Koul48949722018-07-27 14:44:14 +05301067 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301068 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301069 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301070}
1071
1072/**
1073 * sdw_stream_remove_master() - Remove master from sdw_stream
1074 *
1075 * @bus: SDW Bus instance
1076 * @stream: SoundWire stream
1077 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301078 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301079 */
1080int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001081 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301082{
Vinod Koul48949722018-07-27 14:44:14 +05301083 struct sdw_master_runtime *m_rt, *_m_rt;
1084
Sanyog Kale89e59052018-04-26 18:38:08 +05301085 mutex_lock(&bus->bus_lock);
1086
Vinod Koul48949722018-07-27 14:44:14 +05301087 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001088 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301089 if (m_rt->bus != bus)
1090 continue;
1091
1092 sdw_master_port_release(bus, m_rt);
1093 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301094 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301095 }
1096
1097 if (list_empty(&stream->master_list))
1098 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301099
1100 mutex_unlock(&bus->bus_lock);
1101
1102 return 0;
1103}
1104EXPORT_SYMBOL(sdw_stream_remove_master);
1105
1106/**
1107 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1108 *
1109 * @slave: SDW Slave instance
1110 * @stream: SoundWire stream
1111 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301112 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301113 */
1114int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001115 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301116{
1117 mutex_lock(&slave->bus->bus_lock);
1118
Sanyog Kalebbe73792018-04-26 18:38:13 +05301119 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301120 sdw_release_slave_stream(slave, stream);
1121
1122 mutex_unlock(&slave->bus->bus_lock);
1123
1124 return 0;
1125}
1126EXPORT_SYMBOL(sdw_stream_remove_slave);
1127
1128/**
1129 * sdw_config_stream() - Configure the allocated stream
1130 *
1131 * @dev: SDW device
1132 * @stream: SoundWire stream
1133 * @stream_config: Stream configuration for audio stream
1134 * @is_slave: is API called from Slave or Master
1135 *
1136 * This function is to be called with bus_lock held.
1137 */
1138static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001139 struct sdw_stream_runtime *stream,
1140 struct sdw_stream_config *stream_config,
1141 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301142{
1143 /*
1144 * Update the stream rate, channel and bps based on data
1145 * source. For more than one data source (multilink),
1146 * match the rate, bps, stream type and increment number of channels.
1147 *
1148 * If rate/bps is zero, it means the values are not set, so skip
1149 * comparison and allow the value to be set and stored in stream
1150 */
1151 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001152 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001153 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301154 return -EINVAL;
1155 }
1156
1157 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001158 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001159 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301160 return -EINVAL;
1161 }
1162
1163 stream->type = stream_config->type;
1164 stream->params.rate = stream_config->frame_rate;
1165 stream->params.bps = stream_config->bps;
1166
1167 /* TODO: Update this check during Device-device support */
1168 if (is_slave)
1169 stream->params.ch_count += stream_config->ch_count;
1170
1171 return 0;
1172}
1173
Sanyog Kalebbe73792018-04-26 18:38:13 +05301174static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001175 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301176{
1177 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1178 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001179 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301180 return -EINVAL;
1181 }
1182
1183 return 0;
1184}
1185
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001186static struct sdw_port_runtime
1187*sdw_port_alloc(struct device *dev,
1188 struct sdw_port_config *port_config,
1189 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301190{
1191 struct sdw_port_runtime *p_rt;
1192
1193 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1194 if (!p_rt)
1195 return NULL;
1196
1197 p_rt->ch_mask = port_config[port_index].ch_mask;
1198 p_rt->num = port_config[port_index].num;
1199
1200 return p_rt;
1201}
1202
1203static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001204 struct sdw_master_runtime *m_rt,
1205 struct sdw_port_config *port_config,
1206 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301207{
1208 struct sdw_port_runtime *p_rt;
1209 int i;
1210
1211 /* Iterate for number of ports to perform initialization */
1212 for (i = 0; i < num_ports; i++) {
1213 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1214 if (!p_rt)
1215 return -ENOMEM;
1216
1217 /*
1218 * TODO: Check port capabilities for requested
1219 * configuration (audio mode support)
1220 */
1221
1222 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1223 }
1224
1225 return 0;
1226}
1227
1228static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001229 struct sdw_slave_runtime *s_rt,
1230 struct sdw_port_config *port_config,
1231 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301232{
1233 struct sdw_port_runtime *p_rt;
1234 int i, ret;
1235
1236 /* Iterate for number of ports to perform initialization */
1237 for (i = 0; i < num_config; i++) {
1238 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1239 if (!p_rt)
1240 return -ENOMEM;
1241
1242 /*
1243 * TODO: Check valid port range as defined by DisCo/
1244 * slave
1245 */
1246 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1247 if (ret < 0) {
1248 kfree(p_rt);
1249 return ret;
1250 }
1251
1252 /*
1253 * TODO: Check port capabilities for requested
1254 * configuration (audio mode support)
1255 */
1256
1257 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1258 }
1259
1260 return 0;
1261}
1262
Sanyog Kale89e59052018-04-26 18:38:08 +05301263/**
1264 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1265 *
1266 * @bus: SDW Bus instance
1267 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301268 * @port_config: Port configuration for audio stream
1269 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301270 * @stream: SoundWire stream
1271 */
1272int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001273 struct sdw_stream_config *stream_config,
1274 struct sdw_port_config *port_config,
1275 unsigned int num_ports,
1276 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301277{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001278 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301279 int ret;
1280
1281 mutex_lock(&bus->bus_lock);
1282
Shreyas NCce6e74d2018-07-27 14:44:16 +05301283 /*
1284 * For multi link streams, add the second master only if
1285 * the bus supports it.
1286 * Check if bus->multi_link is set
1287 */
1288 if (!bus->multi_link && stream->m_rt_count > 0) {
1289 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001290 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301291 ret = -EINVAL;
1292 goto unlock;
1293 }
1294
Sanyog Kale89e59052018-04-26 18:38:08 +05301295 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1296 if (!m_rt) {
1297 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001298 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001299 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301300 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301301 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301302 }
1303
1304 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1305 if (ret)
1306 goto stream_error;
1307
Sanyog Kalebbe73792018-04-26 18:38:13 +05301308 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1309 if (ret)
1310 goto stream_error;
1311
Shreyas NCce6e74d2018-07-27 14:44:16 +05301312 stream->m_rt_count++;
1313
Shreyas NC3fef1a22018-07-27 14:44:09 +05301314 goto unlock;
1315
Sanyog Kale89e59052018-04-26 18:38:08 +05301316stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301317 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301318unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301319 mutex_unlock(&bus->bus_lock);
1320 return ret;
1321}
1322EXPORT_SYMBOL(sdw_stream_add_master);
1323
1324/**
1325 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1326 *
1327 * @slave: SDW Slave instance
1328 * @stream_config: Stream configuration for audio stream
1329 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301330 * @port_config: Port configuration for audio stream
1331 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301332 *
1333 * It is expected that Slave is added before adding Master
1334 * to the Stream.
1335 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301336 */
1337int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001338 struct sdw_stream_config *stream_config,
1339 struct sdw_port_config *port_config,
1340 unsigned int num_ports,
1341 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301342{
1343 struct sdw_slave_runtime *s_rt;
1344 struct sdw_master_runtime *m_rt;
1345 int ret;
1346
1347 mutex_lock(&slave->bus->bus_lock);
1348
1349 /*
1350 * If this API is invoked by Slave first then m_rt is not valid.
1351 * So, allocate m_rt and add Slave to it.
1352 */
1353 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1354 if (!m_rt) {
1355 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001356 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001357 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301358 ret = -ENOMEM;
1359 goto error;
1360 }
1361
1362 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1363 if (!s_rt) {
1364 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001365 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001366 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301367 ret = -ENOMEM;
1368 goto stream_error;
1369 }
1370
1371 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1372 if (ret)
1373 goto stream_error;
1374
1375 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1376
Sanyog Kalebbe73792018-04-26 18:38:13 +05301377 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1378 if (ret)
1379 goto stream_error;
1380
Shreyas NC0aebe402018-07-27 14:44:08 +05301381 /*
1382 * Change stream state to CONFIGURED on first Slave add.
1383 * Bus is not aware of number of Slave(s) in a stream at this
1384 * point so cannot depend on all Slave(s) to be added in order to
1385 * change stream state to CONFIGURED.
1386 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301387 stream->state = SDW_STREAM_CONFIGURED;
1388 goto error;
1389
1390stream_error:
1391 /*
1392 * we hit error so cleanup the stream, release all Slave(s) and
1393 * Master runtime
1394 */
Vinod Koul48949722018-07-27 14:44:14 +05301395 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301396error:
1397 mutex_unlock(&slave->bus->bus_lock);
1398 return ret;
1399}
1400EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301401
1402/**
1403 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1404 *
1405 * @slave: Slave handle
1406 * @direction: Data direction.
1407 * @port_num: Port number
1408 */
1409struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001410 enum sdw_data_direction direction,
1411 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301412{
1413 struct sdw_dpn_prop *dpn_prop;
1414 u8 num_ports;
1415 int i;
1416
1417 if (direction == SDW_DATA_DIR_TX) {
1418 num_ports = hweight32(slave->prop.source_ports);
1419 dpn_prop = slave->prop.src_dpn_prop;
1420 } else {
1421 num_ports = hweight32(slave->prop.sink_ports);
1422 dpn_prop = slave->prop.sink_dpn_prop;
1423 }
1424
1425 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001426 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301427 return &dpn_prop[i];
1428 }
1429
1430 return NULL;
1431}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301432
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301433/**
1434 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1435 *
1436 * @stream: SoundWire stream
1437 *
1438 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1439 * stream to reconfigure the bus.
1440 * NOTE: This function is called from SoundWire stream ops and is
1441 * expected that a global lock is held before acquiring bus_lock.
1442 */
1443static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1444{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001445 struct sdw_master_runtime *m_rt;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301446 struct sdw_bus *bus = NULL;
1447
1448 /* Iterate for all Master(s) in Master list */
1449 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1450 bus = m_rt->bus;
1451
1452 mutex_lock(&bus->bus_lock);
1453 }
1454}
1455
1456/**
1457 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1458 *
1459 * @stream: SoundWire stream
1460 *
1461 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301462 * NOTE: This function is called from SoundWire stream ops and is
1463 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301464 */
1465static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1466{
1467 struct sdw_master_runtime *m_rt = NULL;
1468 struct sdw_bus *bus = NULL;
1469
1470 /* Iterate for all Master(s) in Master list */
1471 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1472 bus = m_rt->bus;
1473 mutex_unlock(&bus->bus_lock);
1474 }
1475}
1476
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001477static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1478 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301479{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001480 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301481 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001482 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301483 struct sdw_bus_params params;
1484 int ret;
1485
Vinod Koul48949722018-07-27 14:44:14 +05301486 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1487 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1488 bus = m_rt->bus;
1489 prop = &bus->prop;
1490 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301491
Vinod Koul48949722018-07-27 14:44:14 +05301492 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001493 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001494 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301495 return -EINVAL;
1496 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301497
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001498 if (!update_params)
1499 goto program_params;
1500
Vinod Koul48949722018-07-27 14:44:14 +05301501 /* Increment cumulative bus bandwidth */
1502 /* TODO: Update this during Device-Device support */
1503 bus->params.bandwidth += m_rt->stream->params.rate *
1504 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301505
Vinod Koulc7578c12019-08-13 09:35:46 +01001506 /* Compute params */
1507 if (bus->compute_params) {
1508 ret = bus->compute_params(bus);
1509 if (ret < 0) {
1510 dev_err(bus->dev, "Compute params failed: %d",
1511 ret);
1512 return ret;
1513 }
1514 }
1515
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001516program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301517 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001518 ret = sdw_program_params(bus, true);
Vinod Koul48949722018-07-27 14:44:14 +05301519 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001520 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301521 goto restore_params;
1522 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301523 }
1524
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001525 if (!bus) {
1526 pr_err("Configuration error in %s\n", __func__);
1527 return -EINVAL;
1528 }
1529
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301530 ret = do_bank_switch(stream);
1531 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001532 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301533 goto restore_params;
1534 }
1535
Vinod Koul48949722018-07-27 14:44:14 +05301536 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1537 bus = m_rt->bus;
1538
1539 /* Prepare port(s) on the new clock configuration */
1540 ret = sdw_prep_deprep_ports(m_rt, true);
1541 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001542 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001543 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301544 return ret;
1545 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301546 }
1547
1548 stream->state = SDW_STREAM_PREPARED;
1549
1550 return ret;
1551
1552restore_params:
1553 memcpy(&bus->params, &params, sizeof(params));
1554 return ret;
1555}
1556
1557/**
1558 * sdw_prepare_stream() - Prepare SoundWire stream
1559 *
1560 * @stream: Soundwire stream
1561 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001562 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301563 */
1564int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1565{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001566 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001567 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301568
1569 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001570 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301571 return -EINVAL;
1572 }
1573
Vinod Koul48949722018-07-27 14:44:14 +05301574 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301575
Bard Liaoc32464c2020-01-14 17:52:24 -06001576 if (stream->state == SDW_STREAM_PREPARED) {
1577 ret = 0;
1578 goto state_err;
1579 }
1580
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001581 if (stream->state != SDW_STREAM_CONFIGURED &&
1582 stream->state != SDW_STREAM_DEPREPARED &&
1583 stream->state != SDW_STREAM_DISABLED) {
1584 pr_err("%s: %s: inconsistent state state %d\n",
1585 __func__, stream->name, stream->state);
1586 ret = -EINVAL;
1587 goto state_err;
1588 }
1589
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001590 /*
1591 * when the stream is DISABLED, this means sdw_prepare_stream()
1592 * is called as a result of an underflow or a resume operation.
1593 * In this case, the bus parameters shall not be recomputed, but
1594 * still need to be re-applied
1595 */
1596 if (stream->state == SDW_STREAM_DISABLED)
1597 update_params = false;
1598
1599 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301600
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001601state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301602 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301603 return ret;
1604}
1605EXPORT_SYMBOL(sdw_prepare_stream);
1606
1607static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1608{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001609 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301610 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301611 int ret;
1612
Vinod Koul48949722018-07-27 14:44:14 +05301613 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1614 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1615 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301616
Vinod Koul48949722018-07-27 14:44:14 +05301617 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001618 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301619 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001620 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301621 return ret;
1622 }
1623
1624 /* Enable port(s) */
1625 ret = sdw_enable_disable_ports(m_rt, true);
1626 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301627 dev_err(bus->dev,
1628 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301629 return ret;
1630 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301631 }
1632
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001633 if (!bus) {
1634 pr_err("Configuration error in %s\n", __func__);
1635 return -EINVAL;
1636 }
1637
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301638 ret = do_bank_switch(stream);
1639 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001640 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301641 return ret;
1642 }
1643
1644 stream->state = SDW_STREAM_ENABLED;
1645 return 0;
1646}
1647
1648/**
1649 * sdw_enable_stream() - Enable SoundWire stream
1650 *
1651 * @stream: Soundwire stream
1652 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001653 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301654 */
1655int sdw_enable_stream(struct sdw_stream_runtime *stream)
1656{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001657 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301658
1659 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001660 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301661 return -EINVAL;
1662 }
1663
Vinod Koul48949722018-07-27 14:44:14 +05301664 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301665
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001666 if (stream->state != SDW_STREAM_PREPARED &&
1667 stream->state != SDW_STREAM_DISABLED) {
1668 pr_err("%s: %s: inconsistent state state %d\n",
1669 __func__, stream->name, stream->state);
1670 ret = -EINVAL;
1671 goto state_err;
1672 }
1673
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301674 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301675
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001676state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301677 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301678 return ret;
1679}
1680EXPORT_SYMBOL(sdw_enable_stream);
1681
1682static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1683{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001684 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301685 int ret;
1686
Vinod Koul48949722018-07-27 14:44:14 +05301687 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001688 struct sdw_bus *bus = m_rt->bus;
1689
Vinod Koul48949722018-07-27 14:44:14 +05301690 /* Disable port(s) */
1691 ret = sdw_enable_disable_ports(m_rt, false);
1692 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001693 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301694 return ret;
1695 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301696 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301697 stream->state = SDW_STREAM_DISABLED;
1698
Vinod Koul48949722018-07-27 14:44:14 +05301699 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001700 struct sdw_bus *bus = m_rt->bus;
1701
Vinod Koul48949722018-07-27 14:44:14 +05301702 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001703 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301704 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001705 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301706 return ret;
1707 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301708 }
1709
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001710 ret = do_bank_switch(stream);
1711 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001712 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001713 return ret;
1714 }
1715
1716 /* make sure alternate bank (previous current) is also disabled */
1717 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001718 struct sdw_bus *bus = m_rt->bus;
1719
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001720 /* Disable port(s) */
1721 ret = sdw_enable_disable_ports(m_rt, false);
1722 if (ret < 0) {
1723 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1724 return ret;
1725 }
1726 }
1727
1728 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301729}
1730
1731/**
1732 * sdw_disable_stream() - Disable SoundWire stream
1733 *
1734 * @stream: Soundwire stream
1735 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001736 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301737 */
1738int sdw_disable_stream(struct sdw_stream_runtime *stream)
1739{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001740 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301741
1742 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001743 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301744 return -EINVAL;
1745 }
1746
Vinod Koul48949722018-07-27 14:44:14 +05301747 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301748
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001749 if (stream->state != SDW_STREAM_ENABLED) {
1750 pr_err("%s: %s: inconsistent state state %d\n",
1751 __func__, stream->name, stream->state);
1752 ret = -EINVAL;
1753 goto state_err;
1754 }
1755
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301756 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301757
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001758state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301759 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301760 return ret;
1761}
1762EXPORT_SYMBOL(sdw_disable_stream);
1763
1764static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1765{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001766 struct sdw_master_runtime *m_rt;
1767 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301768 int ret = 0;
1769
Vinod Koul48949722018-07-27 14:44:14 +05301770 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1771 bus = m_rt->bus;
1772 /* De-prepare port(s) */
1773 ret = sdw_prep_deprep_ports(m_rt, false);
1774 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301775 dev_err(bus->dev,
1776 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301777 return ret;
1778 }
1779
1780 /* TODO: Update this during Device-Device support */
1781 bus->params.bandwidth -= m_rt->stream->params.rate *
1782 m_rt->ch_count * m_rt->stream->params.bps;
1783
1784 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001785 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301786 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001787 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301788 return ret;
1789 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301790 }
1791
1792 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301793 return do_bank_switch(stream);
1794}
1795
1796/**
1797 * sdw_deprepare_stream() - Deprepare SoundWire stream
1798 *
1799 * @stream: Soundwire stream
1800 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001801 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301802 */
1803int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1804{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001805 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301806
1807 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001808 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301809 return -EINVAL;
1810 }
1811
Vinod Koul48949722018-07-27 14:44:14 +05301812 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001813
1814 if (stream->state != SDW_STREAM_PREPARED &&
1815 stream->state != SDW_STREAM_DISABLED) {
1816 pr_err("%s: %s: inconsistent state state %d\n",
1817 __func__, stream->name, stream->state);
1818 ret = -EINVAL;
1819 goto state_err;
1820 }
1821
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301822 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301823
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001824state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301825 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301826 return ret;
1827}
1828EXPORT_SYMBOL(sdw_deprepare_stream);