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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 5055610e3d30ed90de77525cf240d0066ac616e4 / . / arch / arm / boot / dts / imx28.dtsi
blob: 74aa151cdb45ec094f70f823063d5e73034b710f [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "skeleton.dtsi"
14#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]15
16/ {
17 interrupt-parent = <&icoll>;
18
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]19 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]27 saif0 = &saif0;
28 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]34 spi0 = &ssp1;
35 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]38 };
39
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]40 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]65 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]71 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]72 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]73 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]76 status = "disabled";
77 };
78
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]79 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]80 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]81 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]92 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]93 };
94
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]95 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]96 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]97 interrupts = <27>;
98 status = "disabled";
99 };
100
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]101 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]106 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]107 interrupts = <41>;
108 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]109 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]110 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]117 #address-cells = <1>;
118 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]119 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]120 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]121 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]130 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]131 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]132 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]141 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]142 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]143 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]152 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]153 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]154 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]157 status = "disabled";
158 };
159
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]160 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]163 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]164 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]165
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <127>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio1: gpio@1 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <126>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 gpio2: gpio@2 {
185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupts = <125>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 };
192
193 gpio3: gpio@3 {
194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupts = <124>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio4: gpio@4 {
203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupts = <123>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]211 duart_pins_a: duart@0 {
212 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]213 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]214 MX28_PAD_PWM0__DUART_RX
215 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]216 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]217 fsl,drive-strength = <MXS_DRIVE_4mA>;
218 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]220 };
221
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]222 duart_pins_b: duart@1 {
223 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]224 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]225 MX28_PAD_AUART0_CTS__DUART_RX
226 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]227 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]228 fsl,drive-strength = <MXS_DRIVE_4mA>;
229 fsl,voltage = <MXS_VOLTAGE_HIGH>;
230 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]231 };
232
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]233 duart_4pins_a: duart-4pins@0 {
234 reg = <0>;
235 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]236 MX28_PAD_AUART0_CTS__DUART_RX
237 MX28_PAD_AUART0_RTS__DUART_TX
238 MX28_PAD_AUART0_RX__DUART_CTS
239 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]240 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]241 fsl,drive-strength = <MXS_DRIVE_4mA>;
242 fsl,voltage = <MXS_VOLTAGE_HIGH>;
243 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]244 };
245
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]246 gpmi_pins_a: gpmi-nand@0 {
247 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]248 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]249 MX28_PAD_GPMI_D00__GPMI_D0
250 MX28_PAD_GPMI_D01__GPMI_D1
251 MX28_PAD_GPMI_D02__GPMI_D2
252 MX28_PAD_GPMI_D03__GPMI_D3
253 MX28_PAD_GPMI_D04__GPMI_D4
254 MX28_PAD_GPMI_D05__GPMI_D5
255 MX28_PAD_GPMI_D06__GPMI_D6
256 MX28_PAD_GPMI_D07__GPMI_D7
257 MX28_PAD_GPMI_CE0N__GPMI_CE0N
258 MX28_PAD_GPMI_RDY0__GPMI_READY0
259 MX28_PAD_GPMI_RDN__GPMI_RDN
260 MX28_PAD_GPMI_WRN__GPMI_WRN
261 MX28_PAD_GPMI_ALE__GPMI_ALE
262 MX28_PAD_GPMI_CLE__GPMI_CLE
263 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]264 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]265 fsl,drive-strength = <MXS_DRIVE_4mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]268 };
269
270 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]271 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]272 MX28_PAD_GPMI_RDN__GPMI_RDN
273 MX28_PAD_GPMI_WRN__GPMI_WRN
274 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]275 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]276 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]277 };
278
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]279 auart0_pins_a: auart0@0 {
280 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]281 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]282 MX28_PAD_AUART0_RX__AUART0_RX
283 MX28_PAD_AUART0_TX__AUART0_TX
284 MX28_PAD_AUART0_CTS__AUART0_CTS
285 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]286 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]287 fsl,drive-strength = <MXS_DRIVE_4mA>;
288 fsl,voltage = <MXS_VOLTAGE_HIGH>;
289 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]290 };
291
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]292 auart0_2pins_a: auart0-2pins@0 {
293 reg = <0>;
294 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]295 MX28_PAD_AUART0_RX__AUART0_RX
296 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]297 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]298 fsl,drive-strength = <MXS_DRIVE_4mA>;
299 fsl,voltage = <MXS_VOLTAGE_HIGH>;
300 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]301 };
302
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]303 auart1_pins_a: auart1@0 {
304 reg = <0>;
305 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]306 MX28_PAD_AUART1_RX__AUART1_RX
307 MX28_PAD_AUART1_TX__AUART1_TX
308 MX28_PAD_AUART1_CTS__AUART1_CTS
309 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]310 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]311 fsl,drive-strength = <MXS_DRIVE_4mA>;
312 fsl,voltage = <MXS_VOLTAGE_HIGH>;
313 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]314 };
315
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]316 auart1_2pins_a: auart1-2pins@0 {
317 reg = <0>;
318 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]319 MX28_PAD_AUART1_RX__AUART1_RX
320 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]321 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]322 fsl,drive-strength = <MXS_DRIVE_4mA>;
323 fsl,voltage = <MXS_VOLTAGE_HIGH>;
324 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]325 };
326
327 auart2_2pins_a: auart2-2pins@0 {
328 reg = <0>;
329 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]330 MX28_PAD_SSP2_SCK__AUART2_RX
331 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]332 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]333 fsl,drive-strength = <MXS_DRIVE_4mA>;
334 fsl,voltage = <MXS_VOLTAGE_HIGH>;
335 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]336 };
337
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]338 auart2_2pins_b: auart2-2pins@1 {
339 reg = <1>;
340 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]341 MX28_PAD_AUART2_RX__AUART2_RX
342 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]343 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]347 };
348
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]349 auart2_pins_a: auart2-pins@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
352 MX28_PAD_AUART2_RX__AUART2_RX
353 MX28_PAD_AUART2_TX__AUART2_TX
354 MX28_PAD_AUART2_CTS__AUART2_CTS
355 MX28_PAD_AUART2_RTS__AUART2_RTS
356 >;
357 fsl,drive-strength = <MXS_DRIVE_4mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_DISABLE>;
360 };
361
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]362 auart3_pins_a: auart3@0 {
363 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]364 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]365 MX28_PAD_AUART3_RX__AUART3_RX
366 MX28_PAD_AUART3_TX__AUART3_TX
367 MX28_PAD_AUART3_CTS__AUART3_CTS
368 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]369 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]370 fsl,drive-strength = <MXS_DRIVE_4mA>;
371 fsl,voltage = <MXS_VOLTAGE_HIGH>;
372 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]373 };
374
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]375 auart3_2pins_a: auart3-2pins@0 {
376 reg = <0>;
377 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]378 MX28_PAD_SSP2_MISO__AUART3_RX
379 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]380 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]381 fsl,drive-strength = <MXS_DRIVE_4mA>;
382 fsl,voltage = <MXS_VOLTAGE_HIGH>;
383 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]384 };
385
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]386 auart3_2pins_b: auart3-2pins@1 {
387 reg = <1>;
388 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]389 MX28_PAD_AUART3_RX__AUART3_RX
390 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]391 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]392 fsl,drive-strength = <MXS_DRIVE_4mA>;
393 fsl,voltage = <MXS_VOLTAGE_HIGH>;
394 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]395 };
396
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]397 auart4_2pins_a: auart4@0 {
398 reg = <0>;
399 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]400 MX28_PAD_SSP3_SCK__AUART4_TX
401 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]402 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]403 fsl,drive-strength = <MXS_DRIVE_4mA>;
404 fsl,voltage = <MXS_VOLTAGE_HIGH>;
405 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]406 };
407
Mans Rullgardcfa1dd92015-12-11 13:36:26 +0000[diff] [blame]408 auart4_2pins_b: auart4@1 {
409 reg = <1>;
410 fsl,pinmux-ids = <
411 MX28_PAD_AUART0_CTS__AUART4_RX
412 MX28_PAD_AUART0_RTS__AUART4_TX
413 >;
414 fsl,drive-strength = <MXS_DRIVE_4mA>;
415 fsl,voltage = <MXS_VOLTAGE_HIGH>;
416 fsl,pull-up = <MXS_PULL_DISABLE>;
417 };
418
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]419 mac0_pins_a: mac0@0 {
420 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]421 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]422 MX28_PAD_ENET0_MDC__ENET0_MDC
423 MX28_PAD_ENET0_MDIO__ENET0_MDIO
424 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
425 MX28_PAD_ENET0_RXD0__ENET0_RXD0
426 MX28_PAD_ENET0_RXD1__ENET0_RXD1
427 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
428 MX28_PAD_ENET0_TXD0__ENET0_TXD0
429 MX28_PAD_ENET0_TXD1__ENET0_TXD1
430 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]431 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]432 fsl,drive-strength = <MXS_DRIVE_8mA>;
433 fsl,voltage = <MXS_VOLTAGE_HIGH>;
434 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]435 };
436
Uwe Kleine-König9eb7db12016-04-06 09:32:59 +0200[diff] [blame]437 mac0_pins_b: mac0@1 {
438 reg = <1>;
439 fsl,pinmux-ids = <
440 MX28_PAD_ENET0_MDC__ENET0_MDC
441 MX28_PAD_ENET0_MDIO__ENET0_MDIO
442 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
443 MX28_PAD_ENET0_RXD0__ENET0_RXD0
444 MX28_PAD_ENET0_RXD1__ENET0_RXD1
445 MX28_PAD_ENET0_RXD2__ENET0_RXD2
446 MX28_PAD_ENET0_RXD3__ENET0_RXD3
447 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
448 MX28_PAD_ENET0_TXD0__ENET0_TXD0
449 MX28_PAD_ENET0_TXD1__ENET0_TXD1
450 MX28_PAD_ENET0_TXD2__ENET0_TXD2
451 MX28_PAD_ENET0_TXD3__ENET0_TXD3
452 MX28_PAD_ENET_CLK__CLKCTRL_ENET
453 MX28_PAD_ENET0_COL__ENET0_COL
454 MX28_PAD_ENET0_CRS__ENET0_CRS
455 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
456 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
457 >;
458 fsl,drive-strength = <MXS_DRIVE_8mA>;
459 fsl,voltage = <MXS_VOLTAGE_HIGH>;
460 fsl,pull-up = <MXS_PULL_ENABLE>;
461 };
462
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]463 mac1_pins_a: mac1@0 {
464 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]465 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]466 MX28_PAD_ENET0_CRS__ENET1_RX_EN
467 MX28_PAD_ENET0_RXD2__ENET1_RXD0
468 MX28_PAD_ENET0_RXD3__ENET1_RXD1
469 MX28_PAD_ENET0_COL__ENET1_TX_EN
470 MX28_PAD_ENET0_TXD2__ENET1_TXD0
471 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]472 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]473 fsl,drive-strength = <MXS_DRIVE_8mA>;
474 fsl,voltage = <MXS_VOLTAGE_HIGH>;
475 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]476 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]477
478 mmc0_8bit_pins_a: mmc0-8bit@0 {
479 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]480 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]481 MX28_PAD_SSP0_DATA0__SSP0_D0
482 MX28_PAD_SSP0_DATA1__SSP0_D1
483 MX28_PAD_SSP0_DATA2__SSP0_D2
484 MX28_PAD_SSP0_DATA3__SSP0_D3
485 MX28_PAD_SSP0_DATA4__SSP0_D4
486 MX28_PAD_SSP0_DATA5__SSP0_D5
487 MX28_PAD_SSP0_DATA6__SSP0_D6
488 MX28_PAD_SSP0_DATA7__SSP0_D7
489 MX28_PAD_SSP0_CMD__SSP0_CMD
490 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
491 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]492 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]493 fsl,drive-strength = <MXS_DRIVE_8mA>;
494 fsl,voltage = <MXS_VOLTAGE_HIGH>;
495 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]496 };
497
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]498 mmc0_4bit_pins_a: mmc0-4bit@0 {
499 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]500 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]501 MX28_PAD_SSP0_DATA0__SSP0_D0
502 MX28_PAD_SSP0_DATA1__SSP0_D1
503 MX28_PAD_SSP0_DATA2__SSP0_D2
504 MX28_PAD_SSP0_DATA3__SSP0_D3
505 MX28_PAD_SSP0_CMD__SSP0_CMD
506 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
507 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]508 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]509 fsl,drive-strength = <MXS_DRIVE_8mA>;
510 fsl,voltage = <MXS_VOLTAGE_HIGH>;
511 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]512 };
513
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]514 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]515 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]516 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]517 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]518 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]519 };
520
521 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]522 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]523 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]524 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]525 fsl,drive-strength = <MXS_DRIVE_12mA>;
526 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]527 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]528
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]529 mmc1_4bit_pins_a: mmc1-4bit@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
532 MX28_PAD_GPMI_D00__SSP1_D0
533 MX28_PAD_GPMI_D01__SSP1_D1
534 MX28_PAD_GPMI_D02__SSP1_D2
535 MX28_PAD_GPMI_D03__SSP1_D3
536 MX28_PAD_GPMI_RDY1__SSP1_CMD
537 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
538 MX28_PAD_GPMI_WRN__SSP1_SCK
539 >;
540 fsl,drive-strength = <MXS_DRIVE_8mA>;
541 fsl,voltage = <MXS_VOLTAGE_HIGH>;
542 fsl,pull-up = <MXS_PULL_ENABLE>;
543 };
544
545 mmc1_cd_cfg: mmc1-cd-cfg {
546 fsl,pinmux-ids = <
547 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
548 >;
549 fsl,pull-up = <MXS_PULL_DISABLE>;
550 };
551
552 mmc1_sck_cfg: mmc1-sck-cfg {
553 fsl,pinmux-ids = <
554 MX28_PAD_GPMI_WRN__SSP1_SCK
555 >;
556 fsl,drive-strength = <MXS_DRIVE_12mA>;
557 fsl,pull-up = <MXS_PULL_DISABLE>;
558 };
559
560
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]561 mmc2_4bit_pins_a: mmc2-4bit@0 {
562 reg = <0>;
563 fsl,pinmux-ids = <
564 MX28_PAD_SSP0_DATA4__SSP2_D0
565 MX28_PAD_SSP1_SCK__SSP2_D1
566 MX28_PAD_SSP1_CMD__SSP2_D2
567 MX28_PAD_SSP0_DATA5__SSP2_D3
568 MX28_PAD_SSP0_DATA6__SSP2_CMD
569 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
570 MX28_PAD_SSP0_DATA7__SSP2_SCK
571 >;
572 fsl,drive-strength = <MXS_DRIVE_8mA>;
573 fsl,voltage = <MXS_VOLTAGE_HIGH>;
574 fsl,pull-up = <MXS_PULL_ENABLE>;
575 };
576
577 mmc2_cd_cfg: mmc2-cd-cfg {
578 fsl,pinmux-ids = <
579 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
580 >;
581 fsl,pull-up = <MXS_PULL_DISABLE>;
582 };
583
584 mmc2_sck_cfg: mmc2-sck-cfg {
585 fsl,pinmux-ids = <
586 MX28_PAD_SSP0_DATA7__SSP2_SCK
587 >;
588 fsl,drive-strength = <MXS_DRIVE_12mA>;
589 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]590 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]591
592 i2c0_pins_a: i2c0@0 {
593 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]594 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]595 MX28_PAD_I2C0_SCL__I2C0_SCL
596 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]597 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]598 fsl,drive-strength = <MXS_DRIVE_8mA>;
599 fsl,voltage = <MXS_VOLTAGE_HIGH>;
600 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]601 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]602
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]603 i2c0_pins_b: i2c0@1 {
604 reg = <1>;
605 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]606 MX28_PAD_AUART0_RX__I2C0_SCL
607 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]608 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]609 fsl,drive-strength = <MXS_DRIVE_8mA>;
610 fsl,voltage = <MXS_VOLTAGE_HIGH>;
611 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]612 };
613
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]614 i2c1_pins_a: i2c1@0 {
615 reg = <0>;
616 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]617 MX28_PAD_PWM0__I2C1_SCL
618 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]619 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]620 fsl,drive-strength = <MXS_DRIVE_8mA>;
621 fsl,voltage = <MXS_VOLTAGE_HIGH>;
622 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]623 };
624
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]625 i2c1_pins_b: i2c1@1 {
626 reg = <1>;
627 fsl,pinmux-ids = <
628 MX28_PAD_AUART2_CTS__I2C1_SCL
629 MX28_PAD_AUART2_RTS__I2C1_SDA
630 >;
631 fsl,drive-strength = <MXS_DRIVE_8mA>;
632 fsl,voltage = <MXS_VOLTAGE_HIGH>;
633 fsl,pull-up = <MXS_PULL_ENABLE>;
634 };
635
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]636 saif0_pins_a: saif0@0 {
637 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]638 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]639 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
640 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
641 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
642 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]643 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]644 fsl,drive-strength = <MXS_DRIVE_12mA>;
645 fsl,voltage = <MXS_VOLTAGE_HIGH>;
646 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]647 };
648
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]649 saif0_pins_b: saif0@1 {
650 reg = <1>;
651 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]652 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
653 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
654 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]655 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]656 fsl,drive-strength = <MXS_DRIVE_12mA>;
657 fsl,voltage = <MXS_VOLTAGE_HIGH>;
658 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]659 };
660
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]661 saif1_pins_a: saif1@0 {
662 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]663 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]664 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]665 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]666 fsl,drive-strength = <MXS_DRIVE_12mA>;
667 fsl,voltage = <MXS_VOLTAGE_HIGH>;
668 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]669 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]670
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]671 pwm0_pins_a: pwm0@0 {
672 reg = <0>;
673 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]674 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]675 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]676 fsl,drive-strength = <MXS_DRIVE_4mA>;
677 fsl,voltage = <MXS_VOLTAGE_HIGH>;
678 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]679 };
680
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]681 pwm2_pins_a: pwm2@0 {
682 reg = <0>;
683 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]684 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]685 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]686 fsl,drive-strength = <MXS_DRIVE_4mA>;
687 fsl,voltage = <MXS_VOLTAGE_HIGH>;
688 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]689 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]690
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]691 pwm3_pins_a: pwm3@0 {
692 reg = <0>;
693 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]694 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]695 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]696 fsl,drive-strength = <MXS_DRIVE_4mA>;
697 fsl,voltage = <MXS_VOLTAGE_HIGH>;
698 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]699 };
700
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]701 pwm3_pins_b: pwm3@1 {
702 reg = <1>;
703 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]704 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]705 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]706 fsl,drive-strength = <MXS_DRIVE_4mA>;
707 fsl,voltage = <MXS_VOLTAGE_HIGH>;
708 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]709 };
710
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]711 pwm4_pins_a: pwm4@0 {
712 reg = <0>;
713 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]714 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]715 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]716 fsl,drive-strength = <MXS_DRIVE_4mA>;
717 fsl,voltage = <MXS_VOLTAGE_HIGH>;
718 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]719 };
720
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]721 lcdif_24bit_pins_a: lcdif-24bit@0 {
722 reg = <0>;
723 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]724 MX28_PAD_LCD_D00__LCD_D0
725 MX28_PAD_LCD_D01__LCD_D1
726 MX28_PAD_LCD_D02__LCD_D2
727 MX28_PAD_LCD_D03__LCD_D3
728 MX28_PAD_LCD_D04__LCD_D4
729 MX28_PAD_LCD_D05__LCD_D5
730 MX28_PAD_LCD_D06__LCD_D6
731 MX28_PAD_LCD_D07__LCD_D7
732 MX28_PAD_LCD_D08__LCD_D8
733 MX28_PAD_LCD_D09__LCD_D9
734 MX28_PAD_LCD_D10__LCD_D10
735 MX28_PAD_LCD_D11__LCD_D11
736 MX28_PAD_LCD_D12__LCD_D12
737 MX28_PAD_LCD_D13__LCD_D13
738 MX28_PAD_LCD_D14__LCD_D14
739 MX28_PAD_LCD_D15__LCD_D15
740 MX28_PAD_LCD_D16__LCD_D16
741 MX28_PAD_LCD_D17__LCD_D17
742 MX28_PAD_LCD_D18__LCD_D18
743 MX28_PAD_LCD_D19__LCD_D19
744 MX28_PAD_LCD_D20__LCD_D20
745 MX28_PAD_LCD_D21__LCD_D21
746 MX28_PAD_LCD_D22__LCD_D22
747 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]748 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]749 fsl,drive-strength = <MXS_DRIVE_4mA>;
750 fsl,voltage = <MXS_VOLTAGE_HIGH>;
751 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]752 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]753
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]754 lcdif_18bit_pins_a: lcdif-18bit@0 {
755 reg = <0>;
756 fsl,pinmux-ids = <
757 MX28_PAD_LCD_D00__LCD_D0
758 MX28_PAD_LCD_D01__LCD_D1
759 MX28_PAD_LCD_D02__LCD_D2
760 MX28_PAD_LCD_D03__LCD_D3
761 MX28_PAD_LCD_D04__LCD_D4
762 MX28_PAD_LCD_D05__LCD_D5
763 MX28_PAD_LCD_D06__LCD_D6
764 MX28_PAD_LCD_D07__LCD_D7
765 MX28_PAD_LCD_D08__LCD_D8
766 MX28_PAD_LCD_D09__LCD_D9
767 MX28_PAD_LCD_D10__LCD_D10
768 MX28_PAD_LCD_D11__LCD_D11
769 MX28_PAD_LCD_D12__LCD_D12
770 MX28_PAD_LCD_D13__LCD_D13
771 MX28_PAD_LCD_D14__LCD_D14
772 MX28_PAD_LCD_D15__LCD_D15
773 MX28_PAD_LCD_D16__LCD_D16
774 MX28_PAD_LCD_D17__LCD_D17
775 >;
776 fsl,drive-strength = <MXS_DRIVE_4mA>;
777 fsl,voltage = <MXS_VOLTAGE_HIGH>;
778 fsl,pull-up = <MXS_PULL_DISABLE>;
779 };
780
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]781 lcdif_16bit_pins_a: lcdif-16bit@0 {
782 reg = <0>;
783 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]784 MX28_PAD_LCD_D00__LCD_D0
785 MX28_PAD_LCD_D01__LCD_D1
786 MX28_PAD_LCD_D02__LCD_D2
787 MX28_PAD_LCD_D03__LCD_D3
788 MX28_PAD_LCD_D04__LCD_D4
789 MX28_PAD_LCD_D05__LCD_D5
790 MX28_PAD_LCD_D06__LCD_D6
791 MX28_PAD_LCD_D07__LCD_D7
792 MX28_PAD_LCD_D08__LCD_D8
793 MX28_PAD_LCD_D09__LCD_D9
794 MX28_PAD_LCD_D10__LCD_D10
795 MX28_PAD_LCD_D11__LCD_D11
796 MX28_PAD_LCD_D12__LCD_D12
797 MX28_PAD_LCD_D13__LCD_D13
798 MX28_PAD_LCD_D14__LCD_D14
799 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]800 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]801 fsl,drive-strength = <MXS_DRIVE_4mA>;
802 fsl,voltage = <MXS_VOLTAGE_HIGH>;
803 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]804 };
805
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]806 lcdif_sync_pins_a: lcdif-sync@0 {
807 reg = <0>;
808 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]809 MX28_PAD_LCD_RS__LCD_DOTCLK
810 MX28_PAD_LCD_CS__LCD_ENABLE
811 MX28_PAD_LCD_RD_E__LCD_VSYNC
812 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]813 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]814 fsl,drive-strength = <MXS_DRIVE_4mA>;
815 fsl,voltage = <MXS_VOLTAGE_HIGH>;
816 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]817 };
818
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]819 can0_pins_a: can0@0 {
820 reg = <0>;
821 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]822 MX28_PAD_GPMI_RDY2__CAN0_TX
823 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]824 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]825 fsl,drive-strength = <MXS_DRIVE_4mA>;
826 fsl,voltage = <MXS_VOLTAGE_HIGH>;
827 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]828 };
829
830 can1_pins_a: can1@0 {
831 reg = <0>;
832 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]833 MX28_PAD_GPMI_CE2N__CAN1_TX
834 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]835 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]836 fsl,drive-strength = <MXS_DRIVE_4mA>;
837 fsl,voltage = <MXS_VOLTAGE_HIGH>;
838 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]839 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]840
841 spi2_pins_a: spi2@0 {
842 reg = <0>;
843 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]844 MX28_PAD_SSP2_SCK__SSP2_SCK
845 MX28_PAD_SSP2_MOSI__SSP2_CMD
846 MX28_PAD_SSP2_MISO__SSP2_D0
847 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]848 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]849 fsl,drive-strength = <MXS_DRIVE_8mA>;
850 fsl,voltage = <MXS_VOLTAGE_HIGH>;
851 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]852 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]853
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]854 spi3_pins_a: spi3@0 {
855 reg = <0>;
856 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]857 MX28_PAD_AUART2_RX__SSP3_D4
858 MX28_PAD_AUART2_TX__SSP3_D5
859 MX28_PAD_SSP3_SCK__SSP3_SCK
860 MX28_PAD_SSP3_MOSI__SSP3_CMD
861 MX28_PAD_SSP3_MISO__SSP3_D0
862 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]863 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]864 fsl,drive-strength = <MXS_DRIVE_8mA>;
865 fsl,voltage = <MXS_VOLTAGE_HIGH>;
866 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]867 };
868
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]869 spi3_pins_b: spi3@1 {
870 reg = <1>;
871 fsl,pinmux-ids = <
872 MX28_PAD_SSP3_SCK__SSP3_SCK
873 MX28_PAD_SSP3_MOSI__SSP3_CMD
874 MX28_PAD_SSP3_MISO__SSP3_D0
875 MX28_PAD_SSP3_SS0__SSP3_D3
876 >;
877 fsl,drive-strength = <MXS_DRIVE_8mA>;
878 fsl,voltage = <MXS_VOLTAGE_HIGH>;
879 fsl,pull-up = <MXS_PULL_ENABLE>;
880 };
881
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]882 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]883 reg = <0>;
884 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]885 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]886 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]887 fsl,drive-strength = <MXS_DRIVE_12mA>;
888 fsl,voltage = <MXS_VOLTAGE_HIGH>;
889 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]890 };
891
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]892 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]893 reg = <1>;
894 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]895 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]896 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]897 fsl,drive-strength = <MXS_DRIVE_12mA>;
898 fsl,voltage = <MXS_VOLTAGE_HIGH>;
899 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]900 };
901
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]902 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]903 reg = <0>;
904 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]905 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]906 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]907 fsl,drive-strength = <MXS_DRIVE_12mA>;
908 fsl,voltage = <MXS_VOLTAGE_HIGH>;
909 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]910 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]911
912 usb0_id_pins_a: usb0id@0 {
913 reg = <0>;
914 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]915 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]916 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]917 fsl,drive-strength = <MXS_DRIVE_12mA>;
918 fsl,voltage = <MXS_VOLTAGE_HIGH>;
919 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]920 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]921
922 usb0_id_pins_b: usb0id1@0 {
923 reg = <0>;
924 fsl,pinmux-ids = <
925 MX28_PAD_PWM2__USB0_ID
926 >;
927 fsl,drive-strength = <MXS_DRIVE_12mA>;
928 fsl,voltage = <MXS_VOLTAGE_HIGH>;
929 fsl,pull-up = <MXS_PULL_ENABLE>;
930 };
931
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]932 };
933
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]934 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]935 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]936 reg = <0x8001c000 0x2000>;
937 interrupts = <89>;
938 status = "disabled";
939 };
940
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]941 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]942 reg = <0x80022000 0x2000>;
943 status = "disabled";
944 };
945
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]946 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]947 compatible = "fsl,imx28-dma-apbx";
948 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]949 interrupts = <78 79 66 0
950 80 81 68 69
951 70 71 72 73
952 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]953 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]954 "saif0", "saif1", "i2c0", "i2c1",
955 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
956 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
957 #dma-cells = <1>;
958 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]959 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]960 };
961
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]962 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]963 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]964 reg = <0x80028000 0x2000>;
965 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]966 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]967 };
968
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]969 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]970 reg = <0x8002a000 0x2000>;
971 interrupts = <39>;
972 status = "disabled";
973 };
974
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]975 ocotp: ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]976 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
977 #address-cells = <1>;
978 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]979 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]980 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]981 };
982
983 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]984 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]985 status = "disabled";
986 };
987
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]988 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]989 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]990 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]991 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]992 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]993 dmas = <&dma_apbh 13>;
994 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]995 status = "disabled";
996 };
997
998 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]999 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1000 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1001 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1002 clocks = <&clks 58>, <&clks 58>;
1003 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1004 status = "disabled";
1005 };
1006
1007 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1008 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1009 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1010 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1011 clocks = <&clks 59>, <&clks 59>;
1012 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1013 status = "disabled";
1014 };
1015
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1016 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1017 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1018 status = "disabled";
1019 };
1020
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1021 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1022 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1023 status = "disabled";
1024 };
1025
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1026 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1027 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1028 status = "disabled";
1029 };
1030
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1031 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1032 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1033 status = "disabled";
1034 };
1035
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1036 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1037 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1038 status = "disabled";
1039 };
1040
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1041 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1042 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1043 status = "disabled";
1044 };
1045
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1046 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1047 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1048 status = "disabled";
1049 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1050 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1051
1052 apbx@80040000 {
1053 compatible = "simple-bus";
1054 #address-cells = <1>;
1055 #size-cells = <1>;
1056 reg = <0x80040000 0x40000>;
1057 ranges;
1058
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1059 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]1060 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1061 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1062 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1063 };
1064
1065 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1066 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1067 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1068 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1069 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1070 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1071 dmas = <&dma_apbx 4>;
1072 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1073 status = "disabled";
1074 };
1075
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1076 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1077 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1078 status = "disabled";
1079 };
1080
1081 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1082 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1083 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1084 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1085 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1086 dmas = <&dma_apbx 5>;
1087 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1088 status = "disabled";
1089 };
1090
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1091 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1092 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1093 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1094 interrupts = <10 14 15 16 17 18 19
1095 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1096 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1097 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1098 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1099 };
1100
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1101 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1102 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1103 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1104 dmas = <&dma_apbx 2>;
1105 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1106 status = "disabled";
1107 };
1108
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1109 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1110 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1111 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1112 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1113 };
1114
1115 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1119 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1120 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1121 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1122 dmas = <&dma_apbx 6>;
1123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1124 status = "disabled";
1125 };
1126
1127 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1131 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1132 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1133 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1134 dmas = <&dma_apbx 7>;
1135 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1136 status = "disabled";
1137 };
1138
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1139 pwm: pwm@80064000 {
1140 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1141 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1142 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1143 #pwm-cells = <2>;
1144 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1145 status = "disabled";
1146 };
1147
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1148 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1149 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1150 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1151 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1152 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1153 };
1154
1155 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1156 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1157 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1158 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1159 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1160 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1161 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1162 status = "disabled";
1163 };
1164
1165 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1166 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1167 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1168 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1169 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1170 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1171 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1172 status = "disabled";
1173 };
1174
1175 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1176 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1177 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1178 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1179 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1180 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1181 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1182 status = "disabled";
1183 };
1184
1185 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1186 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1187 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1188 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1189 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1190 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1191 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1192 status = "disabled";
1193 };
1194
1195 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1196 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1197 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1198 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1199 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1200 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1201 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1202 status = "disabled";
1203 };
1204
1205 duart: serial@80074000 {
1206 compatible = "arm,pl011", "arm,primecell";
1207 reg = <0x80074000 0x1000>;
1208 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1209 clocks = <&clks 45>, <&clks 26>;
1210 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1211 status = "disabled";
1212 };
1213
1214 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1215 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1216 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1217 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1218 status = "disabled";
1219 };
1220
1221 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1222 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1223 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1224 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1225 status = "disabled";
1226 };
1227 };
1228 };
1229
1230 ahb@80080000 {
1231 compatible = "simple-bus";
1232 #address-cells = <1>;
1233 #size-cells = <1>;
1234 reg = <0x80080000 0x80000>;
1235 ranges;
1236
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1237 usb0: usb@80080000 {
1238 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1239 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1240 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1241 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1242 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1243 status = "disabled";
1244 };
1245
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1246 usb1: usb@80090000 {
1247 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1248 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1249 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1250 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1251 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1252 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1253 status = "disabled";
1254 };
1255
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1256 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1257 reg = <0x800c0000 0x10000>;
1258 status = "disabled";
1259 };
1260
1261 mac0: ethernet@800f0000 {
1262 compatible = "fsl,imx28-fec";
1263 reg = <0x800f0000 0x4000>;
1264 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1265 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1266 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1267 status = "disabled";
1268 };
1269
1270 mac1: ethernet@800f4000 {
1271 compatible = "fsl,imx28-fec";
1272 reg = <0x800f4000 0x4000>;
1273 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1274 clocks = <&clks 57>, <&clks 57>;
1275 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1276 status = "disabled";
1277 };
1278
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1279 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1280 reg = <0x800f8000 0x8000>;
1281 status = "disabled";
1282 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1283 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1284
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]1285 iio-hwmon {
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1286 compatible = "iio-hwmon";
1287 io-channels = <&lradc 8>;
1288 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1289};