Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | /include/ "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | interrupt-parent = <&icoll>; |
| 16 | |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 17 | aliases { |
Fabio Estevam | 6bf6eb0 | 2013-07-22 17:57:01 -0300 | [diff] [blame] | 18 | ethernet0 = &mac0; |
| 19 | ethernet1 = &mac1; |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 20 | gpio0 = &gpio0; |
| 21 | gpio1 = &gpio1; |
| 22 | gpio2 = &gpio2; |
| 23 | gpio3 = &gpio3; |
| 24 | gpio4 = &gpio4; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 25 | saif0 = &saif0; |
| 26 | saif1 = &saif1; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 27 | serial0 = &auart0; |
| 28 | serial1 = &auart1; |
| 29 | serial2 = &auart2; |
| 30 | serial3 = &auart3; |
| 31 | serial4 = &auart4; |
Fabio Estevam | 6bf6eb0 | 2013-07-22 17:57:01 -0300 | [diff] [blame] | 32 | spi0 = &ssp1; |
| 33 | spi1 = &ssp2; |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 34 | }; |
| 35 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 36 | cpus { |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 37 | #address-cells = <0>; |
| 38 | #size-cells = <0>; |
| 39 | |
| 40 | cpu { |
| 41 | compatible = "arm,arm926ej-s"; |
| 42 | device_type = "cpu"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 43 | }; |
| 44 | }; |
| 45 | |
| 46 | apb@80000000 { |
| 47 | compatible = "simple-bus"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | reg = <0x80000000 0x80000>; |
| 51 | ranges; |
| 52 | |
| 53 | apbh@80000000 { |
| 54 | compatible = "simple-bus"; |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <1>; |
| 57 | reg = <0x80000000 0x3c900>; |
| 58 | ranges; |
| 59 | |
| 60 | icoll: interrupt-controller@80000000 { |
Shawn Guo | 83a84ef | 2012-08-20 21:34:56 +0800 | [diff] [blame] | 61 | compatible = "fsl,imx28-icoll", "fsl,icoll"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 62 | interrupt-controller; |
| 63 | #interrupt-cells = <1>; |
| 64 | reg = <0x80000000 0x2000>; |
| 65 | }; |
| 66 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 67 | hsadc: hsadc@80002000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 68 | reg = <0x80002000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 69 | interrupts = <13>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 70 | dmas = <&dma_apbh 12>; |
| 71 | dma-names = "rx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 72 | status = "disabled"; |
| 73 | }; |
| 74 | |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 75 | dma_apbh: dma-apbh@80004000 { |
Dong Aisheng | 84f3570 | 2012-05-04 20:12:19 +0800 | [diff] [blame] | 76 | compatible = "fsl,imx28-dma-apbh"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 77 | reg = <0x80004000 0x2000>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 78 | interrupts = <82 83 84 85 |
| 79 | 88 88 88 88 |
| 80 | 88 88 88 88 |
| 81 | 87 86 0 0>; |
| 82 | interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", |
| 83 | "gpmi0", "gmpi1", "gpmi2", "gmpi3", |
| 84 | "gpmi4", "gmpi5", "gpmi6", "gmpi7", |
| 85 | "hsadc", "lcdif", "empty", "empty"; |
| 86 | #dma-cells = <1>; |
| 87 | dma-channels = <16>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 88 | clocks = <&clks 25>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 89 | }; |
| 90 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 91 | perfmon: perfmon@80006000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 92 | reg = <0x80006000 0x800>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 93 | interrupts = <27>; |
| 94 | status = "disabled"; |
| 95 | }; |
| 96 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 97 | gpmi: gpmi-nand@8000c000 { |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 98 | compatible = "fsl,imx28-gpmi-nand"; |
| 99 | #address-cells = <1>; |
| 100 | #size-cells = <1>; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 101 | reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 102 | reg-names = "gpmi-nand", "bch"; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 103 | interrupts = <41>; |
| 104 | interrupt-names = "bch"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 105 | clocks = <&clks 50>; |
Huang Shijie | b644255 | 2012-10-10 18:27:09 +0800 | [diff] [blame] | 106 | clock-names = "gpmi_io"; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 107 | dmas = <&dma_apbh 4>; |
| 108 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 109 | status = "disabled"; |
| 110 | }; |
| 111 | |
| 112 | ssp0: ssp@80010000 { |
Maxime Ripard | 41bf570 | 2012-09-04 10:44:02 +0200 | [diff] [blame] | 113 | #address-cells = <1>; |
| 114 | #size-cells = <0>; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 115 | reg = <0x80010000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 116 | interrupts = <96>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 117 | clocks = <&clks 46>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 118 | dmas = <&dma_apbh 0>; |
| 119 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 120 | status = "disabled"; |
| 121 | }; |
| 122 | |
| 123 | ssp1: ssp@80012000 { |
Maxime Ripard | 41bf570 | 2012-09-04 10:44:02 +0200 | [diff] [blame] | 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 126 | reg = <0x80012000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 127 | interrupts = <97>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 128 | clocks = <&clks 47>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 129 | dmas = <&dma_apbh 1>; |
| 130 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 131 | status = "disabled"; |
| 132 | }; |
| 133 | |
| 134 | ssp2: ssp@80014000 { |
Maxime Ripard | 41bf570 | 2012-09-04 10:44:02 +0200 | [diff] [blame] | 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 137 | reg = <0x80014000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 138 | interrupts = <98>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 139 | clocks = <&clks 48>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 140 | dmas = <&dma_apbh 2>; |
| 141 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 142 | status = "disabled"; |
| 143 | }; |
| 144 | |
| 145 | ssp3: ssp@80016000 { |
Maxime Ripard | 41bf570 | 2012-09-04 10:44:02 +0200 | [diff] [blame] | 146 | #address-cells = <1>; |
| 147 | #size-cells = <0>; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 148 | reg = <0x80016000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 149 | interrupts = <99>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 150 | clocks = <&clks 49>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 151 | dmas = <&dma_apbh 3>; |
| 152 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 153 | status = "disabled"; |
| 154 | }; |
| 155 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 156 | pinctrl: pinctrl@80018000 { |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 157 | #address-cells = <1>; |
| 158 | #size-cells = <0>; |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 159 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 160 | reg = <0x80018000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 161 | |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 162 | gpio0: gpio@0 { |
| 163 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 164 | interrupts = <127>; |
| 165 | gpio-controller; |
| 166 | #gpio-cells = <2>; |
| 167 | interrupt-controller; |
| 168 | #interrupt-cells = <2>; |
| 169 | }; |
| 170 | |
| 171 | gpio1: gpio@1 { |
| 172 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 173 | interrupts = <126>; |
| 174 | gpio-controller; |
| 175 | #gpio-cells = <2>; |
| 176 | interrupt-controller; |
| 177 | #interrupt-cells = <2>; |
| 178 | }; |
| 179 | |
| 180 | gpio2: gpio@2 { |
| 181 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 182 | interrupts = <125>; |
| 183 | gpio-controller; |
| 184 | #gpio-cells = <2>; |
| 185 | interrupt-controller; |
| 186 | #interrupt-cells = <2>; |
| 187 | }; |
| 188 | |
| 189 | gpio3: gpio@3 { |
| 190 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 191 | interrupts = <124>; |
| 192 | gpio-controller; |
| 193 | #gpio-cells = <2>; |
| 194 | interrupt-controller; |
| 195 | #interrupt-cells = <2>; |
| 196 | }; |
| 197 | |
| 198 | gpio4: gpio@4 { |
| 199 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 200 | interrupts = <123>; |
| 201 | gpio-controller; |
| 202 | #gpio-cells = <2>; |
| 203 | interrupt-controller; |
| 204 | #interrupt-cells = <2>; |
| 205 | }; |
| 206 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 207 | duart_pins_a: duart@0 { |
| 208 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 209 | fsl,pinmux-ids = < |
| 210 | 0x3102 /* MX28_PAD_PWM0__DUART_RX */ |
| 211 | 0x3112 /* MX28_PAD_PWM1__DUART_TX */ |
| 212 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 213 | fsl,drive-strength = <0>; |
| 214 | fsl,voltage = <1>; |
| 215 | fsl,pull-up = <0>; |
| 216 | }; |
| 217 | |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 218 | duart_pins_b: duart@1 { |
| 219 | reg = <1>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 220 | fsl,pinmux-ids = < |
| 221 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ |
| 222 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ |
| 223 | >; |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 224 | fsl,drive-strength = <0>; |
| 225 | fsl,voltage = <1>; |
| 226 | fsl,pull-up = <0>; |
| 227 | }; |
| 228 | |
Shawn Guo | e1a4d18 | 2012-07-09 12:34:35 +0800 | [diff] [blame] | 229 | duart_4pins_a: duart-4pins@0 { |
| 230 | reg = <0>; |
| 231 | fsl,pinmux-ids = < |
| 232 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ |
| 233 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ |
| 234 | 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ |
| 235 | 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ |
| 236 | >; |
| 237 | fsl,drive-strength = <0>; |
| 238 | fsl,voltage = <1>; |
| 239 | fsl,pull-up = <0>; |
| 240 | }; |
| 241 | |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 242 | gpmi_pins_a: gpmi-nand@0 { |
| 243 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 244 | fsl,pinmux-ids = < |
| 245 | 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ |
| 246 | 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ |
| 247 | 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ |
| 248 | 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ |
| 249 | 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ |
| 250 | 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ |
| 251 | 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ |
| 252 | 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ |
| 253 | 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 254 | 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 255 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ |
| 256 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ |
| 257 | 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ |
| 258 | 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ |
| 259 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ |
| 260 | >; |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 261 | fsl,drive-strength = <0>; |
| 262 | fsl,voltage = <1>; |
| 263 | fsl,pull-up = <0>; |
| 264 | }; |
| 265 | |
| 266 | gpmi_status_cfg: gpmi-status-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 267 | fsl,pinmux-ids = < |
| 268 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ |
| 269 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ |
| 270 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ |
| 271 | >; |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 272 | fsl,drive-strength = <2>; |
| 273 | }; |
| 274 | |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 275 | auart0_pins_a: auart0@0 { |
| 276 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 277 | fsl,pinmux-ids = < |
| 278 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ |
| 279 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ |
| 280 | 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ |
| 281 | 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ |
| 282 | >; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 283 | fsl,drive-strength = <0>; |
| 284 | fsl,voltage = <1>; |
| 285 | fsl,pull-up = <0>; |
| 286 | }; |
| 287 | |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 288 | auart0_2pins_a: auart0-2pins@0 { |
| 289 | reg = <0>; |
| 290 | fsl,pinmux-ids = < |
| 291 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ |
| 292 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ |
| 293 | >; |
| 294 | fsl,drive-strength = <0>; |
| 295 | fsl,voltage = <1>; |
| 296 | fsl,pull-up = <0>; |
| 297 | }; |
| 298 | |
Shawn Guo | e1a4d18 | 2012-07-09 12:34:35 +0800 | [diff] [blame] | 299 | auart1_pins_a: auart1@0 { |
| 300 | reg = <0>; |
| 301 | fsl,pinmux-ids = < |
| 302 | 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ |
| 303 | 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ |
| 304 | 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ |
| 305 | 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ |
| 306 | >; |
| 307 | fsl,drive-strength = <0>; |
| 308 | fsl,voltage = <1>; |
| 309 | fsl,pull-up = <0>; |
| 310 | }; |
| 311 | |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 312 | auart1_2pins_a: auart1-2pins@0 { |
| 313 | reg = <0>; |
| 314 | fsl,pinmux-ids = < |
| 315 | 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ |
| 316 | 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ |
| 317 | >; |
| 318 | fsl,drive-strength = <0>; |
| 319 | fsl,voltage = <1>; |
| 320 | fsl,pull-up = <0>; |
| 321 | }; |
| 322 | |
| 323 | auart2_2pins_a: auart2-2pins@0 { |
| 324 | reg = <0>; |
| 325 | fsl,pinmux-ids = < |
| 326 | 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ |
| 327 | 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ |
| 328 | >; |
| 329 | fsl,drive-strength = <0>; |
| 330 | fsl,voltage = <1>; |
| 331 | fsl,pull-up = <0>; |
| 332 | }; |
| 333 | |
Eric Bénard | f8040cf | 2013-04-08 14:57:31 +0200 | [diff] [blame] | 334 | auart2_2pins_b: auart2-2pins@1 { |
| 335 | reg = <1>; |
| 336 | fsl,pinmux-ids = < |
| 337 | 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ |
| 338 | 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ |
| 339 | >; |
| 340 | fsl,drive-strength = <0>; |
| 341 | fsl,voltage = <1>; |
| 342 | fsl,pull-up = <0>; |
| 343 | }; |
| 344 | |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 345 | auart3_pins_a: auart3@0 { |
| 346 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 347 | fsl,pinmux-ids = < |
| 348 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ |
| 349 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ |
| 350 | 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ |
| 351 | 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ |
| 352 | >; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 353 | fsl,drive-strength = <0>; |
| 354 | fsl,voltage = <1>; |
| 355 | fsl,pull-up = <0>; |
| 356 | }; |
| 357 | |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 358 | auart3_2pins_a: auart3-2pins@0 { |
| 359 | reg = <0>; |
| 360 | fsl,pinmux-ids = < |
| 361 | 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ |
| 362 | 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ |
| 363 | >; |
| 364 | fsl,drive-strength = <0>; |
| 365 | fsl,voltage = <1>; |
| 366 | fsl,pull-up = <0>; |
| 367 | }; |
| 368 | |
Eric Bénard | 4812e74 | 2013-04-08 14:57:32 +0200 | [diff] [blame] | 369 | auart3_2pins_b: auart3-2pins@1 { |
| 370 | reg = <1>; |
| 371 | fsl,pinmux-ids = < |
| 372 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ |
| 373 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ |
| 374 | >; |
| 375 | fsl,drive-strength = <0>; |
| 376 | fsl,voltage = <1>; |
| 377 | fsl,pull-up = <0>; |
| 378 | }; |
| 379 | |
Eric Bénard | 33678d1 | 2013-04-08 14:57:33 +0200 | [diff] [blame] | 380 | auart4_2pins_a: auart4@0 { |
| 381 | reg = <0>; |
| 382 | fsl,pinmux-ids = < |
| 383 | 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ |
| 384 | 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ |
| 385 | >; |
| 386 | fsl,drive-strength = <0>; |
| 387 | fsl,voltage = <1>; |
| 388 | fsl,pull-up = <0>; |
| 389 | }; |
| 390 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 391 | mac0_pins_a: mac0@0 { |
| 392 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 393 | fsl,pinmux-ids = < |
| 394 | 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ |
| 395 | 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ |
| 396 | 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ |
| 397 | 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ |
| 398 | 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ |
| 399 | 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ |
| 400 | 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ |
| 401 | 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ |
| 402 | 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ |
| 403 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 404 | fsl,drive-strength = <1>; |
| 405 | fsl,voltage = <1>; |
| 406 | fsl,pull-up = <1>; |
| 407 | }; |
| 408 | |
| 409 | mac1_pins_a: mac1@0 { |
| 410 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 411 | fsl,pinmux-ids = < |
| 412 | 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ |
| 413 | 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ |
| 414 | 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ |
| 415 | 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ |
| 416 | 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ |
| 417 | 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ |
| 418 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 419 | fsl,drive-strength = <1>; |
| 420 | fsl,voltage = <1>; |
| 421 | fsl,pull-up = <1>; |
| 422 | }; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 423 | |
| 424 | mmc0_8bit_pins_a: mmc0-8bit@0 { |
| 425 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 426 | fsl,pinmux-ids = < |
| 427 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ |
| 428 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ |
| 429 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ |
| 430 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ |
| 431 | 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ |
| 432 | 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ |
| 433 | 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ |
| 434 | 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ |
| 435 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ |
| 436 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 437 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 438 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 439 | fsl,drive-strength = <1>; |
| 440 | fsl,voltage = <1>; |
| 441 | fsl,pull-up = <1>; |
| 442 | }; |
| 443 | |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 444 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
| 445 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 446 | fsl,pinmux-ids = < |
| 447 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ |
| 448 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ |
| 449 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ |
| 450 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ |
| 451 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ |
| 452 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 453 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 454 | >; |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 455 | fsl,drive-strength = <1>; |
| 456 | fsl,voltage = <1>; |
| 457 | fsl,pull-up = <1>; |
| 458 | }; |
| 459 | |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 460 | mmc0_cd_cfg: mmc0-cd-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 461 | fsl,pinmux-ids = < |
| 462 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 463 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 464 | fsl,pull-up = <0>; |
| 465 | }; |
| 466 | |
| 467 | mmc0_sck_cfg: mmc0-sck-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 468 | fsl,pinmux-ids = < |
| 469 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 470 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 471 | fsl,drive-strength = <2>; |
| 472 | fsl,pull-up = <0>; |
| 473 | }; |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 474 | |
| 475 | i2c0_pins_a: i2c0@0 { |
| 476 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 477 | fsl,pinmux-ids = < |
| 478 | 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ |
| 479 | 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ |
| 480 | >; |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 481 | fsl,drive-strength = <1>; |
| 482 | fsl,voltage = <1>; |
| 483 | fsl,pull-up = <1>; |
| 484 | }; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 485 | |
Maxime Ripard | 5c697ea | 2012-08-23 10:42:29 +0200 | [diff] [blame] | 486 | i2c0_pins_b: i2c0@1 { |
| 487 | reg = <1>; |
| 488 | fsl,pinmux-ids = < |
| 489 | 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ |
| 490 | 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ |
| 491 | >; |
| 492 | fsl,drive-strength = <1>; |
| 493 | fsl,voltage = <1>; |
| 494 | fsl,pull-up = <1>; |
| 495 | }; |
| 496 | |
Maxime Ripard | de7e934 | 2012-08-31 16:00:40 +0200 | [diff] [blame] | 497 | i2c1_pins_a: i2c1@0 { |
| 498 | reg = <0>; |
| 499 | fsl,pinmux-ids = < |
| 500 | 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ |
| 501 | 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ |
| 502 | >; |
| 503 | fsl,drive-strength = <1>; |
| 504 | fsl,voltage = <1>; |
| 505 | fsl,pull-up = <1>; |
| 506 | }; |
| 507 | |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 508 | saif0_pins_a: saif0@0 { |
| 509 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 510 | fsl,pinmux-ids = < |
| 511 | 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ |
| 512 | 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ |
| 513 | 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ |
| 514 | 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ |
| 515 | >; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 516 | fsl,drive-strength = <2>; |
| 517 | fsl,voltage = <1>; |
| 518 | fsl,pull-up = <1>; |
| 519 | }; |
| 520 | |
Lothar Waßmann | 2e1dd9f | 2013-08-08 14:51:22 +0200 | [diff] [blame] | 521 | saif0_pins_b: saif0@1 { |
| 522 | reg = <1>; |
| 523 | fsl,pinmux-ids = < |
| 524 | 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ |
| 525 | 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ |
| 526 | 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ |
| 527 | >; |
| 528 | fsl,drive-strength = <2>; |
| 529 | fsl,voltage = <1>; |
| 530 | fsl,pull-up = <1>; |
| 531 | }; |
| 532 | |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 533 | saif1_pins_a: saif1@0 { |
| 534 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 535 | fsl,pinmux-ids = < |
| 536 | 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ |
| 537 | >; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 538 | fsl,drive-strength = <2>; |
| 539 | fsl,voltage = <1>; |
| 540 | fsl,pull-up = <1>; |
| 541 | }; |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 542 | |
Shawn Guo | e1a4d18 | 2012-07-09 12:34:35 +0800 | [diff] [blame] | 543 | pwm0_pins_a: pwm0@0 { |
| 544 | reg = <0>; |
| 545 | fsl,pinmux-ids = < |
| 546 | 0x3100 /* MX28_PAD_PWM0__PWM_0 */ |
| 547 | >; |
| 548 | fsl,drive-strength = <0>; |
| 549 | fsl,voltage = <1>; |
| 550 | fsl,pull-up = <0>; |
| 551 | }; |
| 552 | |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 553 | pwm2_pins_a: pwm2@0 { |
| 554 | reg = <0>; |
| 555 | fsl,pinmux-ids = < |
| 556 | 0x3120 /* MX28_PAD_PWM2__PWM_2 */ |
| 557 | >; |
| 558 | fsl,drive-strength = <0>; |
| 559 | fsl,voltage = <1>; |
| 560 | fsl,pull-up = <0>; |
| 561 | }; |
Shawn Guo | a915ee4 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 562 | |
Julien Boibessot | 2bde51c | 2012-10-27 12:15:46 +0200 | [diff] [blame] | 563 | pwm3_pins_a: pwm3@0 { |
| 564 | reg = <0>; |
| 565 | fsl,pinmux-ids = < |
| 566 | 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ |
| 567 | >; |
| 568 | fsl,drive-strength = <0>; |
| 569 | fsl,voltage = <1>; |
| 570 | fsl,pull-up = <0>; |
| 571 | }; |
| 572 | |
Maxime Ripard | d248620 | 2013-01-25 09:54:06 +0100 | [diff] [blame] | 573 | pwm3_pins_b: pwm3@1 { |
| 574 | reg = <1>; |
| 575 | fsl,pinmux-ids = < |
| 576 | 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */ |
| 577 | >; |
| 578 | fsl,drive-strength = <0>; |
| 579 | fsl,voltage = <1>; |
| 580 | fsl,pull-up = <0>; |
| 581 | }; |
| 582 | |
Maxime Ripard | 2f44211 | 2012-08-23 10:42:30 +0200 | [diff] [blame] | 583 | pwm4_pins_a: pwm4@0 { |
| 584 | reg = <0>; |
| 585 | fsl,pinmux-ids = < |
| 586 | 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ |
| 587 | >; |
| 588 | fsl,drive-strength = <0>; |
| 589 | fsl,voltage = <1>; |
| 590 | fsl,pull-up = <0>; |
| 591 | }; |
| 592 | |
Shawn Guo | a915ee4 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 593 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
| 594 | reg = <0>; |
| 595 | fsl,pinmux-ids = < |
| 596 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ |
| 597 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ |
| 598 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ |
| 599 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ |
| 600 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ |
| 601 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ |
| 602 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ |
| 603 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ |
| 604 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ |
| 605 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ |
| 606 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ |
| 607 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ |
| 608 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ |
| 609 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ |
| 610 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ |
| 611 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ |
| 612 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ |
| 613 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ |
| 614 | 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ |
| 615 | 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ |
| 616 | 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ |
| 617 | 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ |
| 618 | 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ |
| 619 | 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ |
Shawn Guo | a915ee4 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 620 | >; |
| 621 | fsl,drive-strength = <0>; |
| 622 | fsl,voltage = <1>; |
| 623 | fsl,pull-up = <0>; |
| 624 | }; |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame] | 625 | |
Gwenhael Goavec-Merou | 4ced2a4 | 2012-11-01 17:50:59 +0100 | [diff] [blame] | 626 | lcdif_16bit_pins_a: lcdif-16bit@0 { |
| 627 | reg = <0>; |
| 628 | fsl,pinmux-ids = < |
| 629 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ |
| 630 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ |
| 631 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ |
| 632 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ |
| 633 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ |
| 634 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ |
| 635 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ |
| 636 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ |
| 637 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ |
| 638 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ |
| 639 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ |
| 640 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ |
| 641 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ |
| 642 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ |
| 643 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ |
| 644 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ |
| 645 | >; |
| 646 | fsl,drive-strength = <0>; |
| 647 | fsl,voltage = <1>; |
| 648 | fsl,pull-up = <0>; |
| 649 | }; |
| 650 | |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame] | 651 | can0_pins_a: can0@0 { |
| 652 | reg = <0>; |
| 653 | fsl,pinmux-ids = < |
| 654 | 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ |
| 655 | 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ |
| 656 | >; |
| 657 | fsl,drive-strength = <0>; |
| 658 | fsl,voltage = <1>; |
| 659 | fsl,pull-up = <0>; |
| 660 | }; |
| 661 | |
| 662 | can1_pins_a: can1@0 { |
| 663 | reg = <0>; |
| 664 | fsl,pinmux-ids = < |
| 665 | 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ |
| 666 | 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ |
| 667 | >; |
| 668 | fsl,drive-strength = <0>; |
| 669 | fsl,voltage = <1>; |
| 670 | fsl,pull-up = <0>; |
| 671 | }; |
Marek Vasut | 7f12221 | 2012-08-25 01:51:37 +0200 | [diff] [blame] | 672 | |
| 673 | spi2_pins_a: spi2@0 { |
| 674 | reg = <0>; |
| 675 | fsl,pinmux-ids = < |
| 676 | 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ |
| 677 | 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ |
| 678 | 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ |
| 679 | 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ |
| 680 | >; |
| 681 | fsl,drive-strength = <1>; |
| 682 | fsl,voltage = <1>; |
| 683 | fsl,pull-up = <1>; |
| 684 | }; |
Marek Vasut | bb2f126 | 2012-08-25 01:51:38 +0200 | [diff] [blame] | 685 | |
Lothar Waßmann | 3314d2b | 2013-08-08 14:51:23 +0200 | [diff] [blame^] | 686 | spi3_pins_a: spi3@0 { |
| 687 | reg = <0>; |
| 688 | fsl,pinmux-ids = < |
| 689 | 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */ |
| 690 | 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */ |
| 691 | 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */ |
| 692 | 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */ |
| 693 | 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */ |
| 694 | 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */ |
| 695 | >; |
| 696 | fsl,drive-strength = <1>; |
| 697 | fsl,voltage = <1>; |
| 698 | fsl,pull-up = <0>; |
| 699 | }; |
| 700 | |
Marek Vasut | bb2f126 | 2012-08-25 01:51:38 +0200 | [diff] [blame] | 701 | usbphy0_pins_a: usbphy0@0 { |
| 702 | reg = <0>; |
| 703 | fsl,pinmux-ids = < |
| 704 | 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ |
| 705 | >; |
| 706 | fsl,drive-strength = <2>; |
| 707 | fsl,voltage = <1>; |
| 708 | fsl,pull-up = <0>; |
| 709 | }; |
| 710 | |
| 711 | usbphy0_pins_b: usbphy0@1 { |
| 712 | reg = <1>; |
| 713 | fsl,pinmux-ids = < |
| 714 | 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ |
| 715 | >; |
| 716 | fsl,drive-strength = <2>; |
| 717 | fsl,voltage = <1>; |
| 718 | fsl,pull-up = <0>; |
| 719 | }; |
| 720 | |
| 721 | usbphy1_pins_a: usbphy1@0 { |
| 722 | reg = <0>; |
| 723 | fsl,pinmux-ids = < |
| 724 | 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ |
| 725 | >; |
| 726 | fsl,drive-strength = <2>; |
| 727 | fsl,voltage = <1>; |
| 728 | fsl,pull-up = <0>; |
| 729 | }; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 730 | }; |
| 731 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 732 | digctl: digctl@8001c000 { |
Fabio Estevam | 115581c | 2013-06-04 10:18:44 -0300 | [diff] [blame] | 733 | compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 734 | reg = <0x8001c000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 735 | interrupts = <89>; |
| 736 | status = "disabled"; |
| 737 | }; |
| 738 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 739 | etm: etm@80022000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 740 | reg = <0x80022000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 741 | status = "disabled"; |
| 742 | }; |
| 743 | |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 744 | dma_apbx: dma-apbx@80024000 { |
Dong Aisheng | 84f3570 | 2012-05-04 20:12:19 +0800 | [diff] [blame] | 745 | compatible = "fsl,imx28-dma-apbx"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 746 | reg = <0x80024000 0x2000>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 747 | interrupts = <78 79 66 0 |
| 748 | 80 81 68 69 |
| 749 | 70 71 72 73 |
| 750 | 74 75 76 77>; |
| 751 | interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", |
| 752 | "saif0", "saif1", "i2c0", "i2c1", |
| 753 | "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", |
| 754 | "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; |
| 755 | #dma-cells = <1>; |
| 756 | dma-channels = <16>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 757 | clocks = <&clks 26>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 758 | }; |
| 759 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 760 | dcp: dcp@80028000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 761 | reg = <0x80028000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 762 | interrupts = <52 53 54>; |
Tobias Rauter | 519d8b1 | 2013-05-19 21:59:38 +0200 | [diff] [blame] | 763 | compatible = "fsl-dcp"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 764 | }; |
| 765 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 766 | pxp: pxp@8002a000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 767 | reg = <0x8002a000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 768 | interrupts = <39>; |
| 769 | status = "disabled"; |
| 770 | }; |
| 771 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 772 | ocotp: ocotp@8002c000 { |
Shawn Guo | 69d75a0 | 2013-03-29 09:59:28 +0800 | [diff] [blame] | 773 | compatible = "fsl,ocotp"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 774 | reg = <0x8002c000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 775 | status = "disabled"; |
| 776 | }; |
| 777 | |
| 778 | axi-ahb@8002e000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 779 | reg = <0x8002e000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 780 | status = "disabled"; |
| 781 | }; |
| 782 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 783 | lcdif: lcdif@80030000 { |
Shawn Guo | a915ee4 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 784 | compatible = "fsl,imx28-lcdif"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 785 | reg = <0x80030000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 786 | interrupts = <38>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 787 | clocks = <&clks 55>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 788 | dmas = <&dma_apbh 13>; |
| 789 | dma-names = "rx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 790 | status = "disabled"; |
| 791 | }; |
| 792 | |
| 793 | can0: can@80032000 { |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame] | 794 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 795 | reg = <0x80032000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 796 | interrupts = <8>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 797 | clocks = <&clks 58>, <&clks 58>; |
| 798 | clock-names = "ipg", "per"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 799 | status = "disabled"; |
| 800 | }; |
| 801 | |
| 802 | can1: can@80034000 { |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame] | 803 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 804 | reg = <0x80034000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 805 | interrupts = <9>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 806 | clocks = <&clks 59>, <&clks 59>; |
| 807 | clock-names = "ipg", "per"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 808 | status = "disabled"; |
| 809 | }; |
| 810 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 811 | simdbg: simdbg@8003c000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 812 | reg = <0x8003c000 0x200>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 813 | status = "disabled"; |
| 814 | }; |
| 815 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 816 | simgpmisel: simgpmisel@8003c200 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 817 | reg = <0x8003c200 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 818 | status = "disabled"; |
| 819 | }; |
| 820 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 821 | simsspsel: simsspsel@8003c300 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 822 | reg = <0x8003c300 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 823 | status = "disabled"; |
| 824 | }; |
| 825 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 826 | simmemsel: simmemsel@8003c400 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 827 | reg = <0x8003c400 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 828 | status = "disabled"; |
| 829 | }; |
| 830 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 831 | gpiomon: gpiomon@8003c500 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 832 | reg = <0x8003c500 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 833 | status = "disabled"; |
| 834 | }; |
| 835 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 836 | simenet: simenet@8003c700 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 837 | reg = <0x8003c700 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 838 | status = "disabled"; |
| 839 | }; |
| 840 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 841 | armjtag: armjtag@8003c800 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 842 | reg = <0x8003c800 0x100>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 843 | status = "disabled"; |
| 844 | }; |
Lothar Waßmann | 07a3ce7 | 2013-08-08 14:51:20 +0200 | [diff] [blame] | 845 | }; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 846 | |
| 847 | apbx@80040000 { |
| 848 | compatible = "simple-bus"; |
| 849 | #address-cells = <1>; |
| 850 | #size-cells = <1>; |
| 851 | reg = <0x80040000 0x40000>; |
| 852 | ranges; |
| 853 | |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 854 | clks: clkctrl@80040000 { |
Shawn Guo | 8f7cf88 | 2013-03-29 09:33:09 +0800 | [diff] [blame] | 855 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 856 | reg = <0x80040000 0x2000>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 857 | #clock-cells = <1>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 858 | }; |
| 859 | |
| 860 | saif0: saif@80042000 { |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 861 | compatible = "fsl,imx28-saif"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 862 | reg = <0x80042000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 863 | interrupts = <59>; |
Shawn Guo | 66acaf3 | 2013-07-01 15:46:05 +0800 | [diff] [blame] | 864 | #clock-cells = <0>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 865 | clocks = <&clks 53>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 866 | dmas = <&dma_apbx 4>; |
| 867 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 868 | status = "disabled"; |
| 869 | }; |
| 870 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 871 | power: power@80044000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 872 | reg = <0x80044000 0x2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 873 | status = "disabled"; |
| 874 | }; |
| 875 | |
| 876 | saif1: saif@80046000 { |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 877 | compatible = "fsl,imx28-saif"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 878 | reg = <0x80046000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 879 | interrupts = <58>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 880 | clocks = <&clks 54>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 881 | dmas = <&dma_apbx 5>; |
| 882 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 883 | status = "disabled"; |
| 884 | }; |
| 885 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 886 | lradc: lradc@80050000 { |
Marek Vasut | aef3510 | 2012-08-17 10:42:52 +0800 | [diff] [blame] | 887 | compatible = "fsl,imx28-lradc"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 888 | reg = <0x80050000 0x2000>; |
Marek Vasut | aef3510 | 2012-08-17 10:42:52 +0800 | [diff] [blame] | 889 | interrupts = <10 14 15 16 17 18 19 |
| 890 | 20 21 22 23 24 25>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 891 | status = "disabled"; |
| 892 | }; |
| 893 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 894 | spdif: spdif@80054000 { |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 895 | reg = <0x80054000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 896 | interrupts = <45>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 897 | dmas = <&dma_apbx 2>; |
| 898 | dma-names = "tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 899 | status = "disabled"; |
| 900 | }; |
| 901 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 902 | mxs_rtc: rtc@80056000 { |
Shawn Guo | f98c990 | 2012-06-28 11:45:05 +0800 | [diff] [blame] | 903 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 904 | reg = <0x80056000 0x2000>; |
Shawn Guo | f98c990 | 2012-06-28 11:45:05 +0800 | [diff] [blame] | 905 | interrupts = <29>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 906 | }; |
| 907 | |
| 908 | i2c0: i2c@80058000 { |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 909 | #address-cells = <1>; |
| 910 | #size-cells = <0>; |
| 911 | compatible = "fsl,imx28-i2c"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 912 | reg = <0x80058000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 913 | interrupts = <111>; |
Marek Vasut | cd4f2d4 | 2012-07-09 18:22:53 +0200 | [diff] [blame] | 914 | clock-frequency = <100000>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 915 | dmas = <&dma_apbx 6>; |
| 916 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 917 | status = "disabled"; |
| 918 | }; |
| 919 | |
| 920 | i2c1: i2c@8005a000 { |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 921 | #address-cells = <1>; |
| 922 | #size-cells = <0>; |
| 923 | compatible = "fsl,imx28-i2c"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 924 | reg = <0x8005a000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 925 | interrupts = <110>; |
Marek Vasut | cd4f2d4 | 2012-07-09 18:22:53 +0200 | [diff] [blame] | 926 | clock-frequency = <100000>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 927 | dmas = <&dma_apbx 7>; |
| 928 | dma-names = "rx-tx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 929 | status = "disabled"; |
| 930 | }; |
| 931 | |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 932 | pwm: pwm@80064000 { |
| 933 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 934 | reg = <0x80064000 0x2000>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 935 | clocks = <&clks 44>; |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 936 | #pwm-cells = <2>; |
| 937 | fsl,pwm-number = <8>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 938 | status = "disabled"; |
| 939 | }; |
| 940 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 941 | timer: timrot@80068000 { |
Shawn Guo | eeca6e6 | 2012-08-20 08:51:45 +0800 | [diff] [blame] | 942 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
Fabio Estevam | 0f06cde | 2012-07-30 21:29:19 -0300 | [diff] [blame] | 943 | reg = <0x80068000 0x2000>; |
Shawn Guo | eeca6e6 | 2012-08-20 08:51:45 +0800 | [diff] [blame] | 944 | interrupts = <48 49 50 51>; |
Shawn Guo | 2efb950 | 2013-03-25 22:57:14 +0800 | [diff] [blame] | 945 | clocks = <&clks 26>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 946 | }; |
| 947 | |
| 948 | auart0: serial@8006a000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 949 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 950 | reg = <0x8006a000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 951 | interrupts = <112>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 952 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; |
| 953 | dma-names = "rx", "tx"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 954 | clocks = <&clks 45>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 955 | status = "disabled"; |
| 956 | }; |
| 957 | |
| 958 | auart1: serial@8006c000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 959 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 960 | reg = <0x8006c000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 961 | interrupts = <113>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 962 | dmas = <&dma_apbx 10>, <&dma_apbx 11>; |
| 963 | dma-names = "rx", "tx"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 964 | clocks = <&clks 45>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 965 | status = "disabled"; |
| 966 | }; |
| 967 | |
| 968 | auart2: serial@8006e000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 969 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 970 | reg = <0x8006e000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 971 | interrupts = <114>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 972 | dmas = <&dma_apbx 12>, <&dma_apbx 13>; |
| 973 | dma-names = "rx", "tx"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 974 | clocks = <&clks 45>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 975 | status = "disabled"; |
| 976 | }; |
| 977 | |
| 978 | auart3: serial@80070000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 979 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 980 | reg = <0x80070000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 981 | interrupts = <115>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 982 | dmas = <&dma_apbx 14>, <&dma_apbx 15>; |
| 983 | dma-names = "rx", "tx"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 984 | clocks = <&clks 45>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 985 | status = "disabled"; |
| 986 | }; |
| 987 | |
| 988 | auart4: serial@80072000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 989 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 990 | reg = <0x80072000 0x2000>; |
Shawn Guo | 7f2b928 | 2013-07-16 17:10:55 +0800 | [diff] [blame] | 991 | interrupts = <116>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 992 | dmas = <&dma_apbx 0>, <&dma_apbx 1>; |
| 993 | dma-names = "rx", "tx"; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 994 | clocks = <&clks 45>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 995 | status = "disabled"; |
| 996 | }; |
| 997 | |
| 998 | duart: serial@80074000 { |
| 999 | compatible = "arm,pl011", "arm,primecell"; |
| 1000 | reg = <0x80074000 0x1000>; |
| 1001 | interrupts = <47>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1002 | clocks = <&clks 45>, <&clks 26>; |
| 1003 | clock-names = "uart", "apb_pclk"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1004 | status = "disabled"; |
| 1005 | }; |
| 1006 | |
| 1007 | usbphy0: usbphy@8007c000 { |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1008 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1009 | reg = <0x8007c000 0x2000>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1010 | clocks = <&clks 62>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1011 | status = "disabled"; |
| 1012 | }; |
| 1013 | |
| 1014 | usbphy1: usbphy@8007e000 { |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1015 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1016 | reg = <0x8007e000 0x2000>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1017 | clocks = <&clks 63>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1018 | status = "disabled"; |
| 1019 | }; |
| 1020 | }; |
| 1021 | }; |
| 1022 | |
| 1023 | ahb@80080000 { |
| 1024 | compatible = "simple-bus"; |
| 1025 | #address-cells = <1>; |
| 1026 | #size-cells = <1>; |
| 1027 | reg = <0x80080000 0x80000>; |
| 1028 | ranges; |
| 1029 | |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1030 | usb0: usb@80080000 { |
| 1031 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1032 | reg = <0x80080000 0x10000>; |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1033 | interrupts = <93>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1034 | clocks = <&clks 60>; |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1035 | fsl,usbphy = <&usbphy0>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1036 | status = "disabled"; |
| 1037 | }; |
| 1038 | |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1039 | usb1: usb@80090000 { |
| 1040 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1041 | reg = <0x80090000 0x10000>; |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1042 | interrupts = <92>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1043 | clocks = <&clks 61>; |
Richard Zhao | 5da0127 | 2012-07-12 10:25:27 +0800 | [diff] [blame] | 1044 | fsl,usbphy = <&usbphy1>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1045 | status = "disabled"; |
| 1046 | }; |
| 1047 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 1048 | dflpt: dflpt@800c0000 { |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1049 | reg = <0x800c0000 0x10000>; |
| 1050 | status = "disabled"; |
| 1051 | }; |
| 1052 | |
| 1053 | mac0: ethernet@800f0000 { |
| 1054 | compatible = "fsl,imx28-fec"; |
| 1055 | reg = <0x800f0000 0x4000>; |
| 1056 | interrupts = <101>; |
Wolfram Sang | f231a9f | 2013-01-29 15:46:12 +0100 | [diff] [blame] | 1057 | clocks = <&clks 57>, <&clks 57>, <&clks 64>; |
| 1058 | clock-names = "ipg", "ahb", "enet_out"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1059 | status = "disabled"; |
| 1060 | }; |
| 1061 | |
| 1062 | mac1: ethernet@800f4000 { |
| 1063 | compatible = "fsl,imx28-fec"; |
| 1064 | reg = <0x800f4000 0x4000>; |
| 1065 | interrupts = <102>; |
Shawn Guo | b598b9f | 2012-08-22 21:36:29 +0800 | [diff] [blame] | 1066 | clocks = <&clks 57>, <&clks 57>; |
| 1067 | clock-names = "ipg", "ahb"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1068 | status = "disabled"; |
| 1069 | }; |
| 1070 | |
Lothar Waßmann | 296f8cd | 2013-08-08 14:51:21 +0200 | [diff] [blame] | 1071 | etn_switch: switch@800f8000 { |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1072 | reg = <0x800f8000 0x8000>; |
| 1073 | status = "disabled"; |
| 1074 | }; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1075 | }; |
| 1076 | }; |