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review.shift-gmbh.com / SHIFTPHONES / kernel / common / bb89b8d2aa371d2a4f74ff66c386089c4d0c2f99 / . / arch / arm / boot / dts / imx28.dtsi
blob: df783c2648a951e743757ae71ae8c437990d2016 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
16 interrupt-parent = <&icoll>;
17
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]18 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]26 saif0 = &saif0;
27 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]33 spi0 = &ssp1;
34 spi1 = &ssp2;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]35 };
36
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]37 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]44 };
45 };
46
47 apb@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x80000>;
52 ranges;
53
54 apbh@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x3c900>;
59 ranges;
60
61 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]62 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
66 };
67
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]68 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]69 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]70 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]71 dmas = <&dma_apbh 12>;
72 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]73 status = "disabled";
74 };
75
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]76 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]77 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]78 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]79 interrupts = <82 83 84 85
80 88 88 88 88
81 88 88 88 88
82 87 86 0 0>;
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
87 #dma-cells = <1>;
88 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]89 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]90 };
91
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]92 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]93 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]94 interrupts = <27>;
95 status = "disabled";
96 };
97
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]98 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
101 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]103 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]104 interrupts = <41>;
105 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]106 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]107 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]108 dmas = <&dma_apbh 4>;
109 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]110 status = "disabled";
111 };
112
113 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]114 #address-cells = <1>;
115 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]116 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]117 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]118 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]121 status = "disabled";
122 };
123
124 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]127 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]128 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]129 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]130 dmas = <&dma_apbh 1>;
131 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]132 status = "disabled";
133 };
134
135 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]136 #address-cells = <1>;
137 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]138 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]139 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]140 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]141 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]143 status = "disabled";
144 };
145
146 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]147 #address-cells = <1>;
148 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]149 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]150 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]151 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]152 dmas = <&dma_apbh 3>;
153 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]154 status = "disabled";
155 };
156
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]157 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]158 #address-cells = <1>;
159 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]160 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]161 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]162
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]163 gpio0: gpio@0 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <127>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio1: gpio@1 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <126>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 gpio2: gpio@2 {
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupts = <125>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio3: gpio@3 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192 interrupts = <124>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpio4: gpio@4 {
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
201 interrupts = <123>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]208 duart_pins_a: duart@0 {
209 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]210 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]213 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]214 fsl,drive-strength = <MXS_DRIVE_4mA>;
215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
216 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]217 };
218
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]219 duart_pins_b: duart@1 {
220 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]221 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]224 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]225 fsl,drive-strength = <MXS_DRIVE_4mA>;
226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
227 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]228 };
229
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]230 duart_4pins_a: duart-4pins@0 {
231 reg = <0>;
232 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]237 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]238 fsl,drive-strength = <MXS_DRIVE_4mA>;
239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
240 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]241 };
242
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]243 gpmi_pins_a: gpmi-nand@0 {
244 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]245 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]261 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]262 fsl,drive-strength = <MXS_DRIVE_4mA>;
263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
264 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]265 };
266
267 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]268 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]272 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]273 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]274 };
275
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]276 auart0_pins_a: auart0@0 {
277 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]278 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]283 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]284 fsl,drive-strength = <MXS_DRIVE_4mA>;
285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
286 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]287 };
288
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]289 auart0_2pins_a: auart0-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]294 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]295 fsl,drive-strength = <MXS_DRIVE_4mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]298 };
299
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]300 auart1_pins_a: auart1@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]307 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]311 };
312
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]313 auart1_2pins_a: auart1-2pins@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]318 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]319 fsl,drive-strength = <MXS_DRIVE_4mA>;
320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
321 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]322 };
323
324 auart2_2pins_a: auart2-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]329 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]330 fsl,drive-strength = <MXS_DRIVE_4mA>;
331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
332 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]333 };
334
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]335 auart2_2pins_b: auart2-2pins@1 {
336 reg = <1>;
337 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]340 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]341 fsl,drive-strength = <MXS_DRIVE_4mA>;
342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
343 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]344 };
345
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]346 auart2_pins_a: auart2-pins@0 {
347 reg = <0>;
348 fsl,pinmux-ids = <
349 MX28_PAD_AUART2_RX__AUART2_RX
350 MX28_PAD_AUART2_TX__AUART2_TX
351 MX28_PAD_AUART2_CTS__AUART2_CTS
352 MX28_PAD_AUART2_RTS__AUART2_RTS
353 >;
354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
357 };
358
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]359 auart3_pins_a: auart3@0 {
360 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]361 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]362 MX28_PAD_AUART3_RX__AUART3_RX
363 MX28_PAD_AUART3_TX__AUART3_TX
364 MX28_PAD_AUART3_CTS__AUART3_CTS
365 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]366 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]367 fsl,drive-strength = <MXS_DRIVE_4mA>;
368 fsl,voltage = <MXS_VOLTAGE_HIGH>;
369 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]370 };
371
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]372 auart3_2pins_a: auart3-2pins@0 {
373 reg = <0>;
374 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]375 MX28_PAD_SSP2_MISO__AUART3_RX
376 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]377 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]378 fsl,drive-strength = <MXS_DRIVE_4mA>;
379 fsl,voltage = <MXS_VOLTAGE_HIGH>;
380 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]381 };
382
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]383 auart3_2pins_b: auart3-2pins@1 {
384 reg = <1>;
385 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]386 MX28_PAD_AUART3_RX__AUART3_RX
387 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]388 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]389 fsl,drive-strength = <MXS_DRIVE_4mA>;
390 fsl,voltage = <MXS_VOLTAGE_HIGH>;
391 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]392 };
393
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]394 auart4_2pins_a: auart4@0 {
395 reg = <0>;
396 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]397 MX28_PAD_SSP3_SCK__AUART4_TX
398 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]399 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]400 fsl,drive-strength = <MXS_DRIVE_4mA>;
401 fsl,voltage = <MXS_VOLTAGE_HIGH>;
402 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]403 };
404
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]405 mac0_pins_a: mac0@0 {
406 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]407 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]408 MX28_PAD_ENET0_MDC__ENET0_MDC
409 MX28_PAD_ENET0_MDIO__ENET0_MDIO
410 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
411 MX28_PAD_ENET0_RXD0__ENET0_RXD0
412 MX28_PAD_ENET0_RXD1__ENET0_RXD1
413 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
414 MX28_PAD_ENET0_TXD0__ENET0_TXD0
415 MX28_PAD_ENET0_TXD1__ENET0_TXD1
416 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]417 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]418 fsl,drive-strength = <MXS_DRIVE_8mA>;
419 fsl,voltage = <MXS_VOLTAGE_HIGH>;
420 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]421 };
422
423 mac1_pins_a: mac1@0 {
424 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]425 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]426 MX28_PAD_ENET0_CRS__ENET1_RX_EN
427 MX28_PAD_ENET0_RXD2__ENET1_RXD0
428 MX28_PAD_ENET0_RXD3__ENET1_RXD1
429 MX28_PAD_ENET0_COL__ENET1_TX_EN
430 MX28_PAD_ENET0_TXD2__ENET1_TXD0
431 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]432 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]433 fsl,drive-strength = <MXS_DRIVE_8mA>;
434 fsl,voltage = <MXS_VOLTAGE_HIGH>;
435 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]436 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]437
438 mmc0_8bit_pins_a: mmc0-8bit@0 {
439 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]440 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]441 MX28_PAD_SSP0_DATA0__SSP0_D0
442 MX28_PAD_SSP0_DATA1__SSP0_D1
443 MX28_PAD_SSP0_DATA2__SSP0_D2
444 MX28_PAD_SSP0_DATA3__SSP0_D3
445 MX28_PAD_SSP0_DATA4__SSP0_D4
446 MX28_PAD_SSP0_DATA5__SSP0_D5
447 MX28_PAD_SSP0_DATA6__SSP0_D6
448 MX28_PAD_SSP0_DATA7__SSP0_D7
449 MX28_PAD_SSP0_CMD__SSP0_CMD
450 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
451 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]452 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]453 fsl,drive-strength = <MXS_DRIVE_8mA>;
454 fsl,voltage = <MXS_VOLTAGE_HIGH>;
455 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]456 };
457
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]458 mmc0_4bit_pins_a: mmc0-4bit@0 {
459 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]460 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]461 MX28_PAD_SSP0_DATA0__SSP0_D0
462 MX28_PAD_SSP0_DATA1__SSP0_D1
463 MX28_PAD_SSP0_DATA2__SSP0_D2
464 MX28_PAD_SSP0_DATA3__SSP0_D3
465 MX28_PAD_SSP0_CMD__SSP0_CMD
466 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
467 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]468 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]469 fsl,drive-strength = <MXS_DRIVE_8mA>;
470 fsl,voltage = <MXS_VOLTAGE_HIGH>;
471 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]472 };
473
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]474 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]475 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]476 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]477 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]478 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]479 };
480
481 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]482 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]483 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]484 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]485 fsl,drive-strength = <MXS_DRIVE_12mA>;
486 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]487 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]488
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]489 mmc2_4bit_pins_a: mmc2-4bit@0 {
490 reg = <0>;
491 fsl,pinmux-ids = <
492 MX28_PAD_SSP0_DATA4__SSP2_D0
493 MX28_PAD_SSP1_SCK__SSP2_D1
494 MX28_PAD_SSP1_CMD__SSP2_D2
495 MX28_PAD_SSP0_DATA5__SSP2_D3
496 MX28_PAD_SSP0_DATA6__SSP2_CMD
497 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
498 MX28_PAD_SSP0_DATA7__SSP2_SCK
499 >;
500 fsl,drive-strength = <MXS_DRIVE_8mA>;
501 fsl,voltage = <MXS_VOLTAGE_HIGH>;
502 fsl,pull-up = <MXS_PULL_ENABLE>;
503 };
504
505 mmc2_cd_cfg: mmc2-cd-cfg {
506 fsl,pinmux-ids = <
507 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
508 >;
509 fsl,pull-up = <MXS_PULL_DISABLE>;
510 };
511
512 mmc2_sck_cfg: mmc2-sck-cfg {
513 fsl,pinmux-ids = <
514 MX28_PAD_SSP0_DATA7__SSP2_SCK
515 >;
516 fsl,drive-strength = <MXS_DRIVE_12mA>;
517 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]518 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]519
520 i2c0_pins_a: i2c0@0 {
521 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]522 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]523 MX28_PAD_I2C0_SCL__I2C0_SCL
524 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]525 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]526 fsl,drive-strength = <MXS_DRIVE_8mA>;
527 fsl,voltage = <MXS_VOLTAGE_HIGH>;
528 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]529 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]530
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]531 i2c0_pins_b: i2c0@1 {
532 reg = <1>;
533 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]534 MX28_PAD_AUART0_RX__I2C0_SCL
535 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]536 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]537 fsl,drive-strength = <MXS_DRIVE_8mA>;
538 fsl,voltage = <MXS_VOLTAGE_HIGH>;
539 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]540 };
541
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]542 i2c1_pins_a: i2c1@0 {
543 reg = <0>;
544 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]545 MX28_PAD_PWM0__I2C1_SCL
546 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]547 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]548 fsl,drive-strength = <MXS_DRIVE_8mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]551 };
552
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]553 saif0_pins_a: saif0@0 {
554 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]555 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]556 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
557 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
558 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
559 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]560 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]561 fsl,drive-strength = <MXS_DRIVE_12mA>;
562 fsl,voltage = <MXS_VOLTAGE_HIGH>;
563 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]564 };
565
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]566 saif0_pins_b: saif0@1 {
567 reg = <1>;
568 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]569 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
570 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
571 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]572 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]573 fsl,drive-strength = <MXS_DRIVE_12mA>;
574 fsl,voltage = <MXS_VOLTAGE_HIGH>;
575 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]576 };
577
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]578 saif1_pins_a: saif1@0 {
579 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]580 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]581 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]582 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]583 fsl,drive-strength = <MXS_DRIVE_12mA>;
584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
585 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]586 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]587
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]588 pwm0_pins_a: pwm0@0 {
589 reg = <0>;
590 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]591 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]592 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]593 fsl,drive-strength = <MXS_DRIVE_4mA>;
594 fsl,voltage = <MXS_VOLTAGE_HIGH>;
595 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]596 };
597
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]598 pwm2_pins_a: pwm2@0 {
599 reg = <0>;
600 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]601 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]602 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]603 fsl,drive-strength = <MXS_DRIVE_4mA>;
604 fsl,voltage = <MXS_VOLTAGE_HIGH>;
605 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]606 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]607
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]608 pwm3_pins_a: pwm3@0 {
609 reg = <0>;
610 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]611 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]612 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]613 fsl,drive-strength = <MXS_DRIVE_4mA>;
614 fsl,voltage = <MXS_VOLTAGE_HIGH>;
615 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]616 };
617
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]618 pwm3_pins_b: pwm3@1 {
619 reg = <1>;
620 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]621 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]622 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]623 fsl,drive-strength = <MXS_DRIVE_4mA>;
624 fsl,voltage = <MXS_VOLTAGE_HIGH>;
625 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]626 };
627
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]628 pwm4_pins_a: pwm4@0 {
629 reg = <0>;
630 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]631 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]632 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]633 fsl,drive-strength = <MXS_DRIVE_4mA>;
634 fsl,voltage = <MXS_VOLTAGE_HIGH>;
635 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]636 };
637
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]638 lcdif_24bit_pins_a: lcdif-24bit@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]641 MX28_PAD_LCD_D00__LCD_D0
642 MX28_PAD_LCD_D01__LCD_D1
643 MX28_PAD_LCD_D02__LCD_D2
644 MX28_PAD_LCD_D03__LCD_D3
645 MX28_PAD_LCD_D04__LCD_D4
646 MX28_PAD_LCD_D05__LCD_D5
647 MX28_PAD_LCD_D06__LCD_D6
648 MX28_PAD_LCD_D07__LCD_D7
649 MX28_PAD_LCD_D08__LCD_D8
650 MX28_PAD_LCD_D09__LCD_D9
651 MX28_PAD_LCD_D10__LCD_D10
652 MX28_PAD_LCD_D11__LCD_D11
653 MX28_PAD_LCD_D12__LCD_D12
654 MX28_PAD_LCD_D13__LCD_D13
655 MX28_PAD_LCD_D14__LCD_D14
656 MX28_PAD_LCD_D15__LCD_D15
657 MX28_PAD_LCD_D16__LCD_D16
658 MX28_PAD_LCD_D17__LCD_D17
659 MX28_PAD_LCD_D18__LCD_D18
660 MX28_PAD_LCD_D19__LCD_D19
661 MX28_PAD_LCD_D20__LCD_D20
662 MX28_PAD_LCD_D21__LCD_D21
663 MX28_PAD_LCD_D22__LCD_D22
664 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]665 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]666 fsl,drive-strength = <MXS_DRIVE_4mA>;
667 fsl,voltage = <MXS_VOLTAGE_HIGH>;
668 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]669 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]670
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]671 lcdif_18bit_pins_a: lcdif-18bit@0 {
672 reg = <0>;
673 fsl,pinmux-ids = <
674 MX28_PAD_LCD_D00__LCD_D0
675 MX28_PAD_LCD_D01__LCD_D1
676 MX28_PAD_LCD_D02__LCD_D2
677 MX28_PAD_LCD_D03__LCD_D3
678 MX28_PAD_LCD_D04__LCD_D4
679 MX28_PAD_LCD_D05__LCD_D5
680 MX28_PAD_LCD_D06__LCD_D6
681 MX28_PAD_LCD_D07__LCD_D7
682 MX28_PAD_LCD_D08__LCD_D8
683 MX28_PAD_LCD_D09__LCD_D9
684 MX28_PAD_LCD_D10__LCD_D10
685 MX28_PAD_LCD_D11__LCD_D11
686 MX28_PAD_LCD_D12__LCD_D12
687 MX28_PAD_LCD_D13__LCD_D13
688 MX28_PAD_LCD_D14__LCD_D14
689 MX28_PAD_LCD_D15__LCD_D15
690 MX28_PAD_LCD_D16__LCD_D16
691 MX28_PAD_LCD_D17__LCD_D17
692 >;
693 fsl,drive-strength = <MXS_DRIVE_4mA>;
694 fsl,voltage = <MXS_VOLTAGE_HIGH>;
695 fsl,pull-up = <MXS_PULL_DISABLE>;
696 };
697
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]698 lcdif_16bit_pins_a: lcdif-16bit@0 {
699 reg = <0>;
700 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]701 MX28_PAD_LCD_D00__LCD_D0
702 MX28_PAD_LCD_D01__LCD_D1
703 MX28_PAD_LCD_D02__LCD_D2
704 MX28_PAD_LCD_D03__LCD_D3
705 MX28_PAD_LCD_D04__LCD_D4
706 MX28_PAD_LCD_D05__LCD_D5
707 MX28_PAD_LCD_D06__LCD_D6
708 MX28_PAD_LCD_D07__LCD_D7
709 MX28_PAD_LCD_D08__LCD_D8
710 MX28_PAD_LCD_D09__LCD_D9
711 MX28_PAD_LCD_D10__LCD_D10
712 MX28_PAD_LCD_D11__LCD_D11
713 MX28_PAD_LCD_D12__LCD_D12
714 MX28_PAD_LCD_D13__LCD_D13
715 MX28_PAD_LCD_D14__LCD_D14
716 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]717 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]718 fsl,drive-strength = <MXS_DRIVE_4mA>;
719 fsl,voltage = <MXS_VOLTAGE_HIGH>;
720 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]721 };
722
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]723 lcdif_sync_pins_a: lcdif-sync@0 {
724 reg = <0>;
725 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]726 MX28_PAD_LCD_RS__LCD_DOTCLK
727 MX28_PAD_LCD_CS__LCD_ENABLE
728 MX28_PAD_LCD_RD_E__LCD_VSYNC
729 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]730 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]731 fsl,drive-strength = <MXS_DRIVE_4mA>;
732 fsl,voltage = <MXS_VOLTAGE_HIGH>;
733 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]734 };
735
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]736 can0_pins_a: can0@0 {
737 reg = <0>;
738 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]739 MX28_PAD_GPMI_RDY2__CAN0_TX
740 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]741 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]742 fsl,drive-strength = <MXS_DRIVE_4mA>;
743 fsl,voltage = <MXS_VOLTAGE_HIGH>;
744 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]745 };
746
747 can1_pins_a: can1@0 {
748 reg = <0>;
749 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]750 MX28_PAD_GPMI_CE2N__CAN1_TX
751 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]752 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]753 fsl,drive-strength = <MXS_DRIVE_4mA>;
754 fsl,voltage = <MXS_VOLTAGE_HIGH>;
755 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]756 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]757
758 spi2_pins_a: spi2@0 {
759 reg = <0>;
760 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]761 MX28_PAD_SSP2_SCK__SSP2_SCK
762 MX28_PAD_SSP2_MOSI__SSP2_CMD
763 MX28_PAD_SSP2_MISO__SSP2_D0
764 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]765 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]766 fsl,drive-strength = <MXS_DRIVE_8mA>;
767 fsl,voltage = <MXS_VOLTAGE_HIGH>;
768 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]769 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]770
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]771 spi3_pins_a: spi3@0 {
772 reg = <0>;
773 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]774 MX28_PAD_AUART2_RX__SSP3_D4
775 MX28_PAD_AUART2_TX__SSP3_D5
776 MX28_PAD_SSP3_SCK__SSP3_SCK
777 MX28_PAD_SSP3_MOSI__SSP3_CMD
778 MX28_PAD_SSP3_MISO__SSP3_D0
779 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]780 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]781 fsl,drive-strength = <MXS_DRIVE_8mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]784 };
785
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]786 usbphy0_pins_a: usbphy0@0 {
787 reg = <0>;
788 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]789 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]790 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]791 fsl,drive-strength = <MXS_DRIVE_12mA>;
792 fsl,voltage = <MXS_VOLTAGE_HIGH>;
793 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]794 };
795
796 usbphy0_pins_b: usbphy0@1 {
797 reg = <1>;
798 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]799 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]800 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]801 fsl,drive-strength = <MXS_DRIVE_12mA>;
802 fsl,voltage = <MXS_VOLTAGE_HIGH>;
803 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]804 };
805
806 usbphy1_pins_a: usbphy1@0 {
807 reg = <0>;
808 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]809 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]810 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]811 fsl,drive-strength = <MXS_DRIVE_12mA>;
812 fsl,voltage = <MXS_VOLTAGE_HIGH>;
813 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]814 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]815
816 usb0_id_pins_a: usb0id@0 {
817 reg = <0>;
818 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]819 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]820 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]821 fsl,drive-strength = <MXS_DRIVE_12mA>;
822 fsl,voltage = <MXS_VOLTAGE_HIGH>;
823 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]824 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame^]825
826 usb0_id_pins_b: usb0id1@0 {
827 reg = <0>;
828 fsl,pinmux-ids = <
829 MX28_PAD_PWM2__USB0_ID
830 >;
831 fsl,drive-strength = <MXS_DRIVE_12mA>;
832 fsl,voltage = <MXS_VOLTAGE_HIGH>;
833 fsl,pull-up = <MXS_PULL_ENABLE>;
834 };
835
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]836 };
837
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]838 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]839 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]840 reg = <0x8001c000 0x2000>;
841 interrupts = <89>;
842 status = "disabled";
843 };
844
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]845 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]846 reg = <0x80022000 0x2000>;
847 status = "disabled";
848 };
849
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]850 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]851 compatible = "fsl,imx28-dma-apbx";
852 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]853 interrupts = <78 79 66 0
854 80 81 68 69
855 70 71 72 73
856 74 75 76 77>;
857 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
858 "saif0", "saif1", "i2c0", "i2c1",
859 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
860 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
861 #dma-cells = <1>;
862 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]863 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]864 };
865
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]866 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]867 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]868 reg = <0x80028000 0x2000>;
869 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]870 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]871 };
872
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]873 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]874 reg = <0x8002a000 0x2000>;
875 interrupts = <39>;
876 status = "disabled";
877 };
878
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]879 ocotp: ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800[diff] [blame]880 compatible = "fsl,ocotp";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]881 reg = <0x8002c000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]882 status = "disabled";
883 };
884
885 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]886 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]887 status = "disabled";
888 };
889
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]890 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]891 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]892 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]893 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]894 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]895 dmas = <&dma_apbh 13>;
896 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]897 status = "disabled";
898 };
899
900 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]901 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]902 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]903 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]904 clocks = <&clks 58>, <&clks 58>;
905 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]906 status = "disabled";
907 };
908
909 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]910 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]911 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]912 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]913 clocks = <&clks 59>, <&clks 59>;
914 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]915 status = "disabled";
916 };
917
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]918 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]919 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]920 status = "disabled";
921 };
922
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]923 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]924 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]925 status = "disabled";
926 };
927
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]928 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]929 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]930 status = "disabled";
931 };
932
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]933 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]934 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]935 status = "disabled";
936 };
937
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]938 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]939 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]940 status = "disabled";
941 };
942
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]943 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]944 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]945 status = "disabled";
946 };
947
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]948 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]949 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]950 status = "disabled";
951 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]952 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]953
954 apbx@80040000 {
955 compatible = "simple-bus";
956 #address-cells = <1>;
957 #size-cells = <1>;
958 reg = <0x80040000 0x40000>;
959 ranges;
960
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]961 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]962 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]963 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]964 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]965 };
966
967 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]968 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]969 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]970 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]971 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]972 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]973 dmas = <&dma_apbx 4>;
974 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]975 status = "disabled";
976 };
977
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]978 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]979 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]980 status = "disabled";
981 };
982
983 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]984 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]985 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]986 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]987 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]988 dmas = <&dma_apbx 5>;
989 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]990 status = "disabled";
991 };
992
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]993 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]994 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]995 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]996 interrupts = <10 14 15 16 17 18 19
997 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]998 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]999 clocks = <&clks 41>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1000 };
1001
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1002 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1003 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1004 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1005 dmas = <&dma_apbx 2>;
1006 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1007 status = "disabled";
1008 };
1009
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1010 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1011 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1012 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1013 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1014 };
1015
1016 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1020 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1021 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1022 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1023 dmas = <&dma_apbx 6>;
1024 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1025 status = "disabled";
1026 };
1027
1028 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1032 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1033 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1034 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1035 dmas = <&dma_apbx 7>;
1036 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1037 status = "disabled";
1038 };
1039
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1040 pwm: pwm@80064000 {
1041 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1042 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1043 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1044 #pwm-cells = <2>;
1045 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1046 status = "disabled";
1047 };
1048
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1049 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1050 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1051 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1052 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1053 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1054 };
1055
1056 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1057 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1058 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1059 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1060 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1061 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1062 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1063 status = "disabled";
1064 };
1065
1066 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1067 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1068 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1069 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1070 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1071 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1072 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1073 status = "disabled";
1074 };
1075
1076 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1077 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1078 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1079 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1080 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1081 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1082 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1083 status = "disabled";
1084 };
1085
1086 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1087 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1088 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1089 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1090 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1091 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1092 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1093 status = "disabled";
1094 };
1095
1096 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1097 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1098 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1099 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1100 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1101 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1102 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1103 status = "disabled";
1104 };
1105
1106 duart: serial@80074000 {
1107 compatible = "arm,pl011", "arm,primecell";
1108 reg = <0x80074000 0x1000>;
1109 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1110 clocks = <&clks 45>, <&clks 26>;
1111 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1112 status = "disabled";
1113 };
1114
1115 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1116 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1117 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1118 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1119 status = "disabled";
1120 };
1121
1122 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1123 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1124 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1125 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1126 status = "disabled";
1127 };
1128 };
1129 };
1130
1131 ahb@80080000 {
1132 compatible = "simple-bus";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 reg = <0x80080000 0x80000>;
1136 ranges;
1137
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1138 usb0: usb@80080000 {
1139 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1140 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1141 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1142 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1143 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1144 status = "disabled";
1145 };
1146
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1147 usb1: usb@80090000 {
1148 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1149 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1150 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1151 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1152 fsl,usbphy = <&usbphy1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1153 status = "disabled";
1154 };
1155
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1156 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1157 reg = <0x800c0000 0x10000>;
1158 status = "disabled";
1159 };
1160
1161 mac0: ethernet@800f0000 {
1162 compatible = "fsl,imx28-fec";
1163 reg = <0x800f0000 0x4000>;
1164 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1165 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1166 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1167 status = "disabled";
1168 };
1169
1170 mac1: ethernet@800f4000 {
1171 compatible = "fsl,imx28-fec";
1172 reg = <0x800f4000 0x4000>;
1173 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1174 clocks = <&clks 57>, <&clks 57>;
1175 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1176 status = "disabled";
1177 };
1178
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1179 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1180 reg = <0x800f8000 0x8000>;
1181 status = "disabled";
1182 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1183 };
1184};