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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 1f35cc6ae09f51cd2c216f65c253b033d17e86fb / . / arch / arm / boot / dts / imx28.dtsi
blob: 90a579532b8b7619c334b77ef740ec3b0f6b233e [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
16 interrupt-parent = <&icoll>;
17
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]18 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]26 saif0 = &saif0;
27 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]33 spi0 = &ssp1;
34 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame^]35 usbphy0 = &usbphy0;
36 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]37 };
38
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]39 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]46 };
47 };
48
49 apb@80000000 {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 reg = <0x80000000 0x80000>;
54 ranges;
55
56 apbh@80000000 {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 reg = <0x80000000 0x3c900>;
61 ranges;
62
63 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]64 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]65 interrupt-controller;
66 #interrupt-cells = <1>;
67 reg = <0x80000000 0x2000>;
68 };
69
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]70 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]71 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]72 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]73 dmas = <&dma_apbh 12>;
74 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]75 status = "disabled";
76 };
77
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]78 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]79 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]80 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]81 interrupts = <82 83 84 85
82 88 88 88 88
83 88 88 88 88
84 87 86 0 0>;
85 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
86 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
87 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
88 "hsadc", "lcdif", "empty", "empty";
89 #dma-cells = <1>;
90 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]91 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]92 };
93
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]94 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]95 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]96 interrupts = <27>;
97 status = "disabled";
98 };
99
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]100 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]101 compatible = "fsl,imx28-gpmi-nand";
102 #address-cells = <1>;
103 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]104 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]105 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]106 interrupts = <41>;
107 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]108 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]109 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]110 dmas = <&dma_apbh 4>;
111 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]112 status = "disabled";
113 };
114
115 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]116 #address-cells = <1>;
117 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]118 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]119 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]120 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]121 dmas = <&dma_apbh 0>;
122 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]123 status = "disabled";
124 };
125
126 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]127 #address-cells = <1>;
128 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]129 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]130 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]131 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]132 dmas = <&dma_apbh 1>;
133 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]134 status = "disabled";
135 };
136
137 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]138 #address-cells = <1>;
139 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]140 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]141 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]142 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]143 dmas = <&dma_apbh 2>;
144 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]145 status = "disabled";
146 };
147
148 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]149 #address-cells = <1>;
150 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]151 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]152 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]153 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]154 dmas = <&dma_apbh 3>;
155 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]156 status = "disabled";
157 };
158
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]159 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]160 #address-cells = <1>;
161 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]162 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]163 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]164
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]165 gpio0: gpio@0 {
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
167 interrupts = <127>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 gpio1: gpio@1 {
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
176 interrupts = <126>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
183 gpio2: gpio@2 {
184 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
185 interrupts = <125>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 };
191
192 gpio3: gpio@3 {
193 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
194 interrupts = <124>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 };
200
201 gpio4: gpio@4 {
202 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
203 interrupts = <123>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 };
209
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]210 duart_pins_a: duart@0 {
211 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]212 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]213 MX28_PAD_PWM0__DUART_RX
214 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]215 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]216 fsl,drive-strength = <MXS_DRIVE_4mA>;
217 fsl,voltage = <MXS_VOLTAGE_HIGH>;
218 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]219 };
220
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]221 duart_pins_b: duart@1 {
222 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]223 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]224 MX28_PAD_AUART0_CTS__DUART_RX
225 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]226 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]227 fsl,drive-strength = <MXS_DRIVE_4mA>;
228 fsl,voltage = <MXS_VOLTAGE_HIGH>;
229 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]230 };
231
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]232 duart_4pins_a: duart-4pins@0 {
233 reg = <0>;
234 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]235 MX28_PAD_AUART0_CTS__DUART_RX
236 MX28_PAD_AUART0_RTS__DUART_TX
237 MX28_PAD_AUART0_RX__DUART_CTS
238 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]239 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]240 fsl,drive-strength = <MXS_DRIVE_4mA>;
241 fsl,voltage = <MXS_VOLTAGE_HIGH>;
242 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]243 };
244
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]245 gpmi_pins_a: gpmi-nand@0 {
246 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]247 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]248 MX28_PAD_GPMI_D00__GPMI_D0
249 MX28_PAD_GPMI_D01__GPMI_D1
250 MX28_PAD_GPMI_D02__GPMI_D2
251 MX28_PAD_GPMI_D03__GPMI_D3
252 MX28_PAD_GPMI_D04__GPMI_D4
253 MX28_PAD_GPMI_D05__GPMI_D5
254 MX28_PAD_GPMI_D06__GPMI_D6
255 MX28_PAD_GPMI_D07__GPMI_D7
256 MX28_PAD_GPMI_CE0N__GPMI_CE0N
257 MX28_PAD_GPMI_RDY0__GPMI_READY0
258 MX28_PAD_GPMI_RDN__GPMI_RDN
259 MX28_PAD_GPMI_WRN__GPMI_WRN
260 MX28_PAD_GPMI_ALE__GPMI_ALE
261 MX28_PAD_GPMI_CLE__GPMI_CLE
262 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]263 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]264 fsl,drive-strength = <MXS_DRIVE_4mA>;
265 fsl,voltage = <MXS_VOLTAGE_HIGH>;
266 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]267 };
268
269 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]270 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]271 MX28_PAD_GPMI_RDN__GPMI_RDN
272 MX28_PAD_GPMI_WRN__GPMI_WRN
273 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]274 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]275 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]276 };
277
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]278 auart0_pins_a: auart0@0 {
279 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]280 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]281 MX28_PAD_AUART0_RX__AUART0_RX
282 MX28_PAD_AUART0_TX__AUART0_TX
283 MX28_PAD_AUART0_CTS__AUART0_CTS
284 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]285 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]286 fsl,drive-strength = <MXS_DRIVE_4mA>;
287 fsl,voltage = <MXS_VOLTAGE_HIGH>;
288 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]289 };
290
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]291 auart0_2pins_a: auart0-2pins@0 {
292 reg = <0>;
293 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]294 MX28_PAD_AUART0_RX__AUART0_RX
295 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]296 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]297 fsl,drive-strength = <MXS_DRIVE_4mA>;
298 fsl,voltage = <MXS_VOLTAGE_HIGH>;
299 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]300 };
301
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]302 auart1_pins_a: auart1@0 {
303 reg = <0>;
304 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]305 MX28_PAD_AUART1_RX__AUART1_RX
306 MX28_PAD_AUART1_TX__AUART1_TX
307 MX28_PAD_AUART1_CTS__AUART1_CTS
308 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]309 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]310 fsl,drive-strength = <MXS_DRIVE_4mA>;
311 fsl,voltage = <MXS_VOLTAGE_HIGH>;
312 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]313 };
314
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]315 auart1_2pins_a: auart1-2pins@0 {
316 reg = <0>;
317 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]318 MX28_PAD_AUART1_RX__AUART1_RX
319 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]320 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]321 fsl,drive-strength = <MXS_DRIVE_4mA>;
322 fsl,voltage = <MXS_VOLTAGE_HIGH>;
323 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]324 };
325
326 auart2_2pins_a: auart2-2pins@0 {
327 reg = <0>;
328 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]329 MX28_PAD_SSP2_SCK__AUART2_RX
330 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]331 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]332 fsl,drive-strength = <MXS_DRIVE_4mA>;
333 fsl,voltage = <MXS_VOLTAGE_HIGH>;
334 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]335 };
336
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]337 auart2_2pins_b: auart2-2pins@1 {
338 reg = <1>;
339 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]340 MX28_PAD_AUART2_RX__AUART2_RX
341 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]342 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]343 fsl,drive-strength = <MXS_DRIVE_4mA>;
344 fsl,voltage = <MXS_VOLTAGE_HIGH>;
345 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]346 };
347
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]348 auart2_pins_a: auart2-pins@0 {
349 reg = <0>;
350 fsl,pinmux-ids = <
351 MX28_PAD_AUART2_RX__AUART2_RX
352 MX28_PAD_AUART2_TX__AUART2_TX
353 MX28_PAD_AUART2_CTS__AUART2_CTS
354 MX28_PAD_AUART2_RTS__AUART2_RTS
355 >;
356 fsl,drive-strength = <MXS_DRIVE_4mA>;
357 fsl,voltage = <MXS_VOLTAGE_HIGH>;
358 fsl,pull-up = <MXS_PULL_DISABLE>;
359 };
360
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]361 auart3_pins_a: auart3@0 {
362 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]363 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]364 MX28_PAD_AUART3_RX__AUART3_RX
365 MX28_PAD_AUART3_TX__AUART3_TX
366 MX28_PAD_AUART3_CTS__AUART3_CTS
367 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]368 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]369 fsl,drive-strength = <MXS_DRIVE_4mA>;
370 fsl,voltage = <MXS_VOLTAGE_HIGH>;
371 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]372 };
373
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]374 auart3_2pins_a: auart3-2pins@0 {
375 reg = <0>;
376 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]377 MX28_PAD_SSP2_MISO__AUART3_RX
378 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]379 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]380 fsl,drive-strength = <MXS_DRIVE_4mA>;
381 fsl,voltage = <MXS_VOLTAGE_HIGH>;
382 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]383 };
384
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]385 auart3_2pins_b: auart3-2pins@1 {
386 reg = <1>;
387 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]388 MX28_PAD_AUART3_RX__AUART3_RX
389 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]390 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]391 fsl,drive-strength = <MXS_DRIVE_4mA>;
392 fsl,voltage = <MXS_VOLTAGE_HIGH>;
393 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]394 };
395
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]396 auart4_2pins_a: auart4@0 {
397 reg = <0>;
398 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]399 MX28_PAD_SSP3_SCK__AUART4_TX
400 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]401 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]402 fsl,drive-strength = <MXS_DRIVE_4mA>;
403 fsl,voltage = <MXS_VOLTAGE_HIGH>;
404 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]405 };
406
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]407 mac0_pins_a: mac0@0 {
408 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]409 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]410 MX28_PAD_ENET0_MDC__ENET0_MDC
411 MX28_PAD_ENET0_MDIO__ENET0_MDIO
412 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
413 MX28_PAD_ENET0_RXD0__ENET0_RXD0
414 MX28_PAD_ENET0_RXD1__ENET0_RXD1
415 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
416 MX28_PAD_ENET0_TXD0__ENET0_TXD0
417 MX28_PAD_ENET0_TXD1__ENET0_TXD1
418 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]419 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]420 fsl,drive-strength = <MXS_DRIVE_8mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]423 };
424
425 mac1_pins_a: mac1@0 {
426 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]427 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]428 MX28_PAD_ENET0_CRS__ENET1_RX_EN
429 MX28_PAD_ENET0_RXD2__ENET1_RXD0
430 MX28_PAD_ENET0_RXD3__ENET1_RXD1
431 MX28_PAD_ENET0_COL__ENET1_TX_EN
432 MX28_PAD_ENET0_TXD2__ENET1_TXD0
433 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]434 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]435 fsl,drive-strength = <MXS_DRIVE_8mA>;
436 fsl,voltage = <MXS_VOLTAGE_HIGH>;
437 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]438 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]439
440 mmc0_8bit_pins_a: mmc0-8bit@0 {
441 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]442 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]443 MX28_PAD_SSP0_DATA0__SSP0_D0
444 MX28_PAD_SSP0_DATA1__SSP0_D1
445 MX28_PAD_SSP0_DATA2__SSP0_D2
446 MX28_PAD_SSP0_DATA3__SSP0_D3
447 MX28_PAD_SSP0_DATA4__SSP0_D4
448 MX28_PAD_SSP0_DATA5__SSP0_D5
449 MX28_PAD_SSP0_DATA6__SSP0_D6
450 MX28_PAD_SSP0_DATA7__SSP0_D7
451 MX28_PAD_SSP0_CMD__SSP0_CMD
452 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
453 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]454 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]455 fsl,drive-strength = <MXS_DRIVE_8mA>;
456 fsl,voltage = <MXS_VOLTAGE_HIGH>;
457 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]458 };
459
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]460 mmc0_4bit_pins_a: mmc0-4bit@0 {
461 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]462 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]463 MX28_PAD_SSP0_DATA0__SSP0_D0
464 MX28_PAD_SSP0_DATA1__SSP0_D1
465 MX28_PAD_SSP0_DATA2__SSP0_D2
466 MX28_PAD_SSP0_DATA3__SSP0_D3
467 MX28_PAD_SSP0_CMD__SSP0_CMD
468 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
469 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]470 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]471 fsl,drive-strength = <MXS_DRIVE_8mA>;
472 fsl,voltage = <MXS_VOLTAGE_HIGH>;
473 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]474 };
475
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]476 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]477 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]478 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]479 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]480 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]481 };
482
483 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]484 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]485 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]486 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]487 fsl,drive-strength = <MXS_DRIVE_12mA>;
488 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]489 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]490
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]491 mmc2_4bit_pins_a: mmc2-4bit@0 {
492 reg = <0>;
493 fsl,pinmux-ids = <
494 MX28_PAD_SSP0_DATA4__SSP2_D0
495 MX28_PAD_SSP1_SCK__SSP2_D1
496 MX28_PAD_SSP1_CMD__SSP2_D2
497 MX28_PAD_SSP0_DATA5__SSP2_D3
498 MX28_PAD_SSP0_DATA6__SSP2_CMD
499 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
500 MX28_PAD_SSP0_DATA7__SSP2_SCK
501 >;
502 fsl,drive-strength = <MXS_DRIVE_8mA>;
503 fsl,voltage = <MXS_VOLTAGE_HIGH>;
504 fsl,pull-up = <MXS_PULL_ENABLE>;
505 };
506
507 mmc2_cd_cfg: mmc2-cd-cfg {
508 fsl,pinmux-ids = <
509 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
510 >;
511 fsl,pull-up = <MXS_PULL_DISABLE>;
512 };
513
514 mmc2_sck_cfg: mmc2-sck-cfg {
515 fsl,pinmux-ids = <
516 MX28_PAD_SSP0_DATA7__SSP2_SCK
517 >;
518 fsl,drive-strength = <MXS_DRIVE_12mA>;
519 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]520 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]521
522 i2c0_pins_a: i2c0@0 {
523 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]524 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]525 MX28_PAD_I2C0_SCL__I2C0_SCL
526 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]527 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]528 fsl,drive-strength = <MXS_DRIVE_8mA>;
529 fsl,voltage = <MXS_VOLTAGE_HIGH>;
530 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]531 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]532
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]533 i2c0_pins_b: i2c0@1 {
534 reg = <1>;
535 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]536 MX28_PAD_AUART0_RX__I2C0_SCL
537 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]538 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]539 fsl,drive-strength = <MXS_DRIVE_8mA>;
540 fsl,voltage = <MXS_VOLTAGE_HIGH>;
541 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]542 };
543
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]544 i2c1_pins_a: i2c1@0 {
545 reg = <0>;
546 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]547 MX28_PAD_PWM0__I2C1_SCL
548 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]549 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]550 fsl,drive-strength = <MXS_DRIVE_8mA>;
551 fsl,voltage = <MXS_VOLTAGE_HIGH>;
552 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]553 };
554
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]555 saif0_pins_a: saif0@0 {
556 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]557 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]558 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
559 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
560 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
561 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]562 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]563 fsl,drive-strength = <MXS_DRIVE_12mA>;
564 fsl,voltage = <MXS_VOLTAGE_HIGH>;
565 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]566 };
567
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]568 saif0_pins_b: saif0@1 {
569 reg = <1>;
570 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]571 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
572 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
573 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]574 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]575 fsl,drive-strength = <MXS_DRIVE_12mA>;
576 fsl,voltage = <MXS_VOLTAGE_HIGH>;
577 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]578 };
579
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]580 saif1_pins_a: saif1@0 {
581 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]582 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]583 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]584 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]585 fsl,drive-strength = <MXS_DRIVE_12mA>;
586 fsl,voltage = <MXS_VOLTAGE_HIGH>;
587 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]588 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]589
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]590 pwm0_pins_a: pwm0@0 {
591 reg = <0>;
592 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]593 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]594 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]595 fsl,drive-strength = <MXS_DRIVE_4mA>;
596 fsl,voltage = <MXS_VOLTAGE_HIGH>;
597 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]598 };
599
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]600 pwm2_pins_a: pwm2@0 {
601 reg = <0>;
602 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]603 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]604 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]605 fsl,drive-strength = <MXS_DRIVE_4mA>;
606 fsl,voltage = <MXS_VOLTAGE_HIGH>;
607 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]608 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]609
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]610 pwm3_pins_a: pwm3@0 {
611 reg = <0>;
612 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]613 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]614 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]615 fsl,drive-strength = <MXS_DRIVE_4mA>;
616 fsl,voltage = <MXS_VOLTAGE_HIGH>;
617 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]618 };
619
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]620 pwm3_pins_b: pwm3@1 {
621 reg = <1>;
622 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]623 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]624 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]625 fsl,drive-strength = <MXS_DRIVE_4mA>;
626 fsl,voltage = <MXS_VOLTAGE_HIGH>;
627 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]628 };
629
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]630 pwm4_pins_a: pwm4@0 {
631 reg = <0>;
632 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]633 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]634 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]635 fsl,drive-strength = <MXS_DRIVE_4mA>;
636 fsl,voltage = <MXS_VOLTAGE_HIGH>;
637 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]638 };
639
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]640 lcdif_24bit_pins_a: lcdif-24bit@0 {
641 reg = <0>;
642 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]643 MX28_PAD_LCD_D00__LCD_D0
644 MX28_PAD_LCD_D01__LCD_D1
645 MX28_PAD_LCD_D02__LCD_D2
646 MX28_PAD_LCD_D03__LCD_D3
647 MX28_PAD_LCD_D04__LCD_D4
648 MX28_PAD_LCD_D05__LCD_D5
649 MX28_PAD_LCD_D06__LCD_D6
650 MX28_PAD_LCD_D07__LCD_D7
651 MX28_PAD_LCD_D08__LCD_D8
652 MX28_PAD_LCD_D09__LCD_D9
653 MX28_PAD_LCD_D10__LCD_D10
654 MX28_PAD_LCD_D11__LCD_D11
655 MX28_PAD_LCD_D12__LCD_D12
656 MX28_PAD_LCD_D13__LCD_D13
657 MX28_PAD_LCD_D14__LCD_D14
658 MX28_PAD_LCD_D15__LCD_D15
659 MX28_PAD_LCD_D16__LCD_D16
660 MX28_PAD_LCD_D17__LCD_D17
661 MX28_PAD_LCD_D18__LCD_D18
662 MX28_PAD_LCD_D19__LCD_D19
663 MX28_PAD_LCD_D20__LCD_D20
664 MX28_PAD_LCD_D21__LCD_D21
665 MX28_PAD_LCD_D22__LCD_D22
666 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]667 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]668 fsl,drive-strength = <MXS_DRIVE_4mA>;
669 fsl,voltage = <MXS_VOLTAGE_HIGH>;
670 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]671 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]672
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]673 lcdif_18bit_pins_a: lcdif-18bit@0 {
674 reg = <0>;
675 fsl,pinmux-ids = <
676 MX28_PAD_LCD_D00__LCD_D0
677 MX28_PAD_LCD_D01__LCD_D1
678 MX28_PAD_LCD_D02__LCD_D2
679 MX28_PAD_LCD_D03__LCD_D3
680 MX28_PAD_LCD_D04__LCD_D4
681 MX28_PAD_LCD_D05__LCD_D5
682 MX28_PAD_LCD_D06__LCD_D6
683 MX28_PAD_LCD_D07__LCD_D7
684 MX28_PAD_LCD_D08__LCD_D8
685 MX28_PAD_LCD_D09__LCD_D9
686 MX28_PAD_LCD_D10__LCD_D10
687 MX28_PAD_LCD_D11__LCD_D11
688 MX28_PAD_LCD_D12__LCD_D12
689 MX28_PAD_LCD_D13__LCD_D13
690 MX28_PAD_LCD_D14__LCD_D14
691 MX28_PAD_LCD_D15__LCD_D15
692 MX28_PAD_LCD_D16__LCD_D16
693 MX28_PAD_LCD_D17__LCD_D17
694 >;
695 fsl,drive-strength = <MXS_DRIVE_4mA>;
696 fsl,voltage = <MXS_VOLTAGE_HIGH>;
697 fsl,pull-up = <MXS_PULL_DISABLE>;
698 };
699
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]700 lcdif_16bit_pins_a: lcdif-16bit@0 {
701 reg = <0>;
702 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]703 MX28_PAD_LCD_D00__LCD_D0
704 MX28_PAD_LCD_D01__LCD_D1
705 MX28_PAD_LCD_D02__LCD_D2
706 MX28_PAD_LCD_D03__LCD_D3
707 MX28_PAD_LCD_D04__LCD_D4
708 MX28_PAD_LCD_D05__LCD_D5
709 MX28_PAD_LCD_D06__LCD_D6
710 MX28_PAD_LCD_D07__LCD_D7
711 MX28_PAD_LCD_D08__LCD_D8
712 MX28_PAD_LCD_D09__LCD_D9
713 MX28_PAD_LCD_D10__LCD_D10
714 MX28_PAD_LCD_D11__LCD_D11
715 MX28_PAD_LCD_D12__LCD_D12
716 MX28_PAD_LCD_D13__LCD_D13
717 MX28_PAD_LCD_D14__LCD_D14
718 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]719 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]720 fsl,drive-strength = <MXS_DRIVE_4mA>;
721 fsl,voltage = <MXS_VOLTAGE_HIGH>;
722 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]723 };
724
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]725 lcdif_sync_pins_a: lcdif-sync@0 {
726 reg = <0>;
727 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]728 MX28_PAD_LCD_RS__LCD_DOTCLK
729 MX28_PAD_LCD_CS__LCD_ENABLE
730 MX28_PAD_LCD_RD_E__LCD_VSYNC
731 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]732 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]733 fsl,drive-strength = <MXS_DRIVE_4mA>;
734 fsl,voltage = <MXS_VOLTAGE_HIGH>;
735 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]736 };
737
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]738 can0_pins_a: can0@0 {
739 reg = <0>;
740 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]741 MX28_PAD_GPMI_RDY2__CAN0_TX
742 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]743 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]744 fsl,drive-strength = <MXS_DRIVE_4mA>;
745 fsl,voltage = <MXS_VOLTAGE_HIGH>;
746 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]747 };
748
749 can1_pins_a: can1@0 {
750 reg = <0>;
751 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]752 MX28_PAD_GPMI_CE2N__CAN1_TX
753 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]754 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]755 fsl,drive-strength = <MXS_DRIVE_4mA>;
756 fsl,voltage = <MXS_VOLTAGE_HIGH>;
757 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]758 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]759
760 spi2_pins_a: spi2@0 {
761 reg = <0>;
762 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]763 MX28_PAD_SSP2_SCK__SSP2_SCK
764 MX28_PAD_SSP2_MOSI__SSP2_CMD
765 MX28_PAD_SSP2_MISO__SSP2_D0
766 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]767 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]768 fsl,drive-strength = <MXS_DRIVE_8mA>;
769 fsl,voltage = <MXS_VOLTAGE_HIGH>;
770 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]771 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]772
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]773 spi3_pins_a: spi3@0 {
774 reg = <0>;
775 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]776 MX28_PAD_AUART2_RX__SSP3_D4
777 MX28_PAD_AUART2_TX__SSP3_D5
778 MX28_PAD_SSP3_SCK__SSP3_SCK
779 MX28_PAD_SSP3_MOSI__SSP3_CMD
780 MX28_PAD_SSP3_MISO__SSP3_D0
781 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]782 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]783 fsl,drive-strength = <MXS_DRIVE_8mA>;
784 fsl,voltage = <MXS_VOLTAGE_HIGH>;
785 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]786 };
787
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]788 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]789 reg = <0>;
790 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]791 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]792 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]793 fsl,drive-strength = <MXS_DRIVE_12mA>;
794 fsl,voltage = <MXS_VOLTAGE_HIGH>;
795 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]796 };
797
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]798 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]799 reg = <1>;
800 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]801 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]802 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]803 fsl,drive-strength = <MXS_DRIVE_12mA>;
804 fsl,voltage = <MXS_VOLTAGE_HIGH>;
805 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]806 };
807
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]808 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]809 reg = <0>;
810 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]811 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]812 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]813 fsl,drive-strength = <MXS_DRIVE_12mA>;
814 fsl,voltage = <MXS_VOLTAGE_HIGH>;
815 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]816 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]817
818 usb0_id_pins_a: usb0id@0 {
819 reg = <0>;
820 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]821 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]822 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]823 fsl,drive-strength = <MXS_DRIVE_12mA>;
824 fsl,voltage = <MXS_VOLTAGE_HIGH>;
825 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]826 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]827
828 usb0_id_pins_b: usb0id1@0 {
829 reg = <0>;
830 fsl,pinmux-ids = <
831 MX28_PAD_PWM2__USB0_ID
832 >;
833 fsl,drive-strength = <MXS_DRIVE_12mA>;
834 fsl,voltage = <MXS_VOLTAGE_HIGH>;
835 fsl,pull-up = <MXS_PULL_ENABLE>;
836 };
837
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]838 };
839
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]840 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]841 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]842 reg = <0x8001c000 0x2000>;
843 interrupts = <89>;
844 status = "disabled";
845 };
846
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]847 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]848 reg = <0x80022000 0x2000>;
849 status = "disabled";
850 };
851
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]852 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]853 compatible = "fsl,imx28-dma-apbx";
854 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]855 interrupts = <78 79 66 0
856 80 81 68 69
857 70 71 72 73
858 74 75 76 77>;
859 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
860 "saif0", "saif1", "i2c0", "i2c1",
861 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
862 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
863 #dma-cells = <1>;
864 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]865 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]866 };
867
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]868 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]869 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]870 reg = <0x80028000 0x2000>;
871 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]872 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]873 };
874
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]875 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]876 reg = <0x8002a000 0x2000>;
877 interrupts = <39>;
878 status = "disabled";
879 };
880
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]881 ocotp: ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800[diff] [blame]882 compatible = "fsl,ocotp";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]883 reg = <0x8002c000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]884 status = "disabled";
885 };
886
887 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]888 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]889 status = "disabled";
890 };
891
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]892 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]893 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]894 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]895 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]896 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]897 dmas = <&dma_apbh 13>;
898 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]899 status = "disabled";
900 };
901
902 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]903 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]904 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]905 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]906 clocks = <&clks 58>, <&clks 58>;
907 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]908 status = "disabled";
909 };
910
911 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]912 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]913 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]914 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]915 clocks = <&clks 59>, <&clks 59>;
916 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]917 status = "disabled";
918 };
919
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]920 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]921 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]922 status = "disabled";
923 };
924
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]925 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]926 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]927 status = "disabled";
928 };
929
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]930 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]931 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]932 status = "disabled";
933 };
934
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]935 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]936 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]937 status = "disabled";
938 };
939
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]940 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]941 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]942 status = "disabled";
943 };
944
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]945 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]946 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]947 status = "disabled";
948 };
949
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]950 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]951 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]952 status = "disabled";
953 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]954 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]955
956 apbx@80040000 {
957 compatible = "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <1>;
960 reg = <0x80040000 0x40000>;
961 ranges;
962
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]963 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]964 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]965 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]966 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]967 };
968
969 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]970 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]971 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]972 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]973 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]974 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]975 dmas = <&dma_apbx 4>;
976 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]977 status = "disabled";
978 };
979
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]980 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]981 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]982 status = "disabled";
983 };
984
985 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]986 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]987 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]988 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]989 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]990 dmas = <&dma_apbx 5>;
991 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]992 status = "disabled";
993 };
994
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]995 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]996 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]997 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]998 interrupts = <10 14 15 16 17 18 19
999 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1000 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1001 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1002 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1003 };
1004
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1005 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1006 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1007 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1008 dmas = <&dma_apbx 2>;
1009 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1010 status = "disabled";
1011 };
1012
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1013 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1014 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1015 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1016 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1017 };
1018
1019 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1023 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1024 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1025 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1026 dmas = <&dma_apbx 6>;
1027 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1028 status = "disabled";
1029 };
1030
1031 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1035 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1036 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1037 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1038 dmas = <&dma_apbx 7>;
1039 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1040 status = "disabled";
1041 };
1042
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1043 pwm: pwm@80064000 {
1044 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1045 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1046 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1047 #pwm-cells = <2>;
1048 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1049 status = "disabled";
1050 };
1051
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1052 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1053 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1054 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1055 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1056 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1057 };
1058
1059 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1060 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1061 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1062 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1063 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1064 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1065 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1066 status = "disabled";
1067 };
1068
1069 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1070 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1071 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1072 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1073 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1074 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1075 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1076 status = "disabled";
1077 };
1078
1079 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1080 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1081 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1082 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1083 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1084 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1085 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1086 status = "disabled";
1087 };
1088
1089 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1090 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1091 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1092 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1093 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1094 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1095 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1096 status = "disabled";
1097 };
1098
1099 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1100 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1101 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1102 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1103 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1104 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1105 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1106 status = "disabled";
1107 };
1108
1109 duart: serial@80074000 {
1110 compatible = "arm,pl011", "arm,primecell";
1111 reg = <0x80074000 0x1000>;
1112 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1113 clocks = <&clks 45>, <&clks 26>;
1114 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1115 status = "disabled";
1116 };
1117
1118 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1119 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1120 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1121 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1122 status = "disabled";
1123 };
1124
1125 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1126 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1127 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1128 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1129 status = "disabled";
1130 };
1131 };
1132 };
1133
1134 ahb@80080000 {
1135 compatible = "simple-bus";
1136 #address-cells = <1>;
1137 #size-cells = <1>;
1138 reg = <0x80080000 0x80000>;
1139 ranges;
1140
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1141 usb0: usb@80080000 {
1142 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1143 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1144 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1145 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1146 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1147 status = "disabled";
1148 };
1149
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1150 usb1: usb@80090000 {
1151 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1152 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1153 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1154 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1155 fsl,usbphy = <&usbphy1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1156 status = "disabled";
1157 };
1158
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1159 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1160 reg = <0x800c0000 0x10000>;
1161 status = "disabled";
1162 };
1163
1164 mac0: ethernet@800f0000 {
1165 compatible = "fsl,imx28-fec";
1166 reg = <0x800f0000 0x4000>;
1167 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1168 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1169 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1170 status = "disabled";
1171 };
1172
1173 mac1: ethernet@800f4000 {
1174 compatible = "fsl,imx28-fec";
1175 reg = <0x800f4000 0x4000>;
1176 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1177 clocks = <&clks 57>, <&clks 57>;
1178 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1179 status = "disabled";
1180 };
1181
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1182 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1183 reg = <0x800f8000 0x8000>;
1184 status = "disabled";
1185 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1186 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1187
1188 iio_hwmon {
1189 compatible = "iio-hwmon";
1190 io-channels = <&lradc 8>;
1191 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1192};