blob: 524933b014838cea66f4d3a0f47a513bcb9023a5 [file] [log] [blame]
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
Ben Widawsky714244e2017-08-01 09:58:16 -070033#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drm_crtc.h>
35#include <drm/drm_fourcc.h>
Ville Syrjälä17316932013-04-24 18:52:38 +030036#include <drm/drm_rect.h>
Chandra Konduruc3318792015-04-15 15:15:02 -070037#include <drm/drm_atomic.h>
Matt Roperea2c67b2014-12-23 10:41:52 -080038#include <drm/drm_plane_helper.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080039#include "intel_drv.h"
Chris Wilson5d723d72016-08-04 16:32:35 +010040#include "intel_frontbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/i915_drm.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080042#include "i915_drv.h"
43
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +030044static bool
45format_is_yuv(uint32_t format)
46{
47 switch (format) {
48 case DRM_FORMAT_YUYV:
49 case DRM_FORMAT_UYVY:
50 case DRM_FORMAT_VYUY:
51 case DRM_FORMAT_YVYU:
52 return true;
53 default:
54 return false;
55 }
56}
57
Ville Syrjälädfd2e9a2016-05-18 11:34:38 +030058int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
59 int usecs)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030060{
61 /* paranoia */
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030062 if (!adjusted_mode->crtc_htotal)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030063 return 1;
64
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030065 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
66 1000 * adjusted_mode->crtc_htotal);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030067}
68
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010069#define VBLANK_EVASION_TIME_US 100
70
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020071/**
72 * intel_pipe_update_start() - start update of a set of display registers
73 * @crtc: the crtc of which the registers are going to be updated
74 * @start_vbl_count: vblank counter return pointer used for error checking
75 *
76 * Mark the start of an update to pipe registers that should be updated
77 * atomically regarding vblank. If the next vblank will happens within
78 * the next 100 us, this function waits until the vblank passes.
79 *
80 * After a successful call to this function, interrupts will be disabled
81 * until a subsequent call to intel_pipe_update_end(). That is done to
82 * avoid random delays. The value written to @start_vbl_count should be
83 * supplied to intel_pipe_update_end() for error checking.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020084 */
Maarten Lankhorst34e0adb2015-08-31 13:04:25 +020085void intel_pipe_update_start(struct intel_crtc *crtc)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030086{
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020087 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä124abe02015-09-08 13:40:45 +030088 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030089 long timeout = msecs_to_jiffies_timeout(1);
90 int scanline, min, max, vblank_start;
Ville Syrjälä210871b62014-05-22 19:00:50 +030091 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020092 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
93 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030094 DEFINE_WAIT(wait);
95
Ville Syrjälä124abe02015-09-08 13:40:45 +030096 vblank_start = adjusted_mode->crtc_vblank_start;
97 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030098 vblank_start = DIV_ROUND_UP(vblank_start, 2);
99
100 /* FIXME needs to be calibrated sensibly */
Maarten Lankhorste1edbd42017-02-28 15:28:48 +0100101 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
102 VBLANK_EVASION_TIME_US);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300103 max = vblank_start - 1;
104
Maarten Lankhorst8f539a832015-07-13 16:30:32 +0200105 local_irq_disable();
Maarten Lankhorst8f539a832015-07-13 16:30:32 +0200106
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300107 if (min <= 0 || max <= 0)
Maarten Lankhorst8f539a832015-07-13 16:30:32 +0200108 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300109
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100110 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
Maarten Lankhorst8f539a832015-07-13 16:30:32 +0200111 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300112
Jesse Barnesd637ce32015-09-17 08:08:32 -0700113 crtc->debug.min_vbl = min;
114 crtc->debug.max_vbl = max;
115 trace_i915_pipe_update_start(crtc);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300116
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300117 for (;;) {
118 /*
119 * prepare_to_wait() has a memory barrier, which guarantees
120 * other CPUs can see the task state update by the time we
121 * read the scanline.
122 */
Ville Syrjälä210871b62014-05-22 19:00:50 +0300123 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300124
125 scanline = intel_get_crtc_scanline(crtc);
126 if (scanline < min || scanline > max)
127 break;
128
129 if (timeout <= 0) {
130 DRM_ERROR("Potential atomic update failure on pipe %c\n",
131 pipe_name(crtc->pipe));
132 break;
133 }
134
135 local_irq_enable();
136
137 timeout = schedule_timeout(timeout);
138
139 local_irq_disable();
140 }
141
Ville Syrjälä210871b62014-05-22 19:00:50 +0300142 finish_wait(wq, &wait);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300143
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100144 drm_crtc_vblank_put(&crtc->base);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300145
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +0200146 /*
147 * On VLV/CHV DSI the scanline counter would appear to
148 * increment approx. 1/3 of a scanline before start of vblank.
149 * The registers still get latched at start of vblank however.
150 * This means we must not write any registers on the first
151 * line of vblank (since not the whole line is actually in
152 * vblank). And unfortunately we can't use the interrupt to
153 * wait here since it will fire too soon. We could use the
154 * frame start interrupt instead since it will fire after the
155 * critical scanline, but that would require more changes
156 * in the interrupt code. So for now we'll just do the nasty
157 * thing and poll for the bad scanline to pass us by.
158 *
159 * FIXME figure out if BXT+ DSI suffers from this as well
160 */
161 while (need_vlv_dsi_wa && scanline == vblank_start)
162 scanline = intel_get_crtc_scanline(crtc);
163
Jesse Barneseb120ef2015-09-15 14:19:32 -0700164 crtc->debug.scanline_start = scanline;
165 crtc->debug.start_vbl_time = ktime_get();
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200166 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300167
Jesse Barnesd637ce32015-09-17 08:08:32 -0700168 trace_i915_pipe_update_vblank_evaded(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300169}
170
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200171/**
172 * intel_pipe_update_end() - end update of a set of display registers
173 * @crtc: the crtc of which the registers were updated
174 * @start_vbl_count: start vblank counter (used for error checking)
175 *
176 * Mark the end of an update started with intel_pipe_update_start(). This
177 * re-enables interrupts and verifies the update was actually completed
178 * before a vblank using the value of @start_vbl_count.
179 */
Daniel Vetter8b5d27b2017-07-20 19:57:53 +0200180void intel_pipe_update_end(struct intel_crtc *crtc)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300181{
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300182 enum pipe pipe = crtc->pipe;
Jesse Barneseb120ef2015-09-15 14:19:32 -0700183 int scanline_end = intel_get_crtc_scanline(crtc);
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200184 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
Maarten Lankhorst85a62bf2015-09-01 12:15:33 +0200185 ktime_t end_vbl_time = ktime_get();
Bing Niua94f2b92017-03-08 15:14:03 -0500186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300187
Jesse Barnesd637ce32015-09-17 08:08:32 -0700188 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300189
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200190 /* We're still in the vblank-evade critical section, this can't race.
191 * Would be slightly nice to just grab the vblank count and arm the
192 * event outside of the critical section - the spinlock might spin for a
193 * while ... */
194 if (crtc->base.state->event) {
195 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
196
197 spin_lock(&crtc->base.dev->event_lock);
198 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
199 spin_unlock(&crtc->base.dev->event_lock);
200
201 crtc->base.state->event = NULL;
202 }
203
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300204 local_irq_enable();
205
Bing Niua94f2b92017-03-08 15:14:03 -0500206 if (intel_vgpu_active(dev_priv))
207 return;
208
Jesse Barneseb120ef2015-09-15 14:19:32 -0700209 if (crtc->debug.start_vbl_count &&
210 crtc->debug.start_vbl_count != end_vbl_count) {
211 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
212 pipe_name(pipe), crtc->debug.start_vbl_count,
213 end_vbl_count,
214 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
215 crtc->debug.min_vbl, crtc->debug.max_vbl,
216 crtc->debug.scanline_start, scanline_end);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300217 }
218#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
219 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
220 VBLANK_EVASION_TIME_US)
Maarten Lankhorste1edbd42017-02-28 15:28:48 +0100221 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
222 pipe_name(pipe),
223 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
224 VBLANK_EVASION_TIME_US);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300225#endif
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300226}
227
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800228static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300229skl_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100230 const struct intel_crtc_state *crtc_state,
231 const struct intel_plane_state *plane_state)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000232{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300233 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
234 const struct drm_framebuffer *fb = plane_state->base.fb;
235 enum plane_id plane_id = plane->id;
236 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200237 u32 plane_ctl = plane_state->ctl;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100238 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200239 u32 surf_addr = plane_state->main.offset;
Ville Syrjälä8d0deca2016-02-15 22:54:41 +0200240 unsigned int rotation = plane_state->base.rotation;
Ville Syrjäläd2196772016-01-28 18:33:11 +0200241 u32 stride = skl_plane_stride(fb, 0, rotation);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700242 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300243 int crtc_x = plane_state->base.dst.x1;
244 int crtc_y = plane_state->base.dst.y1;
245 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
246 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200247 uint32_t x = plane_state->main.x;
248 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300249 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
250 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200251 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000252
Ville Syrjälä6687c902015-09-15 13:16:41 +0300253 /* Sizes are 0 based */
254 src_w--;
255 src_h--;
256 crtc_w--;
257 crtc_h--;
258
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200259 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
260
Rodrigo Vivi6602be02017-07-06 14:01:13 -0700261 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200262 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
263 PLANE_COLOR_PIPE_GAMMA_ENABLE |
264 PLANE_COLOR_PIPE_CSC_ENABLE |
265 PLANE_COLOR_PLANE_GAMMA_DISABLE);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200266 }
267
268 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200269 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
270 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
271 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200272 }
273
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200274 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
275 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
276 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700277 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
278 (plane_state->aux.offset - surf_addr) | aux_stride);
279 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
280 (plane_state->aux.y << 16) | plane_state->aux.x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700281
282 /* program plane scaler */
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100283 if (plane_state->scaler_id >= 0) {
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100284 int scaler_id = plane_state->scaler_id;
Imre Deak7494bcd2016-05-12 16:18:49 +0300285 const struct intel_scaler *scaler;
Chandra Konduruc3318792015-04-15 15:15:02 -0700286
Imre Deak7494bcd2016-05-12 16:18:49 +0300287 scaler = &crtc_state->scaler_state.scalers[scaler_id];
288
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200289 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
290 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
291 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
292 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
293 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
294 ((crtc_w + 1) << 16)|(crtc_h + 1));
Chandra Konduruc3318792015-04-15 15:15:02 -0700295
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200296 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
Chandra Konduruc3318792015-04-15 15:15:02 -0700297 } else {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200298 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700299 }
300
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200301 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
302 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
303 intel_plane_ggtt_offset(plane_state) + surf_addr);
304 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
305
306 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000307}
308
309static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300310skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000311{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
313 enum plane_id plane_id = plane->id;
314 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200315 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000316
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200317 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000318
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200319 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
320
321 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
322 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
323
324 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000325}
326
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000327static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300328chv_update_csc(struct intel_plane *plane, uint32_t format)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300329{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300330 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
331 enum plane_id plane_id = plane->id;
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300332
333 /* Seems RGB data bypasses the CSC always */
334 if (!format_is_yuv(format))
335 return;
336
337 /*
338 * BT.601 limited range YCbCr -> full range RGB
339 *
340 * |r| | 6537 4769 0| |cr |
341 * |g| = |-3330 4769 -1605| x |y-64|
342 * |b| | 0 4769 8263| |cb |
343 *
344 * Cb and Cr apparently come in as signed already, so no
345 * need for any offset. For Y we need to remove the offset.
346 */
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200347 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
348 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
349 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300350
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200351 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
352 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
353 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
354 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
355 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300356
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200357 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
358 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
359 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300360
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200361 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
362 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
363 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300364}
365
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200366static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
367 const struct intel_plane_state *plane_state)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700368{
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200369 const struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjälä11df4d92016-11-07 22:20:55 +0200370 unsigned int rotation = plane_state->base.rotation;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100371 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200372 u32 sprctl;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700373
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200374 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700375
Ville Syrjälä438b74a2016-12-14 23:32:55 +0200376 switch (fb->format->format) {
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700377 case DRM_FORMAT_YUYV:
378 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
379 break;
380 case DRM_FORMAT_YVYU:
381 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
382 break;
383 case DRM_FORMAT_UYVY:
384 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
385 break;
386 case DRM_FORMAT_VYUY:
387 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
388 break;
389 case DRM_FORMAT_RGB565:
390 sprctl |= SP_FORMAT_BGR565;
391 break;
392 case DRM_FORMAT_XRGB8888:
393 sprctl |= SP_FORMAT_BGRX8888;
394 break;
395 case DRM_FORMAT_ARGB8888:
396 sprctl |= SP_FORMAT_BGRA8888;
397 break;
398 case DRM_FORMAT_XBGR2101010:
399 sprctl |= SP_FORMAT_RGBX1010102;
400 break;
401 case DRM_FORMAT_ABGR2101010:
402 sprctl |= SP_FORMAT_RGBA1010102;
403 break;
404 case DRM_FORMAT_XBGR8888:
405 sprctl |= SP_FORMAT_RGBX8888;
406 break;
407 case DRM_FORMAT_ABGR8888:
408 sprctl |= SP_FORMAT_RGBA8888;
409 break;
410 default:
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200411 MISSING_CASE(fb->format->format);
412 return 0;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700413 }
414
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200415 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700416 sprctl |= SP_TILED;
417
Robert Fossc2c446a2017-05-19 16:50:17 -0400418 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälädf0cd452016-11-14 18:53:59 +0200419 sprctl |= SP_ROTATE_180;
420
Robert Fossc2c446a2017-05-19 16:50:17 -0400421 if (rotation & DRM_MODE_REFLECT_X)
Ville Syrjälä4ea7be22016-11-14 18:54:00 +0200422 sprctl |= SP_MIRROR;
423
Ville Syrjälä78587de2017-03-09 17:44:32 +0200424 if (key->flags & I915_SET_COLORKEY_SOURCE)
425 sprctl |= SP_SOURCE_KEY;
426
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200427 return sprctl;
428}
429
430static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300431vlv_update_plane(struct intel_plane *plane,
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200432 const struct intel_crtc_state *crtc_state,
433 const struct intel_plane_state *plane_state)
434{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300435 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
436 const struct drm_framebuffer *fb = plane_state->base.fb;
437 enum pipe pipe = plane->pipe;
438 enum plane_id plane_id = plane->id;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200439 u32 sprctl = plane_state->ctl;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200440 u32 sprsurf_offset = plane_state->main.offset;
441 u32 linear_offset;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200442 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
443 int crtc_x = plane_state->base.dst.x1;
444 int crtc_y = plane_state->base.dst.y1;
445 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
446 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200447 uint32_t x = plane_state->main.x;
448 uint32_t y = plane_state->main.y;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200449 unsigned long irqflags;
450
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700451 /* Sizes are 0 based */
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700452 crtc_w--;
453 crtc_h--;
454
Ville Syrjälä29490562016-01-20 18:02:50 +0200455 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300456
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200457 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
458
Ville Syrjälä78587de2017-03-09 17:44:32 +0200459 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300460 chv_update_csc(plane, fb->format->format);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200461
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200462 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200463 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
464 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
465 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200466 }
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200467 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
468 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200469
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200470 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200471 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700472 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200473 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700474
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200475 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +0300476
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200477 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
478 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
479 I915_WRITE_FW(SPSURF(pipe, plane_id),
480 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
481 POSTING_READ_FW(SPSURF(pipe, plane_id));
482
483 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700484}
485
486static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300487vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700488{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300489 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
490 enum pipe pipe = plane->pipe;
491 enum plane_id plane_id = plane->id;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200492 unsigned long irqflags;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700493
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200494 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200495
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200496 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
497
498 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
499 POSTING_READ_FW(SPSURF(pipe, plane_id));
500
501 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700502}
503
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200504static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
505 const struct intel_plane_state *plane_state)
506{
507 struct drm_i915_private *dev_priv =
508 to_i915(plane_state->base.plane->dev);
509 const struct drm_framebuffer *fb = plane_state->base.fb;
510 unsigned int rotation = plane_state->base.rotation;
511 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
512 u32 sprctl;
513
514 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
515
516 if (IS_IVYBRIDGE(dev_priv))
517 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
518
519 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
520 sprctl |= SPRITE_PIPE_CSC_ENABLE;
521
522 switch (fb->format->format) {
523 case DRM_FORMAT_XBGR8888:
524 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
525 break;
526 case DRM_FORMAT_XRGB8888:
527 sprctl |= SPRITE_FORMAT_RGBX888;
528 break;
529 case DRM_FORMAT_YUYV:
530 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
531 break;
532 case DRM_FORMAT_YVYU:
533 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
534 break;
535 case DRM_FORMAT_UYVY:
536 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
537 break;
538 case DRM_FORMAT_VYUY:
539 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
540 break;
541 default:
542 MISSING_CASE(fb->format->format);
543 return 0;
544 }
545
546 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
547 sprctl |= SPRITE_TILED;
548
Robert Fossc2c446a2017-05-19 16:50:17 -0400549 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200550 sprctl |= SPRITE_ROTATE_180;
551
552 if (key->flags & I915_SET_COLORKEY_DESTINATION)
553 sprctl |= SPRITE_DEST_KEY;
554 else if (key->flags & I915_SET_COLORKEY_SOURCE)
555 sprctl |= SPRITE_SOURCE_KEY;
556
557 return sprctl;
558}
559
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700560static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300561ivb_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100562 const struct intel_crtc_state *crtc_state,
563 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800564{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300565 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
566 const struct drm_framebuffer *fb = plane_state->base.fb;
567 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200568 u32 sprctl = plane_state->ctl, sprscale = 0;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200569 u32 sprsurf_offset = plane_state->main.offset;
570 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100571 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300572 int crtc_x = plane_state->base.dst.x1;
573 int crtc_y = plane_state->base.dst.y1;
574 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
575 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200576 uint32_t x = plane_state->main.x;
577 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300578 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
579 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200580 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800581
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800582 /* Sizes are 0 based */
583 src_w--;
584 src_h--;
585 crtc_w--;
586 crtc_h--;
587
Ville Syrjälä8553c182013-12-05 15:51:39 +0200588 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800589 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800590
Ville Syrjälä29490562016-01-20 18:02:50 +0200591 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300592
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200593 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
594
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200595 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200596 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
597 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
598 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200599 }
600
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200601 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
602 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200603
Damien Lespiau5a35e992012-10-26 18:20:12 +0100604 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
605 * register */
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100606 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200607 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200608 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200609 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100610 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200611 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
Damien Lespiauc54173a2012-10-26 18:20:11 +0100612
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200613 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300614 if (plane->can_scale)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200615 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
616 I915_WRITE_FW(SPRCTL(pipe), sprctl);
617 I915_WRITE_FW(SPRSURF(pipe),
618 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
619 POSTING_READ_FW(SPRSURF(pipe));
620
621 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800622}
623
624static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300625ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800626{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300627 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
628 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200629 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800630
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200631 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
632
633 I915_WRITE_FW(SPRCTL(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800634 /* Can't leave the scaler enabled... */
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300635 if (plane->can_scale)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200636 I915_WRITE_FW(SPRSCALE(pipe), 0);
Ville Syrjälä5b633d62014-04-29 13:35:47 +0300637
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200638 I915_WRITE_FW(SPRSURF(pipe), 0);
639 POSTING_READ_FW(SPRSURF(pipe));
640
641 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800642}
643
Ville Syrjäläab330812017-04-21 21:14:32 +0300644static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
Ville Syrjälä0a375142017-03-17 23:18:00 +0200645 const struct intel_plane_state *plane_state)
646{
647 struct drm_i915_private *dev_priv =
648 to_i915(plane_state->base.plane->dev);
649 const struct drm_framebuffer *fb = plane_state->base.fb;
650 unsigned int rotation = plane_state->base.rotation;
651 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
652 u32 dvscntr;
653
654 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
655
656 if (IS_GEN6(dev_priv))
657 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
658
659 switch (fb->format->format) {
660 case DRM_FORMAT_XBGR8888:
661 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
662 break;
663 case DRM_FORMAT_XRGB8888:
664 dvscntr |= DVS_FORMAT_RGBX888;
665 break;
666 case DRM_FORMAT_YUYV:
667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
668 break;
669 case DRM_FORMAT_YVYU:
670 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
671 break;
672 case DRM_FORMAT_UYVY:
673 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
674 break;
675 case DRM_FORMAT_VYUY:
676 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
677 break;
678 default:
679 MISSING_CASE(fb->format->format);
680 return 0;
681 }
682
683 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
684 dvscntr |= DVS_TILED;
685
Robert Fossc2c446a2017-05-19 16:50:17 -0400686 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä0a375142017-03-17 23:18:00 +0200687 dvscntr |= DVS_ROTATE_180;
688
689 if (key->flags & I915_SET_COLORKEY_DESTINATION)
690 dvscntr |= DVS_DEST_KEY;
691 else if (key->flags & I915_SET_COLORKEY_SOURCE)
692 dvscntr |= DVS_SOURCE_KEY;
693
694 return dvscntr;
695}
696
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800697static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300698g4x_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100699 const struct intel_crtc_state *crtc_state,
700 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800701{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300702 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
703 const struct drm_framebuffer *fb = plane_state->base.fb;
704 enum pipe pipe = plane->pipe;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200705 u32 dvscntr = plane_state->ctl, dvsscale = 0;
706 u32 dvssurf_offset = plane_state->main.offset;
707 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100708 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300709 int crtc_x = plane_state->base.dst.x1;
710 int crtc_y = plane_state->base.dst.y1;
711 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
712 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200713 uint32_t x = plane_state->main.x;
714 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300715 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
716 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200717 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800718
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800719 /* Sizes are 0 based */
720 src_w--;
721 src_h--;
722 crtc_w--;
723 crtc_h--;
724
Ville Syrjälä8368f012013-12-05 15:51:31 +0200725 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800726 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
727
Ville Syrjälä29490562016-01-20 18:02:50 +0200728 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300729
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200730 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
731
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200732 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200733 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
734 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
735 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200736 }
737
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200738 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
739 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200740
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200741 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200742 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100743 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200744 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100745
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200746 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
747 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
748 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
749 I915_WRITE_FW(DVSSURF(pipe),
750 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
751 POSTING_READ_FW(DVSSURF(pipe));
752
753 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800754}
755
756static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300757g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800758{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300759 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
760 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200761 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800762
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200763 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
764
765 I915_WRITE_FW(DVSCNTR(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800766 /* Disable the scaler */
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200767 I915_WRITE_FW(DVSSCALE(pipe), 0);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200768
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200769 I915_WRITE_FW(DVSSURF(pipe), 0);
770 POSTING_READ_FW(DVSSURF(pipe));
771
772 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800773}
774
Jesse Barnes8ea30862012-01-03 08:05:39 -0800775static int
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300776intel_check_sprite_plane(struct intel_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +0200777 struct intel_crtc_state *crtc_state,
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300778 struct intel_plane_state *state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800779{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300780 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Matt Roper2b875c22014-12-01 15:40:13 -0800782 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300783 int crtc_x, crtc_y;
784 unsigned int crtc_w, crtc_h;
785 uint32_t src_x, src_y, src_w, src_h;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300786 struct drm_rect *src = &state->base.src;
787 struct drm_rect *dst = &state->base.dst;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300788 const struct drm_rect *clip = &state->clip;
Ville Syrjälä17316932013-04-24 18:52:38 +0300789 int hscale, vscale;
790 int max_scale, min_scale;
Chandra Konduru225c2282015-05-18 16:18:44 -0700791 bool can_scale;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200792 int ret;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800793
Rob Clark1638d302016-11-05 11:08:08 -0400794 *src = drm_plane_state_src(&state->base);
795 *dst = drm_plane_state_dest(&state->base);
Ville Syrjäläf8856a42016-07-26 19:07:00 +0300796
Matt Ropercf4c7c12014-12-04 10:27:42 -0800797 if (!fb) {
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300798 state->base.visible = false;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +0200799 return 0;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800800 }
Jesse Barnes5e1bac22013-03-26 09:25:43 -0700801
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800802 /* Don't modify another pipe's plane */
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300803 if (plane->pipe != crtc->pipe) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300804 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800805 return -EINVAL;
Ville Syrjälä17316932013-04-24 18:52:38 +0300806 }
807
808 /* FIXME check all gen limits */
809 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
810 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
811 return -EINVAL;
812 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800813
Chandra Konduru225c2282015-05-18 16:18:44 -0700814 /* setup can_scale, min_scale, max_scale */
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100815 if (INTEL_GEN(dev_priv) >= 9) {
Chandra Konduru225c2282015-05-18 16:18:44 -0700816 /* use scaler when colorkey is not required */
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200817 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
Chandra Konduru225c2282015-05-18 16:18:44 -0700818 can_scale = 1;
819 min_scale = 1;
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300820 max_scale = skl_max_scale(crtc, crtc_state);
Chandra Konduru225c2282015-05-18 16:18:44 -0700821 } else {
822 can_scale = 0;
823 min_scale = DRM_PLANE_HELPER_NO_SCALING;
824 max_scale = DRM_PLANE_HELPER_NO_SCALING;
825 }
826 } else {
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300827 can_scale = plane->can_scale;
828 max_scale = plane->max_downscale << 16;
829 min_scale = plane->can_scale ? 1 : (1 << 16);
Chandra Konduru225c2282015-05-18 16:18:44 -0700830 }
831
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300832 /*
833 * FIXME the following code does a bunch of fuzzy adjustments to the
834 * coordinates and sizes. We probably need some way to decide whether
835 * more strict checking should be done instead.
836 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300837 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800838 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530839
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300840 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300841 BUG_ON(hscale < 0);
Ville Syrjälä17316932013-04-24 18:52:38 +0300842
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300843 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300844 BUG_ON(vscale < 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800845
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300846 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800847
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300848 crtc_x = dst->x1;
849 crtc_y = dst->y1;
850 crtc_w = drm_rect_width(dst);
851 crtc_h = drm_rect_height(dst);
Damien Lespiau2d354c32012-10-22 18:19:27 +0100852
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300853 if (state->base.visible) {
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300854 /* check again in case clipping clamped the results */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300855 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300856 if (hscale < 0) {
857 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200858 drm_rect_debug_print("src: ", src, true);
859 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300860
861 return hscale;
862 }
863
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300864 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300865 if (vscale < 0) {
866 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200867 drm_rect_debug_print("src: ", src, true);
868 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300869
870 return vscale;
871 }
872
Ville Syrjälä17316932013-04-24 18:52:38 +0300873 /* Make the source viewport size an exact multiple of the scaling factors. */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300874 drm_rect_adjust_size(src,
875 drm_rect_width(dst) * hscale - drm_rect_width(src),
876 drm_rect_height(dst) * vscale - drm_rect_height(src));
Ville Syrjälä17316932013-04-24 18:52:38 +0300877
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300878 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800879 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530880
Ville Syrjälä17316932013-04-24 18:52:38 +0300881 /* sanity check to make sure the src viewport wasn't enlarged */
Matt Roperea2c67b2014-12-23 10:41:52 -0800882 WARN_ON(src->x1 < (int) state->base.src_x ||
883 src->y1 < (int) state->base.src_y ||
884 src->x2 > (int) state->base.src_x + state->base.src_w ||
885 src->y2 > (int) state->base.src_y + state->base.src_h);
Ville Syrjälä17316932013-04-24 18:52:38 +0300886
887 /*
888 * Hardware doesn't handle subpixel coordinates.
889 * Adjust to (macro)pixel boundary, but be careful not to
890 * increase the source viewport size, because that could
891 * push the downscaling factor out of bounds.
Ville Syrjälä17316932013-04-24 18:52:38 +0300892 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300893 src_x = src->x1 >> 16;
894 src_w = drm_rect_width(src) >> 16;
895 src_y = src->y1 >> 16;
896 src_h = drm_rect_height(src) >> 16;
Ville Syrjälä17316932013-04-24 18:52:38 +0300897
Ville Syrjälä438b74a2016-12-14 23:32:55 +0200898 if (format_is_yuv(fb->format->format)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300899 src_x &= ~1;
900 src_w &= ~1;
901
902 /*
903 * Must keep src and dst the
904 * same if we can't scale.
905 */
Chandra Konduru225c2282015-05-18 16:18:44 -0700906 if (!can_scale)
Ville Syrjälä17316932013-04-24 18:52:38 +0300907 crtc_w &= ~1;
908
909 if (crtc_w == 0)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300910 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300911 }
912 }
913
914 /* Check size restrictions when scaling */
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300915 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300916 unsigned int width_bytes;
Ville Syrjälä353c8592016-12-14 23:30:57 +0200917 int cpp = fb->format->cpp[0];
Ville Syrjälä17316932013-04-24 18:52:38 +0300918
Chandra Konduru225c2282015-05-18 16:18:44 -0700919 WARN_ON(!can_scale);
Ville Syrjälä17316932013-04-24 18:52:38 +0300920
921 /* FIXME interlacing min height is 6 */
922
923 if (crtc_w < 3 || crtc_h < 3)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300924 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300925
926 if (src_w < 3 || src_h < 3)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300927 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300928
Ville Syrjäläac484962016-01-20 21:05:26 +0200929 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
Ville Syrjälä17316932013-04-24 18:52:38 +0300930
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100931 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
Chandra Konduruc3318792015-04-15 15:15:02 -0700932 width_bytes > 4096 || fb->pitches[0] > 4096)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300933 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
934 return -EINVAL;
935 }
936 }
937
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300938 if (state->base.visible) {
Chandra Konduru0a5ae1b2015-04-09 16:41:54 -0700939 src->x1 = src_x << 16;
940 src->x2 = (src_x + src_w) << 16;
941 src->y1 = src_y << 16;
942 src->y2 = (src_y + src_h) << 16;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300943 }
944
945 dst->x1 = crtc_x;
946 dst->x2 = crtc_x + crtc_w;
947 dst->y1 = crtc_y;
948 dst->y2 = crtc_y + crtc_h;
949
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100950 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200951 ret = skl_check_plane_surface(state);
952 if (ret)
953 return ret;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200954
955 state->ctl = skl_plane_ctl(crtc_state, state);
956 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200957 ret = i9xx_check_plane_surface(state);
958 if (ret)
959 return ret;
960
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200961 state->ctl = vlv_sprite_ctl(crtc_state, state);
962 } else if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200963 ret = i9xx_check_plane_surface(state);
964 if (ret)
965 return ret;
966
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200967 state->ctl = ivb_sprite_ctl(crtc_state, state);
968 } else {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200969 ret = i9xx_check_plane_surface(state);
970 if (ret)
971 return ret;
972
Ville Syrjäläab330812017-04-21 21:14:32 +0300973 state->ctl = g4x_sprite_ctl(crtc_state, state);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200974 }
975
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300976 return 0;
977}
978
Jesse Barnes8ea30862012-01-03 08:05:39 -0800979int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
980 struct drm_file *file_priv)
981{
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100982 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes8ea30862012-01-03 08:05:39 -0800983 struct drm_intel_sprite_colorkey *set = data;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800984 struct drm_plane *plane;
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200985 struct drm_plane_state *plane_state;
986 struct drm_atomic_state *state;
987 struct drm_modeset_acquire_ctx ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800988 int ret = 0;
989
Jesse Barnes8ea30862012-01-03 08:05:39 -0800990 /* Make sure we don't try to enable both src & dest simultaneously */
991 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
992 return -EINVAL;
993
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100994 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200995 set->flags & I915_SET_COLORKEY_DESTINATION)
996 return -EINVAL;
997
Rob Clark7707e652014-07-17 23:30:04 -0400998 plane = drm_plane_find(dev, set->plane_id);
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200999 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1000 return -ENOENT;
1001
1002 drm_modeset_acquire_init(&ctx, 0);
1003
1004 state = drm_atomic_state_alloc(plane->dev);
1005 if (!state) {
1006 ret = -ENOMEM;
1007 goto out;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001008 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001009 state->acquire_ctx = &ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001010
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001011 while (1) {
1012 plane_state = drm_atomic_get_plane_state(state, plane);
1013 ret = PTR_ERR_OR_ZERO(plane_state);
1014 if (!ret) {
1015 to_intel_plane_state(plane_state)->ckey = *set;
1016 ret = drm_atomic_commit(state);
Chandra Konduru6156a452015-04-27 13:48:39 -07001017 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001018
1019 if (ret != -EDEADLK)
1020 break;
1021
1022 drm_atomic_state_clear(state);
1023 drm_modeset_backoff(&ctx);
Chandra Konduru6156a452015-04-27 13:48:39 -07001024 }
1025
Chris Wilson08536952016-10-14 13:18:18 +01001026 drm_atomic_state_put(state);
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001027out:
1028 drm_modeset_drop_locks(&ctx);
1029 drm_modeset_acquire_fini(&ctx);
Jesse Barnes8ea30862012-01-03 08:05:39 -08001030 return ret;
1031}
1032
Ville Syrjäläab330812017-04-21 21:14:32 +03001033static const uint32_t g4x_plane_formats[] = {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001034 DRM_FORMAT_XRGB8888,
1035 DRM_FORMAT_YUYV,
1036 DRM_FORMAT_YVYU,
1037 DRM_FORMAT_UYVY,
1038 DRM_FORMAT_VYUY,
1039};
1040
Ben Widawsky714244e2017-08-01 09:58:16 -07001041static const uint64_t i9xx_plane_format_modifiers[] = {
1042 I915_FORMAT_MOD_X_TILED,
1043 DRM_FORMAT_MOD_LINEAR,
1044 DRM_FORMAT_MOD_INVALID
1045};
1046
Damien Lespiaudada2d52015-05-12 16:13:22 +01001047static const uint32_t snb_plane_formats[] = {
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001048 DRM_FORMAT_XBGR8888,
1049 DRM_FORMAT_XRGB8888,
1050 DRM_FORMAT_YUYV,
1051 DRM_FORMAT_YVYU,
1052 DRM_FORMAT_UYVY,
1053 DRM_FORMAT_VYUY,
1054};
1055
Damien Lespiaudada2d52015-05-12 16:13:22 +01001056static const uint32_t vlv_plane_formats[] = {
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001057 DRM_FORMAT_RGB565,
1058 DRM_FORMAT_ABGR8888,
1059 DRM_FORMAT_ARGB8888,
1060 DRM_FORMAT_XBGR8888,
1061 DRM_FORMAT_XRGB8888,
1062 DRM_FORMAT_XBGR2101010,
1063 DRM_FORMAT_ABGR2101010,
1064 DRM_FORMAT_YUYV,
1065 DRM_FORMAT_YVYU,
1066 DRM_FORMAT_UYVY,
1067 DRM_FORMAT_VYUY,
1068};
1069
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001070static uint32_t skl_plane_formats[] = {
1071 DRM_FORMAT_RGB565,
1072 DRM_FORMAT_ABGR8888,
1073 DRM_FORMAT_ARGB8888,
1074 DRM_FORMAT_XBGR8888,
1075 DRM_FORMAT_XRGB8888,
1076 DRM_FORMAT_YUYV,
1077 DRM_FORMAT_YVYU,
1078 DRM_FORMAT_UYVY,
1079 DRM_FORMAT_VYUY,
1080};
1081
Ben Widawsky714244e2017-08-01 09:58:16 -07001082static const uint64_t skl_plane_format_modifiers[] = {
1083 I915_FORMAT_MOD_X_TILED,
1084 DRM_FORMAT_MOD_LINEAR,
1085 DRM_FORMAT_MOD_INVALID
1086};
1087
1088static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1089 uint32_t format,
1090 uint64_t modifier)
1091{
1092 switch (format) {
1093 case DRM_FORMAT_XBGR8888:
1094 case DRM_FORMAT_XRGB8888:
1095 case DRM_FORMAT_YUYV:
1096 case DRM_FORMAT_YVYU:
1097 case DRM_FORMAT_UYVY:
1098 case DRM_FORMAT_VYUY:
1099 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1100 modifier == I915_FORMAT_MOD_X_TILED)
1101 return true;
1102 /* fall through */
1103 default:
1104 return false;
1105 }
1106}
1107
1108static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1109 uint32_t format,
1110 uint64_t modifier)
1111{
1112 switch (format) {
1113 case DRM_FORMAT_YUYV:
1114 case DRM_FORMAT_YVYU:
1115 case DRM_FORMAT_UYVY:
1116 case DRM_FORMAT_VYUY:
1117 case DRM_FORMAT_RGB565:
1118 case DRM_FORMAT_XRGB8888:
1119 case DRM_FORMAT_ARGB8888:
1120 case DRM_FORMAT_XBGR2101010:
1121 case DRM_FORMAT_ABGR2101010:
1122 case DRM_FORMAT_XBGR8888:
1123 case DRM_FORMAT_ABGR8888:
1124 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1125 modifier == I915_FORMAT_MOD_X_TILED)
1126 return true;
1127 /* fall through */
1128 default:
1129 return false;
1130 }
1131}
1132
1133static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1134 uint32_t format,
1135 uint64_t modifier)
1136{
1137 /* This is the same as primary plane since SKL has universal planes */
1138 switch (format) {
1139 case DRM_FORMAT_XRGB8888:
1140 case DRM_FORMAT_XBGR8888:
1141 case DRM_FORMAT_ARGB8888:
1142 case DRM_FORMAT_ABGR8888:
1143 case DRM_FORMAT_RGB565:
1144 case DRM_FORMAT_XRGB2101010:
1145 case DRM_FORMAT_XBGR2101010:
1146 case DRM_FORMAT_YUYV:
1147 case DRM_FORMAT_YVYU:
1148 case DRM_FORMAT_UYVY:
1149 case DRM_FORMAT_VYUY:
1150 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1151 return true;
1152 /* fall through */
1153 case DRM_FORMAT_C8:
1154 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1155 modifier == I915_FORMAT_MOD_X_TILED ||
1156 modifier == I915_FORMAT_MOD_Y_TILED)
1157 return true;
1158 /* fall through */
1159 default:
1160 return false;
1161 }
1162}
1163
1164static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1165 uint32_t format,
1166 uint64_t modifier)
1167{
1168 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1169
1170 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1171 return false;
1172
1173 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1174 modifier != DRM_FORMAT_MOD_LINEAR)
1175 return false;
1176
1177 if (INTEL_GEN(dev_priv) >= 9)
1178 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1179 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1180 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1181 else
1182 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1183
1184 unreachable();
1185}
1186
Colin Ian King2d567582017-08-11 14:49:38 +01001187static const struct drm_plane_funcs intel_sprite_plane_funcs = {
Ben Widawsky714244e2017-08-01 09:58:16 -07001188 .update_plane = drm_atomic_helper_update_plane,
1189 .disable_plane = drm_atomic_helper_disable_plane,
1190 .destroy = intel_plane_destroy,
1191 .atomic_get_property = intel_plane_atomic_get_property,
1192 .atomic_set_property = intel_plane_atomic_set_property,
1193 .atomic_duplicate_state = intel_plane_duplicate_state,
1194 .atomic_destroy_state = intel_plane_destroy_state,
1195 .format_mod_supported = intel_sprite_plane_format_mod_supported,
1196};
1197
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001198struct intel_plane *
Ville Syrjälä580503c2016-10-31 22:37:00 +02001199intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int plane)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001201{
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001202 struct intel_plane *intel_plane = NULL;
1203 struct intel_plane_state *state = NULL;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001204 unsigned long possible_crtcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001205 const uint32_t *plane_formats;
Ben Widawsky714244e2017-08-01 09:58:16 -07001206 const uint64_t *modifiers;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001207 unsigned int supported_rotations;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001208 int num_plane_formats;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001209 int ret;
1210
Daniel Vetterb14c5672013-09-19 12:18:32 +02001211 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001212 if (!intel_plane) {
1213 ret = -ENOMEM;
1214 goto fail;
1215 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001216
Matt Roper8e7d6882015-01-21 16:35:41 -08001217 state = intel_create_plane_state(&intel_plane->base);
1218 if (!state) {
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001219 ret = -ENOMEM;
1220 goto fail;
Matt Roperea2c67b2014-12-23 10:41:52 -08001221 }
Matt Roper8e7d6882015-01-21 16:35:41 -08001222 intel_plane->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -08001223
Ben Widawsky714244e2017-08-01 09:58:16 -07001224 if (INTEL_GEN(dev_priv) >= 10) {
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001225 intel_plane->can_scale = true;
1226 state->scaler_id = -1;
1227
1228 intel_plane->update_plane = skl_update_plane;
1229 intel_plane->disable_plane = skl_disable_plane;
1230
1231 plane_formats = skl_plane_formats;
1232 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001233 modifiers = skl_plane_format_modifiers;
1234 } else if (INTEL_GEN(dev_priv) >= 9) {
1235 intel_plane->can_scale = true;
1236 state->scaler_id = -1;
1237
1238 intel_plane->update_plane = skl_update_plane;
1239 intel_plane->disable_plane = skl_disable_plane;
1240
1241 plane_formats = skl_plane_formats;
1242 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1243 modifiers = skl_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001244 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1245 intel_plane->can_scale = false;
1246 intel_plane->max_downscale = 1;
1247
1248 intel_plane->update_plane = vlv_update_plane;
1249 intel_plane->disable_plane = vlv_disable_plane;
1250
1251 plane_formats = vlv_plane_formats;
1252 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001253 modifiers = i9xx_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001254 } else if (INTEL_GEN(dev_priv) >= 7) {
1255 if (IS_IVYBRIDGE(dev_priv)) {
1256 intel_plane->can_scale = true;
1257 intel_plane->max_downscale = 2;
1258 } else {
1259 intel_plane->can_scale = false;
1260 intel_plane->max_downscale = 1;
1261 }
1262
1263 intel_plane->update_plane = ivb_update_plane;
1264 intel_plane->disable_plane = ivb_disable_plane;
1265
1266 plane_formats = snb_plane_formats;
1267 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001268 modifiers = i9xx_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001269 } else {
Damien Lespiau2d354c32012-10-22 18:19:27 +01001270 intel_plane->can_scale = true;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001271 intel_plane->max_downscale = 16;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001272
Ville Syrjäläab330812017-04-21 21:14:32 +03001273 intel_plane->update_plane = g4x_update_plane;
1274 intel_plane->disable_plane = g4x_disable_plane;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001275
Ben Widawsky714244e2017-08-01 09:58:16 -07001276 modifiers = i9xx_plane_format_modifiers;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01001277 if (IS_GEN6(dev_priv)) {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001278 plane_formats = snb_plane_formats;
1279 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1280 } else {
Ville Syrjäläab330812017-04-21 21:14:32 +03001281 plane_formats = g4x_plane_formats;
1282 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
Chris Wilsond1686ae2012-04-10 11:41:49 +01001283 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001284 }
1285
Dave Airlie5481e272016-10-25 16:36:13 +10001286 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001287 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001288 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1289 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
Ville Syrjälä4ea7be22016-11-14 18:54:00 +02001290 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1291 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001292 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1293 DRM_MODE_REFLECT_X;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001294 } else {
1295 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001296 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001297 }
1298
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001299 intel_plane->pipe = pipe;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001300 intel_plane->plane = plane;
Ville Syrjäläb14e5842016-11-22 18:01:56 +02001301 intel_plane->id = PLANE_SPRITE0 + plane;
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05301302 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
Matt Roperc59cb172014-12-01 15:40:16 -08001303 intel_plane->check_plane = intel_check_sprite_plane;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001304
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001305 possible_crtcs = (1 << pipe);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001306
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001307 if (INTEL_GEN(dev_priv) >= 9)
Ville Syrjälä580503c2016-10-31 22:37:00 +02001308 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ben Widawsky714244e2017-08-01 09:58:16 -07001309 possible_crtcs, &intel_sprite_plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001310 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001311 modifiers,
1312 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001313 "plane %d%c", plane + 2, pipe_name(pipe));
1314 else
Ville Syrjälä580503c2016-10-31 22:37:00 +02001315 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ben Widawsky714244e2017-08-01 09:58:16 -07001316 possible_crtcs, &intel_sprite_plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001317 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001318 modifiers,
1319 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001320 "sprite %c", sprite_name(pipe, plane));
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001321 if (ret)
1322 goto fail;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001323
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001324 drm_plane_create_rotation_property(&intel_plane->base,
Robert Fossc2c446a2017-05-19 16:50:17 -04001325 DRM_MODE_ROTATE_0,
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001326 supported_rotations);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301327
Matt Roperea2c67b2014-12-23 10:41:52 -08001328 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1329
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001330 return intel_plane;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001331
1332fail:
1333 kfree(state);
1334 kfree(intel_plane);
1335
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001336 return ERR_PTR(ret);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001337}