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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Daniel Mackaff18a62012-07-25 17:56:48 +02002/* The pxa3xx skeleton simply augments the 2xx version */
Robert Jarzmik85fe55c2014-07-30 22:51:03 +02003#include "pxa2xx.dtsi"
Robert Jarzmikd96672e2015-02-07 13:13:24 +01004#include "dt-bindings/clock/pxa-clock.h"
Daniel Mackaff18a62012-07-25 17:56:48 +02005
6/ {
7 model = "Marvell PXA27x familiy SoC";
8 compatible = "marvell,pxa27x";
9
10 pxabus {
Robert Jarzmik0cd49142015-06-20 10:17:26 +020011 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
13 reg = <0x40000000 0x10000>;
14 interrupts = <25>;
15 #dma-channels = <32>;
16 #dma-cells = <2>;
Robert Jarzmik72b195c2016-02-15 21:57:47 +010017 #dma-requests = <75>;
Robert Jarzmik0cd49142015-06-20 10:17:26 +020018 status = "okay";
19 };
20
Daniel Mackaff18a62012-07-25 17:56:48 +020021 pxairq: interrupt-controller@40d00000 {
22 marvell,intc-priority;
23 marvell,intc-nr-irqs = <34>;
24 };
Mike Dunne7b4a8d2013-09-21 12:19:34 -070025
Robert Jarzmikca91c702016-04-05 08:35:52 +020026 pinctrl: pinctrl@40e00000 {
27 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
28 0x40f00020 0x10>;
29 compatible = "marvell,pxa27x-pinctrl";
30 };
31
Robert Jarzmikd96672e2015-02-07 13:13:24 +010032 gpio: gpio@40e00000 {
33 compatible = "intel,pxa27x-gpio";
Robert Jarzmikca91c702016-04-05 08:35:52 +020034 gpio-ranges = <&pinctrl 0 0 128>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010035 clocks = <&clks CLK_NONE>;
36 };
37
Daniel Mackc40ad242018-12-01 14:54:51 +010038 usb0: usb@4c000000 {
Robert Jarzmik0ec19392015-06-20 10:17:31 +020039 compatible = "marvell,pxa-ohci";
40 reg = <0x4c000000 0x10000>;
41 interrupts = <3>;
42 clocks = <&clks CLK_USBHOST>;
43 status = "disabled";
44 };
45
Mike Dunne7b4a8d2013-09-21 12:19:34 -070046 pwm0: pwm@40b00000 {
47 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
48 reg = <0x40b00000 0x10>;
49 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010050 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070051 };
52
53 pwm1: pwm@40b00010 {
54 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
55 reg = <0x40b00010 0x10>;
56 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010057 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070058 };
59
60 pwm2: pwm@40c00000 {
61 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
62 reg = <0x40c00000 0x10>;
63 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010064 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070065 };
66
67 pwm3: pwm@40c00010 {
68 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
69 reg = <0x40c00010 0x10>;
70 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010071 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070072 };
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010073
Marcel Ziswiler8a1ecc02018-08-31 14:03:09 +020074 pwri2c: i2c@40f00180 {
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010075 compatible = "mrvl,pxa-i2c";
76 reg = <0x40f00180 0x24>;
77 interrupts = <6>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010078 clocks = <&clks CLK_PWRI2C>;
Robert Jarzmikfb185392015-06-20 10:17:30 +020079 #address-cells = <0x1>;
80 #size-cells = <0>;
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010081 status = "disabled";
82 };
Robert Jarzmikd96672e2015-02-07 13:13:24 +010083
Robert Jarzmik361818c2015-02-07 13:27:55 +010084 pxa27x_udc: udc@40600000 {
85 compatible = "marvell,pxa270-udc";
86 reg = <0x40600000 0x10000>;
87 interrupts = <11>;
88 clocks = <&clks CLK_USB>;
89 status = "disabled";
90 };
Robert Jarzmik8dcba812015-02-07 13:19:38 +010091
92 keypad: keypad@41500000 {
93 compatible = "marvell,pxa27x-keypad";
94 reg = <0x41500000 0x4c>;
95 interrupts = <4>;
96 clocks = <&clks CLK_KEYPAD>;
97 status = "disabled";
98 };
Robert Jarzmik796b7dc2015-06-20 10:17:29 +020099
100 pxa_camera: imaging@50000000 {
101 compatible = "marvell,pxa270-qci";
102 reg = <0x50000000 0x1000>;
103 interrupts = <33>;
104 dmas = <&pdma 68 0 /* Y channel */
105 &pdma 69 0 /* U channel */
106 &pdma 70 0>; /* V channel */
107 dma-names = "CI_Y", "CI_U", "CI_V";
108
109 clocks = <&clks CLK_CAMERA>;
110 clock-names = "ciclk";
111 clock-frequency = <5000000>;
112 clock-output-names = "qci_mclk";
113
114 status = "disabled";
115 };
Robert Jarzmik24a610e2018-06-25 18:44:01 +0200116
117 rtc@40900000 {
118 clocks = <&clks CLK_OSC32k768>;
119 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200120 };
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200121
122 clocks {
123 /*
124 * The muxing of external clocks/internal dividers for osc* clock
125 * sources has been hidden under the carpet by now.
126 */
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges;
130
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100131 clks: pxa2xx_clks@41300004 {
132 compatible = "marvell,pxa270-clocks";
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200133 #clock-cells = <1>;
134 status = "okay";
135 };
136 };
Robert Jarzmik8dd30752014-10-12 22:11:08 +0200137
138 timer@40a00000 {
139 compatible = "marvell,pxa-timer";
140 reg = <0x40a00000 0x20>;
141 interrupts = <26>;
142 clocks = <&clks CLK_OSTIMER>;
143 status = "okay";
144 };
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100145
146 pxa270_opp_table: opp_table0 {
147 compatible = "operating-points-v2";
148
Viresh Kumara8702712017-04-20 16:25:08 +0530149 opp-104000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100150 opp-hz = /bits/ 64 <104000000>;
151 opp-microvolt = <900000 900000 1705000>;
152 clock-latency-ns = <20>;
153 };
Viresh Kumara8702712017-04-20 16:25:08 +0530154 opp-156000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100155 opp-hz = /bits/ 64 <156000000>;
156 opp-microvolt = <1000000 1000000 1705000>;
157 clock-latency-ns = <20>;
158 };
Viresh Kumara8702712017-04-20 16:25:08 +0530159 opp-208000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100160 opp-hz = /bits/ 64 <208000000>;
161 opp-microvolt = <1180000 1180000 1705000>;
162 clock-latency-ns = <20>;
163 };
Viresh Kumara8702712017-04-20 16:25:08 +0530164 opp-312000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100165 opp-hz = /bits/ 64 <312000000>;
166 opp-microvolt = <1250000 1250000 1705000>;
167 clock-latency-ns = <20>;
168 };
Viresh Kumara8702712017-04-20 16:25:08 +0530169 opp-416000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100170 opp-hz = /bits/ 64 <416000000>;
171 opp-microvolt = <1350000 1350000 1705000>;
172 clock-latency-ns = <20>;
173 };
Viresh Kumara8702712017-04-20 16:25:08 +0530174 opp-520000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100175 opp-hz = /bits/ 64 <520000000>;
176 opp-microvolt = <1450000 1450000 1705000>;
177 clock-latency-ns = <20>;
178 };
Viresh Kumara8702712017-04-20 16:25:08 +0530179 opp-624000000 {
Robert Jarzmik74e382b2016-10-31 20:54:55 +0100180 opp-hz = /bits/ 64 <624000000>;
181 opp-microvolt = <1550000 1550000 1705000>;
182 clock-latency-ns = <20>;
183 };
184 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200185};