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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8dd3075c489ba19a8f2795199352334e52f34bed / . / arch / arm / boot / dts / pxa27x.dtsi
blob: 90b99714ad80ef2293cf254c3d43074d79cadb03 [file] [log] [blame]
Daniel Mackaff18a62012-07-25 17:56:48 +0200[diff] [blame]1/* The pxa3xx skeleton simply augments the 2xx version */
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200[diff] [blame]2#include "pxa2xx.dtsi"
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]3#include "dt-bindings/clock/pxa-clock.h"
Daniel Mackaff18a62012-07-25 17:56:48 +0200[diff] [blame]4
5/ {
6 model = "Marvell PXA27x familiy SoC";
7 compatible = "marvell,pxa27x";
8
9 pxabus {
10 pxairq: interrupt-controller@40d00000 {
11 marvell,intc-priority;
12 marvell,intc-nr-irqs = <34>;
13 };
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]14
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]15 gpio: gpio@40e00000 {
16 compatible = "intel,pxa27x-gpio";
17 clocks = <&clks CLK_NONE>;
18 };
19
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]20 pwm0: pwm@40b00000 {
21 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
22 reg = <0x40b00000 0x10>;
23 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]24 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]25 };
26
27 pwm1: pwm@40b00010 {
28 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
29 reg = <0x40b00010 0x10>;
30 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]31 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]32 };
33
34 pwm2: pwm@40c00000 {
35 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
36 reg = <0x40c00000 0x10>;
37 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]38 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]39 };
40
41 pwm3: pwm@40c00010 {
42 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
43 reg = <0x40c00010 0x10>;
44 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]45 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -0700[diff] [blame]46 };
Robert Jarzmikf374d1e2015-02-07 13:26:09 +0100[diff] [blame]47
48 pwri2c: i2c@40f000180 {
49 compatible = "mrvl,pxa-i2c";
50 reg = <0x40f00180 0x24>;
51 interrupts = <6>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]52 clocks = <&clks CLK_PWRI2C>;
Robert Jarzmikf374d1e2015-02-07 13:26:09 +0100[diff] [blame]53 status = "disabled";
54 };
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]55
Robert Jarzmik361818c2015-02-07 13:27:55 +0100[diff] [blame]56 pxa27x_udc: udc@40600000 {
57 compatible = "marvell,pxa270-udc";
58 reg = <0x40600000 0x10000>;
59 interrupts = <11>;
60 clocks = <&clks CLK_USB>;
61 status = "disabled";
62 };
Robert Jarzmik8dcba812015-02-07 13:19:38 +0100[diff] [blame]63
64 keypad: keypad@41500000 {
65 compatible = "marvell,pxa27x-keypad";
66 reg = <0x41500000 0x4c>;
67 interrupts = <4>;
68 clocks = <&clks CLK_KEYPAD>;
69 status = "disabled";
70 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200[diff] [blame]71 };
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200[diff] [blame]72
73 clocks {
74 /*
75 * The muxing of external clocks/internal dividers for osc* clock
76 * sources has been hidden under the carpet by now.
77 */
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges;
81
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100[diff] [blame]82 clks: pxa2xx_clks@41300004 {
83 compatible = "marvell,pxa270-clocks";
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200[diff] [blame]84 #clock-cells = <1>;
85 status = "okay";
86 };
87 };
Robert Jarzmik8dd30752014-10-12 22:11:08 +0200[diff] [blame^]88
89 timer@40a00000 {
90 compatible = "marvell,pxa-timer";
91 reg = <0x40a00000 0x20>;
92 interrupts = <26>;
93 clocks = <&clks CLK_OSTIMER>;
94 status = "okay";
95 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200[diff] [blame]96};