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Daniel Mackaff18a62012-07-25 17:56:48 +02001/* The pxa3xx skeleton simply augments the 2xx version */
Robert Jarzmik85fe55c2014-07-30 22:51:03 +02002#include "pxa2xx.dtsi"
Robert Jarzmikd96672e2015-02-07 13:13:24 +01003#include "dt-bindings/clock/pxa-clock.h"
Daniel Mackaff18a62012-07-25 17:56:48 +02004
5/ {
6 model = "Marvell PXA27x familiy SoC";
7 compatible = "marvell,pxa27x";
8
9 pxabus {
Robert Jarzmik0cd49142015-06-20 10:17:26 +020010 pdma: dma-controller@40000000 {
11 compatible = "marvell,pdma-1.0";
12 reg = <0x40000000 0x10000>;
13 interrupts = <25>;
14 #dma-channels = <32>;
15 #dma-cells = <2>;
Robert Jarzmik72b195c2016-02-15 21:57:47 +010016 #dma-requests = <75>;
Robert Jarzmik0cd49142015-06-20 10:17:26 +020017 status = "okay";
18 };
19
Daniel Mackaff18a62012-07-25 17:56:48 +020020 pxairq: interrupt-controller@40d00000 {
21 marvell,intc-priority;
22 marvell,intc-nr-irqs = <34>;
23 };
Mike Dunne7b4a8d2013-09-21 12:19:34 -070024
Robert Jarzmikd96672e2015-02-07 13:13:24 +010025 gpio: gpio@40e00000 {
26 compatible = "intel,pxa27x-gpio";
27 clocks = <&clks CLK_NONE>;
28 };
29
Robert Jarzmik0ec19392015-06-20 10:17:31 +020030 pxa27x_ohci: usb@4c000000 {
31 compatible = "marvell,pxa-ohci";
32 reg = <0x4c000000 0x10000>;
33 interrupts = <3>;
34 clocks = <&clks CLK_USBHOST>;
35 status = "disabled";
36 };
37
Mike Dunne7b4a8d2013-09-21 12:19:34 -070038 pwm0: pwm@40b00000 {
39 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
40 reg = <0x40b00000 0x10>;
41 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010042 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070043 };
44
45 pwm1: pwm@40b00010 {
46 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
47 reg = <0x40b00010 0x10>;
48 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010049 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070050 };
51
52 pwm2: pwm@40c00000 {
53 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
54 reg = <0x40c00000 0x10>;
55 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010056 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070057 };
58
59 pwm3: pwm@40c00010 {
60 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
61 reg = <0x40c00010 0x10>;
62 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010063 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070064 };
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010065
66 pwri2c: i2c@40f000180 {
67 compatible = "mrvl,pxa-i2c";
68 reg = <0x40f00180 0x24>;
69 interrupts = <6>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010070 clocks = <&clks CLK_PWRI2C>;
Robert Jarzmikfb185392015-06-20 10:17:30 +020071 #address-cells = <0x1>;
72 #size-cells = <0>;
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010073 status = "disabled";
74 };
Robert Jarzmikd96672e2015-02-07 13:13:24 +010075
Robert Jarzmik361818c2015-02-07 13:27:55 +010076 pxa27x_udc: udc@40600000 {
77 compatible = "marvell,pxa270-udc";
78 reg = <0x40600000 0x10000>;
79 interrupts = <11>;
80 clocks = <&clks CLK_USB>;
81 status = "disabled";
82 };
Robert Jarzmik8dcba812015-02-07 13:19:38 +010083
84 keypad: keypad@41500000 {
85 compatible = "marvell,pxa27x-keypad";
86 reg = <0x41500000 0x4c>;
87 interrupts = <4>;
88 clocks = <&clks CLK_KEYPAD>;
89 status = "disabled";
90 };
Robert Jarzmik796b7dc2015-06-20 10:17:29 +020091
92 pxa_camera: imaging@50000000 {
93 compatible = "marvell,pxa270-qci";
94 reg = <0x50000000 0x1000>;
95 interrupts = <33>;
96 dmas = <&pdma 68 0 /* Y channel */
97 &pdma 69 0 /* U channel */
98 &pdma 70 0>; /* V channel */
99 dma-names = "CI_Y", "CI_U", "CI_V";
100
101 clocks = <&clks CLK_CAMERA>;
102 clock-names = "ciclk";
103 clock-frequency = <5000000>;
104 clock-output-names = "qci_mclk";
105
106 status = "disabled";
107 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200108 };
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200109
110 clocks {
111 /*
112 * The muxing of external clocks/internal dividers for osc* clock
113 * sources has been hidden under the carpet by now.
114 */
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100119 clks: pxa2xx_clks@41300004 {
120 compatible = "marvell,pxa270-clocks";
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200121 #clock-cells = <1>;
122 status = "okay";
123 };
124 };
Robert Jarzmik8dd30752014-10-12 22:11:08 +0200125
126 timer@40a00000 {
127 compatible = "marvell,pxa-timer";
128 reg = <0x40a00000 0x20>;
129 interrupts = <26>;
130 clocks = <&clks CLK_OSTIMER>;
131 status = "okay";
132 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200133};