Daniel Mack | aff18a6 | 2012-07-25 17:56:48 +0200 | [diff] [blame] | 1 | /* The pxa3xx skeleton simply augments the 2xx version */ |
Robert Jarzmik | 85fe55c | 2014-07-30 22:51:03 +0200 | [diff] [blame] | 2 | #include "pxa2xx.dtsi" |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 3 | #include "dt-bindings/clock/pxa-clock.h" |
Daniel Mack | aff18a6 | 2012-07-25 17:56:48 +0200 | [diff] [blame] | 4 | |
| 5 | / { |
| 6 | model = "Marvell PXA27x familiy SoC"; |
| 7 | compatible = "marvell,pxa27x"; |
| 8 | |
| 9 | pxabus { |
Robert Jarzmik | 0cd4914 | 2015-06-20 10:17:26 +0200 | [diff] [blame] | 10 | pdma: dma-controller@40000000 { |
| 11 | compatible = "marvell,pdma-1.0"; |
| 12 | reg = <0x40000000 0x10000>; |
| 13 | interrupts = <25>; |
| 14 | #dma-channels = <32>; |
| 15 | #dma-cells = <2>; |
Robert Jarzmik | 72b195c | 2016-02-15 21:57:47 +0100 | [diff] [blame^] | 16 | #dma-requests = <75>; |
Robert Jarzmik | 0cd4914 | 2015-06-20 10:17:26 +0200 | [diff] [blame] | 17 | status = "okay"; |
| 18 | }; |
| 19 | |
Daniel Mack | aff18a6 | 2012-07-25 17:56:48 +0200 | [diff] [blame] | 20 | pxairq: interrupt-controller@40d00000 { |
| 21 | marvell,intc-priority; |
| 22 | marvell,intc-nr-irqs = <34>; |
| 23 | }; |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 24 | |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 25 | gpio: gpio@40e00000 { |
| 26 | compatible = "intel,pxa27x-gpio"; |
| 27 | clocks = <&clks CLK_NONE>; |
| 28 | }; |
| 29 | |
Robert Jarzmik | 0ec1939 | 2015-06-20 10:17:31 +0200 | [diff] [blame] | 30 | pxa27x_ohci: usb@4c000000 { |
| 31 | compatible = "marvell,pxa-ohci"; |
| 32 | reg = <0x4c000000 0x10000>; |
| 33 | interrupts = <3>; |
| 34 | clocks = <&clks CLK_USBHOST>; |
| 35 | status = "disabled"; |
| 36 | }; |
| 37 | |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 38 | pwm0: pwm@40b00000 { |
| 39 | compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; |
| 40 | reg = <0x40b00000 0x10>; |
| 41 | #pwm-cells = <1>; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 42 | clocks = <&clks CLK_PWM0>; |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | pwm1: pwm@40b00010 { |
| 46 | compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; |
| 47 | reg = <0x40b00010 0x10>; |
| 48 | #pwm-cells = <1>; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 49 | clocks = <&clks CLK_PWM1>; |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | pwm2: pwm@40c00000 { |
| 53 | compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; |
| 54 | reg = <0x40c00000 0x10>; |
| 55 | #pwm-cells = <1>; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 56 | clocks = <&clks CLK_PWM0>; |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | pwm3: pwm@40c00010 { |
| 60 | compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; |
| 61 | reg = <0x40c00010 0x10>; |
| 62 | #pwm-cells = <1>; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 63 | clocks = <&clks CLK_PWM1>; |
Mike Dunn | e7b4a8d | 2013-09-21 12:19:34 -0700 | [diff] [blame] | 64 | }; |
Robert Jarzmik | f374d1e | 2015-02-07 13:26:09 +0100 | [diff] [blame] | 65 | |
| 66 | pwri2c: i2c@40f000180 { |
| 67 | compatible = "mrvl,pxa-i2c"; |
| 68 | reg = <0x40f00180 0x24>; |
| 69 | interrupts = <6>; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 70 | clocks = <&clks CLK_PWRI2C>; |
Robert Jarzmik | fb18539 | 2015-06-20 10:17:30 +0200 | [diff] [blame] | 71 | #address-cells = <0x1>; |
| 72 | #size-cells = <0>; |
Robert Jarzmik | f374d1e | 2015-02-07 13:26:09 +0100 | [diff] [blame] | 73 | status = "disabled"; |
| 74 | }; |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 75 | |
Robert Jarzmik | 361818c | 2015-02-07 13:27:55 +0100 | [diff] [blame] | 76 | pxa27x_udc: udc@40600000 { |
| 77 | compatible = "marvell,pxa270-udc"; |
| 78 | reg = <0x40600000 0x10000>; |
| 79 | interrupts = <11>; |
| 80 | clocks = <&clks CLK_USB>; |
| 81 | status = "disabled"; |
| 82 | }; |
Robert Jarzmik | 8dcba81 | 2015-02-07 13:19:38 +0100 | [diff] [blame] | 83 | |
| 84 | keypad: keypad@41500000 { |
| 85 | compatible = "marvell,pxa27x-keypad"; |
| 86 | reg = <0x41500000 0x4c>; |
| 87 | interrupts = <4>; |
| 88 | clocks = <&clks CLK_KEYPAD>; |
| 89 | status = "disabled"; |
| 90 | }; |
Robert Jarzmik | 796b7dc | 2015-06-20 10:17:29 +0200 | [diff] [blame] | 91 | |
| 92 | pxa_camera: imaging@50000000 { |
| 93 | compatible = "marvell,pxa270-qci"; |
| 94 | reg = <0x50000000 0x1000>; |
| 95 | interrupts = <33>; |
| 96 | dmas = <&pdma 68 0 /* Y channel */ |
| 97 | &pdma 69 0 /* U channel */ |
| 98 | &pdma 70 0>; /* V channel */ |
| 99 | dma-names = "CI_Y", "CI_U", "CI_V"; |
| 100 | |
| 101 | clocks = <&clks CLK_CAMERA>; |
| 102 | clock-names = "ciclk"; |
| 103 | clock-frequency = <5000000>; |
| 104 | clock-output-names = "qci_mclk"; |
| 105 | |
| 106 | status = "disabled"; |
| 107 | }; |
Daniel Mack | aff18a6 | 2012-07-25 17:56:48 +0200 | [diff] [blame] | 108 | }; |
Robert Jarzmik | 85fe55c | 2014-07-30 22:51:03 +0200 | [diff] [blame] | 109 | |
| 110 | clocks { |
| 111 | /* |
| 112 | * The muxing of external clocks/internal dividers for osc* clock |
| 113 | * sources has been hidden under the carpet by now. |
| 114 | */ |
| 115 | #address-cells = <1>; |
| 116 | #size-cells = <1>; |
| 117 | ranges; |
| 118 | |
Robert Jarzmik | d96672e | 2015-02-07 13:13:24 +0100 | [diff] [blame] | 119 | clks: pxa2xx_clks@41300004 { |
| 120 | compatible = "marvell,pxa270-clocks"; |
Robert Jarzmik | 85fe55c | 2014-07-30 22:51:03 +0200 | [diff] [blame] | 121 | #clock-cells = <1>; |
| 122 | status = "okay"; |
| 123 | }; |
| 124 | }; |
Robert Jarzmik | 8dd3075 | 2014-10-12 22:11:08 +0200 | [diff] [blame] | 125 | |
| 126 | timer@40a00000 { |
| 127 | compatible = "marvell,pxa-timer"; |
| 128 | reg = <0x40a00000 0x20>; |
| 129 | interrupts = <26>; |
| 130 | clocks = <&clks CLK_OSTIMER>; |
| 131 | status = "okay"; |
| 132 | }; |
Daniel Mack | aff18a6 | 2012-07-25 17:56:48 +0200 | [diff] [blame] | 133 | }; |