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Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010033#include <linux/circ_buf.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drmP.h>
35#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010037#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Daniel Vetterfca52a52014-09-30 10:56:45 +020040/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +030048static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50};
51
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +030052static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54};
55
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +030056static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58};
59
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020060static const u32 hpd_ibx[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050061 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66};
67
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020068static const u32 hpd_cpt[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050069 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010070 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050071 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74};
75
Xiong Zhang26951ca2015-08-17 15:55:50 +080076static const u32 hpd_spt[HPD_NUM_PINS] = {
Ville Syrjälä74c0b392015-08-27 23:56:07 +030077 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
Xiong Zhang26951ca2015-08-17 15:55:50 +080078 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82};
83
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020084static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050085 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91};
92
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020093static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050094 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100};
101
Ville Syrjälä4bca26d2015-05-11 20:49:10 +0300102static const u32 hpd_status_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -0500103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109};
110
Shashank Sharmae0a20ad2015-03-27 14:54:14 +0200111/* BXT hpd list */
112static const u32 hpd_bxt[HPD_NUM_PINS] = {
Sonika Jindal7f3561b2015-08-10 10:35:35 +0530113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
Shashank Sharmae0a20ad2015-03-27 14:54:14 +0200114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116};
117
Paulo Zanoni5c502442014-04-01 15:37:11 -0300118/* IIR can theoretically queue up two events. Be paranoid. */
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300119#define GEN8_IRQ_RESET_NDX(type, which) do { \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127} while (0)
128
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300129#define GEN5_IRQ_RESET(type) do { \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300130 I915_WRITE(type##IMR, 0xffffffff); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300131 POSTING_READ(type##IMR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300132 I915_WRITE(type##IER, 0); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300137} while (0)
138
Paulo Zanoni337ba012014-04-01 15:37:16 -0300139/*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200142static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143 i915_reg_t reg)
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300144{
145 u32 val = I915_READ(reg);
146
147 if (val == 0)
148 return;
149
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200151 i915_mmio_reg_offset(reg), val);
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300152 I915_WRITE(reg, 0xffffffff);
153 POSTING_READ(reg);
154 I915_WRITE(reg, 0xffffffff);
155 POSTING_READ(reg);
156}
Paulo Zanoni337ba012014-04-01 15:37:16 -0300157
Paulo Zanoni35079892014-04-01 15:37:15 -0300158#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300163} while (0)
164
165#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300167 I915_WRITE(type##IER, (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300170} while (0)
171
Imre Deakc9a9a262014-11-05 20:48:37 +0200172static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
Sagar Arun Kamble26705e22016-10-12 21:54:31 +0530173static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
Imre Deakc9a9a262014-11-05 20:48:37 +0200174
Egbert Eich0706f172015-09-23 16:15:27 +0200175/* For display hotplug interrupt */
176static inline void
177i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
178 uint32_t mask,
179 uint32_t bits)
180{
181 uint32_t val;
182
Chris Wilson67520412017-03-02 13:28:01 +0000183 lockdep_assert_held(&dev_priv->irq_lock);
Egbert Eich0706f172015-09-23 16:15:27 +0200184 WARN_ON(bits & ~mask);
185
186 val = I915_READ(PORT_HOTPLUG_EN);
187 val &= ~mask;
188 val |= bits;
189 I915_WRITE(PORT_HOTPLUG_EN, val);
190}
191
192/**
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
203 */
204void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
205 uint32_t mask,
206 uint32_t bits)
207{
208 spin_lock_irq(&dev_priv->irq_lock);
209 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
210 spin_unlock_irq(&dev_priv->irq_lock);
211}
212
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300213/**
214 * ilk_update_display_irq - update DEIMR
215 * @dev_priv: driver private
216 * @interrupt_mask: mask of interrupt bits to update
217 * @enabled_irq_mask: mask of interrupt bits to enable
218 */
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +0200219void ilk_update_display_irq(struct drm_i915_private *dev_priv,
220 uint32_t interrupt_mask,
221 uint32_t enabled_irq_mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800222{
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300223 uint32_t new_val;
224
Chris Wilson67520412017-03-02 13:28:01 +0000225 lockdep_assert_held(&dev_priv->irq_lock);
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200226
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300227 WARN_ON(enabled_irq_mask & ~interrupt_mask);
228
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700229 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300230 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300231
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300232 new_val = dev_priv->irq_mask;
233 new_val &= ~interrupt_mask;
234 new_val |= (~enabled_irq_mask & interrupt_mask);
235
236 if (new_val != dev_priv->irq_mask) {
237 dev_priv->irq_mask = new_val;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000238 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000239 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800240 }
241}
242
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300243/**
244 * ilk_update_gt_irq - update GTIMR
245 * @dev_priv: driver private
246 * @interrupt_mask: mask of interrupt bits to update
247 * @enabled_irq_mask: mask of interrupt bits to enable
248 */
249static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
252{
Chris Wilson67520412017-03-02 13:28:01 +0000253 lockdep_assert_held(&dev_priv->irq_lock);
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300254
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100255 WARN_ON(enabled_irq_mask & ~interrupt_mask);
256
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300258 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300259
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300260 dev_priv->gt_irq_mask &= ~interrupt_mask;
261 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
262 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300263}
264
Daniel Vetter480c8032014-07-16 09:49:40 +0200265void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300266{
267 ilk_update_gt_irq(dev_priv, mask, mask);
Chris Wilson31bb59c2016-07-01 17:23:27 +0100268 POSTING_READ_FW(GTIMR);
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300269}
270
Daniel Vetter480c8032014-07-16 09:49:40 +0200271void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300272{
273 ilk_update_gt_irq(dev_priv, mask, 0);
274}
275
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200276static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
Imre Deakb900b942014-11-05 20:48:48 +0200277{
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -0700278 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
Imre Deakb900b942014-11-05 20:48:48 +0200279}
280
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200281static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
Imre Deaka72fbc32014-11-05 20:48:31 +0200282{
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -0700283 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
Imre Deaka72fbc32014-11-05 20:48:31 +0200284}
285
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200286static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
Imre Deakb900b942014-11-05 20:48:48 +0200287{
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -0700288 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
Imre Deakb900b942014-11-05 20:48:48 +0200289}
290
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300291/**
Ville Syrjälä81fd8742015-11-25 16:21:30 +0200292 * snb_update_pm_irq - update GEN6_PMIMR
293 * @dev_priv: driver private
294 * @interrupt_mask: mask of interrupt bits to update
295 * @enabled_irq_mask: mask of interrupt bits to enable
296 */
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300297static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
298 uint32_t interrupt_mask,
299 uint32_t enabled_irq_mask)
300{
Paulo Zanoni605cd252013-08-06 18:57:15 -0300301 uint32_t new_val;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300302
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100303 WARN_ON(enabled_irq_mask & ~interrupt_mask);
304
Chris Wilson67520412017-03-02 13:28:01 +0000305 lockdep_assert_held(&dev_priv->irq_lock);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300306
Akash Goelf4e9af42016-10-12 21:54:30 +0530307 new_val = dev_priv->pm_imr;
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300308 new_val &= ~interrupt_mask;
309 new_val |= (~enabled_irq_mask & interrupt_mask);
310
Akash Goelf4e9af42016-10-12 21:54:30 +0530311 if (new_val != dev_priv->pm_imr) {
312 dev_priv->pm_imr = new_val;
313 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
Imre Deaka72fbc32014-11-05 20:48:31 +0200314 POSTING_READ(gen6_pm_imr(dev_priv));
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300315 }
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300316}
317
Akash Goelf4e9af42016-10-12 21:54:30 +0530318void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300319{
Imre Deak9939fba2014-11-20 23:01:47 +0200320 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
321 return;
322
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300323 snb_update_pm_irq(dev_priv, mask, mask);
324}
325
Akash Goelf4e9af42016-10-12 21:54:30 +0530326static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
Imre Deak9939fba2014-11-20 23:01:47 +0200327{
328 snb_update_pm_irq(dev_priv, mask, 0);
329}
330
Akash Goelf4e9af42016-10-12 21:54:30 +0530331void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300332{
Imre Deak9939fba2014-11-20 23:01:47 +0200333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334 return;
335
Akash Goelf4e9af42016-10-12 21:54:30 +0530336 __gen6_mask_pm_irq(dev_priv, mask);
337}
338
339void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
340{
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
342
Chris Wilson67520412017-03-02 13:28:01 +0000343 lockdep_assert_held(&dev_priv->irq_lock);
Akash Goelf4e9af42016-10-12 21:54:30 +0530344
345 I915_WRITE(reg, reset_mask);
346 I915_WRITE(reg, reset_mask);
347 POSTING_READ(reg);
348}
349
350void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
351{
Chris Wilson67520412017-03-02 13:28:01 +0000352 lockdep_assert_held(&dev_priv->irq_lock);
Akash Goelf4e9af42016-10-12 21:54:30 +0530353
354 dev_priv->pm_ier |= enable_mask;
355 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
356 gen6_unmask_pm_irq(dev_priv, enable_mask);
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
358}
359
360void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
361{
Chris Wilson67520412017-03-02 13:28:01 +0000362 lockdep_assert_held(&dev_priv->irq_lock);
Akash Goelf4e9af42016-10-12 21:54:30 +0530363
364 dev_priv->pm_ier &= ~disable_mask;
365 __gen6_mask_pm_irq(dev_priv, disable_mask);
366 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
367 /* though a barrier is missing here, but don't really need a one */
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300368}
369
Chris Wilsondc979972016-05-10 14:10:04 +0100370void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
Imre Deak3cc134e2014-11-19 15:30:03 +0200371{
Imre Deak3cc134e2014-11-19 15:30:03 +0200372 spin_lock_irq(&dev_priv->irq_lock);
Akash Goelf4e9af42016-10-12 21:54:30 +0530373 gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
Imre Deak096fad92015-03-23 19:11:35 +0200374 dev_priv->rps.pm_iir = 0;
Imre Deak3cc134e2014-11-19 15:30:03 +0200375 spin_unlock_irq(&dev_priv->irq_lock);
376}
377
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100378void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
Imre Deakb900b942014-11-05 20:48:48 +0200379{
Chris Wilsonf2a91d12016-09-21 14:51:06 +0100380 if (READ_ONCE(dev_priv->rps.interrupts_enabled))
381 return;
382
Imre Deakb900b942014-11-05 20:48:48 +0200383 spin_lock_irq(&dev_priv->irq_lock);
Chris Wilsonc33d2472016-07-04 08:08:36 +0100384 WARN_ON_ONCE(dev_priv->rps.pm_iir);
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +0200386 dev_priv->rps.interrupts_enabled = true;
Imre Deakb900b942014-11-05 20:48:48 +0200387 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deak78e68d32014-12-15 18:59:27 +0200388
Imre Deakb900b942014-11-05 20:48:48 +0200389 spin_unlock_irq(&dev_priv->irq_lock);
390}
391
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100392void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
Imre Deakb900b942014-11-05 20:48:48 +0200393{
Chris Wilsonf2a91d12016-09-21 14:51:06 +0100394 if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
395 return;
396
Imre Deakd4d70aa2014-11-19 15:30:04 +0200397 spin_lock_irq(&dev_priv->irq_lock);
398 dev_priv->rps.interrupts_enabled = false;
Imre Deak9939fba2014-11-20 23:01:47 +0200399
Dave Gordonb20e3cf2016-09-12 21:19:35 +0100400 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
Imre Deak9939fba2014-11-20 23:01:47 +0200401
Akash Goelf4e9af42016-10-12 21:54:30 +0530402 gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deak58072cc2015-03-23 19:11:34 +0200403
404 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilson91c8a322016-07-05 10:40:23 +0100405 synchronize_irq(dev_priv->drm.irq);
Chris Wilsonc33d2472016-07-04 08:08:36 +0100406
407 /* Now that we will not be generating any more work, flush any
408 * outsanding tasks. As we are called on the RPS idle path,
409 * we will reset the GPU to minimum frequencies, so the current
410 * state of the worker can be discarded.
411 */
412 cancel_work_sync(&dev_priv->rps.work);
413 gen6_reset_rps_interrupts(dev_priv);
Imre Deakb900b942014-11-05 20:48:48 +0200414}
415
Sagar Arun Kamble26705e22016-10-12 21:54:31 +0530416void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
417{
418 spin_lock_irq(&dev_priv->irq_lock);
419 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
420 spin_unlock_irq(&dev_priv->irq_lock);
421}
422
423void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
424{
425 spin_lock_irq(&dev_priv->irq_lock);
426 if (!dev_priv->guc.interrupts_enabled) {
427 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
428 dev_priv->pm_guc_events);
429 dev_priv->guc.interrupts_enabled = true;
430 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
431 }
432 spin_unlock_irq(&dev_priv->irq_lock);
433}
434
435void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
436{
437 spin_lock_irq(&dev_priv->irq_lock);
438 dev_priv->guc.interrupts_enabled = false;
439
440 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
441
442 spin_unlock_irq(&dev_priv->irq_lock);
443 synchronize_irq(dev_priv->drm.irq);
444
445 gen9_reset_guc_interrupts(dev_priv);
446}
447
Ben Widawsky09610212014-05-15 20:58:08 +0300448/**
Ville Syrjälä81fd8742015-11-25 16:21:30 +0200449 * bdw_update_port_irq - update DE port interrupt
450 * @dev_priv: driver private
451 * @interrupt_mask: mask of interrupt bits to update
452 * @enabled_irq_mask: mask of interrupt bits to enable
453 */
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +0300454static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
455 uint32_t interrupt_mask,
456 uint32_t enabled_irq_mask)
457{
458 uint32_t new_val;
459 uint32_t old_val;
460
Chris Wilson67520412017-03-02 13:28:01 +0000461 lockdep_assert_held(&dev_priv->irq_lock);
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +0300462
463 WARN_ON(enabled_irq_mask & ~interrupt_mask);
464
465 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
466 return;
467
468 old_val = I915_READ(GEN8_DE_PORT_IMR);
469
470 new_val = old_val;
471 new_val &= ~interrupt_mask;
472 new_val |= (~enabled_irq_mask & interrupt_mask);
473
474 if (new_val != old_val) {
475 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
476 POSTING_READ(GEN8_DE_PORT_IMR);
477 }
478}
479
480/**
Ville Syrjälä013d3752015-11-23 18:06:17 +0200481 * bdw_update_pipe_irq - update DE pipe interrupt
482 * @dev_priv: driver private
483 * @pipe: pipe whose interrupt to update
484 * @interrupt_mask: mask of interrupt bits to update
485 * @enabled_irq_mask: mask of interrupt bits to enable
486 */
487void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
488 enum pipe pipe,
489 uint32_t interrupt_mask,
490 uint32_t enabled_irq_mask)
491{
492 uint32_t new_val;
493
Chris Wilson67520412017-03-02 13:28:01 +0000494 lockdep_assert_held(&dev_priv->irq_lock);
Ville Syrjälä013d3752015-11-23 18:06:17 +0200495
496 WARN_ON(enabled_irq_mask & ~interrupt_mask);
497
498 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
499 return;
500
501 new_val = dev_priv->de_irq_mask[pipe];
502 new_val &= ~interrupt_mask;
503 new_val |= (~enabled_irq_mask & interrupt_mask);
504
505 if (new_val != dev_priv->de_irq_mask[pipe]) {
506 dev_priv->de_irq_mask[pipe] = new_val;
507 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
508 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
509 }
510}
511
512/**
Daniel Vetterfee884e2013-07-04 23:35:21 +0200513 * ibx_display_interrupt_update - update SDEIMR
514 * @dev_priv: driver private
515 * @interrupt_mask: mask of interrupt bits to update
516 * @enabled_irq_mask: mask of interrupt bits to enable
517 */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200518void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
519 uint32_t interrupt_mask,
520 uint32_t enabled_irq_mask)
Daniel Vetterfee884e2013-07-04 23:35:21 +0200521{
522 uint32_t sdeimr = I915_READ(SDEIMR);
523 sdeimr &= ~interrupt_mask;
524 sdeimr |= (~enabled_irq_mask & interrupt_mask);
525
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100526 WARN_ON(enabled_irq_mask & ~interrupt_mask);
527
Chris Wilson67520412017-03-02 13:28:01 +0000528 lockdep_assert_held(&dev_priv->irq_lock);
Daniel Vetterfee884e2013-07-04 23:35:21 +0200529
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700530 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300531 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300532
Daniel Vetterfee884e2013-07-04 23:35:21 +0200533 I915_WRITE(SDEIMR, sdeimr);
534 POSTING_READ(SDEIMR);
535}
Paulo Zanoni86642812013-04-12 17:57:57 -0300536
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100537static void
Imre Deak755e9012014-02-10 18:42:47 +0200538__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
539 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800540{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200541 i915_reg_t reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200542 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800543
Chris Wilson67520412017-03-02 13:28:01 +0000544 lockdep_assert_held(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200545 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200546
Ville Syrjälä04feced2014-04-03 13:28:33 +0300547 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
548 status_mask & ~PIPESTAT_INT_STATUS_MASK,
549 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
550 pipe_name(pipe), enable_mask, status_mask))
Imre Deak755e9012014-02-10 18:42:47 +0200551 return;
552
553 if ((pipestat & enable_mask) == enable_mask)
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200554 return;
555
Imre Deak91d181d2014-02-10 18:42:49 +0200556 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
557
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200558 /* Enable the interrupt, clear any pending status */
Imre Deak755e9012014-02-10 18:42:47 +0200559 pipestat |= enable_mask | status_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200560 I915_WRITE(reg, pipestat);
561 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800562}
563
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100564static void
Imre Deak755e9012014-02-10 18:42:47 +0200565__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
566 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800567{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200568 i915_reg_t reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200569 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800570
Chris Wilson67520412017-03-02 13:28:01 +0000571 lockdep_assert_held(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200572 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200573
Ville Syrjälä04feced2014-04-03 13:28:33 +0300574 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
575 status_mask & ~PIPESTAT_INT_STATUS_MASK,
576 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
577 pipe_name(pipe), enable_mask, status_mask))
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200578 return;
579
Imre Deak755e9012014-02-10 18:42:47 +0200580 if ((pipestat & enable_mask) == 0)
581 return;
582
Imre Deak91d181d2014-02-10 18:42:49 +0200583 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
584
Imre Deak755e9012014-02-10 18:42:47 +0200585 pipestat &= ~enable_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200586 I915_WRITE(reg, pipestat);
587 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800588}
589
Imre Deak10c59c52014-02-10 18:42:48 +0200590static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
591{
592 u32 enable_mask = status_mask << 16;
593
594 /*
Ville Syrjälä724a6902014-04-09 13:28:48 +0300595 * On pipe A we don't support the PSR interrupt yet,
596 * on pipe B and C the same bit MBZ.
Imre Deak10c59c52014-02-10 18:42:48 +0200597 */
598 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
599 return 0;
Ville Syrjälä724a6902014-04-09 13:28:48 +0300600 /*
601 * On pipe B and C we don't support the PSR interrupt yet, on pipe
602 * A the same bit is for perf counters which we don't use either.
603 */
604 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
605 return 0;
Imre Deak10c59c52014-02-10 18:42:48 +0200606
607 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
608 SPRITE0_FLIP_DONE_INT_EN_VLV |
609 SPRITE1_FLIP_DONE_INT_EN_VLV);
610 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
611 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
612 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
613 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
614
615 return enable_mask;
616}
617
Imre Deak755e9012014-02-10 18:42:47 +0200618void
619i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
620 u32 status_mask)
621{
622 u32 enable_mask;
623
Wayne Boyer666a4532015-12-09 12:29:35 -0800624 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Chris Wilson91c8a322016-07-05 10:40:23 +0100625 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
Imre Deak10c59c52014-02-10 18:42:48 +0200626 status_mask);
627 else
628 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200629 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
630}
631
632void
633i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
634 u32 status_mask)
635{
636 u32 enable_mask;
637
Wayne Boyer666a4532015-12-09 12:29:35 -0800638 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Chris Wilson91c8a322016-07-05 10:40:23 +0100639 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
Imre Deak10c59c52014-02-10 18:42:48 +0200640 status_mask);
641 else
642 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200643 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
644}
645
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000646/**
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300647 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
Tvrtko Ursulin14bb2c12016-06-03 14:02:17 +0100648 * @dev_priv: i915 device private
Zhao Yakui01c66882009-10-28 05:10:00 +0000649 */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100650static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
Zhao Yakui01c66882009-10-28 05:10:00 +0000651{
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100652 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300653 return;
654
Daniel Vetter13321782014-09-15 14:55:29 +0200655 spin_lock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000656
Imre Deak755e9012014-02-10 18:42:47 +0200657 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100658 if (INTEL_GEN(dev_priv) >= 4)
Daniel Vetter3b6c42e2013-10-21 18:04:35 +0200659 i915_enable_pipestat(dev_priv, PIPE_A,
Imre Deak755e9012014-02-10 18:42:47 +0200660 PIPE_LEGACY_BLC_EVENT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000661
Daniel Vetter13321782014-09-15 14:55:29 +0200662 spin_unlock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000663}
664
Ville Syrjäläf75f3742014-05-15 20:20:36 +0300665/*
666 * This timing diagram depicts the video signal in and
667 * around the vertical blanking period.
668 *
669 * Assumptions about the fictitious mode used in this example:
670 * vblank_start >= 3
671 * vsync_start = vblank_start + 1
672 * vsync_end = vblank_start + 2
673 * vtotal = vblank_start + 3
674 *
675 * start of vblank:
676 * latch double buffered registers
677 * increment frame counter (ctg+)
678 * generate start of vblank interrupt (gen4+)
679 * |
680 * | frame start:
681 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
682 * | may be shifted forward 1-3 extra lines via PIPECONF
683 * | |
684 * | | start of vsync:
685 * | | generate vsync interrupt
686 * | | |
687 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
688 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
689 * ----va---> <-----------------vb--------------------> <--------va-------------
690 * | | <----vs-----> |
691 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
692 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
693 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
694 * | | |
695 * last visible pixel first visible pixel
696 * | increment frame counter (gen3/4)
697 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
698 *
699 * x = horizontal active
700 * _ = horizontal blanking
701 * hs = horizontal sync
702 * va = vertical active
703 * vb = vertical blanking
704 * vs = vertical sync
705 * vbs = vblank_start (number)
706 *
707 * Summary:
708 * - most events happen at the start of horizontal sync
709 * - frame start happens at the start of horizontal blank, 1-4 lines
710 * (depending on PIPECONF settings) after the start of vblank
711 * - gen3/4 pixel and frame counter are synchronized with the start
712 * of horizontal active on the first line of vertical active
713 */
714
Keith Packard42f52ef2008-10-18 19:39:29 -0700715/* Called from drm generic code, passed a 'crtc', which
716 * we use as a pipe index
717 */
Thierry Reding88e72712015-09-24 18:35:31 +0200718static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700719{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100720 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200721 i915_reg_t high_frame, low_frame;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300722 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
Daniel Vetter5caa0fe2017-05-09 16:03:29 +0200723 const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
Ville Syrjälä694e4092017-03-09 17:44:30 +0200724 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700725
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +0100726 htotal = mode->crtc_htotal;
727 hsync_start = mode->crtc_hsync_start;
728 vbl_start = mode->crtc_vblank_start;
729 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
730 vbl_start = DIV_ROUND_UP(vbl_start, 2);
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300731
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300732 /* Convert to pixel count */
733 vbl_start *= htotal;
734
735 /* Start of vblank event occurs at start of hsync */
736 vbl_start -= htotal - hsync_start;
737
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800738 high_frame = PIPEFRAME(pipe);
739 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100740
Ville Syrjälä694e4092017-03-09 17:44:30 +0200741 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
742
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700743 /*
744 * High & low register fields aren't synchronized, so make sure
745 * we get a low value that's stable across two reads of the high
746 * register.
747 */
748 do {
Ville Syrjälä694e4092017-03-09 17:44:30 +0200749 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
750 low = I915_READ_FW(low_frame);
751 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700752 } while (high1 != high2);
753
Ville Syrjälä694e4092017-03-09 17:44:30 +0200754 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
755
Chris Wilson5eddb702010-09-11 13:48:45 +0100756 high1 >>= PIPE_FRAME_HIGH_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300757 pixel = low & PIPE_PIXEL_MASK;
Chris Wilson5eddb702010-09-11 13:48:45 +0100758 low >>= PIPE_FRAME_LOW_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300759
760 /*
761 * The frame counter increments at beginning of active.
762 * Cook up a vblank counter by also checking the pixel
763 * counter against vblank start.
764 */
Ville Syrjäläedc08d02013-11-06 13:56:27 -0200765 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700766}
767
Dave Airlie974e59b2015-10-30 09:45:33 +1000768static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800769{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100770 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800771
Ville Syrjälä649636e2015-09-22 19:50:01 +0300772 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800773}
774
Ville Syrjälä75aa3f62015-10-22 15:34:56 +0300775/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
Ville Syrjäläa225f072014-04-29 13:35:45 +0300776static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
777{
778 struct drm_device *dev = crtc->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100779 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter5caa0fe2017-05-09 16:03:29 +0200780 const struct drm_display_mode *mode;
781 struct drm_vblank_crtc *vblank;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300782 enum pipe pipe = crtc->pipe;
Ville Syrjälä80715b22014-05-15 20:23:23 +0300783 int position, vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300784
Ville Syrjälä72259532017-03-02 19:15:05 +0200785 if (!crtc->active)
786 return -1;
787
Daniel Vetter5caa0fe2017-05-09 16:03:29 +0200788 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
789 mode = &vblank->hwmode;
790
Ville Syrjälä80715b22014-05-15 20:23:23 +0300791 vtotal = mode->crtc_vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300792 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
793 vtotal /= 2;
794
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100795 if (IS_GEN2(dev_priv))
Ville Syrjälä75aa3f62015-10-22 15:34:56 +0300796 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300797 else
Ville Syrjälä75aa3f62015-10-22 15:34:56 +0300798 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300799
800 /*
Jesse Barnes41b578f2015-09-22 12:15:54 -0700801 * On HSW, the DSL reg (0x70000) appears to return 0 if we
802 * read it just before the start of vblank. So try it again
803 * so we don't accidentally end up spanning a vblank frame
804 * increment, causing the pipe_update_end() code to squak at us.
805 *
806 * The nature of this problem means we can't simply check the ISR
807 * bit and return the vblank start value; nor can we use the scanline
808 * debug register in the transcoder as it appears to have the same
809 * problem. We may need to extend this to include other platforms,
810 * but so far testing only shows the problem on HSW.
811 */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100812 if (HAS_DDI(dev_priv) && !position) {
Jesse Barnes41b578f2015-09-22 12:15:54 -0700813 int i, temp;
814
815 for (i = 0; i < 100; i++) {
816 udelay(1);
Ville Syrjälä707bdd32017-03-09 17:44:31 +0200817 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
Jesse Barnes41b578f2015-09-22 12:15:54 -0700818 if (temp != position) {
819 position = temp;
820 break;
821 }
822 }
823 }
824
825 /*
Ville Syrjälä80715b22014-05-15 20:23:23 +0300826 * See update_scanline_offset() for the details on the
827 * scanline_offset adjustment.
Ville Syrjäläa225f072014-04-29 13:35:45 +0300828 */
Ville Syrjälä80715b22014-05-15 20:23:23 +0300829 return (position + crtc->scanline_offset) % vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300830}
831
Daniel Vetter1bf6ad62017-05-09 16:03:28 +0200832static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
833 bool in_vblank_irq, int *vpos, int *hpos,
834 ktime_t *stime, ktime_t *etime,
835 const struct drm_display_mode *mode)
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100836{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100837 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä98187832016-10-31 22:37:10 +0200838 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
839 pipe);
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300840 int position;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300841 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100842 bool in_vbl = true;
Mario Kleinerad3543e2013-10-30 05:13:08 +0100843 unsigned long irqflags;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100844
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200845 if (WARN_ON(!mode->crtc_clock)) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100846 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800847 "pipe %c\n", pipe_name(pipe));
Daniel Vetter1bf6ad62017-05-09 16:03:28 +0200848 return false;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100849 }
850
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300851 htotal = mode->crtc_htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300852 hsync_start = mode->crtc_hsync_start;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300853 vtotal = mode->crtc_vtotal;
854 vbl_start = mode->crtc_vblank_start;
855 vbl_end = mode->crtc_vblank_end;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100856
Ville Syrjäläd31faf62013-10-28 16:31:41 +0200857 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
858 vbl_start = DIV_ROUND_UP(vbl_start, 2);
859 vbl_end /= 2;
860 vtotal /= 2;
861 }
862
Mario Kleinerad3543e2013-10-30 05:13:08 +0100863 /*
864 * Lock uncore.lock, as we will do multiple timing critical raw
865 * register reads, potentially with preemption disabled, so the
866 * following code must not block on uncore.lock.
867 */
868 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300869
Mario Kleinerad3543e2013-10-30 05:13:08 +0100870 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
871
872 /* Get optional system timestamp before query. */
873 if (stime)
874 *stime = ktime_get();
875
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100876 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100877 /* No obvious pixelcount register. Only query vertical
878 * scanout position from Display scan line register.
879 */
Ville Syrjäläa225f072014-04-29 13:35:45 +0300880 position = __intel_get_crtc_scanline(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100881 } else {
882 /* Have access to pixelcount since start of frame.
883 * We can split this into vertical and horizontal
884 * scanout position.
885 */
Ville Syrjälä75aa3f62015-10-22 15:34:56 +0300886 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100887
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300888 /* convert to pixel counts */
889 vbl_start *= htotal;
890 vbl_end *= htotal;
891 vtotal *= htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300892
893 /*
Ville Syrjälä7e78f1cb2014-04-29 13:35:49 +0300894 * In interlaced modes, the pixel counter counts all pixels,
895 * so one field will have htotal more pixels. In order to avoid
896 * the reported position from jumping backwards when the pixel
897 * counter is beyond the length of the shorter field, just
898 * clamp the position the length of the shorter field. This
899 * matches how the scanline counter based position works since
900 * the scanline counter doesn't count the two half lines.
901 */
902 if (position >= vtotal)
903 position = vtotal - 1;
904
905 /*
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300906 * Start of vblank interrupt is triggered at start of hsync,
907 * just prior to the first active line of vblank. However we
908 * consider lines to start at the leading edge of horizontal
909 * active. So, should we get here before we've crossed into
910 * the horizontal active of the first line in vblank, we would
911 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
912 * always add htotal-hsync_start to the current pixel position.
913 */
914 position = (position + htotal - hsync_start) % vtotal;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300915 }
916
Mario Kleinerad3543e2013-10-30 05:13:08 +0100917 /* Get optional system timestamp after query. */
918 if (etime)
919 *etime = ktime_get();
920
921 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
922
923 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300925 in_vbl = position >= vbl_start && position < vbl_end;
926
927 /*
928 * While in vblank, position will be negative
929 * counting up towards 0 at vbl_end. And outside
930 * vblank, position will be positive counting
931 * up since vbl_end.
932 */
933 if (position >= vbl_start)
934 position -= vbl_end;
935 else
936 position += vtotal - vbl_end;
937
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100938 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300939 *vpos = position;
940 *hpos = 0;
941 } else {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100942 *vpos = position / htotal;
943 *hpos = position - (*vpos * htotal);
944 }
945
Daniel Vetter1bf6ad62017-05-09 16:03:28 +0200946 return true;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100947}
948
Ville Syrjäläa225f072014-04-29 13:35:45 +0300949int intel_get_crtc_scanline(struct intel_crtc *crtc)
950{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjäläa225f072014-04-29 13:35:45 +0300952 unsigned long irqflags;
953 int position;
954
955 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
956 position = __intel_get_crtc_scanline(crtc);
957 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
958
959 return position;
960}
961
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100962static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800963{
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000964 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200965 u8 new_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200966
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200967 spin_lock(&mchdev_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800968
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200969 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
970
Daniel Vetter20e4d402012-08-08 23:35:39 +0200971 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200972
Jesse Barnes7648fa92010-05-20 14:28:11 -0700973 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000974 busy_up = I915_READ(RCPREVBSYTUPAVG);
975 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800976 max_avg = I915_READ(RCBMAXAVG);
977 min_avg = I915_READ(RCBMINAVG);
978
979 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000980 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200981 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
982 new_delay = dev_priv->ips.cur_delay - 1;
983 if (new_delay < dev_priv->ips.max_delay)
984 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000985 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200986 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
987 new_delay = dev_priv->ips.cur_delay + 1;
988 if (new_delay > dev_priv->ips.min_delay)
989 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800990 }
991
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100992 if (ironlake_set_drps(dev_priv, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200993 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800994
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200995 spin_unlock(&mchdev_lock);
Daniel Vetter92703882012-08-09 16:46:01 +0200996
Jesse Barnesf97108d2010-01-29 11:27:07 -0800997 return;
998}
999
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001000static void notify_ring(struct intel_engine_cs *engine)
Chris Wilson549f7362010-10-19 11:19:32 +01001001{
Chris Wilson56299fb2017-02-27 20:58:48 +00001002 struct drm_i915_gem_request *rq = NULL;
1003 struct intel_wait *wait;
Tvrtko Ursulindffabc82017-02-21 09:13:48 +00001004
Chris Wilson2246bea2017-02-17 15:13:00 +00001005 atomic_inc(&engine->irq_count);
Chris Wilson538b2572017-01-24 15:18:05 +00001006 set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
Chris Wilson56299fb2017-02-27 20:58:48 +00001007
Chris Wilson61d3dc72017-03-03 19:08:24 +00001008 spin_lock(&engine->breadcrumbs.irq_lock);
1009 wait = engine->breadcrumbs.irq_wait;
Chris Wilson56299fb2017-02-27 20:58:48 +00001010 if (wait) {
1011 /* We use a callback from the dma-fence to submit
1012 * requests after waiting on our own requests. To
1013 * ensure minimum delay in queuing the next request to
1014 * hardware, signal the fence now rather than wait for
1015 * the signaler to be woken up. We still wake up the
1016 * waiter in order to handle the irq-seqno coherency
1017 * issues (we may receive the interrupt before the
1018 * seqno is written, see __i915_request_irq_complete())
1019 * and to handle coalescing of multiple seqno updates
1020 * and many waiters.
1021 */
1022 if (i915_seqno_passed(intel_engine_get_seqno(engine),
Chris Wilsondb939912017-03-15 21:07:26 +00001023 wait->seqno) &&
1024 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1025 &wait->request->fence.flags))
Chris Wilson24754d72017-03-03 14:45:57 +00001026 rq = i915_gem_request_get(wait->request);
Chris Wilson56299fb2017-02-27 20:58:48 +00001027
1028 wake_up_process(wait->tsk);
Chris Wilson67b807a82017-02-27 20:58:50 +00001029 } else {
1030 __intel_engine_disarm_breadcrumbs(engine);
Chris Wilson56299fb2017-02-27 20:58:48 +00001031 }
Chris Wilson61d3dc72017-03-03 19:08:24 +00001032 spin_unlock(&engine->breadcrumbs.irq_lock);
Chris Wilson56299fb2017-02-27 20:58:48 +00001033
Chris Wilson24754d72017-03-03 14:45:57 +00001034 if (rq) {
Chris Wilson56299fb2017-02-27 20:58:48 +00001035 dma_fence_signal(&rq->fence);
Chris Wilson24754d72017-03-03 14:45:57 +00001036 i915_gem_request_put(rq);
1037 }
Chris Wilson56299fb2017-02-27 20:58:48 +00001038
1039 trace_intel_engine_notify(engine, wait);
Chris Wilson549f7362010-10-19 11:19:32 +01001040}
1041
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001042static void vlv_c0_read(struct drm_i915_private *dev_priv,
1043 struct intel_rps_ei *ei)
Deepak S31685c22014-07-03 17:33:01 -04001044{
Mika Kuoppala679cb6c2017-03-15 17:43:03 +02001045 ei->ktime = ktime_get_raw();
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001046 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1047 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
Deepak S31685c22014-07-03 17:33:01 -04001048}
1049
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001050void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1051{
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001052 memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001053}
1054
1055static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1056{
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001057 const struct intel_rps_ei *prev = &dev_priv->rps.ei;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001058 struct intel_rps_ei now;
1059 u32 events = 0;
1060
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001061 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001062 return 0;
1063
1064 vlv_c0_read(dev_priv, &now);
Deepak S31685c22014-07-03 17:33:01 -04001065
Mika Kuoppala679cb6c2017-03-15 17:43:03 +02001066 if (prev->ktime) {
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001067 u64 time, c0;
Chris Wilson569884e2017-03-09 21:12:31 +00001068 u32 render, media;
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001069
Mika Kuoppala679cb6c2017-03-15 17:43:03 +02001070 time = ktime_us_delta(now.ktime, prev->ktime);
Chris Wilson8f68d592017-03-13 17:06:17 +00001071
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001072 time *= dev_priv->czclk_freq;
1073
1074 /* Workload can be split between render + media,
1075 * e.g. SwapBuffers being blitted in X after being rendered in
1076 * mesa. To account for this we need to combine both engines
1077 * into our activity counter.
1078 */
Chris Wilson569884e2017-03-09 21:12:31 +00001079 render = now.render_c0 - prev->render_c0;
1080 media = now.media_c0 - prev->media_c0;
1081 c0 = max(render, media);
Mika Kuoppala6b7f6aa2017-03-15 18:12:59 +02001082 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001083
1084 if (c0 > time * dev_priv->rps.up_threshold)
1085 events = GEN6_PM_RP_UP_THRESHOLD;
1086 else if (c0 < time * dev_priv->rps.down_threshold)
1087 events = GEN6_PM_RP_DOWN_THRESHOLD;
Deepak S31685c22014-07-03 17:33:01 -04001088 }
1089
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001090 dev_priv->rps.ei = now;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001091 return events;
Deepak S31685c22014-07-03 17:33:01 -04001092}
1093
Ben Widawsky4912d042011-04-25 11:25:20 -07001094static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001095{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001096 struct drm_i915_private *dev_priv =
1097 container_of(work, struct drm_i915_private, rps.work);
Chris Wilson7c0a16a2017-03-09 21:12:32 +00001098 bool client_boost = false;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001099 int new_delay, adj, min, max;
Chris Wilson7c0a16a2017-03-09 21:12:32 +00001100 u32 pm_iir = 0;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001101
Daniel Vetter59cdb632013-07-04 23:35:28 +02001102 spin_lock_irq(&dev_priv->irq_lock);
Chris Wilson7c0a16a2017-03-09 21:12:32 +00001103 if (dev_priv->rps.interrupts_enabled) {
1104 pm_iir = fetch_and_zero(&dev_priv->rps.pm_iir);
Chris Wilson7b92c1b2017-06-28 13:35:48 +01001105 client_boost = atomic_read(&dev_priv->rps.num_waiters);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001106 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001107 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawsky4912d042011-04-25 11:25:20 -07001108
Paulo Zanoni60611c12013-08-15 11:50:01 -03001109 /* Make sure we didn't queue anything we're not going to process. */
Deepak Sa6706b42014-03-15 20:23:22 +05301110 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
Chris Wilson8d3afd72015-05-21 21:01:47 +01001111 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
Chris Wilson7c0a16a2017-03-09 21:12:32 +00001112 goto out;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001113
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001114 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01001115
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001116 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1117
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001118 adj = dev_priv->rps.last_adj;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001119 new_delay = dev_priv->rps.cur_freq;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001120 min = dev_priv->rps.min_freq_softlimit;
1121 max = dev_priv->rps.max_freq_softlimit;
Chris Wilson7b92c1b2017-06-28 13:35:48 +01001122 if (client_boost)
Chris Wilson29ecd78d2016-07-13 09:10:35 +01001123 max = dev_priv->rps.max_freq;
1124 if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1125 new_delay = dev_priv->rps.boost_freq;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001126 adj = 0;
1127 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001128 if (adj > 0)
1129 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001130 else /* CHV needs even encode values */
1131 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
Sagar Arun Kamble7e79a682017-01-20 09:18:24 +05301132
1133 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1134 adj = 0;
Chris Wilson7b92c1b2017-06-28 13:35:48 +01001135 } else if (client_boost) {
Chris Wilsonf5a4c672015-04-27 13:41:23 +01001136 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001137 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001138 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1139 new_delay = dev_priv->rps.efficient_freq;
Chris Wilson17136d52017-02-10 15:03:47 +00001140 else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
Ben Widawskyb39fb292014-03-19 18:31:11 -07001141 new_delay = dev_priv->rps.min_freq_softlimit;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001142 adj = 0;
1143 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1144 if (adj < 0)
1145 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001146 else /* CHV needs even encode values */
1147 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
Sagar Arun Kamble7e79a682017-01-20 09:18:24 +05301148
1149 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1150 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001151 } else { /* unknown event */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001152 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001153 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001154
Chris Wilsonedcf2842015-04-07 16:20:29 +01001155 dev_priv->rps.last_adj = adj;
1156
Ben Widawsky79249632012-09-07 19:43:42 -07001157 /* sysfs frequency interfaces may have snuck in while servicing the
1158 * interrupt
1159 */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001160 new_delay += adj;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001161 new_delay = clamp_t(int, new_delay, min, max);
Deepak S27544362014-01-27 21:35:05 +05301162
Chris Wilson9fcee2f2017-01-26 10:19:19 +00001163 if (intel_set_rps(dev_priv, new_delay)) {
1164 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1165 dev_priv->rps.last_adj = 0;
1166 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001167
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001168 mutex_unlock(&dev_priv->rps.hw_lock);
Chris Wilson7c0a16a2017-03-09 21:12:32 +00001169
1170out:
1171 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1172 spin_lock_irq(&dev_priv->irq_lock);
1173 if (dev_priv->rps.interrupts_enabled)
1174 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1175 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001176}
1177
Ben Widawskye3689192012-05-25 16:56:22 -07001178
1179/**
1180 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1181 * occurred.
1182 * @work: workqueue struct
1183 *
1184 * Doesn't actually do anything except notify userspace. As a consequence of
1185 * this event, userspace should try to remap the bad rows since statistically
1186 * it is likely the same row is more likely to go bad again.
1187 */
1188static void ivybridge_parity_work(struct work_struct *work)
1189{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001190 struct drm_i915_private *dev_priv =
Joonas Lahtinencefcff82017-04-28 10:58:39 +03001191 container_of(work, typeof(*dev_priv), l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001192 u32 error_status, row, bank, subbank;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001193 char *parity_event[6];
Ben Widawskye3689192012-05-25 16:56:22 -07001194 uint32_t misccpctl;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001195 uint8_t slice = 0;
Ben Widawskye3689192012-05-25 16:56:22 -07001196
1197 /* We must turn off DOP level clock gating to access the L3 registers.
1198 * In order to prevent a get/put style interface, acquire struct mutex
1199 * any time we access those registers.
1200 */
Chris Wilson91c8a322016-07-05 10:40:23 +01001201 mutex_lock(&dev_priv->drm.struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001202
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001203 /* If we've screwed up tracking, just let the interrupt fire again */
1204 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1205 goto out;
1206
Ben Widawskye3689192012-05-25 16:56:22 -07001207 misccpctl = I915_READ(GEN7_MISCCPCTL);
1208 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1209 POSTING_READ(GEN7_MISCCPCTL);
1210
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001211 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001212 i915_reg_t reg;
Ben Widawskye3689192012-05-25 16:56:22 -07001213
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001214 slice--;
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001215 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001216 break;
1217
1218 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1219
Ville Syrjälä6fa1c5f2015-11-04 23:20:02 +02001220 reg = GEN7_L3CDERRST1(slice);
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001221
1222 error_status = I915_READ(reg);
1223 row = GEN7_PARITY_ERROR_ROW(error_status);
1224 bank = GEN7_PARITY_ERROR_BANK(error_status);
1225 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1226
1227 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1228 POSTING_READ(reg);
1229
1230 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1231 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1232 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1233 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1234 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1235 parity_event[5] = NULL;
1236
Chris Wilson91c8a322016-07-05 10:40:23 +01001237 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001238 KOBJ_CHANGE, parity_event);
1239
1240 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1241 slice, row, bank, subbank);
1242
1243 kfree(parity_event[4]);
1244 kfree(parity_event[3]);
1245 kfree(parity_event[2]);
1246 kfree(parity_event[1]);
1247 }
Ben Widawskye3689192012-05-25 16:56:22 -07001248
1249 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1250
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001251out:
1252 WARN_ON(dev_priv->l3_parity.which_slice);
Daniel Vetter4cb21832014-09-15 14:55:26 +02001253 spin_lock_irq(&dev_priv->irq_lock);
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001254 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
Daniel Vetter4cb21832014-09-15 14:55:26 +02001255 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001256
Chris Wilson91c8a322016-07-05 10:40:23 +01001257 mutex_unlock(&dev_priv->drm.struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001258}
1259
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001260static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1261 u32 iir)
Ben Widawskye3689192012-05-25 16:56:22 -07001262{
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001263 if (!HAS_L3_DPF(dev_priv))
Ben Widawskye3689192012-05-25 16:56:22 -07001264 return;
1265
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001266 spin_lock(&dev_priv->irq_lock);
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001267 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001268 spin_unlock(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001269
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001270 iir &= GT_PARITY_ERROR(dev_priv);
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001271 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1272 dev_priv->l3_parity.which_slice |= 1 << 1;
1273
1274 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1275 dev_priv->l3_parity.which_slice |= 1 << 0;
1276
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001277 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001278}
1279
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001280static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001281 u32 gt_iir)
1282{
Chris Wilsonf8973c22016-07-01 17:23:21 +01001283 if (gt_iir & GT_RENDER_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301284 notify_ring(dev_priv->engine[RCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001285 if (gt_iir & ILK_BSD_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301286 notify_ring(dev_priv->engine[VCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001287}
1288
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001289static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001290 u32 gt_iir)
1291{
Chris Wilsonf8973c22016-07-01 17:23:21 +01001292 if (gt_iir & GT_RENDER_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301293 notify_ring(dev_priv->engine[RCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001294 if (gt_iir & GT_BSD_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301295 notify_ring(dev_priv->engine[VCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001296 if (gt_iir & GT_BLT_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301297 notify_ring(dev_priv->engine[BCS]);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001298
Ben Widawskycc609d52013-05-28 19:22:29 -07001299 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1300 GT_BSD_CS_ERROR_INTERRUPT |
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001301 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1302 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
Ben Widawskye3689192012-05-25 16:56:22 -07001303
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001304 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1305 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001306}
1307
Chris Wilson5d3d69d2017-05-17 13:10:06 +01001308static void
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00001309gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
Nick Hoathfbcc1a02015-10-20 10:23:52 +01001310{
Chris Wilson31de7352017-03-16 12:56:18 +00001311 bool tasklet = false;
Chris Wilsonf7470262017-01-24 15:20:21 +00001312
1313 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
Chris Wilsona4b2b012017-05-17 13:10:01 +01001314 if (port_count(&engine->execlist_port[0])) {
Chris Wilson955a4b82017-05-17 13:10:07 +01001315 __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
Chris Wilsona4b2b012017-05-17 13:10:01 +01001316 tasklet = true;
1317 }
Chris Wilsonf7470262017-01-24 15:20:21 +00001318 }
Chris Wilson31de7352017-03-16 12:56:18 +00001319
1320 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
1321 notify_ring(engine);
1322 tasklet |= i915.enable_guc_submission;
1323 }
1324
1325 if (tasklet)
1326 tasklet_hi_schedule(&engine->irq_tasklet);
Nick Hoathfbcc1a02015-10-20 10:23:52 +01001327}
1328
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001329static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1330 u32 master_ctl,
1331 u32 gt_iir[4])
Ben Widawskyabd58f02013-11-02 21:07:09 -07001332{
Ben Widawskyabd58f02013-11-02 21:07:09 -07001333 irqreturn_t ret = IRQ_NONE;
1334
1335 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001336 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1337 if (gt_iir[0]) {
1338 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001339 ret = IRQ_HANDLED;
Ben Widawskyabd58f02013-11-02 21:07:09 -07001340 } else
1341 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1342 }
1343
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001344 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001345 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1346 if (gt_iir[1]) {
1347 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001348 ret = IRQ_HANDLED;
Ben Widawskyabd58f02013-11-02 21:07:09 -07001349 } else
1350 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1351 }
1352
Chris Wilson74cdb332015-04-07 16:21:05 +01001353 if (master_ctl & GEN8_GT_VECS_IRQ) {
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001354 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1355 if (gt_iir[3]) {
1356 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
Chris Wilson74cdb332015-04-07 16:21:05 +01001357 ret = IRQ_HANDLED;
Chris Wilson74cdb332015-04-07 16:21:05 +01001358 } else
1359 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1360 }
1361
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301362 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001363 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301364 if (gt_iir[2] & (dev_priv->pm_rps_events |
1365 dev_priv->pm_guc_events)) {
Chris Wilsoncb0d2052015-04-07 16:21:04 +01001366 I915_WRITE_FW(GEN8_GT_IIR(2),
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301367 gt_iir[2] & (dev_priv->pm_rps_events |
1368 dev_priv->pm_guc_events));
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001369 ret = IRQ_HANDLED;
Ben Widawsky09610212014-05-15 20:58:08 +03001370 } else
1371 DRM_ERROR("The master control interrupt lied (PM)!\n");
1372 }
1373
Ben Widawskyabd58f02013-11-02 21:07:09 -07001374 return ret;
1375}
1376
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001377static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1378 u32 gt_iir[4])
1379{
1380 if (gt_iir[0]) {
Akash Goel3b3f1652016-10-13 22:44:48 +05301381 gen8_cs_irq_handler(dev_priv->engine[RCS],
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001382 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
Akash Goel3b3f1652016-10-13 22:44:48 +05301383 gen8_cs_irq_handler(dev_priv->engine[BCS],
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001384 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1385 }
1386
1387 if (gt_iir[1]) {
Akash Goel3b3f1652016-10-13 22:44:48 +05301388 gen8_cs_irq_handler(dev_priv->engine[VCS],
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001389 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
Akash Goel3b3f1652016-10-13 22:44:48 +05301390 gen8_cs_irq_handler(dev_priv->engine[VCS2],
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001391 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1392 }
1393
1394 if (gt_iir[3])
Akash Goel3b3f1652016-10-13 22:44:48 +05301395 gen8_cs_irq_handler(dev_priv->engine[VECS],
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001396 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1397
1398 if (gt_iir[2] & dev_priv->pm_rps_events)
1399 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301400
1401 if (gt_iir[2] & dev_priv->pm_guc_events)
1402 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001403}
1404
Imre Deak63c88d22015-07-20 14:43:39 -07001405static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1406{
1407 switch (port) {
1408 case PORT_A:
Ville Syrjälä195baa02015-08-27 23:56:00 +03001409 return val & PORTA_HOTPLUG_LONG_DETECT;
Imre Deak63c88d22015-07-20 14:43:39 -07001410 case PORT_B:
1411 return val & PORTB_HOTPLUG_LONG_DETECT;
1412 case PORT_C:
1413 return val & PORTC_HOTPLUG_LONG_DETECT;
Imre Deak63c88d22015-07-20 14:43:39 -07001414 default:
1415 return false;
1416 }
1417}
1418
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03001419static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1420{
1421 switch (port) {
1422 case PORT_E:
1423 return val & PORTE_HOTPLUG_LONG_DETECT;
1424 default:
1425 return false;
1426 }
1427}
1428
Ville Syrjälä74c0b392015-08-27 23:56:07 +03001429static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1430{
1431 switch (port) {
1432 case PORT_A:
1433 return val & PORTA_HOTPLUG_LONG_DETECT;
1434 case PORT_B:
1435 return val & PORTB_HOTPLUG_LONG_DETECT;
1436 case PORT_C:
1437 return val & PORTC_HOTPLUG_LONG_DETECT;
1438 case PORT_D:
1439 return val & PORTD_HOTPLUG_LONG_DETECT;
1440 default:
1441 return false;
1442 }
1443}
1444
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03001445static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1446{
1447 switch (port) {
1448 case PORT_A:
1449 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1450 default:
1451 return false;
1452 }
1453}
1454
Jani Nikula676574d2015-05-28 15:43:53 +03001455static bool pch_port_hotplug_long_detect(enum port port, u32 val)
Dave Airlie13cf5502014-06-18 11:29:35 +10001456{
1457 switch (port) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001458 case PORT_B:
Jani Nikula676574d2015-05-28 15:43:53 +03001459 return val & PORTB_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001460 case PORT_C:
Jani Nikula676574d2015-05-28 15:43:53 +03001461 return val & PORTC_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001462 case PORT_D:
Jani Nikula676574d2015-05-28 15:43:53 +03001463 return val & PORTD_HOTPLUG_LONG_DETECT;
1464 default:
1465 return false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001466 }
1467}
1468
Jani Nikula676574d2015-05-28 15:43:53 +03001469static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
Dave Airlie13cf5502014-06-18 11:29:35 +10001470{
1471 switch (port) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001472 case PORT_B:
Jani Nikula676574d2015-05-28 15:43:53 +03001473 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
Dave Airlie13cf5502014-06-18 11:29:35 +10001474 case PORT_C:
Jani Nikula676574d2015-05-28 15:43:53 +03001475 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
Dave Airlie13cf5502014-06-18 11:29:35 +10001476 case PORT_D:
Jani Nikula676574d2015-05-28 15:43:53 +03001477 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1478 default:
1479 return false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001480 }
1481}
1482
Ville Syrjälä42db67d2015-08-28 21:26:27 +03001483/*
1484 * Get a bit mask of pins that have triggered, and which ones may be long.
1485 * This can be called multiple times with the same masks to accumulate
1486 * hotplug detection results from several registers.
1487 *
1488 * Note that the caller is expected to zero out the masks initially.
1489 */
Imre Deakfd63e2a2015-07-21 15:32:44 -07001490static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
Jani Nikula8c841e52015-06-18 13:06:17 +03001491 u32 hotplug_trigger, u32 dig_hotplug_reg,
Imre Deakfd63e2a2015-07-21 15:32:44 -07001492 const u32 hpd[HPD_NUM_PINS],
1493 bool long_pulse_detect(enum port port, u32 val))
Jani Nikula676574d2015-05-28 15:43:53 +03001494{
Jani Nikula8c841e52015-06-18 13:06:17 +03001495 enum port port;
Jani Nikula676574d2015-05-28 15:43:53 +03001496 int i;
1497
Jani Nikula676574d2015-05-28 15:43:53 +03001498 for_each_hpd_pin(i) {
Jani Nikula8c841e52015-06-18 13:06:17 +03001499 if ((hpd[i] & hotplug_trigger) == 0)
1500 continue;
Jani Nikula676574d2015-05-28 15:43:53 +03001501
Jani Nikula8c841e52015-06-18 13:06:17 +03001502 *pin_mask |= BIT(i);
1503
Rodrigo Vivi256cfdde2017-08-11 11:26:49 -07001504 port = intel_hpd_pin_to_port(i);
1505 if (port == PORT_NONE)
Imre Deakcc24fcd2015-07-21 15:32:45 -07001506 continue;
1507
Imre Deakfd63e2a2015-07-21 15:32:44 -07001508 if (long_pulse_detect(port, dig_hotplug_reg))
Jani Nikula8c841e52015-06-18 13:06:17 +03001509 *long_mask |= BIT(i);
Jani Nikula676574d2015-05-28 15:43:53 +03001510 }
1511
1512 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1513 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1514
1515}
1516
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001517static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001518{
Daniel Vetter28c70f12012-12-01 13:53:45 +01001519 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001520}
1521
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001522static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
Daniel Vetterce99c252012-12-01 13:53:47 +01001523{
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001524 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +01001525}
1526
Shuang He8bf1e9f2013-10-15 18:55:27 +01001527#if defined(CONFIG_DEBUG_FS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001528static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1529 enum pipe pipe,
Daniel Vetter277de952013-10-18 16:37:07 +02001530 uint32_t crc0, uint32_t crc1,
1531 uint32_t crc2, uint32_t crc3,
1532 uint32_t crc4)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001533{
Shuang He8bf1e9f2013-10-15 18:55:27 +01001534 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1535 struct intel_pipe_crc_entry *entry;
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001536 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1537 struct drm_driver *driver = dev_priv->drm.driver;
1538 uint32_t crcs[5];
Damien Lespiauac2300d2013-10-15 18:55:30 +01001539 int head, tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001540
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001541 spin_lock(&pipe_crc->lock);
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001542 if (pipe_crc->source) {
1543 if (!pipe_crc->entries) {
1544 spin_unlock(&pipe_crc->lock);
1545 DRM_DEBUG_KMS("spurious interrupt\n");
1546 return;
1547 }
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001548
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001549 head = pipe_crc->head;
1550 tail = pipe_crc->tail;
1551
1552 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1553 spin_unlock(&pipe_crc->lock);
1554 DRM_ERROR("CRC buffer overflowing\n");
1555 return;
1556 }
1557
1558 entry = &pipe_crc->entries[head];
1559
1560 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1561 entry->crc[0] = crc0;
1562 entry->crc[1] = crc1;
1563 entry->crc[2] = crc2;
1564 entry->crc[3] = crc3;
1565 entry->crc[4] = crc4;
1566
1567 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1568 pipe_crc->head = head;
1569
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001570 spin_unlock(&pipe_crc->lock);
Damien Lespiau0c912c72013-10-15 18:55:37 +01001571
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001572 wake_up_interruptible(&pipe_crc->wq);
1573 } else {
1574 /*
1575 * For some not yet identified reason, the first CRC is
1576 * bonkers. So let's just wait for the next vblank and read
1577 * out the buggy result.
1578 *
1579 * On CHV sometimes the second CRC is bonkers as well, so
1580 * don't trust that one either.
1581 */
1582 if (pipe_crc->skipped == 0 ||
1583 (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1584 pipe_crc->skipped++;
1585 spin_unlock(&pipe_crc->lock);
1586 return;
1587 }
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001588 spin_unlock(&pipe_crc->lock);
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001589 crcs[0] = crc0;
1590 crcs[1] = crc1;
1591 crcs[2] = crc2;
1592 crcs[3] = crc3;
1593 crcs[4] = crc4;
Tomeu Vizoso246ee522017-01-10 14:43:05 +01001594 drm_crtc_add_crc_entry(&crtc->base, true,
Daniel Vetterca814b22017-05-24 16:51:47 +02001595 drm_crtc_accurate_vblank_count(&crtc->base),
Tomeu Vizoso246ee522017-01-10 14:43:05 +01001596 crcs);
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001597 }
Shuang He8bf1e9f2013-10-15 18:55:27 +01001598}
Daniel Vetter277de952013-10-18 16:37:07 +02001599#else
1600static inline void
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001601display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1602 enum pipe pipe,
Daniel Vetter277de952013-10-18 16:37:07 +02001603 uint32_t crc0, uint32_t crc1,
1604 uint32_t crc2, uint32_t crc3,
1605 uint32_t crc4) {}
1606#endif
Daniel Vettereba94eb2013-10-16 22:55:46 +02001607
Daniel Vetter277de952013-10-18 16:37:07 +02001608
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001609static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1610 enum pipe pipe)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001611{
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001612 display_pipe_crc_irq_handler(dev_priv, pipe,
Daniel Vetter277de952013-10-18 16:37:07 +02001613 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1614 0, 0, 0, 0);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001615}
1616
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001617static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1618 enum pipe pipe)
Daniel Vettereba94eb2013-10-16 22:55:46 +02001619{
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001620 display_pipe_crc_irq_handler(dev_priv, pipe,
Daniel Vetter277de952013-10-18 16:37:07 +02001621 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1622 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1623 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1624 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1625 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
Daniel Vettereba94eb2013-10-16 22:55:46 +02001626}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001627
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001628static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1629 enum pipe pipe)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001630{
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001631 uint32_t res1, res2;
1632
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001633 if (INTEL_GEN(dev_priv) >= 3)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001634 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1635 else
1636 res1 = 0;
1637
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001638 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001639 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1640 else
1641 res2 = 0;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001642
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001643 display_pipe_crc_irq_handler(dev_priv, pipe,
Daniel Vetter277de952013-10-18 16:37:07 +02001644 I915_READ(PIPE_CRC_RES_RED(pipe)),
1645 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1646 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1647 res1, res2);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001648}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001649
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001650/* The RPS events need forcewake, so we add them to a work queue and mask their
1651 * IMR bits until the work is done. Other interrupts can be processed without
1652 * the work queue. */
1653static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
Ben Widawskybaf02a12013-05-28 19:22:24 -07001654{
Deepak Sa6706b42014-03-15 20:23:22 +05301655 if (pm_iir & dev_priv->pm_rps_events) {
Daniel Vetter59cdb632013-07-04 23:35:28 +02001656 spin_lock(&dev_priv->irq_lock);
Akash Goelf4e9af42016-10-12 21:54:30 +05301657 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001658 if (dev_priv->rps.interrupts_enabled) {
1659 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
Chris Wilsonc33d2472016-07-04 08:08:36 +01001660 schedule_work(&dev_priv->rps.work);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001661 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001662 spin_unlock(&dev_priv->irq_lock);
Ben Widawskybaf02a12013-05-28 19:22:24 -07001663 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001664
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07001665 if (INTEL_GEN(dev_priv) >= 8)
Imre Deakc9a9a262014-11-05 20:48:37 +02001666 return;
1667
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001668 if (HAS_VEBOX(dev_priv)) {
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001669 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05301670 notify_ring(dev_priv->engine[VECS]);
Ben Widawsky12638c52013-05-28 19:22:31 -07001671
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001672 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1673 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
Ben Widawsky12638c52013-05-28 19:22:31 -07001674 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001675}
1676
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301677static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1678{
1679 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
Sagar Arun Kamble4100b2a2016-10-12 21:54:32 +05301680 /* Sample the log buffer flush related bits & clear them out now
1681 * itself from the message identity register to minimize the
1682 * probability of losing a flush interrupt, when there are back
1683 * to back flush interrupts.
1684 * There can be a new flush interrupt, for different log buffer
1685 * type (like for ISR), whilst Host is handling one (for DPC).
1686 * Since same bit is used in message register for ISR & DPC, it
1687 * could happen that GuC sets the bit for 2nd interrupt but Host
1688 * clears out the bit on handling the 1st interrupt.
1689 */
1690 u32 msg, flush;
1691
1692 msg = I915_READ(SOFT_SCRATCH(15));
Arkadiusz Hilera80bc452016-11-25 18:59:34 +01001693 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1694 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
Sagar Arun Kamble4100b2a2016-10-12 21:54:32 +05301695 if (flush) {
1696 /* Clear the message bits that are handled */
1697 I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1698
1699 /* Handle flush interrupt in bottom half */
Oscar Mateoe7465472017-03-22 10:39:48 -07001700 queue_work(dev_priv->guc.log.runtime.flush_wq,
1701 &dev_priv->guc.log.runtime.flush_work);
Akash Goel5aa1ee42016-10-12 21:54:36 +05301702
1703 dev_priv->guc.log.flush_interrupt_count++;
Sagar Arun Kamble4100b2a2016-10-12 21:54:32 +05301704 } else {
1705 /* Not clearing of unhandled event bits won't result in
1706 * re-triggering of the interrupt.
1707 */
1708 }
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05301709 }
1710}
1711
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001712static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1713 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
Imre Deakc1874ed2014-02-04 21:35:46 +02001714{
Imre Deakc1874ed2014-02-04 21:35:46 +02001715 int pipe;
1716
Imre Deak58ead0d2014-02-04 21:35:47 +02001717 spin_lock(&dev_priv->irq_lock);
Ville Syrjälä1ca993d2016-02-18 21:54:26 +02001718
1719 if (!dev_priv->display_irqs_enabled) {
1720 spin_unlock(&dev_priv->irq_lock);
1721 return;
1722 }
1723
Damien Lespiau055e3932014-08-18 13:49:10 +01001724 for_each_pipe(dev_priv, pipe) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001725 i915_reg_t reg;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001726 u32 mask, iir_bit = 0;
Imre Deak91d181d2014-02-10 18:42:49 +02001727
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001728 /*
1729 * PIPESTAT bits get signalled even when the interrupt is
1730 * disabled with the mask bits, and some of the status bits do
1731 * not generate interrupts at all (like the underrun bit). Hence
1732 * we need to be careful that we only handle what we want to
1733 * handle.
1734 */
Daniel Vetter0f239f42014-09-30 10:56:49 +02001735
1736 /* fifo underruns are filterered in the underrun handler. */
1737 mask = PIPE_FIFO_UNDERRUN_STATUS;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001738
1739 switch (pipe) {
1740 case PIPE_A:
1741 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1742 break;
1743 case PIPE_B:
1744 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1745 break;
Ville Syrjälä3278f672014-04-09 13:28:49 +03001746 case PIPE_C:
1747 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1748 break;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001749 }
1750 if (iir & iir_bit)
1751 mask |= dev_priv->pipestat_irq_mask[pipe];
1752
1753 if (!mask)
Imre Deak91d181d2014-02-10 18:42:49 +02001754 continue;
1755
1756 reg = PIPESTAT(pipe);
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001757 mask |= PIPESTAT_INT_ENABLE_MASK;
1758 pipe_stats[pipe] = I915_READ(reg) & mask;
Imre Deakc1874ed2014-02-04 21:35:46 +02001759
1760 /*
1761 * Clear the PIPE*STAT regs before the IIR
1762 */
Imre Deak91d181d2014-02-10 18:42:49 +02001763 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1764 PIPESTAT_INT_STATUS_MASK))
Imre Deakc1874ed2014-02-04 21:35:46 +02001765 I915_WRITE(reg, pipe_stats[pipe]);
1766 }
Imre Deak58ead0d2014-02-04 21:35:47 +02001767 spin_unlock(&dev_priv->irq_lock);
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001768}
1769
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001770static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001771 u32 pipe_stats[I915_MAX_PIPES])
1772{
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001773 enum pipe pipe;
Imre Deakc1874ed2014-02-04 21:35:46 +02001774
Damien Lespiau055e3932014-08-18 13:49:10 +01001775 for_each_pipe(dev_priv, pipe) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02001776 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1777 drm_handle_vblank(&dev_priv->drm, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001778
1779 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001780 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001781
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001782 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1783 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001784 }
1785
1786 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001787 gmbus_irq_handler(dev_priv);
Imre Deakc1874ed2014-02-04 21:35:46 +02001788}
1789
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001790static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001791{
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001792 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001793
1794 if (hotplug_status)
1795 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1796
1797 return hotplug_status;
1798}
1799
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001800static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001801 u32 hotplug_status)
1802{
Ville Syrjälä42db67d2015-08-28 21:26:27 +03001803 u32 pin_mask = 0, long_mask = 0;
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001804
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001805 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1806 IS_CHERRYVIEW(dev_priv)) {
Jani Nikula0d2e4292015-05-27 15:03:39 +03001807 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001808
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001809 if (hotplug_trigger) {
1810 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1811 hotplug_trigger, hpd_status_g4x,
1812 i9xx_port_hotplug_long_detect);
1813
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001814 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001815 }
Jani Nikula369712e2015-05-27 15:03:40 +03001816
1817 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001818 dp_aux_irq_handler(dev_priv);
Jani Nikula0d2e4292015-05-27 15:03:39 +03001819 } else {
1820 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001821
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001822 if (hotplug_trigger) {
1823 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
Daniel Vetter44cc6c02015-09-30 08:47:41 +02001824 hotplug_trigger, hpd_status_i915,
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001825 i9xx_port_hotplug_long_detect);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001826 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001827 }
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001828 }
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001829}
1830
Daniel Vetterff1f5252012-10-02 15:10:55 +02001831static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001832{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001833 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001834 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001835 irqreturn_t ret = IRQ_NONE;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001836
Imre Deak2dd2a882015-02-24 11:14:30 +02001837 if (!intel_irqs_enabled(dev_priv))
1838 return IRQ_NONE;
1839
Imre Deak1f814da2015-12-16 02:52:19 +02001840 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1841 disable_rpm_wakeref_asserts(dev_priv);
1842
Ville Syrjälä1e1cace2016-04-13 21:19:52 +03001843 do {
Ville Syrjälä6e814802016-04-13 21:19:53 +03001844 u32 iir, gt_iir, pm_iir;
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001845 u32 pipe_stats[I915_MAX_PIPES] = {};
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001846 u32 hotplug_status = 0;
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001847 u32 ier = 0;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001848
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001849 gt_iir = I915_READ(GTIIR);
1850 pm_iir = I915_READ(GEN6_PMIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001851 iir = I915_READ(VLV_IIR);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001852
1853 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
Ville Syrjälä1e1cace2016-04-13 21:19:52 +03001854 break;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001855
1856 ret = IRQ_HANDLED;
1857
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001858 /*
1859 * Theory on interrupt generation, based on empirical evidence:
1860 *
1861 * x = ((VLV_IIR & VLV_IER) ||
1862 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1863 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1864 *
1865 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1866 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1867 * guarantee the CPU interrupt will be raised again even if we
1868 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1869 * bits this time around.
1870 */
Ville Syrjälä4a0a0202016-04-13 21:19:50 +03001871 I915_WRITE(VLV_MASTER_IER, 0);
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001872 ier = I915_READ(VLV_IER);
1873 I915_WRITE(VLV_IER, 0);
Ville Syrjälä4a0a0202016-04-13 21:19:50 +03001874
1875 if (gt_iir)
1876 I915_WRITE(GTIIR, gt_iir);
1877 if (pm_iir)
1878 I915_WRITE(GEN6_PMIIR, pm_iir);
1879
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001880 if (iir & I915_DISPLAY_PORT_INTERRUPT)
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001881 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001882
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001883 /* Call regardless, as some status bits might not be
1884 * signalled in iir */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001885 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001886
Jerome Anandeef57322017-01-25 04:27:49 +05301887 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1888 I915_LPE_PIPE_B_INTERRUPT))
1889 intel_lpe_audio_irq_handler(dev_priv);
1890
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001891 /*
1892 * VLV_IIR is single buffered, and reflects the level
1893 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1894 */
1895 if (iir)
1896 I915_WRITE(VLV_IIR, iir);
Ville Syrjälä4a0a0202016-04-13 21:19:50 +03001897
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001898 I915_WRITE(VLV_IER, ier);
Ville Syrjälä4a0a0202016-04-13 21:19:50 +03001899 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1900 POSTING_READ(VLV_MASTER_IER);
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001901
Ville Syrjälä52894872016-04-13 21:19:56 +03001902 if (gt_iir)
Ville Syrjälä261e40b2016-04-13 21:19:57 +03001903 snb_gt_irq_handler(dev_priv, gt_iir);
Ville Syrjälä52894872016-04-13 21:19:56 +03001904 if (pm_iir)
1905 gen6_rps_irq_handler(dev_priv, pm_iir);
1906
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001907 if (hotplug_status)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001908 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001909
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001910 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
Ville Syrjälä1e1cace2016-04-13 21:19:52 +03001911 } while (0);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001912
Imre Deak1f814da2015-12-16 02:52:19 +02001913 enable_rpm_wakeref_asserts(dev_priv);
1914
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001915 return ret;
1916}
1917
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001918static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1919{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001920 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001921 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001922 irqreturn_t ret = IRQ_NONE;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001923
Imre Deak2dd2a882015-02-24 11:14:30 +02001924 if (!intel_irqs_enabled(dev_priv))
1925 return IRQ_NONE;
1926
Imre Deak1f814da2015-12-16 02:52:19 +02001927 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1928 disable_rpm_wakeref_asserts(dev_priv);
1929
Chris Wilson579de732016-03-14 09:01:57 +00001930 do {
Ville Syrjälä6e814802016-04-13 21:19:53 +03001931 u32 master_ctl, iir;
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001932 u32 gt_iir[4] = {};
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001933 u32 pipe_stats[I915_MAX_PIPES] = {};
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001934 u32 hotplug_status = 0;
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001935 u32 ier = 0;
1936
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001937 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1938 iir = I915_READ(VLV_IIR);
Ville Syrjälä3278f672014-04-09 13:28:49 +03001939
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001940 if (master_ctl == 0 && iir == 0)
1941 break;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001942
Oscar Mateo27b6c122014-06-16 16:11:00 +01001943 ret = IRQ_HANDLED;
1944
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001945 /*
1946 * Theory on interrupt generation, based on empirical evidence:
1947 *
1948 * x = ((VLV_IIR & VLV_IER) ||
1949 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1950 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1951 *
1952 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1953 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1954 * guarantee the CPU interrupt will be raised again even if we
1955 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1956 * bits this time around.
1957 */
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001958 I915_WRITE(GEN8_MASTER_IRQ, 0);
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001959 ier = I915_READ(VLV_IER);
1960 I915_WRITE(VLV_IER, 0);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001961
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001962 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001963
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001964 if (iir & I915_DISPLAY_PORT_INTERRUPT)
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001965 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001966
Oscar Mateo27b6c122014-06-16 16:11:00 +01001967 /* Call regardless, as some status bits might not be
1968 * signalled in iir */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001969 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001970
Jerome Anandeef57322017-01-25 04:27:49 +05301971 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1972 I915_LPE_PIPE_B_INTERRUPT |
1973 I915_LPE_PIPE_C_INTERRUPT))
1974 intel_lpe_audio_irq_handler(dev_priv);
1975
Ville Syrjälä7ce4d1f2016-04-13 21:19:49 +03001976 /*
1977 * VLV_IIR is single buffered, and reflects the level
1978 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1979 */
1980 if (iir)
1981 I915_WRITE(VLV_IIR, iir);
1982
Ville Syrjäläa5e485a2016-04-13 21:19:51 +03001983 I915_WRITE(VLV_IER, ier);
Ville Syrjäläe5328c42016-04-13 21:19:47 +03001984 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001985 POSTING_READ(GEN8_MASTER_IRQ);
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001986
Ville Syrjäläe30e2512016-04-13 21:19:58 +03001987 gen8_gt_irq_handler(dev_priv, gt_iir);
1988
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03001989 if (hotplug_status)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001990 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
Ville Syrjälä2ecb8ca2016-04-13 21:19:55 +03001991
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001992 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
Chris Wilson579de732016-03-14 09:01:57 +00001993 } while (0);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001994
Imre Deak1f814da2015-12-16 02:52:19 +02001995 enable_rpm_wakeref_asserts(dev_priv);
1996
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001997 return ret;
1998}
1999
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002000static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2001 u32 hotplug_trigger,
Ville Syrjälä40e56412015-08-27 23:56:10 +03002002 const u32 hpd[HPD_NUM_PINS])
2003{
Ville Syrjälä40e56412015-08-27 23:56:10 +03002004 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2005
Jani Nikula6a39d7c2015-11-25 16:47:22 +02002006 /*
2007 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2008 * unless we touch the hotplug register, even if hotplug_trigger is
2009 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2010 * errors.
2011 */
Ville Syrjälä40e56412015-08-27 23:56:10 +03002012 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
Jani Nikula6a39d7c2015-11-25 16:47:22 +02002013 if (!hotplug_trigger) {
2014 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2015 PORTD_HOTPLUG_STATUS_MASK |
2016 PORTC_HOTPLUG_STATUS_MASK |
2017 PORTB_HOTPLUG_STATUS_MASK;
2018 dig_hotplug_reg &= ~mask;
2019 }
2020
Ville Syrjälä40e56412015-08-27 23:56:10 +03002021 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
Jani Nikula6a39d7c2015-11-25 16:47:22 +02002022 if (!hotplug_trigger)
2023 return;
Ville Syrjälä40e56412015-08-27 23:56:10 +03002024
2025 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2026 dig_hotplug_reg, hpd,
2027 pch_port_hotplug_long_detect);
2028
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002029 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Ville Syrjälä40e56412015-08-27 23:56:10 +03002030}
2031
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002032static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -08002033{
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002034 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02002035 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Jesse Barnes776ad802011-01-04 15:09:39 -08002036
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002037 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
Daniel Vetter91d131d2013-06-27 17:52:14 +02002038
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03002039 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2040 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2041 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -08002042 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03002043 port_name(port));
2044 }
Jesse Barnes776ad802011-01-04 15:09:39 -08002045
Daniel Vetterce99c252012-12-01 13:53:47 +01002046 if (pch_iir & SDE_AUX_MASK)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002047 dp_aux_irq_handler(dev_priv);
Daniel Vetterce99c252012-12-01 13:53:47 +01002048
Jesse Barnes776ad802011-01-04 15:09:39 -08002049 if (pch_iir & SDE_GMBUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002050 gmbus_irq_handler(dev_priv);
Jesse Barnes776ad802011-01-04 15:09:39 -08002051
2052 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2053 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2054
2055 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2056 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2057
2058 if (pch_iir & SDE_POISON)
2059 DRM_ERROR("PCH poison interrupt\n");
2060
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002061 if (pch_iir & SDE_FDI_MASK)
Damien Lespiau055e3932014-08-18 13:49:10 +01002062 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002063 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2064 pipe_name(pipe),
2065 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08002066
2067 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2068 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2069
2070 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2071 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2072
Jesse Barnes776ad802011-01-04 15:09:39 -08002073 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Matthias Kaehlckea2196032017-07-17 11:14:03 -07002074 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03002075
2076 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
Matthias Kaehlckea2196032017-07-17 11:14:03 -07002077 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03002078}
2079
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002080static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
Paulo Zanoni86642812013-04-12 17:57:57 -03002081{
Paulo Zanoni86642812013-04-12 17:57:57 -03002082 u32 err_int = I915_READ(GEN7_ERR_INT);
Daniel Vetter5a69b892013-10-16 22:55:52 +02002083 enum pipe pipe;
Paulo Zanoni86642812013-04-12 17:57:57 -03002084
Paulo Zanonide032bf2013-04-12 17:57:58 -03002085 if (err_int & ERR_INT_POISON)
2086 DRM_ERROR("Poison interrupt\n");
2087
Damien Lespiau055e3932014-08-18 13:49:10 +01002088 for_each_pipe(dev_priv, pipe) {
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002089 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2090 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanoni86642812013-04-12 17:57:57 -03002091
Daniel Vetter5a69b892013-10-16 22:55:52 +02002092 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002093 if (IS_IVYBRIDGE(dev_priv))
2094 ivb_pipe_crc_irq_handler(dev_priv, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02002095 else
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002096 hsw_pipe_crc_irq_handler(dev_priv, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02002097 }
2098 }
Shuang He8bf1e9f2013-10-15 18:55:27 +01002099
Paulo Zanoni86642812013-04-12 17:57:57 -03002100 I915_WRITE(GEN7_ERR_INT, err_int);
2101}
2102
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002103static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
Paulo Zanoni86642812013-04-12 17:57:57 -03002104{
Paulo Zanoni86642812013-04-12 17:57:57 -03002105 u32 serr_int = I915_READ(SERR_INT);
2106
Paulo Zanonide032bf2013-04-12 17:57:58 -03002107 if (serr_int & SERR_INT_POISON)
2108 DRM_ERROR("PCH poison interrupt\n");
2109
Paulo Zanoni86642812013-04-12 17:57:57 -03002110 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
Matthias Kaehlckea2196032017-07-17 11:14:03 -07002111 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03002112
2113 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
Matthias Kaehlckea2196032017-07-17 11:14:03 -07002114 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03002115
2116 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
Matthias Kaehlckea2196032017-07-17 11:14:03 -07002117 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
Paulo Zanoni86642812013-04-12 17:57:57 -03002118
2119 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08002120}
2121
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002122static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
Adam Jackson23e81d62012-06-06 15:45:44 -04002123{
Adam Jackson23e81d62012-06-06 15:45:44 -04002124 int pipe;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002125 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Adam Jackson23e81d62012-06-06 15:45:44 -04002126
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002127 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
Daniel Vetter91d131d2013-06-27 17:52:14 +02002128
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03002129 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2130 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2131 SDE_AUDIO_POWER_SHIFT_CPT);
2132 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2133 port_name(port));
2134 }
Adam Jackson23e81d62012-06-06 15:45:44 -04002135
2136 if (pch_iir & SDE_AUX_MASK_CPT)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002137 dp_aux_irq_handler(dev_priv);
Adam Jackson23e81d62012-06-06 15:45:44 -04002138
2139 if (pch_iir & SDE_GMBUS_CPT)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002140 gmbus_irq_handler(dev_priv);
Adam Jackson23e81d62012-06-06 15:45:44 -04002141
2142 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2143 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2144
2145 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2146 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2147
2148 if (pch_iir & SDE_FDI_MASK_CPT)
Damien Lespiau055e3932014-08-18 13:49:10 +01002149 for_each_pipe(dev_priv, pipe)
Adam Jackson23e81d62012-06-06 15:45:44 -04002150 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2151 pipe_name(pipe),
2152 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03002153
2154 if (pch_iir & SDE_ERROR_CPT)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002155 cpt_serr_int_handler(dev_priv);
Adam Jackson23e81d62012-06-06 15:45:44 -04002156}
2157
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002158static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002159{
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002160 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2161 ~SDE_PORTE_HOTPLUG_SPT;
2162 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2163 u32 pin_mask = 0, long_mask = 0;
2164
2165 if (hotplug_trigger) {
2166 u32 dig_hotplug_reg;
2167
2168 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2169 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2170
2171 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2172 dig_hotplug_reg, hpd_spt,
Ville Syrjälä74c0b392015-08-27 23:56:07 +03002173 spt_port_hotplug_long_detect);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002174 }
2175
2176 if (hotplug2_trigger) {
2177 u32 dig_hotplug_reg;
2178
2179 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2180 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2181
2182 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2183 dig_hotplug_reg, hpd_spt,
2184 spt_port_hotplug2_long_detect);
2185 }
2186
2187 if (pin_mask)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002188 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002189
2190 if (pch_iir & SDE_GMBUS_CPT)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002191 gmbus_irq_handler(dev_priv);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002192}
2193
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002194static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2195 u32 hotplug_trigger,
Ville Syrjälä40e56412015-08-27 23:56:10 +03002196 const u32 hpd[HPD_NUM_PINS])
2197{
Ville Syrjälä40e56412015-08-27 23:56:10 +03002198 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2199
2200 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2201 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2202
2203 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2204 dig_hotplug_reg, hpd,
2205 ilk_port_hotplug_long_detect);
2206
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002207 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Ville Syrjälä40e56412015-08-27 23:56:10 +03002208}
2209
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002210static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2211 u32 de_iir)
Paulo Zanonic008bc62013-07-12 16:35:10 -03002212{
Daniel Vetter40da17c22013-10-21 18:04:36 +02002213 enum pipe pipe;
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03002214 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2215
Ville Syrjälä40e56412015-08-27 23:56:10 +03002216 if (hotplug_trigger)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002217 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002218
2219 if (de_iir & DE_AUX_CHANNEL_A)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002220 dp_aux_irq_handler(dev_priv);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002221
2222 if (de_iir & DE_GSE)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002223 intel_opregion_asle_intr(dev_priv);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002224
Paulo Zanonic008bc62013-07-12 16:35:10 -03002225 if (de_iir & DE_POISON)
2226 DRM_ERROR("Poison interrupt\n");
2227
Damien Lespiau055e3932014-08-18 13:49:10 +01002228 for_each_pipe(dev_priv, pipe) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02002229 if (de_iir & DE_PIPE_VBLANK(pipe))
2230 drm_handle_vblank(&dev_priv->drm, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002231
Daniel Vetter40da17c22013-10-21 18:04:36 +02002232 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002233 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002234
Daniel Vetter40da17c22013-10-21 18:04:36 +02002235 if (de_iir & DE_PIPE_CRC_DONE(pipe))
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002236 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002237 }
2238
2239 /* check event from PCH */
2240 if (de_iir & DE_PCH_EVENT) {
2241 u32 pch_iir = I915_READ(SDEIIR);
2242
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002243 if (HAS_PCH_CPT(dev_priv))
2244 cpt_irq_handler(dev_priv, pch_iir);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002245 else
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002246 ibx_irq_handler(dev_priv, pch_iir);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002247
2248 /* should clear PCH hotplug event before clear CPU irq */
2249 I915_WRITE(SDEIIR, pch_iir);
2250 }
2251
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002252 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2253 ironlake_rps_change_irq_handler(dev_priv);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002254}
2255
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002256static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2257 u32 de_iir)
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002258{
Damien Lespiau07d27e22014-03-03 17:31:46 +00002259 enum pipe pipe;
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03002260 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2261
Ville Syrjälä40e56412015-08-27 23:56:10 +03002262 if (hotplug_trigger)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002263 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002264
2265 if (de_iir & DE_ERR_INT_IVB)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002266 ivb_err_int_handler(dev_priv);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002267
2268 if (de_iir & DE_AUX_CHANNEL_A_IVB)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002269 dp_aux_irq_handler(dev_priv);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002270
2271 if (de_iir & DE_GSE_IVB)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002272 intel_opregion_asle_intr(dev_priv);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002273
Damien Lespiau055e3932014-08-18 13:49:10 +01002274 for_each_pipe(dev_priv, pipe) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02002275 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2276 drm_handle_vblank(&dev_priv->drm, pipe);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002277 }
2278
2279 /* check event from PCH */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002280 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002281 u32 pch_iir = I915_READ(SDEIIR);
2282
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002283 cpt_irq_handler(dev_priv, pch_iir);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002284
2285 /* clear PCH hotplug event before clear CPU irq */
2286 I915_WRITE(SDEIIR, pch_iir);
2287 }
2288}
2289
Oscar Mateo72c90f62014-06-16 16:10:57 +01002290/*
2291 * To handle irqs with the minimum potential races with fresh interrupts, we:
2292 * 1 - Disable Master Interrupt Control.
2293 * 2 - Find the source(s) of the interrupt.
2294 * 3 - Clear the Interrupt Identity bits (IIR).
2295 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2296 * 5 - Re-enable Master Interrupt Control.
2297 */
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002298static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002299{
Daniel Vetter45a83f82014-05-12 19:17:55 +02002300 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01002301 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002302 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01002303 irqreturn_t ret = IRQ_NONE;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002304
Imre Deak2dd2a882015-02-24 11:14:30 +02002305 if (!intel_irqs_enabled(dev_priv))
2306 return IRQ_NONE;
2307
Imre Deak1f814da2015-12-16 02:52:19 +02002308 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2309 disable_rpm_wakeref_asserts(dev_priv);
2310
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002311 /* disable master interrupt before clearing iir */
2312 de_ier = I915_READ(DEIER);
2313 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Paulo Zanoni23a78512013-07-12 16:35:14 -03002314 POSTING_READ(DEIER);
Chris Wilson0e434062012-05-09 21:45:44 +01002315
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002316 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2317 * interrupts will will be stored on its back queue, and then we'll be
2318 * able to process them after we restore SDEIER (as soon as we restore
2319 * it, we'll get an interrupt if SDEIIR still has something to process
2320 * due to its back queue). */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002321 if (!HAS_PCH_NOP(dev_priv)) {
Ben Widawskyab5c6082013-04-05 13:12:41 -07002322 sde_ier = I915_READ(SDEIER);
2323 I915_WRITE(SDEIER, 0);
2324 POSTING_READ(SDEIER);
2325 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002326
Oscar Mateo72c90f62014-06-16 16:10:57 +01002327 /* Find, clear, then process each source of interrupt */
2328
Chris Wilson0e434062012-05-09 21:45:44 +01002329 gt_iir = I915_READ(GTIIR);
2330 if (gt_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002331 I915_WRITE(GTIIR, gt_iir);
2332 ret = IRQ_HANDLED;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002333 if (INTEL_GEN(dev_priv) >= 6)
Ville Syrjälä261e40b2016-04-13 21:19:57 +03002334 snb_gt_irq_handler(dev_priv, gt_iir);
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002335 else
Ville Syrjälä261e40b2016-04-13 21:19:57 +03002336 ilk_gt_irq_handler(dev_priv, gt_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002337 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002338
2339 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01002340 if (de_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002341 I915_WRITE(DEIIR, de_iir);
2342 ret = IRQ_HANDLED;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002343 if (INTEL_GEN(dev_priv) >= 7)
2344 ivb_display_irq_handler(dev_priv, de_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002345 else
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002346 ilk_display_irq_handler(dev_priv, de_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002347 }
2348
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002349 if (INTEL_GEN(dev_priv) >= 6) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002350 u32 pm_iir = I915_READ(GEN6_PMIIR);
2351 if (pm_iir) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002352 I915_WRITE(GEN6_PMIIR, pm_iir);
2353 ret = IRQ_HANDLED;
Oscar Mateo72c90f62014-06-16 16:10:57 +01002354 gen6_rps_irq_handler(dev_priv, pm_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002355 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002356 }
2357
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002358 I915_WRITE(DEIER, de_ier);
2359 POSTING_READ(DEIER);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002360 if (!HAS_PCH_NOP(dev_priv)) {
Ben Widawskyab5c6082013-04-05 13:12:41 -07002361 I915_WRITE(SDEIER, sde_ier);
2362 POSTING_READ(SDEIER);
2363 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002364
Imre Deak1f814da2015-12-16 02:52:19 +02002365 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2366 enable_rpm_wakeref_asserts(dev_priv);
2367
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002368 return ret;
2369}
2370
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002371static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2372 u32 hotplug_trigger,
Ville Syrjälä40e56412015-08-27 23:56:10 +03002373 const u32 hpd[HPD_NUM_PINS])
Shashank Sharmad04a4922014-08-22 17:40:41 +05302374{
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002375 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
Shashank Sharmad04a4922014-08-22 17:40:41 +05302376
Ville Syrjäläa52bb152015-08-27 23:56:11 +03002377 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2378 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302379
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002380 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
Ville Syrjälä40e56412015-08-27 23:56:10 +03002381 dig_hotplug_reg, hpd,
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002382 bxt_port_hotplug_long_detect);
Ville Syrjälä40e56412015-08-27 23:56:10 +03002383
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002384 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302385}
2386
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002387static irqreturn_t
2388gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
Ben Widawskyabd58f02013-11-02 21:07:09 -07002389{
Ben Widawskyabd58f02013-11-02 21:07:09 -07002390 irqreturn_t ret = IRQ_NONE;
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002391 u32 iir;
Daniel Vetterc42664c2013-11-07 11:05:40 +01002392 enum pipe pipe;
Jesse Barnes88e04702014-11-13 17:51:48 +00002393
Ben Widawskyabd58f02013-11-02 21:07:09 -07002394 if (master_ctl & GEN8_DE_MISC_IRQ) {
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002395 iir = I915_READ(GEN8_DE_MISC_IIR);
2396 if (iir) {
2397 I915_WRITE(GEN8_DE_MISC_IIR, iir);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002398 ret = IRQ_HANDLED;
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002399 if (iir & GEN8_DE_MISC_GSE)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002400 intel_opregion_asle_intr(dev_priv);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002401 else
2402 DRM_ERROR("Unexpected DE Misc interrupt\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002403 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002404 else
2405 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002406 }
2407
Daniel Vetter6d766f02013-11-07 14:49:55 +01002408 if (master_ctl & GEN8_DE_PORT_IRQ) {
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002409 iir = I915_READ(GEN8_DE_PORT_IIR);
2410 if (iir) {
2411 u32 tmp_mask;
Shashank Sharmad04a4922014-08-22 17:40:41 +05302412 bool found = false;
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002413
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002414 I915_WRITE(GEN8_DE_PORT_IIR, iir);
Daniel Vetter6d766f02013-11-07 14:49:55 +01002415 ret = IRQ_HANDLED;
Jesse Barnes88e04702014-11-13 17:51:48 +00002416
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002417 tmp_mask = GEN8_AUX_CHANNEL_A;
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07002418 if (INTEL_GEN(dev_priv) >= 9)
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002419 tmp_mask |= GEN9_AUX_CHANNEL_B |
2420 GEN9_AUX_CHANNEL_C |
2421 GEN9_AUX_CHANNEL_D;
2422
2423 if (iir & tmp_mask) {
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002424 dp_aux_irq_handler(dev_priv);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302425 found = true;
2426 }
2427
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002428 if (IS_GEN9_LP(dev_priv)) {
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002429 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2430 if (tmp_mask) {
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002431 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2432 hpd_bxt);
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002433 found = true;
2434 }
2435 } else if (IS_BROADWELL(dev_priv)) {
2436 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2437 if (tmp_mask) {
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002438 ilk_hpd_irq_handler(dev_priv,
2439 tmp_mask, hpd_bdw);
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002440 found = true;
2441 }
Shashank Sharmad04a4922014-08-22 17:40:41 +05302442 }
2443
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002444 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002445 gmbus_irq_handler(dev_priv);
Shashank Sharma9e637432014-08-22 17:40:43 +05302446 found = true;
2447 }
2448
Shashank Sharmad04a4922014-08-22 17:40:41 +05302449 if (!found)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002450 DRM_ERROR("Unexpected DE Port interrupt\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002451 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002452 else
2453 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002454 }
2455
Damien Lespiau055e3932014-08-18 13:49:10 +01002456 for_each_pipe(dev_priv, pipe) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02002457 u32 fault_errors;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002458
Daniel Vetterc42664c2013-11-07 11:05:40 +01002459 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2460 continue;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002461
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002462 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2463 if (!iir) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07002464 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002465 continue;
2466 }
2467
2468 ret = IRQ_HANDLED;
2469 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2470
Daniel Vetterfd3a4022017-07-20 19:57:51 +02002471 if (iir & GEN8_PIPE_VBLANK)
2472 drm_handle_vblank(&dev_priv->drm, pipe);
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002473
2474 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002475 hsw_pipe_crc_irq_handler(dev_priv, pipe);
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002476
2477 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2478 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2479
2480 fault_errors = iir;
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07002481 if (INTEL_GEN(dev_priv) >= 9)
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002482 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2483 else
2484 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2485
2486 if (fault_errors)
Tvrtko Ursulin1353ec32016-10-27 13:48:32 +01002487 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002488 pipe_name(pipe),
2489 fault_errors);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002490 }
2491
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002492 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
Shashank Sharma266ea3d2014-08-22 17:40:42 +05302493 master_ctl & GEN8_DE_PCH_IRQ) {
Daniel Vetter92d03a82013-11-07 11:05:43 +01002494 /*
2495 * FIXME(BDW): Assume for now that the new interrupt handling
2496 * scheme also closed the SDE interrupt handling race we've seen
2497 * on older pch-split platforms. But this needs testing.
2498 */
Tvrtko Ursuline32192e2016-01-12 16:04:06 +00002499 iir = I915_READ(SDEIIR);
2500 if (iir) {
2501 I915_WRITE(SDEIIR, iir);
Daniel Vetter92d03a82013-11-07 11:05:43 +01002502 ret = IRQ_HANDLED;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002503
Rodrigo Vivi7b22b8c2017-06-02 13:06:39 -07002504 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
2505 HAS_PCH_CNP(dev_priv))
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002506 spt_irq_handler(dev_priv, iir);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002507 else
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01002508 cpt_irq_handler(dev_priv, iir);
Jani Nikula2dfb0b82016-01-07 10:29:10 +02002509 } else {
2510 /*
2511 * Like on previous PCH there seems to be something
2512 * fishy going on with forwarding PCH interrupts.
2513 */
2514 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2515 }
Daniel Vetter92d03a82013-11-07 11:05:43 +01002516 }
2517
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002518 return ret;
2519}
2520
2521static irqreturn_t gen8_irq_handler(int irq, void *arg)
2522{
2523 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01002524 struct drm_i915_private *dev_priv = to_i915(dev);
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002525 u32 master_ctl;
Ville Syrjäläe30e2512016-04-13 21:19:58 +03002526 u32 gt_iir[4] = {};
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002527 irqreturn_t ret;
2528
2529 if (!intel_irqs_enabled(dev_priv))
2530 return IRQ_NONE;
2531
2532 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2533 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2534 if (!master_ctl)
2535 return IRQ_NONE;
2536
2537 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2538
2539 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2540 disable_rpm_wakeref_asserts(dev_priv);
2541
2542 /* Find, clear, then process each source of interrupt */
Ville Syrjäläe30e2512016-04-13 21:19:58 +03002543 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2544 gen8_gt_irq_handler(dev_priv, gt_iir);
Tvrtko Ursulinf11a0f42016-01-12 16:04:07 +00002545 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2546
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002547 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2548 POSTING_READ_FW(GEN8_MASTER_IRQ);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002549
Imre Deak1f814da2015-12-16 02:52:19 +02002550 enable_rpm_wakeref_asserts(dev_priv);
2551
Ben Widawskyabd58f02013-11-02 21:07:09 -07002552 return ret;
2553}
2554
Chris Wilson36703e72017-06-22 11:56:25 +01002555struct wedge_me {
2556 struct delayed_work work;
2557 struct drm_i915_private *i915;
2558 const char *name;
2559};
2560
2561static void wedge_me(struct work_struct *work)
2562{
2563 struct wedge_me *w = container_of(work, typeof(*w), work.work);
2564
2565 dev_err(w->i915->drm.dev,
2566 "%s timed out, cancelling all in-flight rendering.\n",
2567 w->name);
2568 i915_gem_set_wedged(w->i915);
2569}
2570
2571static void __init_wedge(struct wedge_me *w,
2572 struct drm_i915_private *i915,
2573 long timeout,
2574 const char *name)
2575{
2576 w->i915 = i915;
2577 w->name = name;
2578
2579 INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2580 schedule_delayed_work(&w->work, timeout);
2581}
2582
2583static void __fini_wedge(struct wedge_me *w)
2584{
2585 cancel_delayed_work_sync(&w->work);
2586 destroy_delayed_work_on_stack(&w->work);
2587 w->i915 = NULL;
2588}
2589
2590#define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
2591 for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \
2592 (W)->i915; \
2593 __fini_wedge((W)))
2594
Jesse Barnes8a905232009-07-11 16:48:03 -04002595/**
Chris Wilsond5367302017-06-20 10:57:43 +01002596 * i915_reset_device - do process context error handling work
Tvrtko Ursulin14bb2c12016-06-03 14:02:17 +01002597 * @dev_priv: i915 device private
Jesse Barnes8a905232009-07-11 16:48:03 -04002598 *
2599 * Fire an error uevent so userspace can see that a hang or error
2600 * was detected.
2601 */
Chris Wilsond5367302017-06-20 10:57:43 +01002602static void i915_reset_device(struct drm_i915_private *dev_priv)
Jesse Barnes8a905232009-07-11 16:48:03 -04002603{
Chris Wilson91c8a322016-07-05 10:40:23 +01002604 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
Ben Widawskycce723e2013-07-19 09:16:42 -07002605 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2606 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2607 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
Chris Wilson36703e72017-06-22 11:56:25 +01002608 struct wedge_me w;
Jesse Barnes8a905232009-07-11 16:48:03 -04002609
Chris Wilsonc0336662016-05-06 15:40:21 +01002610 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04002611
Chris Wilson8af29b02016-09-09 14:11:47 +01002612 DRM_DEBUG_DRIVER("resetting chip\n");
2613 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2614
Chris Wilson36703e72017-06-22 11:56:25 +01002615 /* Use a watchdog to ensure that our reset completes */
2616 i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
2617 intel_prepare_reset(dev_priv);
Ville Syrjälä75147472014-11-24 18:28:11 +02002618
Chris Wilson36703e72017-06-22 11:56:25 +01002619 /* Signal that locked waiters should reset the GPU */
2620 set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
2621 wake_up_all(&dev_priv->gpu_error.wait_queue);
Chris Wilson8c185ec2017-03-16 17:13:02 +00002622
Chris Wilson36703e72017-06-22 11:56:25 +01002623 /* Wait for anyone holding the lock to wakeup, without
2624 * blocking indefinitely on struct_mutex.
Chris Wilson780f2622016-09-09 14:11:52 +01002625 */
Chris Wilson36703e72017-06-22 11:56:25 +01002626 do {
2627 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
Chris Wilson535275d2017-07-21 13:32:37 +01002628 i915_reset(dev_priv, 0);
Chris Wilson36703e72017-06-22 11:56:25 +01002629 mutex_unlock(&dev_priv->drm.struct_mutex);
2630 }
2631 } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2632 I915_RESET_HANDOFF,
2633 TASK_UNINTERRUPTIBLE,
2634 1));
Chris Wilson780f2622016-09-09 14:11:52 +01002635
Chris Wilson36703e72017-06-22 11:56:25 +01002636 intel_finish_reset(dev_priv);
2637 }
Daniel Vetter17e1df02013-09-08 21:57:13 +02002638
Chris Wilson780f2622016-09-09 14:11:52 +01002639 if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
Chris Wilson8af29b02016-09-09 14:11:47 +01002640 kobject_uevent_env(kobj,
2641 KOBJ_CHANGE, reset_done_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04002642}
2643
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002644static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
Jesse Barnes8a905232009-07-11 16:48:03 -04002645{
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002646 u32 eir;
Jesse Barnes8a905232009-07-11 16:48:03 -04002647
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002648 if (!IS_GEN2(dev_priv))
2649 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
Jesse Barnes8a905232009-07-11 16:48:03 -04002650
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002651 if (INTEL_GEN(dev_priv) < 4)
2652 I915_WRITE(IPEIR, I915_READ(IPEIR));
2653 else
2654 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002655
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002656 I915_WRITE(EIR, I915_READ(EIR));
Jesse Barnes8a905232009-07-11 16:48:03 -04002657 eir = I915_READ(EIR);
2658 if (eir) {
2659 /*
2660 * some errors might have become stuck,
2661 * mask them.
2662 */
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002663 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04002664 I915_WRITE(EMR, I915_READ(EMR) | eir);
2665 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2666 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01002667}
2668
2669/**
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002670 * i915_handle_error - handle a gpu error
Tvrtko Ursulin14bb2c12016-06-03 14:02:17 +01002671 * @dev_priv: i915 device private
arun.siluvery@linux.intel.com14b730f2016-03-18 20:07:55 +00002672 * @engine_mask: mask representing engines that are hung
Michel Thierry87c390b2017-01-11 20:18:08 -08002673 * @fmt: Error message format string
2674 *
Javier Martinez Canillasaafd8582015-10-08 09:57:49 +02002675 * Do some basic checking of register state at error time and
Chris Wilson35aed2e2010-05-27 13:18:12 +01002676 * dump it to the syslog. Also call i915_capture_error_state() to make
2677 * sure we get a record and make it available in debugfs. Fire a uevent
2678 * so userspace knows something bad happened (should trigger collection
2679 * of a ring dump etc.).
2680 */
Chris Wilsonc0336662016-05-06 15:40:21 +01002681void i915_handle_error(struct drm_i915_private *dev_priv,
2682 u32 engine_mask,
Mika Kuoppala58174462014-02-25 17:11:26 +02002683 const char *fmt, ...)
Chris Wilson35aed2e2010-05-27 13:18:12 +01002684{
Michel Thierry142bc7d2017-06-20 10:57:46 +01002685 struct intel_engine_cs *engine;
2686 unsigned int tmp;
Mika Kuoppala58174462014-02-25 17:11:26 +02002687 va_list args;
2688 char error_msg[80];
Chris Wilson35aed2e2010-05-27 13:18:12 +01002689
Mika Kuoppala58174462014-02-25 17:11:26 +02002690 va_start(args, fmt);
2691 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2692 va_end(args);
2693
Chris Wilson1604a862017-03-14 17:18:40 +00002694 /*
2695 * In most cases it's guaranteed that we get here with an RPM
2696 * reference held, for example because there is a pending GPU
2697 * request that won't finish until the reset is done. This
2698 * isn't the case at least when we get here by doing a
2699 * simulated reset via debugfs, so get an RPM reference.
2700 */
2701 intel_runtime_pm_get(dev_priv);
2702
Chris Wilsonc0336662016-05-06 15:40:21 +01002703 i915_capture_error_state(dev_priv, engine_mask, error_msg);
Chris Wilsoneaa14c22016-10-19 13:52:03 +01002704 i915_clear_error_registers(dev_priv);
Jesse Barnes8a905232009-07-11 16:48:03 -04002705
Michel Thierry142bc7d2017-06-20 10:57:46 +01002706 /*
2707 * Try engine reset when available. We fall back to full reset if
2708 * single reset fails.
2709 */
2710 if (intel_has_reset_engine(dev_priv)) {
2711 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
Daniel Vetter9db529a2017-08-08 10:08:28 +02002712 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
Michel Thierry142bc7d2017-06-20 10:57:46 +01002713 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
2714 &dev_priv->gpu_error.flags))
2715 continue;
2716
Chris Wilson535275d2017-07-21 13:32:37 +01002717 if (i915_reset_engine(engine, 0) == 0)
Michel Thierry142bc7d2017-06-20 10:57:46 +01002718 engine_mask &= ~intel_engine_flag(engine);
2719
2720 clear_bit(I915_RESET_ENGINE + engine->id,
2721 &dev_priv->gpu_error.flags);
2722 wake_up_bit(&dev_priv->gpu_error.flags,
2723 I915_RESET_ENGINE + engine->id);
2724 }
2725 }
2726
Chris Wilson8af29b02016-09-09 14:11:47 +01002727 if (!engine_mask)
Chris Wilson1604a862017-03-14 17:18:40 +00002728 goto out;
Ben Gamariba1234d2009-09-14 17:48:47 -04002729
Michel Thierry142bc7d2017-06-20 10:57:46 +01002730 /* Full reset needs the mutex, stop any other user trying to do so. */
Chris Wilsond5367302017-06-20 10:57:43 +01002731 if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) {
2732 wait_event(dev_priv->gpu_error.reset_queue,
2733 !test_bit(I915_RESET_BACKOFF,
2734 &dev_priv->gpu_error.flags));
Chris Wilson1604a862017-03-14 17:18:40 +00002735 goto out;
Chris Wilsond5367302017-06-20 10:57:43 +01002736 }
Chris Wilson8af29b02016-09-09 14:11:47 +01002737
Michel Thierry142bc7d2017-06-20 10:57:46 +01002738 /* Prevent any other reset-engine attempt. */
2739 for_each_engine(engine, dev_priv, tmp) {
2740 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
2741 &dev_priv->gpu_error.flags))
2742 wait_on_bit(&dev_priv->gpu_error.flags,
2743 I915_RESET_ENGINE + engine->id,
2744 TASK_UNINTERRUPTIBLE);
2745 }
2746
Chris Wilsond5367302017-06-20 10:57:43 +01002747 i915_reset_device(dev_priv);
2748
Michel Thierry142bc7d2017-06-20 10:57:46 +01002749 for_each_engine(engine, dev_priv, tmp) {
2750 clear_bit(I915_RESET_ENGINE + engine->id,
2751 &dev_priv->gpu_error.flags);
2752 }
2753
Chris Wilsond5367302017-06-20 10:57:43 +01002754 clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags);
2755 wake_up_all(&dev_priv->gpu_error.reset_queue);
Chris Wilson1604a862017-03-14 17:18:40 +00002756
2757out:
2758 intel_runtime_pm_put(dev_priv);
Jesse Barnes8a905232009-07-11 16:48:03 -04002759}
2760
Keith Packard42f52ef2008-10-18 19:39:29 -07002761/* Called from drm generic code, passed 'crtc' which
2762 * we use as a pipe index
2763 */
Chris Wilson86e83e32016-10-07 20:49:52 +01002764static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002765{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002766 struct drm_i915_private *dev_priv = to_i915(dev);
Keith Packarde9d21d72008-10-16 11:31:38 -07002767 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002768
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002769 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilson86e83e32016-10-07 20:49:52 +01002770 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2771 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2772
2773 return 0;
2774}
2775
2776static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2777{
2778 struct drm_i915_private *dev_priv = to_i915(dev);
2779 unsigned long irqflags;
2780
2781 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2782 i915_enable_pipestat(dev_priv, pipe,
2783 PIPE_START_VBLANK_INTERRUPT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002784 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002785
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002786 return 0;
2787}
2788
Thierry Reding88e72712015-09-24 18:35:31 +02002789static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002790{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002791 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002792 unsigned long irqflags;
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +01002793 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
Chris Wilson86e83e32016-10-07 20:49:52 +01002794 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002795
Jesse Barnesf796cf82011-04-07 13:58:17 -07002796 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02002797 ilk_enable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002798 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2799
2800 return 0;
2801}
2802
Thierry Reding88e72712015-09-24 18:35:31 +02002803static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
Ben Widawskyabd58f02013-11-02 21:07:09 -07002804{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002805 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002806 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002807
Ben Widawskyabd58f02013-11-02 21:07:09 -07002808 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Ville Syrjälä013d3752015-11-23 18:06:17 +02002809 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002810 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Ville Syrjälä013d3752015-11-23 18:06:17 +02002811
Ben Widawskyabd58f02013-11-02 21:07:09 -07002812 return 0;
2813}
2814
Keith Packard42f52ef2008-10-18 19:39:29 -07002815/* Called from drm generic code, passed 'crtc' which
2816 * we use as a pipe index
2817 */
Chris Wilson86e83e32016-10-07 20:49:52 +01002818static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2819{
2820 struct drm_i915_private *dev_priv = to_i915(dev);
2821 unsigned long irqflags;
2822
2823 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2824 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2825 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2826}
2827
2828static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002829{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002830 struct drm_i915_private *dev_priv = to_i915(dev);
Keith Packarde9d21d72008-10-16 11:31:38 -07002831 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002832
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002833 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002834 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002835 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002836 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2837}
2838
Thierry Reding88e72712015-09-24 18:35:31 +02002839static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002840{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002841 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002842 unsigned long irqflags;
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +01002843 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
Chris Wilson86e83e32016-10-07 20:49:52 +01002844 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002845
2846 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02002847 ilk_disable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002848 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2849}
2850
Thierry Reding88e72712015-09-24 18:35:31 +02002851static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
Ben Widawskyabd58f02013-11-02 21:07:09 -07002852{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002853 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002854 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002855
Ben Widawskyabd58f02013-11-02 21:07:09 -07002856 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Ville Syrjälä013d3752015-11-23 18:06:17 +02002857 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002858 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2859}
2860
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002861static void ibx_irq_reset(struct drm_i915_private *dev_priv)
Paulo Zanoni91738a92013-06-05 14:21:51 -03002862{
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01002863 if (HAS_PCH_NOP(dev_priv))
Paulo Zanoni91738a92013-06-05 14:21:51 -03002864 return;
2865
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03002866 GEN5_IRQ_RESET(SDE);
Paulo Zanoni105b1222014-04-01 15:37:17 -03002867
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01002868 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
Paulo Zanoni105b1222014-04-01 15:37:17 -03002869 I915_WRITE(SERR_INT, 0xffffffff);
Paulo Zanoni622364b2014-04-01 15:37:22 -03002870}
Paulo Zanoni105b1222014-04-01 15:37:17 -03002871
Paulo Zanoni622364b2014-04-01 15:37:22 -03002872/*
2873 * SDEIER is also touched by the interrupt handler to work around missed PCH
2874 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2875 * instead we unconditionally enable all PCH interrupt sources here, but then
2876 * only unmask them as needed with SDEIMR.
2877 *
2878 * This function needs to be called before interrupts are enabled.
2879 */
2880static void ibx_irq_pre_postinstall(struct drm_device *dev)
2881{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002882 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni622364b2014-04-01 15:37:22 -03002883
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01002884 if (HAS_PCH_NOP(dev_priv))
Paulo Zanoni622364b2014-04-01 15:37:22 -03002885 return;
2886
2887 WARN_ON(I915_READ(SDEIER) != 0);
Paulo Zanoni91738a92013-06-05 14:21:51 -03002888 I915_WRITE(SDEIER, 0xffffffff);
2889 POSTING_READ(SDEIER);
2890}
2891
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002892static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02002893{
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03002894 GEN5_IRQ_RESET(GT);
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002895 if (INTEL_GEN(dev_priv) >= 6)
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03002896 GEN5_IRQ_RESET(GEN6_PM);
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02002897}
2898
Ville Syrjälä70591a42014-10-30 19:42:58 +02002899static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2900{
2901 enum pipe pipe;
2902
Ville Syrjälä71b8b412016-04-11 16:56:31 +03002903 if (IS_CHERRYVIEW(dev_priv))
2904 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2905 else
2906 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2907
Ville Syrjäläad22d102016-04-12 18:56:14 +03002908 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
Ville Syrjälä70591a42014-10-30 19:42:58 +02002909 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2910
Ville Syrjäläad22d102016-04-12 18:56:14 +03002911 for_each_pipe(dev_priv, pipe) {
2912 I915_WRITE(PIPESTAT(pipe),
2913 PIPE_FIFO_UNDERRUN_STATUS |
2914 PIPESTAT_INT_STATUS_MASK);
2915 dev_priv->pipestat_irq_mask[pipe] = 0;
2916 }
Ville Syrjälä70591a42014-10-30 19:42:58 +02002917
2918 GEN5_IRQ_RESET(VLV_);
Ville Syrjäläad22d102016-04-12 18:56:14 +03002919 dev_priv->irq_mask = ~0;
Ville Syrjälä70591a42014-10-30 19:42:58 +02002920}
2921
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002922static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2923{
2924 u32 pipestat_mask;
Ville Syrjälä9ab981f2016-04-11 16:56:28 +03002925 u32 enable_mask;
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002926 enum pipe pipe;
2927
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002928 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2929 PIPE_CRC_DONE_INTERRUPT_STATUS;
2930
2931 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2932 for_each_pipe(dev_priv, pipe)
2933 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2934
Ville Syrjälä9ab981f2016-04-11 16:56:28 +03002935 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2936 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Ville Syrjäläebf5f922017-04-27 19:02:22 +03002937 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2938 I915_LPE_PIPE_A_INTERRUPT |
2939 I915_LPE_PIPE_B_INTERRUPT;
2940
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002941 if (IS_CHERRYVIEW(dev_priv))
Ville Syrjäläebf5f922017-04-27 19:02:22 +03002942 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2943 I915_LPE_PIPE_C_INTERRUPT;
Ville Syrjälä6b7eafc2016-04-11 16:56:29 +03002944
2945 WARN_ON(dev_priv->irq_mask != ~0);
2946
Ville Syrjälä9ab981f2016-04-11 16:56:28 +03002947 dev_priv->irq_mask = ~enable_mask;
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002948
Ville Syrjälä9ab981f2016-04-11 16:56:28 +03002949 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002950}
2951
2952/* drm_dma.h hooks
2953*/
2954static void ironlake_irq_reset(struct drm_device *dev)
2955{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002956 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002957
2958 I915_WRITE(HWSTAM, 0xffffffff);
2959
2960 GEN5_IRQ_RESET(DE);
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002961 if (IS_GEN7(dev_priv))
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002962 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2963
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002964 gen5_gt_irq_reset(dev_priv);
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002965
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002966 ibx_irq_reset(dev_priv);
Ville Syrjälä8bb61302016-04-12 18:56:44 +03002967}
2968
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002969static void valleyview_irq_preinstall(struct drm_device *dev)
2970{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002971 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002972
Ville Syrjälä34c7b8a2016-04-13 21:19:48 +03002973 I915_WRITE(VLV_MASTER_IER, 0);
2974 POSTING_READ(VLV_MASTER_IER);
2975
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00002976 gen5_gt_irq_reset(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002977
Ville Syrjäläad22d102016-04-12 18:56:14 +03002978 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03002979 if (dev_priv->display_irqs_enabled)
2980 vlv_display_irq_reset(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03002981 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002982}
2983
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02002984static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
2985{
2986 GEN8_IRQ_RESET_NDX(GT, 0);
2987 GEN8_IRQ_RESET_NDX(GT, 1);
2988 GEN8_IRQ_RESET_NDX(GT, 2);
2989 GEN8_IRQ_RESET_NDX(GT, 3);
2990}
2991
Paulo Zanoni823f6b32014-04-01 15:37:26 -03002992static void gen8_irq_reset(struct drm_device *dev)
Ben Widawskyabd58f02013-11-02 21:07:09 -07002993{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002994 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002995 int pipe;
2996
Ben Widawskyabd58f02013-11-02 21:07:09 -07002997 I915_WRITE(GEN8_MASTER_IRQ, 0);
2998 POSTING_READ(GEN8_MASTER_IRQ);
2999
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003000 gen8_gt_irq_reset(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003001
Damien Lespiau055e3932014-08-18 13:49:10 +01003002 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003003 if (intel_display_power_is_enabled(dev_priv,
3004 POWER_DOMAIN_PIPE(pipe)))
Paulo Zanoni813bde42014-07-04 11:50:29 -03003005 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003006
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003007 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3008 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3009 GEN5_IRQ_RESET(GEN8_PCU_);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003010
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003011 if (HAS_PCH_SPLIT(dev_priv))
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00003012 ibx_irq_reset(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003013}
Ben Widawskyabd58f02013-11-02 21:07:09 -07003014
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00003015void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
Imre Deak001bd2c2017-07-12 18:54:13 +03003016 u8 pipe_mask)
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003017{
Paulo Zanoni1180e202014-10-07 18:02:52 -03003018 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
Ville Syrjälä6831f3e2016-02-19 20:47:31 +02003019 enum pipe pipe;
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003020
Daniel Vetter13321782014-09-15 14:55:29 +02003021 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä6831f3e2016-02-19 20:47:31 +02003022 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3023 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3024 dev_priv->de_irq_mask[pipe],
3025 ~dev_priv->de_irq_mask[pipe] | extra_ier);
Daniel Vetter13321782014-09-15 14:55:29 +02003026 spin_unlock_irq(&dev_priv->irq_lock);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003027}
3028
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02003029void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
Imre Deak001bd2c2017-07-12 18:54:13 +03003030 u8 pipe_mask)
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02003031{
Ville Syrjälä6831f3e2016-02-19 20:47:31 +02003032 enum pipe pipe;
3033
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02003034 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä6831f3e2016-02-19 20:47:31 +02003035 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3036 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02003037 spin_unlock_irq(&dev_priv->irq_lock);
3038
3039 /* make sure we're done processing display irqs */
Chris Wilson91c8a322016-07-05 10:40:23 +01003040 synchronize_irq(dev_priv->drm.irq);
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02003041}
3042
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003043static void cherryview_irq_preinstall(struct drm_device *dev)
3044{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003045 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003046
3047 I915_WRITE(GEN8_MASTER_IRQ, 0);
3048 POSTING_READ(GEN8_MASTER_IRQ);
3049
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003050 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003051
3052 GEN5_IRQ_RESET(GEN8_PCU_);
3053
Ville Syrjäläad22d102016-04-12 18:56:14 +03003054 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03003055 if (dev_priv->display_irqs_enabled)
3056 vlv_display_irq_reset(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003057 spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003058}
3059
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003060static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
Ville Syrjälä87a02102015-08-27 23:55:57 +03003061 const u32 hpd[HPD_NUM_PINS])
3062{
Ville Syrjälä87a02102015-08-27 23:55:57 +03003063 struct intel_encoder *encoder;
3064 u32 enabled_irqs = 0;
3065
Chris Wilson91c8a322016-07-05 10:40:23 +01003066 for_each_intel_encoder(&dev_priv->drm, encoder)
Ville Syrjälä87a02102015-08-27 23:55:57 +03003067 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3068 enabled_irqs |= hpd[encoder->hpd_pin];
3069
3070 return enabled_irqs;
3071}
3072
Imre Deak1a56b1a2017-01-27 11:39:21 +02003073static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3074{
3075 u32 hotplug;
3076
3077 /*
3078 * Enable digital hotplug on the PCH, and configure the DP short pulse
3079 * duration to 2ms (which is the minimum in the Display Port spec).
3080 * The pulse duration bits are reserved on LPT+.
3081 */
3082 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3083 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3084 PORTC_PULSE_DURATION_MASK |
3085 PORTD_PULSE_DURATION_MASK);
3086 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3087 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3088 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3089 /*
3090 * When CPU and PCH are on the same package, port A
3091 * HPD must be enabled in both north and south.
3092 */
3093 if (HAS_PCH_LPT_LP(dev_priv))
3094 hotplug |= PORTA_HOTPLUG_ENABLE;
3095 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3096}
3097
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003098static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
Keith Packard7fe0b972011-09-19 13:31:02 -07003099{
Imre Deak1a56b1a2017-01-27 11:39:21 +02003100 u32 hotplug_irqs, enabled_irqs;
Keith Packard7fe0b972011-09-19 13:31:02 -07003101
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003102 if (HAS_PCH_IBX(dev_priv)) {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003103 hotplug_irqs = SDE_HOTPLUG_MASK;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003104 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003105 } else {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003106 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003107 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003108 }
3109
Daniel Vetterfee884e2013-07-04 23:35:21 +02003110 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003111
Imre Deak1a56b1a2017-01-27 11:39:21 +02003112 ibx_hpd_detection_setup(dev_priv);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003113}
Xiong Zhang26951ca2015-08-17 15:55:50 +08003114
Imre Deak2a57d9c2017-01-27 11:39:18 +02003115static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3116{
3117 u32 hotplug;
3118
3119 /* Enable digital hotplug on the PCH */
3120 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3121 hotplug |= PORTA_HOTPLUG_ENABLE |
3122 PORTB_HOTPLUG_ENABLE |
3123 PORTC_HOTPLUG_ENABLE |
3124 PORTD_HOTPLUG_ENABLE;
3125 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3126
3127 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3128 hotplug |= PORTE_HOTPLUG_ENABLE;
3129 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3130}
3131
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003132static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003133{
Imre Deak2a57d9c2017-01-27 11:39:18 +02003134 u32 hotplug_irqs, enabled_irqs;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003135
3136 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003137 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003138
3139 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3140
Imre Deak2a57d9c2017-01-27 11:39:18 +02003141 spt_hpd_detection_setup(dev_priv);
Keith Packard7fe0b972011-09-19 13:31:02 -07003142}
3143
Imre Deak1a56b1a2017-01-27 11:39:21 +02003144static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3145{
3146 u32 hotplug;
3147
3148 /*
3149 * Enable digital hotplug on the CPU, and configure the DP short pulse
3150 * duration to 2ms (which is the minimum in the Display Port spec)
3151 * The pulse duration bits are reserved on HSW+.
3152 */
3153 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3154 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3155 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3156 DIGITAL_PORTA_PULSE_DURATION_2ms;
3157 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3158}
3159
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003160static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003161{
Imre Deak1a56b1a2017-01-27 11:39:21 +02003162 u32 hotplug_irqs, enabled_irqs;
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003163
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003164 if (INTEL_GEN(dev_priv) >= 8) {
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003165 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003166 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003167
3168 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003169 } else if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003170 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003171 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003172
3173 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003174 } else {
3175 hotplug_irqs = DE_DP_A_HOTPLUG;
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003176 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003177
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003178 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3179 }
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003180
Imre Deak1a56b1a2017-01-27 11:39:21 +02003181 ilk_hpd_detection_setup(dev_priv);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003182
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003183 ibx_hpd_irq_setup(dev_priv);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003184}
3185
Imre Deak2a57d9c2017-01-27 11:39:18 +02003186static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3187 u32 enabled_irqs)
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003188{
Imre Deak2a57d9c2017-01-27 11:39:18 +02003189 u32 hotplug;
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003190
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003191 hotplug = I915_READ(PCH_PORT_HOTPLUG);
Imre Deak2a57d9c2017-01-27 11:39:18 +02003192 hotplug |= PORTA_HOTPLUG_ENABLE |
3193 PORTB_HOTPLUG_ENABLE |
3194 PORTC_HOTPLUG_ENABLE;
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05303195
3196 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3197 hotplug, enabled_irqs);
3198 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3199
3200 /*
3201 * For BXT invert bit has to be set based on AOB design
3202 * for HPD detection logic, update it based on VBT fields.
3203 */
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05303204 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3205 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3206 hotplug |= BXT_DDIA_HPD_INVERT;
3207 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3208 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3209 hotplug |= BXT_DDIB_HPD_INVERT;
3210 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3211 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3212 hotplug |= BXT_DDIC_HPD_INVERT;
3213
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003214 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003215}
3216
Imre Deak2a57d9c2017-01-27 11:39:18 +02003217static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3218{
3219 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3220}
3221
3222static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3223{
3224 u32 hotplug_irqs, enabled_irqs;
3225
3226 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3227 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3228
3229 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3230
3231 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3232}
3233
Paulo Zanonid46da432013-02-08 17:35:15 -02003234static void ibx_irq_postinstall(struct drm_device *dev)
3235{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003236 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003237 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02003238
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003239 if (HAS_PCH_NOP(dev_priv))
Daniel Vetter692a04c2013-05-29 21:43:05 +02003240 return;
3241
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003242 if (HAS_PCH_IBX(dev_priv))
Daniel Vetter5c673b62014-03-07 20:34:46 +01003243 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
Paulo Zanoni105b1222014-04-01 15:37:17 -03003244 else
Daniel Vetter5c673b62014-03-07 20:34:46 +01003245 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
Paulo Zanoni86642812013-04-12 17:57:57 -03003246
Ville Syrjäläb51a2842015-09-18 20:03:41 +03003247 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
Paulo Zanonid46da432013-02-08 17:35:15 -02003248 I915_WRITE(SDEIMR, ~mask);
Imre Deak2a57d9c2017-01-27 11:39:18 +02003249
3250 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3251 HAS_PCH_LPT(dev_priv))
Imre Deak1a56b1a2017-01-27 11:39:21 +02003252 ibx_hpd_detection_setup(dev_priv);
Imre Deak2a57d9c2017-01-27 11:39:18 +02003253 else
3254 spt_hpd_detection_setup(dev_priv);
Paulo Zanonid46da432013-02-08 17:35:15 -02003255}
3256
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003257static void gen5_gt_irq_postinstall(struct drm_device *dev)
3258{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003259 struct drm_i915_private *dev_priv = to_i915(dev);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003260 u32 pm_irqs, gt_irqs;
3261
3262 pm_irqs = gt_irqs = 0;
3263
3264 dev_priv->gt_irq_mask = ~0;
Tvrtko Ursulin3c9192b2016-10-13 11:03:05 +01003265 if (HAS_L3_DPF(dev_priv)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003266 /* L3 parity interrupt is always unmasked. */
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01003267 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3268 gt_irqs |= GT_PARITY_ERROR(dev_priv);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003269 }
3270
3271 gt_irqs |= GT_RENDER_USER_INTERRUPT;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003272 if (IS_GEN5(dev_priv)) {
Chris Wilsonf8973c22016-07-01 17:23:21 +01003273 gt_irqs |= ILK_BSD_USER_INTERRUPT;
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003274 } else {
3275 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3276 }
3277
Paulo Zanoni35079892014-04-01 15:37:15 -03003278 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003279
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00003280 if (INTEL_GEN(dev_priv) >= 6) {
Imre Deak78e68d32014-12-15 18:59:27 +02003281 /*
3282 * RPS interrupts will get enabled/disabled on demand when RPS
3283 * itself is enabled/disabled.
3284 */
Akash Goelf4e9af42016-10-12 21:54:30 +05303285 if (HAS_VEBOX(dev_priv)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003286 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
Akash Goelf4e9af42016-10-12 21:54:30 +05303287 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3288 }
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003289
Akash Goelf4e9af42016-10-12 21:54:30 +05303290 dev_priv->pm_imr = 0xffffffff;
3291 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003292 }
3293}
3294
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003295static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003296{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003297 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003298 u32 display_mask, extra_mask;
3299
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00003300 if (INTEL_GEN(dev_priv) >= 7) {
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003301 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3302 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3303 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003304 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003305 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003306 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3307 DE_DP_A_HOTPLUG_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003308 } else {
3309 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3310 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003311 DE_AUX_CHANNEL_A |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003312 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3313 DE_POISON);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003314 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3315 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3316 DE_DP_A_HOTPLUG);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003317 }
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003318
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003319 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003320
Paulo Zanoni0c841212014-04-01 15:37:27 -03003321 I915_WRITE(HWSTAM, 0xeffe);
3322
Paulo Zanoni622364b2014-04-01 15:37:22 -03003323 ibx_irq_pre_postinstall(dev);
3324
Paulo Zanoni35079892014-04-01 15:37:15 -03003325 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003326
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003327 gen5_gt_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003328
Imre Deak1a56b1a2017-01-27 11:39:21 +02003329 ilk_hpd_detection_setup(dev_priv);
3330
Paulo Zanonid46da432013-02-08 17:35:15 -02003331 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07003332
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01003333 if (IS_IRONLAKE_M(dev_priv)) {
Daniel Vetter6005ce42013-06-27 13:44:59 +02003334 /* Enable PCU event interrupts
3335 *
3336 * spinlocking not required here for correctness since interrupt
Daniel Vetter4bc9d432013-06-27 13:44:58 +02003337 * setup is guaranteed to run in single-threaded context. But we
3338 * need it to make the assert_spin_locked happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003339 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02003340 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
Daniel Vetterd6207432014-09-15 14:55:27 +02003341 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003342 }
3343
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003344 return 0;
3345}
3346
Imre Deakf8b79e52014-03-04 19:23:07 +02003347void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3348{
Chris Wilson67520412017-03-02 13:28:01 +00003349 lockdep_assert_held(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003350
3351 if (dev_priv->display_irqs_enabled)
3352 return;
3353
3354 dev_priv->display_irqs_enabled = true;
3355
Ville Syrjäläd6c69802016-04-11 16:56:27 +03003356 if (intel_irqs_enabled(dev_priv)) {
3357 vlv_display_irq_reset(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003358 vlv_display_irq_postinstall(dev_priv);
Ville Syrjäläd6c69802016-04-11 16:56:27 +03003359 }
Imre Deakf8b79e52014-03-04 19:23:07 +02003360}
3361
3362void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3363{
Chris Wilson67520412017-03-02 13:28:01 +00003364 lockdep_assert_held(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003365
3366 if (!dev_priv->display_irqs_enabled)
3367 return;
3368
3369 dev_priv->display_irqs_enabled = false;
3370
Imre Deak950eaba2014-09-08 15:21:09 +03003371 if (intel_irqs_enabled(dev_priv))
Ville Syrjäläad22d102016-04-12 18:56:14 +03003372 vlv_display_irq_reset(dev_priv);
Imre Deakf8b79e52014-03-04 19:23:07 +02003373}
3374
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003375
3376static int valleyview_irq_postinstall(struct drm_device *dev)
3377{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003378 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003379
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003380 gen5_gt_irq_postinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003381
Ville Syrjäläad22d102016-04-12 18:56:14 +03003382 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03003383 if (dev_priv->display_irqs_enabled)
3384 vlv_display_irq_postinstall(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003385 spin_unlock_irq(&dev_priv->irq_lock);
3386
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003387 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Ville Syrjälä34c7b8a2016-04-13 21:19:48 +03003388 POSTING_READ(VLV_MASTER_IER);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003389
3390 return 0;
3391}
3392
Ben Widawskyabd58f02013-11-02 21:07:09 -07003393static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3394{
Ben Widawskyabd58f02013-11-02 21:07:09 -07003395 /* These are interrupts we'll toggle with the ring mask register */
3396 uint32_t gt_interrupts[] = {
3397 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003398 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003399 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3400 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003401 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003402 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3403 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3404 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003405 0,
Oscar Mateo73d477f2014-07-24 17:04:31 +01003406 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3407 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
Ben Widawskyabd58f02013-11-02 21:07:09 -07003408 };
3409
Tvrtko Ursulin98735732016-04-19 16:46:08 +01003410 if (HAS_L3_DPF(dev_priv))
3411 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3412
Akash Goelf4e9af42016-10-12 21:54:30 +05303413 dev_priv->pm_ier = 0x0;
3414 dev_priv->pm_imr = ~dev_priv->pm_ier;
Deepak S9a2d2d82014-08-22 08:32:40 +05303415 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3416 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
Imre Deak78e68d32014-12-15 18:59:27 +02003417 /*
3418 * RPS interrupts will get enabled/disabled on demand when RPS itself
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05303419 * is enabled/disabled. Same wil be the case for GuC interrupts.
Imre Deak78e68d32014-12-15 18:59:27 +02003420 */
Akash Goelf4e9af42016-10-12 21:54:30 +05303421 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
Deepak S9a2d2d82014-08-22 08:32:40 +05303422 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003423}
3424
3425static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3426{
Damien Lespiau770de83d2014-03-20 20:45:01 +00003427 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3428 uint32_t de_pipe_enables;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003429 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3430 u32 de_port_enables;
Ville Syrjälä11825b02016-05-19 12:14:43 +03003431 u32 de_misc_masked = GEN8_DE_MISC_GSE;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003432 enum pipe pipe;
Damien Lespiau770de83d2014-03-20 20:45:01 +00003433
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07003434 if (INTEL_GEN(dev_priv) >= 9) {
Damien Lespiau770de83d2014-03-20 20:45:01 +00003435 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3436 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003437 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3438 GEN9_AUX_CHANNEL_D;
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02003439 if (IS_GEN9_LP(dev_priv))
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003440 de_port_masked |= BXT_DE_PORT_GMBUS;
3441 } else {
Damien Lespiau770de83d2014-03-20 20:45:01 +00003442 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3443 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003444 }
Damien Lespiau770de83d2014-03-20 20:45:01 +00003445
3446 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3447 GEN8_PIPE_FIFO_UNDERRUN;
3448
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003449 de_port_enables = de_port_masked;
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02003450 if (IS_GEN9_LP(dev_priv))
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003451 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3452 else if (IS_BROADWELL(dev_priv))
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003453 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3454
Daniel Vetter13b3a0a2013-11-07 15:31:52 +01003455 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3456 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3457 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003458
Damien Lespiau055e3932014-08-18 13:49:10 +01003459 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003460 if (intel_display_power_is_enabled(dev_priv,
Paulo Zanoni813bde42014-07-04 11:50:29 -03003461 POWER_DOMAIN_PIPE(pipe)))
3462 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3463 dev_priv->de_irq_mask[pipe],
3464 de_pipe_enables);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003465
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003466 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
Ville Syrjälä11825b02016-05-19 12:14:43 +03003467 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
Imre Deak2a57d9c2017-01-27 11:39:18 +02003468
3469 if (IS_GEN9_LP(dev_priv))
3470 bxt_hpd_detection_setup(dev_priv);
Imre Deak1a56b1a2017-01-27 11:39:21 +02003471 else if (IS_BROADWELL(dev_priv))
3472 ilk_hpd_detection_setup(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003473}
3474
3475static int gen8_irq_postinstall(struct drm_device *dev)
3476{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003477 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003478
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003479 if (HAS_PCH_SPLIT(dev_priv))
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303480 ibx_irq_pre_postinstall(dev);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003481
Ben Widawskyabd58f02013-11-02 21:07:09 -07003482 gen8_gt_irq_postinstall(dev_priv);
3483 gen8_de_irq_postinstall(dev_priv);
3484
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003485 if (HAS_PCH_SPLIT(dev_priv))
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303486 ibx_irq_postinstall(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003487
Ville Syrjäläe5328c42016-04-13 21:19:47 +03003488 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003489 POSTING_READ(GEN8_MASTER_IRQ);
3490
3491 return 0;
3492}
3493
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003494static int cherryview_irq_postinstall(struct drm_device *dev)
3495{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003496 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003497
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003498 gen8_gt_irq_postinstall(dev_priv);
3499
Ville Syrjäläad22d102016-04-12 18:56:14 +03003500 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03003501 if (dev_priv->display_irqs_enabled)
3502 vlv_display_irq_postinstall(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003503 spin_unlock_irq(&dev_priv->irq_lock);
3504
Ville Syrjäläe5328c42016-04-13 21:19:47 +03003505 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003506 POSTING_READ(GEN8_MASTER_IRQ);
3507
3508 return 0;
3509}
3510
Ben Widawskyabd58f02013-11-02 21:07:09 -07003511static void gen8_irq_uninstall(struct drm_device *dev)
3512{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003513 struct drm_i915_private *dev_priv = to_i915(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003514
3515 if (!dev_priv)
3516 return;
3517
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003518 gen8_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003519}
3520
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003521static void valleyview_irq_uninstall(struct drm_device *dev)
3522{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003523 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003524
3525 if (!dev_priv)
3526 return;
3527
Imre Deak843d0e72014-04-14 20:24:23 +03003528 I915_WRITE(VLV_MASTER_IER, 0);
Ville Syrjälä34c7b8a2016-04-13 21:19:48 +03003529 POSTING_READ(VLV_MASTER_IER);
Imre Deak843d0e72014-04-14 20:24:23 +03003530
Tvrtko Ursulinb243f532016-11-16 08:55:38 +00003531 gen5_gt_irq_reset(dev_priv);
Ville Syrjälä893fce82014-10-30 19:42:56 +02003532
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003533 I915_WRITE(HWSTAM, 0xffffffff);
Imre Deakf8b79e52014-03-04 19:23:07 +02003534
Ville Syrjäläad22d102016-04-12 18:56:14 +03003535 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03003536 if (dev_priv->display_irqs_enabled)
3537 vlv_display_irq_reset(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003538 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003539}
3540
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003541static void cherryview_irq_uninstall(struct drm_device *dev)
3542{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003543 struct drm_i915_private *dev_priv = to_i915(dev);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003544
3545 if (!dev_priv)
3546 return;
3547
3548 I915_WRITE(GEN8_MASTER_IRQ, 0);
3549 POSTING_READ(GEN8_MASTER_IRQ);
3550
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003551 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003552
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003553 GEN5_IRQ_RESET(GEN8_PCU_);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003554
Ville Syrjäläad22d102016-04-12 18:56:14 +03003555 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä99182712016-04-11 16:56:25 +03003556 if (dev_priv->display_irqs_enabled)
3557 vlv_display_irq_reset(dev_priv);
Ville Syrjäläad22d102016-04-12 18:56:14 +03003558 spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003559}
3560
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003561static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003562{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003563 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes46979952011-04-07 13:53:55 -07003564
3565 if (!dev_priv)
3566 return;
3567
Paulo Zanonibe30b292014-04-01 15:37:25 -03003568 ironlake_irq_reset(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003569}
3570
Chris Wilsonc2798b12012-04-22 21:13:57 +01003571static void i8xx_irq_preinstall(struct drm_device * dev)
3572{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003573 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003574 int pipe;
3575
Damien Lespiau055e3932014-08-18 13:49:10 +01003576 for_each_pipe(dev_priv, pipe)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003577 I915_WRITE(PIPESTAT(pipe), 0);
3578 I915_WRITE16(IMR, 0xffff);
3579 I915_WRITE16(IER, 0x0);
3580 POSTING_READ16(IER);
3581}
3582
3583static int i8xx_irq_postinstall(struct drm_device *dev)
3584{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003585 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003586
Chris Wilsonc2798b12012-04-22 21:13:57 +01003587 I915_WRITE16(EMR,
3588 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3589
3590 /* Unmask the interrupts that we always want on. */
3591 dev_priv->irq_mask =
3592 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3593 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3594 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003595 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003596 I915_WRITE16(IMR, dev_priv->irq_mask);
3597
3598 I915_WRITE16(IER,
3599 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3600 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilsonc2798b12012-04-22 21:13:57 +01003601 I915_USER_INTERRUPT);
3602 POSTING_READ16(IER);
3603
Daniel Vetter379ef822013-10-16 22:55:56 +02003604 /* Interrupt setup is already guaranteed to be single-threaded, this is
3605 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003606 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003607 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3608 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003609 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003610
Chris Wilsonc2798b12012-04-22 21:13:57 +01003611 return 0;
3612}
3613
Daniel Vetter5a21b662016-05-24 17:13:53 +02003614/*
3615 * Returns true when a page flip has completed.
3616 */
Daniel Vetterff1f5252012-10-02 15:10:55 +02003617static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003618{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003619 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003620 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003621 u16 iir, new_iir;
3622 u32 pipe_stats[2];
Chris Wilsonc2798b12012-04-22 21:13:57 +01003623 int pipe;
Imre Deak1f814da2015-12-16 02:52:19 +02003624 irqreturn_t ret;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003625
Imre Deak2dd2a882015-02-24 11:14:30 +02003626 if (!intel_irqs_enabled(dev_priv))
3627 return IRQ_NONE;
3628
Imre Deak1f814da2015-12-16 02:52:19 +02003629 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3630 disable_rpm_wakeref_asserts(dev_priv);
3631
3632 ret = IRQ_NONE;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003633 iir = I915_READ16(IIR);
3634 if (iir == 0)
Imre Deak1f814da2015-12-16 02:52:19 +02003635 goto out;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003636
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003637 while (iir) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003638 /* Can't rely on pipestat interrupt bit in iir as it might
3639 * have been cleared after the pipestat interrupt was received.
3640 * It doesn't set the bit in iir again, but it still produces
3641 * interrupts (for non-MSI).
3642 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003643 spin_lock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003644 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01003645 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003646
Damien Lespiau055e3932014-08-18 13:49:10 +01003647 for_each_pipe(dev_priv, pipe) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003648 i915_reg_t reg = PIPESTAT(pipe);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003649 pipe_stats[pipe] = I915_READ(reg);
3650
3651 /*
3652 * Clear the PIPE*STAT regs before the IIR
3653 */
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003654 if (pipe_stats[pipe] & 0x8000ffff)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003655 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003656 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003657 spin_unlock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003658
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003659 I915_WRITE16(IIR, iir);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003660 new_iir = I915_READ16(IIR); /* Flush posted writes */
3661
Chris Wilsonc2798b12012-04-22 21:13:57 +01003662 if (iir & I915_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05303663 notify_ring(dev_priv->engine[RCS]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003664
Damien Lespiau055e3932014-08-18 13:49:10 +01003665 for_each_pipe(dev_priv, pipe) {
Daniel Vetter5a21b662016-05-24 17:13:53 +02003666 int plane = pipe;
3667 if (HAS_FBC(dev_priv))
3668 plane = !plane;
3669
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003670 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
3671 drm_handle_vblank(&dev_priv->drm, pipe);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003672
Daniel Vetter4356d582013-10-16 22:55:55 +02003673 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003674 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003675
Daniel Vetter1f7247c2014-09-30 10:56:48 +02003676 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3677 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3678 pipe);
Daniel Vetter4356d582013-10-16 22:55:55 +02003679 }
Chris Wilsonc2798b12012-04-22 21:13:57 +01003680
3681 iir = new_iir;
3682 }
Imre Deak1f814da2015-12-16 02:52:19 +02003683 ret = IRQ_HANDLED;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003684
Imre Deak1f814da2015-12-16 02:52:19 +02003685out:
3686 enable_rpm_wakeref_asserts(dev_priv);
3687
3688 return ret;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003689}
3690
3691static void i8xx_irq_uninstall(struct drm_device * dev)
3692{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003693 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003694 int pipe;
3695
Damien Lespiau055e3932014-08-18 13:49:10 +01003696 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003697 /* Clear enable bits; then clear status bits */
3698 I915_WRITE(PIPESTAT(pipe), 0);
3699 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3700 }
3701 I915_WRITE16(IMR, 0xffff);
3702 I915_WRITE16(IER, 0x0);
3703 I915_WRITE16(IIR, I915_READ16(IIR));
3704}
3705
Chris Wilsona266c7d2012-04-24 22:59:44 +01003706static void i915_irq_preinstall(struct drm_device * dev)
3707{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003708 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003709 int pipe;
3710
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00003711 if (I915_HAS_HOTPLUG(dev_priv)) {
Egbert Eich0706f172015-09-23 16:15:27 +02003712 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003713 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3714 }
3715
Chris Wilson00d98eb2012-04-24 22:59:48 +01003716 I915_WRITE16(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01003717 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003718 I915_WRITE(PIPESTAT(pipe), 0);
3719 I915_WRITE(IMR, 0xffffffff);
3720 I915_WRITE(IER, 0x0);
3721 POSTING_READ(IER);
3722}
3723
3724static int i915_irq_postinstall(struct drm_device *dev)
3725{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003726 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson38bde182012-04-24 22:59:50 +01003727 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003728
Chris Wilson38bde182012-04-24 22:59:50 +01003729 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3730
3731 /* Unmask the interrupts that we always want on. */
3732 dev_priv->irq_mask =
3733 ~(I915_ASLE_INTERRUPT |
3734 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3735 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3736 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003737 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilson38bde182012-04-24 22:59:50 +01003738
3739 enable_mask =
3740 I915_ASLE_INTERRUPT |
3741 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3742 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilson38bde182012-04-24 22:59:50 +01003743 I915_USER_INTERRUPT;
3744
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00003745 if (I915_HAS_HOTPLUG(dev_priv)) {
Egbert Eich0706f172015-09-23 16:15:27 +02003746 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003747 POSTING_READ(PORT_HOTPLUG_EN);
3748
Chris Wilsona266c7d2012-04-24 22:59:44 +01003749 /* Enable in IER... */
3750 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3751 /* and unmask in IMR */
3752 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3753 }
3754
Chris Wilsona266c7d2012-04-24 22:59:44 +01003755 I915_WRITE(IMR, dev_priv->irq_mask);
3756 I915_WRITE(IER, enable_mask);
3757 POSTING_READ(IER);
3758
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003759 i915_enable_asle_pipestat(dev_priv);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003760
Daniel Vetter379ef822013-10-16 22:55:56 +02003761 /* Interrupt setup is already guaranteed to be single-threaded, this is
3762 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003763 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003764 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3765 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003766 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003767
Daniel Vetter20afbda2012-12-11 14:05:07 +01003768 return 0;
3769}
3770
Daniel Vetterff1f5252012-10-02 15:10:55 +02003771static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003772{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003773 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003774 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson8291ee92012-04-24 22:59:47 +01003775 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilson38bde182012-04-24 22:59:50 +01003776 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003777
Imre Deak2dd2a882015-02-24 11:14:30 +02003778 if (!intel_irqs_enabled(dev_priv))
3779 return IRQ_NONE;
3780
Imre Deak1f814da2015-12-16 02:52:19 +02003781 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3782 disable_rpm_wakeref_asserts(dev_priv);
3783
Chris Wilsona266c7d2012-04-24 22:59:44 +01003784 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01003785 do {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003786 bool irq_received = (iir) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01003787 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003788
3789 /* Can't rely on pipestat interrupt bit in iir as it might
3790 * have been cleared after the pipestat interrupt was received.
3791 * It doesn't set the bit in iir again, but it still produces
3792 * interrupts (for non-MSI).
3793 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003794 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003795 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01003796 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003797
Damien Lespiau055e3932014-08-18 13:49:10 +01003798 for_each_pipe(dev_priv, pipe) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003799 i915_reg_t reg = PIPESTAT(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003800 pipe_stats[pipe] = I915_READ(reg);
3801
Chris Wilson38bde182012-04-24 22:59:50 +01003802 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003803 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003804 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01003805 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003806 }
3807 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003808 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003809
3810 if (!irq_received)
3811 break;
3812
Chris Wilsona266c7d2012-04-24 22:59:44 +01003813 /* Consume port. Then clear IIR or we'll miss events */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003814 if (I915_HAS_HOTPLUG(dev_priv) &&
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03003815 iir & I915_DISPLAY_PORT_INTERRUPT) {
3816 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3817 if (hotplug_status)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003818 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03003819 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003820
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003821 I915_WRITE(IIR, iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003822 new_iir = I915_READ(IIR); /* Flush posted writes */
3823
Chris Wilsona266c7d2012-04-24 22:59:44 +01003824 if (iir & I915_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05303825 notify_ring(dev_priv->engine[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003826
Damien Lespiau055e3932014-08-18 13:49:10 +01003827 for_each_pipe(dev_priv, pipe) {
Daniel Vetter5a21b662016-05-24 17:13:53 +02003828 int plane = pipe;
3829 if (HAS_FBC(dev_priv))
3830 plane = !plane;
3831
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003832 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
3833 drm_handle_vblank(&dev_priv->drm, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003834
3835 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3836 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02003837
3838 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003839 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003840
Daniel Vetter1f7247c2014-09-30 10:56:48 +02003841 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3842 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3843 pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003844 }
3845
Chris Wilsona266c7d2012-04-24 22:59:44 +01003846 if (blc_event || (iir & I915_ASLE_INTERRUPT))
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003847 intel_opregion_asle_intr(dev_priv);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003848
3849 /* With MSI, interrupts are only generated when iir
3850 * transitions from zero to nonzero. If another bit got
3851 * set while we were handling the existing iir bits, then
3852 * we would never get another interrupt.
3853 *
3854 * This is fine on non-MSI as well, as if we hit this path
3855 * we avoid exiting the interrupt handler only to generate
3856 * another one.
3857 *
3858 * Note that for MSI this could cause a stray interrupt report
3859 * if an interrupt landed in the time between writing IIR and
3860 * the posting read. This should be rare enough to never
3861 * trigger the 99% of 100,000 interrupts test for disabling
3862 * stray interrupts.
3863 */
Chris Wilson38bde182012-04-24 22:59:50 +01003864 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003865 iir = new_iir;
Daniel Vetterfd3a4022017-07-20 19:57:51 +02003866 } while (iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003867
Imre Deak1f814da2015-12-16 02:52:19 +02003868 enable_rpm_wakeref_asserts(dev_priv);
3869
Chris Wilsona266c7d2012-04-24 22:59:44 +01003870 return ret;
3871}
3872
3873static void i915_irq_uninstall(struct drm_device * dev)
3874{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003875 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003876 int pipe;
3877
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00003878 if (I915_HAS_HOTPLUG(dev_priv)) {
Egbert Eich0706f172015-09-23 16:15:27 +02003879 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003880 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3881 }
3882
Chris Wilson00d98eb2012-04-24 22:59:48 +01003883 I915_WRITE16(HWSTAM, 0xffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01003884 for_each_pipe(dev_priv, pipe) {
Chris Wilson55b39752012-04-24 22:59:49 +01003885 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003886 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01003887 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3888 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003889 I915_WRITE(IMR, 0xffffffff);
3890 I915_WRITE(IER, 0x0);
3891
Chris Wilsona266c7d2012-04-24 22:59:44 +01003892 I915_WRITE(IIR, I915_READ(IIR));
3893}
3894
3895static void i965_irq_preinstall(struct drm_device * dev)
3896{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003897 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003898 int pipe;
3899
Egbert Eich0706f172015-09-23 16:15:27 +02003900 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsonadca4732012-05-11 18:01:31 +01003901 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01003902
3903 I915_WRITE(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01003904 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003905 I915_WRITE(PIPESTAT(pipe), 0);
3906 I915_WRITE(IMR, 0xffffffff);
3907 I915_WRITE(IER, 0x0);
3908 POSTING_READ(IER);
3909}
3910
3911static int i965_irq_postinstall(struct drm_device *dev)
3912{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003913 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003914 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003915 u32 error_mask;
3916
Chris Wilsona266c7d2012-04-24 22:59:44 +01003917 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003918 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01003919 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003920 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3921 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3922 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3923 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3924 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3925
3926 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003927 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3928 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003929 enable_mask |= I915_USER_INTERRUPT;
3930
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003931 if (IS_G4X(dev_priv))
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003932 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003933
Daniel Vetterb79480b2013-06-27 17:52:10 +02003934 /* Interrupt setup is already guaranteed to be single-threaded, this is
3935 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003936 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003937 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3938 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3939 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003940 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003941
Chris Wilsona266c7d2012-04-24 22:59:44 +01003942 /*
3943 * Enable some error detection, note the instruction error mask
3944 * bit is reserved, so we leave it masked.
3945 */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003946 if (IS_G4X(dev_priv)) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003947 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3948 GM45_ERROR_MEM_PRIV |
3949 GM45_ERROR_CP_PRIV |
3950 I915_ERROR_MEMORY_REFRESH);
3951 } else {
3952 error_mask = ~(I915_ERROR_PAGE_TABLE |
3953 I915_ERROR_MEMORY_REFRESH);
3954 }
3955 I915_WRITE(EMR, error_mask);
3956
3957 I915_WRITE(IMR, dev_priv->irq_mask);
3958 I915_WRITE(IER, enable_mask);
3959 POSTING_READ(IER);
3960
Egbert Eich0706f172015-09-23 16:15:27 +02003961 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003962 POSTING_READ(PORT_HOTPLUG_EN);
3963
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003964 i915_enable_asle_pipestat(dev_priv);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003965
3966 return 0;
3967}
3968
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003969static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
Daniel Vetter20afbda2012-12-11 14:05:07 +01003970{
Daniel Vetter20afbda2012-12-11 14:05:07 +01003971 u32 hotplug_en;
3972
Chris Wilson67520412017-03-02 13:28:01 +00003973 lockdep_assert_held(&dev_priv->irq_lock);
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02003974
Ville Syrjälä778eb332015-01-09 14:21:13 +02003975 /* Note HDMI and DP share hotplug bits */
3976 /* enable bits are the same for all generations */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003977 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
Ville Syrjälä778eb332015-01-09 14:21:13 +02003978 /* Programming the CRT detection parameters tends
3979 to generate a spurious hotplug event about three
3980 seconds later. So just do it once.
3981 */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003982 if (IS_G4X(dev_priv))
Ville Syrjälä778eb332015-01-09 14:21:13 +02003983 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Ville Syrjälä778eb332015-01-09 14:21:13 +02003984 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003985
Ville Syrjälä778eb332015-01-09 14:21:13 +02003986 /* Ignore TV since it's buggy */
Egbert Eich0706f172015-09-23 16:15:27 +02003987 i915_hotplug_interrupt_update_locked(dev_priv,
Jani Nikulaf9e3dc72015-10-21 17:22:43 +03003988 HOTPLUG_INT_EN_MASK |
3989 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
3990 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
3991 hotplug_en);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003992}
3993
Daniel Vetterff1f5252012-10-02 15:10:55 +02003994static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003995{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003996 struct drm_device *dev = arg;
Chris Wilsonfac5e232016-07-04 11:34:36 +01003997 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003998 u32 iir, new_iir;
3999 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01004000 int ret = IRQ_NONE, pipe;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004001
Imre Deak2dd2a882015-02-24 11:14:30 +02004002 if (!intel_irqs_enabled(dev_priv))
4003 return IRQ_NONE;
4004
Imre Deak1f814da2015-12-16 02:52:19 +02004005 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4006 disable_rpm_wakeref_asserts(dev_priv);
4007
Chris Wilsona266c7d2012-04-24 22:59:44 +01004008 iir = I915_READ(IIR);
4009
Chris Wilsona266c7d2012-04-24 22:59:44 +01004010 for (;;) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02004011 bool irq_received = (iir) != 0;
Chris Wilson2c8ba292012-04-24 22:59:46 +01004012 bool blc_event = false;
4013
Chris Wilsona266c7d2012-04-24 22:59:44 +01004014 /* Can't rely on pipestat interrupt bit in iir as it might
4015 * have been cleared after the pipestat interrupt was received.
4016 * It doesn't set the bit in iir again, but it still produces
4017 * interrupts (for non-MSI).
4018 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02004019 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004020 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01004021 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004022
Damien Lespiau055e3932014-08-18 13:49:10 +01004023 for_each_pipe(dev_priv, pipe) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004024 i915_reg_t reg = PIPESTAT(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004025 pipe_stats[pipe] = I915_READ(reg);
4026
4027 /*
4028 * Clear the PIPE*STAT regs before the IIR
4029 */
4030 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004031 I915_WRITE(reg, pipe_stats[pipe]);
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004032 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004033 }
4034 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02004035 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004036
4037 if (!irq_received)
4038 break;
4039
4040 ret = IRQ_HANDLED;
4041
4042 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03004043 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4044 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4045 if (hotplug_status)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004046 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
Ville Syrjälä1ae3c342016-04-13 21:19:54 +03004047 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004048
Daniel Vetterfd3a4022017-07-20 19:57:51 +02004049 I915_WRITE(IIR, iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004050 new_iir = I915_READ(IIR); /* Flush posted writes */
4051
Chris Wilsona266c7d2012-04-24 22:59:44 +01004052 if (iir & I915_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05304053 notify_ring(dev_priv->engine[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004054 if (iir & I915_BSD_USER_INTERRUPT)
Akash Goel3b3f1652016-10-13 22:44:48 +05304055 notify_ring(dev_priv->engine[VCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004056
Damien Lespiau055e3932014-08-18 13:49:10 +01004057 for_each_pipe(dev_priv, pipe) {
Daniel Vetterfd3a4022017-07-20 19:57:51 +02004058 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
4059 drm_handle_vblank(&dev_priv->drm, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004060
4061 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4062 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004063
4064 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004065 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004066
Daniel Vetter1f7247c2014-09-30 10:56:48 +02004067 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4068 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004069 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004070
4071 if (blc_event || (iir & I915_ASLE_INTERRUPT))
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004072 intel_opregion_asle_intr(dev_priv);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004073
Daniel Vetter515ac2b2012-12-01 13:53:44 +01004074 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01004075 gmbus_irq_handler(dev_priv);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01004076
Chris Wilsona266c7d2012-04-24 22:59:44 +01004077 /* With MSI, interrupts are only generated when iir
4078 * transitions from zero to nonzero. If another bit got
4079 * set while we were handling the existing iir bits, then
4080 * we would never get another interrupt.
4081 *
4082 * This is fine on non-MSI as well, as if we hit this path
4083 * we avoid exiting the interrupt handler only to generate
4084 * another one.
4085 *
4086 * Note that for MSI this could cause a stray interrupt report
4087 * if an interrupt landed in the time between writing IIR and
4088 * the posting read. This should be rare enough to never
4089 * trigger the 99% of 100,000 interrupts test for disabling
4090 * stray interrupts.
4091 */
4092 iir = new_iir;
4093 }
4094
Imre Deak1f814da2015-12-16 02:52:19 +02004095 enable_rpm_wakeref_asserts(dev_priv);
4096
Chris Wilsona266c7d2012-04-24 22:59:44 +01004097 return ret;
4098}
4099
4100static void i965_irq_uninstall(struct drm_device * dev)
4101{
Chris Wilsonfac5e232016-07-04 11:34:36 +01004102 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004103 int pipe;
4104
4105 if (!dev_priv)
4106 return;
4107
Egbert Eich0706f172015-09-23 16:15:27 +02004108 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsonadca4732012-05-11 18:01:31 +01004109 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004110
4111 I915_WRITE(HWSTAM, 0xffffffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004112 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004113 I915_WRITE(PIPESTAT(pipe), 0);
4114 I915_WRITE(IMR, 0xffffffff);
4115 I915_WRITE(IER, 0x0);
4116
Damien Lespiau055e3932014-08-18 13:49:10 +01004117 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004118 I915_WRITE(PIPESTAT(pipe),
4119 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4120 I915_WRITE(IIR, I915_READ(IIR));
4121}
4122
Daniel Vetterfca52a52014-09-30 10:56:45 +02004123/**
4124 * intel_irq_init - initializes irq support
4125 * @dev_priv: i915 device instance
4126 *
4127 * This function initializes all the irq support including work items, timers
4128 * and all the vtables. It does not setup the interrupt itself though.
4129 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004130void intel_irq_init(struct drm_i915_private *dev_priv)
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004131{
Chris Wilson91c8a322016-07-05 10:40:23 +01004132 struct drm_device *dev = &dev_priv->drm;
Joonas Lahtinencefcff82017-04-28 10:58:39 +03004133 int i;
Chris Wilson8b2e3262012-04-24 22:59:41 +01004134
Jani Nikula77913b32015-06-18 13:06:16 +03004135 intel_hpd_init_work(dev_priv);
4136
Daniel Vetterc6a828d2012-08-08 23:35:35 +02004137 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Joonas Lahtinencefcff82017-04-28 10:58:39 +03004138
Daniel Vettera4da4fa2012-11-02 19:55:07 +01004139 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Joonas Lahtinencefcff82017-04-28 10:58:39 +03004140 for (i = 0; i < MAX_L3_SLICES; ++i)
4141 dev_priv->l3_parity.remap_info[i] = NULL;
Chris Wilson8b2e3262012-04-24 22:59:41 +01004142
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00004143 if (HAS_GUC_SCHED(dev_priv))
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05304144 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4145
Deepak Sa6706b42014-03-15 20:23:22 +05304146 /* Let's track the enabled rps events */
Wayne Boyer666a4532015-12-09 12:29:35 -08004147 if (IS_VALLEYVIEW(dev_priv))
Ville Syrjälä6c65a5872014-08-29 14:14:07 +03004148 /* WaGsvRC0ResidencyMethod:vlv */
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00004149 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
Deepak S31685c22014-07-03 17:33:01 -04004150 else
4151 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
Deepak Sa6706b42014-03-15 20:23:22 +05304152
Sagar Arun Kamble5dd04552017-03-11 08:07:00 +05304153 dev_priv->rps.pm_intrmsk_mbz = 0;
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05304154
4155 /*
Mika Kuoppalaacf2dc22017-04-13 14:15:27 +03004156 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05304157 * if GEN6_PM_UP_EI_EXPIRED is masked.
4158 *
4159 * TODO: verify if this can be reproduced on VLV,CHV.
4160 */
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07004161 if (INTEL_GEN(dev_priv) <= 7)
Sagar Arun Kamble5dd04552017-03-11 08:07:00 +05304162 dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05304163
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07004164 if (INTEL_GEN(dev_priv) >= 8)
Chris Wilson655d49e2017-03-12 13:27:45 +00004165 dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05304166
Daniel Vetterb9632912014-09-30 10:56:44 +02004167 if (IS_GEN2(dev_priv)) {
Rodrigo Vivi4194c082016-08-03 10:00:56 -07004168 /* Gen2 doesn't have a hardware frame counter */
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +03004169 dev->max_vblank_count = 0;
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07004170 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004171 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
Ville Syrjäläfd8f507c2015-09-18 20:03:42 +03004172 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
Ville Syrjälä391f75e2013-09-25 19:55:26 +03004173 } else {
4174 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4175 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004176 }
4177
Ville Syrjälä21da2702014-08-06 14:49:55 +03004178 /*
4179 * Opt out of the vblank disable timer on everything except gen2.
4180 * Gen2 doesn't have a hardware frame counter and so depends on
4181 * vblank interrupts to produce sane vblank seuquence numbers.
4182 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004183 if (!IS_GEN2(dev_priv))
Ville Syrjälä21da2702014-08-06 14:49:55 +03004184 dev->vblank_disable_immediate = true;
4185
Chris Wilson262fd482017-02-15 13:15:47 +00004186 /* Most platforms treat the display irq block as an always-on
4187 * power domain. vlv/chv can disable it at runtime and need
4188 * special care to avoid writing any of the display block registers
4189 * outside of the power domain. We defer setting up the display irqs
4190 * in this case to the runtime pm.
4191 */
4192 dev_priv->display_irqs_enabled = true;
4193 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4194 dev_priv->display_irqs_enabled = false;
4195
Lyude317eaa92017-02-03 21:18:25 -05004196 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4197
Daniel Vetter1bf6ad62017-05-09 16:03:28 +02004198 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +01004199 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004200
Daniel Vetterb9632912014-09-30 10:56:44 +02004201 if (IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä43f328d2014-04-09 20:40:52 +03004202 dev->driver->irq_handler = cherryview_irq_handler;
4203 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4204 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4205 dev->driver->irq_uninstall = cherryview_irq_uninstall;
Chris Wilson86e83e32016-10-07 20:49:52 +01004206 dev->driver->enable_vblank = i965_enable_vblank;
4207 dev->driver->disable_vblank = i965_disable_vblank;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03004208 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004209 } else if (IS_VALLEYVIEW(dev_priv)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07004210 dev->driver->irq_handler = valleyview_irq_handler;
4211 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4212 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4213 dev->driver->irq_uninstall = valleyview_irq_uninstall;
Chris Wilson86e83e32016-10-07 20:49:52 +01004214 dev->driver->enable_vblank = i965_enable_vblank;
4215 dev->driver->disable_vblank = i965_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05004216 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Pandiyan, Dhinakaranbca2bf22017-07-18 11:28:00 -07004217 } else if (INTEL_GEN(dev_priv) >= 8) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07004218 dev->driver->irq_handler = gen8_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004219 dev->driver->irq_preinstall = gen8_irq_reset;
Ben Widawskyabd58f02013-11-02 21:07:09 -07004220 dev->driver->irq_postinstall = gen8_irq_postinstall;
4221 dev->driver->irq_uninstall = gen8_irq_uninstall;
4222 dev->driver->enable_vblank = gen8_enable_vblank;
4223 dev->driver->disable_vblank = gen8_disable_vblank;
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02004224 if (IS_GEN9_LP(dev_priv))
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02004225 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
Rodrigo Vivi7b22b8c2017-06-02 13:06:39 -07004226 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
4227 HAS_PCH_CNP(dev_priv))
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03004228 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4229 else
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03004230 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01004231 } else if (HAS_PCH_SPLIT(dev_priv)) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004232 dev->driver->irq_handler = ironlake_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004233 dev->driver->irq_preinstall = ironlake_irq_reset;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004234 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4235 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4236 dev->driver->enable_vblank = ironlake_enable_vblank;
4237 dev->driver->disable_vblank = ironlake_disable_vblank;
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03004238 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004239 } else {
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01004240 if (IS_GEN2(dev_priv)) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01004241 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4242 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4243 dev->driver->irq_handler = i8xx_irq_handler;
4244 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Chris Wilson86e83e32016-10-07 20:49:52 +01004245 dev->driver->enable_vblank = i8xx_enable_vblank;
4246 dev->driver->disable_vblank = i8xx_disable_vblank;
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01004247 } else if (IS_GEN3(dev_priv)) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004248 dev->driver->irq_preinstall = i915_irq_preinstall;
4249 dev->driver->irq_postinstall = i915_irq_postinstall;
4250 dev->driver->irq_uninstall = i915_irq_uninstall;
4251 dev->driver->irq_handler = i915_irq_handler;
Chris Wilson86e83e32016-10-07 20:49:52 +01004252 dev->driver->enable_vblank = i8xx_enable_vblank;
4253 dev->driver->disable_vblank = i8xx_disable_vblank;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004254 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004255 dev->driver->irq_preinstall = i965_irq_preinstall;
4256 dev->driver->irq_postinstall = i965_irq_postinstall;
4257 dev->driver->irq_uninstall = i965_irq_uninstall;
4258 dev->driver->irq_handler = i965_irq_handler;
Chris Wilson86e83e32016-10-07 20:49:52 +01004259 dev->driver->enable_vblank = i965_enable_vblank;
4260 dev->driver->disable_vblank = i965_disable_vblank;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004261 }
Ville Syrjälä778eb332015-01-09 14:21:13 +02004262 if (I915_HAS_HOTPLUG(dev_priv))
4263 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004264 }
4265}
Daniel Vetter20afbda2012-12-11 14:05:07 +01004266
Daniel Vetterfca52a52014-09-30 10:56:45 +02004267/**
Joonas Lahtinencefcff82017-04-28 10:58:39 +03004268 * intel_irq_fini - deinitializes IRQ support
4269 * @i915: i915 device instance
4270 *
4271 * This function deinitializes all the IRQ support.
4272 */
4273void intel_irq_fini(struct drm_i915_private *i915)
4274{
4275 int i;
4276
4277 for (i = 0; i < MAX_L3_SLICES; ++i)
4278 kfree(i915->l3_parity.remap_info[i]);
4279}
4280
4281/**
Daniel Vetterfca52a52014-09-30 10:56:45 +02004282 * intel_irq_install - enables the hardware interrupt
4283 * @dev_priv: i915 device instance
4284 *
4285 * This function enables the hardware interrupt handling, but leaves the hotplug
4286 * handling still disabled. It is called after intel_irq_init().
4287 *
4288 * In the driver load and resume code we need working interrupts in a few places
4289 * but don't want to deal with the hassle of concurrent probe and hotplug
4290 * workers. Hence the split into this two-stage approach.
4291 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004292int intel_irq_install(struct drm_i915_private *dev_priv)
4293{
4294 /*
4295 * We enable some interrupt sources in our postinstall hooks, so mark
4296 * interrupts as enabled _before_ actually enabling them to avoid
4297 * special cases in our ordering checks.
4298 */
4299 dev_priv->pm.irqs_enabled = true;
4300
Chris Wilson91c8a322016-07-05 10:40:23 +01004301 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004302}
4303
Daniel Vetterfca52a52014-09-30 10:56:45 +02004304/**
4305 * intel_irq_uninstall - finilizes all irq handling
4306 * @dev_priv: i915 device instance
4307 *
4308 * This stops interrupt and hotplug handling and unregisters and frees all
4309 * resources acquired in the init functions.
4310 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004311void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4312{
Chris Wilson91c8a322016-07-05 10:40:23 +01004313 drm_irq_uninstall(&dev_priv->drm);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004314 intel_hpd_cancel_work(dev_priv);
4315 dev_priv->pm.irqs_enabled = false;
4316}
4317
Daniel Vetterfca52a52014-09-30 10:56:45 +02004318/**
4319 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4320 * @dev_priv: i915 device instance
4321 *
4322 * This function is used to disable interrupts at runtime, both in the runtime
4323 * pm and the system suspend/resume code.
4324 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004325void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004326{
Chris Wilson91c8a322016-07-05 10:40:23 +01004327 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004328 dev_priv->pm.irqs_enabled = false;
Chris Wilson91c8a322016-07-05 10:40:23 +01004329 synchronize_irq(dev_priv->drm.irq);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004330}
4331
Daniel Vetterfca52a52014-09-30 10:56:45 +02004332/**
4333 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4334 * @dev_priv: i915 device instance
4335 *
4336 * This function is used to enable interrupts at runtime, both in the runtime
4337 * pm and the system suspend/resume code.
4338 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004339void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004340{
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004341 dev_priv->pm.irqs_enabled = true;
Chris Wilson91c8a322016-07-05 10:40:23 +01004342 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4343 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004344}