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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7b1f2485db253aaa0081e1c5213533e166130732 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 4f8447557298ae3241716f03f4d94d6486965b7e [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]46 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]47 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]60void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]61bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]62int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]66void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]67void r100_ring_start(struct radeon_device *rdev);
68int r100_irq_set(struct radeon_device *rdev);
69int r100_irq_process(struct radeon_device *rdev);
70void r100_fence_ring_emit(struct radeon_device *rdev,
71 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]72void r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]73 struct radeon_cp *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]74 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]75 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]76int r100_cs_parse(struct radeon_cs_parser *p);
77void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
78uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
79int r100_copy_blit(struct radeon_device *rdev,
80 uint64_t src_offset,
81 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]82 unsigned num_gpu_pages,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]83 struct radeon_fence *fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]84int r100_set_surface_reg(struct radeon_device *rdev, int reg,
85 uint32_t tiling_flags, uint32_t pitch,
86 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]87void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]88void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]89void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]90int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]91void r100_hpd_init(struct radeon_device *rdev);
92void r100_hpd_fini(struct radeon_device *rdev);
93bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
94void r100_hpd_set_polarity(struct radeon_device *rdev,
95 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]96int r100_debugfs_rbbm_init(struct radeon_device *rdev);
97int r100_debugfs_cp_init(struct radeon_device *rdev);
98void r100_cp_disable(struct radeon_device *rdev);
99int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
100void r100_cp_fini(struct radeon_device *rdev);
101int r100_pci_gart_init(struct radeon_device *rdev);
102void r100_pci_gart_fini(struct radeon_device *rdev);
103int r100_pci_gart_enable(struct radeon_device *rdev);
104void r100_pci_gart_disable(struct radeon_device *rdev);
105int r100_debugfs_mc_info_init(struct radeon_device *rdev);
106int r100_gui_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]107void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup,
108 struct radeon_cp *cp);
109bool r100_gpu_cp_is_lockup(struct radeon_device *rdev,
110 struct r100_gpu_lockup *lockup,
111 struct radeon_cp *cp);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]112void r100_ib_fini(struct radeon_device *rdev);
113int r100_ib_init(struct radeon_device *rdev);
114void r100_irq_disable(struct radeon_device *rdev);
115void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
116void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
117void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]118int r100_cp_reset(struct radeon_device *rdev);
119void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]120void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]121int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
122 struct radeon_cs_packet *pkt,
123 struct radeon_bo *robj);
124int r100_cs_parse_packet0(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 const unsigned *auth, unsigned n,
127 radeon_packet0_check_t check);
128int r100_cs_packet_parse(struct radeon_cs_parser *p,
129 struct radeon_cs_packet *pkt,
130 unsigned idx);
131void r100_enable_bm(struct radeon_device *rdev);
132void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]133void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]134extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]135extern void r100_pm_misc(struct radeon_device *rdev);
136extern void r100_pm_prepare(struct radeon_device *rdev);
137extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]138extern void r100_pm_init_profile(struct radeon_device *rdev);
139extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]140extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
141extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
142extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]143
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]144/*
145 * r200,rv250,rs300,rv280
146 */
147extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]148 uint64_t src_offset,
149 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]150 unsigned num_gpu_pages,
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]151 struct radeon_fence *fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]152void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]153
154/*
155 * r300,r350,rv350,rv380
156 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]157extern int r300_init(struct radeon_device *rdev);
158extern void r300_fini(struct radeon_device *rdev);
159extern int r300_suspend(struct radeon_device *rdev);
160extern int r300_resume(struct radeon_device *rdev);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]161extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]162extern int r300_asic_reset(struct radeon_device *rdev);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]163extern void r300_ring_start(struct radeon_device *rdev);
164extern void r300_fence_ring_emit(struct radeon_device *rdev,
165 struct radeon_fence *fence);
166extern int r300_cs_parse(struct radeon_cs_parser *p);
167extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
168extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]169extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]170extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]171extern void r300_set_reg_safe(struct radeon_device *rdev);
172extern void r300_mc_program(struct radeon_device *rdev);
173extern void r300_mc_init(struct radeon_device *rdev);
174extern void r300_clock_startup(struct radeon_device *rdev);
175extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
176extern int rv370_pcie_gart_init(struct radeon_device *rdev);
177extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
178extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
179extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]180
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]181/*
182 * r420,r423,rv410
183 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]184extern int r420_init(struct radeon_device *rdev);
185extern void r420_fini(struct radeon_device *rdev);
186extern int r420_suspend(struct radeon_device *rdev);
187extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]188extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]189extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
190extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
191extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
192extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]193
194/*
195 * rs400,rs480
196 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]197extern int rs400_init(struct radeon_device *rdev);
198extern void rs400_fini(struct radeon_device *rdev);
199extern int rs400_suspend(struct radeon_device *rdev);
200extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]201void rs400_gart_tlb_flush(struct radeon_device *rdev);
202int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
203uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
204void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]205int rs400_gart_init(struct radeon_device *rdev);
206int rs400_gart_enable(struct radeon_device *rdev);
207void rs400_gart_adjust_size(struct radeon_device *rdev);
208void rs400_gart_disable(struct radeon_device *rdev);
209void rs400_gart_fini(struct radeon_device *rdev);
210
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]211/*
212 * rs600.
213 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]214extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]215extern int rs600_init(struct radeon_device *rdev);
216extern void rs600_fini(struct radeon_device *rdev);
217extern int rs600_suspend(struct radeon_device *rdev);
218extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]220int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]221void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]222u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]223void rs600_gart_tlb_flush(struct radeon_device *rdev);
224int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
225uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
226void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]227void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]228void rs600_hpd_init(struct radeon_device *rdev);
229void rs600_hpd_fini(struct radeon_device *rdev);
230bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
231void rs600_hpd_set_polarity(struct radeon_device *rdev,
232 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]233extern void rs600_pm_misc(struct radeon_device *rdev);
234extern void rs600_pm_prepare(struct radeon_device *rdev);
235extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]236extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
237extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
238extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]239void rs600_set_safe_registers(struct radeon_device *rdev);
240
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]241
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]242/*
243 * rs690,rs740
244 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]245int rs690_init(struct radeon_device *rdev);
246void rs690_fini(struct radeon_device *rdev);
247int rs690_resume(struct radeon_device *rdev);
248int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]249uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
250void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]251void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]252void rs690_line_buffer_adjust(struct radeon_device *rdev,
253 struct drm_display_mode *mode1,
254 struct drm_display_mode *mode2);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]255
256/*
257 * rv515
258 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]259struct rv515_mc_save {
260 u32 d1vga_control;
261 u32 d2vga_control;
262 u32 vga_render_control;
263 u32 vga_hdp_control;
264 u32 d1crtc_control;
265 u32 d2crtc_control;
266};
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]267int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]268void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]269uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
270void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
271void rv515_ring_start(struct radeon_device *rdev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]272void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]273int rv515_resume(struct radeon_device *rdev);
274int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]275void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
276void rv515_vga_render_disable(struct radeon_device *rdev);
277void rv515_set_safe_registers(struct radeon_device *rdev);
278void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
279void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
280void rv515_clock_startup(struct radeon_device *rdev);
281void rv515_debugfs(struct radeon_device *rdev);
282
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]283
284/*
285 * r520,rv530,rv560,rv570,r580
286 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]287int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]288int r520_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]289
290/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]291 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]292 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]293int r600_init(struct radeon_device *rdev);
294void r600_fini(struct radeon_device *rdev);
295int r600_suspend(struct radeon_device *rdev);
296int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]297void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]298int r600_wb_init(struct radeon_device *rdev);
299void r600_wb_fini(struct radeon_device *rdev);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]300void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]301void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]302uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
303void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]304int r600_cs_parse(struct radeon_cs_parser *p);
305void r600_fence_ring_emit(struct radeon_device *rdev,
306 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]307void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]308 struct radeon_cp *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]309 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]310 bool emit_wait);
311bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]312int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]313int r600_set_surface_reg(struct radeon_device *rdev, int reg,
314 uint32_t tiling_flags, uint32_t pitch,
315 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]316void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]317int r600_ib_test(struct radeon_device *rdev, int ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]318void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]319int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]320int r600_copy_blit(struct radeon_device *rdev,
321 uint64_t src_offset, uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]322 unsigned num_gpu_pages, struct radeon_fence *fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]323void r600_hpd_init(struct radeon_device *rdev);
324void r600_hpd_fini(struct radeon_device *rdev);
325bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
326void r600_hpd_set_polarity(struct radeon_device *rdev,
327 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]328extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]329extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]330extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]331extern void r600_pm_init_profile(struct radeon_device *rdev);
332extern void rs780_pm_init_profile(struct radeon_device *rdev);
333extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]334extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
335extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]336bool r600_card_posted(struct radeon_device *rdev);
337void r600_cp_stop(struct radeon_device *rdev);
338int r600_cp_start(struct radeon_device *rdev);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]339void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]340int r600_cp_resume(struct radeon_device *rdev);
341void r600_cp_fini(struct radeon_device *rdev);
342int r600_count_pipe_bits(uint32_t val);
343int r600_mc_wait_for_idle(struct radeon_device *rdev);
344int r600_pcie_gart_init(struct radeon_device *rdev);
345void r600_scratch_init(struct radeon_device *rdev);
346int r600_blit_init(struct radeon_device *rdev);
347void r600_blit_fini(struct radeon_device *rdev);
348int r600_init_microcode(struct radeon_device *rdev);
349/* r600 irq */
350int r600_irq_process(struct radeon_device *rdev);
351int r600_irq_init(struct radeon_device *rdev);
352void r600_irq_fini(struct radeon_device *rdev);
353void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
354int r600_irq_set(struct radeon_device *rdev);
355void r600_irq_suspend(struct radeon_device *rdev);
356void r600_disable_interrupts(struct radeon_device *rdev);
357void r600_rlc_stop(struct radeon_device *rdev);
358/* r600 audio */
359int r600_audio_init(struct radeon_device *rdev);
360int r600_audio_tmds_index(struct drm_encoder *encoder);
361void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
362int r600_audio_channels(struct radeon_device *rdev);
363int r600_audio_bits_per_sample(struct radeon_device *rdev);
364int r600_audio_rate(struct radeon_device *rdev);
365uint8_t r600_audio_status_bits(struct radeon_device *rdev);
366uint8_t r600_audio_category_code(struct radeon_device *rdev);
367void r600_audio_schedule_polling(struct radeon_device *rdev);
368void r600_audio_enable_polling(struct drm_encoder *encoder);
369void r600_audio_disable_polling(struct drm_encoder *encoder);
370void r600_audio_fini(struct radeon_device *rdev);
371void r600_hdmi_init(struct drm_encoder *encoder);
372int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
373void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]374/* r600 blit */
Ilija Hadzicb3530962011-10-12 23:29:42 -0400[diff] [blame]375int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]376void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
377void r600_kms_blit_copy(struct radeon_device *rdev,
378 u64 src_gpu_addr, u64 dst_gpu_addr,
Ilija Hadzicb3530962011-10-12 23:29:42 -0400[diff] [blame]379 unsigned num_gpu_pages);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]380
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]381/*
382 * rv770,rv730,rv710,rv740
383 */
384int rv770_init(struct radeon_device *rdev);
385void rv770_fini(struct radeon_device *rdev);
386int rv770_suspend(struct radeon_device *rdev);
387int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]388void rv770_pm_misc(struct radeon_device *rdev);
389u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
390void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
391void r700_cp_stop(struct radeon_device *rdev);
392void r700_cp_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]393
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]394/*
395 * evergreen
396 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]397struct evergreen_mc_save {
398 u32 vga_control[6];
399 u32 vga_render_control;
400 u32 vga_hdp_control;
401 u32 crtc_control[6];
402};
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]403void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]404int evergreen_init(struct radeon_device *rdev);
405void evergreen_fini(struct radeon_device *rdev);
406int evergreen_suspend(struct radeon_device *rdev);
407int evergreen_resume(struct radeon_device *rdev);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]408bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]409int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]410void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]411void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]412void evergreen_hpd_init(struct radeon_device *rdev);
413void evergreen_hpd_fini(struct radeon_device *rdev);
414bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
415void evergreen_hpd_set_polarity(struct radeon_device *rdev,
416 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]417u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
418int evergreen_irq_set(struct radeon_device *rdev);
419int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]420extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]421extern void evergreen_pm_misc(struct radeon_device *rdev);
422extern void evergreen_pm_prepare(struct radeon_device *rdev);
423extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]424extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]425extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
426extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
427extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]428void evergreen_disable_interrupt_state(struct radeon_device *rdev);
429int evergreen_blit_init(struct radeon_device *rdev);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]430
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]431/*
432 * cayman
433 */
434void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
435int cayman_init(struct radeon_device *rdev);
436void cayman_fini(struct radeon_device *rdev);
437int cayman_suspend(struct radeon_device *rdev);
438int cayman_resume(struct radeon_device *rdev);
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame^]439bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]440int cayman_asic_reset(struct radeon_device *rdev);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]441
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]442#endif