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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / def9ba9cf6a8266ee1ffd72556db002c3a2663db / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: c74bf9bd26c2bcba82e2568e119adaff5654f428 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]46 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]47 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]60uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
61void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]62void r100_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]63bool r100_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]64int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]65u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]66void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
67int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]68void r100_cp_commit(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]69void r100_ring_start(struct radeon_device *rdev);
70int r100_irq_set(struct radeon_device *rdev);
71int r100_irq_process(struct radeon_device *rdev);
72void r100_fence_ring_emit(struct radeon_device *rdev,
73 struct radeon_fence *fence);
74int r100_cs_parse(struct radeon_cs_parser *p);
75void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
76uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
77int r100_copy_blit(struct radeon_device *rdev,
78 uint64_t src_offset,
79 uint64_t dst_offset,
80 unsigned num_pages,
81 struct radeon_fence *fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]82int r100_set_surface_reg(struct radeon_device *rdev, int reg,
83 uint32_t tiling_flags, uint32_t pitch,
84 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]85void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]86void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]87void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]88int r100_ring_test(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]89void r100_hpd_init(struct radeon_device *rdev);
90void r100_hpd_fini(struct radeon_device *rdev);
91bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
92void r100_hpd_set_polarity(struct radeon_device *rdev,
93 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]94int r100_debugfs_rbbm_init(struct radeon_device *rdev);
95int r100_debugfs_cp_init(struct radeon_device *rdev);
96void r100_cp_disable(struct radeon_device *rdev);
97int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
98void r100_cp_fini(struct radeon_device *rdev);
99int r100_pci_gart_init(struct radeon_device *rdev);
100void r100_pci_gart_fini(struct radeon_device *rdev);
101int r100_pci_gart_enable(struct radeon_device *rdev);
102void r100_pci_gart_disable(struct radeon_device *rdev);
103int r100_debugfs_mc_info_init(struct radeon_device *rdev);
104int r100_gui_wait_for_idle(struct radeon_device *rdev);
105void r100_ib_fini(struct radeon_device *rdev);
106int r100_ib_init(struct radeon_device *rdev);
107void r100_irq_disable(struct radeon_device *rdev);
108void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
109void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
110void r100_vram_init_sizes(struct radeon_device *rdev);
111void r100_wb_disable(struct radeon_device *rdev);
112void r100_wb_fini(struct radeon_device *rdev);
113int r100_wb_init(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]114int r100_cp_reset(struct radeon_device *rdev);
115void r100_vga_render_disable(struct radeon_device *rdev);
116int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
117 struct radeon_cs_packet *pkt,
118 struct radeon_bo *robj);
119int r100_cs_parse_packet0(struct radeon_cs_parser *p,
120 struct radeon_cs_packet *pkt,
121 const unsigned *auth, unsigned n,
122 radeon_packet0_check_t check);
123int r100_cs_packet_parse(struct radeon_cs_parser *p,
124 struct radeon_cs_packet *pkt,
125 unsigned idx);
126void r100_enable_bm(struct radeon_device *rdev);
127void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]128void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame^]129extern bool r100_gui_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]130/*
131 * r200,rv250,rs300,rv280
132 */
133extern int r200_copy_dma(struct radeon_device *rdev,
134 uint64_t src_offset,
135 uint64_t dst_offset,
136 unsigned num_pages,
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]137 struct radeon_fence *fence);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]138
139/*
140 * r300,r350,rv350,rv380
141 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]142extern int r300_init(struct radeon_device *rdev);
143extern void r300_fini(struct radeon_device *rdev);
144extern int r300_suspend(struct radeon_device *rdev);
145extern int r300_resume(struct radeon_device *rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]146extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]147extern int r300_asic_reset(struct radeon_device *rdev);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]148extern void r300_ring_start(struct radeon_device *rdev);
149extern void r300_fence_ring_emit(struct radeon_device *rdev,
150 struct radeon_fence *fence);
151extern int r300_cs_parse(struct radeon_cs_parser *p);
152extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
153extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
154extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
155extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
156extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]157extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]158
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]159/*
160 * r420,r423,rv410
161 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]162extern int r420_init(struct radeon_device *rdev);
163extern void r420_fini(struct radeon_device *rdev);
164extern int r420_suspend(struct radeon_device *rdev);
165extern int r420_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]166
167/*
168 * rs400,rs480
169 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]170extern int rs400_init(struct radeon_device *rdev);
171extern void rs400_fini(struct radeon_device *rdev);
172extern int rs400_suspend(struct radeon_device *rdev);
173extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]174void rs400_gart_tlb_flush(struct radeon_device *rdev);
175int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
176uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
177void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]178
179/*
180 * rs600.
181 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]182extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]183extern int rs600_init(struct radeon_device *rdev);
184extern void rs600_fini(struct radeon_device *rdev);
185extern int rs600_suspend(struct radeon_device *rdev);
186extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]187int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]188int rs600_irq_process(struct radeon_device *rdev);
189u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]190void rs600_gart_tlb_flush(struct radeon_device *rdev);
191int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
192uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
193void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]194void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]195void rs600_hpd_init(struct radeon_device *rdev);
196void rs600_hpd_fini(struct radeon_device *rdev);
197bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
198void rs600_hpd_set_polarity(struct radeon_device *rdev,
199 enum radeon_hpd_id hpd);
200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]201/*
202 * rs690,rs740
203 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]204int rs690_init(struct radeon_device *rdev);
205void rs690_fini(struct radeon_device *rdev);
206int rs690_resume(struct radeon_device *rdev);
207int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]208uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
209void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]210void rs690_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]211
212/*
213 * rv515
214 */
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]215int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]216void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]217uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
218void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
219void rv515_ring_start(struct radeon_device *rdev);
220uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
221void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]222void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]223int rv515_resume(struct radeon_device *rdev);
224int rv515_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]225
226/*
227 * r520,rv530,rv560,rv570,r580
228 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]229int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]230int r520_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]231
232/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]233 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]234 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]235int r600_init(struct radeon_device *rdev);
236void r600_fini(struct radeon_device *rdev);
237int r600_suspend(struct radeon_device *rdev);
238int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]239void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]240int r600_wb_init(struct radeon_device *rdev);
241void r600_wb_fini(struct radeon_device *rdev);
242void r600_cp_commit(struct radeon_device *rdev);
243void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]244uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
245void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]246int r600_cs_parse(struct radeon_cs_parser *p);
247void r600_fence_ring_emit(struct radeon_device *rdev,
248 struct radeon_fence *fence);
249int r600_copy_dma(struct radeon_device *rdev,
250 uint64_t src_offset,
251 uint64_t dst_offset,
252 unsigned num_pages,
253 struct radeon_fence *fence);
254int r600_irq_process(struct radeon_device *rdev);
255int r600_irq_set(struct radeon_device *rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]256bool r600_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]257int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]258int r600_set_surface_reg(struct radeon_device *rdev, int reg,
259 uint32_t tiling_flags, uint32_t pitch,
260 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]261void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]262void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]263int r600_ring_test(struct radeon_device *rdev);
264int r600_copy_blit(struct radeon_device *rdev,
265 uint64_t src_offset, uint64_t dst_offset,
266 unsigned num_pages, struct radeon_fence *fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]267void r600_hpd_init(struct radeon_device *rdev);
268void r600_hpd_fini(struct radeon_device *rdev);
269bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
270void r600_hpd_set_polarity(struct radeon_device *rdev,
271 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]272extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame^]273extern bool r600_gui_idle(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]274
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]275/*
276 * rv770,rv730,rv710,rv740
277 */
278int rv770_init(struct radeon_device *rdev);
279void rv770_fini(struct radeon_device *rdev);
280int rv770_suspend(struct radeon_device *rdev);
281int rv770_resume(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]282
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]283/*
284 * evergreen
285 */
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]286void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]287int evergreen_init(struct radeon_device *rdev);
288void evergreen_fini(struct radeon_device *rdev);
289int evergreen_suspend(struct radeon_device *rdev);
290int evergreen_resume(struct radeon_device *rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]291bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]292int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]293void evergreen_bandwidth_update(struct radeon_device *rdev);
294void evergreen_hpd_init(struct radeon_device *rdev);
295void evergreen_hpd_fini(struct radeon_device *rdev);
296bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
297void evergreen_hpd_set_polarity(struct radeon_device *rdev,
298 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]299u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
300int evergreen_irq_set(struct radeon_device *rdev);
301int evergreen_irq_process(struct radeon_device *rdev);
302
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]303#endif