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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 003cefe0c238e683a29d2207dba945b508cd45b7 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 3dedaa07aac197b4179ce27aa25054b460684f7b [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]46 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]47 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]60void r100_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]61bool r100_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]62int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]66void r100_cp_commit(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]67void r100_ring_start(struct radeon_device *rdev);
68int r100_irq_set(struct radeon_device *rdev);
69int r100_irq_process(struct radeon_device *rdev);
70void r100_fence_ring_emit(struct radeon_device *rdev,
71 struct radeon_fence *fence);
72int r100_cs_parse(struct radeon_cs_parser *p);
73void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
74uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
75int r100_copy_blit(struct radeon_device *rdev,
76 uint64_t src_offset,
77 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame^]78 unsigned num_gpu_pages,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]79 struct radeon_fence *fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]80int r100_set_surface_reg(struct radeon_device *rdev, int reg,
81 uint32_t tiling_flags, uint32_t pitch,
82 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]83void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]84void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]85void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]86int r100_ring_test(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]87void r100_hpd_init(struct radeon_device *rdev);
88void r100_hpd_fini(struct radeon_device *rdev);
89bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
90void r100_hpd_set_polarity(struct radeon_device *rdev,
91 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]92int r100_debugfs_rbbm_init(struct radeon_device *rdev);
93int r100_debugfs_cp_init(struct radeon_device *rdev);
94void r100_cp_disable(struct radeon_device *rdev);
95int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
96void r100_cp_fini(struct radeon_device *rdev);
97int r100_pci_gart_init(struct radeon_device *rdev);
98void r100_pci_gart_fini(struct radeon_device *rdev);
99int r100_pci_gart_enable(struct radeon_device *rdev);
100void r100_pci_gart_disable(struct radeon_device *rdev);
101int r100_debugfs_mc_info_init(struct radeon_device *rdev);
102int r100_gui_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]103void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup,
104 struct radeon_cp *cp);
105bool r100_gpu_cp_is_lockup(struct radeon_device *rdev,
106 struct r100_gpu_lockup *lockup,
107 struct radeon_cp *cp);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]108void r100_ib_fini(struct radeon_device *rdev);
109int r100_ib_init(struct radeon_device *rdev);
110void r100_irq_disable(struct radeon_device *rdev);
111void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
112void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
113void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]114int r100_cp_reset(struct radeon_device *rdev);
115void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]116void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
118 struct radeon_cs_packet *pkt,
119 struct radeon_bo *robj);
120int r100_cs_parse_packet0(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 const unsigned *auth, unsigned n,
123 radeon_packet0_check_t check);
124int r100_cs_packet_parse(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 unsigned idx);
127void r100_enable_bm(struct radeon_device *rdev);
128void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]129void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]130extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]131extern void r100_pm_misc(struct radeon_device *rdev);
132extern void r100_pm_prepare(struct radeon_device *rdev);
133extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]134extern void r100_pm_init_profile(struct radeon_device *rdev);
135extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]136extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
137extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
138extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]139
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]140/*
141 * r200,rv250,rs300,rv280
142 */
143extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]144 uint64_t src_offset,
145 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame^]146 unsigned num_gpu_pages,
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]147 struct radeon_fence *fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]148void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]149
150/*
151 * r300,r350,rv350,rv380
152 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]153extern int r300_init(struct radeon_device *rdev);
154extern void r300_fini(struct radeon_device *rdev);
155extern int r300_suspend(struct radeon_device *rdev);
156extern int r300_resume(struct radeon_device *rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]157extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]158extern int r300_asic_reset(struct radeon_device *rdev);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]159extern void r300_ring_start(struct radeon_device *rdev);
160extern void r300_fence_ring_emit(struct radeon_device *rdev,
161 struct radeon_fence *fence);
162extern int r300_cs_parse(struct radeon_cs_parser *p);
163extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
164extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]165extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]166extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]167extern void r300_set_reg_safe(struct radeon_device *rdev);
168extern void r300_mc_program(struct radeon_device *rdev);
169extern void r300_mc_init(struct radeon_device *rdev);
170extern void r300_clock_startup(struct radeon_device *rdev);
171extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
172extern int rv370_pcie_gart_init(struct radeon_device *rdev);
173extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
174extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
175extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]176
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]177/*
178 * r420,r423,rv410
179 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]180extern int r420_init(struct radeon_device *rdev);
181extern void r420_fini(struct radeon_device *rdev);
182extern int r420_suspend(struct radeon_device *rdev);
183extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]184extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]185extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
186extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
187extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
188extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]189
190/*
191 * rs400,rs480
192 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]193extern int rs400_init(struct radeon_device *rdev);
194extern void rs400_fini(struct radeon_device *rdev);
195extern int rs400_suspend(struct radeon_device *rdev);
196extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]197void rs400_gart_tlb_flush(struct radeon_device *rdev);
198int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
199uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
200void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]201int rs400_gart_init(struct radeon_device *rdev);
202int rs400_gart_enable(struct radeon_device *rdev);
203void rs400_gart_adjust_size(struct radeon_device *rdev);
204void rs400_gart_disable(struct radeon_device *rdev);
205void rs400_gart_fini(struct radeon_device *rdev);
206
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]207/*
208 * rs600.
209 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]210extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]211extern int rs600_init(struct radeon_device *rdev);
212extern void rs600_fini(struct radeon_device *rdev);
213extern int rs600_suspend(struct radeon_device *rdev);
214extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]215int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]216int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]217void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]218u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219void rs600_gart_tlb_flush(struct radeon_device *rdev);
220int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
221uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
222void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]223void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]224void rs600_hpd_init(struct radeon_device *rdev);
225void rs600_hpd_fini(struct radeon_device *rdev);
226bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
227void rs600_hpd_set_polarity(struct radeon_device *rdev,
228 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]229extern void rs600_pm_misc(struct radeon_device *rdev);
230extern void rs600_pm_prepare(struct radeon_device *rdev);
231extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]232extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
233extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
234extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]235void rs600_set_safe_registers(struct radeon_device *rdev);
236
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]237
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]238/*
239 * rs690,rs740
240 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]241int rs690_init(struct radeon_device *rdev);
242void rs690_fini(struct radeon_device *rdev);
243int rs690_resume(struct radeon_device *rdev);
244int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]245uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
246void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]247void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]248void rs690_line_buffer_adjust(struct radeon_device *rdev,
249 struct drm_display_mode *mode1,
250 struct drm_display_mode *mode2);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]251
252/*
253 * rv515
254 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]255struct rv515_mc_save {
256 u32 d1vga_control;
257 u32 d2vga_control;
258 u32 vga_render_control;
259 u32 vga_hdp_control;
260 u32 d1crtc_control;
261 u32 d2crtc_control;
262};
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]263int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]264void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]265uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
266void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
267void rv515_ring_start(struct radeon_device *rdev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]268void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]269int rv515_resume(struct radeon_device *rdev);
270int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]271void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
272void rv515_vga_render_disable(struct radeon_device *rdev);
273void rv515_set_safe_registers(struct radeon_device *rdev);
274void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
275void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
276void rv515_clock_startup(struct radeon_device *rdev);
277void rv515_debugfs(struct radeon_device *rdev);
278
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]279
280/*
281 * r520,rv530,rv560,rv570,r580
282 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]283int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]284int r520_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]285
286/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]287 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]288 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]289int r600_init(struct radeon_device *rdev);
290void r600_fini(struct radeon_device *rdev);
291int r600_suspend(struct radeon_device *rdev);
292int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]293void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]294int r600_wb_init(struct radeon_device *rdev);
295void r600_wb_fini(struct radeon_device *rdev);
296void r600_cp_commit(struct radeon_device *rdev);
297void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]298uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
299void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]300int r600_cs_parse(struct radeon_cs_parser *p);
301void r600_fence_ring_emit(struct radeon_device *rdev,
302 struct radeon_fence *fence);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]303bool r600_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]304int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]305int r600_set_surface_reg(struct radeon_device *rdev, int reg,
306 uint32_t tiling_flags, uint32_t pitch,
307 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]308void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]309int r600_ib_test(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]310void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]311int r600_ring_test(struct radeon_device *rdev);
312int r600_copy_blit(struct radeon_device *rdev,
313 uint64_t src_offset, uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame^]314 unsigned num_gpu_pages, struct radeon_fence *fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]315void r600_hpd_init(struct radeon_device *rdev);
316void r600_hpd_fini(struct radeon_device *rdev);
317bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
318void r600_hpd_set_polarity(struct radeon_device *rdev,
319 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]320extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]321extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]322extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]323extern void r600_pm_init_profile(struct radeon_device *rdev);
324extern void rs780_pm_init_profile(struct radeon_device *rdev);
325extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]326extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
327extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]328bool r600_card_posted(struct radeon_device *rdev);
329void r600_cp_stop(struct radeon_device *rdev);
330int r600_cp_start(struct radeon_device *rdev);
331void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
332int r600_cp_resume(struct radeon_device *rdev);
333void r600_cp_fini(struct radeon_device *rdev);
334int r600_count_pipe_bits(uint32_t val);
335int r600_mc_wait_for_idle(struct radeon_device *rdev);
336int r600_pcie_gart_init(struct radeon_device *rdev);
337void r600_scratch_init(struct radeon_device *rdev);
338int r600_blit_init(struct radeon_device *rdev);
339void r600_blit_fini(struct radeon_device *rdev);
340int r600_init_microcode(struct radeon_device *rdev);
341/* r600 irq */
342int r600_irq_process(struct radeon_device *rdev);
343int r600_irq_init(struct radeon_device *rdev);
344void r600_irq_fini(struct radeon_device *rdev);
345void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
346int r600_irq_set(struct radeon_device *rdev);
347void r600_irq_suspend(struct radeon_device *rdev);
348void r600_disable_interrupts(struct radeon_device *rdev);
349void r600_rlc_stop(struct radeon_device *rdev);
350/* r600 audio */
351int r600_audio_init(struct radeon_device *rdev);
352int r600_audio_tmds_index(struct drm_encoder *encoder);
353void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
354int r600_audio_channels(struct radeon_device *rdev);
355int r600_audio_bits_per_sample(struct radeon_device *rdev);
356int r600_audio_rate(struct radeon_device *rdev);
357uint8_t r600_audio_status_bits(struct radeon_device *rdev);
358uint8_t r600_audio_category_code(struct radeon_device *rdev);
359void r600_audio_schedule_polling(struct radeon_device *rdev);
360void r600_audio_enable_polling(struct drm_encoder *encoder);
361void r600_audio_disable_polling(struct drm_encoder *encoder);
362void r600_audio_fini(struct radeon_device *rdev);
363void r600_hdmi_init(struct drm_encoder *encoder);
364int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
365void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]366/* r600 blit */
367int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
368void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
369void r600_kms_blit_copy(struct radeon_device *rdev,
370 u64 src_gpu_addr, u64 dst_gpu_addr,
371 int size_bytes);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]372
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]373/*
374 * rv770,rv730,rv710,rv740
375 */
376int rv770_init(struct radeon_device *rdev);
377void rv770_fini(struct radeon_device *rdev);
378int rv770_suspend(struct radeon_device *rdev);
379int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]380void rv770_pm_misc(struct radeon_device *rdev);
381u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
382void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
383void r700_cp_stop(struct radeon_device *rdev);
384void r700_cp_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]385
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]386/*
387 * evergreen
388 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]389struct evergreen_mc_save {
390 u32 vga_control[6];
391 u32 vga_render_control;
392 u32 vga_hdp_control;
393 u32 crtc_control[6];
394};
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]395void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]396int evergreen_init(struct radeon_device *rdev);
397void evergreen_fini(struct radeon_device *rdev);
398int evergreen_suspend(struct radeon_device *rdev);
399int evergreen_resume(struct radeon_device *rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]400bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]401int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]402void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]403void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400[diff] [blame]404int evergreen_copy_blit(struct radeon_device *rdev,
405 uint64_t src_offset, uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame^]406 unsigned num_gpu_pages, struct radeon_fence *fence);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]407void evergreen_hpd_init(struct radeon_device *rdev);
408void evergreen_hpd_fini(struct radeon_device *rdev);
409bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
410void evergreen_hpd_set_polarity(struct radeon_device *rdev,
411 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]412u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
413int evergreen_irq_set(struct radeon_device *rdev);
414int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]415extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]416extern void evergreen_pm_misc(struct radeon_device *rdev);
417extern void evergreen_pm_prepare(struct radeon_device *rdev);
418extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]419extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
420extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
421extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]422void evergreen_disable_interrupt_state(struct radeon_device *rdev);
423int evergreen_blit_init(struct radeon_device *rdev);
424void evergreen_blit_fini(struct radeon_device *rdev);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]425/* evergreen blit */
426int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
427void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
428void evergreen_kms_blit_copy(struct radeon_device *rdev,
429 u64 src_gpu_addr, u64 dst_gpu_addr,
430 int size_bytes);
431
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]432/*
433 * cayman
434 */
435void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
436int cayman_init(struct radeon_device *rdev);
437void cayman_fini(struct radeon_device *rdev);
438int cayman_suspend(struct radeon_device *rdev);
439int cayman_resume(struct radeon_device *rdev);
440bool cayman_gpu_is_lockup(struct radeon_device *rdev);
441int cayman_asic_reset(struct radeon_device *rdev);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]442
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]443#endif