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review.shift-gmbh.com / SHIFTPHONES / kernel / common / c8ca97ca9b87c0a9c9e67feda656b8dbca65cf08 / . / arch / powerpc / kvm / booke_emulate.c
blob: 4b9a079927539ed1940334ba2b3a46ee8a2c226d [file] [log] [blame]
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]16 * Copyright 2011 Freescale Semiconductor, Inc.
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21#include <linux/kvm_host.h>
22#include <asm/disassemble.h>
23
24#include "booke.h"
25
26#define OP_19_XOP_RFI 50
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]27#define OP_19_XOP_RFCI 51
Bharat Bhushanc8ca97c2014-08-06 12:08:52 +0530[diff] [blame^]28#define OP_19_XOP_RFDI 39
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]29
30#define OP_31_XOP_MFMSR 83
31#define OP_31_XOP_WRTEE 131
32#define OP_31_XOP_MTMSR 146
33#define OP_31_XOP_WRTEEI 163
34
35static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
36{
Alexander Grafde7906c2010-07-29 14:47:46 +0200[diff] [blame]37 vcpu->arch.pc = vcpu->arch.shared->srr0;
38 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]39}
40
Bharat Bhushanc8ca97c2014-08-06 12:08:52 +0530[diff] [blame^]41static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
42{
43 vcpu->arch.pc = vcpu->arch.dsrr0;
44 kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
45}
46
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]47static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
48{
49 vcpu->arch.pc = vcpu->arch.csrr0;
50 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
51}
52
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]53int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
54 unsigned int inst, int *advance)
55{
56 int emulated = EMULATE_DONE;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200[diff] [blame]57 int rs = get_rs(inst);
58 int rt = get_rt(inst);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]59
60 switch (get_op(inst)) {
61 case 19:
62 switch (get_xop(inst)) {
63 case OP_19_XOP_RFI:
64 kvmppc_emul_rfi(vcpu);
65 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
66 *advance = 0;
67 break;
68
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]69 case OP_19_XOP_RFCI:
70 kvmppc_emul_rfci(vcpu);
71 kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
72 *advance = 0;
73 break;
74
Bharat Bhushanc8ca97c2014-08-06 12:08:52 +0530[diff] [blame^]75 case OP_19_XOP_RFDI:
76 kvmppc_emul_rfdi(vcpu);
77 kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
78 *advance = 0;
79 break;
80
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]81 default:
82 emulated = EMULATE_FAIL;
83 break;
84 }
85 break;
86
87 case 31:
88 switch (get_xop(inst)) {
89
90 case OP_31_XOP_MFMSR:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]91 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]92 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
93 break;
94
95 case OP_31_XOP_MTMSR:
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]96 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]97 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]98 break;
99
100 case OP_31_XOP_WRTEE:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]101 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]102 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]103 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
104 break;
105
106 case OP_31_XOP_WRTEEI:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]107 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]108 | (inst & MSR_EE);
109 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
110 break;
111
112 default:
113 emulated = EMULATE_FAIL;
114 }
115
116 break;
117
118 default:
119 emulated = EMULATE_FAIL;
120 }
121
122 return emulated;
123}
124
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]125/*
126 * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
127 * Their backing store is in real registers, and these functions
128 * will return the wrong result if called for them in another context
129 * (such as debugging).
130 */
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]131int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]132{
133 int emulated = EMULATE_DONE;
134
135 switch (sprn) {
136 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]137 vcpu->arch.shared->dar = spr_val;
138 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]139 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]140 vcpu->arch.shared->esr = spr_val;
141 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]142 case SPRN_CSRR0:
143 vcpu->arch.csrr0 = spr_val;
144 break;
145 case SPRN_CSRR1:
146 vcpu->arch.csrr1 = spr_val;
147 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]148 case SPRN_DBCR0:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]149 vcpu->arch.dbg_reg.dbcr0 = spr_val;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]150 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]151 case SPRN_DBCR1:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]152 vcpu->arch.dbg_reg.dbcr1 = spr_val;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]153 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]154 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]155 vcpu->arch.dbsr &= ~spr_val;
156 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]157 case SPRN_TSR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]158 kvmppc_clr_tsr_bits(vcpu, spr_val);
159 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]160 case SPRN_TCR:
Bharat Bhushanf61c94b2012-08-08 20:38:19 +0000[diff] [blame]161 /*
162 * WRC is a 2-bit field that is supposed to preserve its
163 * value once written to non-zero.
164 */
165 if (vcpu->arch.tcr & TCR_WRC_MASK) {
166 spr_val &= ~TCR_WRC_MASK;
167 spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
168 }
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]169 kvmppc_set_tcr(vcpu, spr_val);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]170 break;
171
Bharat Bhushan21bd0002012-05-20 23:21:23 +0000[diff] [blame]172 case SPRN_DECAR:
173 vcpu->arch.decar = spr_val;
174 break;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]175 /*
176 * Note: SPRG4-7 are user-readable.
177 * These values are loaded into the real SPRGs when resuming the
178 * guest (PR-mode only).
179 */
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]180 case SPRN_SPRG4:
Bharat Bhushanc1b8a012014-07-17 17:01:39 +0530[diff] [blame]181 kvmppc_set_sprg4(vcpu, spr_val);
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]182 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]183 case SPRN_SPRG5:
Bharat Bhushanc1b8a012014-07-17 17:01:39 +0530[diff] [blame]184 kvmppc_set_sprg5(vcpu, spr_val);
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]185 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]186 case SPRN_SPRG6:
Bharat Bhushanc1b8a012014-07-17 17:01:39 +0530[diff] [blame]187 kvmppc_set_sprg6(vcpu, spr_val);
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]188 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]189 case SPRN_SPRG7:
Bharat Bhushanc1b8a012014-07-17 17:01:39 +0530[diff] [blame]190 kvmppc_set_sprg7(vcpu, spr_val);
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]191 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]192
193 case SPRN_IVPR:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]194 vcpu->arch.ivpr = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]195#ifdef CONFIG_KVM_BOOKE_HV
196 mtspr(SPRN_GIVPR, spr_val);
197#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]198 break;
199 case SPRN_IVOR0:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]200 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]201 break;
202 case SPRN_IVOR1:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]203 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]204 break;
205 case SPRN_IVOR2:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]206 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]207#ifdef CONFIG_KVM_BOOKE_HV
208 mtspr(SPRN_GIVOR2, spr_val);
209#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]210 break;
211 case SPRN_IVOR3:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]212 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]213 break;
214 case SPRN_IVOR4:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]215 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]216 break;
217 case SPRN_IVOR5:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]218 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]219 break;
220 case SPRN_IVOR6:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]221 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]222 break;
223 case SPRN_IVOR7:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]224 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]225 break;
226 case SPRN_IVOR8:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]227 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]228#ifdef CONFIG_KVM_BOOKE_HV
229 mtspr(SPRN_GIVOR8, spr_val);
230#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]231 break;
232 case SPRN_IVOR9:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]233 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]234 break;
235 case SPRN_IVOR10:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]236 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]237 break;
238 case SPRN_IVOR11:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]239 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]240 break;
241 case SPRN_IVOR12:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]242 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]243 break;
244 case SPRN_IVOR13:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]245 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]246 break;
247 case SPRN_IVOR14:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]248 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]249 break;
250 case SPRN_IVOR15:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]251 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]252 break;
Alexander Graf50c871e2012-08-13 14:50:54 +0200[diff] [blame]253 case SPRN_MCSR:
254 vcpu->arch.mcsr &= ~spr_val;
255 break;
Mihai Caraman38f98822012-10-11 06:13:27 +0000[diff] [blame]256#if defined(CONFIG_64BIT)
257 case SPRN_EPCR:
258 kvmppc_set_epcr(vcpu, spr_val);
259#ifdef CONFIG_KVM_BOOKE_HV
260 mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
261#endif
262 break;
263#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]264 default:
265 emulated = EMULATE_FAIL;
266 }
267
268 return emulated;
269}
270
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]271int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]272{
273 int emulated = EMULATE_DONE;
274
275 switch (sprn) {
276 case SPRN_IVPR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]277 *spr_val = vcpu->arch.ivpr;
278 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]279 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]280 *spr_val = vcpu->arch.shared->dar;
281 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]282 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]283 *spr_val = vcpu->arch.shared->esr;
284 break;
Alexander Graf37ecb252013-01-04 18:02:14 +0100[diff] [blame]285 case SPRN_EPR:
286 *spr_val = vcpu->arch.epr;
287 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]288 case SPRN_CSRR0:
289 *spr_val = vcpu->arch.csrr0;
290 break;
291 case SPRN_CSRR1:
292 *spr_val = vcpu->arch.csrr1;
293 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]294 case SPRN_DBCR0:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]295 *spr_val = vcpu->arch.dbg_reg.dbcr0;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]296 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]297 case SPRN_DBCR1:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]298 *spr_val = vcpu->arch.dbg_reg.dbcr1;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]299 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]300 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]301 *spr_val = vcpu->arch.dbsr;
302 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]303 case SPRN_TSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]304 *spr_val = vcpu->arch.tsr;
305 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]306 case SPRN_TCR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]307 *spr_val = vcpu->arch.tcr;
308 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]309
310 case SPRN_IVOR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]311 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]312 break;
313 case SPRN_IVOR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]314 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]315 break;
316 case SPRN_IVOR2:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]317 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]318 break;
319 case SPRN_IVOR3:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]320 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]321 break;
322 case SPRN_IVOR4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]323 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]324 break;
325 case SPRN_IVOR5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]326 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]327 break;
328 case SPRN_IVOR6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]329 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]330 break;
331 case SPRN_IVOR7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]332 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]333 break;
334 case SPRN_IVOR8:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]335 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]336 break;
337 case SPRN_IVOR9:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]338 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]339 break;
340 case SPRN_IVOR10:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]341 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]342 break;
343 case SPRN_IVOR11:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]344 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]345 break;
346 case SPRN_IVOR12:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]347 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]348 break;
349 case SPRN_IVOR13:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]350 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]351 break;
352 case SPRN_IVOR14:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]353 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]354 break;
355 case SPRN_IVOR15:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]356 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]357 break;
Alexander Graf50c871e2012-08-13 14:50:54 +0200[diff] [blame]358 case SPRN_MCSR:
359 *spr_val = vcpu->arch.mcsr;
360 break;
Mihai Caraman38f98822012-10-11 06:13:27 +0000[diff] [blame]361#if defined(CONFIG_64BIT)
362 case SPRN_EPCR:
363 *spr_val = vcpu->arch.epcr;
364 break;
365#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]366
367 default:
368 emulated = EMULATE_FAIL;
369 }
370
371 return emulated;
372}