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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 21bd000abff7d587229dbbee6f8c17f3aad9f9d8 / . / arch / powerpc / kvm / booke_emulate.c
blob: 9eb9809eb13e2aa8ffee131c3550ba73bb4ce2f1 [file] [log] [blame]
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]16 * Copyright 2011 Freescale Semiconductor, Inc.
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21#include <linux/kvm_host.h>
22#include <asm/disassemble.h>
23
24#include "booke.h"
25
26#define OP_19_XOP_RFI 50
27
28#define OP_31_XOP_MFMSR 83
29#define OP_31_XOP_WRTEE 131
30#define OP_31_XOP_MTMSR 146
31#define OP_31_XOP_WRTEEI 163
32
33static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
34{
Alexander Grafde7906c2010-07-29 14:47:46 +0200[diff] [blame]35 vcpu->arch.pc = vcpu->arch.shared->srr0;
36 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]37}
38
39int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
40 unsigned int inst, int *advance)
41{
42 int emulated = EMULATE_DONE;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200[diff] [blame]43 int rs = get_rs(inst);
44 int rt = get_rt(inst);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]45
46 switch (get_op(inst)) {
47 case 19:
48 switch (get_xop(inst)) {
49 case OP_19_XOP_RFI:
50 kvmppc_emul_rfi(vcpu);
51 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
52 *advance = 0;
53 break;
54
55 default:
56 emulated = EMULATE_FAIL;
57 break;
58 }
59 break;
60
61 case 31:
62 switch (get_xop(inst)) {
63
64 case OP_31_XOP_MFMSR:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]65 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]66 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
67 break;
68
69 case OP_31_XOP_MTMSR:
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]70 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]71 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]72 break;
73
74 case OP_31_XOP_WRTEE:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]75 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]76 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]77 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
78 break;
79
80 case OP_31_XOP_WRTEEI:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]81 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]82 | (inst & MSR_EE);
83 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
84 break;
85
86 default:
87 emulated = EMULATE_FAIL;
88 }
89
90 break;
91
92 default:
93 emulated = EMULATE_FAIL;
94 }
95
96 return emulated;
97}
98
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]99/*
100 * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
101 * Their backing store is in real registers, and these functions
102 * will return the wrong result if called for them in another context
103 * (such as debugging).
104 */
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]105int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]106{
107 int emulated = EMULATE_DONE;
108
109 switch (sprn) {
110 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]111 vcpu->arch.shared->dar = spr_val;
112 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]113 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]114 vcpu->arch.shared->esr = spr_val;
115 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]116 case SPRN_DBCR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]117 vcpu->arch.dbcr0 = spr_val;
118 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]119 case SPRN_DBCR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]120 vcpu->arch.dbcr1 = spr_val;
121 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]122 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]123 vcpu->arch.dbsr &= ~spr_val;
124 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]125 case SPRN_TSR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]126 kvmppc_clr_tsr_bits(vcpu, spr_val);
127 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]128 case SPRN_TCR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]129 kvmppc_set_tcr(vcpu, spr_val);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]130 break;
131
Bharat Bhushan21bd0002012-05-20 23:21:23 +0000[diff] [blame^]132 case SPRN_DECAR:
133 vcpu->arch.decar = spr_val;
134 break;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]135 /*
136 * Note: SPRG4-7 are user-readable.
137 * These values are loaded into the real SPRGs when resuming the
138 * guest (PR-mode only).
139 */
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]140 case SPRN_SPRG4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]141 vcpu->arch.shared->sprg4 = spr_val;
142 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]143 case SPRN_SPRG5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]144 vcpu->arch.shared->sprg5 = spr_val;
145 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]146 case SPRN_SPRG6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]147 vcpu->arch.shared->sprg6 = spr_val;
148 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]149 case SPRN_SPRG7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]150 vcpu->arch.shared->sprg7 = spr_val;
151 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]152
153 case SPRN_IVPR:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]154 vcpu->arch.ivpr = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]155#ifdef CONFIG_KVM_BOOKE_HV
156 mtspr(SPRN_GIVPR, spr_val);
157#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]158 break;
159 case SPRN_IVOR0:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]160 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]161 break;
162 case SPRN_IVOR1:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]163 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]164 break;
165 case SPRN_IVOR2:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]166 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]167#ifdef CONFIG_KVM_BOOKE_HV
168 mtspr(SPRN_GIVOR2, spr_val);
169#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]170 break;
171 case SPRN_IVOR3:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]172 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]173 break;
174 case SPRN_IVOR4:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]175 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]176 break;
177 case SPRN_IVOR5:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]178 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]179 break;
180 case SPRN_IVOR6:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]181 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]182 break;
183 case SPRN_IVOR7:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]184 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]185 break;
186 case SPRN_IVOR8:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]187 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]188#ifdef CONFIG_KVM_BOOKE_HV
189 mtspr(SPRN_GIVOR8, spr_val);
190#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]191 break;
192 case SPRN_IVOR9:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]193 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]194 break;
195 case SPRN_IVOR10:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]196 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]197 break;
198 case SPRN_IVOR11:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]199 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]200 break;
201 case SPRN_IVOR12:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]202 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]203 break;
204 case SPRN_IVOR13:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]205 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]206 break;
207 case SPRN_IVOR14:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]208 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]209 break;
210 case SPRN_IVOR15:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]211 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]212 break;
213
214 default:
215 emulated = EMULATE_FAIL;
216 }
217
218 return emulated;
219}
220
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]221int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]222{
223 int emulated = EMULATE_DONE;
224
225 switch (sprn) {
226 case SPRN_IVPR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]227 *spr_val = vcpu->arch.ivpr;
228 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]229 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]230 *spr_val = vcpu->arch.shared->dar;
231 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]232 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]233 *spr_val = vcpu->arch.shared->esr;
234 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]235 case SPRN_DBCR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]236 *spr_val = vcpu->arch.dbcr0;
237 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]238 case SPRN_DBCR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]239 *spr_val = vcpu->arch.dbcr1;
240 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]241 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]242 *spr_val = vcpu->arch.dbsr;
243 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]244 case SPRN_TSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]245 *spr_val = vcpu->arch.tsr;
246 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]247 case SPRN_TCR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]248 *spr_val = vcpu->arch.tcr;
249 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]250
251 case SPRN_IVOR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]252 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]253 break;
254 case SPRN_IVOR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]255 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]256 break;
257 case SPRN_IVOR2:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]258 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]259 break;
260 case SPRN_IVOR3:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]261 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]262 break;
263 case SPRN_IVOR4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]264 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]265 break;
266 case SPRN_IVOR5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]267 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]268 break;
269 case SPRN_IVOR6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]270 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]271 break;
272 case SPRN_IVOR7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]273 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]274 break;
275 case SPRN_IVOR8:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]276 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]277 break;
278 case SPRN_IVOR9:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]279 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]280 break;
281 case SPRN_IVOR10:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]282 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]283 break;
284 case SPRN_IVOR11:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]285 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]286 break;
287 case SPRN_IVOR12:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]288 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]289 break;
290 case SPRN_IVOR13:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]291 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]292 break;
293 case SPRN_IVOR14:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]294 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]295 break;
296 case SPRN_IVOR15:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]297 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]298 break;
299
300 default:
301 emulated = EMULATE_FAIL;
302 }
303
304 return emulated;
305}