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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 0c1fc3c3c496f8719fbea7fd3668491413ad420e / . / arch / powerpc / kvm / booke_emulate.c
blob: 12834bb608aba1e41653fa6aaa96f0735d587b80 [file] [log] [blame]
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]16 * Copyright 2011 Freescale Semiconductor, Inc.
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21#include <linux/kvm_host.h>
22#include <asm/disassemble.h>
23
24#include "booke.h"
25
26#define OP_19_XOP_RFI 50
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame^]27#define OP_19_XOP_RFCI 51
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]28
29#define OP_31_XOP_MFMSR 83
30#define OP_31_XOP_WRTEE 131
31#define OP_31_XOP_MTMSR 146
32#define OP_31_XOP_WRTEEI 163
33
34static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
35{
Alexander Grafde7906c2010-07-29 14:47:46 +0200[diff] [blame]36 vcpu->arch.pc = vcpu->arch.shared->srr0;
37 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]38}
39
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame^]40static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
41{
42 vcpu->arch.pc = vcpu->arch.csrr0;
43 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
44}
45
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]46int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
47 unsigned int inst, int *advance)
48{
49 int emulated = EMULATE_DONE;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200[diff] [blame]50 int rs = get_rs(inst);
51 int rt = get_rt(inst);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]52
53 switch (get_op(inst)) {
54 case 19:
55 switch (get_xop(inst)) {
56 case OP_19_XOP_RFI:
57 kvmppc_emul_rfi(vcpu);
58 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
59 *advance = 0;
60 break;
61
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame^]62 case OP_19_XOP_RFCI:
63 kvmppc_emul_rfci(vcpu);
64 kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
65 *advance = 0;
66 break;
67
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]68 default:
69 emulated = EMULATE_FAIL;
70 break;
71 }
72 break;
73
74 case 31:
75 switch (get_xop(inst)) {
76
77 case OP_31_XOP_MFMSR:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]78 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]79 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
80 break;
81
82 case OP_31_XOP_MTMSR:
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]83 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]84 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]85 break;
86
87 case OP_31_XOP_WRTEE:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]88 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]89 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]90 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
91 break;
92
93 case OP_31_XOP_WRTEEI:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]94 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]95 | (inst & MSR_EE);
96 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
97 break;
98
99 default:
100 emulated = EMULATE_FAIL;
101 }
102
103 break;
104
105 default:
106 emulated = EMULATE_FAIL;
107 }
108
109 return emulated;
110}
111
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]112/*
113 * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
114 * Their backing store is in real registers, and these functions
115 * will return the wrong result if called for them in another context
116 * (such as debugging).
117 */
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]118int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]119{
120 int emulated = EMULATE_DONE;
121
122 switch (sprn) {
123 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]124 vcpu->arch.shared->dar = spr_val;
125 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]126 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]127 vcpu->arch.shared->esr = spr_val;
128 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame^]129 case SPRN_CSRR0:
130 vcpu->arch.csrr0 = spr_val;
131 break;
132 case SPRN_CSRR1:
133 vcpu->arch.csrr1 = spr_val;
134 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]135 case SPRN_DBCR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]136 vcpu->arch.dbcr0 = spr_val;
137 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]138 case SPRN_DBCR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]139 vcpu->arch.dbcr1 = spr_val;
140 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]141 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]142 vcpu->arch.dbsr &= ~spr_val;
143 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]144 case SPRN_TSR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]145 kvmppc_clr_tsr_bits(vcpu, spr_val);
146 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]147 case SPRN_TCR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]148 kvmppc_set_tcr(vcpu, spr_val);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]149 break;
150
Bharat Bhushan21bd0002012-05-20 23:21:23 +0000[diff] [blame]151 case SPRN_DECAR:
152 vcpu->arch.decar = spr_val;
153 break;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]154 /*
155 * Note: SPRG4-7 are user-readable.
156 * These values are loaded into the real SPRGs when resuming the
157 * guest (PR-mode only).
158 */
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]159 case SPRN_SPRG4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]160 vcpu->arch.shared->sprg4 = spr_val;
161 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]162 case SPRN_SPRG5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]163 vcpu->arch.shared->sprg5 = spr_val;
164 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]165 case SPRN_SPRG6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]166 vcpu->arch.shared->sprg6 = spr_val;
167 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]168 case SPRN_SPRG7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]169 vcpu->arch.shared->sprg7 = spr_val;
170 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]171
172 case SPRN_IVPR:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]173 vcpu->arch.ivpr = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]174#ifdef CONFIG_KVM_BOOKE_HV
175 mtspr(SPRN_GIVPR, spr_val);
176#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]177 break;
178 case SPRN_IVOR0:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]179 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]180 break;
181 case SPRN_IVOR1:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]182 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]183 break;
184 case SPRN_IVOR2:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]185 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]186#ifdef CONFIG_KVM_BOOKE_HV
187 mtspr(SPRN_GIVOR2, spr_val);
188#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]189 break;
190 case SPRN_IVOR3:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]191 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]192 break;
193 case SPRN_IVOR4:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]194 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]195 break;
196 case SPRN_IVOR5:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]197 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]198 break;
199 case SPRN_IVOR6:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]200 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]201 break;
202 case SPRN_IVOR7:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]203 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]204 break;
205 case SPRN_IVOR8:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]206 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]207#ifdef CONFIG_KVM_BOOKE_HV
208 mtspr(SPRN_GIVOR8, spr_val);
209#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]210 break;
211 case SPRN_IVOR9:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]212 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]213 break;
214 case SPRN_IVOR10:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]215 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]216 break;
217 case SPRN_IVOR11:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]218 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]219 break;
220 case SPRN_IVOR12:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]221 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]222 break;
223 case SPRN_IVOR13:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]224 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]225 break;
226 case SPRN_IVOR14:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]227 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]228 break;
229 case SPRN_IVOR15:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]230 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]231 break;
232
233 default:
234 emulated = EMULATE_FAIL;
235 }
236
237 return emulated;
238}
239
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]240int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]241{
242 int emulated = EMULATE_DONE;
243
244 switch (sprn) {
245 case SPRN_IVPR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]246 *spr_val = vcpu->arch.ivpr;
247 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]248 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]249 *spr_val = vcpu->arch.shared->dar;
250 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]251 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]252 *spr_val = vcpu->arch.shared->esr;
253 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame^]254 case SPRN_CSRR0:
255 *spr_val = vcpu->arch.csrr0;
256 break;
257 case SPRN_CSRR1:
258 *spr_val = vcpu->arch.csrr1;
259 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]260 case SPRN_DBCR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]261 *spr_val = vcpu->arch.dbcr0;
262 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]263 case SPRN_DBCR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]264 *spr_val = vcpu->arch.dbcr1;
265 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]266 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]267 *spr_val = vcpu->arch.dbsr;
268 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]269 case SPRN_TSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]270 *spr_val = vcpu->arch.tsr;
271 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]272 case SPRN_TCR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]273 *spr_val = vcpu->arch.tcr;
274 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]275
276 case SPRN_IVOR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]277 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]278 break;
279 case SPRN_IVOR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]280 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]281 break;
282 case SPRN_IVOR2:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]283 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]284 break;
285 case SPRN_IVOR3:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]286 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]287 break;
288 case SPRN_IVOR4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]289 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]290 break;
291 case SPRN_IVOR5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]292 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]293 break;
294 case SPRN_IVOR6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]295 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]296 break;
297 case SPRN_IVOR7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]298 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]299 break;
300 case SPRN_IVOR8:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]301 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]302 break;
303 case SPRN_IVOR9:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]304 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]305 break;
306 case SPRN_IVOR10:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]307 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]308 break;
309 case SPRN_IVOR11:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]310 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]311 break;
312 case SPRN_IVOR12:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]313 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]314 break;
315 case SPRN_IVOR13:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]316 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]317 break;
318 case SPRN_IVOR14:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]319 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]320 break;
321 case SPRN_IVOR15:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]322 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]323 break;
324
325 default:
326 emulated = EMULATE_FAIL;
327 }
328
329 return emulated;
330}