Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / common / 50c871edf59b4585fd2c17acfe4e7cd3752418b7 / . / arch / powerpc / kvm / booke_emulate.c
blob: 514790f41abafa9c752ebdaa90bde9f1e961423f [file] [log] [blame]
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]16 * Copyright 2011 Freescale Semiconductor, Inc.
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21#include <linux/kvm_host.h>
22#include <asm/disassemble.h>
23
24#include "booke.h"
25
26#define OP_19_XOP_RFI 50
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]27#define OP_19_XOP_RFCI 51
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]28
29#define OP_31_XOP_MFMSR 83
30#define OP_31_XOP_WRTEE 131
31#define OP_31_XOP_MTMSR 146
32#define OP_31_XOP_WRTEEI 163
33
34static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
35{
Alexander Grafde7906c2010-07-29 14:47:46 +0200[diff] [blame]36 vcpu->arch.pc = vcpu->arch.shared->srr0;
37 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]38}
39
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]40static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
41{
42 vcpu->arch.pc = vcpu->arch.csrr0;
43 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
44}
45
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]46int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
47 unsigned int inst, int *advance)
48{
49 int emulated = EMULATE_DONE;
Alexander Grafc46dc9a2012-05-04 14:01:33 +0200[diff] [blame]50 int rs = get_rs(inst);
51 int rt = get_rt(inst);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]52
53 switch (get_op(inst)) {
54 case 19:
55 switch (get_xop(inst)) {
56 case OP_19_XOP_RFI:
57 kvmppc_emul_rfi(vcpu);
58 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
59 *advance = 0;
60 break;
61
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]62 case OP_19_XOP_RFCI:
63 kvmppc_emul_rfci(vcpu);
64 kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
65 *advance = 0;
66 break;
67
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]68 default:
69 emulated = EMULATE_FAIL;
70 break;
71 }
72 break;
73
74 case 31:
75 switch (get_xop(inst)) {
76
77 case OP_31_XOP_MFMSR:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]78 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]79 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
80 break;
81
82 case OP_31_XOP_MTMSR:
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]83 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]84 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]85 break;
86
87 case OP_31_XOP_WRTEE:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]88 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]89 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]90 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
91 break;
92
93 case OP_31_XOP_WRTEEI:
Alexander Graf666e7252010-07-29 14:47:43 +0200[diff] [blame]94 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]95 | (inst & MSR_EE);
96 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
97 break;
98
99 default:
100 emulated = EMULATE_FAIL;
101 }
102
103 break;
104
105 default:
106 emulated = EMULATE_FAIL;
107 }
108
109 return emulated;
110}
111
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]112/*
113 * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
114 * Their backing store is in real registers, and these functions
115 * will return the wrong result if called for them in another context
116 * (such as debugging).
117 */
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]118int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]119{
120 int emulated = EMULATE_DONE;
121
122 switch (sprn) {
123 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]124 vcpu->arch.shared->dar = spr_val;
125 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]126 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]127 vcpu->arch.shared->esr = spr_val;
128 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]129 case SPRN_CSRR0:
130 vcpu->arch.csrr0 = spr_val;
131 break;
132 case SPRN_CSRR1:
133 vcpu->arch.csrr1 = spr_val;
134 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]135 case SPRN_DBCR0:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]136 vcpu->arch.dbg_reg.dbcr0 = spr_val;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]137 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]138 case SPRN_DBCR1:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]139 vcpu->arch.dbg_reg.dbcr1 = spr_val;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]140 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]141 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]142 vcpu->arch.dbsr &= ~spr_val;
143 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]144 case SPRN_TSR:
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]145 kvmppc_clr_tsr_bits(vcpu, spr_val);
146 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]147 case SPRN_TCR:
Bharat Bhushanf61c94b2012-08-08 20:38:19 +0000[diff] [blame]148 /*
149 * WRC is a 2-bit field that is supposed to preserve its
150 * value once written to non-zero.
151 */
152 if (vcpu->arch.tcr & TCR_WRC_MASK) {
153 spr_val &= ~TCR_WRC_MASK;
154 spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
155 }
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]156 kvmppc_set_tcr(vcpu, spr_val);
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]157 break;
158
Bharat Bhushan21bd0002012-05-20 23:21:23 +0000[diff] [blame]159 case SPRN_DECAR:
160 vcpu->arch.decar = spr_val;
161 break;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]162 /*
163 * Note: SPRG4-7 are user-readable.
164 * These values are loaded into the real SPRGs when resuming the
165 * guest (PR-mode only).
166 */
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]167 case SPRN_SPRG4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]168 vcpu->arch.shared->sprg4 = spr_val;
169 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]170 case SPRN_SPRG5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]171 vcpu->arch.shared->sprg5 = spr_val;
172 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]173 case SPRN_SPRG6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]174 vcpu->arch.shared->sprg6 = spr_val;
175 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]176 case SPRN_SPRG7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]177 vcpu->arch.shared->sprg7 = spr_val;
178 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]179
180 case SPRN_IVPR:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]181 vcpu->arch.ivpr = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]182#ifdef CONFIG_KVM_BOOKE_HV
183 mtspr(SPRN_GIVPR, spr_val);
184#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]185 break;
186 case SPRN_IVOR0:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]187 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]188 break;
189 case SPRN_IVOR1:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]190 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]191 break;
192 case SPRN_IVOR2:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]193 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]194#ifdef CONFIG_KVM_BOOKE_HV
195 mtspr(SPRN_GIVOR2, spr_val);
196#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]197 break;
198 case SPRN_IVOR3:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]199 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]200 break;
201 case SPRN_IVOR4:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]202 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]203 break;
204 case SPRN_IVOR5:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]205 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]206 break;
207 case SPRN_IVOR6:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]208 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]209 break;
210 case SPRN_IVOR7:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]211 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]212 break;
213 case SPRN_IVOR8:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]214 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]215#ifdef CONFIG_KVM_BOOKE_HV
216 mtspr(SPRN_GIVOR8, spr_val);
217#endif
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]218 break;
219 case SPRN_IVOR9:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]220 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]221 break;
222 case SPRN_IVOR10:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]223 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]224 break;
225 case SPRN_IVOR11:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]226 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]227 break;
228 case SPRN_IVOR12:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]229 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]230 break;
231 case SPRN_IVOR13:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]232 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]233 break;
234 case SPRN_IVOR14:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]235 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]236 break;
237 case SPRN_IVOR15:
Alexander Graf8e5b26b2010-01-08 02:58:01 +0100[diff] [blame]238 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]239 break;
Alexander Graf50c871e2012-08-13 14:50:54 +0200[diff] [blame^]240 case SPRN_MCSR:
241 vcpu->arch.mcsr &= ~spr_val;
242 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]243
244 default:
245 emulated = EMULATE_FAIL;
246 }
247
248 return emulated;
249}
250
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]251int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]252{
253 int emulated = EMULATE_DONE;
254
255 switch (sprn) {
256 case SPRN_IVPR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]257 *spr_val = vcpu->arch.ivpr;
258 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]259 case SPRN_DEAR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]260 *spr_val = vcpu->arch.shared->dar;
261 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]262 case SPRN_ESR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]263 *spr_val = vcpu->arch.shared->esr;
264 break;
Bharat Bhushan0c1fc3c2012-06-27 19:37:31 +0000[diff] [blame]265 case SPRN_CSRR0:
266 *spr_val = vcpu->arch.csrr0;
267 break;
268 case SPRN_CSRR1:
269 *spr_val = vcpu->arch.csrr1;
270 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]271 case SPRN_DBCR0:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]272 *spr_val = vcpu->arch.dbg_reg.dbcr0;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]273 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]274 case SPRN_DBCR1:
Bharat Bhushan6df8d3f2012-08-08 21:17:55 +0000[diff] [blame]275 *spr_val = vcpu->arch.dbg_reg.dbcr1;
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]276 break;
Hollis Blanchardf7b200a2009-01-03 16:23:07 -0600[diff] [blame]277 case SPRN_DBSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]278 *spr_val = vcpu->arch.dbsr;
279 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]280 case SPRN_TSR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]281 *spr_val = vcpu->arch.tsr;
282 break;
Scott Wooddfd4d472011-11-17 12:39:59 +0000[diff] [blame]283 case SPRN_TCR:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]284 *spr_val = vcpu->arch.tcr;
285 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]286
287 case SPRN_IVOR0:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]288 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]289 break;
290 case SPRN_IVOR1:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]291 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]292 break;
293 case SPRN_IVOR2:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]294 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]295 break;
296 case SPRN_IVOR3:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]297 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]298 break;
299 case SPRN_IVOR4:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]300 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]301 break;
302 case SPRN_IVOR5:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]303 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]304 break;
305 case SPRN_IVOR6:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]306 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]307 break;
308 case SPRN_IVOR7:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]309 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]310 break;
311 case SPRN_IVOR8:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]312 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]313 break;
314 case SPRN_IVOR9:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]315 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]316 break;
317 case SPRN_IVOR10:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]318 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]319 break;
320 case SPRN_IVOR11:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]321 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]322 break;
323 case SPRN_IVOR12:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]324 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]325 break;
326 case SPRN_IVOR13:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]327 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]328 break;
329 case SPRN_IVOR14:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]330 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]331 break;
332 case SPRN_IVOR15:
Alexander Graf54771e62012-05-04 14:55:12 +0200[diff] [blame]333 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]334 break;
Alexander Graf50c871e2012-08-13 14:50:54 +0200[diff] [blame^]335 case SPRN_MCSR:
336 *spr_val = vcpu->arch.mcsr;
337 break;
Hollis Blanchardd0c7dc02009-01-03 16:23:06 -0600[diff] [blame]338
339 default:
340 emulated = EMULATE_FAIL;
341 }
342
343 return emulated;
344}