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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Damien Lespiau70d21f02013-07-03 21:06:04 +010029#define _PLANE(plane, a, b) _PIPE(plane, a, b)
Paulo Zanonia5c961d2012-10-24 15:59:34 -020030#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030031#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Ville Syrjälä2d401b12014-04-09 13:29:08 +030032#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
Jani Nikulae7d7cad2014-11-14 16:54:21 +020034#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35 (port) == PORT_B ? (b) : (c))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030036
Damien Lespiau98533252014-12-08 17:33:51 +000037#define _MASKED_FIELD(mask, value) ({ \
38 if (__builtin_constant_p(mask)) \
39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40 if (__builtin_constant_p(value)) \
41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
43 BUILD_BUG_ON_MSG((value) & ~(mask), \
44 "Incorrect value for mask"); \
45 (mask) << 16 | (value); })
46#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
48
49
Daniel Vetter6b26c862012-04-24 14:04:12 +020050
Jesse Barnes585fb112008-07-29 11:54:06 -070051/* PCI config space */
52
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030053#define HPLLCC 0xc0 /* 85x only */
54#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070055#define GC_CLOCK_133_200 (0 << 0)
56#define GC_CLOCK_100_200 (1 << 0)
57#define GC_CLOCK_100_133 (2 << 0)
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030058#define GC_CLOCK_133_266 (3 << 0)
59#define GC_CLOCK_133_200_2 (4 << 0)
60#define GC_CLOCK_133_266_2 (5 << 0)
61#define GC_CLOCK_166_266 (6 << 0)
62#define GC_CLOCK_166_250 (7 << 0)
63
Jesse Barnesf97108d2010-01-29 11:27:07 -080064#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070065#define GCFGC 0xf0 /* 915+ only */
66#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
67#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
68#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +020069#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
70#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
71#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
72#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
73#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
74#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070075#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070076#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
77#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
78#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
79#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
80#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
81#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
82#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
83#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
84#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
85#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
86#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
87#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
90#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
91#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
92#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
93#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
94#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Jesse Barnes9f49c372014-12-10 12:16:05 -080095#define GCDGMBUS 0xcc
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +010096#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
97
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070098
99/* Graphics reset regs */
Ville Syrjälä59ea9052014-11-21 21:54:27 +0200100#define I915_GDRST 0xc0 /* PCI config register */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700101#define GRDOM_FULL (0<<2)
102#define GRDOM_RENDER (1<<2)
103#define GRDOM_MEDIA (3<<2)
Jesse Barnes8a5c2ae2013-03-28 13:57:19 -0700104#define GRDOM_MASK (3<<2)
Ville Syrjälä73bbf6b2014-11-21 21:54:25 +0200105#define GRDOM_RESET_STATUS (1<<1)
Daniel Vetter5ccce182012-04-27 15:17:45 +0200106#define GRDOM_RESET_ENABLE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700107
Ville Syrjäläb3a3f032014-05-19 19:23:24 +0300108#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
109#define ILK_GRDOM_FULL (0<<1)
110#define ILK_GRDOM_RENDER (1<<1)
111#define ILK_GRDOM_MEDIA (3<<1)
112#define ILK_GRDOM_MASK (3<<1)
113#define ILK_GRDOM_RESET_ENABLE (1<<0)
114
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700115#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
116#define GEN6_MBC_SNPCR_SHIFT 21
117#define GEN6_MBC_SNPCR_MASK (3<<21)
118#define GEN6_MBC_SNPCR_MAX (0<<21)
119#define GEN6_MBC_SNPCR_MED (1<<21)
120#define GEN6_MBC_SNPCR_LOW (2<<21)
121#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
122
Imre Deak9e72b462014-05-05 15:13:55 +0300123#define VLV_G3DCTL 0x9024
124#define VLV_GSCKGCTL 0x9028
125
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100126#define GEN6_MBCTL 0x0907c
127#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
128#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
129#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
130#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
131#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
132
Eric Anholtcff458c2010-11-18 09:31:14 +0800133#define GEN6_GDRST 0x941c
134#define GEN6_GRDOM_FULL (1 << 0)
135#define GEN6_GRDOM_RENDER (1 << 1)
136#define GEN6_GRDOM_MEDIA (1 << 2)
137#define GEN6_GRDOM_BLT (1 << 3)
138
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100139#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
140#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
141#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
142#define PP_DIR_DCLV_2G 0xffffffff
143
Ben Widawsky94e409c2013-11-04 22:29:36 -0800144#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
145#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
146
Jeff McGee0cea6502015-02-13 10:27:56 -0600147#define GEN8_R_PWR_CLK_STATE 0x20C8
148#define GEN8_RPCS_ENABLE (1 << 31)
149#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
150#define GEN8_RPCS_S_CNT_SHIFT 15
151#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
152#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
153#define GEN8_RPCS_SS_CNT_SHIFT 8
154#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
155#define GEN8_RPCS_EU_MAX_SHIFT 4
156#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
157#define GEN8_RPCS_EU_MIN_SHIFT 0
158#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
159
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100160#define GAM_ECOCHK 0x4090
Damien Lespiau81e231a2015-02-09 19:33:19 +0000161#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100162#define ECOCHK_SNB_BIT (1<<10)
Nick Hoath6381b552015-07-14 14:41:15 +0100163#define ECOCHK_DIS_TLB (1<<8)
Ben Widawskye3dff582013-03-20 14:49:14 -0700164#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100165#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
166#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300167#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
168#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
169#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
170#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
171#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100172
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200173#define GAC_ECO_BITS 0x14090
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300174#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200175#define ECOBITS_PPGTT_CACHE64B (3<<8)
176#define ECOBITS_PPGTT_CACHE4B (0<<8)
177
Daniel Vetterbe901a52012-04-11 20:42:39 +0200178#define GAB_CTL 0x24000
179#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
180
Daniel Vetter40bae732014-09-11 13:28:08 +0200181#define GEN7_BIOS_RESERVED 0x1082C0
182#define GEN7_BIOS_RESERVED_1M (0 << 5)
183#define GEN7_BIOS_RESERVED_256K (1 << 5)
184#define GEN8_BIOS_RESERVED_SHIFT 7
185#define GEN7_BIOS_RESERVED_MASK 0x1
186#define GEN8_BIOS_RESERVED_MASK 0x3
187
188
Jesse Barnes585fb112008-07-29 11:54:06 -0700189/* VGA stuff */
190
191#define VGA_ST01_MDA 0x3ba
192#define VGA_ST01_CGA 0x3da
193
194#define VGA_MSR_WRITE 0x3c2
195#define VGA_MSR_READ 0x3cc
196#define VGA_MSR_MEM_EN (1<<1)
197#define VGA_MSR_CGA_MODE (1<<0)
198
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300199#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100200#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300201#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700202
203#define VGA_AR_INDEX 0x3c0
204#define VGA_AR_VID_EN (1<<5)
205#define VGA_AR_DATA_WRITE 0x3c0
206#define VGA_AR_DATA_READ 0x3c1
207
208#define VGA_GR_INDEX 0x3ce
209#define VGA_GR_DATA 0x3cf
210/* GR05 */
211#define VGA_GR_MEM_READ_MODE_SHIFT 3
212#define VGA_GR_MEM_READ_MODE_PLANE 1
213/* GR06 */
214#define VGA_GR_MEM_MODE_MASK 0xc
215#define VGA_GR_MEM_MODE_SHIFT 2
216#define VGA_GR_MEM_A0000_AFFFF 0
217#define VGA_GR_MEM_A0000_BFFFF 1
218#define VGA_GR_MEM_B0000_B7FFF 2
219#define VGA_GR_MEM_B0000_BFFFF 3
220
221#define VGA_DACMASK 0x3c6
222#define VGA_DACRX 0x3c7
223#define VGA_DACWX 0x3c8
224#define VGA_DACDATA 0x3c9
225
226#define VGA_CR_INDEX_MDA 0x3b4
227#define VGA_CR_DATA_MDA 0x3b5
228#define VGA_CR_INDEX_CGA 0x3d4
229#define VGA_CR_DATA_CGA 0x3d5
230
231/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800232 * Instruction field definitions used by the command parser
233 */
234#define INSTR_CLIENT_SHIFT 29
235#define INSTR_CLIENT_MASK 0xE0000000
236#define INSTR_MI_CLIENT 0x0
237#define INSTR_BC_CLIENT 0x2
238#define INSTR_RC_CLIENT 0x3
239#define INSTR_SUBCLIENT_SHIFT 27
240#define INSTR_SUBCLIENT_MASK 0x18000000
241#define INSTR_MEDIA_SUBCLIENT 0x2
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800242#define INSTR_26_TO_24_MASK 0x7000000
243#define INSTR_26_TO_24_SHIFT 24
Brad Volkin351e3db2014-02-18 10:15:46 -0800244
245/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700246 * Memory interface instructions used by the kernel
247 */
248#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800249/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
250#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700251
252#define MI_NOOP MI_INSTR(0, 0)
253#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
254#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200255#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700256#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
257#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
258#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
259#define MI_FLUSH MI_INSTR(0x04, 0)
260#define MI_READ_FLUSH (1 << 0)
261#define MI_EXE_FLUSH (1 << 1)
262#define MI_NO_WRITE_FLUSH (1 << 2)
263#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
264#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800265#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800266#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
267#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
268#define MI_ARB_ENABLE (1<<0)
269#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700270#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800271#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
272#define MI_SUSPEND_FLUSH_EN (1<<0)
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800273#define MI_SET_APPID MI_INSTR(0x0e, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400274#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200275#define MI_OVERLAY_CONTINUE (0x0<<21)
276#define MI_OVERLAY_ON (0x1<<21)
277#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700278#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500279#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700280#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500281#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200282/* IVB has funny definitions for which plane to flip. */
283#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
284#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
285#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
286#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
287#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
288#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Damien Lespiau830c81d2014-11-13 17:51:46 +0000289/* SKL ones */
290#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
291#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
292#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
293#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
294#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
295#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
296#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
297#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
298#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700299#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
Ben Widawsky0e792842013-12-16 20:50:37 -0800300#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
301#define MI_SEMAPHORE_UPDATE (1<<21)
302#define MI_SEMAPHORE_COMPARE (1<<20)
303#define MI_SEMAPHORE_REGISTER (1<<18)
304#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
305#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
306#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
307#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
308#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
309#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
310#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
311#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
312#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
313#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
314#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
315#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100316#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
317#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800318#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
319#define MI_MM_SPACE_GTT (1<<8)
320#define MI_MM_SPACE_PHYSICAL (0<<8)
321#define MI_SAVE_EXT_STATE_EN (1<<3)
322#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800323#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800324#define MI_RESTORE_INHIBIT (1<<0)
Abdiel Janulgue4c436d552015-06-16 13:39:41 +0300325#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
326#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
Ben Widawsky3e789982014-06-30 09:53:37 -0700327#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
328#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
Ben Widawsky5ee426c2014-06-30 09:53:38 -0700329#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
330#define MI_SEMAPHORE_POLL (1<<15)
331#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
Jesse Barnes585fb112008-07-29 11:54:06 -0700332#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
Ville Syrjälä8edfbb82014-11-14 18:16:56 +0200333#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
334#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
335#define MI_USE_GGTT (1 << 22) /* g4x+ */
Jesse Barnes585fb112008-07-29 11:54:06 -0700336#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
337#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000338/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
339 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
340 * simply ignores the register load under certain conditions.
341 * - One can actually load arbitrary many arbitrary registers: Simply issue x
342 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
343 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100344#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100345#define MI_LRI_FORCE_POSTED (1<<12)
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100346#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
Damien Lespiaub76bfeb2014-04-07 20:24:33 +0100347#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800348#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000349#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700350#define MI_FLUSH_DW_STORE_INDEX (1<<21)
351#define MI_INVALIDATE_TLB (1<<18)
352#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800353#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800354#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700355#define MI_INVALIDATE_BSD (1<<7)
356#define MI_FLUSH_DW_USE_GTT (1<<2)
357#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Arun Siluvery9e000842015-07-03 14:27:31 +0100358#define MI_LOAD_REGISTER_MEM(x) MI_INSTR(0x29, 2*(x)-1)
359#define MI_LOAD_REGISTER_MEM_GEN8(x) MI_INSTR(0x29, 3*(x)-1)
Jesse Barnes585fb112008-07-29 11:54:06 -0700360#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100361#define MI_BATCH_NON_SECURE (1)
362/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800363#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100364#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800365#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700366#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100367#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700368#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Abdiel Janulgue919032e2015-06-16 13:39:40 +0300369#define MI_BATCH_RESOURCE_STREAMER (1<<10)
Ben Widawsky0e792842013-12-16 20:50:37 -0800370
Neil Robertsf1f55cc2014-11-07 19:00:26 +0000371#define MI_PREDICATE_SRC0 (0x2400)
372#define MI_PREDICATE_SRC1 (0x2408)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300373
374#define MI_PREDICATE_RESULT_2 (0x2214)
375#define LOWER_SLICE_ENABLED (1<<0)
376#define LOWER_SLICE_DISABLED (0<<0)
377
Jesse Barnes585fb112008-07-29 11:54:06 -0700378/*
379 * 3D instructions used by the kernel
380 */
381#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
382
383#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
384#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
385#define SC_UPDATE_SCISSOR (0x1<<1)
386#define SC_ENABLE_MASK (0x1<<0)
387#define SC_ENABLE (0x1<<0)
388#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
389#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
390#define SCI_YMIN_MASK (0xffff<<16)
391#define SCI_XMIN_MASK (0xffff<<0)
392#define SCI_YMAX_MASK (0xffff<<16)
393#define SCI_XMAX_MASK (0xffff<<0)
394#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
395#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
396#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
397#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
398#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
399#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
400#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
401#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
402#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100403
404#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
405#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700406#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
407#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100408#define BLT_WRITE_A (2<<20)
409#define BLT_WRITE_RGB (1<<20)
410#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
Jesse Barnes585fb112008-07-29 11:54:06 -0700411#define BLT_DEPTH_8 (0<<24)
412#define BLT_DEPTH_16_565 (1<<24)
413#define BLT_DEPTH_16_1555 (2<<24)
414#define BLT_DEPTH_32 (3<<24)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100415#define BLT_ROP_SRC_COPY (0xcc<<16)
416#define BLT_ROP_COLOR_COPY (0xf0<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700417#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
418#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
419#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
420#define ASYNC_FLIP (1<<22)
421#define DISPLAY_PLANE_A (0<<20)
422#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200423#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Arun Siluvery0160f052015-06-23 15:46:57 +0100424#define PIPE_CONTROL_FLUSH_L3 (1<<27)
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200425#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800426#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800427#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200428#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700429#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Chris Wilson148b83d2014-12-16 08:44:31 +0000430#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200431#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800432#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200433#define PIPE_CONTROL_DEPTH_STALL (1<<13)
434#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200435#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200436#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
437#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
438#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
439#define PIPE_CONTROL_NOTIFY (1<<8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700440#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
Arun Siluveryc82435b2015-06-19 18:37:13 +0100441#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
Jesse Barnes8d315282011-10-16 10:23:31 +0200442#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
443#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
444#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200445#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200446#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700447#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700448
Brad Volkin3a6fa982014-02-18 10:15:47 -0800449/*
450 * Commands used only by the command parser
451 */
452#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
453#define MI_ARB_CHECK MI_INSTR(0x05, 0)
454#define MI_RS_CONTROL MI_INSTR(0x06, 0)
455#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
456#define MI_PREDICATE MI_INSTR(0x0C, 0)
457#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
458#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800459#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800460#define MI_URB_CLEAR MI_INSTR(0x19, 0)
461#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
462#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800463#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
464#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800465#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
466#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
467#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
468#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
469#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
470
471#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
472#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800473#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
474#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800475#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
476#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
477#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
478 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
479#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
480 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
481#define GFX_OP_3DSTATE_SO_DECL_LIST \
482 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
483
484#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
485 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
486#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
487 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
488#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
489 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
490#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
491 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
492#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
493 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
494
495#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
496
497#define COLOR_BLT ((0x2<<29)|(0x40<<22))
498#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100499
500/*
Brad Volkin5947de92014-02-18 10:15:50 -0800501 * Registers used only by the command parser
502 */
503#define BCS_SWCTRL 0x22200
504
Jordan Justenc61200c2014-12-11 13:28:09 -0800505#define GPGPU_THREADS_DISPATCHED 0x2290
506#define HS_INVOCATION_COUNT 0x2300
507#define DS_INVOCATION_COUNT 0x2308
508#define IA_VERTICES_COUNT 0x2310
509#define IA_PRIMITIVES_COUNT 0x2318
510#define VS_INVOCATION_COUNT 0x2320
511#define GS_INVOCATION_COUNT 0x2328
512#define GS_PRIMITIVES_COUNT 0x2330
513#define CL_INVOCATION_COUNT 0x2338
514#define CL_PRIMITIVES_COUNT 0x2340
515#define PS_INVOCATION_COUNT 0x2348
516#define PS_DEPTH_COUNT 0x2350
Brad Volkin5947de92014-02-18 10:15:50 -0800517
518/* There are the 4 64-bit counter registers, one for each stream output */
519#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
520
Brad Volkin113a0472014-04-08 14:18:58 -0700521#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
522
523#define GEN7_3DPRIM_END_OFFSET 0x2420
524#define GEN7_3DPRIM_START_VERTEX 0x2430
525#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
526#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
527#define GEN7_3DPRIM_START_INSTANCE 0x243C
528#define GEN7_3DPRIM_BASE_VERTEX 0x2440
529
Kenneth Graunke180b8132014-03-25 22:52:03 -0700530#define OACONTROL 0x2360
531
Brad Volkin220375a2014-02-18 10:15:51 -0800532#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
533#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
534#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
535 _GEN7_PIPEA_DE_LOAD_SL, \
536 _GEN7_PIPEB_DE_LOAD_SL)
537
Brad Volkin5947de92014-02-18 10:15:50 -0800538/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100539 * Reset registers
540 */
541#define DEBUG_RESET_I830 0x6070
542#define DEBUG_RESET_FULL (1<<7)
543#define DEBUG_RESET_RENDER (1<<8)
544#define DEBUG_RESET_DISPLAY (1<<9)
545
Jesse Barnes57f350b2012-03-28 13:39:25 -0700546/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300547 * IOSF sideband
548 */
549#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
550#define IOSF_DEVFN_SHIFT 24
551#define IOSF_OPCODE_SHIFT 16
552#define IOSF_PORT_SHIFT 8
553#define IOSF_BYTE_ENABLES_SHIFT 4
554#define IOSF_BAR_SHIFT 1
555#define IOSF_SB_BUSY (1<<0)
Jesse Barnesf3419152013-11-04 11:52:44 -0800556#define IOSF_PORT_BUNIT 0x3
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300557#define IOSF_PORT_PUNIT 0x4
558#define IOSF_PORT_NC 0x11
559#define IOSF_PORT_DPIO 0x12
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300560#define IOSF_PORT_DPIO_2 0x1a
Jani Nikulae9f882a2013-08-27 15:12:14 +0300561#define IOSF_PORT_GPIO_NC 0x13
562#define IOSF_PORT_CCK 0x14
563#define IOSF_PORT_CCU 0xA9
564#define IOSF_PORT_GPS_CORE 0x48
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530565#define IOSF_PORT_FLISDSI 0x1B
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300566#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
567#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
568
Jesse Barnes30a970c2013-11-04 13:48:12 -0800569/* See configdb bunit SB addr map */
570#define BUNIT_REG_BISOC 0x11
571
Jesse Barnes30a970c2013-11-04 13:48:12 -0800572#define PUNIT_REG_DSPFREQ 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +0300573#define DSPFREQSTAT_SHIFT_CHV 24
574#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
575#define DSPFREQGUAR_SHIFT_CHV 8
576#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800577#define DSPFREQSTAT_SHIFT 30
578#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
579#define DSPFREQGUAR_SHIFT 14
580#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200581#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
582#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
583#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
Ville Syrjälä26972b02014-06-28 02:04:11 +0300584#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
585#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
586#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
587#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
588#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
589#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
590#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
591#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
592#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
593#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
594#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
595#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +0200596
597/* See the PUNIT HAS v0.8 for the below bits */
598enum punit_power_well {
599 PUNIT_POWER_WELL_RENDER = 0,
600 PUNIT_POWER_WELL_MEDIA = 1,
601 PUNIT_POWER_WELL_DISP2D = 3,
602 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
603 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
604 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
605 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
606 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
607 PUNIT_POWER_WELL_DPIO_RX0 = 10,
608 PUNIT_POWER_WELL_DPIO_RX1 = 11,
Ville Syrjälä5d6f7ea2014-06-28 02:04:08 +0300609 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
Imre Deaka30180a2014-03-04 19:23:02 +0200610
611 PUNIT_POWER_WELL_NUM,
612};
613
Satheeshakrishna M94dd5132015-02-04 13:57:44 +0000614enum skl_disp_power_wells {
615 SKL_DISP_PW_MISC_IO,
616 SKL_DISP_PW_DDI_A_E,
617 SKL_DISP_PW_DDI_B,
618 SKL_DISP_PW_DDI_C,
619 SKL_DISP_PW_DDI_D,
620 SKL_DISP_PW_1 = 14,
621 SKL_DISP_PW_2,
622};
623
624#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
625#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
626
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800627#define PUNIT_REG_PWRGT_CTRL 0x60
628#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +0200629#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
630#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
631#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
632#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
633#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800634
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300635#define PUNIT_REG_GPU_LFM 0xd3
636#define PUNIT_REG_GPU_FREQ_REQ 0xd4
637#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläc8e96272014-11-07 21:33:44 +0200638#define GPLLENABLE (1<<4)
Ville Syrjäläe8474402013-06-26 17:43:24 +0300639#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300640#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -0400641#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300642
643#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
644#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
645
Deepak S095acd52015-01-17 11:05:59 +0530646#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
647#define FB_GFX_FREQ_FUSE_MASK 0xff
648#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
649#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
650#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
651
652#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
653#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
654
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200655#define PUNIT_REG_DDR_SETUP2 0x139
656#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
657#define FORCE_DDR_LOW_FREQ (1 << 1)
658#define FORCE_DDR_HIGH_FREQ (1 << 0)
659
Deepak S2b6b3a02014-05-27 15:59:30 +0530660#define PUNIT_GPU_STATUS_REG 0xdb
661#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
662#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
663#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
664#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
665
666#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
667#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
668#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
669
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300670#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
671#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
672#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
673#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
674#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
675#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
676#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
677#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
678#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
679#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
680
Deepak S3ef62342015-04-29 08:36:24 +0530681#define VLV_TURBO_SOC_OVERRIDE 0x04
682#define VLV_OVERRIDE_EN 1
683#define VLV_SOC_TDP_EN (1 << 1)
684#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
685#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
686
Deepak S31685c22014-07-03 17:33:01 -0400687#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
Deepak S31685c22014-07-03 17:33:01 -0400688
ymohanmabe4fc042013-08-27 23:40:56 +0300689/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800690#define CCK_FUSE_REG 0x8
691#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300692#define CCK_REG_DSI_PLL_FUSE 0x44
693#define CCK_REG_DSI_PLL_CONTROL 0x48
694#define DSI_PLL_VCO_EN (1 << 31)
695#define DSI_PLL_LDO_GATE (1 << 30)
696#define DSI_PLL_P1_POST_DIV_SHIFT 17
697#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
698#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
699#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
700#define DSI_PLL_MUX_MASK (3 << 9)
701#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
702#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
703#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
704#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
705#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
706#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
707#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
708#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
709#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
710#define DSI_PLL_LOCK (1 << 0)
711#define CCK_REG_DSI_PLL_DIVIDER 0x4c
712#define DSI_PLL_LFSR (1 << 31)
713#define DSI_PLL_FRACTION_EN (1 << 30)
714#define DSI_PLL_FRAC_COUNTER_SHIFT 27
715#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
716#define DSI_PLL_USYNC_CNT_SHIFT 18
717#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
718#define DSI_PLL_N1_DIV_SHIFT 16
719#define DSI_PLL_N1_DIV_MASK (3 << 16)
720#define DSI_PLL_M1_DIV_SHIFT 0
721#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800722#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä9cf33db2014-06-13 13:37:48 +0300723#define DISPLAY_TRUNK_FORCE_ON (1 << 17)
724#define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
725#define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
726#define DISPLAY_FREQUENCY_STATUS_SHIFT 8
727#define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +0300728
Ville Syrjälä0e767182014-04-25 20:14:31 +0300729/**
730 * DOC: DPIO
731 *
Imre Deakeee21562015-03-10 21:18:30 +0200732 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
Ville Syrjälä0e767182014-04-25 20:14:31 +0300733 * ports. DPIO is the name given to such a display PHY. These PHYs
734 * don't follow the standard programming model using direct MMIO
735 * registers, and instead their registers must be accessed trough IOSF
736 * sideband. VLV has one such PHY for driving ports B and C, and CHV
737 * adds another PHY for driving port D. Each PHY responds to specific
738 * IOSF-SB port.
739 *
740 * Each display PHY is made up of one or two channels. Each channel
741 * houses a common lane part which contains the PLL and other common
742 * logic. CH0 common lane also contains the IOSF-SB logic for the
743 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
744 * must be running when any DPIO registers are accessed.
745 *
746 * In addition to having their own registers, the PHYs are also
747 * controlled through some dedicated signals from the display
748 * controller. These include PLL reference clock enable, PLL enable,
749 * and CRI clock selection, for example.
750 *
751 * Eeach channel also has two splines (also called data lanes), and
752 * each spline is made up of one Physical Access Coding Sub-Layer
753 * (PCS) block and two TX lanes. So each channel has two PCS blocks
754 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
755 * data/clock pairs depending on the output type.
756 *
757 * Additionally the PHY also contains an AUX lane with AUX blocks
758 * for each channel. This is used for DP AUX communication, but
759 * this fact isn't really relevant for the driver since AUX is
760 * controlled from the display controller side. No DPIO registers
761 * need to be accessed during AUX communication,
762 *
Imre Deakeee21562015-03-10 21:18:30 +0200763 * Generally on VLV/CHV the common lane corresponds to the pipe and
Masanari Iida32197aa2014-10-20 23:53:13 +0900764 * the spline (PCS/TX) corresponds to the port.
Ville Syrjälä0e767182014-04-25 20:14:31 +0300765 *
766 * For dual channel PHY (VLV/CHV):
767 *
768 * pipe A == CMN/PLL/REF CH0
769 *
770 * pipe B == CMN/PLL/REF CH1
771 *
772 * port B == PCS/TX CH0
773 *
774 * port C == PCS/TX CH1
775 *
776 * This is especially important when we cross the streams
777 * ie. drive port B with pipe B, or port C with pipe A.
778 *
779 * For single channel PHY (CHV):
780 *
781 * pipe C == CMN/PLL/REF CH0
782 *
783 * port D == PCS/TX CH0
784 *
Imre Deakeee21562015-03-10 21:18:30 +0200785 * On BXT the entire PHY channel corresponds to the port. That means
786 * the PLL is also now associated with the port rather than the pipe,
787 * and so the clock needs to be routed to the appropriate transcoder.
788 * Port A PLL is directly connected to transcoder EDP and port B/C
789 * PLLs can be routed to any transcoder A/B/C.
790 *
791 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
792 * digital port D (CHV) or port A (BXT).
Ville Syrjälä0e767182014-04-25 20:14:31 +0300793 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300794/*
Imre Deakeee21562015-03-10 21:18:30 +0200795 * Dual channel PHY (VLV/CHV/BXT)
Ville Syrjälä0e767182014-04-25 20:14:31 +0300796 * ---------------------------------
797 * | CH0 | CH1 |
798 * | CMN/PLL/REF | CMN/PLL/REF |
799 * |---------------|---------------| Display PHY
800 * | PCS01 | PCS23 | PCS01 | PCS23 |
801 * |-------|-------|-------|-------|
802 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
803 * ---------------------------------
804 * | DDI0 | DDI1 | DP/HDMI ports
805 * ---------------------------------
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200806 *
Imre Deakeee21562015-03-10 21:18:30 +0200807 * Single channel PHY (CHV/BXT)
Ville Syrjälä0e767182014-04-25 20:14:31 +0300808 * -----------------
809 * | CH0 |
810 * | CMN/PLL/REF |
811 * |---------------| Display PHY
812 * | PCS01 | PCS23 |
813 * |-------|-------|
814 * |TX0|TX1|TX2|TX3|
815 * -----------------
816 * | DDI2 | DP/HDMI port
817 * -----------------
Jesse Barnes57f350b2012-03-28 13:39:25 -0700818 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300819#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300820
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200821#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700822#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
823#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
824#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700825#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700826
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800827#define DPIO_PHY(pipe) ((pipe) >> 1)
828#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
829
Daniel Vetter598fac62013-04-18 22:01:46 +0200830/*
831 * Per pipe/PLL DPIO regs
832 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800833#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -0700834#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200835#define DPIO_POST_DIV_DAC 0
836#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
837#define DPIO_POST_DIV_LVDS1 2
838#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700839#define DPIO_K_SHIFT (24) /* 4 bits */
840#define DPIO_P1_SHIFT (21) /* 3 bits */
841#define DPIO_P2_SHIFT (16) /* 5 bits */
842#define DPIO_N_SHIFT (12) /* 4 bits */
843#define DPIO_ENABLE_CALIBRATION (1<<11)
844#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
845#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800846#define _VLV_PLL_DW3_CH1 0x802c
847#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700848
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800849#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -0700850#define DPIO_REFSEL_OVERRIDE 27
851#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
852#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
853#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530854#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700855#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
856#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800857#define _VLV_PLL_DW5_CH1 0x8034
858#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700859
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800860#define _VLV_PLL_DW7_CH0 0x801c
861#define _VLV_PLL_DW7_CH1 0x803c
862#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700863
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800864#define _VLV_PLL_DW8_CH0 0x8040
865#define _VLV_PLL_DW8_CH1 0x8060
866#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200867
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800868#define VLV_PLL_DW9_BCAST 0xc044
869#define _VLV_PLL_DW9_CH0 0x8044
870#define _VLV_PLL_DW9_CH1 0x8064
871#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200872
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800873#define _VLV_PLL_DW10_CH0 0x8048
874#define _VLV_PLL_DW10_CH1 0x8068
875#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200876
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800877#define _VLV_PLL_DW11_CH0 0x804c
878#define _VLV_PLL_DW11_CH1 0x806c
879#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700880
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800881/* Spec for ref block start counts at DW10 */
882#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +0200883
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800884#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100885
Daniel Vetter598fac62013-04-18 22:01:46 +0200886/*
887 * Per DDI channel DPIO regs
888 */
889
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800890#define _VLV_PCS_DW0_CH0 0x8200
891#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +0200892#define DPIO_PCS_TX_LANE2_RESET (1<<16)
893#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300894#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
895#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800896#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200897
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300898#define _VLV_PCS01_DW0_CH0 0x200
899#define _VLV_PCS23_DW0_CH0 0x400
900#define _VLV_PCS01_DW0_CH1 0x2600
901#define _VLV_PCS23_DW0_CH1 0x2800
902#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
903#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
904
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800905#define _VLV_PCS_DW1_CH0 0x8204
906#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +0300907#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +0200908#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
909#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
910#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
911#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800912#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200913
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300914#define _VLV_PCS01_DW1_CH0 0x204
915#define _VLV_PCS23_DW1_CH0 0x404
916#define _VLV_PCS01_DW1_CH1 0x2604
917#define _VLV_PCS23_DW1_CH1 0x2804
918#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
919#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
920
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800921#define _VLV_PCS_DW8_CH0 0x8220
922#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +0300923#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
924#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800925#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200926
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800927#define _VLV_PCS01_DW8_CH0 0x0220
928#define _VLV_PCS23_DW8_CH0 0x0420
929#define _VLV_PCS01_DW8_CH1 0x2620
930#define _VLV_PCS23_DW8_CH1 0x2820
931#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
932#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200933
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800934#define _VLV_PCS_DW9_CH0 0x8224
935#define _VLV_PCS_DW9_CH1 0x8424
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300936#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
937#define DPIO_PCS_TX2MARGIN_000 (0<<13)
938#define DPIO_PCS_TX2MARGIN_101 (1<<13)
939#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
940#define DPIO_PCS_TX1MARGIN_000 (0<<10)
941#define DPIO_PCS_TX1MARGIN_101 (1<<10)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800942#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200943
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300944#define _VLV_PCS01_DW9_CH0 0x224
945#define _VLV_PCS23_DW9_CH0 0x424
946#define _VLV_PCS01_DW9_CH1 0x2624
947#define _VLV_PCS23_DW9_CH1 0x2824
948#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
949#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
950
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300951#define _CHV_PCS_DW10_CH0 0x8228
952#define _CHV_PCS_DW10_CH1 0x8428
953#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
954#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300955#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
956#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
957#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
958#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
959#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
960#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300961#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
962
Ville Syrjälä1966e592014-04-09 13:29:04 +0300963#define _VLV_PCS01_DW10_CH0 0x0228
964#define _VLV_PCS23_DW10_CH0 0x0428
965#define _VLV_PCS01_DW10_CH1 0x2628
966#define _VLV_PCS23_DW10_CH1 0x2828
967#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
968#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
969
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800970#define _VLV_PCS_DW11_CH0 0x822c
971#define _VLV_PCS_DW11_CH1 0x842c
Ville Syrjälä2e523e92015-04-10 18:21:27 +0300972#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300973#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
974#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
975#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800976#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200977
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300978#define _VLV_PCS01_DW11_CH0 0x022c
979#define _VLV_PCS23_DW11_CH0 0x042c
980#define _VLV_PCS01_DW11_CH1 0x262c
981#define _VLV_PCS23_DW11_CH1 0x282c
Ville Syrjälä142d2ec2014-10-16 20:52:32 +0300982#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
983#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300984
Ville Syrjälä2e523e92015-04-10 18:21:27 +0300985#define _VLV_PCS01_DW12_CH0 0x0230
986#define _VLV_PCS23_DW12_CH0 0x0430
987#define _VLV_PCS01_DW12_CH1 0x2630
988#define _VLV_PCS23_DW12_CH1 0x2830
989#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
990#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
991
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800992#define _VLV_PCS_DW12_CH0 0x8230
993#define _VLV_PCS_DW12_CH1 0x8430
Ville Syrjälä2e523e92015-04-10 18:21:27 +0300994#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
995#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
996#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
997#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
998#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800999#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001000
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001001#define _VLV_PCS_DW14_CH0 0x8238
1002#define _VLV_PCS_DW14_CH1 0x8438
1003#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001004
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001005#define _VLV_PCS_DW23_CH0 0x825c
1006#define _VLV_PCS_DW23_CH1 0x845c
1007#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001008
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001009#define _VLV_TX_DW2_CH0 0x8288
1010#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001011#define DPIO_SWING_MARGIN000_SHIFT 16
1012#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001013#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001014#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001015
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001016#define _VLV_TX_DW3_CH0 0x828c
1017#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001018/* The following bit for CHV phy */
1019#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001020#define DPIO_SWING_MARGIN101_SHIFT 16
1021#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001022#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1023
1024#define _VLV_TX_DW4_CH0 0x8290
1025#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001026#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1027#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +03001028#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1029#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001030#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1031
1032#define _VLV_TX3_DW4_CH0 0x690
1033#define _VLV_TX3_DW4_CH1 0x2a90
1034#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1035
1036#define _VLV_TX_DW5_CH0 0x8294
1037#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +02001038#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001039#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001040
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001041#define _VLV_TX_DW11_CH0 0x82ac
1042#define _VLV_TX_DW11_CH1 0x84ac
1043#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001044
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001045#define _VLV_TX_DW14_CH0 0x82b8
1046#define _VLV_TX_DW14_CH1 0x84b8
1047#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301048
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001049/* CHV dpPhy registers */
1050#define _CHV_PLL_DW0_CH0 0x8000
1051#define _CHV_PLL_DW0_CH1 0x8180
1052#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1053
1054#define _CHV_PLL_DW1_CH0 0x8004
1055#define _CHV_PLL_DW1_CH1 0x8184
1056#define DPIO_CHV_N_DIV_SHIFT 8
1057#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1058#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1059
1060#define _CHV_PLL_DW2_CH0 0x8008
1061#define _CHV_PLL_DW2_CH1 0x8188
1062#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1063
1064#define _CHV_PLL_DW3_CH0 0x800c
1065#define _CHV_PLL_DW3_CH1 0x818c
1066#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1067#define DPIO_CHV_FIRST_MOD (0 << 8)
1068#define DPIO_CHV_SECOND_MOD (1 << 8)
1069#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05301070#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001071#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1072
1073#define _CHV_PLL_DW6_CH0 0x8018
1074#define _CHV_PLL_DW6_CH1 0x8198
1075#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1076#define DPIO_CHV_INT_COEFF_SHIFT 8
1077#define DPIO_CHV_PROP_COEFF_SHIFT 0
1078#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1079
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301080#define _CHV_PLL_DW8_CH0 0x8020
1081#define _CHV_PLL_DW8_CH1 0x81A0
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05301082#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1083#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301084#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1085
1086#define _CHV_PLL_DW9_CH0 0x8024
1087#define _CHV_PLL_DW9_CH1 0x81A4
1088#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05301089#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301090#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1091#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1092
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001093#define _CHV_CMN_DW5_CH0 0x8114
1094#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1095#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1096#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1097#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1098#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1099#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1100#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1101#define CHV_BUFLEFTENA1_MASK (3 << 22)
1102
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001103#define _CHV_CMN_DW13_CH0 0x8134
1104#define _CHV_CMN_DW0_CH1 0x8080
1105#define DPIO_CHV_S1_DIV_SHIFT 21
1106#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1107#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1108#define DPIO_CHV_K_DIV_SHIFT 4
1109#define DPIO_PLL_FREQLOCK (1 << 1)
1110#define DPIO_PLL_LOCK (1 << 0)
1111#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1112
1113#define _CHV_CMN_DW14_CH0 0x8138
1114#define _CHV_CMN_DW1_CH1 0x8084
1115#define DPIO_AFC_RECAL (1 << 14)
1116#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001117#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1118#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1119#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1120#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1121#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1122#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1123#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1124#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001125#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1126
Ville Syrjälä9197c882014-04-09 13:29:05 +03001127#define _CHV_CMN_DW19_CH0 0x814c
1128#define _CHV_CMN_DW6_CH1 0x8098
1129#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1130#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1131
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001132#define CHV_CMN_DW30 0x8178
1133#define DPIO_LRC_BYPASS (1 << 3)
1134
1135#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1136 (lane) * 0x200 + (offset))
1137
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001138#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1139#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1140#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1141#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1142#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1143#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1144#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1145#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1146#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1147#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1148#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001149#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1150#define DPIO_FRC_LATENCY_SHFIT 8
1151#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1152#define DPIO_UPAR_SHIFT 30
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301153
1154/* BXT PHY registers */
1155#define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))
1156
1157#define BXT_P_CR_GT_DISP_PWRON 0x138090
1158#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1159
1160#define _PHY_CTL_FAMILY_EDP 0x64C80
1161#define _PHY_CTL_FAMILY_DDI 0x64C90
1162#define COMMON_RESET_DIS (1 << 31)
1163#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1164 _PHY_CTL_FAMILY_EDP)
1165
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301166/* BXT PHY PLL registers */
1167#define _PORT_PLL_A 0x46074
1168#define _PORT_PLL_B 0x46078
1169#define _PORT_PLL_C 0x4607c
1170#define PORT_PLL_ENABLE (1 << 31)
1171#define PORT_PLL_LOCK (1 << 30)
1172#define PORT_PLL_REF_SEL (1 << 27)
1173#define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1174
1175#define _PORT_PLL_EBB_0_A 0x162034
1176#define _PORT_PLL_EBB_0_B 0x6C034
1177#define _PORT_PLL_EBB_0_C 0x6C340
Imre Deakaa610dc2015-06-22 23:35:52 +03001178#define PORT_PLL_P1_SHIFT 13
1179#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1180#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1181#define PORT_PLL_P2_SHIFT 8
1182#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1183#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301184#define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \
1185 _PORT_PLL_EBB_0_B, \
1186 _PORT_PLL_EBB_0_C)
1187
1188#define _PORT_PLL_EBB_4_A 0x162038
1189#define _PORT_PLL_EBB_4_B 0x6C038
1190#define _PORT_PLL_EBB_4_C 0x6C344
1191#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1192#define PORT_PLL_RECALIBRATE (1 << 14)
1193#define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \
1194 _PORT_PLL_EBB_4_B, \
1195 _PORT_PLL_EBB_4_C)
1196
1197#define _PORT_PLL_0_A 0x162100
1198#define _PORT_PLL_0_B 0x6C100
1199#define _PORT_PLL_0_C 0x6C380
1200/* PORT_PLL_0_A */
1201#define PORT_PLL_M2_MASK 0xFF
1202/* PORT_PLL_1_A */
Imre Deakaa610dc2015-06-22 23:35:52 +03001203#define PORT_PLL_N_SHIFT 8
1204#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1205#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301206/* PORT_PLL_2_A */
1207#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1208/* PORT_PLL_3_A */
1209#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1210/* PORT_PLL_6_A */
1211#define PORT_PLL_PROP_COEFF_MASK 0xF
1212#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1213#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1214#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1215#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1216/* PORT_PLL_8_A */
1217#define PORT_PLL_TARGET_CNT_MASK 0x3FF
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301218/* PORT_PLL_9_A */
Imre Deak05712c12015-06-18 17:25:54 +03001219#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1220#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301221/* PORT_PLL_10_A */
1222#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
Vandana Kannane6292552015-07-01 17:02:57 +05301223#define PORT_PLL_DCO_AMP_DEFAULT 15
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301224#define PORT_PLL_DCO_AMP_MASK 0x3c00
1225#define PORT_PLL_DCO_AMP(x) (x<<10)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301226#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1227 _PORT_PLL_0_B, \
1228 _PORT_PLL_0_C)
1229#define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4)
1230
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301231/* BXT PHY common lane registers */
1232#define _PORT_CL1CM_DW0_A 0x162000
1233#define _PORT_CL1CM_DW0_BC 0x6C000
1234#define PHY_POWER_GOOD (1 << 16)
1235#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1236 _PORT_CL1CM_DW0_A)
1237
1238#define _PORT_CL1CM_DW9_A 0x162024
1239#define _PORT_CL1CM_DW9_BC 0x6C024
1240#define IREF0RC_OFFSET_SHIFT 8
1241#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1242#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1243 _PORT_CL1CM_DW9_A)
1244
1245#define _PORT_CL1CM_DW10_A 0x162028
1246#define _PORT_CL1CM_DW10_BC 0x6C028
1247#define IREF1RC_OFFSET_SHIFT 8
1248#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1249#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1250 _PORT_CL1CM_DW10_A)
1251
1252#define _PORT_CL1CM_DW28_A 0x162070
1253#define _PORT_CL1CM_DW28_BC 0x6C070
1254#define OCL1_POWER_DOWN_EN (1 << 23)
1255#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1256#define SUS_CLK_CONFIG 0x3
1257#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1258 _PORT_CL1CM_DW28_A)
1259
1260#define _PORT_CL1CM_DW30_A 0x162078
1261#define _PORT_CL1CM_DW30_BC 0x6C078
1262#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1263#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1264 _PORT_CL1CM_DW30_A)
1265
1266/* Defined for PHY0 only */
1267#define BXT_PORT_CL2CM_DW6_BC 0x6C358
1268#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1269
1270/* BXT PHY Ref registers */
1271#define _PORT_REF_DW3_A 0x16218C
1272#define _PORT_REF_DW3_BC 0x6C18C
1273#define GRC_DONE (1 << 22)
1274#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1275 _PORT_REF_DW3_A)
1276
1277#define _PORT_REF_DW6_A 0x162198
1278#define _PORT_REF_DW6_BC 0x6C198
1279/*
1280 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1281 * after testing.
1282 */
1283#define GRC_CODE_SHIFT 23
1284#define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
1285#define GRC_CODE_FAST_SHIFT 16
1286#define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
1287#define GRC_CODE_SLOW_SHIFT 8
1288#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1289#define GRC_CODE_NOM_MASK 0xFF
1290#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1291 _PORT_REF_DW6_A)
1292
1293#define _PORT_REF_DW8_A 0x1621A0
1294#define _PORT_REF_DW8_BC 0x6C1A0
1295#define GRC_DIS (1 << 15)
1296#define GRC_RDY_OVRD (1 << 1)
1297#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1298 _PORT_REF_DW8_A)
1299
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301300/* BXT PHY PCS registers */
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301301#define _PORT_PCS_DW10_LN01_A 0x162428
1302#define _PORT_PCS_DW10_LN01_B 0x6C428
1303#define _PORT_PCS_DW10_LN01_C 0x6C828
1304#define _PORT_PCS_DW10_GRP_A 0x162C28
1305#define _PORT_PCS_DW10_GRP_B 0x6CC28
1306#define _PORT_PCS_DW10_GRP_C 0x6CE28
1307#define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \
1308 _PORT_PCS_DW10_LN01_B, \
1309 _PORT_PCS_DW10_LN01_C)
1310#define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \
1311 _PORT_PCS_DW10_GRP_B, \
1312 _PORT_PCS_DW10_GRP_C)
1313#define TX2_SWING_CALC_INIT (1 << 31)
1314#define TX1_SWING_CALC_INIT (1 << 30)
1315
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05301316#define _PORT_PCS_DW12_LN01_A 0x162430
1317#define _PORT_PCS_DW12_LN01_B 0x6C430
1318#define _PORT_PCS_DW12_LN01_C 0x6C830
1319#define _PORT_PCS_DW12_LN23_A 0x162630
1320#define _PORT_PCS_DW12_LN23_B 0x6C630
1321#define _PORT_PCS_DW12_LN23_C 0x6CA30
1322#define _PORT_PCS_DW12_GRP_A 0x162c30
1323#define _PORT_PCS_DW12_GRP_B 0x6CC30
1324#define _PORT_PCS_DW12_GRP_C 0x6CE30
1325#define LANESTAGGER_STRAP_OVRD (1 << 6)
1326#define LANE_STAGGER_MASK 0x1F
1327#define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \
1328 _PORT_PCS_DW12_LN01_B, \
1329 _PORT_PCS_DW12_LN01_C)
1330#define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \
1331 _PORT_PCS_DW12_LN23_B, \
1332 _PORT_PCS_DW12_LN23_C)
1333#define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \
1334 _PORT_PCS_DW12_GRP_B, \
1335 _PORT_PCS_DW12_GRP_C)
1336
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301337/* BXT PHY TX registers */
1338#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1339 ((lane) & 1) * 0x80)
1340
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301341#define _PORT_TX_DW2_LN0_A 0x162508
1342#define _PORT_TX_DW2_LN0_B 0x6C508
1343#define _PORT_TX_DW2_LN0_C 0x6C908
1344#define _PORT_TX_DW2_GRP_A 0x162D08
1345#define _PORT_TX_DW2_GRP_B 0x6CD08
1346#define _PORT_TX_DW2_GRP_C 0x6CF08
1347#define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \
1348 _PORT_TX_DW2_GRP_B, \
1349 _PORT_TX_DW2_GRP_C)
1350#define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \
1351 _PORT_TX_DW2_LN0_B, \
1352 _PORT_TX_DW2_LN0_C)
1353#define MARGIN_000_SHIFT 16
1354#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1355#define UNIQ_TRANS_SCALE_SHIFT 8
1356#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1357
1358#define _PORT_TX_DW3_LN0_A 0x16250C
1359#define _PORT_TX_DW3_LN0_B 0x6C50C
1360#define _PORT_TX_DW3_LN0_C 0x6C90C
1361#define _PORT_TX_DW3_GRP_A 0x162D0C
1362#define _PORT_TX_DW3_GRP_B 0x6CD0C
1363#define _PORT_TX_DW3_GRP_C 0x6CF0C
1364#define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \
1365 _PORT_TX_DW3_GRP_B, \
1366 _PORT_TX_DW3_GRP_C)
1367#define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \
1368 _PORT_TX_DW3_LN0_B, \
1369 _PORT_TX_DW3_LN0_C)
1370#define UNIQE_TRANGE_EN_METHOD (1 << 27)
1371
1372#define _PORT_TX_DW4_LN0_A 0x162510
1373#define _PORT_TX_DW4_LN0_B 0x6C510
1374#define _PORT_TX_DW4_LN0_C 0x6C910
1375#define _PORT_TX_DW4_GRP_A 0x162D10
1376#define _PORT_TX_DW4_GRP_B 0x6CD10
1377#define _PORT_TX_DW4_GRP_C 0x6CF10
1378#define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \
1379 _PORT_TX_DW4_LN0_B, \
1380 _PORT_TX_DW4_LN0_C)
1381#define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \
1382 _PORT_TX_DW4_GRP_B, \
1383 _PORT_TX_DW4_GRP_C)
1384#define DEEMPH_SHIFT 24
1385#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1386
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301387#define _PORT_TX_DW14_LN0_A 0x162538
1388#define _PORT_TX_DW14_LN0_B 0x6C538
1389#define _PORT_TX_DW14_LN0_C 0x6C938
1390#define LATENCY_OPTIM_SHIFT 30
1391#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1392#define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \
1393 _PORT_TX_DW14_LN0_B, \
1394 _PORT_TX_DW14_LN0_C) + \
1395 _BXT_LANE_OFFSET(lane))
1396
David Weinehallf8896f52015-06-25 11:11:03 +03001397/* UAIMI scratch pad register 1 */
1398#define UAIMI_SPR1 0x4F074
1399/* SKL VccIO mask */
1400#define SKL_VCCIO_MASK 0x1
1401/* SKL balance leg register */
1402#define DISPIO_CR_TX_BMU_CR0 0x6C00C
1403/* I_boost values */
1404#define BALANCE_LEG_SHIFT(port) (8+3*(port))
1405#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1406/* Balance leg disable bits */
1407#define BALANCE_LEG_DISABLE_SHIFT 23
1408
Jesse Barnes585fb112008-07-29 11:54:06 -07001409/*
Jesse Barnesde151cf2008-11-12 10:03:55 -08001410 * Fence registers
1411 */
1412#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -07001413#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -08001414#define I830_FENCE_START_MASK 0x07f80000
1415#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -08001416#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001417#define I830_FENCE_PITCH_SHIFT 4
1418#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02001419#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07001420#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001421#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001422
1423#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08001424#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001425
1426#define FENCE_REG_965_0 0x03000
1427#define I965_FENCE_PITCH_SHIFT 2
1428#define I965_FENCE_TILING_Y_SHIFT 1
1429#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001430#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08001431
Eric Anholt4e901fd2009-10-26 16:44:17 -07001432#define FENCE_REG_SANDYBRIDGE_0 0x100000
1433#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03001434#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07001435
Deepak S2b6b3a02014-05-27 15:59:30 +05301436
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001437/* control register for cpu gtt access */
1438#define TILECTL 0x101000
1439#define TILECTL_SWZCTL (1 << 0)
Robert Beckette3a29052015-03-11 10:28:25 +02001440#define TILECTL_TLBPF (1 << 1)
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001441#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1442#define TILECTL_BACKSNOOP_DIS (1 << 3)
1443
Jesse Barnesde151cf2008-11-12 10:03:55 -08001444/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001445 * Instruction and interrupt control regs
1446 */
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03001447#define PGTBL_CTL 0x02020
1448#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1449#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001450#define PGTBL_ER 0x02024
Ville Syrjälä81e7f202014-08-15 01:21:55 +03001451#define PRB0_BASE (0x2030-0x30)
1452#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1453#define PRB2_BASE (0x2050-0x30) /* gen3 */
1454#define SRB0_BASE (0x2100-0x30) /* gen2 */
1455#define SRB1_BASE (0x2110-0x30) /* gen2 */
1456#define SRB2_BASE (0x2120-0x30) /* 830 */
1457#define SRB3_BASE (0x2130-0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02001458#define RENDER_RING_BASE 0x02000
1459#define BSD_RING_BASE 0x04000
1460#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08001461#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -07001462#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +01001463#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +02001464#define RING_TAIL(base) ((base)+0x30)
1465#define RING_HEAD(base) ((base)+0x34)
1466#define RING_START(base) ((base)+0x38)
1467#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001468#define RING_SYNC_0(base) ((base)+0x40)
1469#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawsky1950de12013-05-28 19:22:20 -07001470#define RING_SYNC_2(base) ((base)+0x48)
1471#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1472#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1473#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1474#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1475#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1476#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1477#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1478#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1479#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1480#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1481#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1482#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ben Widawskyad776f82013-05-28 19:22:18 -07001483#define GEN6_NOSYNC 0
Chris Wilson2c550182014-12-16 10:02:27 +00001484#define RING_PSMI_CTL(base) ((base)+0x50)
Chris Wilson8fd26852010-12-08 18:40:43 +00001485#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001486#define RING_HWS_PGA(base) ((base)+0x80)
1487#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Mika Kuoppala7fd2d262015-06-18 12:51:40 +03001488#define RING_RESET_CTL(base) ((base)+0xd0)
1489#define RESET_CTL_REQUEST_RESET (1 << 0)
1490#define RESET_CTL_READY_TO_RESET (1 << 1)
Imre Deak9e72b462014-05-05 15:13:55 +03001491
Ville Syrjälä6d50b062015-05-19 20:32:57 +03001492#define HSW_GTT_CACHE_EN 0x4024
1493#define GTT_CACHE_EN_ALL 0xF0007FFF
Imre Deak9e72b462014-05-05 15:13:55 +03001494#define GEN7_WR_WATERMARK 0x4028
1495#define GEN7_GFX_PRIO_CTRL 0x402C
1496#define ARB_MODE 0x4030
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001497#define ARB_MODE_SWIZZLE_SNB (1<<4)
1498#define ARB_MODE_SWIZZLE_IVB (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03001499#define GEN7_GFX_PEND_TLB0 0x4034
1500#define GEN7_GFX_PEND_TLB1 0x4038
1501/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1502#define GEN7_LRA_LIMITS_BASE 0x403C
1503#define GEN7_LRA_LIMITS_REG_NUM 13
1504#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1505#define GEN7_GFX_MAX_REQ_COUNT 0x4074
1506
Ben Widawsky31a53362013-11-02 21:07:04 -07001507#define GAMTARBMODE 0x04a08
Ben Widawsky4afe8d32013-11-02 21:07:55 -07001508#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07001509#define ARB_MODE_SWIZZLE_BDW (1<<1)
Eric Anholt45930102011-05-06 17:12:35 -07001510#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001511#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -07001512#define RING_FAULT_GTTSEL_MASK (1<<11)
1513#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1514#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1515#define RING_FAULT_VALID (1<<0)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001516#define DONE_REG 0x40b0
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001517#define GEN8_PRIVATE_PAT 0x40e0
Eric Anholt45930102011-05-06 17:12:35 -07001518#define BSD_HWS_PGA_GEN7 (0x04180)
1519#define BLT_HWS_PGA_GEN7 (0x04280)
Ben Widawsky9a8a2212013-05-28 19:22:23 -07001520#define VEBOX_HWS_PGA_GEN7 (0x04380)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001521#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson50877442014-03-21 12:41:53 +00001522#define RING_ACTHD_UDW(base) ((base)+0x5c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001523#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +00001524#define RING_IMR(base) ((base)+0xa8)
Oscar Mateo73d477f2014-07-24 17:04:31 +01001525#define RING_HWSTAM(base) ((base)+0x98)
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001526#define RING_TIMESTAMP(base) ((base)+0x358)
Jesse Barnes585fb112008-07-29 11:54:06 -07001527#define TAIL_ADDR 0x001FFFF8
1528#define HEAD_WRAP_COUNT 0xFFE00000
1529#define HEAD_WRAP_ONE 0x00200000
1530#define HEAD_ADDR 0x001FFFFC
1531#define RING_NR_PAGES 0x001FF000
1532#define RING_REPORT_MASK 0x00000006
1533#define RING_REPORT_64K 0x00000002
1534#define RING_REPORT_128K 0x00000004
1535#define RING_NO_REPORT 0x00000000
1536#define RING_VALID_MASK 0x00000001
1537#define RING_VALID 0x00000001
1538#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01001539#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1540#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001541#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03001542
1543#define GEN7_TLB_RD_ADDR 0x4700
1544
Chris Wilson8168bd42010-11-11 17:54:52 +00001545#if 0
1546#define PRB0_TAIL 0x02030
1547#define PRB0_HEAD 0x02034
1548#define PRB0_START 0x02038
1549#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -07001550#define PRB1_TAIL 0x02040 /* 915+ only */
1551#define PRB1_HEAD 0x02044 /* 915+ only */
1552#define PRB1_START 0x02048 /* 915+ only */
1553#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00001554#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001555#define IPEIR_I965 0x02064
1556#define IPEHR_I965 0x02068
1557#define INSTDONE_I965 0x0206c
Ben Widawskyd53bd482012-08-22 11:32:14 -07001558#define GEN7_INSTDONE_1 0x0206c
1559#define GEN7_SC_INSTDONE 0x07100
1560#define GEN7_SAMPLER_INSTDONE 0x0e160
1561#define GEN7_ROW_INSTDONE 0x0e164
1562#define I915_NUM_INSTDONE_REG 4
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001563#define RING_IPEIR(base) ((base)+0x64)
1564#define RING_IPEHR(base) ((base)+0x68)
1565#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001566#define RING_INSTPS(base) ((base)+0x70)
1567#define RING_DMA_FADD(base) ((base)+0x78)
Ben Widawsky13ffadd2014-04-01 16:31:07 -07001568#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001569#define RING_INSTPM(base) ((base)+0xc0)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301570#define RING_MI_MODE(base) ((base)+0x9c)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001571#define INSTPS 0x02070 /* 965+ only */
1572#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001573#define ACTHD_I965 0x02074
1574#define HWS_PGA 0x02080
1575#define HWS_ADDRESS_MASK 0xfffff000
1576#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -07001577#define PWRCTXA 0x2088 /* 965GM+ only */
1578#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001579#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001580#define IPEHR 0x0208c
1581#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -07001582#define NOPID 0x02094
1583#define HWSTAM 0x02098
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001584#define DMA_FADD_I8XX 0x020d0
Chris Wilson94e39e22013-10-30 09:28:22 +00001585#define RING_BBSTATE(base) ((base)+0x110)
Ville Syrjälä3dda20a2013-12-10 21:44:43 +02001586#define RING_BBADDR(base) ((base)+0x140)
1587#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08001588
Chris Wilsonf4068392010-10-27 20:36:41 +01001589#define ERROR_GEN6 0x040a0
Ben Widawsky71e172e2012-08-20 16:15:13 -07001590#define GEN7_ERR_INT 0x44040
Paulo Zanonide032bf2013-04-12 17:57:58 -03001591#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03001592#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001593#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03001594#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001595#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03001596#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001597#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001598#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03001599#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Daniel Vetter7336df62013-07-09 22:59:16 +02001600#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01001601
Mika Kuoppala6c826f32015-03-24 14:54:19 +02001602#define GEN8_FAULT_TLB_DATA0 0x04b10
1603#define GEN8_FAULT_TLB_DATA1 0x04b14
1604
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03001605#define FPGA_DBG 0x42300
1606#define FPGA_DBG_RM_NOCLAIM (1<<31)
1607
Chris Wilson0f3b6842013-01-15 12:05:55 +00001608#define DERRMR 0x44050
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001609/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01001610#define DERRMR_PIPEA_SCANLINE (1<<0)
1611#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1612#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1613#define DERRMR_PIPEA_VBLANK (1<<3)
1614#define DERRMR_PIPEA_HBLANK (1<<5)
1615#define DERRMR_PIPEB_SCANLINE (1<<8)
1616#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1617#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1618#define DERRMR_PIPEB_VBLANK (1<<11)
1619#define DERRMR_PIPEB_HBLANK (1<<13)
1620/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1621#define DERRMR_PIPEC_SCANLINE (1<<14)
1622#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1623#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1624#define DERRMR_PIPEC_VBLANK (1<<21)
1625#define DERRMR_PIPEC_HBLANK (1<<22)
1626
Chris Wilson0f3b6842013-01-15 12:05:55 +00001627
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001628/* GM45+ chicken bits -- debug workaround bits that may be required
1629 * for various sorts of correct behavior. The top 16 bits of each are
1630 * the enables for writing to the corresponding low bit.
1631 */
1632#define _3D_CHICKEN 0x02084
Daniel Vetter42839082012-12-14 23:38:28 +01001633#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001634#define _3D_CHICKEN2 0x0208c
1635/* Disables pipelining of read flushes past the SF-WIZ interface.
1636 * Required on all Ironlake steppings according to the B-Spec, but the
1637 * particular danger of not doing so is not specified.
1638 */
1639# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1640#define _3D_CHICKEN3 0x02090
Jesse Barnes87f80202012-10-02 17:43:41 -05001641#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07001642#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02001643#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1644#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001645
Eric Anholt71cf39b2010-03-08 23:41:55 -08001646#define MI_MODE 0x0209c
1647# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08001648# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00001649# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301650# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01001651# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001652
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001653#define GEN6_GT_MODE 0x20d0
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02001654#define GEN7_GT_MODE 0x7008
Ville Syrjälä8d85d272014-02-04 21:59:15 +02001655#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1656#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1657#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1658#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
Damien Lespiau98533252014-12-08 17:33:51 +00001659#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001660#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Damien Lespiaub7668792015-02-14 18:30:29 +00001661#define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2))
1662#define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2))
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001663
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001664#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -07001665#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +01001666#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001667#define GFX_RUN_LIST_ENABLE (1<<15)
Chris Wilsonaa83e302014-03-21 17:18:54 +00001668#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001669#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1670#define GFX_REPLAY_MODE (1<<11)
1671#define GFX_PSMI_GRANULARITY (1<<10)
1672#define GFX_PPGTT_ENABLE (1<<9)
1673
Daniel Vettera7e806d2012-07-11 16:27:55 +02001674#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301675#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Daniel Vettera7e806d2012-07-11 16:27:55 +02001676
Imre Deak9e72b462014-05-05 15:13:55 +03001677#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1678#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
Jesse Barnes585fb112008-07-29 11:54:06 -07001679#define SCPD0 0x0209c /* 915+ only */
1680#define IER 0x020a0
1681#define IIR 0x020a4
1682#define IMR 0x020a8
1683#define ISR 0x020ac
Ville Syrjälä07ec7ec2013-01-24 15:29:51 +02001684#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001685#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07001686#define GCFG_DIS (1<<8)
Imre Deak9e72b462014-05-05 15:13:55 +03001687#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
Ville Syrjäläff763012013-01-24 15:29:52 +02001688#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1689#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1690#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1691#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1692#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001693#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05301694#define VLV_PCBR_ADDR_SHIFT 12
1695
Ville Syrjälä90a72f82013-02-19 23:16:44 +02001696#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001697#define EIR 0x020b0
1698#define EMR 0x020b4
1699#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001700#define GM45_ERROR_PAGE_TABLE (1<<5)
1701#define GM45_ERROR_MEM_PRIV (1<<4)
1702#define I915_ERROR_PAGE_TABLE (1<<4)
1703#define GM45_ERROR_CP_PRIV (1<<3)
1704#define I915_ERROR_MEMORY_REFRESH (1<<1)
1705#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001706#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +08001707#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02001708#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00001709 will not assert AGPBUSY# and will only
1710 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08001711#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01001712#define INSTPM_TLB_INVALIDATE (1<<9)
1713#define INSTPM_SYNC_FLUSH (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001714#define ACTHD 0x020c8
Ville Syrjälä10383922014-08-15 01:21:54 +03001715#define MEM_MODE 0x020cc
1716#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1717#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1718#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001719#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +00001720#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -07001721#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08001722#define FW_BLC_SELF_EN_MASK (1<<31)
1723#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1724#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001725#define MM_BURST_LENGTH 0x00700000
1726#define MM_FIFO_WATERMARK 0x0001F000
1727#define LM_BURST_LENGTH 0x00000700
1728#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -07001729#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07001730
1731/* Make render/texture TLB fetches lower priorty than associated data
1732 * fetches. This is not turned on by default
1733 */
1734#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1735
1736/* Isoch request wait on GTT enable (Display A/B/C streams).
1737 * Make isoch requests stall on the TLB update. May cause
1738 * display underruns (test mode only)
1739 */
1740#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1741
1742/* Block grant count for isoch requests when block count is
1743 * set to a finite value.
1744 */
1745#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1746#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1747#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1748#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1749#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1750
1751/* Enable render writes to complete in C2/C3/C4 power states.
1752 * If this isn't enabled, render writes are prevented in low
1753 * power states. That seems bad to me.
1754 */
1755#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1756
1757/* This acknowledges an async flip immediately instead
1758 * of waiting for 2TLB fetches.
1759 */
1760#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1761
1762/* Enables non-sequential data reads through arbiter
1763 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001764#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07001765
1766/* Disable FSB snooping of cacheable write cycles from binner/render
1767 * command stream
1768 */
1769#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1770
1771/* Arbiter time slice for non-isoch streams */
1772#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1773#define MI_ARB_TIME_SLICE_1 (0 << 5)
1774#define MI_ARB_TIME_SLICE_2 (1 << 5)
1775#define MI_ARB_TIME_SLICE_4 (2 << 5)
1776#define MI_ARB_TIME_SLICE_6 (3 << 5)
1777#define MI_ARB_TIME_SLICE_8 (4 << 5)
1778#define MI_ARB_TIME_SLICE_10 (5 << 5)
1779#define MI_ARB_TIME_SLICE_14 (6 << 5)
1780#define MI_ARB_TIME_SLICE_16 (7 << 5)
1781
1782/* Low priority grace period page size */
1783#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1784#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1785
1786/* Disable display A/B trickle feed */
1787#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1788
1789/* Set display plane priority */
1790#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1791#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1792
Ville Syrjälä54e472a2014-02-25 15:13:40 +02001793#define MI_STATE 0x020e4 /* gen2 only */
1794#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1795#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1796
Jesse Barnes585fb112008-07-29 11:54:06 -07001797#define CACHE_MODE_0 0x02120 /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02001798#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001799#define CM0_IZ_OPT_DISABLE (1<<6)
1800#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02001801#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001802#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1803#define CM0_COLOR_EVICT_DISABLE (1<<3)
1804#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1805#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1806#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001807#define GFX_FLSH_CNTL_GEN6 0x101008
1808#define GFX_FLSH_CNTL_EN (1<<0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07001809#define ECOSKPD 0x021d0
1810#define ECO_GATING_CX_ONLY (1<<3)
1811#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001812
Chia-I Wufe27c602014-01-28 13:29:33 +08001813#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05301814#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08001815#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Jesse Barnesfb046852012-03-28 13:39:26 -07001816#define CACHE_MODE_1 0x7004 /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00001817#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1818#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Damien Lespiau9370cd92015-02-09 19:33:17 +00001819#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
Jesse Barnesfb046852012-03-28 13:39:26 -07001820
Jesse Barnes4efe0702011-01-18 11:25:41 -08001821#define GEN6_BLITTER_ECOSKPD 0x221d0
1822#define GEN6_BLITTER_LOCK_SHIFT 16
1823#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1824
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001825#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
Chris Wilson2c550182014-12-16 10:02:27 +00001826#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001827#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001828#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001829
Deepak S693d11c2015-01-16 20:42:16 +05301830/* Fuse readout registers for GT */
1831#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
Jeff McGeec93043a2015-02-27 12:12:28 -08001832#define CHV_FGT_DISABLE_SS0 (1 << 10)
1833#define CHV_FGT_DISABLE_SS1 (1 << 11)
Deepak S693d11c2015-01-16 20:42:16 +05301834#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1835#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1836#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1837#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1838#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1839#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1840#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1841#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1842
Jeff McGee38732182015-02-13 10:27:54 -06001843#define GEN8_FUSE2 0x9120
1844#define GEN8_F2_S_ENA_SHIFT 25
1845#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
1846
1847#define GEN9_F2_SS_DIS_SHIFT 20
1848#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1849
Jeff McGeedead16e2015-04-03 18:13:16 -07001850#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
Jeff McGee38732182015-02-13 10:27:54 -06001851
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001852#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
Chris Wilson12f55812012-07-05 17:14:01 +01001853#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1854#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1855#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1856#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001857
Ben Widawskycc609d52013-05-28 19:22:29 -07001858/* On modern GEN architectures interrupt control consists of two sets
1859 * of registers. The first set pertains to the ring generating the
1860 * interrupt. The second control is for the functional block generating the
1861 * interrupt. These are PM, GT, DE, etc.
1862 *
1863 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1864 * GT interrupt bits, so we don't need to duplicate the defines.
1865 *
1866 * These defines should cover us well from SNB->HSW with minor exceptions
1867 * it can also work on ILK.
1868 */
1869#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1870#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1871#define GT_BLT_USER_INTERRUPT (1 << 22)
1872#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1873#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001874#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Oscar Mateo73d477f2014-07-24 17:04:31 +01001875#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001876#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1877#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1878#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1879#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1880#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1881#define GT_RENDER_USER_INTERRUPT (1 << 0)
1882
Ben Widawsky12638c52013-05-28 19:22:31 -07001883#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1884#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1885
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001886#define GT_PARITY_ERROR(dev) \
1887 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +03001888 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001889
Ben Widawskycc609d52013-05-28 19:22:29 -07001890/* These are all the "old" interrupts */
1891#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001892
1893#define I915_PM_INTERRUPT (1<<31)
1894#define I915_ISP_INTERRUPT (1<<22)
1895#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1896#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02001897#define I915_MIPIC_INTERRUPT (1<<19)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001898#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07001899#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1900#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001901#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1902#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07001903#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001904#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07001905#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001906#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07001907#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001908#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07001909#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001910#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07001911#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001912#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07001913#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001914#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07001915#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001916#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001917#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1918#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1919#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1920#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1921#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001922#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1923#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07001924#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001925#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07001926#define I915_USER_INTERRUPT (1<<1)
1927#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001928#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001929
1930#define GEN6_BSD_RNCID 0x12198
1931
Ben Widawskya1e969e2012-04-14 18:41:32 -07001932#define GEN7_FF_THREAD_MODE 0x20a0
1933#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08001934#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001935#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1936#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1937#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1938#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08001939#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001940#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1941#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1942#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1943#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1944#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1945#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1946#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1947#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1948
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001949/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001950 * Framebuffer compression (915+ only)
1951 */
1952
1953#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1954#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1955#define FBC_CONTROL 0x03208
1956#define FBC_CTL_EN (1<<31)
1957#define FBC_CTL_PERIODIC (1<<30)
1958#define FBC_CTL_INTERVAL_SHIFT (16)
1959#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02001960#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07001961#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001962#define FBC_CTL_FENCENO_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001963#define FBC_COMMAND 0x0320c
1964#define FBC_CMD_COMPRESS (1<<0)
1965#define FBC_STATUS 0x03210
1966#define FBC_STAT_COMPRESSING (1<<31)
1967#define FBC_STAT_COMPRESSED (1<<30)
1968#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001969#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001970#define FBC_CONTROL2 0x03214
1971#define FBC_CTL_FENCE_DBL (0<<4)
1972#define FBC_CTL_IDLE_IMM (0<<2)
1973#define FBC_CTL_IDLE_FULL (1<<2)
1974#define FBC_CTL_IDLE_LINE (2<<2)
1975#define FBC_CTL_IDLE_DEBUG (3<<2)
1976#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001977#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf64f1722014-01-23 16:49:17 +02001978#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
Jesse Barnes80824002009-09-10 15:28:06 -07001979#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -07001980
Paulo Zanoni31b9df12015-06-12 14:36:18 -03001981#define FBC_STATUS2 0x43214
1982#define FBC_COMPRESSION_MASK 0x7ff
1983
Jesse Barnes585fb112008-07-29 11:54:06 -07001984#define FBC_LL_SIZE (1536)
1985
Jesse Barnes74dff282009-09-14 15:39:40 -07001986/* Framebuffer compression for GM45+ */
1987#define DPFC_CB_BASE 0x3200
1988#define DPFC_CONTROL 0x3208
1989#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001990#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1991#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07001992#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001993#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01001994#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07001995#define DPFC_SR_EN (1<<10)
1996#define DPFC_CTL_LIMIT_1X (0<<6)
1997#define DPFC_CTL_LIMIT_2X (1<<6)
1998#define DPFC_CTL_LIMIT_4X (2<<6)
1999#define DPFC_RECOMP_CTL 0x320c
2000#define DPFC_RECOMP_STALL_EN (1<<27)
2001#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2002#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2003#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2004#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2005#define DPFC_STATUS 0x3210
2006#define DPFC_INVAL_SEG_SHIFT (16)
2007#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2008#define DPFC_COMP_SEG_SHIFT (0)
2009#define DPFC_COMP_SEG_MASK (0x000003ff)
2010#define DPFC_STATUS2 0x3214
2011#define DPFC_FENCE_YOFF 0x3218
2012#define DPFC_CHICKEN 0x3224
2013#define DPFC_HT_MODIFY (1<<31)
2014
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002015/* Framebuffer compression for Ironlake */
2016#define ILK_DPFC_CB_BASE 0x43200
2017#define ILK_DPFC_CONTROL 0x43208
Rodrigo Vivida46f932014-08-01 02:04:45 -07002018#define FBC_CTL_FALSE_COLOR (1<<10)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002019/* The bit 28-8 is reserved */
2020#define DPFC_RESERVED (0x1FFFFF00)
2021#define ILK_DPFC_RECOMP_CTL 0x4320c
2022#define ILK_DPFC_STATUS 0x43210
2023#define ILK_DPFC_FENCE_YOFF 0x43218
2024#define ILK_DPFC_CHICKEN 0x43224
2025#define ILK_FBC_RT_BASE 0x2128
2026#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002027#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002028
2029#define ILK_DISPLAY_CHICKEN1 0x42000
2030#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04002031#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08002032
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002033
Jesse Barnes585fb112008-07-29 11:54:06 -07002034/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002035 * Framebuffer compression for Sandybridge
2036 *
2037 * The following two registers are of type GTTMMADR
2038 */
2039#define SNB_DPFC_CTL_SA 0x100100
2040#define SNB_CPU_FENCE_ENABLE (1<<29)
2041#define DPFC_CPU_FENCE_OFFSET 0x100104
2042
Rodrigo Viviabe959c2013-05-06 19:37:33 -03002043/* Framebuffer compression for Ivybridge */
2044#define IVB_FBC_RT_BASE 0x7020
2045
Paulo Zanoni42db64e2013-05-31 16:33:22 -03002046#define IPS_CTL 0x43408
2047#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002048
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03002049#define MSG_FBC_REND_STATE 0x50380
2050#define FBC_REND_NUKE (1<<2)
2051#define FBC_REND_CACHE_CLEAN (1<<1)
2052
Yuanhan Liu9c04f012010-12-15 15:42:32 +08002053/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002054 * GPIO regs
2055 */
2056#define GPIOA 0x5010
2057#define GPIOB 0x5014
2058#define GPIOC 0x5018
2059#define GPIOD 0x501c
2060#define GPIOE 0x5020
2061#define GPIOF 0x5024
2062#define GPIOG 0x5028
2063#define GPIOH 0x502c
2064# define GPIO_CLOCK_DIR_MASK (1 << 0)
2065# define GPIO_CLOCK_DIR_IN (0 << 1)
2066# define GPIO_CLOCK_DIR_OUT (1 << 1)
2067# define GPIO_CLOCK_VAL_MASK (1 << 2)
2068# define GPIO_CLOCK_VAL_OUT (1 << 3)
2069# define GPIO_CLOCK_VAL_IN (1 << 4)
2070# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2071# define GPIO_DATA_DIR_MASK (1 << 8)
2072# define GPIO_DATA_DIR_IN (0 << 9)
2073# define GPIO_DATA_DIR_OUT (1 << 9)
2074# define GPIO_DATA_VAL_MASK (1 << 10)
2075# define GPIO_DATA_VAL_OUT (1 << 11)
2076# define GPIO_DATA_VAL_IN (1 << 12)
2077# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2078
Chris Wilsonf899fc62010-07-20 15:44:45 -07002079#define GMBUS0 0x5100 /* clock/port select */
2080#define GMBUS_RATE_100KHZ (0<<8)
2081#define GMBUS_RATE_50KHZ (1<<8)
2082#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2083#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2084#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
Jani Nikula988c7012015-03-27 00:20:19 +02002085#define GMBUS_PIN_DISABLED 0
2086#define GMBUS_PIN_SSC 1
2087#define GMBUS_PIN_VGADDC 2
2088#define GMBUS_PIN_PANEL 3
2089#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2090#define GMBUS_PIN_DPC 4 /* HDMIC */
2091#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2092#define GMBUS_PIN_DPD 6 /* HDMID */
2093#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
Jani Nikula4c272832015-04-01 10:58:05 +03002094#define GMBUS_PIN_1_BXT 1
2095#define GMBUS_PIN_2_BXT 2
2096#define GMBUS_PIN_3_BXT 3
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03002097#define GMBUS_NUM_PINS 7 /* including 0 */
Chris Wilsonf899fc62010-07-20 15:44:45 -07002098#define GMBUS1 0x5104 /* command/status */
2099#define GMBUS_SW_CLR_INT (1<<31)
2100#define GMBUS_SW_RDY (1<<30)
2101#define GMBUS_ENT (1<<29) /* enable timeout */
2102#define GMBUS_CYCLE_NONE (0<<25)
2103#define GMBUS_CYCLE_WAIT (1<<25)
2104#define GMBUS_CYCLE_INDEX (2<<25)
2105#define GMBUS_CYCLE_STOP (4<<25)
2106#define GMBUS_BYTE_COUNT_SHIFT 16
Dmitry Torokhov9535c472015-04-21 09:49:11 -07002107#define GMBUS_BYTE_COUNT_MAX 256U
Chris Wilsonf899fc62010-07-20 15:44:45 -07002108#define GMBUS_SLAVE_INDEX_SHIFT 8
2109#define GMBUS_SLAVE_ADDR_SHIFT 1
2110#define GMBUS_SLAVE_READ (1<<0)
2111#define GMBUS_SLAVE_WRITE (0<<0)
2112#define GMBUS2 0x5108 /* status */
2113#define GMBUS_INUSE (1<<15)
2114#define GMBUS_HW_WAIT_PHASE (1<<14)
2115#define GMBUS_STALL_TIMEOUT (1<<13)
2116#define GMBUS_INT (1<<12)
2117#define GMBUS_HW_RDY (1<<11)
2118#define GMBUS_SATOER (1<<10)
2119#define GMBUS_ACTIVE (1<<9)
2120#define GMBUS3 0x510c /* data buffer bytes 3-0 */
2121#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
2122#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2123#define GMBUS_NAK_EN (1<<3)
2124#define GMBUS_IDLE_EN (1<<2)
2125#define GMBUS_HW_WAIT_EN (1<<1)
2126#define GMBUS_HW_RDY_EN (1<<0)
2127#define GMBUS5 0x5120 /* byte index */
2128#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08002129
Jesse Barnes585fb112008-07-29 11:54:06 -07002130/*
2131 * Clock control & power management
2132 */
Ville Syrjälä2d401b12014-04-09 13:29:08 +03002133#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2134#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2135#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2136#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07002137
2138#define VGA0 0x6000
2139#define VGA1 0x6004
2140#define VGA_PD 0x6010
2141#define VGA0_PD_P2_DIV_4 (1 << 7)
2142#define VGA0_PD_P1_DIV_2 (1 << 5)
2143#define VGA0_PD_P1_SHIFT 0
2144#define VGA0_PD_P1_MASK (0x1f << 0)
2145#define VGA1_PD_P2_DIV_4 (1 << 15)
2146#define VGA1_PD_P1_DIV_2 (1 << 13)
2147#define VGA1_PD_P1_SHIFT 8
2148#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07002149#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02002150#define DPLL_SDVO_HIGH_SPEED (1 << 30)
2151#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07002152#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07002153#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03002154#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07002155#define DPLL_VGA_MODE_DIS (1 << 28)
2156#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2157#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2158#define DPLL_MODE_MASK (3 << 26)
2159#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2160#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2161#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2162#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2163#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2164#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002165#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07002166#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02002167#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03002168#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2169#define DPLL_SSC_REF_CLK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02002170#define DPLL_PORTC_READY_MASK (0xf << 4)
2171#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07002172
Jesse Barnes585fb112008-07-29 11:54:06 -07002173#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03002174
2175/* Additional CHV pll/phy registers */
2176#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
2177#define DPLL_PORTD_READY_MASK (0xf)
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03002178#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
Ville Syrjäläbc284542015-05-26 20:22:38 +03002179#define PHY_LDO_DELAY_0NS 0x0
2180#define PHY_LDO_DELAY_200NS 0x1
2181#define PHY_LDO_DELAY_600NS 0x2
2182#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
Ville Syrjälä70722462015-04-10 18:21:28 +03002183#define PHY_CH_SU_PSR 0x1
2184#define PHY_CH_DEEP_PSR 0x7
2185#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2186#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03002187#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03002188#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03002189
Jesse Barnes585fb112008-07-29 11:54:06 -07002190/*
2191 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2192 * this field (only one bit may be set).
2193 */
2194#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2195#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002196#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07002197/* i830, required in DVO non-gang */
2198#define PLL_P2_DIVIDE_BY_4 (1 << 23)
2199#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2200#define PLL_REF_INPUT_DREFCLK (0 << 13)
2201#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2202#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2203#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2204#define PLL_REF_INPUT_MASK (3 << 13)
2205#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002206/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08002207# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2208# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2209# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2210# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2211# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2212
Jesse Barnes585fb112008-07-29 11:54:06 -07002213/*
2214 * Parallel to Serial Load Pulse phase selection.
2215 * Selects the phase for the 10X DPLL clock for the PCIe
2216 * digital display port. The range is 4 to 13; 10 or more
2217 * is just a flip delay. The default is 6
2218 */
2219#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2220#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2221/*
2222 * SDVO multiplier for 945G/GM. Not used on 965.
2223 */
2224#define SDVO_MULTIPLIER_MASK 0x000000ff
2225#define SDVO_MULTIPLIER_SHIFT_HIRES 4
2226#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002227
Ville Syrjälä2d401b12014-04-09 13:29:08 +03002228#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2229#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2230#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2231#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002232
Jesse Barnes585fb112008-07-29 11:54:06 -07002233/*
2234 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2235 *
2236 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2237 */
2238#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2239#define DPLL_MD_UDI_DIVIDER_SHIFT 24
2240/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2241#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2242#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2243/*
2244 * SDVO/UDI pixel multiplier.
2245 *
2246 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2247 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2248 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2249 * dummy bytes in the datastream at an increased clock rate, with both sides of
2250 * the link knowing how many bytes are fill.
2251 *
2252 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2253 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2254 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2255 * through an SDVO command.
2256 *
2257 * This register field has values of multiplication factor minus 1, with
2258 * a maximum multiplier of 5 for SDVO.
2259 */
2260#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2261#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2262/*
2263 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2264 * This best be set to the default value (3) or the CRT won't work. No,
2265 * I don't entirely understand what this does...
2266 */
2267#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2268#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07002269
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002270#define _FPA0 0x06040
2271#define _FPA1 0x06044
2272#define _FPB0 0x06048
2273#define _FPB1 0x0604c
2274#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
2275#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07002276#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002277#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07002278#define FP_N_DIV_SHIFT 16
2279#define FP_M1_DIV_MASK 0x00003f00
2280#define FP_M1_DIV_SHIFT 8
2281#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002282#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07002283#define FP_M2_DIV_SHIFT 0
2284#define DPLL_TEST 0x606c
2285#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2286#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2287#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2288#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2289#define DPLLB_TEST_N_BYPASS (1 << 19)
2290#define DPLLB_TEST_M_BYPASS (1 << 18)
2291#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2292#define DPLLA_TEST_N_BYPASS (1 << 3)
2293#define DPLLA_TEST_M_BYPASS (1 << 2)
2294#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2295#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +01002296#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07002297#define DSTATE_PLL_D3_OFF (1<<3)
2298#define DSTATE_GFX_CLOCK_GATING (1<<1)
2299#define DSTATE_DOT_CLOCK_GATING (1<<0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002300#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07002301# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2302# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2303# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2304# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2305# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2306# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2307# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2308# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2309# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2310# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2311# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2312# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2313# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2314# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2315# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2316# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2317# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2318# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2319# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2320# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2321# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2322# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2323# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2324# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2325# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2326# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2327# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2328# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002329/*
Jesse Barnes652c3932009-08-17 13:31:43 -07002330 * This bit must be set on the 830 to prevent hangs when turning off the
2331 * overlay scaler.
2332 */
2333# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2334# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2335# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2336# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2337# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2338
2339#define RENCLK_GATE_D1 0x6204
2340# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2341# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2342# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2343# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2344# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2345# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2346# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2347# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2348# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002349/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07002350# define MECI_CLOCK_GATE_DISABLE (1 << 4)
2351# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2352# define MEC_CLOCK_GATE_DISABLE (1 << 2)
2353# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002354/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07002355# define SV_CLOCK_GATE_DISABLE (1 << 0)
2356# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2357# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2358# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2359# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2360# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2361# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2362# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2363# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2364# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2365# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2366# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2367# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2368# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2369# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2370# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2371# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2372# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2373
2374# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002375/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07002376# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2377# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2378# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2379# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2380# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2381# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002382/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07002383# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2384# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2385# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2386# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2387# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2388# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2389# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2390# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2391# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2392# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2393# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2394# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2395# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2396# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2397# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2398# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2399# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2400# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2401# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2402
2403#define RENCLK_GATE_D2 0x6208
2404#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2405#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2406#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03002407
2408#define VDECCLK_GATE_D 0x620C /* g4x only */
2409#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2410
Jesse Barnes652c3932009-08-17 13:31:43 -07002411#define RAMCLK_GATE_D 0x6210 /* CRL only */
2412#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002413
Ville Syrjäläd88b2272013-01-24 15:29:48 +02002414#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07002415#define FW_CSPWRDWNEN (1<<15)
2416
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03002417#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2418
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002419#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2420#define CDCLK_FREQ_SHIFT 4
2421#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2422#define CZCLK_FREQ_MASK 0xf
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02002423
2424#define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)
2425#define PFI_CREDIT_63 (9 << 28) /* chv only */
2426#define PFI_CREDIT_31 (8 << 28) /* chv only */
2427#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2428#define PFI_CREDIT_RESEND (1 << 27)
2429#define VGA_FAST_MODE_DISABLE (1 << 14)
2430
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002431#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2432
Jesse Barnes585fb112008-07-29 11:54:06 -07002433/*
2434 * Palette regs
2435 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002436#define PALETTE_A_OFFSET 0xa000
2437#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002438#define CHV_PALETTE_C_OFFSET 0xc000
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002439#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2440 dev_priv->info.display_mmio_offset)
Jesse Barnes585fb112008-07-29 11:54:06 -07002441
Eric Anholt673a3942008-07-30 12:06:12 -07002442/* MCH MMIO space */
2443
2444/*
2445 * MCHBAR mirror.
2446 *
2447 * This mirrors the MCHBAR MMIO space whose location is determined by
2448 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2449 * every way. It is not accessible from the CP register read instructions.
2450 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03002451 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2452 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07002453 */
2454#define MCHBAR_MIRROR_BASE 0x10000
2455
Yuanhan Liu13982612010-12-15 15:42:31 +08002456#define MCHBAR_MIRROR_BASE_SNB 0x140000
2457
Chris Wilson3ebecd02013-04-12 19:10:13 +01002458/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ben Widawsky153b4b952013-10-22 22:05:09 -07002459#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01002460
Ville Syrjälä646b4262014-04-25 20:14:30 +03002461/* 915-945 and GM965 MCH register controlling DRAM channel access */
Eric Anholt673a3942008-07-30 12:06:12 -07002462#define DCC 0x10200
2463#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2464#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2465#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2466#define DCC_ADDRESSING_MODE_MASK (3 << 0)
2467#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08002468#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Daniel Vetter656bfa32014-11-20 09:26:30 +01002469#define DCC2 0x10204
2470#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
Eric Anholt673a3942008-07-30 12:06:12 -07002471
Ville Syrjälä646b4262014-04-25 20:14:30 +03002472/* Pineview MCH register contains DDR3 setting */
Li Peng95534262010-05-18 18:58:44 +08002473#define CSHRDDR3CTL 0x101a8
2474#define CSHRDDR3CTL_DDR3 (1 << 2)
2475
Ville Syrjälä646b4262014-04-25 20:14:30 +03002476/* 965 MCH register controlling DRAM channel configuration */
Eric Anholt673a3942008-07-30 12:06:12 -07002477#define C0DRB3 0x10206
2478#define C1DRB3 0x10606
2479
Ville Syrjälä646b4262014-04-25 20:14:30 +03002480/* snb MCH registers for reading the DRAM channel configuration */
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002481#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2482#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2483#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2484#define MAD_DIMM_ECC_MASK (0x3 << 24)
2485#define MAD_DIMM_ECC_OFF (0x0 << 24)
2486#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2487#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2488#define MAD_DIMM_ECC_ON (0x3 << 24)
2489#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2490#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2491#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2492#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2493#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2494#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2495#define MAD_DIMM_A_SELECT (0x1 << 16)
2496/* DIMM sizes are in multiples of 256mb. */
2497#define MAD_DIMM_B_SIZE_SHIFT 8
2498#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2499#define MAD_DIMM_A_SIZE_SHIFT 0
2500#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2501
Ville Syrjälä646b4262014-04-25 20:14:30 +03002502/* snb MCH registers for priority tuning */
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01002503#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2504#define MCH_SSKPD_WM0_MASK 0x3f
2505#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002506
Jesse Barnesec013e72013-08-20 10:29:23 +01002507#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2508
Keith Packardb11248d2009-06-11 22:28:56 -07002509/* Clocking configuration register */
2510#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08002511#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07002512#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2513#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2514#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2515#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2516#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002517/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07002518#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002519#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07002520#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002521#define CLKCFG_MEM_533 (1 << 4)
2522#define CLKCFG_MEM_667 (2 << 4)
2523#define CLKCFG_MEM_800 (3 << 4)
2524#define CLKCFG_MEM_MASK (7 << 4)
2525
Ville Syrjälä34edce22015-05-22 11:22:33 +03002526#define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38)
2527#define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f)
2528
Jesse Barnesea056c12010-09-10 10:02:13 -07002529#define TSC1 0x11001
2530#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002531#define TR1 0x11006
2532#define TSFS 0x11020
2533#define TSFS_SLOPE_MASK 0x0000ff00
2534#define TSFS_SLOPE_SHIFT 8
2535#define TSFS_INTR_MASK 0x000000ff
2536
Jesse Barnesf97108d2010-01-29 11:27:07 -08002537#define CRSTANDVID 0x11100
2538#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2539#define PXVFREQ_PX_MASK 0x7f000000
2540#define PXVFREQ_PX_SHIFT 24
2541#define VIDFREQ_BASE 0x11110
2542#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2543#define VIDFREQ2 0x11114
2544#define VIDFREQ3 0x11118
2545#define VIDFREQ4 0x1111c
2546#define VIDFREQ_P0_MASK 0x1f000000
2547#define VIDFREQ_P0_SHIFT 24
2548#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2549#define VIDFREQ_P0_CSCLK_SHIFT 20
2550#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2551#define VIDFREQ_P0_CRCLK_SHIFT 16
2552#define VIDFREQ_P1_MASK 0x00001f00
2553#define VIDFREQ_P1_SHIFT 8
2554#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2555#define VIDFREQ_P1_CSCLK_SHIFT 4
2556#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2557#define INTTOEXT_BASE_ILK 0x11300
2558#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2559#define INTTOEXT_MAP3_SHIFT 24
2560#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2561#define INTTOEXT_MAP2_SHIFT 16
2562#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2563#define INTTOEXT_MAP1_SHIFT 8
2564#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2565#define INTTOEXT_MAP0_SHIFT 0
2566#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2567#define MEMSWCTL 0x11170 /* Ironlake only */
2568#define MEMCTL_CMD_MASK 0xe000
2569#define MEMCTL_CMD_SHIFT 13
2570#define MEMCTL_CMD_RCLK_OFF 0
2571#define MEMCTL_CMD_RCLK_ON 1
2572#define MEMCTL_CMD_CHFREQ 2
2573#define MEMCTL_CMD_CHVID 3
2574#define MEMCTL_CMD_VMMOFF 4
2575#define MEMCTL_CMD_VMMON 5
2576#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2577 when command complete */
2578#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2579#define MEMCTL_FREQ_SHIFT 8
2580#define MEMCTL_SFCAVM (1<<7)
2581#define MEMCTL_TGT_VID_MASK 0x007f
2582#define MEMIHYST 0x1117c
2583#define MEMINTREN 0x11180 /* 16 bits */
2584#define MEMINT_RSEXIT_EN (1<<8)
2585#define MEMINT_CX_SUPR_EN (1<<7)
2586#define MEMINT_CONT_BUSY_EN (1<<6)
2587#define MEMINT_AVG_BUSY_EN (1<<5)
2588#define MEMINT_EVAL_CHG_EN (1<<4)
2589#define MEMINT_MON_IDLE_EN (1<<3)
2590#define MEMINT_UP_EVAL_EN (1<<2)
2591#define MEMINT_DOWN_EVAL_EN (1<<1)
2592#define MEMINT_SW_CMD_EN (1<<0)
2593#define MEMINTRSTR 0x11182 /* 16 bits */
2594#define MEM_RSEXIT_MASK 0xc000
2595#define MEM_RSEXIT_SHIFT 14
2596#define MEM_CONT_BUSY_MASK 0x3000
2597#define MEM_CONT_BUSY_SHIFT 12
2598#define MEM_AVG_BUSY_MASK 0x0c00
2599#define MEM_AVG_BUSY_SHIFT 10
2600#define MEM_EVAL_CHG_MASK 0x0300
2601#define MEM_EVAL_BUSY_SHIFT 8
2602#define MEM_MON_IDLE_MASK 0x00c0
2603#define MEM_MON_IDLE_SHIFT 6
2604#define MEM_UP_EVAL_MASK 0x0030
2605#define MEM_UP_EVAL_SHIFT 4
2606#define MEM_DOWN_EVAL_MASK 0x000c
2607#define MEM_DOWN_EVAL_SHIFT 2
2608#define MEM_SW_CMD_MASK 0x0003
2609#define MEM_INT_STEER_GFX 0
2610#define MEM_INT_STEER_CMR 1
2611#define MEM_INT_STEER_SMI 2
2612#define MEM_INT_STEER_SCI 3
2613#define MEMINTRSTS 0x11184
2614#define MEMINT_RSEXIT (1<<7)
2615#define MEMINT_CONT_BUSY (1<<6)
2616#define MEMINT_AVG_BUSY (1<<5)
2617#define MEMINT_EVAL_CHG (1<<4)
2618#define MEMINT_MON_IDLE (1<<3)
2619#define MEMINT_UP_EVAL (1<<2)
2620#define MEMINT_DOWN_EVAL (1<<1)
2621#define MEMINT_SW_CMD (1<<0)
2622#define MEMMODECTL 0x11190
2623#define MEMMODE_BOOST_EN (1<<31)
2624#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2625#define MEMMODE_BOOST_FREQ_SHIFT 24
2626#define MEMMODE_IDLE_MODE_MASK 0x00030000
2627#define MEMMODE_IDLE_MODE_SHIFT 16
2628#define MEMMODE_IDLE_MODE_EVAL 0
2629#define MEMMODE_IDLE_MODE_CONT 1
2630#define MEMMODE_HWIDLE_EN (1<<15)
2631#define MEMMODE_SWMODE_EN (1<<14)
2632#define MEMMODE_RCLK_GATE (1<<13)
2633#define MEMMODE_HW_UPDATE (1<<12)
2634#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2635#define MEMMODE_FSTART_SHIFT 8
2636#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2637#define MEMMODE_FMAX_SHIFT 4
2638#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2639#define RCBMAXAVG 0x1119c
2640#define MEMSWCTL2 0x1119e /* Cantiga only */
2641#define SWMEMCMD_RENDER_OFF (0 << 13)
2642#define SWMEMCMD_RENDER_ON (1 << 13)
2643#define SWMEMCMD_SWFREQ (2 << 13)
2644#define SWMEMCMD_TARVID (3 << 13)
2645#define SWMEMCMD_VRM_OFF (4 << 13)
2646#define SWMEMCMD_VRM_ON (5 << 13)
2647#define CMDSTS (1<<12)
2648#define SFCAVM (1<<11)
2649#define SWFREQ_MASK 0x0380 /* P0-7 */
2650#define SWFREQ_SHIFT 7
2651#define TARVID_MASK 0x001f
2652#define MEMSTAT_CTG 0x111a0
2653#define RCBMINAVG 0x111a0
2654#define RCUPEI 0x111b0
2655#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08002656#define RSTDBYCTL 0x111b8
2657#define RS1EN (1<<31)
2658#define RS2EN (1<<30)
2659#define RS3EN (1<<29)
2660#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2661#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2662#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2663#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2664#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2665#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2666#define RSX_STATUS_MASK (7<<20)
2667#define RSX_STATUS_ON (0<<20)
2668#define RSX_STATUS_RC1 (1<<20)
2669#define RSX_STATUS_RC1E (2<<20)
2670#define RSX_STATUS_RS1 (3<<20)
2671#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2672#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2673#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2674#define RSX_STATUS_RSVD2 (7<<20)
2675#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2676#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2677#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2678#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2679#define RS1CONTSAV_MASK (3<<14)
2680#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2681#define RS1CONTSAV_RSVD (1<<14)
2682#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2683#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2684#define NORMSLEXLAT_MASK (3<<12)
2685#define SLOW_RS123 (0<<12)
2686#define SLOW_RS23 (1<<12)
2687#define SLOW_RS3 (2<<12)
2688#define NORMAL_RS123 (3<<12)
2689#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2690#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2691#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2692#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2693#define RS_CSTATE_MASK (3<<4)
2694#define RS_CSTATE_C367_RS1 (0<<4)
2695#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2696#define RS_CSTATE_RSVD (2<<4)
2697#define RS_CSTATE_C367_RS2 (3<<4)
2698#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2699#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002700#define VIDCTL 0x111c0
2701#define VIDSTS 0x111c8
2702#define VIDSTART 0x111cc /* 8 bits */
2703#define MEMSTAT_ILK 0x111f8
2704#define MEMSTAT_VID_MASK 0x7f00
2705#define MEMSTAT_VID_SHIFT 8
2706#define MEMSTAT_PSTATE_MASK 0x00f8
2707#define MEMSTAT_PSTATE_SHIFT 3
2708#define MEMSTAT_MON_ACTV (1<<2)
2709#define MEMSTAT_SRC_CTL_MASK 0x0003
2710#define MEMSTAT_SRC_CTL_CORE 0
2711#define MEMSTAT_SRC_CTL_TRB 1
2712#define MEMSTAT_SRC_CTL_THM 2
2713#define MEMSTAT_SRC_CTL_STDBY 3
2714#define RCPREVBSYTUPAVG 0x113b8
2715#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07002716#define PMMISC 0x11214
2717#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07002718#define SDEW 0x1124c
2719#define CSIEW0 0x11250
2720#define CSIEW1 0x11254
2721#define CSIEW2 0x11258
2722#define PEW 0x1125c
2723#define DEW 0x11270
2724#define MCHAFE 0x112c0
2725#define CSIEC 0x112e0
2726#define DMIEC 0x112e4
2727#define DDREC 0x112e8
2728#define PEG0EC 0x112ec
2729#define PEG1EC 0x112f0
2730#define GFXEC 0x112f4
2731#define RPPREVBSYTUPAVG 0x113b8
2732#define RPPREVBSYTDNAVG 0x113bc
2733#define ECR 0x11600
2734#define ECR_GPFE (1<<31)
2735#define ECR_IMONE (1<<30)
2736#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2737#define OGW0 0x11608
2738#define OGW1 0x1160c
2739#define EG0 0x11610
2740#define EG1 0x11614
2741#define EG2 0x11618
2742#define EG3 0x1161c
2743#define EG4 0x11620
2744#define EG5 0x11624
2745#define EG6 0x11628
2746#define EG7 0x1162c
2747#define PXW 0x11664
2748#define PXWL 0x11680
2749#define LCFUSE02 0x116c0
2750#define LCFUSE_HIV_MASK 0x000000ff
2751#define CSIPLL0 0x12c10
2752#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08002753#define PEG_BAND_GAP_DATA 0x14d68
2754
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002755#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2756#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002757
Ben Widawsky153b4b952013-10-22 22:05:09 -07002758#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
Bob Paauwe35040562015-06-25 14:54:07 -07002759#define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070)
Ben Widawsky153b4b952013-10-22 22:05:09 -07002760#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2761#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
Bob Paauwe35040562015-06-25 14:54:07 -07002762#define BXT_RP_STATE_CAP 0x138170
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002763
Akash Goelde43ae92015-03-06 11:07:14 +05302764#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
2765#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2766#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2767 INTERVAL_1_33_US(us) : \
2768 INTERVAL_1_28_US(us))
2769
Jesse Barnes585fb112008-07-29 11:54:06 -07002770/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002771 * Logical Context regs
2772 */
2773#define CCID 0x2180
2774#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002775/*
2776 * Notes on SNB/IVB/VLV context size:
2777 * - Power context is saved elsewhere (LLC or stolen)
2778 * - Ring/execlist context is saved on SNB, not on IVB
2779 * - Extended context size already includes render context size
2780 * - We always need to follow the extended context size.
2781 * SNB BSpec has comments indicating that we should use the
2782 * render context size instead if execlists are disabled, but
2783 * based on empirical testing that's just nonsense.
2784 * - Pipelined/VF state is saved on SNB/IVB respectively
2785 * - GT1 size just indicates how much of render context
2786 * doesn't need saving on GT1
2787 */
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002788#define CXT_SIZE 0x21a0
2789#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2790#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2791#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2792#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2793#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002794#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002795 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2796 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002797#define GEN7_CXT_SIZE 0x21a8
Ben Widawsky6a4ea1242012-07-18 10:10:10 -07002798#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2799#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002800#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2801#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2802#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2803#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002804#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002805 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07002806/* Haswell does have the CXT_SIZE register however it does not appear to be
2807 * valid. Now, docs explain in dwords what is in the context object. The full
2808 * size is 70720 bytes, however, the power context and execlist context will
2809 * never be saved (power context is stored elsewhere, and execlists don't work
Abdiel Janulgue4c436d552015-06-16 13:39:41 +03002810 * on HSW) - so the final size, including the extra state required for the
2811 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
Ben Widawskya0de80a2013-06-25 21:53:40 -07002812 */
2813#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawsky88976442013-11-02 21:07:05 -07002814/* Same as Haswell, but 72064 bytes now. */
2815#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2816
Mika Kuoppala542a6b22014-07-09 14:55:56 +03002817#define CHV_CLK_CTL1 0x101100
Jesse Barnese454a052013-09-26 17:55:58 -07002818#define VLV_CLK_CTL2 0x101104
2819#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2820
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002821/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002822 * Overlay regs
2823 */
2824
2825#define OVADD 0x30000
2826#define DOVSTA 0x30008
2827#define OC_BUF (0x3<<20)
2828#define OGAMC5 0x30010
2829#define OGAMC4 0x30014
2830#define OGAMC3 0x30018
2831#define OGAMC2 0x3001c
2832#define OGAMC1 0x30020
2833#define OGAMC0 0x30024
2834
2835/*
2836 * Display engine regs
2837 */
2838
Shuang He8bf1e9f2013-10-15 18:55:27 +01002839/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002840#define _PIPE_CRC_CTL_A 0x60050
Shuang He8bf1e9f2013-10-15 18:55:27 +01002841#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002842/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01002843#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2844#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2845#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002846/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002847#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2848#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2849#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2850/* embedded DP port on the north display block, reserved on ivb */
2851#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2852#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02002853/* vlv source selection */
2854#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2855#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2856#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2857/* with DP port the pipe source is invalid */
2858#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2859#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2860#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2861/* gen3+ source selection */
2862#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2863#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2864#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2865/* with DP/TV port the pipe source is invalid */
2866#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2867#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2868#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2869#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2870#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2871/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02002872#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002873
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002874#define _PIPE_CRC_RES_1_A_IVB 0x60064
2875#define _PIPE_CRC_RES_2_A_IVB 0x60068
2876#define _PIPE_CRC_RES_3_A_IVB 0x6006c
2877#define _PIPE_CRC_RES_4_A_IVB 0x60070
2878#define _PIPE_CRC_RES_5_A_IVB 0x60074
2879
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002880#define _PIPE_CRC_RES_RED_A 0x60060
2881#define _PIPE_CRC_RES_GREEN_A 0x60064
2882#define _PIPE_CRC_RES_BLUE_A 0x60068
2883#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2884#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01002885
2886/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002887#define _PIPE_CRC_RES_1_B_IVB 0x61064
2888#define _PIPE_CRC_RES_2_B_IVB 0x61068
2889#define _PIPE_CRC_RES_3_B_IVB 0x6106c
2890#define _PIPE_CRC_RES_4_B_IVB 0x61070
2891#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01002892
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002893#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002894#define PIPE_CRC_RES_1_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002895 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002896#define PIPE_CRC_RES_2_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002897 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002898#define PIPE_CRC_RES_3_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002899 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002900#define PIPE_CRC_RES_4_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002901 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002902#define PIPE_CRC_RES_5_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002903 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002904
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002905#define PIPE_CRC_RES_RED(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002906 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002907#define PIPE_CRC_RES_GREEN(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002908 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002909#define PIPE_CRC_RES_BLUE(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002910 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002911#define PIPE_CRC_RES_RES1_I915(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002912 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002913#define PIPE_CRC_RES_RES2_G4X(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002914 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002915
Jesse Barnes585fb112008-07-29 11:54:06 -07002916/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002917#define _HTOTAL_A 0x60000
2918#define _HBLANK_A 0x60004
2919#define _HSYNC_A 0x60008
2920#define _VTOTAL_A 0x6000c
2921#define _VBLANK_A 0x60010
2922#define _VSYNC_A 0x60014
2923#define _PIPEASRC 0x6001c
2924#define _BCLRPAT_A 0x60020
2925#define _VSYNCSHIFT_A 0x60028
Clint Taylorebb69c92014-09-30 10:30:22 -07002926#define _PIPE_MULT_A 0x6002c
Jesse Barnes585fb112008-07-29 11:54:06 -07002927
2928/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002929#define _HTOTAL_B 0x61000
2930#define _HBLANK_B 0x61004
2931#define _HSYNC_B 0x61008
2932#define _VTOTAL_B 0x6100c
2933#define _VBLANK_B 0x61010
2934#define _VSYNC_B 0x61014
2935#define _PIPEBSRC 0x6101c
2936#define _BCLRPAT_B 0x61020
2937#define _VSYNCSHIFT_B 0x61028
Clint Taylorebb69c92014-09-30 10:30:22 -07002938#define _PIPE_MULT_B 0x6102c
Daniel Vetter0529a0d2012-01-28 14:49:24 +01002939
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002940#define TRANSCODER_A_OFFSET 0x60000
2941#define TRANSCODER_B_OFFSET 0x61000
2942#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002943#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002944#define TRANSCODER_EDP_OFFSET 0x6f000
2945
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002946#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2947 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2948 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002949
2950#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2951#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2952#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2953#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2954#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2955#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2956#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2957#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2958#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
Clint Taylorebb69c92014-09-30 10:30:22 -07002959#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
Chris Wilson5eddb702010-09-11 13:48:45 +01002960
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08002961/* VLV eDP PSR registers */
2962#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
2963#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
2964#define VLV_EDP_PSR_ENABLE (1<<0)
2965#define VLV_EDP_PSR_RESET (1<<1)
2966#define VLV_EDP_PSR_MODE_MASK (7<<2)
2967#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
2968#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
2969#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
2970#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
2971#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
2972#define VLV_EDP_PSR_DBL_FRAME (1<<10)
2973#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
2974#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
2975#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
2976
2977#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
2978#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
2979#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
2980#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
2981#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
2982#define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)
2983
2984#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
2985#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
2986#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
2987#define VLV_EDP_PSR_CURR_STATE_MASK 7
2988#define VLV_EDP_PSR_DISABLED (0<<0)
2989#define VLV_EDP_PSR_INACTIVE (1<<0)
2990#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
2991#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
2992#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
2993#define VLV_EDP_PSR_EXIT (5<<0)
2994#define VLV_EDP_PSR_IN_TRANS (1<<7)
2995#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
2996
Ben Widawskyed8546a2013-11-04 22:45:05 -08002997/* HSW+ eDP PSR registers */
2998#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
Ben Widawsky18b59922013-09-20 09:35:30 -07002999#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003000#define EDP_PSR_ENABLE (1<<31)
Rodrigo Vivi82c56252014-06-12 10:16:42 -07003001#define BDW_PSR_SINGLE_FRAME (1<<30)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003002#define EDP_PSR_LINK_STANDBY (1<<27)
3003#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3004#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3005#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3006#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3007#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3008#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3009#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3010#define EDP_PSR_TP1_TP2_SEL (0<<11)
3011#define EDP_PSR_TP1_TP3_SEL (1<<11)
3012#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3013#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3014#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3015#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3016#define EDP_PSR_TP1_TIME_500us (0<<4)
3017#define EDP_PSR_TP1_TIME_100us (1<<4)
3018#define EDP_PSR_TP1_TIME_2500us (2<<4)
3019#define EDP_PSR_TP1_TIME_0us (3<<4)
3020#define EDP_PSR_IDLE_FRAME_SHIFT 0
3021
Ben Widawsky18b59922013-09-20 09:35:30 -07003022#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
3023#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
Ben Widawsky18b59922013-09-20 09:35:30 -07003024#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
Ben Widawsky18b59922013-09-20 09:35:30 -07003025#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
3026#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
3027#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003028
Ben Widawsky18b59922013-09-20 09:35:30 -07003029#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003030#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03003031#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3032#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3033#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3034#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3035#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3036#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3037#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3038#define EDP_PSR_STATUS_LINK_MASK (3<<26)
3039#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3040#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3041#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3042#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3043#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3044#define EDP_PSR_STATUS_COUNT_SHIFT 16
3045#define EDP_PSR_STATUS_COUNT_MASK 0xf
3046#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3047#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3048#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3049#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3050#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3051#define EDP_PSR_STATUS_IDLE_MASK 0xf
3052
Ben Widawsky18b59922013-09-20 09:35:30 -07003053#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03003054#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003055
Ben Widawsky18b59922013-09-20 09:35:30 -07003056#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003057#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3058#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3059#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3060
Sonika Jindal474d1ec2015-04-02 11:02:44 +05303061#define EDP_PSR2_CTL 0x6f900
3062#define EDP_PSR2_ENABLE (1<<31)
3063#define EDP_SU_TRACK_ENABLE (1<<30)
3064#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3065#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3066#define EDP_PSR2_TP2_TIME_500 (0<<8)
3067#define EDP_PSR2_TP2_TIME_100 (1<<8)
3068#define EDP_PSR2_TP2_TIME_2500 (2<<8)
3069#define EDP_PSR2_TP2_TIME_50 (3<<8)
3070#define EDP_PSR2_TP2_TIME_MASK (3<<8)
3071#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3072#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3073#define EDP_PSR2_IDLE_MASK 0xf
3074
Jesse Barnes585fb112008-07-29 11:54:06 -07003075/* VGA port control */
3076#define ADPA 0x61100
Daniel Vetterebc0fd82012-07-11 16:27:56 +02003077#define PCH_ADPA 0xe1100
Daniel Vetter540a8952012-07-11 16:27:57 +02003078#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02003079
Jesse Barnes585fb112008-07-29 11:54:06 -07003080#define ADPA_DAC_ENABLE (1<<31)
3081#define ADPA_DAC_DISABLE 0
3082#define ADPA_PIPE_SELECT_MASK (1<<30)
3083#define ADPA_PIPE_A_SELECT 0
3084#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07003085#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02003086/* CPT uses bits 29:30 for pch transcoder select */
3087#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3088#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3089#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3090#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3091#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3092#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3093#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3094#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3095#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3096#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3097#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3098#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3099#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3100#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3101#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3102#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3103#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3104#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3105#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003106#define ADPA_USE_VGA_HVPOLARITY (1<<15)
3107#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01003108#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003109#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01003110#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07003111#define ADPA_HSYNC_CNTL_ENABLE 0
3112#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3113#define ADPA_VSYNC_ACTIVE_LOW 0
3114#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3115#define ADPA_HSYNC_ACTIVE_LOW 0
3116#define ADPA_DPMS_MASK (~(3<<10))
3117#define ADPA_DPMS_ON (0<<10)
3118#define ADPA_DPMS_SUSPEND (1<<10)
3119#define ADPA_DPMS_STANDBY (2<<10)
3120#define ADPA_DPMS_OFF (3<<10)
3121
Chris Wilson939fe4d2010-10-09 10:33:26 +01003122
Jesse Barnes585fb112008-07-29 11:54:06 -07003123/* Hotplug control (945+ only) */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003124#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01003125#define PORTB_HOTPLUG_INT_EN (1 << 29)
3126#define PORTC_HOTPLUG_INT_EN (1 << 28)
3127#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003128#define SDVOB_HOTPLUG_INT_EN (1 << 26)
3129#define SDVOC_HOTPLUG_INT_EN (1 << 25)
3130#define TV_HOTPLUG_INT_EN (1 << 18)
3131#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05003132#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3133 PORTC_HOTPLUG_INT_EN | \
3134 PORTD_HOTPLUG_INT_EN | \
3135 SDVOC_HOTPLUG_INT_EN | \
3136 SDVOB_HOTPLUG_INT_EN | \
3137 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07003138#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08003139#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3140/* must use period 64 on GM45 according to docs */
3141#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3142#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3143#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3144#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3145#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3146#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3147#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3148#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3149#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3150#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3151#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3152#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003153
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003154#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02003155/*
3156 * HDMI/DP bits are gen4+
3157 *
3158 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3159 * Please check the detailed lore in the commit message for for experimental
3160 * evidence.
3161 */
Todd Previte232a6ee2014-01-23 00:13:41 -07003162#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
3163#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
3164#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
3165/* VLV DP/HDMI bits again match Bspec */
3166#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
3167#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
3168#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01003169#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02003170#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3171#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01003172#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02003173#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3174#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01003175#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02003176#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3177#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01003178/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07003179#define CRT_HOTPLUG_INT_STATUS (1 << 11)
3180#define TV_HOTPLUG_INT_STATUS (1 << 10)
3181#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3182#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3183#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3184#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01003185#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3186#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3187#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02003188#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3189
Chris Wilson084b6122012-05-11 18:01:33 +01003190/* SDVO is different across gen3/4 */
3191#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3192#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02003193/*
3194 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3195 * since reality corrobates that they're the same as on gen3. But keep these
3196 * bits here (and the comment!) to help any other lost wanderers back onto the
3197 * right tracks.
3198 */
Chris Wilson084b6122012-05-11 18:01:33 +01003199#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3200#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3201#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3202#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05003203#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3204 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3205 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3206 PORTB_HOTPLUG_INT_STATUS | \
3207 PORTC_HOTPLUG_INT_STATUS | \
3208 PORTD_HOTPLUG_INT_STATUS)
3209
Egbert Eiche5868a32013-02-28 04:17:12 -05003210#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3211 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3212 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3213 PORTB_HOTPLUG_INT_STATUS | \
3214 PORTC_HOTPLUG_INT_STATUS | \
3215 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07003216
Paulo Zanonic20cd312013-02-19 16:21:45 -03003217/* SDVO and HDMI port control.
3218 * The same register may be used for SDVO or HDMI */
3219#define GEN3_SDVOB 0x61140
3220#define GEN3_SDVOC 0x61160
3221#define GEN4_HDMIB GEN3_SDVOB
3222#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjälä9418c1f2014-04-09 13:28:56 +03003223#define CHV_HDMID 0x6116C
Paulo Zanonic20cd312013-02-19 16:21:45 -03003224#define PCH_SDVOB 0xe1140
3225#define PCH_HDMIB PCH_SDVOB
3226#define PCH_HDMIC 0xe1150
3227#define PCH_HDMID 0xe1160
3228
Daniel Vetter84093602013-11-01 10:50:21 +01003229#define PORT_DFT_I9XX 0x61150
3230#define DC_BALANCE_RESET (1 << 25)
Rodrigo Vivia8aab8b2014-06-05 14:28:17 -07003231#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01003232#define DC_BALANCE_RESET_VLV (1 << 31)
Ville Syrjäläeb736672014-12-09 21:28:28 +02003233#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3234#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
Daniel Vetter84093602013-11-01 10:50:21 +01003235#define PIPE_B_SCRAMBLE_RESET (1 << 1)
3236#define PIPE_A_SCRAMBLE_RESET (1 << 0)
3237
Paulo Zanonic20cd312013-02-19 16:21:45 -03003238/* Gen 3 SDVO bits: */
3239#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003240#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3241#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003242#define SDVO_PIPE_B_SELECT (1 << 30)
3243#define SDVO_STALL_SELECT (1 << 29)
3244#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003245/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003246 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07003247 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07003248 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3249 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003250#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07003251#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03003252#define SDVO_PHASE_SELECT_MASK (15 << 19)
3253#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3254#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3255#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3256#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3257#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3258#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003259/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003260#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3261 SDVO_INTERRUPT_ENABLE)
3262#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3263
3264/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003265#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03003266#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003267#define SDVO_ENCODING_SDVO (0 << 10)
3268#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003269#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3270#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003271#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003272#define SDVO_AUDIO_ENABLE (1 << 6)
3273/* VSYNC/HSYNC bits new with 965, default is to be set */
3274#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3275#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3276
3277/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03003278#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03003279#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3280
3281/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03003282#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3283#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03003284
Chon Ming Lee44f37d12014-04-09 13:28:21 +03003285/* CHV SDVO/HDMI bits: */
3286#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3287#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3288
Jesse Barnes585fb112008-07-29 11:54:06 -07003289
3290/* DVO port control */
3291#define DVOA 0x61120
3292#define DVOB 0x61140
3293#define DVOC 0x61160
3294#define DVO_ENABLE (1 << 31)
3295#define DVO_PIPE_B_SELECT (1 << 30)
3296#define DVO_PIPE_STALL_UNUSED (0 << 28)
3297#define DVO_PIPE_STALL (1 << 28)
3298#define DVO_PIPE_STALL_TV (2 << 28)
3299#define DVO_PIPE_STALL_MASK (3 << 28)
3300#define DVO_USE_VGA_SYNC (1 << 15)
3301#define DVO_DATA_ORDER_I740 (0 << 14)
3302#define DVO_DATA_ORDER_FP (1 << 14)
3303#define DVO_VSYNC_DISABLE (1 << 11)
3304#define DVO_HSYNC_DISABLE (1 << 10)
3305#define DVO_VSYNC_TRISTATE (1 << 9)
3306#define DVO_HSYNC_TRISTATE (1 << 8)
3307#define DVO_BORDER_ENABLE (1 << 7)
3308#define DVO_DATA_ORDER_GBRG (1 << 6)
3309#define DVO_DATA_ORDER_RGGB (0 << 6)
3310#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3311#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3312#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3313#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3314#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3315#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3316#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3317#define DVO_PRESERVE_MASK (0x7<<24)
3318#define DVOA_SRCDIM 0x61124
3319#define DVOB_SRCDIM 0x61144
3320#define DVOC_SRCDIM 0x61164
3321#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3322#define DVO_SRCDIM_VERTICAL_SHIFT 0
3323
3324/* LVDS port control */
3325#define LVDS 0x61180
3326/*
3327 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3328 * the DPLL semantics change when the LVDS is assigned to that pipe.
3329 */
3330#define LVDS_PORT_EN (1 << 31)
3331/* Selects pipe B for LVDS data. Must be set on pre-965. */
3332#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003333#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07003334#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08003335/* LVDS dithering flag on 965/g4x platform */
3336#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08003337/* LVDS sync polarity flags. Set to invert (i.e. negative) */
3338#define LVDS_VSYNC_POLARITY (1 << 21)
3339#define LVDS_HSYNC_POLARITY (1 << 20)
3340
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08003341/* Enable border for unscaled (or aspect-scaled) display */
3342#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07003343/*
3344 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3345 * pixel.
3346 */
3347#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3348#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3349#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3350/*
3351 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3352 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3353 * on.
3354 */
3355#define LVDS_A3_POWER_MASK (3 << 6)
3356#define LVDS_A3_POWER_DOWN (0 << 6)
3357#define LVDS_A3_POWER_UP (3 << 6)
3358/*
3359 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3360 * is set.
3361 */
3362#define LVDS_CLKB_POWER_MASK (3 << 4)
3363#define LVDS_CLKB_POWER_DOWN (0 << 4)
3364#define LVDS_CLKB_POWER_UP (3 << 4)
3365/*
3366 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3367 * setting for whether we are in dual-channel mode. The B3 pair will
3368 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3369 */
3370#define LVDS_B0B3_POWER_MASK (3 << 2)
3371#define LVDS_B0B3_POWER_DOWN (0 << 2)
3372#define LVDS_B0B3_POWER_UP (3 << 2)
3373
David Härdeman3c17fe42010-09-24 21:44:32 +02003374/* Video Data Island Packet control */
3375#define VIDEO_DIP_DATA 0x61178
Yannick Guerrinifd0753c2015-02-28 17:20:41 +01003376/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
Paulo Zanoniadf00b22012-09-25 13:23:34 -03003377 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3378 * of the infoframe structure specified by CEA-861. */
3379#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003380#define VIDEO_DIP_VSC_DATA_SIZE 36
David Härdeman3c17fe42010-09-24 21:44:32 +02003381#define VIDEO_DIP_CTL 0x61170
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003382/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02003383#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02003384#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03003385#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003386#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02003387#define VIDEO_DIP_ENABLE_AVI (1 << 21)
3388#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003389#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02003390#define VIDEO_DIP_ENABLE_SPD (8 << 21)
3391#define VIDEO_DIP_SELECT_AVI (0 << 19)
3392#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3393#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07003394#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02003395#define VIDEO_DIP_FREQ_ONCE (0 << 16)
3396#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3397#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03003398#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003399/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003400#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3401#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003402#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003403#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3404#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003405#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02003406
Jesse Barnes585fb112008-07-29 11:54:06 -07003407/* Panel power sequencing */
3408#define PP_STATUS 0x61200
3409#define PP_ON (1 << 31)
3410/*
3411 * Indicates that all dependencies of the panel are on:
3412 *
3413 * - PLL enabled
3414 * - pipe enabled
3415 * - LVDS/DVOB/DVOC on
3416 */
3417#define PP_READY (1 << 30)
3418#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07003419#define PP_SEQUENCE_POWER_UP (1 << 28)
3420#define PP_SEQUENCE_POWER_DOWN (2 << 28)
3421#define PP_SEQUENCE_MASK (3 << 28)
3422#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003423#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003424#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07003425#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3426#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3427#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3428#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3429#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3430#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3431#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3432#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3433#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003434#define PP_CONTROL 0x61204
3435#define POWER_TARGET_ON (1 << 0)
3436#define PP_ON_DELAYS 0x61208
3437#define PP_OFF_DELAYS 0x6120c
3438#define PP_DIVISOR 0x61210
3439
3440/* Panel fitting */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003441#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07003442#define PFIT_ENABLE (1 << 31)
3443#define PFIT_PIPE_MASK (3 << 29)
3444#define PFIT_PIPE_SHIFT 29
3445#define VERT_INTERP_DISABLE (0 << 10)
3446#define VERT_INTERP_BILINEAR (1 << 10)
3447#define VERT_INTERP_MASK (3 << 10)
3448#define VERT_AUTO_SCALE (1 << 9)
3449#define HORIZ_INTERP_DISABLE (0 << 6)
3450#define HORIZ_INTERP_BILINEAR (1 << 6)
3451#define HORIZ_INTERP_MASK (3 << 6)
3452#define HORIZ_AUTO_SCALE (1 << 5)
3453#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003454#define PFIT_FILTER_FUZZY (0 << 24)
3455#define PFIT_SCALING_AUTO (0 << 26)
3456#define PFIT_SCALING_PROGRAMMED (1 << 26)
3457#define PFIT_SCALING_PILLAR (2 << 26)
3458#define PFIT_SCALING_LETTER (3 << 26)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003459#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003460/* Pre-965 */
3461#define PFIT_VERT_SCALE_SHIFT 20
3462#define PFIT_VERT_SCALE_MASK 0xfff00000
3463#define PFIT_HORIZ_SCALE_SHIFT 4
3464#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3465/* 965+ */
3466#define PFIT_VERT_SCALE_SHIFT_965 16
3467#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3468#define PFIT_HORIZ_SCALE_SHIFT_965 0
3469#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3470
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003471#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07003472
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003473#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3474#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003475#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3476 _VLV_BLC_PWM_CTL2_B)
3477
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003478#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3479#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003480#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3481 _VLV_BLC_PWM_CTL_B)
3482
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003483#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3484#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003485#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3486 _VLV_BLC_HIST_CTL_B)
3487
Jesse Barnes585fb112008-07-29 11:54:06 -07003488/* Backlight control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003489#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003490#define BLM_PWM_ENABLE (1 << 31)
3491#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3492#define BLM_PIPE_SELECT (1 << 29)
3493#define BLM_PIPE_SELECT_IVB (3 << 29)
3494#define BLM_PIPE_A (0 << 29)
3495#define BLM_PIPE_B (1 << 29)
3496#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03003497#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3498#define BLM_TRANSCODER_B BLM_PIPE_B
3499#define BLM_TRANSCODER_C BLM_PIPE_C
3500#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003501#define BLM_PIPE(pipe) ((pipe) << 29)
3502#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3503#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3504#define BLM_PHASE_IN_ENABLE (1 << 25)
3505#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3506#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3507#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3508#define BLM_PHASE_IN_COUNT_SHIFT (8)
3509#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3510#define BLM_PHASE_IN_INCR_SHIFT (0)
3511#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003512#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01003513/*
3514 * This is the most significant 15 bits of the number of backlight cycles in a
3515 * complete cycle of the modulated backlight control.
3516 *
3517 * The actual value is this field multiplied by two.
3518 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003519#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3520#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3521#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003522/*
3523 * This is the number of cycles out of the backlight modulation cycle for which
3524 * the backlight is on.
3525 *
3526 * This field must be no greater than the number of cycles in the complete
3527 * backlight modulation cycle.
3528 */
3529#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3530#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02003531#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3532#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003533
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003534#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
Jani Nikula2059ac32015-06-26 14:18:56 +03003535#define BLM_HISTOGRAM_ENABLE (1 << 31)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07003536
Daniel Vetter7cf41602012-06-05 10:07:09 +02003537/* New registers for PCH-split platforms. Safe where new bits show up, the
3538 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3539#define BLC_PWM_CPU_CTL2 0x48250
3540#define BLC_PWM_CPU_CTL 0x48254
3541
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003542#define HSW_BLC_PWM2_CTL 0x48350
3543
Daniel Vetter7cf41602012-06-05 10:07:09 +02003544/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3545 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3546#define BLC_PWM_PCH_CTL1 0xc8250
Daniel Vetter4b4147c2012-07-11 00:31:06 +02003547#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003548#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3549#define BLM_PCH_POLARITY (1 << 29)
3550#define BLC_PWM_PCH_CTL2 0xc8254
3551
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003552#define UTIL_PIN_CTL 0x48400
3553#define UTIL_PIN_ENABLE (1 << 31)
3554
Vandana Kannan0fb890c2015-05-05 14:51:56 +05303555/* BXT backlight register definition. */
3556#define BXT_BLC_PWM_CTL1 0xC8250
3557#define BXT_BLC_PWM_ENABLE (1 << 31)
3558#define BXT_BLC_PWM_POLARITY (1 << 29)
3559#define BXT_BLC_PWM_FREQ1 0xC8254
3560#define BXT_BLC_PWM_DUTY1 0xC8258
3561
3562#define BXT_BLC_PWM_CTL2 0xC8350
3563#define BXT_BLC_PWM_FREQ2 0xC8354
3564#define BXT_BLC_PWM_DUTY2 0xC8358
3565
3566
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003567#define PCH_GTC_CTL 0xe7000
3568#define PCH_GTC_ENABLE (1 << 31)
3569
Jesse Barnes585fb112008-07-29 11:54:06 -07003570/* TV port control */
3571#define TV_CTL 0x68000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003572/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07003573# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003574/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003575# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003576/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003577# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003578/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003579# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003580/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003581# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003582/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003583# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3584# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003585/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003586# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003587/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003588# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003589/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07003590# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003591/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003592# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003593/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07003594# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003595/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07003596# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003597/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003598# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003599/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07003600# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003601/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003602# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003603/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003604 * Enables a fix for the 915GM only.
3605 *
3606 * Not sure what it does.
3607 */
3608# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003609/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08003610# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003611# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003612/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07003613# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003614/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003615# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003616/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003617# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003618/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07003619# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003620/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07003621# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003622/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003623# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003624/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003625# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003626/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07003627# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003628/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07003629# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003630/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003631 * This test mode forces the DACs to 50% of full output.
3632 *
3633 * This is used for load detection in combination with TVDAC_SENSE_MASK
3634 */
3635# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3636# define TV_TEST_MODE_MASK (7 << 0)
3637
3638#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01003639# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003640/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003641 * Reports that DAC state change logic has reported change (RO).
3642 *
3643 * This gets cleared when TV_DAC_STATE_EN is cleared
3644*/
3645# define TVDAC_STATE_CHG (1 << 31)
3646# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003647/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003648# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003649/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003650# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003651/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003652# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003653/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003654 * Enables DAC state detection logic, for load-based TV detection.
3655 *
3656 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3657 * to off, for load detection to work.
3658 */
3659# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003660/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003661# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003662/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003663# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003664/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003665# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003666/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07003667# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003668/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07003669# define ENC_TVDAC_SLEW_FAST (1 << 6)
3670# define DAC_A_1_3_V (0 << 4)
3671# define DAC_A_1_1_V (1 << 4)
3672# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08003673# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003674# define DAC_B_1_3_V (0 << 2)
3675# define DAC_B_1_1_V (1 << 2)
3676# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08003677# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003678# define DAC_C_1_3_V (0 << 0)
3679# define DAC_C_1_1_V (1 << 0)
3680# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08003681# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003682
Ville Syrjälä646b4262014-04-25 20:14:30 +03003683/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003684 * CSC coefficients are stored in a floating point format with 9 bits of
3685 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3686 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3687 * -1 (0x3) being the only legal negative value.
3688 */
3689#define TV_CSC_Y 0x68010
3690# define TV_RY_MASK 0x07ff0000
3691# define TV_RY_SHIFT 16
3692# define TV_GY_MASK 0x00000fff
3693# define TV_GY_SHIFT 0
3694
3695#define TV_CSC_Y2 0x68014
3696# define TV_BY_MASK 0x07ff0000
3697# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003698/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003699 * Y attenuation for component video.
3700 *
3701 * Stored in 1.9 fixed point.
3702 */
3703# define TV_AY_MASK 0x000003ff
3704# define TV_AY_SHIFT 0
3705
3706#define TV_CSC_U 0x68018
3707# define TV_RU_MASK 0x07ff0000
3708# define TV_RU_SHIFT 16
3709# define TV_GU_MASK 0x000007ff
3710# define TV_GU_SHIFT 0
3711
3712#define TV_CSC_U2 0x6801c
3713# define TV_BU_MASK 0x07ff0000
3714# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003715/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003716 * U attenuation for component video.
3717 *
3718 * Stored in 1.9 fixed point.
3719 */
3720# define TV_AU_MASK 0x000003ff
3721# define TV_AU_SHIFT 0
3722
3723#define TV_CSC_V 0x68020
3724# define TV_RV_MASK 0x0fff0000
3725# define TV_RV_SHIFT 16
3726# define TV_GV_MASK 0x000007ff
3727# define TV_GV_SHIFT 0
3728
3729#define TV_CSC_V2 0x68024
3730# define TV_BV_MASK 0x07ff0000
3731# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003732/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003733 * V attenuation for component video.
3734 *
3735 * Stored in 1.9 fixed point.
3736 */
3737# define TV_AV_MASK 0x000007ff
3738# define TV_AV_SHIFT 0
3739
3740#define TV_CLR_KNOBS 0x68028
Ville Syrjälä646b4262014-04-25 20:14:30 +03003741/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07003742# define TV_BRIGHTNESS_MASK 0xff000000
3743# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03003744/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003745# define TV_CONTRAST_MASK 0x00ff0000
3746# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003747/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003748# define TV_SATURATION_MASK 0x0000ff00
3749# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003750/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07003751# define TV_HUE_MASK 0x000000ff
3752# define TV_HUE_SHIFT 0
3753
3754#define TV_CLR_LEVEL 0x6802c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003755/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07003756# define TV_BLACK_LEVEL_MASK 0x01ff0000
3757# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003758/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07003759# define TV_BLANK_LEVEL_MASK 0x000001ff
3760# define TV_BLANK_LEVEL_SHIFT 0
3761
3762#define TV_H_CTL_1 0x68030
Ville Syrjälä646b4262014-04-25 20:14:30 +03003763/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003764# define TV_HSYNC_END_MASK 0x1fff0000
3765# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003766/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07003767# define TV_HTOTAL_MASK 0x00001fff
3768# define TV_HTOTAL_SHIFT 0
3769
3770#define TV_H_CTL_2 0x68034
Ville Syrjälä646b4262014-04-25 20:14:30 +03003771/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003772# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003773/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003774# define TV_HBURST_START_SHIFT 16
3775# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003776/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07003777# define TV_HBURST_LEN_SHIFT 0
3778# define TV_HBURST_LEN_MASK 0x0001fff
3779
3780#define TV_H_CTL_3 0x68038
Ville Syrjälä646b4262014-04-25 20:14:30 +03003781/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003782# define TV_HBLANK_END_SHIFT 16
3783# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003784/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003785# define TV_HBLANK_START_SHIFT 0
3786# define TV_HBLANK_START_MASK 0x0001fff
3787
3788#define TV_V_CTL_1 0x6803c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003789/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003790# define TV_NBR_END_SHIFT 16
3791# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003792/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003793# define TV_VI_END_F1_SHIFT 8
3794# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003795/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003796# define TV_VI_END_F2_SHIFT 0
3797# define TV_VI_END_F2_MASK 0x0000003f
3798
3799#define TV_V_CTL_2 0x68040
Ville Syrjälä646b4262014-04-25 20:14:30 +03003800/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003801# define TV_VSYNC_LEN_MASK 0x07ff0000
3802# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003803/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07003804 * number of half lines.
3805 */
3806# define TV_VSYNC_START_F1_MASK 0x00007f00
3807# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003808/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003809 * Offset of the start of vsync in field 2, measured in one less than the
3810 * number of half lines.
3811 */
3812# define TV_VSYNC_START_F2_MASK 0x0000007f
3813# define TV_VSYNC_START_F2_SHIFT 0
3814
3815#define TV_V_CTL_3 0x68044
Ville Syrjälä646b4262014-04-25 20:14:30 +03003816/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07003817# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003818/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003819# define TV_VEQ_LEN_MASK 0x007f0000
3820# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003821/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07003822 * the number of half lines.
3823 */
3824# define TV_VEQ_START_F1_MASK 0x0007f00
3825# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003826/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003827 * Offset of the start of equalization in field 2, measured in one less than
3828 * the number of half lines.
3829 */
3830# define TV_VEQ_START_F2_MASK 0x000007f
3831# define TV_VEQ_START_F2_SHIFT 0
3832
3833#define TV_V_CTL_4 0x68048
Ville Syrjälä646b4262014-04-25 20:14:30 +03003834/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003835 * Offset to start of vertical colorburst, measured in one less than the
3836 * number of lines from vertical start.
3837 */
3838# define TV_VBURST_START_F1_MASK 0x003f0000
3839# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003840/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003841 * Offset to the end of vertical colorburst, measured in one less than the
3842 * number of lines from the start of NBR.
3843 */
3844# define TV_VBURST_END_F1_MASK 0x000000ff
3845# define TV_VBURST_END_F1_SHIFT 0
3846
3847#define TV_V_CTL_5 0x6804c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003848/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003849 * Offset to start of vertical colorburst, measured in one less than the
3850 * number of lines from vertical start.
3851 */
3852# define TV_VBURST_START_F2_MASK 0x003f0000
3853# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003854/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003855 * Offset to the end of vertical colorburst, measured in one less than the
3856 * number of lines from the start of NBR.
3857 */
3858# define TV_VBURST_END_F2_MASK 0x000000ff
3859# define TV_VBURST_END_F2_SHIFT 0
3860
3861#define TV_V_CTL_6 0x68050
Ville Syrjälä646b4262014-04-25 20:14:30 +03003862/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003863 * Offset to start of vertical colorburst, measured in one less than the
3864 * number of lines from vertical start.
3865 */
3866# define TV_VBURST_START_F3_MASK 0x003f0000
3867# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003868/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003869 * Offset to the end of vertical colorburst, measured in one less than the
3870 * number of lines from the start of NBR.
3871 */
3872# define TV_VBURST_END_F3_MASK 0x000000ff
3873# define TV_VBURST_END_F3_SHIFT 0
3874
3875#define TV_V_CTL_7 0x68054
Ville Syrjälä646b4262014-04-25 20:14:30 +03003876/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003877 * Offset to start of vertical colorburst, measured in one less than the
3878 * number of lines from vertical start.
3879 */
3880# define TV_VBURST_START_F4_MASK 0x003f0000
3881# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003882/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003883 * Offset to the end of vertical colorburst, measured in one less than the
3884 * number of lines from the start of NBR.
3885 */
3886# define TV_VBURST_END_F4_MASK 0x000000ff
3887# define TV_VBURST_END_F4_SHIFT 0
3888
3889#define TV_SC_CTL_1 0x68060
Ville Syrjälä646b4262014-04-25 20:14:30 +03003890/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003891# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003892/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003893# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003894/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003895# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003896/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003897# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003898/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003899# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003900/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003901# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003902/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07003903# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003904/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003905# define TV_BURST_LEVEL_MASK 0x00ff0000
3906# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003907/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003908# define TV_SCDDA1_INC_MASK 0x00000fff
3909# define TV_SCDDA1_INC_SHIFT 0
3910
3911#define TV_SC_CTL_2 0x68064
Ville Syrjälä646b4262014-04-25 20:14:30 +03003912/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003913# define TV_SCDDA2_SIZE_MASK 0x7fff0000
3914# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003915/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003916# define TV_SCDDA2_INC_MASK 0x00007fff
3917# define TV_SCDDA2_INC_SHIFT 0
3918
3919#define TV_SC_CTL_3 0x68068
Ville Syrjälä646b4262014-04-25 20:14:30 +03003920/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003921# define TV_SCDDA3_SIZE_MASK 0x7fff0000
3922# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003923/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003924# define TV_SCDDA3_INC_MASK 0x00007fff
3925# define TV_SCDDA3_INC_SHIFT 0
3926
3927#define TV_WIN_POS 0x68070
Ville Syrjälä646b4262014-04-25 20:14:30 +03003928/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07003929# define TV_XPOS_MASK 0x1fff0000
3930# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003931/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003932# define TV_YPOS_MASK 0x00000fff
3933# define TV_YPOS_SHIFT 0
3934
3935#define TV_WIN_SIZE 0x68074
Ville Syrjälä646b4262014-04-25 20:14:30 +03003936/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003937# define TV_XSIZE_MASK 0x1fff0000
3938# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003939/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003940 * Vertical size of the display window, measured in pixels.
3941 *
3942 * Must be even for interlaced modes.
3943 */
3944# define TV_YSIZE_MASK 0x00000fff
3945# define TV_YSIZE_SHIFT 0
3946
3947#define TV_FILTER_CTL_1 0x68080
Ville Syrjälä646b4262014-04-25 20:14:30 +03003948/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003949 * Enables automatic scaling calculation.
3950 *
3951 * If set, the rest of the registers are ignored, and the calculated values can
3952 * be read back from the register.
3953 */
3954# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003955/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003956 * Disables the vertical filter.
3957 *
3958 * This is required on modes more than 1024 pixels wide */
3959# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003960/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07003961# define TV_VADAPT (1 << 28)
3962# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003963/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003964# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003965/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003966# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003967/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003968# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003969/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003970 * Sets the horizontal scaling factor.
3971 *
3972 * This should be the fractional part of the horizontal scaling factor divided
3973 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3974 *
3975 * (src width - 1) / ((oversample * dest width) - 1)
3976 */
3977# define TV_HSCALE_FRAC_MASK 0x00003fff
3978# define TV_HSCALE_FRAC_SHIFT 0
3979
3980#define TV_FILTER_CTL_2 0x68084
Ville Syrjälä646b4262014-04-25 20:14:30 +03003981/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003982 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3983 *
3984 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3985 */
3986# define TV_VSCALE_INT_MASK 0x00038000
3987# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003988/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003989 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3990 *
3991 * \sa TV_VSCALE_INT_MASK
3992 */
3993# define TV_VSCALE_FRAC_MASK 0x00007fff
3994# define TV_VSCALE_FRAC_SHIFT 0
3995
3996#define TV_FILTER_CTL_3 0x68088
Ville Syrjälä646b4262014-04-25 20:14:30 +03003997/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003998 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3999 *
4000 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4001 *
4002 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4003 */
4004# define TV_VSCALE_IP_INT_MASK 0x00038000
4005# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03004006/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004007 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4008 *
4009 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4010 *
4011 * \sa TV_VSCALE_IP_INT_MASK
4012 */
4013# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4014# define TV_VSCALE_IP_FRAC_SHIFT 0
4015
4016#define TV_CC_CONTROL 0x68090
4017# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004018/*
Jesse Barnes585fb112008-07-29 11:54:06 -07004019 * Specifies which field to send the CC data in.
4020 *
4021 * CC data is usually sent in field 0.
4022 */
4023# define TV_CC_FID_MASK (1 << 27)
4024# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03004025/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004026# define TV_CC_HOFF_MASK 0x03ff0000
4027# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004028/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07004029# define TV_CC_LINE_MASK 0x0000003f
4030# define TV_CC_LINE_SHIFT 0
4031
4032#define TV_CC_DATA 0x68094
4033# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03004034/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004035# define TV_CC_DATA_2_MASK 0x007f0000
4036# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03004037/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07004038# define TV_CC_DATA_1_MASK 0x0000007f
4039# define TV_CC_DATA_1_SHIFT 0
4040
4041#define TV_H_LUMA_0 0x68100
4042#define TV_H_LUMA_59 0x681ec
4043#define TV_H_CHROMA_0 0x68200
4044#define TV_H_CHROMA_59 0x682ec
4045#define TV_V_LUMA_0 0x68300
4046#define TV_V_LUMA_42 0x683a8
4047#define TV_V_CHROMA_0 0x68400
4048#define TV_V_CHROMA_42 0x684a8
4049
Keith Packard040d87f2009-05-30 20:42:33 -07004050/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004051#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07004052#define DP_B 0x64100
4053#define DP_C 0x64200
4054#define DP_D 0x64300
4055
4056#define DP_PORT_EN (1 << 31)
4057#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08004058#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03004059#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4060#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08004061
Keith Packard040d87f2009-05-30 20:42:33 -07004062/* Link training mode - select a suitable mode for each stage */
4063#define DP_LINK_TRAIN_PAT_1 (0 << 28)
4064#define DP_LINK_TRAIN_PAT_2 (1 << 28)
4065#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4066#define DP_LINK_TRAIN_OFF (3 << 28)
4067#define DP_LINK_TRAIN_MASK (3 << 28)
4068#define DP_LINK_TRAIN_SHIFT 28
Ville Syrjäläaad3d142014-06-28 02:04:25 +03004069#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4070#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
Keith Packard040d87f2009-05-30 20:42:33 -07004071
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004072/* CPT Link training mode */
4073#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4074#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4075#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4076#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4077#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4078#define DP_LINK_TRAIN_SHIFT_CPT 8
4079
Keith Packard040d87f2009-05-30 20:42:33 -07004080/* Signal voltages. These are mostly controlled by the other end */
4081#define DP_VOLTAGE_0_4 (0 << 25)
4082#define DP_VOLTAGE_0_6 (1 << 25)
4083#define DP_VOLTAGE_0_8 (2 << 25)
4084#define DP_VOLTAGE_1_2 (3 << 25)
4085#define DP_VOLTAGE_MASK (7 << 25)
4086#define DP_VOLTAGE_SHIFT 25
4087
4088/* Signal pre-emphasis levels, like voltages, the other end tells us what
4089 * they want
4090 */
4091#define DP_PRE_EMPHASIS_0 (0 << 22)
4092#define DP_PRE_EMPHASIS_3_5 (1 << 22)
4093#define DP_PRE_EMPHASIS_6 (2 << 22)
4094#define DP_PRE_EMPHASIS_9_5 (3 << 22)
4095#define DP_PRE_EMPHASIS_MASK (7 << 22)
4096#define DP_PRE_EMPHASIS_SHIFT 22
4097
4098/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02004099#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07004100#define DP_PORT_WIDTH_MASK (7 << 19)
4101
4102/* Mystic DPCD version 1.1 special mode */
4103#define DP_ENHANCED_FRAMING (1 << 18)
4104
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004105/* eDP */
4106#define DP_PLL_FREQ_270MHZ (0 << 16)
4107#define DP_PLL_FREQ_160MHZ (1 << 16)
4108#define DP_PLL_FREQ_MASK (3 << 16)
4109
Ville Syrjälä646b4262014-04-25 20:14:30 +03004110/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07004111#define DP_PORT_REVERSAL (1 << 15)
4112
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004113/* eDP */
4114#define DP_PLL_ENABLE (1 << 14)
4115
Ville Syrjälä646b4262014-04-25 20:14:30 +03004116/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07004117#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4118
4119#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004120#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07004121
Ville Syrjälä646b4262014-04-25 20:14:30 +03004122/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07004123#define DP_COLOR_RANGE_16_235 (1 << 8)
4124
Ville Syrjälä646b4262014-04-25 20:14:30 +03004125/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07004126#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4127
Ville Syrjälä646b4262014-04-25 20:14:30 +03004128/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07004129#define DP_SYNC_VS_HIGH (1 << 4)
4130#define DP_SYNC_HS_HIGH (1 << 3)
4131
Ville Syrjälä646b4262014-04-25 20:14:30 +03004132/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07004133#define DP_DETECTED (1 << 2)
4134
Ville Syrjälä646b4262014-04-25 20:14:30 +03004135/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07004136 * signal sink for DDC etc. Max packet size supported
4137 * is 20 bytes in each direction, hence the 5 fixed
4138 * data registers
4139 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004140#define DPA_AUX_CH_CTL 0x64010
4141#define DPA_AUX_CH_DATA1 0x64014
4142#define DPA_AUX_CH_DATA2 0x64018
4143#define DPA_AUX_CH_DATA3 0x6401c
4144#define DPA_AUX_CH_DATA4 0x64020
4145#define DPA_AUX_CH_DATA5 0x64024
4146
Keith Packard040d87f2009-05-30 20:42:33 -07004147#define DPB_AUX_CH_CTL 0x64110
4148#define DPB_AUX_CH_DATA1 0x64114
4149#define DPB_AUX_CH_DATA2 0x64118
4150#define DPB_AUX_CH_DATA3 0x6411c
4151#define DPB_AUX_CH_DATA4 0x64120
4152#define DPB_AUX_CH_DATA5 0x64124
4153
4154#define DPC_AUX_CH_CTL 0x64210
4155#define DPC_AUX_CH_DATA1 0x64214
4156#define DPC_AUX_CH_DATA2 0x64218
4157#define DPC_AUX_CH_DATA3 0x6421c
4158#define DPC_AUX_CH_DATA4 0x64220
4159#define DPC_AUX_CH_DATA5 0x64224
4160
4161#define DPD_AUX_CH_CTL 0x64310
4162#define DPD_AUX_CH_DATA1 0x64314
4163#define DPD_AUX_CH_DATA2 0x64318
4164#define DPD_AUX_CH_DATA3 0x6431c
4165#define DPD_AUX_CH_DATA4 0x64320
4166#define DPD_AUX_CH_DATA5 0x64324
4167
4168#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4169#define DP_AUX_CH_CTL_DONE (1 << 30)
4170#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4171#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4172#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4173#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4174#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4175#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4176#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4177#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4178#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4179#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4180#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4181#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4182#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4183#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4184#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4185#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4186#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4187#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4188#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
Sonika Jindale3d99842015-01-22 14:30:54 +05304189#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4190#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4191#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
4192#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
4193#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00004194#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
Keith Packard040d87f2009-05-30 20:42:33 -07004195
4196/*
4197 * Computing GMCH M and N values for the Display Port link
4198 *
4199 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4200 *
4201 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4202 *
4203 * The GMCH value is used internally
4204 *
4205 * bytes_per_pixel is the number of bytes coming out of the plane,
4206 * which is after the LUTs, so we want the bytes for our color format.
4207 * For our current usage, this is always 3, one byte for R, G and B.
4208 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02004209#define _PIPEA_DATA_M_G4X 0x70050
4210#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07004211
4212/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004213#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02004214#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004215#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07004216
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004217#define DATA_LINK_M_N_MASK (0xffffff)
4218#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07004219
Daniel Vettere3b95f12013-05-03 11:49:49 +02004220#define _PIPEA_DATA_N_G4X 0x70054
4221#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07004222#define PIPE_GMCH_DATA_N_MASK (0xffffff)
4223
4224/*
4225 * Computing Link M and N values for the Display Port link
4226 *
4227 * Link M / N = pixel_clock / ls_clk
4228 *
4229 * (the DP spec calls pixel_clock the 'strm_clk')
4230 *
4231 * The Link value is transmitted in the Main Stream
4232 * Attributes and VB-ID.
4233 */
4234
Daniel Vettere3b95f12013-05-03 11:49:49 +02004235#define _PIPEA_LINK_M_G4X 0x70060
4236#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07004237#define PIPEA_DP_LINK_M_MASK (0xffffff)
4238
Daniel Vettere3b95f12013-05-03 11:49:49 +02004239#define _PIPEA_LINK_N_G4X 0x70064
4240#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07004241#define PIPEA_DP_LINK_N_MASK (0xffffff)
4242
Daniel Vettere3b95f12013-05-03 11:49:49 +02004243#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4244#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4245#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4246#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004247
Jesse Barnes585fb112008-07-29 11:54:06 -07004248/* Display & cursor control */
4249
4250/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004251#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03004252#define DSL_LINEMASK_GEN2 0x00000fff
4253#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004254#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01004255#define PIPECONF_ENABLE (1<<31)
4256#define PIPECONF_DISABLE 0
4257#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07004258#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03004259#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00004260#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01004261#define PIPECONF_SINGLE_WIDE 0
4262#define PIPECONF_PIPE_UNLOCKED 0
4263#define PIPECONF_PIPE_LOCKED (1<<25)
4264#define PIPECONF_PALETTE 0
4265#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07004266#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01004267#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03004268#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01004269/* Note that pre-gen3 does not support interlaced display directly. Panel
4270 * fitting must be disabled on pre-ilk for interlaced. */
4271#define PIPECONF_PROGRESSIVE (0 << 21)
4272#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4273#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4274#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4275#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4276/* Ironlake and later have a complete new set of values for interlaced. PFIT
4277 * means panel fitter required, PF means progressive fetch, DBL means power
4278 * saving pixel doubling. */
4279#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4280#define PIPECONF_INTERLACED_ILK (3 << 21)
4281#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4282#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004283#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304284#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07004285#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05304286#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02004287#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004288#define PIPECONF_BPC_MASK (0x7 << 5)
4289#define PIPECONF_8BPC (0<<5)
4290#define PIPECONF_10BPC (1<<5)
4291#define PIPECONF_6BPC (2<<5)
4292#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07004293#define PIPECONF_DITHER_EN (1<<4)
4294#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4295#define PIPECONF_DITHER_TYPE_SP (0<<2)
4296#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4297#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4298#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004299#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07004300#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02004301#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07004302#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4303#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004304#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07004305#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004306#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004307#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4308#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4309#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4310#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02004311#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07004312#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4313#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4314#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02004315#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004316#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07004317#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4318#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004319#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07004320#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004321#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07004322#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02004323#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4324#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07004325#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4326#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004327#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07004328#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02004329#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07004330#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4331#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4332#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4333#define PIPE_DPST_EVENT_STATUS (1UL<<7)
Imre Deak10c59c52014-02-10 18:42:48 +02004334#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004335#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07004336#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4337#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02004338#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004339#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07004340#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4341#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004342#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07004343#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004344#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07004345#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4346
Imre Deak755e9012014-02-10 18:42:47 +02004347#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4348#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4349
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03004350#define PIPE_A_OFFSET 0x70000
4351#define PIPE_B_OFFSET 0x71000
4352#define PIPE_C_OFFSET 0x72000
4353#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004354/*
4355 * There's actually no pipe EDP. Some pipe registers have
4356 * simply shifted from the pipe to the transcoder, while
4357 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4358 * to access such registers in transcoder EDP.
4359 */
4360#define PIPE_EDP_OFFSET 0x7f000
4361
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004362#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4363 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4364 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004365
4366#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
4367#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
4368#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
4369#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
4370#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01004371
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004372#define _PIPE_MISC_A 0x70030
4373#define _PIPE_MISC_B 0x71030
4374#define PIPEMISC_DITHER_BPC_MASK (7<<5)
4375#define PIPEMISC_DITHER_8_BPC (0<<5)
4376#define PIPEMISC_DITHER_10_BPC (1<<5)
4377#define PIPEMISC_DITHER_6_BPC (2<<5)
4378#define PIPEMISC_DITHER_12_BPC (3<<5)
4379#define PIPEMISC_DITHER_ENABLE (1<<4)
4380#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4381#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004382#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004383
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02004384#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07004385#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004386#define PIPEB_HLINE_INT_EN (1<<28)
4387#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02004388#define SPRITED_FLIP_DONE_INT_EN (1<<26)
4389#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4390#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004391#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07004392#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004393#define PIPEA_HLINE_INT_EN (1<<20)
4394#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02004395#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4396#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004397#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004398#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4399#define PIPEC_HLINE_INT_EN (1<<12)
4400#define PIPEC_VBLANK_INT_EN (1<<11)
4401#define SPRITEF_FLIPDONE_INT_EN (1<<10)
4402#define SPRITEE_FLIPDONE_INT_EN (1<<9)
4403#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004404
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004405#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4406#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4407#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4408#define PLANEC_INVALID_GTT_INT_EN (1<<25)
4409#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004410#define CURSORB_INVALID_GTT_INT_EN (1<<23)
4411#define CURSORA_INVALID_GTT_INT_EN (1<<22)
4412#define SPRITED_INVALID_GTT_INT_EN (1<<21)
4413#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4414#define PLANEB_INVALID_GTT_INT_EN (1<<19)
4415#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4416#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4417#define PLANEA_INVALID_GTT_INT_EN (1<<16)
4418#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004419#define DPINVGTT_EN_MASK_CHV 0xfff0000
4420#define SPRITEF_INVALID_GTT_STATUS (1<<11)
4421#define SPRITEE_INVALID_GTT_STATUS (1<<10)
4422#define PLANEC_INVALID_GTT_STATUS (1<<9)
4423#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004424#define CURSORB_INVALID_GTT_STATUS (1<<7)
4425#define CURSORA_INVALID_GTT_STATUS (1<<6)
4426#define SPRITED_INVALID_GTT_STATUS (1<<5)
4427#define SPRITEC_INVALID_GTT_STATUS (1<<4)
4428#define PLANEB_INVALID_GTT_STATUS (1<<3)
4429#define SPRITEB_INVALID_GTT_STATUS (1<<2)
4430#define SPRITEA_INVALID_GTT_STATUS (1<<1)
4431#define PLANEA_INVALID_GTT_STATUS (1<<0)
4432#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004433#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004434
Ville Syrjäläb5004722015-03-05 21:19:47 +02004435#define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
Jesse Barnes585fb112008-07-29 11:54:06 -07004436#define DSPARB_CSTART_MASK (0x7f << 7)
4437#define DSPARB_CSTART_SHIFT 7
4438#define DSPARB_BSTART_MASK (0x7f)
4439#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08004440#define DSPARB_BEND_SHIFT 9 /* on 855 */
4441#define DSPARB_AEND_SHIFT 0
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004442#define DSPARB_SPRITEA_SHIFT_VLV 0
4443#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4444#define DSPARB_SPRITEB_SHIFT_VLV 8
4445#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4446#define DSPARB_SPRITEC_SHIFT_VLV 16
4447#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4448#define DSPARB_SPRITED_SHIFT_VLV 24
4449#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
Ville Syrjäläb5004722015-03-05 21:19:47 +02004450#define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004451#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4452#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4453#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4454#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4455#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4456#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4457#define DSPARB_SPRITED_HI_SHIFT_VLV 12
4458#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4459#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4460#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4461#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4462#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
Ville Syrjäläb5004722015-03-05 21:19:47 +02004463#define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */
Ville Syrjälä54f1b6e2015-06-24 22:00:05 +03004464#define DSPARB_SPRITEE_SHIFT_VLV 0
4465#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4466#define DSPARB_SPRITEF_SHIFT_VLV 8
4467#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
Ville Syrjäläb5004722015-03-05 21:19:47 +02004468
Ville Syrjälä0a560672014-06-11 16:51:18 +03004469/* pnv/gen4/g4x/vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004470#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004471#define DSPFW_SR_SHIFT 23
4472#define DSPFW_SR_MASK (0x1ff<<23)
4473#define DSPFW_CURSORB_SHIFT 16
4474#define DSPFW_CURSORB_MASK (0x3f<<16)
4475#define DSPFW_PLANEB_SHIFT 8
4476#define DSPFW_PLANEB_MASK (0x7f<<8)
4477#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4478#define DSPFW_PLANEA_SHIFT 0
4479#define DSPFW_PLANEA_MASK (0x7f<<0)
4480#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004481#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004482#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4483#define DSPFW_FBC_SR_SHIFT 28
4484#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4485#define DSPFW_FBC_HPLL_SR_SHIFT 24
4486#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4487#define DSPFW_SPRITEB_SHIFT (16)
4488#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4489#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4490#define DSPFW_CURSORA_SHIFT 8
4491#define DSPFW_CURSORA_MASK (0x3f<<8)
Ville Syrjäläf4998962015-03-10 17:02:21 +02004492#define DSPFW_PLANEC_OLD_SHIFT 0
4493#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004494#define DSPFW_SPRITEA_SHIFT 0
4495#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4496#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004497#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004498#define DSPFW_HPLL_SR_EN (1<<31)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004499#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004500#define DSPFW_CURSOR_SR_SHIFT 24
Zhao Yakuid4294342010-03-22 22:45:36 +08004501#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4502#define DSPFW_HPLL_CURSOR_SHIFT 16
4503#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004504#define DSPFW_HPLL_SR_SHIFT 0
4505#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4506
4507/* vlv/chv */
4508#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4509#define DSPFW_SPRITEB_WM1_SHIFT 16
4510#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4511#define DSPFW_CURSORA_WM1_SHIFT 8
4512#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4513#define DSPFW_SPRITEA_WM1_SHIFT 0
4514#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4515#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4516#define DSPFW_PLANEB_WM1_SHIFT 24
4517#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4518#define DSPFW_PLANEA_WM1_SHIFT 16
4519#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4520#define DSPFW_CURSORB_WM1_SHIFT 8
4521#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4522#define DSPFW_CURSOR_SR_WM1_SHIFT 0
4523#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4524#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4525#define DSPFW_SR_WM1_SHIFT 0
4526#define DSPFW_SR_WM1_MASK (0x1ff<<0)
4527#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4528#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4529#define DSPFW_SPRITED_WM1_SHIFT 24
4530#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4531#define DSPFW_SPRITED_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004532#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004533#define DSPFW_SPRITEC_WM1_SHIFT 8
4534#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4535#define DSPFW_SPRITEC_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004536#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004537#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4538#define DSPFW_SPRITEF_WM1_SHIFT 24
4539#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4540#define DSPFW_SPRITEF_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004541#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004542#define DSPFW_SPRITEE_WM1_SHIFT 8
4543#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4544#define DSPFW_SPRITEE_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004545#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004546#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4547#define DSPFW_PLANEC_WM1_SHIFT 24
4548#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4549#define DSPFW_PLANEC_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004550#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004551#define DSPFW_CURSORC_WM1_SHIFT 8
4552#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4553#define DSPFW_CURSORC_SHIFT 0
4554#define DSPFW_CURSORC_MASK (0x3f<<0)
4555
4556/* vlv/chv high order bits */
4557#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4558#define DSPFW_SR_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004559#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004560#define DSPFW_SPRITEF_HI_SHIFT 23
4561#define DSPFW_SPRITEF_HI_MASK (1<<23)
4562#define DSPFW_SPRITEE_HI_SHIFT 22
4563#define DSPFW_SPRITEE_HI_MASK (1<<22)
4564#define DSPFW_PLANEC_HI_SHIFT 21
4565#define DSPFW_PLANEC_HI_MASK (1<<21)
4566#define DSPFW_SPRITED_HI_SHIFT 20
4567#define DSPFW_SPRITED_HI_MASK (1<<20)
4568#define DSPFW_SPRITEC_HI_SHIFT 16
4569#define DSPFW_SPRITEC_HI_MASK (1<<16)
4570#define DSPFW_PLANEB_HI_SHIFT 12
4571#define DSPFW_PLANEB_HI_MASK (1<<12)
4572#define DSPFW_SPRITEB_HI_SHIFT 8
4573#define DSPFW_SPRITEB_HI_MASK (1<<8)
4574#define DSPFW_SPRITEA_HI_SHIFT 4
4575#define DSPFW_SPRITEA_HI_MASK (1<<4)
4576#define DSPFW_PLANEA_HI_SHIFT 0
4577#define DSPFW_PLANEA_HI_MASK (1<<0)
4578#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4579#define DSPFW_SR_WM1_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004580#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004581#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4582#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4583#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4584#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4585#define DSPFW_PLANEC_WM1_HI_SHIFT 21
4586#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4587#define DSPFW_SPRITED_WM1_HI_SHIFT 20
4588#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4589#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4590#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4591#define DSPFW_PLANEB_WM1_HI_SHIFT 12
4592#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4593#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4594#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4595#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4596#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4597#define DSPFW_PLANEA_WM1_HI_SHIFT 0
4598#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004599
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004600/* drain latency register values*/
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004601#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004602#define DDL_CURSOR_SHIFT 24
Gajanan Bhat01e184c2014-08-07 17:03:30 +05304603#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004604#define DDL_PLANE_SHIFT 0
Ville Syrjälä341c5262015-03-05 21:19:44 +02004605#define DDL_PRECISION_HIGH (1<<7)
4606#define DDL_PRECISION_LOW (0<<7)
Gajanan Bhat0948c262014-08-07 01:58:24 +05304607#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004608
Ville Syrjäläc6beb132015-03-05 21:19:48 +02004609#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
4610#define CBR_PND_DEADLINE_DISABLE (1<<31)
4611
Shaohua Li7662c8b2009-06-26 11:23:55 +08004612/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09004613#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08004614#define I915_FIFO_LINE_SIZE 64
4615#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09004616
Jesse Barnesceb04242012-03-28 13:39:22 -07004617#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09004618#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08004619#define I965_FIFO_SIZE 512
4620#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08004621#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004622#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004623#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09004624
Jesse Barnesceb04242012-03-28 13:39:22 -07004625#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09004626#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08004627#define I915_MAX_WM 0x3f
4628
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004629#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4630#define PINEVIEW_FIFO_LINE_SIZE 64
4631#define PINEVIEW_MAX_WM 0x1ff
4632#define PINEVIEW_DFT_WM 0x3f
4633#define PINEVIEW_DFT_HPLLOFF_WM 0
4634#define PINEVIEW_GUARD_WM 10
4635#define PINEVIEW_CURSOR_FIFO 64
4636#define PINEVIEW_CURSOR_MAX_WM 0x3f
4637#define PINEVIEW_CURSOR_DFT_WM 0
4638#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08004639
Jesse Barnesceb04242012-03-28 13:39:22 -07004640#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004641#define I965_CURSOR_FIFO 64
4642#define I965_CURSOR_MAX_WM 32
4643#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004644
Pradeep Bhatfae12672014-11-04 17:06:39 +00004645/* Watermark register definitions for SKL */
4646#define CUR_WM_A_0 0x70140
4647#define CUR_WM_B_0 0x71140
4648#define PLANE_WM_1_A_0 0x70240
4649#define PLANE_WM_1_B_0 0x71240
4650#define PLANE_WM_2_A_0 0x70340
4651#define PLANE_WM_2_B_0 0x71340
4652#define PLANE_WM_TRANS_1_A_0 0x70268
4653#define PLANE_WM_TRANS_1_B_0 0x71268
4654#define PLANE_WM_TRANS_2_A_0 0x70368
4655#define PLANE_WM_TRANS_2_B_0 0x71368
4656#define CUR_WM_TRANS_A_0 0x70168
4657#define CUR_WM_TRANS_B_0 0x71168
4658#define PLANE_WM_EN (1 << 31)
4659#define PLANE_WM_LINES_SHIFT 14
4660#define PLANE_WM_LINES_MASK 0x1f
4661#define PLANE_WM_BLOCKS_MASK 0x3ff
4662
4663#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4664#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4665#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4666
4667#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4668#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4669#define _PLANE_WM_BASE(pipe, plane) \
4670 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4671#define PLANE_WM(pipe, plane, level) \
4672 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4673#define _PLANE_WM_TRANS_1(pipe) \
4674 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4675#define _PLANE_WM_TRANS_2(pipe) \
4676 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4677#define PLANE_WM_TRANS(pipe, plane) \
4678 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4679
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004680/* define the Watermark register on Ironlake */
4681#define WM0_PIPEA_ILK 0x45100
Ville Syrjälä1996d622013-10-09 19:18:07 +03004682#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004683#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03004684#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004685#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004686#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004687
4688#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07004689#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004690#define WM1_LP_ILK 0x45108
4691#define WM1_LP_SR_EN (1<<31)
4692#define WM1_LP_LATENCY_SHIFT 24
4693#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01004694#define WM1_LP_FBC_MASK (0xf<<20)
4695#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07004696#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03004697#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004698#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004699#define WM1_LP_CURSOR_MASK (0xff)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004700#define WM2_LP_ILK 0x4510c
4701#define WM2_LP_EN (1<<31)
4702#define WM3_LP_ILK 0x45110
4703#define WM3_LP_EN (1<<31)
4704#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004705#define WM2S_LP_IVB 0x45124
4706#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004707#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004708
Paulo Zanonicca32e92013-05-31 11:45:06 -03004709#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4710 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4711 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4712
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004713/* Memory latency timer register */
4714#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08004715#define MLTR_WM1_SHIFT 0
4716#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004717/* the unit of memory self-refresh latency time is 0.5us */
4718#define ILK_SRLT_MASK 0x3f
4719
Yuanhan Liu13982612010-12-15 15:42:31 +08004720
4721/* the address where we get all kinds of latency value */
4722#define SSKPD 0x5d10
4723#define SSKPD_WM_MASK 0x3f
4724#define SSKPD_WM0_SHIFT 0
4725#define SSKPD_WM1_SHIFT 8
4726#define SSKPD_WM2_SHIFT 16
4727#define SSKPD_WM3_SHIFT 24
4728
Jesse Barnes585fb112008-07-29 11:54:06 -07004729/*
4730 * The two pipe frame counter registers are not synchronized, so
4731 * reading a stable value is somewhat tricky. The following code
4732 * should work:
4733 *
4734 * do {
4735 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4736 * PIPE_FRAME_HIGH_SHIFT;
4737 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4738 * PIPE_FRAME_LOW_SHIFT);
4739 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4740 * PIPE_FRAME_HIGH_SHIFT);
4741 * } while (high1 != high2);
4742 * frame = (high1 << 8) | low1;
4743 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004744#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07004745#define PIPE_FRAME_HIGH_MASK 0x0000ffff
4746#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004747#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07004748#define PIPE_FRAME_LOW_MASK 0xff000000
4749#define PIPE_FRAME_LOW_SHIFT 24
4750#define PIPE_PIXEL_MASK 0x00ffffff
4751#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004752/* GM45+ just has to be different */
Rafael Barbalhoeb6008a2014-03-31 18:21:29 +03004753#define _PIPEA_FRMCOUNT_GM45 0x70040
4754#define _PIPEA_FLIPCOUNT_GM45 0x70044
4755#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03004756#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07004757
4758/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004759#define _CURACNTR 0x70080
Jesse Barnes14b603912009-05-20 16:47:08 -04004760/* Old style CUR*CNTR flags (desktop 8xx) */
4761#define CURSOR_ENABLE 0x80000000
4762#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03004763#define CURSOR_STRIDE_SHIFT 28
4764#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004765#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b603912009-05-20 16:47:08 -04004766#define CURSOR_FORMAT_SHIFT 24
4767#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4768#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4769#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4770#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4771#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4772#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4773/* New style CUR*CNTR flags */
4774#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07004775#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304776#define CURSOR_MODE_128_32B_AX 0x02
4777#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07004778#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304779#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4780#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07004781#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b603912009-05-20 16:47:08 -04004782#define MCURSOR_PIPE_SELECT (1 << 28)
4783#define MCURSOR_PIPE_A 0x00
4784#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07004785#define MCURSOR_GAMMA_ENABLE (1 << 26)
Ville Syrjälä4398ad42014-10-23 07:41:34 -07004786#define CURSOR_ROTATE_180 (1<<15)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03004787#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004788#define _CURABASE 0x70084
4789#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07004790#define CURSOR_POS_MASK 0x007FF
4791#define CURSOR_POS_SIGN 0x8000
4792#define CURSOR_X_SHIFT 0
4793#define CURSOR_Y_SHIFT 16
Jesse Barnes14b603912009-05-20 16:47:08 -04004794#define CURSIZE 0x700a0
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004795#define _CURBCNTR 0x700c0
4796#define _CURBBASE 0x700c4
4797#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07004798
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004799#define _CURBCNTR_IVB 0x71080
4800#define _CURBBASE_IVB 0x71084
4801#define _CURBPOS_IVB 0x71088
4802
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004803#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4804 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4805 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00004806
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004807#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4808#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4809#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4810
4811#define CURSOR_A_OFFSET 0x70080
4812#define CURSOR_B_OFFSET 0x700c0
4813#define CHV_CURSOR_C_OFFSET 0x700e0
4814#define IVB_CURSOR_B_OFFSET 0x71080
4815#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004816
Jesse Barnes585fb112008-07-29 11:54:06 -07004817/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004818#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07004819#define DISPLAY_PLANE_ENABLE (1<<31)
4820#define DISPLAY_PLANE_DISABLE 0
4821#define DISPPLANE_GAMMA_ENABLE (1<<30)
4822#define DISPPLANE_GAMMA_DISABLE 0
4823#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004824#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004825#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004826#define DISPPLANE_BGRA555 (0x3<<26)
4827#define DISPPLANE_BGRX555 (0x4<<26)
4828#define DISPPLANE_BGRX565 (0x5<<26)
4829#define DISPPLANE_BGRX888 (0x6<<26)
4830#define DISPPLANE_BGRA888 (0x7<<26)
4831#define DISPPLANE_RGBX101010 (0x8<<26)
4832#define DISPPLANE_RGBA101010 (0x9<<26)
4833#define DISPPLANE_BGRX101010 (0xa<<26)
4834#define DISPPLANE_RGBX161616 (0xc<<26)
4835#define DISPPLANE_RGBX888 (0xe<<26)
4836#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004837#define DISPPLANE_STEREO_ENABLE (1<<25)
4838#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004839#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08004840#define DISPPLANE_SEL_PIPE_SHIFT 24
4841#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004842#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08004843#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004844#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4845#define DISPPLANE_SRC_KEY_DISABLE 0
4846#define DISPPLANE_LINE_DOUBLE (1<<20)
4847#define DISPPLANE_NO_LINE_DOUBLE 0
4848#define DISPPLANE_STEREO_POLARITY_FIRST 0
4849#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004850#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4851#define DISPPLANE_ROTATE_180 (1<<15)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004852#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07004853#define DISPPLANE_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004854#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004855#define _DSPAADDR 0x70184
4856#define _DSPASTRIDE 0x70188
4857#define _DSPAPOS 0x7018C /* reserved */
4858#define _DSPASIZE 0x70190
4859#define _DSPASURF 0x7019C /* 965+ only */
4860#define _DSPATILEOFF 0x701A4 /* 965+ only */
4861#define _DSPAOFFSET 0x701A4 /* HSW */
4862#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07004863
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004864#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4865#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4866#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4867#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4868#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4869#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4870#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
Daniel Vettere506a0c2012-07-05 12:17:29 +02004871#define DSPLINOFF(plane) DSPADDR(plane)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004872#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4873#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01004874
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004875/* CHV pipe B blender and primary plane */
4876#define _CHV_BLEND_A 0x60a00
4877#define CHV_BLEND_LEGACY (0<<30)
4878#define CHV_BLEND_ANDROID (1<<30)
4879#define CHV_BLEND_MPO (2<<30)
4880#define CHV_BLEND_MASK (3<<30)
4881#define _CHV_CANVAS_A 0x60a04
4882#define _PRIMPOS_A 0x60a08
4883#define _PRIMSIZE_A 0x60a0c
4884#define _PRIMCNSTALPHA_A 0x60a10
4885#define PRIM_CONST_ALPHA_ENABLE (1<<31)
4886
4887#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4888#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4889#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4890#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4891#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4892
Armin Reese446f2542012-03-30 16:20:16 -07004893/* Display/Sprite base address macros */
4894#define DISP_BASEADDR_MASK (0xfffff000)
4895#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4896#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07004897
Jesse Barnes585fb112008-07-29 11:54:06 -07004898/* VBIOS flags */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004899#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4900#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4901#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4902#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4903#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4904#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4905#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4906#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4907#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4908#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4909#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4910#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4911#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
Jesse Barnes585fb112008-07-29 11:54:06 -07004912
4913/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004914#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4915#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4916#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004917#define _PIPEBFRAMEHIGH 0x71040
4918#define _PIPEBFRAMEPIXEL 0x71044
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004919#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4920#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004921
Jesse Barnes585fb112008-07-29 11:54:06 -07004922
4923/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004924#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07004925#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4926#define DISPPLANE_ALPHA_TRANS_DISABLE 0
4927#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4928#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004929#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4930#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4931#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4932#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4933#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4934#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4935#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4936#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07004937
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004938/* Sprite A control */
4939#define _DVSACNTR 0x72180
4940#define DVS_ENABLE (1<<31)
4941#define DVS_GAMMA_ENABLE (1<<30)
4942#define DVS_PIXFORMAT_MASK (3<<25)
4943#define DVS_FORMAT_YUV422 (0<<25)
4944#define DVS_FORMAT_RGBX101010 (1<<25)
4945#define DVS_FORMAT_RGBX888 (2<<25)
4946#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004947#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004948#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08004949#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004950#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4951#define DVS_YUV_ORDER_YUYV (0<<16)
4952#define DVS_YUV_ORDER_UYVY (1<<16)
4953#define DVS_YUV_ORDER_YVYU (2<<16)
4954#define DVS_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304955#define DVS_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004956#define DVS_DEST_KEY (1<<2)
4957#define DVS_TRICKLE_FEED_DISABLE (1<<14)
4958#define DVS_TILED (1<<10)
4959#define _DVSALINOFF 0x72184
4960#define _DVSASTRIDE 0x72188
4961#define _DVSAPOS 0x7218c
4962#define _DVSASIZE 0x72190
4963#define _DVSAKEYVAL 0x72194
4964#define _DVSAKEYMSK 0x72198
4965#define _DVSASURF 0x7219c
4966#define _DVSAKEYMAXVAL 0x721a0
4967#define _DVSATILEOFF 0x721a4
4968#define _DVSASURFLIVE 0x721ac
4969#define _DVSASCALE 0x72204
4970#define DVS_SCALE_ENABLE (1<<31)
4971#define DVS_FILTER_MASK (3<<29)
4972#define DVS_FILTER_MEDIUM (0<<29)
4973#define DVS_FILTER_ENHANCING (1<<29)
4974#define DVS_FILTER_SOFTENING (2<<29)
4975#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4976#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4977#define _DVSAGAMC 0x72300
4978
4979#define _DVSBCNTR 0x73180
4980#define _DVSBLINOFF 0x73184
4981#define _DVSBSTRIDE 0x73188
4982#define _DVSBPOS 0x7318c
4983#define _DVSBSIZE 0x73190
4984#define _DVSBKEYVAL 0x73194
4985#define _DVSBKEYMSK 0x73198
4986#define _DVSBSURF 0x7319c
4987#define _DVSBKEYMAXVAL 0x731a0
4988#define _DVSBTILEOFF 0x731a4
4989#define _DVSBSURFLIVE 0x731ac
4990#define _DVSBSCALE 0x73204
4991#define _DVSBGAMC 0x73300
4992
4993#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4994#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4995#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4996#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4997#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004998#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004999#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5000#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5001#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08005002#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5003#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005004#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005005
5006#define _SPRA_CTL 0x70280
5007#define SPRITE_ENABLE (1<<31)
5008#define SPRITE_GAMMA_ENABLE (1<<30)
5009#define SPRITE_PIXFORMAT_MASK (7<<25)
5010#define SPRITE_FORMAT_YUV422 (0<<25)
5011#define SPRITE_FORMAT_RGBX101010 (1<<25)
5012#define SPRITE_FORMAT_RGBX888 (2<<25)
5013#define SPRITE_FORMAT_RGBX161616 (3<<25)
5014#define SPRITE_FORMAT_YUV444 (4<<25)
5015#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005016#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005017#define SPRITE_SOURCE_KEY (1<<22)
5018#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5019#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5020#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5021#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5022#define SPRITE_YUV_ORDER_YUYV (0<<16)
5023#define SPRITE_YUV_ORDER_UYVY (1<<16)
5024#define SPRITE_YUV_ORDER_YVYU (2<<16)
5025#define SPRITE_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05305026#define SPRITE_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005027#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5028#define SPRITE_INT_GAMMA_ENABLE (1<<13)
5029#define SPRITE_TILED (1<<10)
5030#define SPRITE_DEST_KEY (1<<2)
5031#define _SPRA_LINOFF 0x70284
5032#define _SPRA_STRIDE 0x70288
5033#define _SPRA_POS 0x7028c
5034#define _SPRA_SIZE 0x70290
5035#define _SPRA_KEYVAL 0x70294
5036#define _SPRA_KEYMSK 0x70298
5037#define _SPRA_SURF 0x7029c
5038#define _SPRA_KEYMAX 0x702a0
5039#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01005040#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005041#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005042#define _SPRA_SCALE 0x70304
5043#define SPRITE_SCALE_ENABLE (1<<31)
5044#define SPRITE_FILTER_MASK (3<<29)
5045#define SPRITE_FILTER_MEDIUM (0<<29)
5046#define SPRITE_FILTER_ENHANCING (1<<29)
5047#define SPRITE_FILTER_SOFTENING (2<<29)
5048#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5049#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5050#define _SPRA_GAMC 0x70400
5051
5052#define _SPRB_CTL 0x71280
5053#define _SPRB_LINOFF 0x71284
5054#define _SPRB_STRIDE 0x71288
5055#define _SPRB_POS 0x7128c
5056#define _SPRB_SIZE 0x71290
5057#define _SPRB_KEYVAL 0x71294
5058#define _SPRB_KEYMSK 0x71298
5059#define _SPRB_SURF 0x7129c
5060#define _SPRB_KEYMAX 0x712a0
5061#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01005062#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005063#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005064#define _SPRB_SCALE 0x71304
5065#define _SPRB_GAMC 0x71400
5066
5067#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5068#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5069#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5070#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
5071#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5072#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5073#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5074#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5075#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5076#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
Damien Lespiauc54173a2012-10-26 18:20:11 +01005077#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005078#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5079#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02005080#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08005081
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005082#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005083#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08005084#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005085#define SP_PIXFORMAT_MASK (0xf<<26)
5086#define SP_FORMAT_YUV422 (0<<26)
5087#define SP_FORMAT_BGR565 (5<<26)
5088#define SP_FORMAT_BGRX8888 (6<<26)
5089#define SP_FORMAT_BGRA8888 (7<<26)
5090#define SP_FORMAT_RGBX1010102 (8<<26)
5091#define SP_FORMAT_RGBA1010102 (9<<26)
5092#define SP_FORMAT_RGBX8888 (0xe<<26)
5093#define SP_FORMAT_RGBA8888 (0xf<<26)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005094#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005095#define SP_SOURCE_KEY (1<<22)
5096#define SP_YUV_BYTE_ORDER_MASK (3<<16)
5097#define SP_YUV_ORDER_YUYV (0<<16)
5098#define SP_YUV_ORDER_UYVY (1<<16)
5099#define SP_YUV_ORDER_YVYU (2<<16)
5100#define SP_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05305101#define SP_ROTATE_180 (1<<15)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005102#define SP_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005103#define SP_MIRROR (1<<8) /* CHV pipe B */
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005104#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5105#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5106#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5107#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5108#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5109#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5110#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5111#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5112#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5113#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03005114#define SP_CONST_ALPHA_ENABLE (1<<31)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005115#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005116
Ville Syrjälä921c3b62013-06-25 14:16:35 +03005117#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5118#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5119#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5120#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5121#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5122#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5123#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5124#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5125#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5126#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5127#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5128#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07005129
5130#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
5131#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
5132#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
5133#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
5134#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
5135#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
5136#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
5137#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
5138#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5139#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
5140#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
5141#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
5142
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03005143/*
5144 * CHV pipe B sprite CSC
5145 *
5146 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5147 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5148 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5149 */
5150#define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5151#define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5152#define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5153#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5154#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5155
5156#define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5157#define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5158#define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5159#define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5160#define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5161#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5162#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5163
5164#define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5165#define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5166#define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5167#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5168#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5169
5170#define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5171#define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5172#define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5173#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5174#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5175
Damien Lespiau70d21f02013-07-03 21:06:04 +01005176/* Skylake plane registers */
5177
5178#define _PLANE_CTL_1_A 0x70180
5179#define _PLANE_CTL_2_A 0x70280
5180#define _PLANE_CTL_3_A 0x70380
5181#define PLANE_CTL_ENABLE (1 << 31)
5182#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5183#define PLANE_CTL_FORMAT_MASK (0xf << 24)
5184#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5185#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5186#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5187#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5188#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5189#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5190#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5191#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5192#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005193#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5194#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5195#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
Damien Lespiau70d21f02013-07-03 21:06:04 +01005196#define PLANE_CTL_ORDER_BGRX (0 << 20)
5197#define PLANE_CTL_ORDER_RGBX (1 << 20)
5198#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5199#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5200#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5201#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5202#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5203#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5204#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5205#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5206#define PLANE_CTL_TILED_MASK (0x7 << 10)
5207#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5208#define PLANE_CTL_TILED_X ( 1 << 10)
5209#define PLANE_CTL_TILED_Y ( 4 << 10)
5210#define PLANE_CTL_TILED_YF ( 5 << 10)
5211#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5212#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5213#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5214#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
Sonika Jindal1447dde2014-10-04 10:53:31 +01005215#define PLANE_CTL_ROTATE_MASK 0x3
5216#define PLANE_CTL_ROTATE_0 0x0
Sonika Jindal3b7a5112015-04-10 14:37:29 +05305217#define PLANE_CTL_ROTATE_90 0x1
Sonika Jindal1447dde2014-10-04 10:53:31 +01005218#define PLANE_CTL_ROTATE_180 0x2
Sonika Jindal3b7a5112015-04-10 14:37:29 +05305219#define PLANE_CTL_ROTATE_270 0x3
Damien Lespiau70d21f02013-07-03 21:06:04 +01005220#define _PLANE_STRIDE_1_A 0x70188
5221#define _PLANE_STRIDE_2_A 0x70288
5222#define _PLANE_STRIDE_3_A 0x70388
5223#define _PLANE_POS_1_A 0x7018c
5224#define _PLANE_POS_2_A 0x7028c
5225#define _PLANE_POS_3_A 0x7038c
5226#define _PLANE_SIZE_1_A 0x70190
5227#define _PLANE_SIZE_2_A 0x70290
5228#define _PLANE_SIZE_3_A 0x70390
5229#define _PLANE_SURF_1_A 0x7019c
5230#define _PLANE_SURF_2_A 0x7029c
5231#define _PLANE_SURF_3_A 0x7039c
5232#define _PLANE_OFFSET_1_A 0x701a4
5233#define _PLANE_OFFSET_2_A 0x702a4
5234#define _PLANE_OFFSET_3_A 0x703a4
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005235#define _PLANE_KEYVAL_1_A 0x70194
5236#define _PLANE_KEYVAL_2_A 0x70294
5237#define _PLANE_KEYMSK_1_A 0x70198
5238#define _PLANE_KEYMSK_2_A 0x70298
5239#define _PLANE_KEYMAX_1_A 0x701a0
5240#define _PLANE_KEYMAX_2_A 0x702a0
Damien Lespiau8211bd52014-11-04 17:06:44 +00005241#define _PLANE_BUF_CFG_1_A 0x7027c
5242#define _PLANE_BUF_CFG_2_A 0x7037c
Chandra Konduru2cd601c2015-04-27 15:47:37 -07005243#define _PLANE_NV12_BUF_CFG_1_A 0x70278
5244#define _PLANE_NV12_BUF_CFG_2_A 0x70378
Damien Lespiau70d21f02013-07-03 21:06:04 +01005245
5246#define _PLANE_CTL_1_B 0x71180
5247#define _PLANE_CTL_2_B 0x71280
5248#define _PLANE_CTL_3_B 0x71380
5249#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5250#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5251#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5252#define PLANE_CTL(pipe, plane) \
5253 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5254
5255#define _PLANE_STRIDE_1_B 0x71188
5256#define _PLANE_STRIDE_2_B 0x71288
5257#define _PLANE_STRIDE_3_B 0x71388
5258#define _PLANE_STRIDE_1(pipe) \
5259 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5260#define _PLANE_STRIDE_2(pipe) \
5261 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5262#define _PLANE_STRIDE_3(pipe) \
5263 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5264#define PLANE_STRIDE(pipe, plane) \
5265 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5266
5267#define _PLANE_POS_1_B 0x7118c
5268#define _PLANE_POS_2_B 0x7128c
5269#define _PLANE_POS_3_B 0x7138c
5270#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5271#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5272#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5273#define PLANE_POS(pipe, plane) \
5274 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5275
5276#define _PLANE_SIZE_1_B 0x71190
5277#define _PLANE_SIZE_2_B 0x71290
5278#define _PLANE_SIZE_3_B 0x71390
5279#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5280#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5281#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5282#define PLANE_SIZE(pipe, plane) \
5283 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5284
5285#define _PLANE_SURF_1_B 0x7119c
5286#define _PLANE_SURF_2_B 0x7129c
5287#define _PLANE_SURF_3_B 0x7139c
5288#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5289#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5290#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5291#define PLANE_SURF(pipe, plane) \
5292 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5293
5294#define _PLANE_OFFSET_1_B 0x711a4
5295#define _PLANE_OFFSET_2_B 0x712a4
5296#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5297#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5298#define PLANE_OFFSET(pipe, plane) \
5299 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5300
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00005301#define _PLANE_KEYVAL_1_B 0x71194
5302#define _PLANE_KEYVAL_2_B 0x71294
5303#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5304#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5305#define PLANE_KEYVAL(pipe, plane) \
5306 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5307
5308#define _PLANE_KEYMSK_1_B 0x71198
5309#define _PLANE_KEYMSK_2_B 0x71298
5310#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5311#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5312#define PLANE_KEYMSK(pipe, plane) \
5313 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5314
5315#define _PLANE_KEYMAX_1_B 0x711a0
5316#define _PLANE_KEYMAX_2_B 0x712a0
5317#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5318#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5319#define PLANE_KEYMAX(pipe, plane) \
5320 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5321
Damien Lespiau8211bd52014-11-04 17:06:44 +00005322#define _PLANE_BUF_CFG_1_B 0x7127c
5323#define _PLANE_BUF_CFG_2_B 0x7137c
5324#define _PLANE_BUF_CFG_1(pipe) \
5325 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5326#define _PLANE_BUF_CFG_2(pipe) \
5327 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5328#define PLANE_BUF_CFG(pipe, plane) \
5329 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5330
Chandra Konduru2cd601c2015-04-27 15:47:37 -07005331#define _PLANE_NV12_BUF_CFG_1_B 0x71278
5332#define _PLANE_NV12_BUF_CFG_2_B 0x71378
5333#define _PLANE_NV12_BUF_CFG_1(pipe) \
5334 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5335#define _PLANE_NV12_BUF_CFG_2(pipe) \
5336 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5337#define PLANE_NV12_BUF_CFG(pipe, plane) \
5338 _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5339
Damien Lespiau8211bd52014-11-04 17:06:44 +00005340/* SKL new cursor registers */
5341#define _CUR_BUF_CFG_A 0x7017c
5342#define _CUR_BUF_CFG_B 0x7117c
5343#define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5344
Jesse Barnes585fb112008-07-29 11:54:06 -07005345/* VBIOS regs */
5346#define VGACNTRL 0x71400
5347# define VGA_DISP_DISABLE (1 << 31)
5348# define VGA_2X_MODE (1 << 30)
5349# define VGA_PIPE_B_SELECT (1 << 29)
5350
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02005351#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
5352
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005353/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005354
5355#define CPU_VGACNTRL 0x41000
5356
5357#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
5358#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5359#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
5360#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
5361#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
5362#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
5363#define DIGITAL_PORTA_NO_DETECT (0 << 0)
5364#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
5365#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
5366
5367/* refresh rate hardware control */
5368#define RR_HW_CTL 0x45300
5369#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5370#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5371
5372#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01005373#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08005374#define FDI_PLL_BIOS_1 0x46004
5375#define FDI_PLL_BIOS_2 0x46008
5376#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
5377#define DISPLAY_PORT_PLL_BIOS_1 0x46010
5378#define DISPLAY_PORT_PLL_BIOS_2 0x46014
5379
Eric Anholt8956c8b2010-03-18 13:21:14 -07005380#define PCH_3DCGDIS0 0x46020
5381# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5382# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5383
Eric Anholt06f37752010-12-14 10:06:46 -08005384#define PCH_3DCGDIS1 0x46024
5385# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5386
Zhenyu Wangb9055052009-06-05 15:38:38 +08005387#define FDI_PLL_FREQ_CTL 0x46030
5388#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5389#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5390#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5391
5392
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005393#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01005394#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005395#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01005396#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005397
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005398#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01005399#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005400#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01005401#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005402
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005403#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01005404#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005405#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01005406#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005407
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005408#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01005409#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005410#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01005411#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005412
5413/* PIPEB timing regs are same start from 0x61000 */
5414
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005415#define _PIPEB_DATA_M1 0x61030
5416#define _PIPEB_DATA_N1 0x61034
5417#define _PIPEB_DATA_M2 0x61038
5418#define _PIPEB_DATA_N2 0x6103c
5419#define _PIPEB_LINK_M1 0x61040
5420#define _PIPEB_LINK_N1 0x61044
5421#define _PIPEB_LINK_M2 0x61048
5422#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005423
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005424#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
5425#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
5426#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
5427#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
5428#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
5429#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
5430#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
5431#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005432
5433/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005434/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5435#define _PFA_CTL_1 0x68080
5436#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08005437#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02005438#define PF_PIPE_SEL_MASK_IVB (3<<29)
5439#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08005440#define PF_FILTER_MASK (3<<23)
5441#define PF_FILTER_PROGRAMMED (0<<23)
5442#define PF_FILTER_MED_3x3 (1<<23)
5443#define PF_FILTER_EDGE_ENHANCE (2<<23)
5444#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005445#define _PFA_WIN_SZ 0x68074
5446#define _PFB_WIN_SZ 0x68874
5447#define _PFA_WIN_POS 0x68070
5448#define _PFB_WIN_POS 0x68870
5449#define _PFA_VSCALE 0x68084
5450#define _PFB_VSCALE 0x68884
5451#define _PFA_HSCALE 0x68090
5452#define _PFB_HSCALE 0x68890
5453
5454#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5455#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5456#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5457#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5458#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005459
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005460#define _PSA_CTL 0x68180
5461#define _PSB_CTL 0x68980
5462#define PS_ENABLE (1<<31)
5463#define _PSA_WIN_SZ 0x68174
5464#define _PSB_WIN_SZ 0x68974
5465#define _PSA_WIN_POS 0x68170
5466#define _PSB_WIN_POS 0x68970
5467
5468#define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
5469#define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5470#define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5471
Chandra Konduru1c9a2d42015-04-07 15:28:35 -07005472/*
5473 * Skylake scalers
5474 */
5475#define _PS_1A_CTRL 0x68180
5476#define _PS_2A_CTRL 0x68280
5477#define _PS_1B_CTRL 0x68980
5478#define _PS_2B_CTRL 0x68A80
5479#define _PS_1C_CTRL 0x69180
5480#define PS_SCALER_EN (1 << 31)
5481#define PS_SCALER_MODE_MASK (3 << 28)
5482#define PS_SCALER_MODE_DYN (0 << 28)
5483#define PS_SCALER_MODE_HQ (1 << 28)
5484#define PS_PLANE_SEL_MASK (7 << 25)
5485#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
5486#define PS_FILTER_MASK (3 << 23)
5487#define PS_FILTER_MEDIUM (0 << 23)
5488#define PS_FILTER_EDGE_ENHANCE (2 << 23)
5489#define PS_FILTER_BILINEAR (3 << 23)
5490#define PS_VERT3TAP (1 << 21)
5491#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5492#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5493#define PS_PWRUP_PROGRESS (1 << 17)
5494#define PS_V_FILTER_BYPASS (1 << 8)
5495#define PS_VADAPT_EN (1 << 7)
5496#define PS_VADAPT_MODE_MASK (3 << 5)
5497#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5498#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5499#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5500
5501#define _PS_PWR_GATE_1A 0x68160
5502#define _PS_PWR_GATE_2A 0x68260
5503#define _PS_PWR_GATE_1B 0x68960
5504#define _PS_PWR_GATE_2B 0x68A60
5505#define _PS_PWR_GATE_1C 0x69160
5506#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5507#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5508#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5509#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5510#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5511#define PS_PWR_GATE_SLPEN_8 0
5512#define PS_PWR_GATE_SLPEN_16 1
5513#define PS_PWR_GATE_SLPEN_24 2
5514#define PS_PWR_GATE_SLPEN_32 3
5515
5516#define _PS_WIN_POS_1A 0x68170
5517#define _PS_WIN_POS_2A 0x68270
5518#define _PS_WIN_POS_1B 0x68970
5519#define _PS_WIN_POS_2B 0x68A70
5520#define _PS_WIN_POS_1C 0x69170
5521
5522#define _PS_WIN_SZ_1A 0x68174
5523#define _PS_WIN_SZ_2A 0x68274
5524#define _PS_WIN_SZ_1B 0x68974
5525#define _PS_WIN_SZ_2B 0x68A74
5526#define _PS_WIN_SZ_1C 0x69174
5527
5528#define _PS_VSCALE_1A 0x68184
5529#define _PS_VSCALE_2A 0x68284
5530#define _PS_VSCALE_1B 0x68984
5531#define _PS_VSCALE_2B 0x68A84
5532#define _PS_VSCALE_1C 0x69184
5533
5534#define _PS_HSCALE_1A 0x68190
5535#define _PS_HSCALE_2A 0x68290
5536#define _PS_HSCALE_1B 0x68990
5537#define _PS_HSCALE_2B 0x68A90
5538#define _PS_HSCALE_1C 0x69190
5539
5540#define _PS_VPHASE_1A 0x68188
5541#define _PS_VPHASE_2A 0x68288
5542#define _PS_VPHASE_1B 0x68988
5543#define _PS_VPHASE_2B 0x68A88
5544#define _PS_VPHASE_1C 0x69188
5545
5546#define _PS_HPHASE_1A 0x68194
5547#define _PS_HPHASE_2A 0x68294
5548#define _PS_HPHASE_1B 0x68994
5549#define _PS_HPHASE_2B 0x68A94
5550#define _PS_HPHASE_1C 0x69194
5551
5552#define _PS_ECC_STAT_1A 0x681D0
5553#define _PS_ECC_STAT_2A 0x682D0
5554#define _PS_ECC_STAT_1B 0x689D0
5555#define _PS_ECC_STAT_2B 0x68AD0
5556#define _PS_ECC_STAT_1C 0x691D0
5557
5558#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5559#define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \
5560 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5561 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5562#define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \
5563 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5564 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5565#define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \
5566 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5567 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5568#define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \
5569 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5570 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5571#define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \
5572 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5573 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5574#define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \
5575 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5576 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5577#define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \
5578 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5579 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5580#define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \
5581 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5582 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5583#define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \
5584 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5585 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
5586
Zhenyu Wangb9055052009-06-05 15:38:38 +08005587/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005588#define _LGC_PALETTE_A 0x4a000
5589#define _LGC_PALETTE_B 0x4a800
5590#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005591
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005592#define _GAMMA_MODE_A 0x4a480
5593#define _GAMMA_MODE_B 0x4ac80
5594#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5595#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005596#define GAMMA_MODE_MODE_8BIT (0 << 0)
5597#define GAMMA_MODE_MODE_10BIT (1 << 0)
5598#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005599#define GAMMA_MODE_MODE_SPLIT (3 << 0)
5600
Zhenyu Wangb9055052009-06-05 15:38:38 +08005601/* interrupts */
5602#define DE_MASTER_IRQ_CONTROL (1 << 31)
5603#define DE_SPRITEB_FLIP_DONE (1 << 29)
5604#define DE_SPRITEA_FLIP_DONE (1 << 28)
5605#define DE_PLANEB_FLIP_DONE (1 << 27)
5606#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005607#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005608#define DE_PCU_EVENT (1 << 25)
5609#define DE_GTT_FAULT (1 << 24)
5610#define DE_POISON (1 << 23)
5611#define DE_PERFORM_COUNTER (1 << 22)
5612#define DE_PCH_EVENT (1 << 21)
5613#define DE_AUX_CHANNEL_A (1 << 20)
5614#define DE_DP_A_HOTPLUG (1 << 19)
5615#define DE_GSE (1 << 18)
5616#define DE_PIPEB_VBLANK (1 << 15)
5617#define DE_PIPEB_EVEN_FIELD (1 << 14)
5618#define DE_PIPEB_ODD_FIELD (1 << 13)
5619#define DE_PIPEB_LINE_COMPARE (1 << 12)
5620#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005621#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005622#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5623#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005624#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005625#define DE_PIPEA_EVEN_FIELD (1 << 6)
5626#define DE_PIPEA_ODD_FIELD (1 << 5)
5627#define DE_PIPEA_LINE_COMPARE (1 << 4)
5628#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005629#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005630#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005631#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005632#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005633
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005634/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03005635#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005636#define DE_GSE_IVB (1<<29)
5637#define DE_PCH_EVENT_IVB (1<<28)
5638#define DE_DP_A_HOTPLUG_IVB (1<<27)
5639#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01005640#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5641#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5642#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005643#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005644#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005645#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01005646#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5647#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c22013-10-21 18:04:36 +02005648#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005649#define DE_PIPEA_VBLANK_IVB (1<<0)
Paulo Zanonib5184212013-07-12 20:00:08 -03005650#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
5651
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07005652#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5653#define MASTER_INTERRUPT_ENABLE (1<<31)
5654
Zhenyu Wangb9055052009-06-05 15:38:38 +08005655#define DEISR 0x44000
5656#define DEIMR 0x44004
5657#define DEIIR 0x44008
5658#define DEIER 0x4400c
5659
Zhenyu Wangb9055052009-06-05 15:38:38 +08005660#define GTISR 0x44010
5661#define GTIMR 0x44014
5662#define GTIIR 0x44018
5663#define GTIER 0x4401c
5664
Ben Widawskyabd58f02013-11-02 21:07:09 -07005665#define GEN8_MASTER_IRQ 0x44200
5666#define GEN8_MASTER_IRQ_CONTROL (1<<31)
5667#define GEN8_PCU_IRQ (1<<30)
5668#define GEN8_DE_PCH_IRQ (1<<23)
5669#define GEN8_DE_MISC_IRQ (1<<22)
5670#define GEN8_DE_PORT_IRQ (1<<20)
5671#define GEN8_DE_PIPE_C_IRQ (1<<18)
5672#define GEN8_DE_PIPE_B_IRQ (1<<17)
5673#define GEN8_DE_PIPE_A_IRQ (1<<16)
Daniel Vetterc42664c2013-11-07 11:05:40 +01005674#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
Ben Widawskyabd58f02013-11-02 21:07:09 -07005675#define GEN8_GT_VECS_IRQ (1<<6)
Ben Widawsky09610212014-05-15 20:58:08 +03005676#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005677#define GEN8_GT_VCS2_IRQ (1<<3)
5678#define GEN8_GT_VCS1_IRQ (1<<2)
5679#define GEN8_GT_BCS_IRQ (1<<1)
5680#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005681
5682#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5683#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5684#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5685#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5686
5687#define GEN8_BCS_IRQ_SHIFT 16
5688#define GEN8_RCS_IRQ_SHIFT 0
5689#define GEN8_VCS2_IRQ_SHIFT 16
5690#define GEN8_VCS1_IRQ_SHIFT 0
5691#define GEN8_VECS_IRQ_SHIFT 0
5692
5693#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5694#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5695#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5696#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01005697#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005698#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5699#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5700#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5701#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5702#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5703#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01005704#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005705#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5706#define GEN8_PIPE_VSYNC (1 << 1)
5707#define GEN8_PIPE_VBLANK (1 << 0)
Damien Lespiau770de832014-03-20 20:45:01 +00005708#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
Damien Lespiaub21249c2015-03-17 11:39:33 +02005709#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
Damien Lespiau770de832014-03-20 20:45:01 +00005710#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5711#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5712#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
Damien Lespiaub21249c2015-03-17 11:39:33 +02005713#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
Damien Lespiau770de832014-03-20 20:45:01 +00005714#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5715#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5716#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5717#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
Daniel Vetter30100f22013-11-07 14:49:24 +01005718#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5719 (GEN8_PIPE_CURSOR_FAULT | \
5720 GEN8_PIPE_SPRITE_FAULT | \
5721 GEN8_PIPE_PRIMARY_FAULT)
Damien Lespiau770de832014-03-20 20:45:01 +00005722#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5723 (GEN9_PIPE_CURSOR_FAULT | \
Damien Lespiaub21249c2015-03-17 11:39:33 +02005724 GEN9_PIPE_PLANE4_FAULT | \
Damien Lespiau770de832014-03-20 20:45:01 +00005725 GEN9_PIPE_PLANE3_FAULT | \
5726 GEN9_PIPE_PLANE2_FAULT | \
5727 GEN9_PIPE_PLANE1_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005728
5729#define GEN8_DE_PORT_ISR 0x44440
5730#define GEN8_DE_PORT_IMR 0x44444
5731#define GEN8_DE_PORT_IIR 0x44448
5732#define GEN8_DE_PORT_IER 0x4444c
Jesse Barnes88e04702014-11-13 17:51:48 +00005733#define GEN9_AUX_CHANNEL_D (1 << 27)
5734#define GEN9_AUX_CHANNEL_C (1 << 26)
5735#define GEN9_AUX_CHANNEL_B (1 << 25)
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02005736#define BXT_DE_PORT_HP_DDIC (1 << 5)
5737#define BXT_DE_PORT_HP_DDIB (1 << 4)
5738#define BXT_DE_PORT_HP_DDIA (1 << 3)
5739#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
5740 BXT_DE_PORT_HP_DDIB | \
5741 BXT_DE_PORT_HP_DDIC)
5742#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
Shashank Sharma9e637432014-08-22 17:40:43 +05305743#define BXT_DE_PORT_GMBUS (1 << 1)
Daniel Vetter6d766f02013-11-07 14:49:55 +01005744#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005745
5746#define GEN8_DE_MISC_ISR 0x44460
5747#define GEN8_DE_MISC_IMR 0x44464
5748#define GEN8_DE_MISC_IIR 0x44468
5749#define GEN8_DE_MISC_IER 0x4446c
5750#define GEN8_DE_MISC_GSE (1 << 27)
5751
5752#define GEN8_PCU_ISR 0x444e0
5753#define GEN8_PCU_IMR 0x444e4
5754#define GEN8_PCU_IIR 0x444e8
5755#define GEN8_PCU_IER 0x444ec
5756
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02005757/* BXT hotplug control */
5758#define BXT_HOTPLUG_CTL 0xC4030
5759#define BXT_DDIA_HPD_ENABLE (1 << 28)
5760#define BXT_DDIA_HPD_STATUS (3 << 24)
5761#define BXT_DDIC_HPD_ENABLE (1 << 12)
5762#define BXT_DDIC_HPD_STATUS (3 << 8)
5763#define BXT_DDIB_HPD_ENABLE (1 << 4)
5764#define BXT_DDIB_HPD_STATUS (3 << 0)
5765#define BXT_HOTPLUG_CTL_MASK (BXT_DDIA_HPD_ENABLE | \
5766 BXT_DDIB_HPD_ENABLE | \
5767 BXT_DDIC_HPD_ENABLE)
5768#define BXT_HPD_STATUS_MASK (BXT_DDIA_HPD_STATUS | \
5769 BXT_DDIB_HPD_STATUS | \
5770 BXT_DDIC_HPD_STATUS)
5771
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005772#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07005773/* Required on all Ironlake and Sandybridge according to the B-Spec. */
5774#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005775#define ILK_DPARB_GATE (1<<22)
5776#define ILK_VSDPFD_FULL (1<<21)
Damien Lespiaue3589902014-02-07 19:12:50 +00005777#define FUSE_STRAP 0x42014
5778#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5779#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5780#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5781#define ILK_HDCP_DISABLE (1 << 25)
5782#define ILK_eDP_A_DISABLE (1 << 24)
5783#define HSW_CDCLK_LIMIT (1 << 24)
5784#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08005785
Damien Lespiau231e54f2012-10-19 17:55:41 +01005786#define ILK_DSPCLK_GATE_D 0x42020
5787#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5788#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5789#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5790#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5791#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005792
Eric Anholt116ac8d2011-12-21 10:31:09 -08005793#define IVB_CHICKEN3 0x4200c
5794# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5795# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5796
Paulo Zanoni90a88642013-05-03 17:23:45 -03005797#define CHICKEN_PAR1_1 0x42080
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005798#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03005799#define FORCE_ARB_IDLE_PLANES (1 << 14)
5800
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005801#define _CHICKEN_PIPESL_1_A 0x420b0
5802#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02005803#define HSW_FBCQ_DIS (1 << 22)
5804#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005805#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5806
Zhenyu Wang553bd142009-09-02 10:57:52 +08005807#define DISP_ARB_CTL 0x45000
5808#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005809#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02005810#define DISP_ARB_CTL2 0x45004
5811#define DISP_DATA_PARTITION_5_6 (1<<6)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305812#define DBUF_CTL 0x45008
5813#define DBUF_POWER_REQUEST (1<<31)
5814#define DBUF_POWER_STATE (1<<30)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07005815#define GEN7_MSG_CTL 0x45010
5816#define WAIT_FOR_PCH_RESET_ACK (1<<1)
5817#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01005818#define HSW_NDE_RSTWRN_OPT 0x46408
5819#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08005820
Damien Lespiaua9419e82015-06-04 18:21:30 +01005821#define SKL_DFSM 0x51000
5822#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5823#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5824#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5825#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5826#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5827
Damien Lespiauf1d3d342015-05-06 14:36:27 +01005828#define FF_SLICE_CS_CHICKEN2 0x20e4
Damien Lespiau2caa3b22015-02-09 19:33:20 +00005829#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
5830
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005831/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08005832#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5833# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Damien Lespiau183c6da2015-02-09 19:33:11 +00005834# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
Ben Widawskya75f3622013-11-02 21:07:59 -07005835#define COMMON_SLICE_CHICKEN2 0x7014
5836# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08005837
Damien Lespiaud0bbbc4f2015-02-09 19:33:16 +00005838#define HIZ_CHICKEN 0x7018
5839# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
5840# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
Kenneth Graunked60de812015-01-10 18:02:22 -08005841
Damien Lespiau183c6da2015-02-09 19:33:11 +00005842#define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308
5843#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
5844
Ville Syrjälä031994e2014-01-22 21:32:46 +02005845#define GEN7_L3SQCREG1 0xB010
5846#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5847
Rodrigo Vivi51ce4db2015-03-31 16:03:21 -07005848#define GEN8_L3SQCREG1 0xB100
5849#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
5850
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005851#define GEN7_L3CNTLREG1 0xB01C
Chris Wilson1af84522014-02-14 22:34:43 +00005852#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07005853#define GEN7_L3AGDIS (1<<19)
Brad Volkinc9224fa2014-06-17 14:10:34 -07005854#define GEN7_L3CNTLREG2 0xB020
5855#define GEN7_L3CNTLREG3 0xB024
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005856
5857#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5858#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5859
Jesse Barnes61939d92012-10-02 17:43:38 -05005860#define GEN7_L3SQCREG4 0xb034
5861#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5862
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00005863#define GEN8_L3SQCREG4 0xb118
5864#define GEN8_LQSC_RO_PERF_DIS (1<<27)
Arun Siluveryc82435b2015-06-19 18:37:13 +01005865#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00005866
Ben Widawsky63801f22013-12-12 17:26:03 -08005867/* GEN8 chicken */
5868#define HDC_CHICKEN0 0x7300
Imre Deak2a0ee942015-05-19 17:05:41 +03005869#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
Rodrigo Vivida096542014-09-19 20:16:27 -04005870#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
Damien Lespiau35cb6f32015-02-10 10:31:00 +00005871#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5872#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
5873#define HDC_FORCE_NON_COHERENT (1<<4)
Damien Lespiau65ca7512015-02-09 19:33:22 +00005874#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
Ben Widawsky63801f22013-12-12 17:26:03 -08005875
Ben Widawsky38a39a72015-03-11 10:54:53 +02005876/* GEN9 chicken */
5877#define SLICE_ECO_CHICKEN0 0x7308
5878#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
5879
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08005880/* WaCatErrorRejectionIssue */
5881#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5882#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5883
Francisco Jerezf3fc4882013-10-02 15:53:16 -07005884#define HSW_SCRATCH1 0xb038
5885#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5886
Damien Lespiau77719d22015-02-09 19:33:13 +00005887#define BDW_SCRATCH1 0xb11c
5888#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
5889
Zhenyu Wangb9055052009-06-05 15:38:38 +08005890/* PCH */
5891
Adam Jackson23e81d62012-06-06 15:45:44 -04005892/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08005893#define SDE_AUDIO_POWER_D (1 << 27)
5894#define SDE_AUDIO_POWER_C (1 << 26)
5895#define SDE_AUDIO_POWER_B (1 << 25)
5896#define SDE_AUDIO_POWER_SHIFT (25)
5897#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5898#define SDE_GMBUS (1 << 24)
5899#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5900#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5901#define SDE_AUDIO_HDCP_MASK (3 << 22)
5902#define SDE_AUDIO_TRANSB (1 << 21)
5903#define SDE_AUDIO_TRANSA (1 << 20)
5904#define SDE_AUDIO_TRANS_MASK (3 << 20)
5905#define SDE_POISON (1 << 19)
5906/* 18 reserved */
5907#define SDE_FDI_RXB (1 << 17)
5908#define SDE_FDI_RXA (1 << 16)
5909#define SDE_FDI_MASK (3 << 16)
5910#define SDE_AUXD (1 << 15)
5911#define SDE_AUXC (1 << 14)
5912#define SDE_AUXB (1 << 13)
5913#define SDE_AUX_MASK (7 << 13)
5914/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005915#define SDE_CRT_HOTPLUG (1 << 11)
5916#define SDE_PORTD_HOTPLUG (1 << 10)
5917#define SDE_PORTC_HOTPLUG (1 << 9)
5918#define SDE_PORTB_HOTPLUG (1 << 8)
5919#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05005920#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5921 SDE_SDVOB_HOTPLUG | \
5922 SDE_PORTB_HOTPLUG | \
5923 SDE_PORTC_HOTPLUG | \
5924 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08005925#define SDE_TRANSB_CRC_DONE (1 << 5)
5926#define SDE_TRANSB_CRC_ERR (1 << 4)
5927#define SDE_TRANSB_FIFO_UNDER (1 << 3)
5928#define SDE_TRANSA_CRC_DONE (1 << 2)
5929#define SDE_TRANSA_CRC_ERR (1 << 1)
5930#define SDE_TRANSA_FIFO_UNDER (1 << 0)
5931#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04005932
5933/* south display engine interrupt: CPT/PPT */
5934#define SDE_AUDIO_POWER_D_CPT (1 << 31)
5935#define SDE_AUDIO_POWER_C_CPT (1 << 30)
5936#define SDE_AUDIO_POWER_B_CPT (1 << 29)
5937#define SDE_AUDIO_POWER_SHIFT_CPT 29
5938#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5939#define SDE_AUXD_CPT (1 << 27)
5940#define SDE_AUXC_CPT (1 << 26)
5941#define SDE_AUXB_CPT (1 << 25)
5942#define SDE_AUX_MASK_CPT (7 << 25)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005943#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5944#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5945#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04005946#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01005947#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01005948#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01005949 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01005950 SDE_PORTD_HOTPLUG_CPT | \
5951 SDE_PORTC_HOTPLUG_CPT | \
5952 SDE_PORTB_HOTPLUG_CPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04005953#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03005954#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04005955#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5956#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5957#define SDE_FDI_RXC_CPT (1 << 8)
5958#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5959#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5960#define SDE_FDI_RXB_CPT (1 << 4)
5961#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5962#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5963#define SDE_FDI_RXA_CPT (1 << 0)
5964#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5965 SDE_AUDIO_CP_REQ_B_CPT | \
5966 SDE_AUDIO_CP_REQ_A_CPT)
5967#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5968 SDE_AUDIO_CP_CHG_B_CPT | \
5969 SDE_AUDIO_CP_CHG_A_CPT)
5970#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5971 SDE_FDI_RXB_CPT | \
5972 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005973
5974#define SDEISR 0xc4000
5975#define SDEIMR 0xc4004
5976#define SDEIIR 0xc4008
5977#define SDEIER 0xc400c
5978
Paulo Zanoni86642812013-04-12 17:57:57 -03005979#define SERR_INT 0xc4040
Paulo Zanonide032bf2013-04-12 17:57:58 -03005980#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03005981#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
5982#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
5983#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Daniel Vetter1dd246f2013-07-10 08:30:23 +02005984#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03005985
Zhenyu Wangb9055052009-06-05 15:38:38 +08005986/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07005987#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Imre Deak63c88d22015-07-20 14:43:39 -07005988#define BXT_PORTA_HOTPLUG_ENABLE (1 << 28)
5989#define BXT_PORTA_HOTPLUG_STATUS_MASK (0x3 << 24)
5990#define BXT_PORTA_HOTPLUG_NO_DETECT (0 << 24)
5991#define BXT_PORTA_HOTPLUG_SHORT_DETECT (1 << 24)
5992#define BXT_PORTA_HOTPLUG_LONG_DETECT (2 << 24)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005993#define PORTD_HOTPLUG_ENABLE (1 << 20)
5994#define PORTD_PULSE_DURATION_2ms (0)
5995#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
5996#define PORTD_PULSE_DURATION_6ms (2 << 18)
5997#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07005998#define PORTD_PULSE_DURATION_MASK (3 << 18)
Damien Lespiaub6965192012-12-13 16:08:59 +00005999#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
6000#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
6001#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
6002#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006003#define PORTC_HOTPLUG_ENABLE (1 << 12)
6004#define PORTC_PULSE_DURATION_2ms (0)
6005#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
6006#define PORTC_PULSE_DURATION_6ms (2 << 10)
6007#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07006008#define PORTC_PULSE_DURATION_MASK (3 << 10)
Damien Lespiaub6965192012-12-13 16:08:59 +00006009#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
6010#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6011#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6012#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006013#define PORTB_HOTPLUG_ENABLE (1 << 4)
6014#define PORTB_PULSE_DURATION_2ms (0)
6015#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
6016#define PORTB_PULSE_DURATION_6ms (2 << 2)
6017#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07006018#define PORTB_PULSE_DURATION_MASK (3 << 2)
Damien Lespiaub6965192012-12-13 16:08:59 +00006019#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
6020#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6021#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6022#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006023
6024#define PCH_GPIOA 0xc5010
6025#define PCH_GPIOB 0xc5014
6026#define PCH_GPIOC 0xc5018
6027#define PCH_GPIOD 0xc501c
6028#define PCH_GPIOE 0xc5020
6029#define PCH_GPIOF 0xc5024
6030
Eric Anholtf0217c42009-12-01 11:56:30 -08006031#define PCH_GMBUS0 0xc5100
6032#define PCH_GMBUS1 0xc5104
6033#define PCH_GMBUS2 0xc5108
6034#define PCH_GMBUS3 0xc510c
6035#define PCH_GMBUS4 0xc5110
6036#define PCH_GMBUS5 0xc5120
6037
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006038#define _PCH_DPLL_A 0xc6014
6039#define _PCH_DPLL_B 0xc6018
Daniel Vettere9a632a2013-06-05 13:34:13 +02006040#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006041
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006042#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00006043#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006044#define _PCH_FPA1 0xc6044
6045#define _PCH_FPB0 0xc6048
6046#define _PCH_FPB1 0xc604c
Daniel Vettere9a632a2013-06-05 13:34:13 +02006047#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6048#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006049
6050#define PCH_DPLL_TEST 0xc606c
6051
6052#define PCH_DREF_CONTROL 0xC6200
6053#define DREF_CONTROL_MASK 0x7fc3
6054#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6055#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6056#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6057#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6058#define DREF_SSC_SOURCE_DISABLE (0<<11)
6059#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08006060#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006061#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6062#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6063#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08006064#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006065#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6066#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08006067#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006068#define DREF_SSC4_DOWNSPREAD (0<<6)
6069#define DREF_SSC4_CENTERSPREAD (1<<6)
6070#define DREF_SSC1_DISABLE (0<<1)
6071#define DREF_SSC1_ENABLE (1<<1)
6072#define DREF_SSC4_DISABLE (0)
6073#define DREF_SSC4_ENABLE (1)
6074
6075#define PCH_RAWCLK_FREQ 0xc6204
6076#define FDL_TP1_TIMER_SHIFT 12
6077#define FDL_TP1_TIMER_MASK (3<<12)
6078#define FDL_TP2_TIMER_SHIFT 10
6079#define FDL_TP2_TIMER_MASK (3<<10)
6080#define RAWCLK_FREQ_MASK 0x3ff
6081
6082#define PCH_DPLL_TMR_CFG 0xc6208
6083
6084#define PCH_SSC4_PARMS 0xc6210
6085#define PCH_SSC4_AUX_PARMS 0xc6214
6086
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006087#define PCH_DPLL_SEL 0xc7000
Daniel Vetter11887392013-06-05 13:34:09 +02006088#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
6089#define TRANS_DPLLA_SEL(pipe) 0
6090#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006091
Zhenyu Wangb9055052009-06-05 15:38:38 +08006092/* transcoder */
6093
Daniel Vetter275f01b22013-05-03 11:49:47 +02006094#define _PCH_TRANS_HTOTAL_A 0xe0000
6095#define TRANS_HTOTAL_SHIFT 16
6096#define TRANS_HACTIVE_SHIFT 0
6097#define _PCH_TRANS_HBLANK_A 0xe0004
6098#define TRANS_HBLANK_END_SHIFT 16
6099#define TRANS_HBLANK_START_SHIFT 0
6100#define _PCH_TRANS_HSYNC_A 0xe0008
6101#define TRANS_HSYNC_END_SHIFT 16
6102#define TRANS_HSYNC_START_SHIFT 0
6103#define _PCH_TRANS_VTOTAL_A 0xe000c
6104#define TRANS_VTOTAL_SHIFT 16
6105#define TRANS_VACTIVE_SHIFT 0
6106#define _PCH_TRANS_VBLANK_A 0xe0010
6107#define TRANS_VBLANK_END_SHIFT 16
6108#define TRANS_VBLANK_START_SHIFT 0
6109#define _PCH_TRANS_VSYNC_A 0xe0014
6110#define TRANS_VSYNC_END_SHIFT 16
6111#define TRANS_VSYNC_START_SHIFT 0
6112#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08006113
Daniel Vettere3b95f12013-05-03 11:49:49 +02006114#define _PCH_TRANSA_DATA_M1 0xe0030
6115#define _PCH_TRANSA_DATA_N1 0xe0034
6116#define _PCH_TRANSA_DATA_M2 0xe0038
6117#define _PCH_TRANSA_DATA_N2 0xe003c
6118#define _PCH_TRANSA_LINK_M1 0xe0040
6119#define _PCH_TRANSA_LINK_N1 0xe0044
6120#define _PCH_TRANSA_LINK_M2 0xe0048
6121#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08006122
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006123/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07006124#define _VIDEO_DIP_CTL_A 0xe0200
6125#define _VIDEO_DIP_DATA_A 0xe0208
6126#define _VIDEO_DIP_GCP_A 0xe0210
Ville Syrjälä6d674152015-05-05 17:06:20 +03006127#define GCP_COLOR_INDICATION (1 << 2)
6128#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6129#define GCP_AV_MUTE (1 << 0)
Jesse Barnesb055c8f2011-07-08 11:31:57 -07006130
6131#define _VIDEO_DIP_CTL_B 0xe1200
6132#define _VIDEO_DIP_DATA_B 0xe1208
6133#define _VIDEO_DIP_GCP_B 0xe1210
6134
6135#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6136#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6137#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6138
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006139/* Per-transcoder DIP controls (VLV) */
Ville Syrjäläb9064872013-01-24 15:29:31 +02006140#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6141#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6142#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006143
Ville Syrjäläb9064872013-01-24 15:29:31 +02006144#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6145#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6146#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006147
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006148#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6149#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6150#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6151
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006152#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006153 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
6154 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006155#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006156 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
6157 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006158#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03006159 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6160 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07006161
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006162/* Haswell DIP controls */
6163#define HSW_VIDEO_DIP_CTL_A 0x60200
6164#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6165#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
6166#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6167#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6168#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6169#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6170#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
6171#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6172#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6173#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6174#define HSW_VIDEO_DIP_GCP_A 0x60210
6175
6176#define HSW_VIDEO_DIP_CTL_B 0x61200
6177#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6178#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
6179#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6180#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6181#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6182#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6183#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
6184#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6185#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6186#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6187#define HSW_VIDEO_DIP_GCP_B 0x61210
6188
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03006189#define HSW_TVIDEO_DIP_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006190 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03006191#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006192 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +01006193#define HSW_TVIDEO_DIP_VS_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006194 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03006195#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006196 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03006197#define HSW_TVIDEO_DIP_GCP(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006198 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03006199#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006200 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03006201
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03006202#define HSW_STEREO_3D_CTL_A 0x70020
6203#define S3D_ENABLE (1<<31)
6204#define HSW_STEREO_3D_CTL_B 0x71020
6205
6206#define HSW_STEREO_3D_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006207 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03006208
Daniel Vetter275f01b22013-05-03 11:49:47 +02006209#define _PCH_TRANS_HTOTAL_B 0xe1000
6210#define _PCH_TRANS_HBLANK_B 0xe1004
6211#define _PCH_TRANS_HSYNC_B 0xe1008
6212#define _PCH_TRANS_VTOTAL_B 0xe100c
6213#define _PCH_TRANS_VBLANK_B 0xe1010
6214#define _PCH_TRANS_VSYNC_B 0xe1014
6215#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08006216
Daniel Vetter275f01b22013-05-03 11:49:47 +02006217#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6218#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6219#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6220#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6221#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6222#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6223#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
6224 _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01006225
Daniel Vettere3b95f12013-05-03 11:49:49 +02006226#define _PCH_TRANSB_DATA_M1 0xe1030
6227#define _PCH_TRANSB_DATA_N1 0xe1034
6228#define _PCH_TRANSB_DATA_M2 0xe1038
6229#define _PCH_TRANSB_DATA_N2 0xe103c
6230#define _PCH_TRANSB_LINK_M1 0xe1040
6231#define _PCH_TRANSB_LINK_N1 0xe1044
6232#define _PCH_TRANSB_LINK_M2 0xe1048
6233#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08006234
Daniel Vettere3b95f12013-05-03 11:49:49 +02006235#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6236#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6237#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6238#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6239#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6240#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6241#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6242#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006243
Daniel Vetterab9412b2013-05-03 11:49:46 +02006244#define _PCH_TRANSACONF 0xf0008
6245#define _PCH_TRANSBCONF 0xf1008
6246#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6247#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006248#define TRANS_DISABLE (0<<31)
6249#define TRANS_ENABLE (1<<31)
6250#define TRANS_STATE_MASK (1<<30)
6251#define TRANS_STATE_DISABLE (0<<30)
6252#define TRANS_STATE_ENABLE (1<<30)
6253#define TRANS_FSYNC_DELAY_HB1 (0<<27)
6254#define TRANS_FSYNC_DELAY_HB2 (1<<27)
6255#define TRANS_FSYNC_DELAY_HB3 (2<<27)
6256#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02006257#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006258#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02006259#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02006260#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006261#define TRANS_8BPC (0<<5)
6262#define TRANS_10BPC (1<<5)
6263#define TRANS_6BPC (2<<5)
6264#define TRANS_12BPC (3<<5)
6265
Daniel Vetterce401412012-10-31 22:52:30 +01006266#define _TRANSA_CHICKEN1 0xf0060
6267#define _TRANSB_CHICKEN1 0xf1060
6268#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
Ville Syrjäläd1b15892015-05-05 17:06:19 +03006269#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
Daniel Vetterce401412012-10-31 22:52:30 +01006270#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07006271#define _TRANSA_CHICKEN2 0xf0064
6272#define _TRANSB_CHICKEN2 0xf1064
6273#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03006274#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6275#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6276#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6277#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6278#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07006279
Jesse Barnes291427f2011-07-29 12:42:37 -07006280#define SOUTH_CHICKEN1 0xc2000
6281#define FDIA_PHASE_SYNC_SHIFT_OVR 19
6282#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02006283#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6284#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6285#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jesse Barnes645c62a2011-05-11 09:49:31 -07006286#define SOUTH_CHICKEN2 0xc2004
Paulo Zanonidde86e22012-12-01 12:04:25 -02006287#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6288#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6289#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07006290
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006291#define _FDI_RXA_CHICKEN 0xc200c
6292#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08006293#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6294#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006295#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006296
Jesse Barnes382b0932010-10-07 16:01:25 -07006297#define SOUTH_DSPCLK_GATE_D 0xc2020
Jesse Barnescd664072013-10-02 10:34:19 -07006298#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07006299#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07006300#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02006301#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07006302
Zhenyu Wangb9055052009-06-05 15:38:38 +08006303/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006304#define _FDI_TXA_CTL 0x60100
6305#define _FDI_TXB_CTL 0x61100
6306#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006307#define FDI_TX_DISABLE (0<<31)
6308#define FDI_TX_ENABLE (1<<31)
6309#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6310#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6311#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6312#define FDI_LINK_TRAIN_NONE (3<<28)
6313#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6314#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6315#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6316#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6317#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6318#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6319#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6320#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006321/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6322 SNB has different settings. */
6323/* SNB A-stepping */
6324#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6325#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6326#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6327#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6328/* SNB B-stepping */
6329#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6330#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6331#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6332#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6333#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006334#define FDI_DP_PORT_WIDTH_SHIFT 19
6335#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6336#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006337#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006338/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08006339#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07006340
6341/* Ivybridge has different bits for lolz */
6342#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6343#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6344#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6345#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6346
Zhenyu Wangb9055052009-06-05 15:38:38 +08006347/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07006348#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07006349#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006350#define FDI_SCRAMBLING_ENABLE (0<<7)
6351#define FDI_SCRAMBLING_DISABLE (1<<7)
6352
6353/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006354#define _FDI_RXA_CTL 0xf000c
6355#define _FDI_RXB_CTL 0xf100c
6356#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006357#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006358/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07006359#define FDI_FS_ERRC_ENABLE (1<<27)
6360#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02006361#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006362#define FDI_8BPC (0<<16)
6363#define FDI_10BPC (1<<16)
6364#define FDI_6BPC (2<<16)
6365#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00006366#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006367#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6368#define FDI_RX_PLL_ENABLE (1<<13)
6369#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6370#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6371#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6372#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6373#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01006374#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006375/* CPT */
6376#define FDI_AUTO_TRAINING (1<<10)
6377#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6378#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6379#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6380#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6381#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006382
Paulo Zanoni04945642012-11-01 21:00:59 -02006383#define _FDI_RXA_MISC 0xf0010
6384#define _FDI_RXB_MISC 0xf1010
6385#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6386#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6387#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6388#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6389#define FDI_RX_TP1_TO_TP2_48 (2<<20)
6390#define FDI_RX_TP1_TO_TP2_64 (3<<20)
6391#define FDI_RX_FDI_DELAY_90 (0x90<<0)
6392#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6393
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006394#define _FDI_RXA_TUSIZE1 0xf0030
6395#define _FDI_RXA_TUSIZE2 0xf0038
6396#define _FDI_RXB_TUSIZE1 0xf1030
6397#define _FDI_RXB_TUSIZE2 0xf1038
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006398#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6399#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006400
6401/* FDI_RX interrupt register format */
6402#define FDI_RX_INTER_LANE_ALIGN (1<<10)
6403#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6404#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6405#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6406#define FDI_RX_FS_CODE_ERR (1<<6)
6407#define FDI_RX_FE_CODE_ERR (1<<5)
6408#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6409#define FDI_RX_HDCP_LINK_FAIL (1<<3)
6410#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6411#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6412#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6413
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006414#define _FDI_RXA_IIR 0xf0014
6415#define _FDI_RXA_IMR 0xf0018
6416#define _FDI_RXB_IIR 0xf1014
6417#define _FDI_RXB_IMR 0xf1018
6418#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6419#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08006420
6421#define FDI_PLL_CTL_1 0xfe000
6422#define FDI_PLL_CTL_2 0xfe004
6423
Zhenyu Wangb9055052009-06-05 15:38:38 +08006424#define PCH_LVDS 0xe1180
6425#define LVDS_DETECTED (1 << 1)
6426
Shobhit Kumar98364372012-06-15 11:55:14 -07006427/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02006428#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6429#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6430#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Ville Syrjäläad933b52014-08-18 22:15:56 +03006431#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02006432#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6433#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07006434
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02006435#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6436#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6437#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6438#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6439#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07006440
Jesse Barnes453c5422013-03-28 09:55:41 -07006441#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
6442#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
6443#define VLV_PIPE_PP_ON_DELAYS(pipe) \
6444 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
6445#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
6446 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
6447#define VLV_PIPE_PP_DIVISOR(pipe) \
6448 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
6449
Zhenyu Wangb9055052009-06-05 15:38:38 +08006450#define PCH_PP_STATUS 0xc7200
6451#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07006452#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07006453#define PANEL_UNLOCK_MASK (0xffff << 16)
Vandana Kannanb0a08be2015-06-18 11:00:55 +05306454#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
6455#define BXT_POWER_CYCLE_DELAY_SHIFT 4
Zhenyu Wangb9055052009-06-05 15:38:38 +08006456#define EDP_FORCE_VDD (1 << 3)
6457#define EDP_BLC_ENABLE (1 << 2)
6458#define PANEL_POWER_RESET (1 << 1)
6459#define PANEL_POWER_OFF (0 << 0)
6460#define PANEL_POWER_ON (1 << 0)
6461#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07006462#define PANEL_PORT_SELECT_MASK (3 << 30)
6463#define PANEL_PORT_SELECT_LVDS (0 << 30)
6464#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07006465#define PANEL_PORT_SELECT_DPC (2 << 30)
6466#define PANEL_PORT_SELECT_DPD (3 << 30)
6467#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
6468#define PANEL_POWER_UP_DELAY_SHIFT 16
6469#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6470#define PANEL_LIGHT_ON_DELAY_SHIFT 0
6471
Zhenyu Wangb9055052009-06-05 15:38:38 +08006472#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07006473#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6474#define PANEL_POWER_DOWN_DELAY_SHIFT 16
6475#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6476#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6477
Zhenyu Wangb9055052009-06-05 15:38:38 +08006478#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07006479#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6480#define PP_REFERENCE_DIVIDER_SHIFT 8
6481#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6482#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08006483
Vandana Kannanb0a08be2015-06-18 11:00:55 +05306484/* BXT PPS changes - 2nd set of PPS registers */
6485#define _BXT_PP_STATUS2 0xc7300
6486#define _BXT_PP_CONTROL2 0xc7304
6487#define _BXT_PP_ON_DELAYS2 0xc7308
6488#define _BXT_PP_OFF_DELAYS2 0xc730c
6489
6490#define BXT_PP_STATUS(n) ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
6491#define BXT_PP_CONTROL(n) ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
6492#define BXT_PP_ON_DELAYS(n) ((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
6493#define BXT_PP_OFF_DELAYS(n) ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
6494
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006495#define PCH_DP_B 0xe4100
6496#define PCH_DPB_AUX_CH_CTL 0xe4110
6497#define PCH_DPB_AUX_CH_DATA1 0xe4114
6498#define PCH_DPB_AUX_CH_DATA2 0xe4118
6499#define PCH_DPB_AUX_CH_DATA3 0xe411c
6500#define PCH_DPB_AUX_CH_DATA4 0xe4120
6501#define PCH_DPB_AUX_CH_DATA5 0xe4124
6502
6503#define PCH_DP_C 0xe4200
6504#define PCH_DPC_AUX_CH_CTL 0xe4210
6505#define PCH_DPC_AUX_CH_DATA1 0xe4214
6506#define PCH_DPC_AUX_CH_DATA2 0xe4218
6507#define PCH_DPC_AUX_CH_DATA3 0xe421c
6508#define PCH_DPC_AUX_CH_DATA4 0xe4220
6509#define PCH_DPC_AUX_CH_DATA5 0xe4224
6510
6511#define PCH_DP_D 0xe4300
6512#define PCH_DPD_AUX_CH_CTL 0xe4310
6513#define PCH_DPD_AUX_CH_DATA1 0xe4314
6514#define PCH_DPD_AUX_CH_DATA2 0xe4318
6515#define PCH_DPD_AUX_CH_DATA3 0xe431c
6516#define PCH_DPD_AUX_CH_DATA4 0xe4320
6517#define PCH_DPD_AUX_CH_DATA5 0xe4324
6518
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006519/* CPT */
6520#define PORT_TRANS_A_SEL_CPT 0
6521#define PORT_TRANS_B_SEL_CPT (1<<29)
6522#define PORT_TRANS_C_SEL_CPT (2<<29)
6523#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07006524#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02006525#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6526#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03006527#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6528#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006529
6530#define TRANS_DP_CTL_A 0xe0300
6531#define TRANS_DP_CTL_B 0xe1300
6532#define TRANS_DP_CTL_C 0xe2300
Daniel Vetter23670b322012-11-01 09:15:30 +01006533#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006534#define TRANS_DP_OUTPUT_ENABLE (1<<31)
6535#define TRANS_DP_PORT_SEL_B (0<<29)
6536#define TRANS_DP_PORT_SEL_C (1<<29)
6537#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08006538#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006539#define TRANS_DP_PORT_SEL_MASK (3<<29)
Ville Syrjäläadc289d2015-05-05 17:17:30 +03006540#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006541#define TRANS_DP_AUDIO_ONLY (1<<26)
6542#define TRANS_DP_ENH_FRAMING (1<<18)
6543#define TRANS_DP_8BPC (0<<9)
6544#define TRANS_DP_10BPC (1<<9)
6545#define TRANS_DP_6BPC (2<<9)
6546#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08006547#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006548#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6549#define TRANS_DP_VSYNC_ACTIVE_LOW 0
6550#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6551#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01006552#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006553
6554/* SNB eDP training params */
6555/* SNB A-stepping */
6556#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6557#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6558#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6559#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6560/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08006561#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6562#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6563#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6564#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6565#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006566#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6567
Keith Packard1a2eb462011-11-16 16:26:07 -08006568/* IVB */
6569#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6570#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6571#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6572#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6573#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6574#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03006575#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08006576
6577/* legacy values */
6578#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6579#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6580#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6581#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6582#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6583
6584#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6585
Imre Deak9e72b462014-05-05 15:13:55 +03006586#define VLV_PMWGICZ 0x1300a4
6587
Zou Nan haicae58522010-11-09 17:17:32 +08006588#define FORCEWAKE 0xA18C
Jesse Barnes575155a2012-03-28 13:39:37 -07006589#define FORCEWAKE_VLV 0x1300b0
6590#define FORCEWAKE_ACK_VLV 0x1300b4
Jesse Barnesed5de392013-03-08 10:45:57 -08006591#define FORCEWAKE_MEDIA_VLV 0x1300b8
6592#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
Eugeni Dodonove7911c42012-07-02 11:51:04 -03006593#define FORCEWAKE_ACK_HSW 0x130044
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00006594#define FORCEWAKE_ACK 0x130090
Jesse Barnesd62b4892013-03-08 10:45:53 -08006595#define VLV_GTLC_WAKE_CTRL 0x130090
Imre Deak981a5ae2014-04-14 20:24:22 +03006596#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6597#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6598#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6599
Jesse Barnesd62b4892013-03-08 10:45:53 -08006600#define VLV_GTLC_PW_STATUS 0x130094
Imre Deak981a5ae2014-04-14 20:24:22 +03006601#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6602#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6603#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6604#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Keith Packard8d715f02011-11-18 20:39:01 -08006605#define FORCEWAKE_MT 0xa188 /* multi-threaded */
Zhe Wang38cff0b2014-11-04 17:07:04 +00006606#define FORCEWAKE_MEDIA_GEN9 0xa270
6607#define FORCEWAKE_RENDER_GEN9 0xa278
6608#define FORCEWAKE_BLITTER_GEN9 0xa188
6609#define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
6610#define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
6611#define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
Chris Wilsonc5836c22012-10-17 12:09:55 +01006612#define FORCEWAKE_KERNEL 0x1
6613#define FORCEWAKE_USER 0x2
Keith Packard8d715f02011-11-18 20:39:01 -08006614#define FORCEWAKE_MT_ACK 0x130040
6615#define ECOBUS 0xa180
6616#define FORCEWAKE_MT_ENABLE (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03006617#define VLV_SPAREG2H 0xA194
Chris Wilson8fd26852010-12-08 18:40:43 +00006618
Ben Widawskydd202c62012-02-09 10:15:18 +01006619#define GTFIFODBG 0x120000
Ville Syrjälä90f256b2013-11-14 01:59:59 +02006620#define GT_FIFO_SBDROPERR (1<<6)
6621#define GT_FIFO_BLOBDROPERR (1<<5)
6622#define GT_FIFO_SB_READ_ABORTERR (1<<4)
6623#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01006624#define GT_FIFO_OVFERR (1<<2)
6625#define GT_FIFO_IAWRERR (1<<1)
6626#define GT_FIFO_IARDERR (1<<0)
6627
Ville Syrjälä46520e22013-11-14 02:00:00 +02006628#define GTFIFOCTL 0x120008
6629#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01006630#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Deepak Sa04f90a2015-04-16 08:51:28 +05306631#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6632#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
Chris Wilson91355832011-03-04 19:22:40 +00006633
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006634#define HSW_IDICR 0x9008
6635#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6636#define HSW_EDRAM_PRESENT 0x120010
Damien Lespiau2db59d52015-02-03 14:25:14 +00006637#define EDRAM_ENABLED 0x1
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006638
Daniel Vetter80e829f2012-03-31 11:21:57 +02006639#define GEN6_UCGCTL1 0x9400
Ville Syrjäläe4443e42014-04-09 13:28:41 +03006640# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006641# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02006642# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006643
Eric Anholt406478d2011-11-07 16:07:04 -08006644#define GEN6_UCGCTL2 0x9404
Damien Lespiauf9fc42f2015-02-26 18:20:39 +00006645# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
Jesse Barnes0f846f82012-06-14 11:04:47 -07006646# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07006647# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08006648# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08006649# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08006650# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08006651
Imre Deak9e72b462014-05-05 15:13:55 +03006652#define GEN6_UCGCTL3 0x9408
6653
Jesse Barnese3f33d42012-06-14 11:04:50 -07006654#define GEN7_UCGCTL4 0x940c
6655#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6656
Imre Deak9e72b462014-05-05 15:13:55 +03006657#define GEN6_RCGCTL1 0x9410
6658#define GEN6_RCGCTL2 0x9414
6659#define GEN6_RSTCTL 0x9420
6660
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006661#define GEN8_UCGCTL6 0x9430
Damien Lespiau9253c2e2015-02-09 19:33:10 +00006662#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006663#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
Ben Widawsky868434c2015-03-11 10:49:32 +02006664#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006665
Imre Deak9e72b462014-05-05 15:13:55 +03006666#define GEN6_GFXPAUSE 0xA000
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006667#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00006668#define GEN6_TURBO_DISABLE (1<<31)
6669#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03006670#define HSW_FREQUENCY(x) ((x)<<24)
Akash Goelde43ae92015-03-06 11:07:14 +05306671#define GEN9_FREQUENCY(x) ((x)<<23)
Chris Wilson8fd26852010-12-08 18:40:43 +00006672#define GEN6_OFFSET(x) ((x)<<19)
6673#define GEN6_AGGRESSIVE_TURBO (0<<15)
6674#define GEN6_RC_VIDEO_FREQ 0xA00C
6675#define GEN6_RC_CONTROL 0xA090
6676#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6677#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6678#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
6679#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
6680#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08006681#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07006682#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00006683#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6684#define GEN6_RC_CTL_HW_ENABLE (1<<31)
6685#define GEN6_RP_DOWN_TIMEOUT 0xA010
6686#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006687#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08006688#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08006689#define HSW_CAGF_SHIFT 7
Akash Goelde43ae92015-03-06 11:07:14 +05306690#define GEN9_CAGF_SHIFT 23
Jesse Barnesccab5c82011-01-18 15:49:25 -08006691#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08006692#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Akash Goelde43ae92015-03-06 11:07:14 +05306693#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00006694#define GEN6_RP_CONTROL 0xA024
6695#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08006696#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6697#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6698#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6699#define GEN6_RP_MEDIA_HW_MODE (1<<9)
6700#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00006701#define GEN6_RP_MEDIA_IS_GFX (1<<8)
6702#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08006703#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6704#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6705#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01006706#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08006707#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00006708#define GEN6_RP_UP_THRESHOLD 0xA02C
6709#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08006710#define GEN6_RP_CUR_UP_EI 0xA050
6711#define GEN6_CURICONT_MASK 0xffffff
6712#define GEN6_RP_CUR_UP 0xA054
6713#define GEN6_CURBSYTAVG_MASK 0xffffff
6714#define GEN6_RP_PREV_UP 0xA058
6715#define GEN6_RP_CUR_DOWN_EI 0xA05C
6716#define GEN6_CURIAVG_MASK 0xffffff
6717#define GEN6_RP_CUR_DOWN 0xA060
6718#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00006719#define GEN6_RP_UP_EI 0xA068
6720#define GEN6_RP_DOWN_EI 0xA06C
6721#define GEN6_RP_IDLE_HYSTERSIS 0xA070
Imre Deak9e72b462014-05-05 15:13:55 +03006722#define GEN6_RPDEUHWTC 0xA080
6723#define GEN6_RPDEUC 0xA084
6724#define GEN6_RPDEUCSW 0xA088
Chris Wilson8fd26852010-12-08 18:40:43 +00006725#define GEN6_RC_STATE 0xA094
6726#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
6727#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
6728#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
6729#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
6730#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
6731#define GEN6_RC_SLEEP 0xA0B0
Imre Deak9e72b462014-05-05 15:13:55 +03006732#define GEN6_RCUBMABDTMR 0xA0B0
Chris Wilson8fd26852010-12-08 18:40:43 +00006733#define GEN6_RC1e_THRESHOLD 0xA0B4
6734#define GEN6_RC6_THRESHOLD 0xA0B8
6735#define GEN6_RC6p_THRESHOLD 0xA0BC
Imre Deak9e72b462014-05-05 15:13:55 +03006736#define VLV_RCEDATA 0xA0BC
Chris Wilson8fd26852010-12-08 18:40:43 +00006737#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006738#define GEN6_PMINTRMSK 0xA168
Deepak Sbaccd452014-05-15 20:58:09 +03006739#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
Imre Deak9e72b462014-05-05 15:13:55 +03006740#define VLV_PWRDWNUPCTL 0xA294
Zhe Wang38c23522015-01-20 12:23:04 +00006741#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
6742#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
6743#define GEN9_PG_ENABLE 0xA210
Sagar Kamblea4104c52015-04-10 14:11:29 +05306744#define GEN9_RENDER_PG_ENABLE (1<<0)
6745#define GEN9_MEDIA_PG_ENABLE (1<<1)
Chris Wilson8fd26852010-12-08 18:40:43 +00006746
Gaurav K Singha9da9bc2014-12-05 14:13:41 +05306747#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6748#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6749#define PIXEL_OVERLAP_CNT_SHIFT 30
6750
Chris Wilson8fd26852010-12-08 18:40:43 +00006751#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07006752#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00006753#define GEN6_PMIIR 0x44028
6754#define GEN6_PMIER 0x4402C
6755#define GEN6_PM_MBOX_EVENT (1<<25)
6756#define GEN6_PM_THERMAL_EVENT (1<<24)
6757#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6758#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6759#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6760#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6761#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07006762#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07006763 GEN6_PM_RP_DOWN_THRESHOLD | \
6764 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00006765
Imre Deak9e72b462014-05-05 15:13:55 +03006766#define GEN7_GT_SCRATCH_BASE 0x4F100
6767#define GEN7_GT_SCRATCH_REG_NUM 8
6768
Deepak S76c3552f2014-01-30 23:08:16 +05306769#define VLV_GTLC_SURVIVABILITY_REG 0x130098
6770#define VLV_GFX_CLK_STATUS_BIT (1<<3)
6771#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6772
Ben Widawskycce66a22012-03-27 18:59:38 -07006773#define GEN6_GT_GFX_RC6_LOCKED 0x138104
Jesse Barnes49798eb2013-09-26 17:55:57 -07006774#define VLV_COUNTER_CONTROL 0x138104
6775#define VLV_COUNT_RANGE_HIGH (1<<15)
Deepak S31685c22014-07-03 17:33:01 -04006776#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6777#define VLV_RENDER_RC0_COUNT_EN (1<<4)
Jesse Barnes49798eb2013-09-26 17:55:57 -07006778#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6779#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ben Widawskycce66a22012-03-27 18:59:38 -07006780#define GEN6_GT_GFX_RC6 0x138108
Imre Deak9cc19be2014-04-14 20:24:24 +03006781#define VLV_GT_RENDER_RC6 0x138108
6782#define VLV_GT_MEDIA_RC6 0x13810C
6783
Ben Widawskycce66a22012-03-27 18:59:38 -07006784#define GEN6_GT_GFX_RC6p 0x13810C
6785#define GEN6_GT_GFX_RC6pp 0x138110
Chris Wilson43cf3bf2015-03-18 09:48:22 +00006786#define VLV_RENDER_C0_COUNT 0x138118
6787#define VLV_MEDIA_C0_COUNT 0x13811C
Ben Widawskycce66a22012-03-27 18:59:38 -07006788
Chris Wilson8fd26852010-12-08 18:40:43 +00006789#define GEN6_PCODE_MAILBOX 0x138124
6790#define GEN6_PCODE_READY (1<<31)
Ben Widawsky31643d52012-09-26 10:34:01 -07006791#define GEN6_PCODE_WRITE_RC6VIDS 0x4
6792#define GEN6_PCODE_READ_RC6VIDS 0x5
Damien Lespiau9043ae02015-04-30 16:39:18 +01006793#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6794#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03006795#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
Damien Lespiau57520bc2015-04-30 16:39:19 +01006796#define GEN9_PCODE_READ_MEM_LATENCY 0x6
6797#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6798#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6799#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6800#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01006801#define SKL_PCODE_CDCLK_CONTROL 0x7
6802#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
6803#define SKL_CDCLK_READY_FOR_CHANGE 0x1
Damien Lespiau9043ae02015-04-30 16:39:18 +01006804#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6805#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6806#define GEN6_READ_OC_PARAMS 0xc
Paulo Zanoni515b2392013-09-10 19:36:37 -03006807#define GEN6_PCODE_READ_D_COMP 0x10
6808#define GEN6_PCODE_WRITE_D_COMP 0x11
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306809#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
Ben Widawsky2a114cc2013-11-02 21:07:47 -07006810#define DISPLAY_IPS_CONTROL 0x19
Tom O'Rourke93ee2922014-11-19 14:21:52 -08006811#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
Chris Wilson8fd26852010-12-08 18:40:43 +00006812#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07006813#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01006814#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Damien Lespiaudddab342014-11-13 17:51:50 +00006815#define GEN6_PCODE_DATA1 0x13812C
Chris Wilson8fd26852010-12-08 18:40:43 +00006816
Ben Widawsky4d855292011-12-12 19:34:16 -08006817#define GEN6_GT_CORE_STATUS 0x138060
6818#define GEN6_CORE_CPD_STATE_MASK (7<<4)
6819#define GEN6_RCn_MASK 7
6820#define GEN6_RC0 0
6821#define GEN6_RC3 2
6822#define GEN6_RC6 3
6823#define GEN6_RC7 4
6824
Jeff McGee5575f032015-02-27 10:22:32 -08006825#define CHV_POWER_SS0_SIG1 0xa720
6826#define CHV_POWER_SS1_SIG1 0xa728
6827#define CHV_SS_PG_ENABLE (1<<1)
6828#define CHV_EU08_PG_ENABLE (1<<9)
6829#define CHV_EU19_PG_ENABLE (1<<17)
6830#define CHV_EU210_PG_ENABLE (1<<25)
6831
6832#define CHV_POWER_SS0_SIG2 0xa724
6833#define CHV_POWER_SS1_SIG2 0xa72c
6834#define CHV_EU311_PG_ENABLE (1<<1)
6835
Jeff McGee1c046bc2015-04-03 18:13:18 -07006836#define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)
Jeff McGee7f992ab2015-02-13 10:27:55 -06006837#define GEN9_PGCTL_SLICE_ACK (1 << 0)
Jeff McGee1c046bc2015-04-03 18:13:18 -07006838#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
Jeff McGee7f992ab2015-02-13 10:27:55 -06006839
Jeff McGee1c046bc2015-04-03 18:13:18 -07006840#define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)
6841#define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)
Jeff McGee7f992ab2015-02-13 10:27:55 -06006842#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
6843#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
6844#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
6845#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
6846#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
6847#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
6848#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
6849#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
6850
Ben Widawskye3689192012-05-25 16:56:22 -07006851#define GEN7_MISCCPCTL (0x9424)
6852#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6853
6854/* IVYBRIDGE DPF */
6855#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07006856#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07006857#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6858#define GEN7_PARITY_ERROR_VALID (1<<13)
6859#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6860#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6861#define GEN7_PARITY_ERROR_ROW(reg) \
6862 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6863#define GEN7_PARITY_ERROR_BANK(reg) \
6864 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6865#define GEN7_PARITY_ERROR_SUBBANK(reg) \
6866 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6867#define GEN7_L3CDERRST1_ENABLE (1<<7)
6868
Ben Widawskyb9524a12012-05-25 16:56:24 -07006869#define GEN7_L3LOG_BASE 0xB070
Ben Widawsky35a85ac2013-09-19 11:13:41 -07006870#define HSW_L3LOG_BASE_SLICE1 0xB270
Ben Widawskyb9524a12012-05-25 16:56:24 -07006871#define GEN7_L3LOG_SIZE 0x80
6872
Jesse Barnes12f33822012-10-25 12:15:45 -07006873#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6874#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6875#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07006876#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Nick Hoath983b4b92015-04-10 13:12:25 +01006877#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
Jesse Barnes12f33822012-10-25 12:15:45 -07006878#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6879
Damien Lespiau3ca5da42014-03-26 18:18:01 +00006880#define GEN9_HALF_SLICE_CHICKEN5 0xe188
6881#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
Damien Lespiaue2db7072015-02-09 19:33:21 +00006882#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00006883
Kenneth Graunkec8966e12014-02-26 23:59:30 -08006884#define GEN8_ROW_CHICKEN 0xe4f0
6885#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08006886#define STALL_DOP_GATING_DISABLE (1<<5)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08006887
Jesse Barnes8ab43972012-10-25 12:15:42 -07006888#define GEN7_ROW_CHICKEN2 0xe4f4
6889#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
6890#define DOP_CLOCK_GATING_DISABLE (1<<0)
6891
Francisco Jerezf3fc4882013-10-02 15:53:16 -07006892#define HSW_ROW_CHICKEN3 0xe49c
6893#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
6894
Ben Widawskyfd392b62013-11-04 22:52:39 -08006895#define HALF_SLICE_CHICKEN3 0xe184
Kenneth Graunke94411592014-12-31 16:23:00 -08006896#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
Ben Widawskyfd392b62013-11-04 22:52:39 -08006897#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Nick Hoath84241712015-02-05 10:47:20 +00006898#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
Ben Widawskybf663472013-11-02 21:07:57 -07006899#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08006900
Nick Hoathcac23df2015-02-05 10:47:22 +00006901#define GEN9_HALF_SLICE_CHICKEN7 0xe194
6902#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
6903
Jani Nikulac46f1112014-10-27 16:26:52 +02006904/* Audio */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006905#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
Jani Nikulac46f1112014-10-27 16:26:52 +02006906#define INTEL_AUDIO_DEVCL 0x808629FB
6907#define INTEL_AUDIO_DEVBLC 0x80862801
6908#define INTEL_AUDIO_DEVCTG 0x80862802
Wu Fengguange0dac652011-09-05 14:25:34 +08006909
6910#define G4X_AUD_CNTL_ST 0x620B4
Jani Nikulac46f1112014-10-27 16:26:52 +02006911#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
6912#define G4X_ELDV_DEVCTG (1 << 14)
6913#define G4X_ELD_ADDR_MASK (0xf << 5)
6914#define G4X_ELD_ACK (1 << 4)
Wu Fengguange0dac652011-09-05 14:25:34 +08006915#define G4X_HDMIW_HDMIEDID 0x6210C
6916
Jani Nikulac46f1112014-10-27 16:26:52 +02006917#define _IBX_HDMIW_HDMIEDID_A 0xE2050
6918#define _IBX_HDMIW_HDMIEDID_B 0xE2150
Wang Xingchao9b138a82012-08-09 16:52:18 +08006919#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006920 _IBX_HDMIW_HDMIEDID_A, \
6921 _IBX_HDMIW_HDMIEDID_B)
6922#define _IBX_AUD_CNTL_ST_A 0xE20B4
6923#define _IBX_AUD_CNTL_ST_B 0xE21B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08006924#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006925 _IBX_AUD_CNTL_ST_A, \
6926 _IBX_AUD_CNTL_ST_B)
6927#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
6928#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
6929#define IBX_ELD_ACK (1 << 4)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006930#define IBX_AUD_CNTL_ST2 0xE20C0
Jani Nikula82910ac2014-10-27 16:26:59 +02006931#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
6932#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
Wu Fengguange0dac652011-09-05 14:25:34 +08006933
Jani Nikulac46f1112014-10-27 16:26:52 +02006934#define _CPT_HDMIW_HDMIEDID_A 0xE5050
6935#define _CPT_HDMIW_HDMIEDID_B 0xE5150
Wang Xingchao9b138a82012-08-09 16:52:18 +08006936#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006937 _CPT_HDMIW_HDMIEDID_A, \
6938 _CPT_HDMIW_HDMIEDID_B)
6939#define _CPT_AUD_CNTL_ST_A 0xE50B4
6940#define _CPT_AUD_CNTL_ST_B 0xE51B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08006941#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006942 _CPT_AUD_CNTL_ST_A, \
6943 _CPT_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006944#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08006945
Jani Nikulac46f1112014-10-27 16:26:52 +02006946#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
6947#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006948#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006949 _VLV_HDMIW_HDMIEDID_A, \
6950 _VLV_HDMIW_HDMIEDID_B)
6951#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
6952#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006953#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006954 _VLV_AUD_CNTL_ST_A, \
6955 _VLV_AUD_CNTL_ST_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006956#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
6957
Eric Anholtae662d32012-01-03 09:23:29 -08006958/* These are the 4 32-bit write offset registers for each stream
6959 * output buffer. It determines the offset from the
6960 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6961 */
6962#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
6963
Jani Nikulac46f1112014-10-27 16:26:52 +02006964#define _IBX_AUD_CONFIG_A 0xe2000
6965#define _IBX_AUD_CONFIG_B 0xe2100
Wang Xingchao9b138a82012-08-09 16:52:18 +08006966#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006967 _IBX_AUD_CONFIG_A, \
6968 _IBX_AUD_CONFIG_B)
6969#define _CPT_AUD_CONFIG_A 0xe5000
6970#define _CPT_AUD_CONFIG_B 0xe5100
Wang Xingchao9b138a82012-08-09 16:52:18 +08006971#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006972 _CPT_AUD_CONFIG_A, \
6973 _CPT_AUD_CONFIG_B)
6974#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
6975#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006976#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006977 _VLV_AUD_CONFIG_A, \
6978 _VLV_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006979
Wu Fengguangb6daa022012-01-06 14:41:31 -06006980#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
6981#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
6982#define AUD_CONFIG_UPPER_N_SHIFT 20
Jani Nikulac46f1112014-10-27 16:26:52 +02006983#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006984#define AUD_CONFIG_LOWER_N_SHIFT 4
Jani Nikulac46f1112014-10-27 16:26:52 +02006985#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006986#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03006987#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
6988#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
6989#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
6990#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
6991#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
6992#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
6993#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
6994#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
6995#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
6996#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
6997#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006998#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
6999
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007000/* HSW Audio */
Jani Nikulac46f1112014-10-27 16:26:52 +02007001#define _HSW_AUD_CONFIG_A 0x65000
7002#define _HSW_AUD_CONFIG_B 0x65100
7003#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
7004 _HSW_AUD_CONFIG_A, \
7005 _HSW_AUD_CONFIG_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007006
Jani Nikulac46f1112014-10-27 16:26:52 +02007007#define _HSW_AUD_MISC_CTRL_A 0x65010
7008#define _HSW_AUD_MISC_CTRL_B 0x65110
7009#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
7010 _HSW_AUD_MISC_CTRL_A, \
7011 _HSW_AUD_MISC_CTRL_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007012
Jani Nikulac46f1112014-10-27 16:26:52 +02007013#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7014#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7015#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
7016 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
7017 _HSW_AUD_DIP_ELD_CTRL_ST_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007018
7019/* Audio Digital Converter */
Jani Nikulac46f1112014-10-27 16:26:52 +02007020#define _HSW_AUD_DIG_CNVT_1 0x65080
7021#define _HSW_AUD_DIG_CNVT_2 0x65180
7022#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
7023 _HSW_AUD_DIG_CNVT_1, \
7024 _HSW_AUD_DIG_CNVT_2)
7025#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007026
Jani Nikulac46f1112014-10-27 16:26:52 +02007027#define _HSW_AUD_EDID_DATA_A 0x65050
7028#define _HSW_AUD_EDID_DATA_B 0x65150
7029#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
7030 _HSW_AUD_EDID_DATA_A, \
7031 _HSW_AUD_EDID_DATA_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007032
Jani Nikulac46f1112014-10-27 16:26:52 +02007033#define HSW_AUD_PIPE_CONV_CFG 0x6507c
7034#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
Jani Nikula82910ac2014-10-27 16:26:59 +02007035#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7036#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7037#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7038#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08007039
Lu, Han632f3ab2015-05-05 09:05:47 +08007040#define HSW_AUD_CHICKENBIT 0x65f10
7041#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7042
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007043/* HSW Power Wells */
Paulo Zanonifa42e232013-01-25 16:59:11 -02007044#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
7045#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
7046#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
7047#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03007048#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7049#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007050#define HSW_PWR_WELL_CTL5 0x45410
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007051#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7052#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007053#define HSW_PWR_WELL_FORCE_ON (1<<19)
7054#define HSW_PWR_WELL_CTL6 0x45414
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03007055
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00007056/* SKL Fuse Status */
7057#define SKL_FUSE_STATUS 0x42000
7058#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7059#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7060#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7061#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7062
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007063/* Per-pipe DDI Function Control */
Paulo Zanoniad80a812012-10-24 16:06:19 -02007064#define TRANS_DDI_FUNC_CTL_A 0x60400
7065#define TRANS_DDI_FUNC_CTL_B 0x61400
7066#define TRANS_DDI_FUNC_CTL_C 0x62400
7067#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007068#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
7069
Paulo Zanoniad80a812012-10-24 16:06:19 -02007070#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007071/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02007072#define TRANS_DDI_PORT_MASK (7<<28)
Daniel Vetter26804af2014-06-25 22:01:55 +03007073#define TRANS_DDI_PORT_SHIFT 28
Paulo Zanoniad80a812012-10-24 16:06:19 -02007074#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7075#define TRANS_DDI_PORT_NONE (0<<28)
7076#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7077#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7078#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7079#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7080#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7081#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7082#define TRANS_DDI_BPC_MASK (7<<20)
7083#define TRANS_DDI_BPC_8 (0<<20)
7084#define TRANS_DDI_BPC_10 (1<<20)
7085#define TRANS_DDI_BPC_6 (2<<20)
7086#define TRANS_DDI_BPC_12 (3<<20)
7087#define TRANS_DDI_PVSYNC (1<<17)
7088#define TRANS_DDI_PHSYNC (1<<16)
7089#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7090#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7091#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7092#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7093#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
Dave Airlie01b887c2014-05-02 11:17:41 +10007094#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
Paulo Zanoniad80a812012-10-24 16:06:19 -02007095#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03007096
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007097/* DisplayPort Transport Control */
7098#define DP_TP_CTL_A 0x64040
7099#define DP_TP_CTL_B 0x64140
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007100#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
7101#define DP_TP_CTL_ENABLE (1<<31)
7102#define DP_TP_CTL_MODE_SST (0<<27)
7103#define DP_TP_CTL_MODE_MST (1<<27)
Dave Airlie01b887c2014-05-02 11:17:41 +10007104#define DP_TP_CTL_FORCE_ACT (1<<25)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007105#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007106#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007107#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7108#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7109#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03007110#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7111#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007112#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03007113#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03007114
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03007115/* DisplayPort Transport Status */
7116#define DP_TP_STATUS_A 0x64044
7117#define DP_TP_STATUS_B 0x64144
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007118#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
Dave Airlie01b887c2014-05-02 11:17:41 +10007119#define DP_TP_STATUS_IDLE_DONE (1<<25)
7120#define DP_TP_STATUS_ACT_SENT (1<<24)
7121#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7122#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7123#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7124#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7125#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03007126
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03007127/* DDI Buffer Control */
7128#define DDI_BUF_CTL_A 0x64000
7129#define DDI_BUF_CTL_B 0x64100
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007130#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
7131#define DDI_BUF_CTL_ENABLE (1<<31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05307132#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007133#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00007134#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007135#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02007136#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02007137#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03007138#define DDI_INIT_DISPLAY_DETECTED (1<<0)
7139
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03007140/* DDI Buffer Translations */
7141#define DDI_BUF_TRANS_A 0x64E00
7142#define DDI_BUF_TRANS_B 0x64E60
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007143#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03007144
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03007145/* Sideband Interface (SBI) is programmed indirectly, via
7146 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7147 * which contains the payload */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007148#define SBI_ADDR 0xC6000
7149#define SBI_DATA 0xC6004
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03007150#define SBI_CTL_STAT 0xC6008
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02007151#define SBI_CTL_DEST_ICLK (0x0<<16)
7152#define SBI_CTL_DEST_MPHY (0x1<<16)
7153#define SBI_CTL_OP_IORD (0x2<<8)
7154#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03007155#define SBI_CTL_OP_CRRD (0x6<<8)
7156#define SBI_CTL_OP_CRWR (0x7<<8)
7157#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007158#define SBI_RESPONSE_SUCCESS (0x0<<1)
7159#define SBI_BUSY (0x1<<0)
7160#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007161
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007162/* SBI offsets */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007163#define SBI_SSCDIVINTPHASE6 0x0600
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007164#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
7165#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
7166#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
7167#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007168#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007169#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007170#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007171#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02007172#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007173#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007174#define SBI_SSCAUXDIV6 0x0610
7175#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007176#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007177#define SBI_GEN0 0x1f00
7178#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03007179
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007180/* LPT PIXCLK_GATE */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007181#define PIXCLK_GATE 0xC6020
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03007182#define PIXCLK_GATE_UNGATE (1<<0)
7183#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03007184
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007185/* SPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007186#define SPLL_CTL 0x46020
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007187#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01007188#define SPLL_PLL_SSC (1<<28)
7189#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08007190#define SPLL_PLL_LCPLL (3<<28)
7191#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007192#define SPLL_PLL_FREQ_810MHz (0<<26)
7193#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08007194#define SPLL_PLL_FREQ_2700MHz (2<<26)
7195#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03007196
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03007197/* WRPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007198#define WRPLL_CTL1 0x46040
7199#define WRPLL_CTL2 0x46060
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007200#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007201#define WRPLL_PLL_ENABLE (1<<31)
Daniel Vetter114fe482014-06-25 22:01:48 +03007202#define WRPLL_PLL_SSC (1<<28)
7203#define WRPLL_PLL_NON_SSC (2<<28)
7204#define WRPLL_PLL_LCPLL (3<<28)
7205#define WRPLL_PLL_REF_MASK (3<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03007206/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007207#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08007208#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007209#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08007210#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7211#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007212#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08007213#define WRPLL_DIVIDER_FB_SHIFT 16
7214#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03007215
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007216/* Port clock selection */
7217#define PORT_CLK_SEL_A 0x46100
7218#define PORT_CLK_SEL_B 0x46104
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007219#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007220#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7221#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7222#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007223#define PORT_CLK_SEL_SPLL (3<<29)
Daniel Vetter716c2e52014-06-25 22:02:02 +03007224#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007225#define PORT_CLK_SEL_WRPLL1 (4<<29)
7226#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007227#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08007228#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007229
Paulo Zanonibb523fc2012-10-23 18:29:56 -02007230/* Transcoder clock selection */
7231#define TRANS_CLK_SEL_A 0x46140
7232#define TRANS_CLK_SEL_B 0x46144
7233#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
7234/* For each transcoder, we need to select the corresponding port clock */
7235#define TRANS_CLK_SEL_DISABLED (0x0<<29)
7236#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03007237
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007238#define TRANSA_MSA_MISC 0x60410
7239#define TRANSB_MSA_MISC 0x61410
7240#define TRANSC_MSA_MISC 0x62410
7241#define TRANS_EDP_MSA_MISC 0x6f410
7242#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
7243
Paulo Zanonic9809792012-10-23 18:30:00 -02007244#define TRANS_MSA_SYNC_CLK (1<<0)
7245#define TRANS_MSA_6_BPC (0<<5)
7246#define TRANS_MSA_8_BPC (1<<5)
7247#define TRANS_MSA_10_BPC (2<<5)
7248#define TRANS_MSA_12_BPC (3<<5)
7249#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03007250
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007251/* LCPLL Control */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007252#define LCPLL_CTL 0x130040
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007253#define LCPLL_PLL_DISABLE (1<<31)
7254#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03007255#define LCPLL_CLK_FREQ_MASK (3<<26)
7256#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07007257#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7258#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7259#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007260#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03007261#define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007262#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007263#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03007264#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007265#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7266
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007267/*
7268 * SKL Clocks
7269 */
7270
7271/* CDCLK_CTL */
7272#define CDCLK_CTL 0x46000
7273#define CDCLK_FREQ_SEL_MASK (3<<26)
7274#define CDCLK_FREQ_450_432 (0<<26)
7275#define CDCLK_FREQ_540 (1<<26)
7276#define CDCLK_FREQ_337_308 (2<<26)
7277#define CDCLK_FREQ_675_617 (3<<26)
7278#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7279
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307280#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7281#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7282#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7283#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7284#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
7285#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7286
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007287/* LCPLL_CTL */
7288#define LCPLL1_CTL 0x46010
7289#define LCPLL2_CTL 0x46014
7290#define LCPLL_PLL_ENABLE (1<<31)
7291
7292/* DPLL control1 */
7293#define DPLL_CTRL1 0x6C058
7294#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7295#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
Damien Lespiau71cd8422015-04-30 16:39:17 +01007296#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7297#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7298#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007299#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
Damien Lespiau71cd8422015-04-30 16:39:17 +01007300#define DPLL_CTRL1_LINK_RATE_2700 0
7301#define DPLL_CTRL1_LINK_RATE_1350 1
7302#define DPLL_CTRL1_LINK_RATE_810 2
7303#define DPLL_CTRL1_LINK_RATE_1620 3
7304#define DPLL_CTRL1_LINK_RATE_1080 4
7305#define DPLL_CTRL1_LINK_RATE_2160 5
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007306
7307/* DPLL control2 */
7308#define DPLL_CTRL2 0x6C05C
7309#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
7310#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
Satheeshakrishna M540e7322014-11-13 14:55:16 +00007311#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
Satheeshakrishna M326ac39b2014-11-13 14:55:13 +00007312#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
7313#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7314
7315/* DPLL Status */
7316#define DPLL_STATUS 0x6C060
7317#define DPLL_LOCK(id) (1<<((id)*8))
7318
7319/* DPLL cfg */
7320#define DPLL1_CFGCR1 0x6C040
7321#define DPLL2_CFGCR1 0x6C048
7322#define DPLL3_CFGCR1 0x6C050
7323#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7324#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7325#define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
7326#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7327
7328#define DPLL1_CFGCR2 0x6C044
7329#define DPLL2_CFGCR2 0x6C04C
7330#define DPLL3_CFGCR2 0x6C054
7331#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7332#define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
7333#define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
7334#define DPLL_CFGCR2_KDIV_MASK (3<<5)
7335#define DPLL_CFGCR2_KDIV(x) (x<<5)
7336#define DPLL_CFGCR2_KDIV_5 (0<<5)
7337#define DPLL_CFGCR2_KDIV_2 (1<<5)
7338#define DPLL_CFGCR2_KDIV_3 (2<<5)
7339#define DPLL_CFGCR2_KDIV_1 (3<<5)
7340#define DPLL_CFGCR2_PDIV_MASK (7<<2)
7341#define DPLL_CFGCR2_PDIV(x) (x<<2)
7342#define DPLL_CFGCR2_PDIV_1 (0<<2)
7343#define DPLL_CFGCR2_PDIV_2 (1<<2)
7344#define DPLL_CFGCR2_PDIV_3 (2<<2)
7345#define DPLL_CFGCR2_PDIV_7 (4<<2)
7346#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7347
Satheeshakrishna M540e7322014-11-13 14:55:16 +00007348#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
7349#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
7350
Vandana Kannanf8437dd12014-11-24 13:37:39 +05307351/* BXT display engine PLL */
7352#define BXT_DE_PLL_CTL 0x6d000
7353#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7354#define BXT_DE_PLL_RATIO_MASK 0xff
7355
7356#define BXT_DE_PLL_ENABLE 0x46070
7357#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7358#define BXT_DE_PLL_LOCK (1 << 30)
7359
A.Sunil Kamath664326f2014-11-24 13:37:44 +05307360/* GEN9 DC */
7361#define DC_STATE_EN 0x45504
7362#define DC_STATE_EN_UPTO_DC5 (1<<0)
7363#define DC_STATE_EN_DC9 (1<<3)
A.Sunil Kamath6b457d32015-04-16 14:22:09 +05307364#define DC_STATE_EN_UPTO_DC6 (2<<0)
7365#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7366
7367#define DC_STATE_DEBUG 0x45520
7368#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7369
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007370/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7371 * since on HSW we can't write to it using I915_WRITE. */
7372#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7373#define D_COMP_BDW 0x138144
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007374#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7375#define D_COMP_COMP_FORCE (1<<8)
7376#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03007377
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03007378/* Pipe WM_LINETIME - watermark line time */
7379#define PIPE_WM_LINETIME_A 0x45270
7380#define PIPE_WM_LINETIME_B 0x45274
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007381#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
7382 PIPE_WM_LINETIME_B)
7383#define PIPE_WM_LINETIME_MASK (0x1ff)
7384#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03007385#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007386#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03007387
7388/* SFUSE_STRAP */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03007389#define SFUSE_STRAP 0xc2014
Damien Lespiau658ac4c2014-02-10 17:19:45 +00007390#define SFUSE_STRAP_FUSE_LOCK (1<<13)
7391#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03007392#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7393#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7394#define SFUSE_STRAP_DDID_DETECTED (1<<0)
7395
Paulo Zanoni801bcff2013-05-31 10:08:35 -03007396#define WM_MISC 0x45260
7397#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7398
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03007399#define WM_DBG 0x45280
7400#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7401#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7402#define WM_DBG_DISALLOW_SPRITE (1<<2)
7403
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007404/* pipe CSC */
7405#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7406#define _PIPE_A_CSC_COEFF_BY 0x49014
7407#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7408#define _PIPE_A_CSC_COEFF_BU 0x4901c
7409#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7410#define _PIPE_A_CSC_COEFF_BV 0x49024
7411#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03007412#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7413#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7414#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007415#define _PIPE_A_CSC_PREOFF_HI 0x49030
7416#define _PIPE_A_CSC_PREOFF_ME 0x49034
7417#define _PIPE_A_CSC_PREOFF_LO 0x49038
7418#define _PIPE_A_CSC_POSTOFF_HI 0x49040
7419#define _PIPE_A_CSC_POSTOFF_ME 0x49044
7420#define _PIPE_A_CSC_POSTOFF_LO 0x49048
7421
7422#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7423#define _PIPE_B_CSC_COEFF_BY 0x49114
7424#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7425#define _PIPE_B_CSC_COEFF_BU 0x4911c
7426#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7427#define _PIPE_B_CSC_COEFF_BV 0x49124
7428#define _PIPE_B_CSC_MODE 0x49128
7429#define _PIPE_B_CSC_PREOFF_HI 0x49130
7430#define _PIPE_B_CSC_PREOFF_ME 0x49134
7431#define _PIPE_B_CSC_PREOFF_LO 0x49138
7432#define _PIPE_B_CSC_POSTOFF_HI 0x49140
7433#define _PIPE_B_CSC_POSTOFF_ME 0x49144
7434#define _PIPE_B_CSC_POSTOFF_LO 0x49148
7435
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007436#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7437#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7438#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7439#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7440#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7441#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7442#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7443#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7444#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7445#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7446#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7447#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7448#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7449
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007450/* MIPI DSI registers */
7451
7452#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
Jani Nikula3230bf12013-08-27 15:12:16 +03007453
7454#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007455#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7456#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7457#define DPI_ENABLE (1 << 31) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007458#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7459#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
Gaurav K Singh369602d2014-12-05 14:09:28 +05307460#define DUAL_LINK_MODE_SHIFT 26
Jani Nikula3230bf12013-08-27 15:12:16 +03007461#define DUAL_LINK_MODE_MASK (1 << 26)
7462#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7463#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007464#define DITHERING_ENABLE (1 << 25) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007465#define FLOPPED_HSTX (1 << 23)
7466#define DE_INVERT (1 << 19) /* XXX */
7467#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7468#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7469#define AFE_LATCHOUT (1 << 17)
7470#define LP_OUTPUT_HOLD (1 << 16)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007471#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7472#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7473#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7474#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
Jani Nikula3230bf12013-08-27 15:12:16 +03007475#define CSB_SHIFT 9
7476#define CSB_MASK (3 << 9)
7477#define CSB_20MHZ (0 << 9)
7478#define CSB_10MHZ (1 << 9)
7479#define CSB_40MHZ (2 << 9)
7480#define BANDGAP_MASK (1 << 8)
7481#define BANDGAP_PNW_CIRCUIT (0 << 8)
7482#define BANDGAP_LNC_CIRCUIT (1 << 8)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007483#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7484#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
7485#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
7486#define TEARING_EFFECT_SHIFT 2 /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03007487#define TEARING_EFFECT_MASK (3 << 2)
7488#define TEARING_EFFECT_OFF (0 << 2)
7489#define TEARING_EFFECT_DSI (1 << 2)
7490#define TEARING_EFFECT_GPIO (2 << 2)
7491#define LANE_CONFIGURATION_SHIFT 0
7492#define LANE_CONFIGURATION_MASK (3 << 0)
7493#define LANE_CONFIGURATION_4LANE (0 << 0)
7494#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
7495#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
7496
7497#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007498#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
7499#define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \
7500 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007501#define TEARING_EFFECT_DELAY_SHIFT 0
7502#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
7503
7504/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307505#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +03007506
7507/* MIPI DSI Controller and D-PHY registers */
7508
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307509#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007510#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
7511#define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \
7512 _MIPIC_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +03007513#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
7514#define ULPS_STATE_MASK (3 << 1)
7515#define ULPS_STATE_ENTER (2 << 1)
7516#define ULPS_STATE_EXIT (1 << 1)
7517#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
7518#define DEVICE_READY (1 << 0)
7519
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307520#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007521#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
7522#define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \
7523 _MIPIC_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307524#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007525#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
7526#define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \
7527 _MIPIC_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +03007528#define TEARING_EFFECT (1 << 31)
7529#define SPL_PKT_SENT_INTERRUPT (1 << 30)
7530#define GEN_READ_DATA_AVAIL (1 << 29)
7531#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
7532#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
7533#define RX_PROT_VIOLATION (1 << 26)
7534#define RX_INVALID_TX_LENGTH (1 << 25)
7535#define ACK_WITH_NO_ERROR (1 << 24)
7536#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
7537#define LP_RX_TIMEOUT (1 << 22)
7538#define HS_TX_TIMEOUT (1 << 21)
7539#define DPI_FIFO_UNDERRUN (1 << 20)
7540#define LOW_CONTENTION (1 << 19)
7541#define HIGH_CONTENTION (1 << 18)
7542#define TXDSI_VC_ID_INVALID (1 << 17)
7543#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
7544#define TXCHECKSUM_ERROR (1 << 15)
7545#define TXECC_MULTIBIT_ERROR (1 << 14)
7546#define TXECC_SINGLE_BIT_ERROR (1 << 13)
7547#define TXFALSE_CONTROL_ERROR (1 << 12)
7548#define RXDSI_VC_ID_INVALID (1 << 11)
7549#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
7550#define RXCHECKSUM_ERROR (1 << 9)
7551#define RXECC_MULTIBIT_ERROR (1 << 8)
7552#define RXECC_SINGLE_BIT_ERROR (1 << 7)
7553#define RXFALSE_CONTROL_ERROR (1 << 6)
7554#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
7555#define RX_LP_TX_SYNC_ERROR (1 << 4)
7556#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
7557#define RXEOT_SYNC_ERROR (1 << 2)
7558#define RXSOT_SYNC_ERROR (1 << 1)
7559#define RXSOT_ERROR (1 << 0)
7560
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307561#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007562#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7563#define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
7564 _MIPIC_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +03007565#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
7566#define CMD_MODE_NOT_SUPPORTED (0 << 13)
7567#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
7568#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
7569#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
7570#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
7571#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
7572#define VID_MODE_FORMAT_MASK (0xf << 7)
7573#define VID_MODE_NOT_SUPPORTED (0 << 7)
7574#define VID_MODE_FORMAT_RGB565 (1 << 7)
7575#define VID_MODE_FORMAT_RGB666 (2 << 7)
7576#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
7577#define VID_MODE_FORMAT_RGB888 (4 << 7)
7578#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
7579#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
7580#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
7581#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
7582#define DATA_LANES_PRG_REG_SHIFT 0
7583#define DATA_LANES_PRG_REG_MASK (7 << 0)
7584
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307585#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007586#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7587#define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
7588 _MIPIC_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007589#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
7590
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307591#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007592#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7593#define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
7594 _MIPIC_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007595#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
7596
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307597#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007598#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7599#define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \
7600 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007601#define TURN_AROUND_TIMEOUT_MASK 0x3f
7602
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307603#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007604#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7605#define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \
7606 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +03007607#define DEVICE_RESET_TIMER_MASK 0xffff
7608
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307609#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007610#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7611#define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
7612 _MIPIC_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +03007613#define VERTICAL_ADDRESS_SHIFT 16
7614#define VERTICAL_ADDRESS_MASK (0xffff << 16)
7615#define HORIZONTAL_ADDRESS_SHIFT 0
7616#define HORIZONTAL_ADDRESS_MASK 0xffff
7617
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307618#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007619#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7620#define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \
7621 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007622#define DBI_FIFO_EMPTY_HALF (0 << 0)
7623#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
7624#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
7625
7626/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307627#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007628#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7629#define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7630 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007631
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307632#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007633#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7634#define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \
7635 _MIPIC_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007636
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307637#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007638#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7639#define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \
7640 _MIPIC_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007641
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307642#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007643#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7644#define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \
7645 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007646
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307647#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007648#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7649#define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7650 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007651
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307652#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007653#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7654#define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \
7655 _MIPIC_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007656
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307657#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007658#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7659#define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \
7660 _MIPIC_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007661
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307662#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007663#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7664#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \
7665 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307666
Jani Nikula3230bf12013-08-27 15:12:16 +03007667/* regs above are bits 15:0 */
7668
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307669#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007670#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7671#define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
7672 _MIPIC_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007673#define DPI_LP_MODE (1 << 6)
7674#define BACKLIGHT_OFF (1 << 5)
7675#define BACKLIGHT_ON (1 << 4)
7676#define COLOR_MODE_OFF (1 << 3)
7677#define COLOR_MODE_ON (1 << 2)
7678#define TURN_ON (1 << 1)
7679#define SHUTDOWN (1 << 0)
7680
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307681#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007682#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7683#define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \
7684 _MIPIC_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007685#define COMMAND_BYTE_SHIFT 0
7686#define COMMAND_BYTE_MASK (0x3f << 0)
7687
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307688#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007689#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7690#define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \
7691 _MIPIC_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007692#define MASTER_INIT_TIMER_SHIFT 0
7693#define MASTER_INIT_TIMER_MASK (0xffff << 0)
7694
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307695#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007696#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7697#define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \
7698 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007699#define MAX_RETURN_PKT_SIZE_SHIFT 0
7700#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
7701
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307702#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007703#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7704#define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \
7705 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007706#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
7707#define DISABLE_VIDEO_BTA (1 << 3)
7708#define IP_TG_CONFIG (1 << 2)
7709#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
7710#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
7711#define VIDEO_MODE_BURST (3 << 0)
7712
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307713#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007714#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7715#define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
7716 _MIPIC_EOT_DISABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007717#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
7718#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
7719#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
7720#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
7721#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7722#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
7723#define CLOCKSTOP (1 << 1)
7724#define EOT_DISABLE (1 << 0)
7725
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307726#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007727#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7728#define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
7729 _MIPIC_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +03007730#define LP_BYTECLK_SHIFT 0
7731#define LP_BYTECLK_MASK (0xffff << 0)
7732
7733/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307734#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007735#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7736#define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
7737 _MIPIC_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007738
7739/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307740#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007741#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7742#define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
7743 _MIPIC_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007744
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307745#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007746#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7747#define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
7748 _MIPIC_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307749#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007750#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7751#define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
7752 _MIPIC_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007753#define LONG_PACKET_WORD_COUNT_SHIFT 8
7754#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
7755#define SHORT_PACKET_PARAM_SHIFT 8
7756#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
7757#define VIRTUAL_CHANNEL_SHIFT 6
7758#define VIRTUAL_CHANNEL_MASK (3 << 6)
7759#define DATA_TYPE_SHIFT 0
7760#define DATA_TYPE_MASK (3f << 0)
7761/* data type values, see include/video/mipi_display.h */
7762
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307763#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007764#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
7765#define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
7766 _MIPIC_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007767#define DPI_FIFO_EMPTY (1 << 28)
7768#define DBI_FIFO_EMPTY (1 << 27)
7769#define LP_CTRL_FIFO_EMPTY (1 << 26)
7770#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
7771#define LP_CTRL_FIFO_FULL (1 << 24)
7772#define HS_CTRL_FIFO_EMPTY (1 << 18)
7773#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
7774#define HS_CTRL_FIFO_FULL (1 << 16)
7775#define LP_DATA_FIFO_EMPTY (1 << 10)
7776#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
7777#define LP_DATA_FIFO_FULL (1 << 8)
7778#define HS_DATA_FIFO_EMPTY (1 << 2)
7779#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
7780#define HS_DATA_FIFO_FULL (1 << 0)
7781
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307782#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007783#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
7784#define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \
7785 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007786#define DBI_HS_LP_MODE_MASK (1 << 0)
7787#define DBI_LP_MODE (1 << 0)
7788#define DBI_HS_MODE (0 << 0)
7789
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307790#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007791#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
7792#define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
7793 _MIPIC_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +03007794#define EXIT_ZERO_COUNT_SHIFT 24
7795#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
7796#define TRAIL_COUNT_SHIFT 16
7797#define TRAIL_COUNT_MASK (0x1f << 16)
7798#define CLK_ZERO_COUNT_SHIFT 8
7799#define CLK_ZERO_COUNT_MASK (0xff << 8)
7800#define PREPARE_COUNT_SHIFT 0
7801#define PREPARE_COUNT_MASK (0x3f << 0)
7802
7803/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307804#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007805#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
7806#define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
7807 _MIPIC_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007808
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307809#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7810 + 0xb088)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007811#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307812 + 0xb888)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007813#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \
7814 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007815#define LP_HS_SSW_CNT_SHIFT 16
7816#define LP_HS_SSW_CNT_MASK (0xffff << 16)
7817#define HS_LP_PWR_SW_CNT_SHIFT 0
7818#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
7819
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307820#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007821#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
7822#define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \
7823 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007824#define STOP_STATE_STALL_COUNTER_SHIFT 0
7825#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
7826
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307827#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007828#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
7829#define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \
7830 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307831#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007832#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7833#define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
7834 _MIPIC_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +03007835#define RX_CONTENTION_DETECTED (1 << 0)
7836
7837/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307838#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +03007839#define DBI_TYPEC_ENABLE (1 << 31)
7840#define DBI_TYPEC_WIP (1 << 30)
7841#define DBI_TYPEC_OPTION_SHIFT 28
7842#define DBI_TYPEC_OPTION_MASK (3 << 28)
7843#define DBI_TYPEC_FREQ_SHIFT 24
7844#define DBI_TYPEC_FREQ_MASK (0xf << 24)
7845#define DBI_TYPEC_OVERRIDE (1 << 8)
7846#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
7847#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
7848
7849
7850/* MIPI adapter registers */
7851
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307852#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007853#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7854#define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \
7855 _MIPIC_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007856#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
7857#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
7858#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
7859#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
7860#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
7861#define READ_REQUEST_PRIORITY_SHIFT 3
7862#define READ_REQUEST_PRIORITY_MASK (3 << 3)
7863#define READ_REQUEST_PRIORITY_LOW (0 << 3)
7864#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
7865#define RGB_FLIP_TO_BGR (1 << 2)
7866
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307867#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007868#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7869#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
7870 _MIPIC_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03007871#define DATA_MEM_ADDRESS_SHIFT 5
7872#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
7873#define DATA_VALID (1 << 0)
7874
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307875#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007876#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7877#define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
7878 _MIPIC_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03007879#define DATA_LENGTH_SHIFT 0
7880#define DATA_LENGTH_MASK (0xfffff << 0)
7881
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307882#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007883#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7884#define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \
7885 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03007886#define COMMAND_MEM_ADDRESS_SHIFT 5
7887#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
7888#define AUTO_PWG_ENABLE (1 << 2)
7889#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
7890#define COMMAND_VALID (1 << 0)
7891
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307892#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007893#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7894#define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
7895 _MIPIC_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03007896#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
7897#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
7898
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307899#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007900#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7901#define MIPI_READ_DATA_RETURN(port, n) \
7902 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
Shashank Sharmaa2560a62014-06-02 18:07:48 +05307903 + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +03007904
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307905#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007906#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7907#define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \
7908 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +03007909#define READ_DATA_VALID(n) (1 << (n))
7910
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007911/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00007912#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7913#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007914
Peter Antoine3bbaba02015-07-10 20:13:11 +03007915/* MOCS (Memory Object Control State) registers */
7916#define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */
7917
7918#define GEN9_GFX_MOCS_0 0xc800 /* Graphics MOCS base register*/
7919#define GEN9_MFX0_MOCS_0 0xc900 /* Media 0 MOCS base register*/
7920#define GEN9_MFX1_MOCS_0 0xca00 /* Media 1 MOCS base register*/
7921#define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/
7922#define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
7923
Jesse Barnes585fb112008-07-29 11:54:06 -07007924#endif /* _I915_REG_H_ */