| commit | c9224faa59c3071ecfa2d4b24592f4eb61e57069 | [log] [tgz] |
|---|---|---|
| author | Brad Volkin <bradley.d.volkin@intel.com> | Tue Jun 17 14:10:34 2014 -0700 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Wed Jun 18 00:48:35 2014 +0200 |
| tree | bc0e9d8d9155ac38644f461f1d8945f8a781e1ee | |
| parent | beff0d0f6121f6a2a818a050a1e4d91706b3f190 [diff] |
drm/i915: Add some L3 registers to the parser whitelist Beignet needs these in order to program the L3 cache config for OpenCL workloads, particularly when using SLM. Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>