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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / c5d9ae265b105d9a67575fb67bd4650a6fc08e25 / . / arch / arm / boot / dts / imx23.dtsi
blob: 7f4c602454a5fb0721a34833f773c98ea0d1b155 [file] [log] [blame]
Fabio Estevam241f76b2018-05-07 15:23:40 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]4
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]5#include "imx23-pinfunc.h"
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]6
7/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]8 #address-cells = <1>;
9 #size-cells = <1>;
10
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]11 interrupt-parent = <&icoll>;
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]12 /*
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]16 */
17 chosen {};
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]18
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]23 serial0 = &auart0;
24 serial1 = &auart1;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]25 spi0 = &ssp0;
26 spi1 = &ssp1;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]27 usbphy0 = &usbphy0;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]28 };
29
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]30 cpus {
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]31 #address-cells = <1>;
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]32 #size-cells = <0>;
33
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]34 cpu@0 {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]35 compatible = "arm,arm926ej-s";
36 device_type = "cpu";
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]37 reg = <0>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]38 };
39 };
40
41 apb@80000000 {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 reg = <0x80000000 0x80000>;
46 ranges;
47
48 apbh@80000000 {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 reg = <0x80000000 0x40000>;
53 ranges;
54
55 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]56 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x80000000 0x2000>;
60 };
61
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]62 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]63 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]64 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]65 interrupts = <0 14 20 0
66 13 13 13 13>;
67 interrupt-names = "empty", "ssp0", "ssp1", "empty",
68 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
69 #dma-cells = <1>;
70 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]71 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]72 };
73
74 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]75 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]76 status = "disabled";
77 };
78
Anson Huang175808882020-07-30 21:04:06 +0800[diff] [blame]79 nand-controller@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]80 compatible = "fsl,imx23-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]84 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]85 interrupts = <56>;
86 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]87 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]88 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]89 dmas = <&dma_apbh 4>;
90 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]91 status = "disabled";
92 };
93
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]94 ssp0: spi@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]95 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]96 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]97 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]98 dmas = <&dma_apbh 1>;
99 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]100 status = "disabled";
101 };
102
103 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]104 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]105 status = "disabled";
106 };
107
108 pinctrl@80018000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]111 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]112 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]113
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]114 gpio0: gpio@0 {
115 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]116 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]117 interrupts = <16>;
118 gpio-controller;
119 #gpio-cells = <2>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 };
123
124 gpio1: gpio@1 {
125 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]126 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]127 interrupts = <17>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 };
133
134 gpio2: gpio@2 {
135 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]136 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]137 interrupts = <18>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]144 duart_pins_a: duart@0 {
145 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]146 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]147 MX23_PAD_PWM0__DUART_RX
148 MX23_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]149 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]150 fsl,drive-strength = <MXS_DRIVE_4mA>;
151 fsl,voltage = <MXS_VOLTAGE_HIGH>;
152 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]153 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]154
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]155 auart0_pins_a: auart0@0 {
156 reg = <0>;
157 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]158 MX23_PAD_AUART1_RX__AUART1_RX
159 MX23_PAD_AUART1_TX__AUART1_TX
160 MX23_PAD_AUART1_CTS__AUART1_CTS
161 MX23_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]162 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]163 fsl,drive-strength = <MXS_DRIVE_4mA>;
164 fsl,voltage = <MXS_VOLTAGE_HIGH>;
165 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]166 };
167
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]168 auart0_2pins_a: auart0-2pins@0 {
169 reg = <0>;
170 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]171 MX23_PAD_I2C_SCL__AUART1_TX
172 MX23_PAD_I2C_SDA__AUART1_RX
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]173 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]174 fsl,drive-strength = <MXS_DRIVE_4mA>;
175 fsl,voltage = <MXS_VOLTAGE_HIGH>;
176 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]177 };
178
Marek Vasutd33c7312016-06-09 21:43:11 +0200[diff] [blame]179 auart1_2pins_a: auart1-2pins@0 {
180 reg = <0>;
181 fsl,pinmux-ids = <
182 MX23_PAD_GPMI_D14__AUART2_RX
183 MX23_PAD_GPMI_D15__AUART2_TX
184 >;
185 fsl,drive-strength = <MXS_DRIVE_4mA>;
186 fsl,voltage = <MXS_VOLTAGE_HIGH>;
187 fsl,pull-up = <MXS_PULL_DISABLE>;
188 };
189
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]190 gpmi_pins_a: gpmi-nand@0 {
191 reg = <0>;
192 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]193 MX23_PAD_GPMI_D00__GPMI_D00
194 MX23_PAD_GPMI_D01__GPMI_D01
195 MX23_PAD_GPMI_D02__GPMI_D02
196 MX23_PAD_GPMI_D03__GPMI_D03
197 MX23_PAD_GPMI_D04__GPMI_D04
198 MX23_PAD_GPMI_D05__GPMI_D05
199 MX23_PAD_GPMI_D06__GPMI_D06
200 MX23_PAD_GPMI_D07__GPMI_D07
201 MX23_PAD_GPMI_CLE__GPMI_CLE
202 MX23_PAD_GPMI_ALE__GPMI_ALE
203 MX23_PAD_GPMI_RDY0__GPMI_RDY0
204 MX23_PAD_GPMI_RDY1__GPMI_RDY1
205 MX23_PAD_GPMI_WPN__GPMI_WPN
206 MX23_PAD_GPMI_WRN__GPMI_WRN
207 MX23_PAD_GPMI_RDN__GPMI_RDN
208 MX23_PAD_GPMI_CE1N__GPMI_CE1N
209 MX23_PAD_GPMI_CE0N__GPMI_CE0N
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]210 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]211 fsl,drive-strength = <MXS_DRIVE_4mA>;
212 fsl,voltage = <MXS_VOLTAGE_HIGH>;
213 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]214 };
215
Fabio Estevam74aeda32017-12-27 12:04:34 -0200[diff] [blame]216 gpmi_pins_fixup: gpmi-pins-fixup@0 {
217 reg = <0>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]218 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]219 MX23_PAD_GPMI_WPN__GPMI_WPN
220 MX23_PAD_GPMI_WRN__GPMI_WRN
221 MX23_PAD_GPMI_RDN__GPMI_RDN
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]222 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]223 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]224 };
225
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]226 mmc0_4bit_pins_a: mmc0-4bit@0 {
227 reg = <0>;
228 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]229 MX23_PAD_SSP1_DATA0__SSP1_DATA0
230 MX23_PAD_SSP1_DATA1__SSP1_DATA1
231 MX23_PAD_SSP1_DATA2__SSP1_DATA2
232 MX23_PAD_SSP1_DATA3__SSP1_DATA3
233 MX23_PAD_SSP1_CMD__SSP1_CMD
234 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]235 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]236 fsl,drive-strength = <MXS_DRIVE_8mA>;
237 fsl,voltage = <MXS_VOLTAGE_HIGH>;
238 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]239 };
240
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]241 mmc0_8bit_pins_a: mmc0-8bit@0 {
242 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]243 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]244 MX23_PAD_SSP1_DATA0__SSP1_DATA0
245 MX23_PAD_SSP1_DATA1__SSP1_DATA1
246 MX23_PAD_SSP1_DATA2__SSP1_DATA2
247 MX23_PAD_SSP1_DATA3__SSP1_DATA3
248 MX23_PAD_GPMI_D08__SSP1_DATA4
249 MX23_PAD_GPMI_D09__SSP1_DATA5
250 MX23_PAD_GPMI_D10__SSP1_DATA6
251 MX23_PAD_GPMI_D11__SSP1_DATA7
252 MX23_PAD_SSP1_CMD__SSP1_CMD
253 MX23_PAD_SSP1_DETECT__SSP1_DETECT
254 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]255 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]256 fsl,drive-strength = <MXS_DRIVE_8mA>;
257 fsl,voltage = <MXS_VOLTAGE_HIGH>;
258 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]259 };
260
Fabio Estevam74aeda32017-12-27 12:04:34 -0200[diff] [blame]261 mmc0_pins_fixup: mmc0-pins-fixup@0 {
262 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]263 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]264 MX23_PAD_SSP1_DETECT__SSP1_DETECT
265 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]266 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]267 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]268 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]269
Michael Heimpolde4fdac52020-03-08 23:21:44 +0100[diff] [blame]270 mmc0_sck_cfg: mmc0-sck-cfg@0 {
271 reg = <0>;
272 fsl,pinmux-ids = <
273 MX23_PAD_SSP1_SCK__SSP1_SCK
274 >;
275 fsl,pull-up = <MXS_PULL_DISABLE>;
276 };
277
Marek Vasut1ebcb162016-06-09 21:43:10 +0200[diff] [blame]278 mmc1_4bit_pins_a: mmc1-4bit@0 {
279 reg = <0>;
280 fsl,pinmux-ids = <
281 MX23_PAD_GPMI_D00__SSP2_DATA0
282 MX23_PAD_GPMI_D01__SSP2_DATA1
283 MX23_PAD_GPMI_D02__SSP2_DATA2
284 MX23_PAD_GPMI_D03__SSP2_DATA3
285 MX23_PAD_GPMI_RDY1__SSP2_CMD
286 MX23_PAD_GPMI_WRN__SSP2_SCK
287 >;
288 fsl,drive-strength = <MXS_DRIVE_8mA>;
289 fsl,voltage = <MXS_VOLTAGE_HIGH>;
290 fsl,pull-up = <MXS_PULL_ENABLE>;
291 };
292
293 mmc1_8bit_pins_a: mmc1-8bit@0 {
294 reg = <0>;
295 fsl,pinmux-ids = <
296 MX23_PAD_GPMI_D00__SSP2_DATA0
297 MX23_PAD_GPMI_D01__SSP2_DATA1
298 MX23_PAD_GPMI_D02__SSP2_DATA2
299 MX23_PAD_GPMI_D03__SSP2_DATA3
300 MX23_PAD_GPMI_D04__SSP2_DATA4
301 MX23_PAD_GPMI_D05__SSP2_DATA5
302 MX23_PAD_GPMI_D06__SSP2_DATA6
303 MX23_PAD_GPMI_D07__SSP2_DATA7
304 MX23_PAD_GPMI_RDY1__SSP2_CMD
305 MX23_PAD_GPMI_WRN__SSP2_SCK
306 >;
307 fsl,drive-strength = <MXS_DRIVE_8mA>;
308 fsl,voltage = <MXS_VOLTAGE_HIGH>;
309 fsl,pull-up = <MXS_PULL_ENABLE>;
310 };
311
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]312 pwm2_pins_a: pwm2@0 {
313 reg = <0>;
314 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]315 MX23_PAD_PWM2__PWM2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]316 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]317 fsl,drive-strength = <MXS_DRIVE_4mA>;
318 fsl,voltage = <MXS_VOLTAGE_HIGH>;
319 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]320 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]321
322 lcdif_24bit_pins_a: lcdif-24bit@0 {
323 reg = <0>;
324 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]325 MX23_PAD_LCD_D00__LCD_D00
326 MX23_PAD_LCD_D01__LCD_D01
327 MX23_PAD_LCD_D02__LCD_D02
328 MX23_PAD_LCD_D03__LCD_D03
329 MX23_PAD_LCD_D04__LCD_D04
330 MX23_PAD_LCD_D05__LCD_D05
331 MX23_PAD_LCD_D06__LCD_D06
332 MX23_PAD_LCD_D07__LCD_D07
333 MX23_PAD_LCD_D08__LCD_D08
334 MX23_PAD_LCD_D09__LCD_D09
335 MX23_PAD_LCD_D10__LCD_D10
336 MX23_PAD_LCD_D11__LCD_D11
337 MX23_PAD_LCD_D12__LCD_D12
338 MX23_PAD_LCD_D13__LCD_D13
339 MX23_PAD_LCD_D14__LCD_D14
340 MX23_PAD_LCD_D15__LCD_D15
341 MX23_PAD_LCD_D16__LCD_D16
342 MX23_PAD_LCD_D17__LCD_D17
343 MX23_PAD_GPMI_D08__LCD_D18
344 MX23_PAD_GPMI_D09__LCD_D19
345 MX23_PAD_GPMI_D10__LCD_D20
346 MX23_PAD_GPMI_D11__LCD_D21
347 MX23_PAD_GPMI_D12__LCD_D22
348 MX23_PAD_GPMI_D13__LCD_D23
349 MX23_PAD_LCD_DOTCK__LCD_DOTCK
350 MX23_PAD_LCD_ENABLE__LCD_ENABLE
351 MX23_PAD_LCD_HSYNC__LCD_HSYNC
352 MX23_PAD_LCD_VSYNC__LCD_VSYNC
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]353 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]357 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]358
359 spi2_pins_a: spi2@0 {
360 reg = <0>;
361 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]362 MX23_PAD_GPMI_WRN__SSP2_SCK
363 MX23_PAD_GPMI_RDY1__SSP2_CMD
364 MX23_PAD_GPMI_D00__SSP2_DATA0
365 MX23_PAD_GPMI_D03__SSP2_DATA3
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]366 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]367 fsl,drive-strength = <MXS_DRIVE_8mA>;
368 fsl,voltage = <MXS_VOLTAGE_HIGH>;
369 fsl,pull-up = <MXS_PULL_ENABLE>;
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]370 };
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]371
372 i2c_pins_a: i2c@0 {
373 reg = <0>;
374 fsl,pinmux-ids = <
375 MX23_PAD_I2C_SCL__I2C_SCL
376 MX23_PAD_I2C_SDA__I2C_SDA
377 >;
378 fsl,drive-strength = <MXS_DRIVE_8mA>;
379 fsl,voltage = <MXS_VOLTAGE_HIGH>;
380 fsl,pull-up = <MXS_PULL_ENABLE>;
381 };
382
383 i2c_pins_b: i2c@1 {
384 reg = <1>;
385 fsl,pinmux-ids = <
386 MX23_PAD_LCD_ENABLE__I2C_SCL
387 MX23_PAD_LCD_HSYNC__I2C_SDA
388 >;
389 fsl,drive-strength = <MXS_DRIVE_8mA>;
390 fsl,voltage = <MXS_VOLTAGE_HIGH>;
391 fsl,pull-up = <MXS_PULL_ENABLE>;
392 };
393
394 i2c_pins_c: i2c@2 {
395 reg = <2>;
396 fsl,pinmux-ids = <
397 MX23_PAD_SSP1_DATA1__I2C_SCL
398 MX23_PAD_SSP1_DATA2__I2C_SDA
399 >;
400 fsl,drive-strength = <MXS_DRIVE_8mA>;
401 fsl,voltage = <MXS_VOLTAGE_HIGH>;
402 fsl,pull-up = <MXS_PULL_ENABLE>;
403 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]404 };
405
406 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800[diff] [blame]407 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]408 reg = <0x8001c000 2000>;
409 status = "disabled";
410 };
411
412 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]413 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]414 status = "disabled";
415 };
416
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]417 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]418 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]419 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]420 interrupts = <7 5 9 26
421 19 0 25 23
422 60 58 9 0
423 0 0 0 0>;
424 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
425 "saif0", "empty", "auart0-rx", "auart0-tx",
426 "auart1-rx", "auart1-tx", "saif1", "empty",
427 "empty", "empty", "empty", "empty";
428 #dma-cells = <1>;
429 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]430 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]431 };
432
Horia Geantă6cef60f2020-03-05 15:59:08 +0200[diff] [blame]433 dcp: crypto@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]434 compatible = "fsl,imx23-dcp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]435 reg = <0x80028000 0x2000>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]436 interrupts = <53 54>;
437 status = "okay";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]438 };
439
440 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]441 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]442 status = "disabled";
443 };
444
Anson Huang17a2deb2020-05-28 11:12:49 +0800[diff] [blame]445 efuse@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]446 compatible = "fsl,imx23-ocotp", "fsl,ocotp";
447 #address-cells = <1>;
448 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]449 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]450 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]451 };
452
453 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]454 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]455 status = "disabled";
456 };
457
458 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]459 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]460 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]461 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]462 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]463 status = "disabled";
464 };
465
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]466 ssp1: spi@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]467 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]468 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]469 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]470 dmas = <&dma_apbh 2>;
471 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]472 status = "disabled";
473 };
474
475 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]476 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]477 status = "disabled";
478 };
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]479 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]480
481 apbx@80040000 {
482 compatible = "simple-bus";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 reg = <0x80040000 0x40000>;
486 ranges;
487
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]488 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]489 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]490 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]491 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]492 };
493
494 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]495 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]496 dmas = <&dma_apbx 4>;
497 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]498 status = "disabled";
499 };
500
501 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]502 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]503 status = "disabled";
504 };
505
506 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]507 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]508 dmas = <&dma_apbx 10>;
509 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]510 status = "disabled";
511 };
512
513 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]514 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]515 dmas = <&dma_apbx 1>;
516 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]517 status = "disabled";
518 };
519
520 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]521 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]522 dmas = <&dma_apbx 0>;
523 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]524 status = "disabled";
525 };
526
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]527 lradc: lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]528 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]529 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]530 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]531 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]532 clocks = <&clks 26>;
Stefan Wahrene8e94ed2015-06-02 22:03:28 +0000[diff] [blame]533 #io-channel-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]534 };
535
536 spdif@80054000 {
537 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]538 dmas = <&dma_apbx 2>;
539 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]540 status = "disabled";
541 };
542
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]543 i2c: i2c@80058000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "fsl,imx23-i2c";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]547 reg = <0x80058000 0x2000>;
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]548 interrupts = <27>;
549 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]550 dmas = <&dma_apbx 3>;
551 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]552 status = "disabled";
553 };
554
555 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]556 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]557 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]558 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]559 };
560
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]561 pwm: pwm@80064000 {
562 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]563 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]564 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]565 #pwm-cells = <2>;
566 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]567 status = "disabled";
568 };
569
570 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]571 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]572 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]573 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]574 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]575 };
576
577 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]578 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]579 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]580 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]581 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]582 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
583 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]584 status = "disabled";
585 };
586
587 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]588 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]589 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]590 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]591 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]592 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
593 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]594 status = "disabled";
595 };
596
597 duart: serial@80070000 {
598 compatible = "arm,pl011", "arm,primecell";
599 reg = <0x80070000 0x2000>;
600 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]601 clocks = <&clks 32>, <&clks 16>;
602 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]603 status = "disabled";
604 };
605
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]606 usbphy0: usbphy@8007c000 {
607 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]608 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]609 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]610 status = "disabled";
611 };
612 };
613 };
614
615 ahb@80080000 {
616 compatible = "simple-bus";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 reg = <0x80080000 0x80000>;
620 ranges;
621
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]622 usb0: usb@80080000 {
623 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]624 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]625 interrupts = <11>;
626 fsl,usbphy = <&usbphy0>;
627 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]628 status = "disabled";
629 };
630 };
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]631
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]632 iio-hwmon {
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]633 compatible = "iio-hwmon";
634 io-channels = <&lradc 8>;
635 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]636};