blob: 8d37aa7430a3303a38c08a6c62243a0fb2c9bc57 [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080021 serial0 = &auart0;
22 serial1 = &auart1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080023 };
24
Shawn Guo2954ff32012-05-04 21:33:42 +080025 cpus {
26 cpu@0 {
27 compatible = "arm,arm926ejs";
28 };
29 };
30
31 apb@80000000 {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x80000000 0x80000>;
36 ranges;
37
38 apbh@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x40000>;
43 ranges;
44
45 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080046 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080047 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x80000000 0x2000>;
50 };
51
52 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080053 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030054 reg = <0x80004000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +080055 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080056 };
57
58 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030059 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080060 status = "disabled";
61 };
62
Marek Vasuta217c462012-06-09 01:21:55 +020063 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080064 compatible = "fsl,imx23-gpmi-nand";
65 #address-cells = <1>;
66 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030067 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080068 reg-names = "gpmi-nand", "bch";
69 interrupts = <13>, <56>;
70 interrupt-names = "gpmi-dma", "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080071 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +080072 clock-names = "gpmi_io";
Huang Shijieb9f25f82012-07-03 12:58:13 +080073 fsl,gpmi-dma-channel = <4>;
Shawn Guo2954ff32012-05-04 21:33:42 +080074 status = "disabled";
75 };
76
77 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030078 reg = <0x80010000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +080079 interrupts = <15 14>;
Shawn Guo53f94432012-08-22 21:36:30 +080080 clocks = <&clks 33>;
Shawn Guobe1ce302012-05-06 16:29:36 +080081 fsl,ssp-dma-channel = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +080082 status = "disabled";
83 };
84
85 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030086 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080087 status = "disabled";
88 };
89
90 pinctrl@80018000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +080093 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -030094 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080095
Shawn Guoce4c6f92012-05-04 14:32:35 +080096 gpio0: gpio@0 {
97 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
98 interrupts = <16>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpio1: gpio@1 {
106 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
107 interrupts = <17>;
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 };
113
114 gpio2: gpio@2 {
115 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
116 interrupts = <18>;
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 };
122
Shawn Guo2954ff32012-05-04 21:33:42 +0800123 duart_pins_a: duart@0 {
124 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800125 fsl,pinmux-ids = <
126 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
127 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
128 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800129 fsl,drive-strength = <0>;
130 fsl,voltage = <1>;
131 fsl,pull-up = <0>;
132 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800133
Shawn Guoa4508392012-06-28 11:45:00 +0800134 auart0_pins_a: auart0@0 {
135 reg = <0>;
136 fsl,pinmux-ids = <
137 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
138 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
139 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
140 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
141 >;
142 fsl,drive-strength = <0>;
143 fsl,voltage = <1>;
144 fsl,pull-up = <0>;
145 };
146
Fabio Estevam98916a22012-07-30 16:33:44 -0300147 auart0_2pins_a: auart0-2pins@0 {
148 reg = <0>;
149 fsl,pinmux-ids = <
150 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
151 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
152 >;
153 fsl,drive-strength = <0>;
154 fsl,voltage = <1>;
155 fsl,pull-up = <0>;
156 };
157
Huang Shijieb9f25f82012-07-03 12:58:13 +0800158 gpmi_pins_a: gpmi-nand@0 {
159 reg = <0>;
160 fsl,pinmux-ids = <
161 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
162 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
163 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
164 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
165 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
166 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
167 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
168 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
169 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
170 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
171 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
172 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
173 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
174 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
175 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
176 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
177 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
178 >;
179 fsl,drive-strength = <0>;
180 fsl,voltage = <1>;
181 fsl,pull-up = <0>;
182 };
183
184 gpmi_pins_fixup: gpmi-pins-fixup {
185 fsl,pinmux-ids = <
186 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
187 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
188 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
189 >;
190 fsl,drive-strength = <2>;
191 };
192
Shawn Guo72beaba2012-06-28 11:44:59 +0800193 mmc0_4bit_pins_a: mmc0-4bit@0 {
194 reg = <0>;
195 fsl,pinmux-ids = <
196 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
197 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
198 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
199 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
200 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
Shawn Guo72beaba2012-06-28 11:44:59 +0800201 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
202 >;
203 fsl,drive-strength = <1>;
204 fsl,voltage = <1>;
205 fsl,pull-up = <1>;
206 };
207
Shawn Guobe1ce302012-05-06 16:29:36 +0800208 mmc0_8bit_pins_a: mmc0-8bit@0 {
209 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800210 fsl,pinmux-ids = <
211 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
212 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
213 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
214 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
215 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
216 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
217 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
218 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
219 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
220 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
221 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
222 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800223 fsl,drive-strength = <1>;
224 fsl,voltage = <1>;
225 fsl,pull-up = <1>;
226 };
227
228 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800229 fsl,pinmux-ids = <
230 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
231 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
232 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800233 fsl,pull-up = <0>;
234 };
Shawn Guo52f71762012-06-28 11:45:06 +0800235
236 pwm2_pins_a: pwm2@0 {
237 reg = <0>;
238 fsl,pinmux-ids = <
239 0x11c0 /* MX23_PAD_PWM2__PWM2 */
240 >;
241 fsl,drive-strength = <0>;
242 fsl,voltage = <1>;
243 fsl,pull-up = <0>;
244 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800245
246 lcdif_24bit_pins_a: lcdif-24bit@0 {
247 reg = <0>;
248 fsl,pinmux-ids = <
249 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
250 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
251 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
252 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
253 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
254 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
255 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
256 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
257 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
258 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
259 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
260 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
261 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
262 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
263 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
264 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
265 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
266 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
267 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
268 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
269 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
270 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
271 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
272 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
273 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
274 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
275 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
276 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
277 >;
278 fsl,drive-strength = <0>;
279 fsl,voltage = <1>;
280 fsl,pull-up = <0>;
281 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500282
283 spi2_pins_a: spi2@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
287 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
288 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
289 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
290 >;
291 fsl,drive-strength = <1>;
292 fsl,voltage = <1>;
293 fsl,pull-up = <1>;
294 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800295 };
296
297 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800298 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800299 reg = <0x8001c000 2000>;
300 status = "disabled";
301 };
302
303 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300304 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800305 status = "disabled";
306 };
307
308 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800309 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300310 reg = <0x80024000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800311 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800312 };
313
314 dcp@80028000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300315 reg = <0x80028000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800316 status = "disabled";
317 };
318
319 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300320 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800321 status = "disabled";
322 };
323
324 ocotp@8002c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300325 reg = <0x8002c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800326 status = "disabled";
327 };
328
329 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300330 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800331 status = "disabled";
332 };
333
334 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800335 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800336 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800337 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800338 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800339 status = "disabled";
340 };
341
342 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300343 reg = <0x80034000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800344 interrupts = <2 20>;
Shawn Guo53f94432012-08-22 21:36:30 +0800345 clocks = <&clks 33>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800346 fsl,ssp-dma-channel = <2>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800347 status = "disabled";
348 };
349
350 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300351 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800352 status = "disabled";
353 };
354 };
355
356 apbx@80040000 {
357 compatible = "simple-bus";
358 #address-cells = <1>;
359 #size-cells = <1>;
360 reg = <0x80040000 0x40000>;
361 ranges;
362
Shawn Guo53f94432012-08-22 21:36:30 +0800363 clks: clkctrl@80040000 {
364 compatible = "fsl,imx23-clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300365 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800366 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800367 };
368
369 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300370 reg = <0x80042000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800371 status = "disabled";
372 };
373
374 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300375 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800376 status = "disabled";
377 };
378
379 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300380 reg = <0x80046000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800381 status = "disabled";
382 };
383
384 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300385 reg = <0x80048000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800386 status = "disabled";
387 };
388
389 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300390 reg = <0x8004c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800391 status = "disabled";
392 };
393
394 lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000395 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300396 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000397 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800398 status = "disabled";
399 };
400
401 spdif@80054000 {
402 reg = <0x80054000 2000>;
403 status = "disabled";
404 };
405
406 i2c@80058000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300407 reg = <0x80058000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800408 status = "disabled";
409 };
410
411 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800412 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300413 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800414 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800415 };
416
Shawn Guo52f71762012-06-28 11:45:06 +0800417 pwm: pwm@80064000 {
418 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300419 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800420 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800421 #pwm-cells = <2>;
422 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800423 status = "disabled";
424 };
425
426 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800427 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300428 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800429 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800430 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800431 };
432
433 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800434 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800435 reg = <0x8006c000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800436 interrupts = <24 25 23>;
Shawn Guo53f94432012-08-22 21:36:30 +0800437 clocks = <&clks 32>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800438 status = "disabled";
439 };
440
441 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800442 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800443 reg = <0x8006e000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800444 interrupts = <59 60 58>;
Shawn Guo53f94432012-08-22 21:36:30 +0800445 clocks = <&clks 32>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800446 status = "disabled";
447 };
448
449 duart: serial@80070000 {
450 compatible = "arm,pl011", "arm,primecell";
451 reg = <0x80070000 0x2000>;
452 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800453 clocks = <&clks 32>, <&clks 16>;
454 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800455 status = "disabled";
456 };
457
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300458 usbphy0: usbphy@8007c000 {
459 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800460 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300461 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800462 status = "disabled";
463 };
464 };
465 };
466
467 ahb@80080000 {
468 compatible = "simple-bus";
469 #address-cells = <1>;
470 #size-cells = <1>;
471 reg = <0x80080000 0x80000>;
472 ranges;
473
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300474 usb0: usb@80080000 {
475 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300476 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300477 interrupts = <11>;
478 fsl,usbphy = <&usbphy0>;
479 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800480 status = "disabled";
481 };
482 };
483};