blob: 587ceef81e45a5eeb6cb6da0ff5f643f29892669 [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080021 serial0 = &auart0;
22 serial1 = &auart1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080023 };
24
Shawn Guo2954ff32012-05-04 21:33:42 +080025 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +010026 #address-cells = <0>;
27 #size-cells = <0>;
28
29 cpu {
30 compatible = "arm,arm926ej-s";
31 device_type = "cpu";
Shawn Guo2954ff32012-05-04 21:33:42 +080032 };
33 };
34
35 apb@80000000 {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x80000000 0x80000>;
40 ranges;
41
42 apbh@80000000 {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 reg = <0x80000000 0x40000>;
47 ranges;
48
49 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +080050 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +080051 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x80000000 0x2000>;
54 };
55
Shawn Guof30fb032013-02-25 21:56:56 +080056 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080057 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -030058 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +080059 interrupts = <0 14 20 0
60 13 13 13 13>;
61 interrupt-names = "empty", "ssp0", "ssp1", "empty",
62 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
63 #dma-cells = <1>;
64 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +080065 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +080066 };
67
68 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030069 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080070 status = "disabled";
71 };
72
Marek Vasuta217c462012-06-09 01:21:55 +020073 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +080074 compatible = "fsl,imx23-gpmi-nand";
75 #address-cells = <1>;
76 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -030077 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +080078 reg-names = "gpmi-nand", "bch";
79 interrupts = <13>, <56>;
80 interrupt-names = "gpmi-dma", "bch";
Shawn Guo53f94432012-08-22 21:36:30 +080081 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +080082 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +080083 dmas = <&dma_apbh 4>;
84 dma-names = "rx-tx";
Huang Shijieb9f25f82012-07-03 12:58:13 +080085 fsl,gpmi-dma-channel = <4>;
Shawn Guo2954ff32012-05-04 21:33:42 +080086 status = "disabled";
87 };
88
89 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -030090 reg = <0x80010000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +080091 interrupts = <15 14>;
Shawn Guo53f94432012-08-22 21:36:30 +080092 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +080093 dmas = <&dma_apbh 1>;
94 dma-names = "rx-tx";
Shawn Guobe1ce302012-05-06 16:29:36 +080095 fsl,ssp-dma-channel = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +080096 status = "disabled";
97 };
98
99 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300100 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800101 status = "disabled";
102 };
103
104 pinctrl@80018000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800107 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300108 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800109
Shawn Guoce4c6f92012-05-04 14:32:35 +0800110 gpio0: gpio@0 {
111 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
112 interrupts = <16>;
113 gpio-controller;
114 #gpio-cells = <2>;
115 interrupt-controller;
116 #interrupt-cells = <2>;
117 };
118
119 gpio1: gpio@1 {
120 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
121 interrupts = <17>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 };
127
128 gpio2: gpio@2 {
129 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
130 interrupts = <18>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 };
136
Shawn Guo2954ff32012-05-04 21:33:42 +0800137 duart_pins_a: duart@0 {
138 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800139 fsl,pinmux-ids = <
140 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
141 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
142 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800143 fsl,drive-strength = <0>;
144 fsl,voltage = <1>;
145 fsl,pull-up = <0>;
146 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800147
Shawn Guoa4508392012-06-28 11:45:00 +0800148 auart0_pins_a: auart0@0 {
149 reg = <0>;
150 fsl,pinmux-ids = <
151 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
152 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
153 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
154 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
155 >;
156 fsl,drive-strength = <0>;
157 fsl,voltage = <1>;
158 fsl,pull-up = <0>;
159 };
160
Fabio Estevam98916a22012-07-30 16:33:44 -0300161 auart0_2pins_a: auart0-2pins@0 {
162 reg = <0>;
163 fsl,pinmux-ids = <
164 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
165 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
166 >;
167 fsl,drive-strength = <0>;
168 fsl,voltage = <1>;
169 fsl,pull-up = <0>;
170 };
171
Huang Shijieb9f25f82012-07-03 12:58:13 +0800172 gpmi_pins_a: gpmi-nand@0 {
173 reg = <0>;
174 fsl,pinmux-ids = <
175 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
176 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
177 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
178 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
179 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
180 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
181 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
182 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
183 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
184 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
185 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
186 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
187 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
188 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
189 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
190 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
191 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
192 >;
193 fsl,drive-strength = <0>;
194 fsl,voltage = <1>;
195 fsl,pull-up = <0>;
196 };
197
198 gpmi_pins_fixup: gpmi-pins-fixup {
199 fsl,pinmux-ids = <
200 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
201 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
202 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
203 >;
204 fsl,drive-strength = <2>;
205 };
206
Shawn Guo72beaba2012-06-28 11:44:59 +0800207 mmc0_4bit_pins_a: mmc0-4bit@0 {
208 reg = <0>;
209 fsl,pinmux-ids = <
210 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
211 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
212 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
213 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
214 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
Shawn Guo72beaba2012-06-28 11:44:59 +0800215 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
216 >;
217 fsl,drive-strength = <1>;
218 fsl,voltage = <1>;
219 fsl,pull-up = <1>;
220 };
221
Shawn Guobe1ce302012-05-06 16:29:36 +0800222 mmc0_8bit_pins_a: mmc0-8bit@0 {
223 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800224 fsl,pinmux-ids = <
225 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
226 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
227 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
228 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
229 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
230 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
231 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
232 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
233 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
234 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
235 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
236 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800237 fsl,drive-strength = <1>;
238 fsl,voltage = <1>;
239 fsl,pull-up = <1>;
240 };
241
242 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800243 fsl,pinmux-ids = <
244 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
245 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
246 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800247 fsl,pull-up = <0>;
248 };
Shawn Guo52f71762012-06-28 11:45:06 +0800249
250 pwm2_pins_a: pwm2@0 {
251 reg = <0>;
252 fsl,pinmux-ids = <
253 0x11c0 /* MX23_PAD_PWM2__PWM2 */
254 >;
255 fsl,drive-strength = <0>;
256 fsl,voltage = <1>;
257 fsl,pull-up = <0>;
258 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800259
260 lcdif_24bit_pins_a: lcdif-24bit@0 {
261 reg = <0>;
262 fsl,pinmux-ids = <
263 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
264 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
265 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
266 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
267 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
268 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
269 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
270 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
271 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
272 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
273 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
274 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
275 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
276 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
277 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
278 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
279 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
280 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
281 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
282 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
283 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
284 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
285 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
286 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
287 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
288 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
289 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
290 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
291 >;
292 fsl,drive-strength = <0>;
293 fsl,voltage = <1>;
294 fsl,pull-up = <0>;
295 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500296
297 spi2_pins_a: spi2@0 {
298 reg = <0>;
299 fsl,pinmux-ids = <
300 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
301 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
302 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
303 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
304 >;
305 fsl,drive-strength = <1>;
306 fsl,voltage = <1>;
307 fsl,pull-up = <1>;
308 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800309 };
310
311 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800312 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800313 reg = <0x8001c000 2000>;
314 status = "disabled";
315 };
316
317 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300318 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800319 status = "disabled";
320 };
321
Shawn Guof30fb032013-02-25 21:56:56 +0800322 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800323 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300324 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800325 interrupts = <7 5 9 26
326 19 0 25 23
327 60 58 9 0
328 0 0 0 0>;
329 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
330 "saif0", "empty", "auart0-rx", "auart0-tx",
331 "auart1-rx", "auart1-tx", "saif1", "empty",
332 "empty", "empty", "empty", "empty";
333 #dma-cells = <1>;
334 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800335 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800336 };
337
338 dcp@80028000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300339 reg = <0x80028000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800340 status = "disabled";
341 };
342
343 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300344 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800345 status = "disabled";
346 };
347
348 ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800349 compatible = "fsl,ocotp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300350 reg = <0x8002c000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800351 status = "disabled";
352 };
353
354 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300355 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800356 status = "disabled";
357 };
358
359 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800360 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800361 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800362 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800363 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800364 status = "disabled";
365 };
366
367 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300368 reg = <0x80034000 0x2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800369 interrupts = <2 20>;
Shawn Guo53f94432012-08-22 21:36:30 +0800370 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800371 dmas = <&dma_apbh 2>;
372 dma-names = "rx-tx";
Shawn Guobe1ce302012-05-06 16:29:36 +0800373 fsl,ssp-dma-channel = <2>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800374 status = "disabled";
375 };
376
377 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300378 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800379 status = "disabled";
380 };
381 };
382
383 apbx@80040000 {
384 compatible = "simple-bus";
385 #address-cells = <1>;
386 #size-cells = <1>;
387 reg = <0x80040000 0x40000>;
388 ranges;
389
Shawn Guo53f94432012-08-22 21:36:30 +0800390 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800391 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300392 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800393 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800394 };
395
396 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300397 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800398 dmas = <&dma_apbx 4>;
399 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800400 status = "disabled";
401 };
402
403 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300404 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800405 status = "disabled";
406 };
407
408 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300409 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800410 dmas = <&dma_apbx 10>;
411 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800412 status = "disabled";
413 };
414
415 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300416 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800417 dmas = <&dma_apbx 1>;
418 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800419 status = "disabled";
420 };
421
422 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300423 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800424 dmas = <&dma_apbx 0>;
425 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800426 status = "disabled";
427 };
428
429 lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000430 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300431 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000432 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800433 status = "disabled";
434 };
435
436 spdif@80054000 {
437 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800438 dmas = <&dma_apbx 2>;
439 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800440 status = "disabled";
441 };
442
443 i2c@80058000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300444 reg = <0x80058000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800445 dmas = <&dma_apbx 3>;
446 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800447 status = "disabled";
448 };
449
450 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800451 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300452 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800453 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800454 };
455
Shawn Guo52f71762012-06-28 11:45:06 +0800456 pwm: pwm@80064000 {
457 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300458 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800459 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800460 #pwm-cells = <2>;
461 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800462 status = "disabled";
463 };
464
465 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800466 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300467 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800468 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800469 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800470 };
471
472 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800473 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800474 reg = <0x8006c000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800475 interrupts = <24 25 23>;
Shawn Guo53f94432012-08-22 21:36:30 +0800476 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800477 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
478 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800479 status = "disabled";
480 };
481
482 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800483 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800484 reg = <0x8006e000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800485 interrupts = <59 60 58>;
Shawn Guo53f94432012-08-22 21:36:30 +0800486 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800487 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
488 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800489 status = "disabled";
490 };
491
492 duart: serial@80070000 {
493 compatible = "arm,pl011", "arm,primecell";
494 reg = <0x80070000 0x2000>;
495 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800496 clocks = <&clks 32>, <&clks 16>;
497 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800498 status = "disabled";
499 };
500
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300501 usbphy0: usbphy@8007c000 {
502 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800503 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300504 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800505 status = "disabled";
506 };
507 };
508 };
509
510 ahb@80080000 {
511 compatible = "simple-bus";
512 #address-cells = <1>;
513 #size-cells = <1>;
514 reg = <0x80080000 0x80000>;
515 ranges;
516
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300517 usb0: usb@80080000 {
518 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300519 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300520 interrupts = <11>;
521 fsl,usbphy = <&usbphy0>;
522 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800523 status = "disabled";
524 };
525 };
526};