blob: 207cbae3a7bf9f44cb3f75ac34d33d38d05fcae9 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Maxime Ripardf72f4b42016-07-20 16:11:36 +02002/*
Quentin Schulz23f75d72017-12-05 15:46:41 +01003 * AXP20x pinctrl and GPIO driver
Maxime Ripardf72f4b42016-07-20 16:11:36 +02004 *
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
Quentin Schulz23f75d72017-12-05 15:46:41 +01006 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
Maxime Ripardf72f4b42016-07-20 16:11:36 +02007 */
8
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/mfd/axp20x.h>
16#include <linux/module.h>
17#include <linux/of.h>
Quentin Schulze1190082017-12-05 15:46:46 +010018#include <linux/of_device.h>
Quentin Schulz23f75d72017-12-05 15:46:41 +010019#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
Maxime Ripardf72f4b42016-07-20 16:11:36 +020022#include <linux/platform_device.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25
26#define AXP20X_GPIO_FUNCTIONS 0x7
27#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
28#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
29#define AXP20X_GPIO_FUNCTION_INPUT 2
30
Quentin Schulz23f75d72017-12-05 15:46:41 +010031#define AXP20X_FUNC_GPIO_OUT 0
32#define AXP20X_FUNC_GPIO_IN 1
33#define AXP20X_FUNC_LDO 2
34#define AXP20X_FUNC_ADC 3
35#define AXP20X_FUNCS_NB 4
36
37#define AXP20X_MUX_GPIO_OUT 0
38#define AXP20X_MUX_GPIO_IN BIT(1)
39#define AXP20X_MUX_ADC BIT(2)
40
Quentin Schulze1190082017-12-05 15:46:46 +010041#define AXP813_MUX_ADC (BIT(2) | BIT(0))
42
Quentin Schulz23f75d72017-12-05 15:46:41 +010043struct axp20x_pctrl_desc {
44 const struct pinctrl_pin_desc *pins;
45 unsigned int npins;
46 /* Stores the pins supporting LDO function. Bit offset is pin number. */
47 u8 ldo_mask;
48 /* Stores the pins supporting ADC function. Bit offset is pin number. */
49 u8 adc_mask;
Quentin Schulz48e706f2017-12-05 15:46:44 +010050 u8 gpio_status_offset;
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010051 u8 adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +010052};
53
54struct axp20x_pinctrl_function {
55 const char *name;
56 unsigned int muxval;
57 const char **groups;
58 unsigned int ngroups;
59};
60
Quentin Schulzd242e602017-12-05 15:46:43 +010061struct axp20x_pctl {
Maxime Ripardf72f4b42016-07-20 16:11:36 +020062 struct gpio_chip chip;
63 struct regmap *regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +010064 struct pinctrl_dev *pctl_dev;
65 struct device *dev;
66 const struct axp20x_pctrl_desc *desc;
67 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
68};
69
70static const struct pinctrl_pin_desc axp209_pins[] = {
71 PINCTRL_PIN(0, "GPIO0"),
72 PINCTRL_PIN(1, "GPIO1"),
73 PINCTRL_PIN(2, "GPIO2"),
74};
75
Quentin Schulze1190082017-12-05 15:46:46 +010076static const struct pinctrl_pin_desc axp813_pins[] = {
77 PINCTRL_PIN(0, "GPIO0"),
78 PINCTRL_PIN(1, "GPIO1"),
79};
80
Quentin Schulz23f75d72017-12-05 15:46:41 +010081static const struct axp20x_pctrl_desc axp20x_data = {
82 .pins = axp209_pins,
83 .npins = ARRAY_SIZE(axp209_pins),
84 .ldo_mask = BIT(0) | BIT(1),
85 .adc_mask = BIT(0) | BIT(1),
Quentin Schulz48e706f2017-12-05 15:46:44 +010086 .gpio_status_offset = 4,
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010087 .adc_mux = AXP20X_MUX_ADC,
Maxime Ripardf72f4b42016-07-20 16:11:36 +020088};
89
Quentin Schulze1190082017-12-05 15:46:46 +010090static const struct axp20x_pctrl_desc axp813_data = {
91 .pins = axp813_pins,
92 .npins = ARRAY_SIZE(axp813_pins),
93 .ldo_mask = BIT(0) | BIT(1),
94 .adc_mask = BIT(0),
95 .gpio_status_offset = 0,
96 .adc_mux = AXP813_MUX_ADC,
97};
98
Quentin Schulz3cac9912017-12-05 15:46:39 +010099static int axp20x_gpio_get_reg(unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200100{
101 switch (offset) {
102 case 0:
103 return AXP20X_GPIO0_CTRL;
104 case 1:
105 return AXP20X_GPIO1_CTRL;
106 case 2:
107 return AXP20X_GPIO2_CTRL;
108 }
109
110 return -EINVAL;
111}
112
Quentin Schulz3cac9912017-12-05 15:46:39 +0100113static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200114{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100115 return pinctrl_gpio_direction_input(chip->base + offset);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200116}
117
Quentin Schulz3cac9912017-12-05 15:46:39 +0100118static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200119{
Quentin Schulzd242e602017-12-05 15:46:43 +0100120 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200121 unsigned int val;
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100122 int ret;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200123
Quentin Schulzd242e602017-12-05 15:46:43 +0100124 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200125 if (ret)
126 return ret;
127
Quentin Schulz48e706f2017-12-05 15:46:44 +0100128 return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200129}
130
Quentin Schulz3cac9912017-12-05 15:46:39 +0100131static int axp20x_gpio_get_direction(struct gpio_chip *chip,
132 unsigned int offset)
Maxime Ripard81d37532016-09-21 23:51:22 +0300133{
Quentin Schulzd242e602017-12-05 15:46:43 +0100134 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripard81d37532016-09-21 23:51:22 +0300135 unsigned int val;
136 int reg, ret;
137
138 reg = axp20x_gpio_get_reg(offset);
139 if (reg < 0)
140 return reg;
141
Quentin Schulzd242e602017-12-05 15:46:43 +0100142 ret = regmap_read(pctl->regmap, reg, &val);
Maxime Ripard81d37532016-09-21 23:51:22 +0300143 if (ret)
144 return ret;
145
146 /*
147 * This shouldn't really happen if the pin is in use already,
148 * or if it's not in use yet, it doesn't matter since we're
149 * going to change the value soon anyway. Default to output.
150 */
151 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
Matti Vaittinen3c827872020-02-14 15:57:12 +0200152 return GPIO_LINE_DIRECTION_OUT;
Maxime Ripard81d37532016-09-21 23:51:22 +0300153
154 /*
155 * The GPIO directions are the three lowest values.
156 * 2 is input, 0 and 1 are output
157 */
Matti Vaittinen3c827872020-02-14 15:57:12 +0200158 if (val & 2)
159 return GPIO_LINE_DIRECTION_IN;
160
161 return GPIO_LINE_DIRECTION_OUT;
Maxime Ripard81d37532016-09-21 23:51:22 +0300162}
163
Quentin Schulz3cac9912017-12-05 15:46:39 +0100164static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200165 int value)
166{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100167 chip->set(chip, offset, value);
168
169 return 0;
170}
171
172static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
173 int value)
174{
Quentin Schulzd242e602017-12-05 15:46:43 +0100175 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200176 int reg;
177
178 reg = axp20x_gpio_get_reg(offset);
179 if (reg < 0)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100180 return;
181
Quentin Schulzd242e602017-12-05 15:46:43 +0100182 regmap_update_bits(pctl->regmap, reg,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100183 AXP20X_GPIO_FUNCTIONS,
184 value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
185 AXP20X_GPIO_FUNCTION_OUT_LOW);
186}
187
188static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
189 u8 config)
190{
Quentin Schulzd242e602017-12-05 15:46:43 +0100191 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100192 int reg;
193
194 reg = axp20x_gpio_get_reg(offset);
195 if (reg < 0)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200196 return reg;
197
Quentin Schulzd242e602017-12-05 15:46:43 +0100198 return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100199 config);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200200}
201
Quentin Schulz23f75d72017-12-05 15:46:41 +0100202static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200203{
Quentin Schulzd242e602017-12-05 15:46:43 +0100204 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100205
Quentin Schulzd242e602017-12-05 15:46:43 +0100206 return ARRAY_SIZE(pctl->funcs);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100207}
208
209static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
210 unsigned int selector)
211{
Quentin Schulzd242e602017-12-05 15:46:43 +0100212 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100213
Quentin Schulzd242e602017-12-05 15:46:43 +0100214 return pctl->funcs[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100215}
216
217static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
218 unsigned int selector,
219 const char * const **groups,
220 unsigned int *num_groups)
221{
Quentin Schulzd242e602017-12-05 15:46:43 +0100222 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100223
Quentin Schulzd242e602017-12-05 15:46:43 +0100224 *groups = pctl->funcs[selector].groups;
225 *num_groups = pctl->funcs[selector].ngroups;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100226
227 return 0;
228}
229
230static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
231 unsigned int function, unsigned int group)
232{
Quentin Schulzd242e602017-12-05 15:46:43 +0100233 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100234 unsigned int mask;
235
236 /* Every pin supports GPIO_OUT and GPIO_IN functions */
237 if (function <= AXP20X_FUNC_GPIO_IN)
238 return axp20x_pmx_set(pctldev, group,
Quentin Schulzd242e602017-12-05 15:46:43 +0100239 pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100240
241 if (function == AXP20X_FUNC_LDO)
Quentin Schulzd242e602017-12-05 15:46:43 +0100242 mask = pctl->desc->ldo_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100243 else
Quentin Schulzd242e602017-12-05 15:46:43 +0100244 mask = pctl->desc->adc_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100245
246 if (!(BIT(group) & mask))
247 return -EINVAL;
248
249 /*
250 * We let the regulator framework handle the LDO muxing as muxing bits
251 * are basically also regulators on/off bits. It's better not to enforce
252 * any state of the regulator when selecting LDO mux so that we don't
253 * interfere with the regulator driver.
254 */
255 if (function == AXP20X_FUNC_LDO)
256 return 0;
257
Quentin Schulzd242e602017-12-05 15:46:43 +0100258 return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100259}
260
261static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
262 struct pinctrl_gpio_range *range,
263 unsigned int offset, bool input)
264{
Quentin Schulzd242e602017-12-05 15:46:43 +0100265 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100266
267 if (input)
268 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100269 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100270
271 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100272 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100273}
274
275static const struct pinmux_ops axp20x_pmx_ops = {
276 .get_functions_count = axp20x_pmx_func_cnt,
277 .get_function_name = axp20x_pmx_func_name,
278 .get_function_groups = axp20x_pmx_func_groups,
279 .set_mux = axp20x_pmx_set_mux,
280 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
281 .strict = true,
282};
283
284static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
285{
Quentin Schulzd242e602017-12-05 15:46:43 +0100286 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100287
Quentin Schulzd242e602017-12-05 15:46:43 +0100288 return pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100289}
290
291static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
292 const unsigned int **pins, unsigned int *num_pins)
293{
Quentin Schulzd242e602017-12-05 15:46:43 +0100294 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100295
Quentin Schulzd242e602017-12-05 15:46:43 +0100296 *pins = (unsigned int *)&pctl->desc->pins[selector];
Quentin Schulz23f75d72017-12-05 15:46:41 +0100297 *num_pins = 1;
298
299 return 0;
300}
301
302static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
303 unsigned int selector)
304{
Quentin Schulzd242e602017-12-05 15:46:43 +0100305 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100306
Quentin Schulzd242e602017-12-05 15:46:43 +0100307 return pctl->desc->pins[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100308}
309
310static const struct pinctrl_ops axp20x_pctrl_ops = {
311 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
312 .dt_free_map = pinconf_generic_dt_free_map,
313 .get_groups_count = axp20x_groups_cnt,
314 .get_group_name = axp20x_group_name,
315 .get_group_pins = axp20x_group_pins,
316};
317
Anton Vasilyev504c7692018-08-06 19:06:35 +0300318static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100319 unsigned int mask_len,
320 struct axp20x_pinctrl_function *func,
321 const struct pinctrl_pin_desc *pins)
322{
323 unsigned long int mask_cpy = mask;
324 const char **group;
325 unsigned int ngroups = hweight8(mask);
326 int bit;
327
328 func->ngroups = ngroups;
329 if (func->ngroups > 0) {
Kees Cooka86854d2018-06-12 14:07:58 -0700330 func->groups = devm_kcalloc(dev,
331 ngroups, sizeof(const char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100332 GFP_KERNEL);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300333 if (!func->groups)
334 return -ENOMEM;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100335 group = func->groups;
336 for_each_set_bit(bit, &mask_cpy, mask_len) {
337 *group = pins[bit].name;
338 group++;
339 }
340 }
Anton Vasilyev504c7692018-08-06 19:06:35 +0300341
342 return 0;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100343}
344
Anton Vasilyev504c7692018-08-06 19:06:35 +0300345static int axp20x_build_funcs_groups(struct platform_device *pdev)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100346{
Quentin Schulzd242e602017-12-05 15:46:43 +0100347 struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300348 int i, ret, pin, npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100349
Quentin Schulzd242e602017-12-05 15:46:43 +0100350 pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
351 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
352 pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
353 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
354 pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
Quentin Schulz23f75d72017-12-05 15:46:41 +0100355 /*
356 * Muxval for LDO is useless as we won't use it.
357 * See comment in axp20x_pmx_set_mux.
358 */
Quentin Schulzd242e602017-12-05 15:46:43 +0100359 pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
Quentin Schulza0a4b4c2017-12-05 15:46:45 +0100360 pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100361
362 /* Every pin supports GPIO_OUT and GPIO_IN functions */
363 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
Quentin Schulzd242e602017-12-05 15:46:43 +0100364 pctl->funcs[i].ngroups = npins;
Kees Cooka86854d2018-06-12 14:07:58 -0700365 pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
366 npins, sizeof(char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100367 GFP_KERNEL);
Aditya Pakki1adc90c2019-03-12 10:19:10 -0500368 if (!pctl->funcs[i].groups)
369 return -ENOMEM;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100370 for (pin = 0; pin < npins; pin++)
Quentin Schulzd242e602017-12-05 15:46:43 +0100371 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100372 }
373
Anton Vasilyev504c7692018-08-06 19:06:35 +0300374 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100375 npins, &pctl->funcs[AXP20X_FUNC_LDO],
376 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300377 if (ret)
378 return ret;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100379
Anton Vasilyev504c7692018-08-06 19:06:35 +0300380 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100381 npins, &pctl->funcs[AXP20X_FUNC_ADC],
382 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300383 if (ret)
384 return ret;
385
386 return 0;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200387}
388
Quentin Schulze1190082017-12-05 15:46:46 +0100389static const struct of_device_id axp20x_pctl_match[] = {
390 { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
391 { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
392 { }
393};
394MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
395
Quentin Schulzd242e602017-12-05 15:46:43 +0100396static int axp20x_pctl_probe(struct platform_device *pdev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200397{
398 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Quentin Schulzd242e602017-12-05 15:46:43 +0100399 struct axp20x_pctl *pctl;
Quentin Schulze1190082017-12-05 15:46:46 +0100400 struct device *dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100401 struct pinctrl_desc *pctrl_desc;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200402 int ret;
403
404 if (!of_device_is_available(pdev->dev.of_node))
405 return -ENODEV;
406
407 if (!axp20x) {
408 dev_err(&pdev->dev, "Parent drvdata not set\n");
409 return -EINVAL;
410 }
411
Quentin Schulzd242e602017-12-05 15:46:43 +0100412 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
413 if (!pctl)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200414 return -ENOMEM;
415
Quentin Schulzd242e602017-12-05 15:46:43 +0100416 pctl->chip.base = -1;
417 pctl->chip.can_sleep = true;
418 pctl->chip.request = gpiochip_generic_request;
419 pctl->chip.free = gpiochip_generic_free;
420 pctl->chip.parent = &pdev->dev;
421 pctl->chip.label = dev_name(&pdev->dev);
422 pctl->chip.owner = THIS_MODULE;
423 pctl->chip.get = axp20x_gpio_get;
424 pctl->chip.get_direction = axp20x_gpio_get_direction;
425 pctl->chip.set = axp20x_gpio_set;
426 pctl->chip.direction_input = axp20x_gpio_input;
427 pctl->chip.direction_output = axp20x_gpio_output;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200428
Julia Lawall9b8ee3c2018-01-02 14:28:04 +0100429 pctl->desc = of_device_get_match_data(dev);
Quentin Schulza0498152017-12-13 09:55:03 +0100430
431 pctl->chip.ngpio = pctl->desc->npins;
432
Quentin Schulzd242e602017-12-05 15:46:43 +0100433 pctl->regmap = axp20x->regmap;
434 pctl->dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100435
Quentin Schulzd242e602017-12-05 15:46:43 +0100436 platform_set_drvdata(pdev, pctl);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100437
Anton Vasilyev504c7692018-08-06 19:06:35 +0300438 ret = axp20x_build_funcs_groups(pdev);
439 if (ret) {
440 dev_err(&pdev->dev, "failed to build groups\n");
441 return ret;
442 }
Quentin Schulz23f75d72017-12-05 15:46:41 +0100443
444 pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
445 if (!pctrl_desc)
446 return -ENOMEM;
447
448 pctrl_desc->name = dev_name(&pdev->dev);
449 pctrl_desc->owner = THIS_MODULE;
Quentin Schulzd242e602017-12-05 15:46:43 +0100450 pctrl_desc->pins = pctl->desc->pins;
451 pctrl_desc->npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100452 pctrl_desc->pctlops = &axp20x_pctrl_ops;
453 pctrl_desc->pmxops = &axp20x_pmx_ops;
454
Quentin Schulzd242e602017-12-05 15:46:43 +0100455 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
456 if (IS_ERR(pctl->pctl_dev)) {
Quentin Schulz23f75d72017-12-05 15:46:41 +0100457 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
Quentin Schulzd242e602017-12-05 15:46:43 +0100458 return PTR_ERR(pctl->pctl_dev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100459 }
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200460
Quentin Schulzd242e602017-12-05 15:46:43 +0100461 ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200462 if (ret) {
463 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
464 return ret;
465 }
466
Quentin Schulzd242e602017-12-05 15:46:43 +0100467 ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
468 pctl->desc->pins->number,
469 pctl->desc->pins->number,
470 pctl->desc->npins);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100471 if (ret) {
472 dev_err(&pdev->dev, "failed to add pin range\n");
473 return ret;
474 }
475
476 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200477
478 return 0;
479}
480
Quentin Schulzd242e602017-12-05 15:46:43 +0100481static struct platform_driver axp20x_pctl_driver = {
482 .probe = axp20x_pctl_probe,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200483 .driver = {
484 .name = "axp20x-gpio",
Quentin Schulzd242e602017-12-05 15:46:43 +0100485 .of_match_table = axp20x_pctl_match,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200486 },
487};
488
Quentin Schulzd242e602017-12-05 15:46:43 +0100489module_platform_driver(axp20x_pctl_driver);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200490
491MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Quentin Schulz23f75d72017-12-05 15:46:41 +0100492MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
493MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200494MODULE_LICENSE("GPL");