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Maxime Ripardf72f4b42016-07-20 16:11:36 +02001/*
Quentin Schulz23f75d72017-12-05 15:46:41 +01002 * AXP20x pinctrl and GPIO driver
Maxime Ripardf72f4b42016-07-20 16:11:36 +02003 *
4 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
Quentin Schulz23f75d72017-12-05 15:46:41 +01005 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
Maxime Ripardf72f4b42016-07-20 16:11:36 +02006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/bitops.h>
14#include <linux/device.h>
15#include <linux/gpio/driver.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/mfd/axp20x.h>
20#include <linux/module.h>
21#include <linux/of.h>
Quentin Schulz23f75d72017-12-05 15:46:41 +010022#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
Maxime Ripardf72f4b42016-07-20 16:11:36 +020025#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <linux/slab.h>
28
29#define AXP20X_GPIO_FUNCTIONS 0x7
30#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
31#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
32#define AXP20X_GPIO_FUNCTION_INPUT 2
33
Quentin Schulz23f75d72017-12-05 15:46:41 +010034#define AXP20X_FUNC_GPIO_OUT 0
35#define AXP20X_FUNC_GPIO_IN 1
36#define AXP20X_FUNC_LDO 2
37#define AXP20X_FUNC_ADC 3
38#define AXP20X_FUNCS_NB 4
39
40#define AXP20X_MUX_GPIO_OUT 0
41#define AXP20X_MUX_GPIO_IN BIT(1)
42#define AXP20X_MUX_ADC BIT(2)
43
44struct axp20x_pctrl_desc {
45 const struct pinctrl_pin_desc *pins;
46 unsigned int npins;
47 /* Stores the pins supporting LDO function. Bit offset is pin number. */
48 u8 ldo_mask;
49 /* Stores the pins supporting ADC function. Bit offset is pin number. */
50 u8 adc_mask;
51};
52
53struct axp20x_pinctrl_function {
54 const char *name;
55 unsigned int muxval;
56 const char **groups;
57 unsigned int ngroups;
58};
59
Maxime Ripardf72f4b42016-07-20 16:11:36 +020060struct axp20x_gpio {
61 struct gpio_chip chip;
62 struct regmap *regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +010063 struct pinctrl_dev *pctl_dev;
64 struct device *dev;
65 const struct axp20x_pctrl_desc *desc;
66 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
67};
68
69static const struct pinctrl_pin_desc axp209_pins[] = {
70 PINCTRL_PIN(0, "GPIO0"),
71 PINCTRL_PIN(1, "GPIO1"),
72 PINCTRL_PIN(2, "GPIO2"),
73};
74
75static const struct axp20x_pctrl_desc axp20x_data = {
76 .pins = axp209_pins,
77 .npins = ARRAY_SIZE(axp209_pins),
78 .ldo_mask = BIT(0) | BIT(1),
79 .adc_mask = BIT(0) | BIT(1),
Maxime Ripardf72f4b42016-07-20 16:11:36 +020080};
81
Quentin Schulz3cac9912017-12-05 15:46:39 +010082static int axp20x_gpio_get_reg(unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +020083{
84 switch (offset) {
85 case 0:
86 return AXP20X_GPIO0_CTRL;
87 case 1:
88 return AXP20X_GPIO1_CTRL;
89 case 2:
90 return AXP20X_GPIO2_CTRL;
91 }
92
93 return -EINVAL;
94}
95
Quentin Schulz3cac9912017-12-05 15:46:39 +010096static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +020097{
Quentin Schulz23f75d72017-12-05 15:46:41 +010098 return pinctrl_gpio_direction_input(chip->base + offset);
Maxime Ripardf72f4b42016-07-20 16:11:36 +020099}
100
Quentin Schulz3cac9912017-12-05 15:46:39 +0100101static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200102{
103 struct axp20x_gpio *gpio = gpiochip_get_data(chip);
104 unsigned int val;
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100105 int ret;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200106
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100107 ret = regmap_read(gpio->regmap, AXP20X_GPIO20_SS, &val);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200108 if (ret)
109 return ret;
110
111 return !!(val & BIT(offset + 4));
112}
113
Quentin Schulz3cac9912017-12-05 15:46:39 +0100114static int axp20x_gpio_get_direction(struct gpio_chip *chip,
115 unsigned int offset)
Maxime Ripard81d37532016-09-21 23:51:22 +0300116{
117 struct axp20x_gpio *gpio = gpiochip_get_data(chip);
118 unsigned int val;
119 int reg, ret;
120
121 reg = axp20x_gpio_get_reg(offset);
122 if (reg < 0)
123 return reg;
124
125 ret = regmap_read(gpio->regmap, reg, &val);
126 if (ret)
127 return ret;
128
129 /*
130 * This shouldn't really happen if the pin is in use already,
131 * or if it's not in use yet, it doesn't matter since we're
132 * going to change the value soon anyway. Default to output.
133 */
134 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
135 return 0;
136
137 /*
138 * The GPIO directions are the three lowest values.
139 * 2 is input, 0 and 1 are output
140 */
141 return val & 2;
142}
143
Quentin Schulz3cac9912017-12-05 15:46:39 +0100144static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200145 int value)
146{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100147 chip->set(chip, offset, value);
148
149 return 0;
150}
151
152static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
153 int value)
154{
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200155 struct axp20x_gpio *gpio = gpiochip_get_data(chip);
156 int reg;
157
158 reg = axp20x_gpio_get_reg(offset);
159 if (reg < 0)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100160 return;
161
162 regmap_update_bits(gpio->regmap, reg,
163 AXP20X_GPIO_FUNCTIONS,
164 value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
165 AXP20X_GPIO_FUNCTION_OUT_LOW);
166}
167
168static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
169 u8 config)
170{
171 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
172 int reg;
173
174 reg = axp20x_gpio_get_reg(offset);
175 if (reg < 0)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200176 return reg;
177
Quentin Schulz23f75d72017-12-05 15:46:41 +0100178 return regmap_update_bits(gpio->regmap, reg, AXP20X_GPIO_FUNCTIONS,
179 config);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200180}
181
Quentin Schulz23f75d72017-12-05 15:46:41 +0100182static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200183{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100184 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
185
186 return ARRAY_SIZE(gpio->funcs);
187}
188
189static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
190 unsigned int selector)
191{
192 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
193
194 return gpio->funcs[selector].name;
195}
196
197static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
198 unsigned int selector,
199 const char * const **groups,
200 unsigned int *num_groups)
201{
202 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
203
204 *groups = gpio->funcs[selector].groups;
205 *num_groups = gpio->funcs[selector].ngroups;
206
207 return 0;
208}
209
210static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
211 unsigned int function, unsigned int group)
212{
213 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
214 unsigned int mask;
215
216 /* Every pin supports GPIO_OUT and GPIO_IN functions */
217 if (function <= AXP20X_FUNC_GPIO_IN)
218 return axp20x_pmx_set(pctldev, group,
219 gpio->funcs[function].muxval);
220
221 if (function == AXP20X_FUNC_LDO)
222 mask = gpio->desc->ldo_mask;
223 else
224 mask = gpio->desc->adc_mask;
225
226 if (!(BIT(group) & mask))
227 return -EINVAL;
228
229 /*
230 * We let the regulator framework handle the LDO muxing as muxing bits
231 * are basically also regulators on/off bits. It's better not to enforce
232 * any state of the regulator when selecting LDO mux so that we don't
233 * interfere with the regulator driver.
234 */
235 if (function == AXP20X_FUNC_LDO)
236 return 0;
237
238 return axp20x_pmx_set(pctldev, group, gpio->funcs[function].muxval);
239}
240
241static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
242 struct pinctrl_gpio_range *range,
243 unsigned int offset, bool input)
244{
245 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
246
247 if (input)
248 return axp20x_pmx_set(pctldev, offset,
249 gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval);
250
251 return axp20x_pmx_set(pctldev, offset,
252 gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
253}
254
255static const struct pinmux_ops axp20x_pmx_ops = {
256 .get_functions_count = axp20x_pmx_func_cnt,
257 .get_function_name = axp20x_pmx_func_name,
258 .get_function_groups = axp20x_pmx_func_groups,
259 .set_mux = axp20x_pmx_set_mux,
260 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
261 .strict = true,
262};
263
264static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
265{
266 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
267
268 return gpio->desc->npins;
269}
270
271static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
272 const unsigned int **pins, unsigned int *num_pins)
273{
274 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
275
276 *pins = (unsigned int *)&gpio->desc->pins[selector];
277 *num_pins = 1;
278
279 return 0;
280}
281
282static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
283 unsigned int selector)
284{
285 struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
286
287 return gpio->desc->pins[selector].name;
288}
289
290static const struct pinctrl_ops axp20x_pctrl_ops = {
291 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
292 .dt_free_map = pinconf_generic_dt_free_map,
293 .get_groups_count = axp20x_groups_cnt,
294 .get_group_name = axp20x_group_name,
295 .get_group_pins = axp20x_group_pins,
296};
297
298static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
299 unsigned int mask_len,
300 struct axp20x_pinctrl_function *func,
301 const struct pinctrl_pin_desc *pins)
302{
303 unsigned long int mask_cpy = mask;
304 const char **group;
305 unsigned int ngroups = hweight8(mask);
306 int bit;
307
308 func->ngroups = ngroups;
309 if (func->ngroups > 0) {
310 func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *),
311 GFP_KERNEL);
312 group = func->groups;
313 for_each_set_bit(bit, &mask_cpy, mask_len) {
314 *group = pins[bit].name;
315 group++;
316 }
317 }
318}
319
320static void axp20x_build_funcs_groups(struct platform_device *pdev)
321{
322 struct axp20x_gpio *gpio = platform_get_drvdata(pdev);
323 int i, pin, npins = gpio->desc->npins;
324
325 gpio->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
326 gpio->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
327 gpio->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
328 gpio->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
329 gpio->funcs[AXP20X_FUNC_LDO].name = "ldo";
330 /*
331 * Muxval for LDO is useless as we won't use it.
332 * See comment in axp20x_pmx_set_mux.
333 */
334 gpio->funcs[AXP20X_FUNC_ADC].name = "adc";
335 gpio->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC;
336
337 /* Every pin supports GPIO_OUT and GPIO_IN functions */
338 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
339 gpio->funcs[i].ngroups = npins;
340 gpio->funcs[i].groups = devm_kzalloc(&pdev->dev,
341 npins * sizeof(char *),
342 GFP_KERNEL);
343 for (pin = 0; pin < npins; pin++)
344 gpio->funcs[i].groups[pin] = gpio->desc->pins[pin].name;
345 }
346
347 axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->ldo_mask,
348 npins, &gpio->funcs[AXP20X_FUNC_LDO],
349 gpio->desc->pins);
350
351 axp20x_funcs_groups_from_mask(&pdev->dev, gpio->desc->adc_mask,
352 npins, &gpio->funcs[AXP20X_FUNC_ADC],
353 gpio->desc->pins);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200354}
355
356static int axp20x_gpio_probe(struct platform_device *pdev)
357{
358 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
359 struct axp20x_gpio *gpio;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100360 struct pinctrl_desc *pctrl_desc;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200361 int ret;
362
363 if (!of_device_is_available(pdev->dev.of_node))
364 return -ENODEV;
365
366 if (!axp20x) {
367 dev_err(&pdev->dev, "Parent drvdata not set\n");
368 return -EINVAL;
369 }
370
371 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
372 if (!gpio)
373 return -ENOMEM;
374
375 gpio->chip.base = -1;
376 gpio->chip.can_sleep = true;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100377 gpio->chip.request = gpiochip_generic_request;
378 gpio->chip.free = gpiochip_generic_free;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200379 gpio->chip.parent = &pdev->dev;
380 gpio->chip.label = dev_name(&pdev->dev);
381 gpio->chip.owner = THIS_MODULE;
382 gpio->chip.get = axp20x_gpio_get;
Maxime Ripard81d37532016-09-21 23:51:22 +0300383 gpio->chip.get_direction = axp20x_gpio_get_direction;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200384 gpio->chip.set = axp20x_gpio_set;
385 gpio->chip.direction_input = axp20x_gpio_input;
386 gpio->chip.direction_output = axp20x_gpio_output;
387 gpio->chip.ngpio = 3;
388
Quentin Schulz23f75d72017-12-05 15:46:41 +0100389 gpio->desc = &axp20x_data;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200390 gpio->regmap = axp20x->regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100391 gpio->dev = &pdev->dev;
392
393 platform_set_drvdata(pdev, gpio);
394
395 axp20x_build_funcs_groups(pdev);
396
397 pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
398 if (!pctrl_desc)
399 return -ENOMEM;
400
401 pctrl_desc->name = dev_name(&pdev->dev);
402 pctrl_desc->owner = THIS_MODULE;
403 pctrl_desc->pins = gpio->desc->pins;
404 pctrl_desc->npins = gpio->desc->npins;
405 pctrl_desc->pctlops = &axp20x_pctrl_ops;
406 pctrl_desc->pmxops = &axp20x_pmx_ops;
407
408 gpio->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, gpio);
409 if (IS_ERR(gpio->pctl_dev)) {
410 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
411 return PTR_ERR(gpio->pctl_dev);
412 }
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200413
414 ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
415 if (ret) {
416 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
417 return ret;
418 }
419
Quentin Schulz23f75d72017-12-05 15:46:41 +0100420 ret = gpiochip_add_pin_range(&gpio->chip, dev_name(&pdev->dev),
421 gpio->desc->pins->number,
422 gpio->desc->pins->number,
423 gpio->desc->npins);
424 if (ret) {
425 dev_err(&pdev->dev, "failed to add pin range\n");
426 return ret;
427 }
428
429 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200430
431 return 0;
432}
433
434static const struct of_device_id axp20x_gpio_match[] = {
435 { .compatible = "x-powers,axp209-gpio" },
436 { }
437};
438MODULE_DEVICE_TABLE(of, axp20x_gpio_match);
439
440static struct platform_driver axp20x_gpio_driver = {
441 .probe = axp20x_gpio_probe,
442 .driver = {
443 .name = "axp20x-gpio",
444 .of_match_table = axp20x_gpio_match,
445 },
446};
447
448module_platform_driver(axp20x_gpio_driver);
449
450MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Quentin Schulz23f75d72017-12-05 15:46:41 +0100451MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
452MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200453MODULE_LICENSE("GPL");