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Maxime Ripardf72f4b42016-07-20 16:11:36 +02001/*
Quentin Schulz23f75d72017-12-05 15:46:41 +01002 * AXP20x pinctrl and GPIO driver
Maxime Ripardf72f4b42016-07-20 16:11:36 +02003 *
4 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
Quentin Schulz23f75d72017-12-05 15:46:41 +01005 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
Maxime Ripardf72f4b42016-07-20 16:11:36 +02006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/bitops.h>
14#include <linux/device.h>
15#include <linux/gpio/driver.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/mfd/axp20x.h>
20#include <linux/module.h>
21#include <linux/of.h>
Quentin Schulz23f75d72017-12-05 15:46:41 +010022#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
Maxime Ripardf72f4b42016-07-20 16:11:36 +020025#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <linux/slab.h>
28
29#define AXP20X_GPIO_FUNCTIONS 0x7
30#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
31#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
32#define AXP20X_GPIO_FUNCTION_INPUT 2
33
Quentin Schulz23f75d72017-12-05 15:46:41 +010034#define AXP20X_FUNC_GPIO_OUT 0
35#define AXP20X_FUNC_GPIO_IN 1
36#define AXP20X_FUNC_LDO 2
37#define AXP20X_FUNC_ADC 3
38#define AXP20X_FUNCS_NB 4
39
40#define AXP20X_MUX_GPIO_OUT 0
41#define AXP20X_MUX_GPIO_IN BIT(1)
42#define AXP20X_MUX_ADC BIT(2)
43
44struct axp20x_pctrl_desc {
45 const struct pinctrl_pin_desc *pins;
46 unsigned int npins;
47 /* Stores the pins supporting LDO function. Bit offset is pin number. */
48 u8 ldo_mask;
49 /* Stores the pins supporting ADC function. Bit offset is pin number. */
50 u8 adc_mask;
Quentin Schulz48e706f2017-12-05 15:46:44 +010051 u8 gpio_status_offset;
Quentin Schulz23f75d72017-12-05 15:46:41 +010052};
53
54struct axp20x_pinctrl_function {
55 const char *name;
56 unsigned int muxval;
57 const char **groups;
58 unsigned int ngroups;
59};
60
Quentin Schulzd242e602017-12-05 15:46:43 +010061struct axp20x_pctl {
Maxime Ripardf72f4b42016-07-20 16:11:36 +020062 struct gpio_chip chip;
63 struct regmap *regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +010064 struct pinctrl_dev *pctl_dev;
65 struct device *dev;
66 const struct axp20x_pctrl_desc *desc;
67 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
68};
69
70static const struct pinctrl_pin_desc axp209_pins[] = {
71 PINCTRL_PIN(0, "GPIO0"),
72 PINCTRL_PIN(1, "GPIO1"),
73 PINCTRL_PIN(2, "GPIO2"),
74};
75
76static const struct axp20x_pctrl_desc axp20x_data = {
77 .pins = axp209_pins,
78 .npins = ARRAY_SIZE(axp209_pins),
79 .ldo_mask = BIT(0) | BIT(1),
80 .adc_mask = BIT(0) | BIT(1),
Quentin Schulz48e706f2017-12-05 15:46:44 +010081 .gpio_status_offset = 4,
Maxime Ripardf72f4b42016-07-20 16:11:36 +020082};
83
Quentin Schulz3cac9912017-12-05 15:46:39 +010084static int axp20x_gpio_get_reg(unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +020085{
86 switch (offset) {
87 case 0:
88 return AXP20X_GPIO0_CTRL;
89 case 1:
90 return AXP20X_GPIO1_CTRL;
91 case 2:
92 return AXP20X_GPIO2_CTRL;
93 }
94
95 return -EINVAL;
96}
97
Quentin Schulz3cac9912017-12-05 15:46:39 +010098static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +020099{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100100 return pinctrl_gpio_direction_input(chip->base + offset);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200101}
102
Quentin Schulz3cac9912017-12-05 15:46:39 +0100103static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200104{
Quentin Schulzd242e602017-12-05 15:46:43 +0100105 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200106 unsigned int val;
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100107 int ret;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200108
Quentin Schulzd242e602017-12-05 15:46:43 +0100109 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200110 if (ret)
111 return ret;
112
Quentin Schulz48e706f2017-12-05 15:46:44 +0100113 return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200114}
115
Quentin Schulz3cac9912017-12-05 15:46:39 +0100116static int axp20x_gpio_get_direction(struct gpio_chip *chip,
117 unsigned int offset)
Maxime Ripard81d37532016-09-21 23:51:22 +0300118{
Quentin Schulzd242e602017-12-05 15:46:43 +0100119 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripard81d37532016-09-21 23:51:22 +0300120 unsigned int val;
121 int reg, ret;
122
123 reg = axp20x_gpio_get_reg(offset);
124 if (reg < 0)
125 return reg;
126
Quentin Schulzd242e602017-12-05 15:46:43 +0100127 ret = regmap_read(pctl->regmap, reg, &val);
Maxime Ripard81d37532016-09-21 23:51:22 +0300128 if (ret)
129 return ret;
130
131 /*
132 * This shouldn't really happen if the pin is in use already,
133 * or if it's not in use yet, it doesn't matter since we're
134 * going to change the value soon anyway. Default to output.
135 */
136 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
137 return 0;
138
139 /*
140 * The GPIO directions are the three lowest values.
141 * 2 is input, 0 and 1 are output
142 */
143 return val & 2;
144}
145
Quentin Schulz3cac9912017-12-05 15:46:39 +0100146static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200147 int value)
148{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100149 chip->set(chip, offset, value);
150
151 return 0;
152}
153
154static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
155 int value)
156{
Quentin Schulzd242e602017-12-05 15:46:43 +0100157 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200158 int reg;
159
160 reg = axp20x_gpio_get_reg(offset);
161 if (reg < 0)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100162 return;
163
Quentin Schulzd242e602017-12-05 15:46:43 +0100164 regmap_update_bits(pctl->regmap, reg,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100165 AXP20X_GPIO_FUNCTIONS,
166 value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
167 AXP20X_GPIO_FUNCTION_OUT_LOW);
168}
169
170static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
171 u8 config)
172{
Quentin Schulzd242e602017-12-05 15:46:43 +0100173 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100174 int reg;
175
176 reg = axp20x_gpio_get_reg(offset);
177 if (reg < 0)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200178 return reg;
179
Quentin Schulzd242e602017-12-05 15:46:43 +0100180 return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100181 config);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200182}
183
Quentin Schulz23f75d72017-12-05 15:46:41 +0100184static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200185{
Quentin Schulzd242e602017-12-05 15:46:43 +0100186 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100187
Quentin Schulzd242e602017-12-05 15:46:43 +0100188 return ARRAY_SIZE(pctl->funcs);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100189}
190
191static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
192 unsigned int selector)
193{
Quentin Schulzd242e602017-12-05 15:46:43 +0100194 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100195
Quentin Schulzd242e602017-12-05 15:46:43 +0100196 return pctl->funcs[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100197}
198
199static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
200 unsigned int selector,
201 const char * const **groups,
202 unsigned int *num_groups)
203{
Quentin Schulzd242e602017-12-05 15:46:43 +0100204 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100205
Quentin Schulzd242e602017-12-05 15:46:43 +0100206 *groups = pctl->funcs[selector].groups;
207 *num_groups = pctl->funcs[selector].ngroups;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100208
209 return 0;
210}
211
212static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
213 unsigned int function, unsigned int group)
214{
Quentin Schulzd242e602017-12-05 15:46:43 +0100215 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100216 unsigned int mask;
217
218 /* Every pin supports GPIO_OUT and GPIO_IN functions */
219 if (function <= AXP20X_FUNC_GPIO_IN)
220 return axp20x_pmx_set(pctldev, group,
Quentin Schulzd242e602017-12-05 15:46:43 +0100221 pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100222
223 if (function == AXP20X_FUNC_LDO)
Quentin Schulzd242e602017-12-05 15:46:43 +0100224 mask = pctl->desc->ldo_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100225 else
Quentin Schulzd242e602017-12-05 15:46:43 +0100226 mask = pctl->desc->adc_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100227
228 if (!(BIT(group) & mask))
229 return -EINVAL;
230
231 /*
232 * We let the regulator framework handle the LDO muxing as muxing bits
233 * are basically also regulators on/off bits. It's better not to enforce
234 * any state of the regulator when selecting LDO mux so that we don't
235 * interfere with the regulator driver.
236 */
237 if (function == AXP20X_FUNC_LDO)
238 return 0;
239
Quentin Schulzd242e602017-12-05 15:46:43 +0100240 return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100241}
242
243static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
244 struct pinctrl_gpio_range *range,
245 unsigned int offset, bool input)
246{
Quentin Schulzd242e602017-12-05 15:46:43 +0100247 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100248
249 if (input)
250 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100251 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100252
253 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100254 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100255}
256
257static const struct pinmux_ops axp20x_pmx_ops = {
258 .get_functions_count = axp20x_pmx_func_cnt,
259 .get_function_name = axp20x_pmx_func_name,
260 .get_function_groups = axp20x_pmx_func_groups,
261 .set_mux = axp20x_pmx_set_mux,
262 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
263 .strict = true,
264};
265
266static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
267{
Quentin Schulzd242e602017-12-05 15:46:43 +0100268 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100269
Quentin Schulzd242e602017-12-05 15:46:43 +0100270 return pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100271}
272
273static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
274 const unsigned int **pins, unsigned int *num_pins)
275{
Quentin Schulzd242e602017-12-05 15:46:43 +0100276 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100277
Quentin Schulzd242e602017-12-05 15:46:43 +0100278 *pins = (unsigned int *)&pctl->desc->pins[selector];
Quentin Schulz23f75d72017-12-05 15:46:41 +0100279 *num_pins = 1;
280
281 return 0;
282}
283
284static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
285 unsigned int selector)
286{
Quentin Schulzd242e602017-12-05 15:46:43 +0100287 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100288
Quentin Schulzd242e602017-12-05 15:46:43 +0100289 return pctl->desc->pins[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100290}
291
292static const struct pinctrl_ops axp20x_pctrl_ops = {
293 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
294 .dt_free_map = pinconf_generic_dt_free_map,
295 .get_groups_count = axp20x_groups_cnt,
296 .get_group_name = axp20x_group_name,
297 .get_group_pins = axp20x_group_pins,
298};
299
300static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
301 unsigned int mask_len,
302 struct axp20x_pinctrl_function *func,
303 const struct pinctrl_pin_desc *pins)
304{
305 unsigned long int mask_cpy = mask;
306 const char **group;
307 unsigned int ngroups = hweight8(mask);
308 int bit;
309
310 func->ngroups = ngroups;
311 if (func->ngroups > 0) {
312 func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *),
313 GFP_KERNEL);
314 group = func->groups;
315 for_each_set_bit(bit, &mask_cpy, mask_len) {
316 *group = pins[bit].name;
317 group++;
318 }
319 }
320}
321
322static void axp20x_build_funcs_groups(struct platform_device *pdev)
323{
Quentin Schulzd242e602017-12-05 15:46:43 +0100324 struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
325 int i, pin, npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100326
Quentin Schulzd242e602017-12-05 15:46:43 +0100327 pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
328 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
329 pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
330 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
331 pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
Quentin Schulz23f75d72017-12-05 15:46:41 +0100332 /*
333 * Muxval for LDO is useless as we won't use it.
334 * See comment in axp20x_pmx_set_mux.
335 */
Quentin Schulzd242e602017-12-05 15:46:43 +0100336 pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
337 pctl->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100338
339 /* Every pin supports GPIO_OUT and GPIO_IN functions */
340 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
Quentin Schulzd242e602017-12-05 15:46:43 +0100341 pctl->funcs[i].ngroups = npins;
342 pctl->funcs[i].groups = devm_kzalloc(&pdev->dev,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100343 npins * sizeof(char *),
344 GFP_KERNEL);
345 for (pin = 0; pin < npins; pin++)
Quentin Schulzd242e602017-12-05 15:46:43 +0100346 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100347 }
348
Quentin Schulzd242e602017-12-05 15:46:43 +0100349 axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
350 npins, &pctl->funcs[AXP20X_FUNC_LDO],
351 pctl->desc->pins);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100352
Quentin Schulzd242e602017-12-05 15:46:43 +0100353 axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
354 npins, &pctl->funcs[AXP20X_FUNC_ADC],
355 pctl->desc->pins);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200356}
357
Quentin Schulzd242e602017-12-05 15:46:43 +0100358static int axp20x_pctl_probe(struct platform_device *pdev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200359{
360 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Quentin Schulzd242e602017-12-05 15:46:43 +0100361 struct axp20x_pctl *pctl;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100362 struct pinctrl_desc *pctrl_desc;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200363 int ret;
364
365 if (!of_device_is_available(pdev->dev.of_node))
366 return -ENODEV;
367
368 if (!axp20x) {
369 dev_err(&pdev->dev, "Parent drvdata not set\n");
370 return -EINVAL;
371 }
372
Quentin Schulzd242e602017-12-05 15:46:43 +0100373 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
374 if (!pctl)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200375 return -ENOMEM;
376
Quentin Schulzd242e602017-12-05 15:46:43 +0100377 pctl->chip.base = -1;
378 pctl->chip.can_sleep = true;
379 pctl->chip.request = gpiochip_generic_request;
380 pctl->chip.free = gpiochip_generic_free;
381 pctl->chip.parent = &pdev->dev;
382 pctl->chip.label = dev_name(&pdev->dev);
383 pctl->chip.owner = THIS_MODULE;
384 pctl->chip.get = axp20x_gpio_get;
385 pctl->chip.get_direction = axp20x_gpio_get_direction;
386 pctl->chip.set = axp20x_gpio_set;
387 pctl->chip.direction_input = axp20x_gpio_input;
388 pctl->chip.direction_output = axp20x_gpio_output;
389 pctl->chip.ngpio = 3;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200390
Quentin Schulzd242e602017-12-05 15:46:43 +0100391 pctl->desc = &axp20x_data;
392 pctl->regmap = axp20x->regmap;
393 pctl->dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100394
Quentin Schulzd242e602017-12-05 15:46:43 +0100395 platform_set_drvdata(pdev, pctl);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100396
397 axp20x_build_funcs_groups(pdev);
398
399 pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
400 if (!pctrl_desc)
401 return -ENOMEM;
402
403 pctrl_desc->name = dev_name(&pdev->dev);
404 pctrl_desc->owner = THIS_MODULE;
Quentin Schulzd242e602017-12-05 15:46:43 +0100405 pctrl_desc->pins = pctl->desc->pins;
406 pctrl_desc->npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100407 pctrl_desc->pctlops = &axp20x_pctrl_ops;
408 pctrl_desc->pmxops = &axp20x_pmx_ops;
409
Quentin Schulzd242e602017-12-05 15:46:43 +0100410 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
411 if (IS_ERR(pctl->pctl_dev)) {
Quentin Schulz23f75d72017-12-05 15:46:41 +0100412 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
Quentin Schulzd242e602017-12-05 15:46:43 +0100413 return PTR_ERR(pctl->pctl_dev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100414 }
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200415
Quentin Schulzd242e602017-12-05 15:46:43 +0100416 ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200417 if (ret) {
418 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
419 return ret;
420 }
421
Quentin Schulzd242e602017-12-05 15:46:43 +0100422 ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
423 pctl->desc->pins->number,
424 pctl->desc->pins->number,
425 pctl->desc->npins);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100426 if (ret) {
427 dev_err(&pdev->dev, "failed to add pin range\n");
428 return ret;
429 }
430
431 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200432
433 return 0;
434}
435
Quentin Schulzd242e602017-12-05 15:46:43 +0100436static const struct of_device_id axp20x_pctl_match[] = {
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200437 { .compatible = "x-powers,axp209-gpio" },
438 { }
439};
Quentin Schulzd242e602017-12-05 15:46:43 +0100440MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200441
Quentin Schulzd242e602017-12-05 15:46:43 +0100442static struct platform_driver axp20x_pctl_driver = {
443 .probe = axp20x_pctl_probe,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200444 .driver = {
445 .name = "axp20x-gpio",
Quentin Schulzd242e602017-12-05 15:46:43 +0100446 .of_match_table = axp20x_pctl_match,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200447 },
448};
449
Quentin Schulzd242e602017-12-05 15:46:43 +0100450module_platform_driver(axp20x_pctl_driver);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200451
452MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Quentin Schulz23f75d72017-12-05 15:46:41 +0100453MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
454MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200455MODULE_LICENSE("GPL");