Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 1 | /* |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 2 | * AXP20x pinctrl and GPIO driver |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 5 | * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com> |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/bitops.h> |
| 14 | #include <linux/device.h> |
| 15 | #include <linux/gpio/driver.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/mfd/axp20x.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 22 | #include <linux/pinctrl/pinconf-generic.h> |
| 23 | #include <linux/pinctrl/pinctrl.h> |
| 24 | #include <linux/pinctrl/pinmux.h> |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/regmap.h> |
| 27 | #include <linux/slab.h> |
| 28 | |
| 29 | #define AXP20X_GPIO_FUNCTIONS 0x7 |
| 30 | #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 |
| 31 | #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 |
| 32 | #define AXP20X_GPIO_FUNCTION_INPUT 2 |
| 33 | |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 34 | #define AXP20X_FUNC_GPIO_OUT 0 |
| 35 | #define AXP20X_FUNC_GPIO_IN 1 |
| 36 | #define AXP20X_FUNC_LDO 2 |
| 37 | #define AXP20X_FUNC_ADC 3 |
| 38 | #define AXP20X_FUNCS_NB 4 |
| 39 | |
| 40 | #define AXP20X_MUX_GPIO_OUT 0 |
| 41 | #define AXP20X_MUX_GPIO_IN BIT(1) |
| 42 | #define AXP20X_MUX_ADC BIT(2) |
| 43 | |
| 44 | struct axp20x_pctrl_desc { |
| 45 | const struct pinctrl_pin_desc *pins; |
| 46 | unsigned int npins; |
| 47 | /* Stores the pins supporting LDO function. Bit offset is pin number. */ |
| 48 | u8 ldo_mask; |
| 49 | /* Stores the pins supporting ADC function. Bit offset is pin number. */ |
| 50 | u8 adc_mask; |
Quentin Schulz | 48e706f | 2017-12-05 15:46:44 +0100 | [diff] [blame^] | 51 | u8 gpio_status_offset; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | struct axp20x_pinctrl_function { |
| 55 | const char *name; |
| 56 | unsigned int muxval; |
| 57 | const char **groups; |
| 58 | unsigned int ngroups; |
| 59 | }; |
| 60 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 61 | struct axp20x_pctl { |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 62 | struct gpio_chip chip; |
| 63 | struct regmap *regmap; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 64 | struct pinctrl_dev *pctl_dev; |
| 65 | struct device *dev; |
| 66 | const struct axp20x_pctrl_desc *desc; |
| 67 | struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB]; |
| 68 | }; |
| 69 | |
| 70 | static const struct pinctrl_pin_desc axp209_pins[] = { |
| 71 | PINCTRL_PIN(0, "GPIO0"), |
| 72 | PINCTRL_PIN(1, "GPIO1"), |
| 73 | PINCTRL_PIN(2, "GPIO2"), |
| 74 | }; |
| 75 | |
| 76 | static const struct axp20x_pctrl_desc axp20x_data = { |
| 77 | .pins = axp209_pins, |
| 78 | .npins = ARRAY_SIZE(axp209_pins), |
| 79 | .ldo_mask = BIT(0) | BIT(1), |
| 80 | .adc_mask = BIT(0) | BIT(1), |
Quentin Schulz | 48e706f | 2017-12-05 15:46:44 +0100 | [diff] [blame^] | 81 | .gpio_status_offset = 4, |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 82 | }; |
| 83 | |
Quentin Schulz | 3cac991 | 2017-12-05 15:46:39 +0100 | [diff] [blame] | 84 | static int axp20x_gpio_get_reg(unsigned int offset) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 85 | { |
| 86 | switch (offset) { |
| 87 | case 0: |
| 88 | return AXP20X_GPIO0_CTRL; |
| 89 | case 1: |
| 90 | return AXP20X_GPIO1_CTRL; |
| 91 | case 2: |
| 92 | return AXP20X_GPIO2_CTRL; |
| 93 | } |
| 94 | |
| 95 | return -EINVAL; |
| 96 | } |
| 97 | |
Quentin Schulz | 3cac991 | 2017-12-05 15:46:39 +0100 | [diff] [blame] | 98 | static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 99 | { |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 100 | return pinctrl_gpio_direction_input(chip->base + offset); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 101 | } |
| 102 | |
Quentin Schulz | 3cac991 | 2017-12-05 15:46:39 +0100 | [diff] [blame] | 103 | static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 104 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 105 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 106 | unsigned int val; |
Quentin Schulz | 1d2b2ac | 2016-11-23 15:11:50 +0100 | [diff] [blame] | 107 | int ret; |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 108 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 109 | ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 110 | if (ret) |
| 111 | return ret; |
| 112 | |
Quentin Schulz | 48e706f | 2017-12-05 15:46:44 +0100 | [diff] [blame^] | 113 | return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 114 | } |
| 115 | |
Quentin Schulz | 3cac991 | 2017-12-05 15:46:39 +0100 | [diff] [blame] | 116 | static int axp20x_gpio_get_direction(struct gpio_chip *chip, |
| 117 | unsigned int offset) |
Maxime Ripard | 81d3753 | 2016-09-21 23:51:22 +0300 | [diff] [blame] | 118 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 119 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
Maxime Ripard | 81d3753 | 2016-09-21 23:51:22 +0300 | [diff] [blame] | 120 | unsigned int val; |
| 121 | int reg, ret; |
| 122 | |
| 123 | reg = axp20x_gpio_get_reg(offset); |
| 124 | if (reg < 0) |
| 125 | return reg; |
| 126 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 127 | ret = regmap_read(pctl->regmap, reg, &val); |
Maxime Ripard | 81d3753 | 2016-09-21 23:51:22 +0300 | [diff] [blame] | 128 | if (ret) |
| 129 | return ret; |
| 130 | |
| 131 | /* |
| 132 | * This shouldn't really happen if the pin is in use already, |
| 133 | * or if it's not in use yet, it doesn't matter since we're |
| 134 | * going to change the value soon anyway. Default to output. |
| 135 | */ |
| 136 | if ((val & AXP20X_GPIO_FUNCTIONS) > 2) |
| 137 | return 0; |
| 138 | |
| 139 | /* |
| 140 | * The GPIO directions are the three lowest values. |
| 141 | * 2 is input, 0 and 1 are output |
| 142 | */ |
| 143 | return val & 2; |
| 144 | } |
| 145 | |
Quentin Schulz | 3cac991 | 2017-12-05 15:46:39 +0100 | [diff] [blame] | 146 | static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset, |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 147 | int value) |
| 148 | { |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 149 | chip->set(chip, offset, value); |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset, |
| 155 | int value) |
| 156 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 157 | struct axp20x_pctl *pctl = gpiochip_get_data(chip); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 158 | int reg; |
| 159 | |
| 160 | reg = axp20x_gpio_get_reg(offset); |
| 161 | if (reg < 0) |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 162 | return; |
| 163 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 164 | regmap_update_bits(pctl->regmap, reg, |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 165 | AXP20X_GPIO_FUNCTIONS, |
| 166 | value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : |
| 167 | AXP20X_GPIO_FUNCTION_OUT_LOW); |
| 168 | } |
| 169 | |
| 170 | static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, |
| 171 | u8 config) |
| 172 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 173 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 174 | int reg; |
| 175 | |
| 176 | reg = axp20x_gpio_get_reg(offset); |
| 177 | if (reg < 0) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 178 | return reg; |
| 179 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 180 | return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 181 | config); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 182 | } |
| 183 | |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 184 | static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 185 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 186 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 187 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 188 | return ARRAY_SIZE(pctl->funcs); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev, |
| 192 | unsigned int selector) |
| 193 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 194 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 195 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 196 | return pctl->funcs[selector].name; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev, |
| 200 | unsigned int selector, |
| 201 | const char * const **groups, |
| 202 | unsigned int *num_groups) |
| 203 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 204 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 205 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 206 | *groups = pctl->funcs[selector].groups; |
| 207 | *num_groups = pctl->funcs[selector].ngroups; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev, |
| 213 | unsigned int function, unsigned int group) |
| 214 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 215 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 216 | unsigned int mask; |
| 217 | |
| 218 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ |
| 219 | if (function <= AXP20X_FUNC_GPIO_IN) |
| 220 | return axp20x_pmx_set(pctldev, group, |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 221 | pctl->funcs[function].muxval); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 222 | |
| 223 | if (function == AXP20X_FUNC_LDO) |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 224 | mask = pctl->desc->ldo_mask; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 225 | else |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 226 | mask = pctl->desc->adc_mask; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 227 | |
| 228 | if (!(BIT(group) & mask)) |
| 229 | return -EINVAL; |
| 230 | |
| 231 | /* |
| 232 | * We let the regulator framework handle the LDO muxing as muxing bits |
| 233 | * are basically also regulators on/off bits. It's better not to enforce |
| 234 | * any state of the regulator when selecting LDO mux so that we don't |
| 235 | * interfere with the regulator driver. |
| 236 | */ |
| 237 | if (function == AXP20X_FUNC_LDO) |
| 238 | return 0; |
| 239 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 240 | return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 244 | struct pinctrl_gpio_range *range, |
| 245 | unsigned int offset, bool input) |
| 246 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 247 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 248 | |
| 249 | if (input) |
| 250 | return axp20x_pmx_set(pctldev, offset, |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 251 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 252 | |
| 253 | return axp20x_pmx_set(pctldev, offset, |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 254 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static const struct pinmux_ops axp20x_pmx_ops = { |
| 258 | .get_functions_count = axp20x_pmx_func_cnt, |
| 259 | .get_function_name = axp20x_pmx_func_name, |
| 260 | .get_function_groups = axp20x_pmx_func_groups, |
| 261 | .set_mux = axp20x_pmx_set_mux, |
| 262 | .gpio_set_direction = axp20x_pmx_gpio_set_direction, |
| 263 | .strict = true, |
| 264 | }; |
| 265 | |
| 266 | static int axp20x_groups_cnt(struct pinctrl_dev *pctldev) |
| 267 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 268 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 269 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 270 | return pctl->desc->npins; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, |
| 274 | const unsigned int **pins, unsigned int *num_pins) |
| 275 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 276 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 277 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 278 | *pins = (unsigned int *)&pctl->desc->pins[selector]; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 279 | *num_pins = 1; |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | static const char *axp20x_group_name(struct pinctrl_dev *pctldev, |
| 285 | unsigned int selector) |
| 286 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 287 | struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 288 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 289 | return pctl->desc->pins[selector].name; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static const struct pinctrl_ops axp20x_pctrl_ops = { |
| 293 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
| 294 | .dt_free_map = pinconf_generic_dt_free_map, |
| 295 | .get_groups_count = axp20x_groups_cnt, |
| 296 | .get_group_name = axp20x_group_name, |
| 297 | .get_group_pins = axp20x_group_pins, |
| 298 | }; |
| 299 | |
| 300 | static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, |
| 301 | unsigned int mask_len, |
| 302 | struct axp20x_pinctrl_function *func, |
| 303 | const struct pinctrl_pin_desc *pins) |
| 304 | { |
| 305 | unsigned long int mask_cpy = mask; |
| 306 | const char **group; |
| 307 | unsigned int ngroups = hweight8(mask); |
| 308 | int bit; |
| 309 | |
| 310 | func->ngroups = ngroups; |
| 311 | if (func->ngroups > 0) { |
| 312 | func->groups = devm_kzalloc(dev, ngroups * sizeof(const char *), |
| 313 | GFP_KERNEL); |
| 314 | group = func->groups; |
| 315 | for_each_set_bit(bit, &mask_cpy, mask_len) { |
| 316 | *group = pins[bit].name; |
| 317 | group++; |
| 318 | } |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | static void axp20x_build_funcs_groups(struct platform_device *pdev) |
| 323 | { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 324 | struct axp20x_pctl *pctl = platform_get_drvdata(pdev); |
| 325 | int i, pin, npins = pctl->desc->npins; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 326 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 327 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out"; |
| 328 | pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT; |
| 329 | pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in"; |
| 330 | pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN; |
| 331 | pctl->funcs[AXP20X_FUNC_LDO].name = "ldo"; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 332 | /* |
| 333 | * Muxval for LDO is useless as we won't use it. |
| 334 | * See comment in axp20x_pmx_set_mux. |
| 335 | */ |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 336 | pctl->funcs[AXP20X_FUNC_ADC].name = "adc"; |
| 337 | pctl->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 338 | |
| 339 | /* Every pin supports GPIO_OUT and GPIO_IN functions */ |
| 340 | for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) { |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 341 | pctl->funcs[i].ngroups = npins; |
| 342 | pctl->funcs[i].groups = devm_kzalloc(&pdev->dev, |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 343 | npins * sizeof(char *), |
| 344 | GFP_KERNEL); |
| 345 | for (pin = 0; pin < npins; pin++) |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 346 | pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 347 | } |
| 348 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 349 | axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask, |
| 350 | npins, &pctl->funcs[AXP20X_FUNC_LDO], |
| 351 | pctl->desc->pins); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 352 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 353 | axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask, |
| 354 | npins, &pctl->funcs[AXP20X_FUNC_ADC], |
| 355 | pctl->desc->pins); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 356 | } |
| 357 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 358 | static int axp20x_pctl_probe(struct platform_device *pdev) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 359 | { |
| 360 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 361 | struct axp20x_pctl *pctl; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 362 | struct pinctrl_desc *pctrl_desc; |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 363 | int ret; |
| 364 | |
| 365 | if (!of_device_is_available(pdev->dev.of_node)) |
| 366 | return -ENODEV; |
| 367 | |
| 368 | if (!axp20x) { |
| 369 | dev_err(&pdev->dev, "Parent drvdata not set\n"); |
| 370 | return -EINVAL; |
| 371 | } |
| 372 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 373 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
| 374 | if (!pctl) |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 375 | return -ENOMEM; |
| 376 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 377 | pctl->chip.base = -1; |
| 378 | pctl->chip.can_sleep = true; |
| 379 | pctl->chip.request = gpiochip_generic_request; |
| 380 | pctl->chip.free = gpiochip_generic_free; |
| 381 | pctl->chip.parent = &pdev->dev; |
| 382 | pctl->chip.label = dev_name(&pdev->dev); |
| 383 | pctl->chip.owner = THIS_MODULE; |
| 384 | pctl->chip.get = axp20x_gpio_get; |
| 385 | pctl->chip.get_direction = axp20x_gpio_get_direction; |
| 386 | pctl->chip.set = axp20x_gpio_set; |
| 387 | pctl->chip.direction_input = axp20x_gpio_input; |
| 388 | pctl->chip.direction_output = axp20x_gpio_output; |
| 389 | pctl->chip.ngpio = 3; |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 390 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 391 | pctl->desc = &axp20x_data; |
| 392 | pctl->regmap = axp20x->regmap; |
| 393 | pctl->dev = &pdev->dev; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 394 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 395 | platform_set_drvdata(pdev, pctl); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 396 | |
| 397 | axp20x_build_funcs_groups(pdev); |
| 398 | |
| 399 | pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); |
| 400 | if (!pctrl_desc) |
| 401 | return -ENOMEM; |
| 402 | |
| 403 | pctrl_desc->name = dev_name(&pdev->dev); |
| 404 | pctrl_desc->owner = THIS_MODULE; |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 405 | pctrl_desc->pins = pctl->desc->pins; |
| 406 | pctrl_desc->npins = pctl->desc->npins; |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 407 | pctrl_desc->pctlops = &axp20x_pctrl_ops; |
| 408 | pctrl_desc->pmxops = &axp20x_pmx_ops; |
| 409 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 410 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); |
| 411 | if (IS_ERR(pctl->pctl_dev)) { |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 412 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 413 | return PTR_ERR(pctl->pctl_dev); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 414 | } |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 415 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 416 | ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 417 | if (ret) { |
| 418 | dev_err(&pdev->dev, "Failed to register GPIO chip\n"); |
| 419 | return ret; |
| 420 | } |
| 421 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 422 | ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev), |
| 423 | pctl->desc->pins->number, |
| 424 | pctl->desc->pins->number, |
| 425 | pctl->desc->npins); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 426 | if (ret) { |
| 427 | dev_err(&pdev->dev, "failed to add pin range\n"); |
| 428 | return ret; |
| 429 | } |
| 430 | |
| 431 | dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n"); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 436 | static const struct of_device_id axp20x_pctl_match[] = { |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 437 | { .compatible = "x-powers,axp209-gpio" }, |
| 438 | { } |
| 439 | }; |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 440 | MODULE_DEVICE_TABLE(of, axp20x_pctl_match); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 441 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 442 | static struct platform_driver axp20x_pctl_driver = { |
| 443 | .probe = axp20x_pctl_probe, |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 444 | .driver = { |
| 445 | .name = "axp20x-gpio", |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 446 | .of_match_table = axp20x_pctl_match, |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 447 | }, |
| 448 | }; |
| 449 | |
Quentin Schulz | d242e60 | 2017-12-05 15:46:43 +0100 | [diff] [blame] | 450 | module_platform_driver(axp20x_pctl_driver); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 451 | |
| 452 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |
Quentin Schulz | 23f75d7 | 2017-12-05 15:46:41 +0100 | [diff] [blame] | 453 | MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>"); |
| 454 | MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver"); |
Maxime Ripard | f72f4b4 | 2016-07-20 16:11:36 +0200 | [diff] [blame] | 455 | MODULE_LICENSE("GPL"); |