Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Avionic Design GmbH |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 4 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 7 | #include <linux/bitops.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 8 | #include <linux/host1x.h> |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 9 | #include <linux/idr.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 10 | #include <linux/iommu.h> |
Sam Ravnborg | eb1df69 | 2019-08-04 11:41:30 +0200 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/platform_device.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 13 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 14 | #include <drm/drm_atomic.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 15 | #include <drm/drm_atomic_helper.h> |
Sam Ravnborg | eb1df69 | 2019-08-04 11:41:30 +0200 | [diff] [blame] | 16 | #include <drm/drm_debugfs.h> |
| 17 | #include <drm/drm_drv.h> |
| 18 | #include <drm/drm_fourcc.h> |
| 19 | #include <drm/drm_ioctl.h> |
| 20 | #include <drm/drm_prime.h> |
| 21 | #include <drm/drm_vblank.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 22 | |
Dmitry Osipenko | 5ac93f81 | 2018-08-19 17:24:20 +0300 | [diff] [blame] | 23 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 24 | #include <asm/dma-iommu.h> |
| 25 | #endif |
| 26 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 27 | #include "drm.h" |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 28 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 29 | |
| 30 | #define DRIVER_NAME "tegra" |
| 31 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 32 | #define DRIVER_DATE "20120330" |
| 33 | #define DRIVER_MAJOR 0 |
| 34 | #define DRIVER_MINOR 0 |
| 35 | #define DRIVER_PATCHLEVEL 0 |
| 36 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 37 | #define CARVEOUT_SZ SZ_64M |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 38 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 39 | |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 40 | struct tegra_drm_file { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 41 | struct idr contexts; |
| 42 | struct mutex lock; |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 43 | }; |
| 44 | |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 45 | static int tegra_atomic_check(struct drm_device *drm, |
| 46 | struct drm_atomic_state *state) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 47 | { |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 48 | int err; |
| 49 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 50 | err = drm_atomic_helper_check(drm, state); |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 51 | if (err < 0) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 52 | return err; |
| 53 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 54 | return tegra_display_hub_atomic_check(drm, state); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 55 | } |
| 56 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 57 | static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 58 | .fb_create = tegra_fb_create, |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 59 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 60 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 61 | #endif |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 62 | .atomic_check = tegra_atomic_check, |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 63 | .atomic_commit = drm_atomic_helper_commit, |
| 64 | }; |
| 65 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 66 | static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) |
| 67 | { |
| 68 | struct drm_device *drm = old_state->dev; |
| 69 | struct tegra_drm *tegra = drm->dev_private; |
| 70 | |
| 71 | if (tegra->hub) { |
| 72 | drm_atomic_helper_commit_modeset_disables(drm, old_state); |
| 73 | tegra_display_hub_atomic_commit(drm, old_state); |
| 74 | drm_atomic_helper_commit_planes(drm, old_state, 0); |
| 75 | drm_atomic_helper_commit_modeset_enables(drm, old_state); |
| 76 | drm_atomic_helper_commit_hw_done(old_state); |
| 77 | drm_atomic_helper_wait_for_vblanks(drm, old_state); |
| 78 | drm_atomic_helper_cleanup_planes(drm, old_state); |
| 79 | } else { |
| 80 | drm_atomic_helper_commit_tail_rpm(old_state); |
| 81 | } |
| 82 | } |
| 83 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 84 | static const struct drm_mode_config_helper_funcs |
| 85 | tegra_drm_mode_config_helpers = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 86 | .atomic_commit_tail = tegra_atomic_commit_tail, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 87 | }; |
| 88 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 89 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 90 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 91 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 92 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 93 | int err; |
| 94 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 95 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 96 | if (!tegra) |
Terje Bergstrom | 692e6d7 | 2013-03-22 16:34:07 +0200 | [diff] [blame] | 97 | return -ENOMEM; |
| 98 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 99 | if (iommu_present(&platform_bus_type)) { |
| 100 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
Dan Carpenter | bf19b88 | 2014-12-04 14:00:35 +0300 | [diff] [blame] | 101 | if (!tegra->domain) { |
| 102 | err = -ENOMEM; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 103 | goto free; |
| 104 | } |
| 105 | |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 106 | err = iova_cache_get(); |
| 107 | if (err < 0) |
| 108 | goto domain; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 109 | } |
| 110 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 111 | mutex_init(&tegra->clients_lock); |
| 112 | INIT_LIST_HEAD(&tegra->clients); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 113 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 114 | drm->dev_private = tegra; |
| 115 | tegra->drm = drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 116 | |
| 117 | drm_mode_config_init(drm); |
| 118 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 119 | drm->mode_config.min_width = 0; |
| 120 | drm->mode_config.min_height = 0; |
| 121 | |
| 122 | drm->mode_config.max_width = 4096; |
| 123 | drm->mode_config.max_height = 4096; |
| 124 | |
Alexandre Courbot | 5e91144 | 2016-11-08 16:50:42 +0900 | [diff] [blame] | 125 | drm->mode_config.allow_fb_modifiers = true; |
| 126 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 127 | drm->mode_config.normalize_zpos = true; |
| 128 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 129 | drm->mode_config.funcs = &tegra_drm_mode_config_funcs; |
| 130 | drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 131 | |
Thierry Reding | e2215321f | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 132 | err = tegra_drm_fb_prepare(drm); |
| 133 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 134 | goto config; |
Thierry Reding | e2215321f | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 135 | |
| 136 | drm_kms_helper_poll_init(drm); |
| 137 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 138 | err = host1x_device_init(device); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 139 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 140 | goto fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 141 | |
Thierry Reding | b9f8b09 | 2019-02-01 14:28:33 +0100 | [diff] [blame] | 142 | if (tegra->domain) { |
| 143 | u64 carveout_start, carveout_end, gem_start, gem_end; |
Thierry Reding | 02be8e4 | 2019-02-01 14:28:34 +0100 | [diff] [blame] | 144 | u64 dma_mask = dma_get_mask(&device->dev); |
Thierry Reding | b9f8b09 | 2019-02-01 14:28:33 +0100 | [diff] [blame] | 145 | dma_addr_t start, end; |
| 146 | unsigned long order; |
| 147 | |
Thierry Reding | 02be8e4 | 2019-02-01 14:28:34 +0100 | [diff] [blame] | 148 | start = tegra->domain->geometry.aperture_start & dma_mask; |
| 149 | end = tegra->domain->geometry.aperture_end & dma_mask; |
Thierry Reding | b9f8b09 | 2019-02-01 14:28:33 +0100 | [diff] [blame] | 150 | |
| 151 | gem_start = start; |
| 152 | gem_end = end - CARVEOUT_SZ; |
| 153 | carveout_start = gem_end + 1; |
| 154 | carveout_end = end; |
| 155 | |
| 156 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 157 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
| 158 | carveout_start >> order); |
| 159 | |
| 160 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 161 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 162 | |
| 163 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
| 164 | mutex_init(&tegra->mm_lock); |
| 165 | |
Thierry Reding | 0301196 | 2019-09-04 13:00:30 +0200 | [diff] [blame] | 166 | DRM_DEBUG_DRIVER("IOMMU apertures:\n"); |
| 167 | DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 168 | DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start, |
| 169 | carveout_end); |
Thierry Reding | b9f8b09 | 2019-02-01 14:28:33 +0100 | [diff] [blame] | 170 | } |
| 171 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 172 | if (tegra->hub) { |
| 173 | err = tegra_display_hub_prepare(tegra->hub); |
| 174 | if (err < 0) |
| 175 | goto device; |
| 176 | } |
| 177 | |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 178 | /* |
| 179 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 180 | * core, so we need to set this manually in order to allow the |
| 181 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 182 | */ |
Ville Syrjälä | 4423843 | 2013-10-04 14:53:37 +0300 | [diff] [blame] | 183 | drm->irq_enabled = true; |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 184 | |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 185 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 186 | drm->max_vblank_count = 0xffffffff; |
| 187 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 188 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 189 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 190 | goto hub; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 191 | |
Thierry Reding | 31930d4 | 2015-07-02 17:04:06 +0200 | [diff] [blame] | 192 | drm_mode_config_reset(drm); |
| 193 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 194 | err = tegra_drm_fb_init(drm); |
| 195 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 196 | goto hub; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 197 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 198 | return 0; |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 199 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 200 | hub: |
| 201 | if (tegra->hub) |
| 202 | tegra_display_hub_cleanup(tegra->hub); |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 203 | device: |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 204 | if (tegra->domain) { |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 205 | mutex_destroy(&tegra->mm_lock); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 206 | drm_mm_takedown(&tegra->mm); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 207 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 208 | iova_cache_put(); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 209 | } |
Thierry Reding | 051172e | 2019-09-25 13:26:59 +0200 | [diff] [blame] | 210 | |
| 211 | host1x_device_exit(device); |
| 212 | fbdev: |
| 213 | drm_kms_helper_poll_fini(drm); |
| 214 | tegra_drm_fb_free(drm); |
| 215 | config: |
| 216 | drm_mode_config_cleanup(drm); |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 217 | domain: |
| 218 | if (tegra->domain) |
| 219 | iommu_domain_free(tegra->domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 220 | free: |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 221 | kfree(tegra); |
| 222 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 223 | } |
| 224 | |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 225 | static void tegra_drm_unload(struct drm_device *drm) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 226 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 227 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 228 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 229 | int err; |
| 230 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 231 | drm_kms_helper_poll_fini(drm); |
| 232 | tegra_drm_fb_exit(drm); |
Thierry Reding | 192b4af | 2018-03-18 01:13:39 +0100 | [diff] [blame] | 233 | drm_atomic_helper_shutdown(drm); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 234 | drm_mode_config_cleanup(drm); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 235 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 236 | err = host1x_device_exit(device); |
| 237 | if (err < 0) |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 238 | return; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 239 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 240 | if (tegra->domain) { |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 241 | mutex_destroy(&tegra->mm_lock); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 242 | drm_mm_takedown(&tegra->mm); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 243 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 244 | iova_cache_put(); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 245 | iommu_domain_free(tegra->domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 246 | } |
| 247 | |
Thierry Reding | 1053f4dd | 2014-11-04 16:17:55 +0100 | [diff] [blame] | 248 | kfree(tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 252 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 253 | struct tegra_drm_file *fpriv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 254 | |
| 255 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 256 | if (!fpriv) |
| 257 | return -ENOMEM; |
| 258 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 259 | idr_init(&fpriv->contexts); |
| 260 | mutex_init(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 261 | filp->driver_priv = fpriv; |
| 262 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 263 | return 0; |
| 264 | } |
| 265 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 266 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 267 | { |
| 268 | context->client->ops->close_channel(context); |
| 269 | kfree(context); |
| 270 | } |
| 271 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 272 | static struct host1x_bo * |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 273 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 274 | { |
| 275 | struct drm_gem_object *gem; |
| 276 | struct tegra_bo *bo; |
| 277 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 278 | gem = drm_gem_object_lookup(file, handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 279 | if (!gem) |
| 280 | return NULL; |
| 281 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 282 | bo = to_tegra_bo(gem); |
| 283 | return &bo->base; |
| 284 | } |
| 285 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 286 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 287 | struct drm_tegra_reloc __user *src, |
| 288 | struct drm_device *drm, |
| 289 | struct drm_file *file) |
| 290 | { |
| 291 | u32 cmdbuf, target; |
| 292 | int err; |
| 293 | |
| 294 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 295 | if (err < 0) |
| 296 | return err; |
| 297 | |
| 298 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 299 | if (err < 0) |
| 300 | return err; |
| 301 | |
| 302 | err = get_user(target, &src->target.handle); |
| 303 | if (err < 0) |
| 304 | return err; |
| 305 | |
David Ung | 31f40f8 | 2015-01-20 18:37:35 -0800 | [diff] [blame] | 306 | err = get_user(dest->target.offset, &src->target.offset); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 307 | if (err < 0) |
| 308 | return err; |
| 309 | |
| 310 | err = get_user(dest->shift, &src->shift); |
| 311 | if (err < 0) |
| 312 | return err; |
| 313 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 314 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 315 | if (!dest->cmdbuf.bo) |
| 316 | return -ENOENT; |
| 317 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 318 | dest->target.bo = host1x_bo_lookup(file, target); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 319 | if (!dest->target.bo) |
| 320 | return -ENOENT; |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 325 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 326 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 327 | struct drm_file *file) |
| 328 | { |
Thierry Reding | bf3d41c | 2018-05-16 14:12:33 +0200 | [diff] [blame] | 329 | struct host1x_client *client = &context->client->base; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 330 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 331 | unsigned int num_relocs = args->num_relocs; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 332 | struct drm_tegra_cmdbuf __user *user_cmdbufs; |
| 333 | struct drm_tegra_reloc __user *user_relocs; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 334 | struct drm_tegra_syncpt __user *user_syncpt; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 335 | struct drm_tegra_syncpt syncpt; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 336 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 337 | struct drm_gem_object **refs; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 338 | struct host1x_syncpt *sp; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 339 | struct host1x_job *job; |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 340 | unsigned int num_refs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 341 | int err; |
| 342 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 343 | user_cmdbufs = u64_to_user_ptr(args->cmdbufs); |
| 344 | user_relocs = u64_to_user_ptr(args->relocs); |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 345 | user_syncpt = u64_to_user_ptr(args->syncpts); |
| 346 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 347 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 348 | if (args->num_syncpts != 1) |
| 349 | return -EINVAL; |
| 350 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 351 | /* We don't yet support waitchks */ |
| 352 | if (args->num_waitchks != 0) |
| 353 | return -EINVAL; |
| 354 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 355 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
Thierry Reding | 24c94e1 | 2018-05-05 08:45:47 +0200 | [diff] [blame] | 356 | args->num_relocs); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 357 | if (!job) |
| 358 | return -ENOMEM; |
| 359 | |
| 360 | job->num_relocs = args->num_relocs; |
Thierry Reding | bf3d41c | 2018-05-16 14:12:33 +0200 | [diff] [blame] | 361 | job->client = client; |
| 362 | job->class = client->class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 363 | job->serialize = true; |
| 364 | |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 365 | /* |
| 366 | * Track referenced BOs so that they can be unreferenced after the |
| 367 | * submission is complete. |
| 368 | */ |
Thierry Reding | 24c94e1 | 2018-05-05 08:45:47 +0200 | [diff] [blame] | 369 | num_refs = num_cmdbufs + num_relocs * 2; |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 370 | |
| 371 | refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); |
| 372 | if (!refs) { |
| 373 | err = -ENOMEM; |
| 374 | goto put; |
| 375 | } |
| 376 | |
| 377 | /* reuse as an iterator later */ |
| 378 | num_refs = 0; |
| 379 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 380 | while (num_cmdbufs) { |
| 381 | struct drm_tegra_cmdbuf cmdbuf; |
| 382 | struct host1x_bo *bo; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 383 | struct tegra_bo *obj; |
| 384 | u64 offset; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 385 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 386 | if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 387 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 388 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 389 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 390 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 391 | /* |
| 392 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 393 | * value means the words count is malformed. |
| 394 | */ |
| 395 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 396 | err = -EINVAL; |
| 397 | goto fail; |
| 398 | } |
| 399 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 400 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 401 | if (!bo) { |
| 402 | err = -ENOENT; |
| 403 | goto fail; |
| 404 | } |
| 405 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 406 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 407 | obj = host1x_to_tegra_bo(bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 408 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 409 | |
| 410 | /* |
| 411 | * Gather buffer base address must be 4-bytes aligned, |
| 412 | * unaligned offset is malformed and cause commands stream |
| 413 | * corruption on the buffer address relocation. |
| 414 | */ |
Mikko Perttunen | 5265f03 | 2018-06-20 16:03:58 +0300 | [diff] [blame] | 415 | if (offset & 3 || offset > obj->gem.size) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 416 | err = -EINVAL; |
| 417 | goto fail; |
| 418 | } |
| 419 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 420 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 421 | num_cmdbufs--; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 422 | user_cmdbufs++; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 423 | } |
| 424 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 425 | /* copy and resolve relocations from submit */ |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 426 | while (num_relocs--) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 427 | struct host1x_reloc *reloc; |
| 428 | struct tegra_bo *obj; |
| 429 | |
Thierry Reding | 06490bb | 2018-05-16 16:58:44 +0200 | [diff] [blame] | 430 | err = host1x_reloc_copy_from_user(&job->relocs[num_relocs], |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 431 | &user_relocs[num_relocs], drm, |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 432 | file); |
| 433 | if (err < 0) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 434 | goto fail; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 435 | |
Thierry Reding | 06490bb | 2018-05-16 16:58:44 +0200 | [diff] [blame] | 436 | reloc = &job->relocs[num_relocs]; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 437 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 438 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 439 | |
| 440 | /* |
| 441 | * The unaligned cmdbuf offset will cause an unaligned write |
| 442 | * during of the relocations patching, corrupting the commands |
| 443 | * stream. |
| 444 | */ |
| 445 | if (reloc->cmdbuf.offset & 3 || |
| 446 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 447 | err = -EINVAL; |
| 448 | goto fail; |
| 449 | } |
| 450 | |
| 451 | obj = host1x_to_tegra_bo(reloc->target.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 452 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 453 | |
| 454 | if (reloc->target.offset >= obj->gem.size) { |
| 455 | err = -EINVAL; |
| 456 | goto fail; |
| 457 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 458 | } |
| 459 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 460 | if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 461 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 462 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 463 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 464 | |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 465 | /* check whether syncpoint ID is valid */ |
| 466 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 467 | if (!sp) { |
| 468 | err = -ENOENT; |
| 469 | goto fail; |
| 470 | } |
| 471 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 472 | job->is_addr_reg = context->client->ops->is_addr_reg; |
Dmitry Osipenko | 0f563a4 | 2017-06-15 02:18:37 +0300 | [diff] [blame] | 473 | job->is_valid_class = context->client->ops->is_valid_class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 474 | job->syncpt_incrs = syncpt.incrs; |
| 475 | job->syncpt_id = syncpt.id; |
| 476 | job->timeout = 10000; |
| 477 | |
| 478 | if (args->timeout && args->timeout < 10000) |
| 479 | job->timeout = args->timeout; |
| 480 | |
| 481 | err = host1x_job_pin(job, context->client->base.dev); |
| 482 | if (err) |
| 483 | goto fail; |
| 484 | |
| 485 | err = host1x_job_submit(job); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 486 | if (err) { |
| 487 | host1x_job_unpin(job); |
| 488 | goto fail; |
| 489 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 490 | |
| 491 | args->fence = job->syncpt_end; |
| 492 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 493 | fail: |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 494 | while (num_refs--) |
| 495 | drm_gem_object_put_unlocked(refs[num_refs]); |
| 496 | |
| 497 | kfree(refs); |
| 498 | |
| 499 | put: |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 500 | host1x_job_put(job); |
| 501 | return err; |
| 502 | } |
| 503 | |
| 504 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 505 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 506 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 507 | struct drm_file *file) |
| 508 | { |
| 509 | struct drm_tegra_gem_create *args = data; |
| 510 | struct tegra_bo *bo; |
| 511 | |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 512 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 513 | &args->handle); |
| 514 | if (IS_ERR(bo)) |
| 515 | return PTR_ERR(bo); |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
| 520 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 521 | struct drm_file *file) |
| 522 | { |
| 523 | struct drm_tegra_gem_mmap *args = data; |
| 524 | struct drm_gem_object *gem; |
| 525 | struct tegra_bo *bo; |
| 526 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 527 | gem = drm_gem_object_lookup(file, args->handle); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 528 | if (!gem) |
| 529 | return -EINVAL; |
| 530 | |
| 531 | bo = to_tegra_bo(gem); |
| 532 | |
David Herrmann | 2bc7b0c | 2013-08-13 14:19:58 +0200 | [diff] [blame] | 533 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 534 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 535 | drm_gem_object_put_unlocked(gem); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 536 | |
| 537 | return 0; |
| 538 | } |
| 539 | |
| 540 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 541 | struct drm_file *file) |
| 542 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 543 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 544 | struct drm_tegra_syncpt_read *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 545 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 546 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 547 | sp = host1x_syncpt_get(host, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 548 | if (!sp) |
| 549 | return -EINVAL; |
| 550 | |
| 551 | args->value = host1x_syncpt_read_min(sp); |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 556 | struct drm_file *file) |
| 557 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 558 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 559 | struct drm_tegra_syncpt_incr *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 560 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 561 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 562 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 563 | if (!sp) |
| 564 | return -EINVAL; |
| 565 | |
Arto Merilainen | ebae30b | 2013-05-29 13:26:08 +0300 | [diff] [blame] | 566 | return host1x_syncpt_incr(sp); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 570 | struct drm_file *file) |
| 571 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 572 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 573 | struct drm_tegra_syncpt_wait *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 574 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 575 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 576 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 577 | if (!sp) |
| 578 | return -EINVAL; |
| 579 | |
Dmitry Osipenko | 4c69ac12 | 2017-12-20 18:46:14 +0300 | [diff] [blame] | 580 | return host1x_syncpt_wait(sp, args->thresh, |
| 581 | msecs_to_jiffies(args->timeout), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 582 | &args->value); |
| 583 | } |
| 584 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 585 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 586 | struct tegra_drm_client *client, |
| 587 | struct tegra_drm_context *context) |
| 588 | { |
| 589 | int err; |
| 590 | |
| 591 | err = client->ops->open_channel(client, context); |
| 592 | if (err < 0) |
| 593 | return err; |
| 594 | |
Dmitry Osipenko | d6c153e | 2017-06-15 02:18:25 +0300 | [diff] [blame] | 595 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 596 | if (err < 0) { |
| 597 | client->ops->close_channel(context); |
| 598 | return err; |
| 599 | } |
| 600 | |
| 601 | context->client = client; |
| 602 | context->id = err; |
| 603 | |
| 604 | return 0; |
| 605 | } |
| 606 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 607 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 608 | struct drm_file *file) |
| 609 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 610 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 611 | struct tegra_drm *tegra = drm->dev_private; |
| 612 | struct drm_tegra_open_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 613 | struct tegra_drm_context *context; |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 614 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 615 | int err = -ENODEV; |
| 616 | |
| 617 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 618 | if (!context) |
| 619 | return -ENOMEM; |
| 620 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 621 | mutex_lock(&fpriv->lock); |
| 622 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 623 | list_for_each_entry(client, &tegra->clients, list) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 624 | if (client->base.class == args->client) { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 625 | err = tegra_client_open(fpriv, client, context); |
| 626 | if (err < 0) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 627 | break; |
| 628 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 629 | args->context = context->id; |
| 630 | break; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 631 | } |
| 632 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 633 | if (err < 0) |
| 634 | kfree(context); |
| 635 | |
| 636 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 637 | return err; |
| 638 | } |
| 639 | |
| 640 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 641 | struct drm_file *file) |
| 642 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 643 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 644 | struct drm_tegra_close_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 645 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 646 | int err = 0; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 647 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 648 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 649 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 650 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 651 | if (!context) { |
| 652 | err = -EINVAL; |
| 653 | goto unlock; |
| 654 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 655 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 656 | idr_remove(&fpriv->contexts, context->id); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 657 | tegra_drm_context_free(context); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 658 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 659 | unlock: |
| 660 | mutex_unlock(&fpriv->lock); |
| 661 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 662 | } |
| 663 | |
| 664 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 665 | struct drm_file *file) |
| 666 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 667 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 668 | struct drm_tegra_get_syncpt *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 669 | struct tegra_drm_context *context; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 670 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 671 | int err = 0; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 672 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 673 | mutex_lock(&fpriv->lock); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 674 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 675 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 676 | if (!context) { |
| 677 | err = -ENODEV; |
| 678 | goto unlock; |
| 679 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 680 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 681 | if (args->index >= context->client->base.num_syncpts) { |
| 682 | err = -EINVAL; |
| 683 | goto unlock; |
| 684 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 685 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 686 | syncpt = context->client->base.syncpts[args->index]; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 687 | args->id = host1x_syncpt_id(syncpt); |
| 688 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 689 | unlock: |
| 690 | mutex_unlock(&fpriv->lock); |
| 691 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | static int tegra_submit(struct drm_device *drm, void *data, |
| 695 | struct drm_file *file) |
| 696 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 697 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 698 | struct drm_tegra_submit *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 699 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 700 | int err; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 701 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 702 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 703 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 704 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 705 | if (!context) { |
| 706 | err = -ENODEV; |
| 707 | goto unlock; |
| 708 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 709 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 710 | err = context->client->ops->submit(context, args, drm, file); |
| 711 | |
| 712 | unlock: |
| 713 | mutex_unlock(&fpriv->lock); |
| 714 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 715 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 716 | |
| 717 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 718 | struct drm_file *file) |
| 719 | { |
| 720 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 721 | struct drm_tegra_get_syncpt_base *args = data; |
| 722 | struct tegra_drm_context *context; |
| 723 | struct host1x_syncpt_base *base; |
| 724 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 725 | int err = 0; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 726 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 727 | mutex_lock(&fpriv->lock); |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 728 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 729 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 730 | if (!context) { |
| 731 | err = -ENODEV; |
| 732 | goto unlock; |
| 733 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 734 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 735 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 736 | err = -EINVAL; |
| 737 | goto unlock; |
| 738 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 739 | |
| 740 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 741 | |
| 742 | base = host1x_syncpt_get_base(syncpt); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 743 | if (!base) { |
| 744 | err = -ENXIO; |
| 745 | goto unlock; |
| 746 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 747 | |
| 748 | args->id = host1x_syncpt_base_id(base); |
| 749 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 750 | unlock: |
| 751 | mutex_unlock(&fpriv->lock); |
| 752 | return err; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 753 | } |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 754 | |
| 755 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 756 | struct drm_file *file) |
| 757 | { |
| 758 | struct drm_tegra_gem_set_tiling *args = data; |
| 759 | enum tegra_bo_tiling_mode mode; |
| 760 | struct drm_gem_object *gem; |
| 761 | unsigned long value = 0; |
| 762 | struct tegra_bo *bo; |
| 763 | |
| 764 | switch (args->mode) { |
| 765 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 766 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 767 | |
| 768 | if (args->value != 0) |
| 769 | return -EINVAL; |
| 770 | |
| 771 | break; |
| 772 | |
| 773 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 774 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 775 | |
| 776 | if (args->value != 0) |
| 777 | return -EINVAL; |
| 778 | |
| 779 | break; |
| 780 | |
| 781 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 782 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 783 | |
| 784 | if (args->value > 5) |
| 785 | return -EINVAL; |
| 786 | |
| 787 | value = args->value; |
| 788 | break; |
| 789 | |
| 790 | default: |
| 791 | return -EINVAL; |
| 792 | } |
| 793 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 794 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 795 | if (!gem) |
| 796 | return -ENOENT; |
| 797 | |
| 798 | bo = to_tegra_bo(gem); |
| 799 | |
| 800 | bo->tiling.mode = mode; |
| 801 | bo->tiling.value = value; |
| 802 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 803 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 804 | |
| 805 | return 0; |
| 806 | } |
| 807 | |
| 808 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 809 | struct drm_file *file) |
| 810 | { |
| 811 | struct drm_tegra_gem_get_tiling *args = data; |
| 812 | struct drm_gem_object *gem; |
| 813 | struct tegra_bo *bo; |
| 814 | int err = 0; |
| 815 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 816 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 817 | if (!gem) |
| 818 | return -ENOENT; |
| 819 | |
| 820 | bo = to_tegra_bo(gem); |
| 821 | |
| 822 | switch (bo->tiling.mode) { |
| 823 | case TEGRA_BO_TILING_MODE_PITCH: |
| 824 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 825 | args->value = 0; |
| 826 | break; |
| 827 | |
| 828 | case TEGRA_BO_TILING_MODE_TILED: |
| 829 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 830 | args->value = 0; |
| 831 | break; |
| 832 | |
| 833 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 834 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 835 | args->value = bo->tiling.value; |
| 836 | break; |
| 837 | |
| 838 | default: |
| 839 | err = -EINVAL; |
| 840 | break; |
| 841 | } |
| 842 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 843 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 844 | |
| 845 | return err; |
| 846 | } |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 847 | |
| 848 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 849 | struct drm_file *file) |
| 850 | { |
| 851 | struct drm_tegra_gem_set_flags *args = data; |
| 852 | struct drm_gem_object *gem; |
| 853 | struct tegra_bo *bo; |
| 854 | |
| 855 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 856 | return -EINVAL; |
| 857 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 858 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 859 | if (!gem) |
| 860 | return -ENOENT; |
| 861 | |
| 862 | bo = to_tegra_bo(gem); |
| 863 | bo->flags = 0; |
| 864 | |
| 865 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 866 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 867 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 868 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 874 | struct drm_file *file) |
| 875 | { |
| 876 | struct drm_tegra_gem_get_flags *args = data; |
| 877 | struct drm_gem_object *gem; |
| 878 | struct tegra_bo *bo; |
| 879 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 880 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 881 | if (!gem) |
| 882 | return -ENOENT; |
| 883 | |
| 884 | bo = to_tegra_bo(gem); |
| 885 | args->flags = 0; |
| 886 | |
| 887 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 888 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 889 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 890 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 891 | |
| 892 | return 0; |
| 893 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 894 | #endif |
| 895 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 896 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 897 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 898 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 899 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 900 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 901 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 902 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 903 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 904 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 905 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 906 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 907 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 908 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 909 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 910 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 911 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 912 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 913 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 914 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 915 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 916 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 917 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 918 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 919 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 920 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 921 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 922 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 923 | DRM_RENDER_ALLOW), |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 924 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, |
Emil Velikov | d6891db | 2019-05-22 16:46:59 +0100 | [diff] [blame] | 925 | DRM_RENDER_ALLOW), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 926 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 927 | }; |
| 928 | |
| 929 | static const struct file_operations tegra_drm_fops = { |
| 930 | .owner = THIS_MODULE, |
| 931 | .open = drm_open, |
| 932 | .release = drm_release, |
| 933 | .unlocked_ioctl = drm_ioctl, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 934 | .mmap = tegra_drm_mmap, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 935 | .poll = drm_poll, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 936 | .read = drm_read, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 937 | .compat_ioctl = drm_compat_ioctl, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 938 | .llseek = noop_llseek, |
| 939 | }; |
| 940 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 941 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 942 | { |
| 943 | struct tegra_drm_context *context = p; |
| 944 | |
| 945 | tegra_drm_context_free(context); |
| 946 | |
| 947 | return 0; |
| 948 | } |
| 949 | |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 950 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 951 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 952 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 953 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 954 | mutex_lock(&fpriv->lock); |
| 955 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 956 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 957 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 958 | idr_destroy(&fpriv->contexts); |
| 959 | mutex_destroy(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 960 | kfree(fpriv); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 961 | } |
| 962 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 963 | #ifdef CONFIG_DEBUG_FS |
| 964 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 965 | { |
| 966 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 967 | struct drm_device *drm = node->minor->dev; |
| 968 | struct drm_framebuffer *fb; |
| 969 | |
| 970 | mutex_lock(&drm->mode_config.fb_lock); |
| 971 | |
| 972 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 973 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 974 | fb->base.id, fb->width, fb->height, |
| 975 | fb->format->depth, |
Ville Syrjälä | 272725c | 2016-12-14 23:32:20 +0200 | [diff] [blame] | 976 | fb->format->cpp[0] * 8, |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 977 | drm_framebuffer_read_refcount(fb)); |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | mutex_unlock(&drm->mode_config.fb_lock); |
| 981 | |
| 982 | return 0; |
| 983 | } |
| 984 | |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 985 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 986 | { |
| 987 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 988 | struct drm_device *drm = node->minor->dev; |
| 989 | struct tegra_drm *tegra = drm->dev_private; |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 990 | struct drm_printer p = drm_seq_file_printer(s); |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 991 | |
Michał Mirosław | 68d890a | 2017-08-14 23:53:45 +0200 | [diff] [blame] | 992 | if (tegra->domain) { |
| 993 | mutex_lock(&tegra->mm_lock); |
| 994 | drm_mm_print(&tegra->mm, &p); |
| 995 | mutex_unlock(&tegra->mm_lock); |
| 996 | } |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 997 | |
| 998 | return 0; |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 999 | } |
| 1000 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1001 | static struct drm_info_list tegra_debugfs_list[] = { |
| 1002 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1003 | { "iova", tegra_debugfs_iova, 0 }, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1004 | }; |
| 1005 | |
| 1006 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1007 | { |
| 1008 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1009 | ARRAY_SIZE(tegra_debugfs_list), |
| 1010 | minor->debugfs_root, minor); |
| 1011 | } |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1012 | #endif |
| 1013 | |
Thierry Reding | 9b57f5f | 2013-11-08 13:17:14 +0100 | [diff] [blame] | 1014 | static struct drm_driver tegra_drm_driver = { |
Daniel Vetter | 0424fda | 2019-06-17 17:39:24 +0200 | [diff] [blame] | 1015 | .driver_features = DRIVER_MODESET | DRIVER_GEM | |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 1016 | DRIVER_ATOMIC | DRIVER_RENDER, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1017 | .load = tegra_drm_load, |
| 1018 | .unload = tegra_drm_unload, |
| 1019 | .open = tegra_drm_open, |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 1020 | .postclose = tegra_drm_postclose, |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 1021 | .lastclose = drm_fb_helper_lastclose, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1022 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1023 | #if defined(CONFIG_DEBUG_FS) |
| 1024 | .debugfs_init = tegra_debugfs_init, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1025 | #endif |
| 1026 | |
Daniel Vetter | 1ddbdbd | 2016-04-26 19:30:00 +0200 | [diff] [blame] | 1027 | .gem_free_object_unlocked = tegra_bo_free_object, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1028 | .gem_vm_ops = &tegra_bo_vm_ops, |
Thierry Reding | 3800391 | 2013-12-12 10:00:43 +0100 | [diff] [blame] | 1029 | |
| 1030 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1031 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1032 | .gem_prime_export = tegra_gem_prime_export, |
| 1033 | .gem_prime_import = tegra_gem_prime_import, |
| 1034 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1035 | .dumb_create = tegra_bo_dumb_create, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1036 | |
| 1037 | .ioctls = tegra_drm_ioctls, |
| 1038 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1039 | .fops = &tegra_drm_fops, |
| 1040 | |
| 1041 | .name = DRIVER_NAME, |
| 1042 | .desc = DRIVER_DESC, |
| 1043 | .date = DRIVER_DATE, |
| 1044 | .major = DRIVER_MAJOR, |
| 1045 | .minor = DRIVER_MINOR, |
| 1046 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1047 | }; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1048 | |
| 1049 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1050 | struct tegra_drm_client *client) |
| 1051 | { |
| 1052 | mutex_lock(&tegra->clients_lock); |
| 1053 | list_add_tail(&client->list, &tegra->clients); |
Thierry Reding | 8e5d19c | 2019-02-01 14:28:31 +0100 | [diff] [blame] | 1054 | client->drm = tegra; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1055 | mutex_unlock(&tegra->clients_lock); |
| 1056 | |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1061 | struct tegra_drm_client *client) |
| 1062 | { |
| 1063 | mutex_lock(&tegra->clients_lock); |
| 1064 | list_del_init(&client->list); |
Thierry Reding | 8e5d19c | 2019-02-01 14:28:31 +0100 | [diff] [blame] | 1065 | client->drm = NULL; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1066 | mutex_unlock(&tegra->clients_lock); |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1071 | int host1x_client_iommu_attach(struct host1x_client *client, bool shared) |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1072 | { |
| 1073 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1074 | struct tegra_drm *tegra = drm->dev_private; |
| 1075 | struct iommu_group *group = NULL; |
| 1076 | int err; |
| 1077 | |
| 1078 | if (tegra->domain) { |
| 1079 | group = iommu_group_get(client->dev); |
| 1080 | if (!group) { |
| 1081 | dev_err(client->dev, "failed to get IOMMU group\n"); |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1082 | return -ENODEV; |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1083 | } |
| 1084 | |
| 1085 | if (!shared || (shared && (group != tegra->group))) { |
Dmitry Osipenko | 5ac93f81 | 2018-08-19 17:24:20 +0300 | [diff] [blame] | 1086 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 1087 | if (client->dev->archdata.mapping) { |
| 1088 | struct dma_iommu_mapping *mapping = |
| 1089 | to_dma_iommu_mapping(client->dev); |
| 1090 | arm_iommu_detach_device(client->dev); |
| 1091 | arm_iommu_release_mapping(mapping); |
| 1092 | } |
| 1093 | #endif |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1094 | err = iommu_attach_group(tegra->domain, group); |
| 1095 | if (err < 0) { |
| 1096 | iommu_group_put(group); |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1097 | return err; |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | if (shared && !tegra->group) |
| 1101 | tegra->group = group; |
| 1102 | } |
| 1103 | } |
| 1104 | |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1105 | client->group = group; |
| 1106 | |
| 1107 | return 0; |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1108 | } |
| 1109 | |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1110 | void host1x_client_iommu_detach(struct host1x_client *client) |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1111 | { |
| 1112 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1113 | struct tegra_drm *tegra = drm->dev_private; |
| 1114 | |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1115 | if (client->group) { |
| 1116 | if (client->group == tegra->group) { |
| 1117 | iommu_detach_group(tegra->domain, client->group); |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1118 | tegra->group = NULL; |
| 1119 | } |
| 1120 | |
Thierry Reding | aacdf19 | 2019-02-08 14:35:13 +0100 | [diff] [blame^] | 1121 | iommu_group_put(client->group); |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1122 | } |
| 1123 | } |
| 1124 | |
Thierry Reding | 67485fb | 2017-11-09 13:17:11 +0100 | [diff] [blame] | 1125 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 1126 | { |
| 1127 | struct iova *alloc; |
| 1128 | void *virt; |
| 1129 | gfp_t gfp; |
| 1130 | int err; |
| 1131 | |
| 1132 | if (tegra->domain) |
| 1133 | size = iova_align(&tegra->carveout.domain, size); |
| 1134 | else |
| 1135 | size = PAGE_ALIGN(size); |
| 1136 | |
| 1137 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1138 | if (!tegra->domain) { |
| 1139 | /* |
| 1140 | * Many units only support 32-bit addresses, even on 64-bit |
| 1141 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1142 | * virtual address space, force allocations to be in the |
| 1143 | * lower 32-bit range. |
| 1144 | */ |
| 1145 | gfp |= GFP_DMA; |
| 1146 | } |
| 1147 | |
| 1148 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1149 | if (!virt) |
| 1150 | return ERR_PTR(-ENOMEM); |
| 1151 | |
| 1152 | if (!tegra->domain) { |
| 1153 | /* |
| 1154 | * If IOMMU is disabled, devices address physical memory |
| 1155 | * directly. |
| 1156 | */ |
| 1157 | *dma = virt_to_phys(virt); |
| 1158 | return virt; |
| 1159 | } |
| 1160 | |
| 1161 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1162 | size >> tegra->carveout.shift, |
| 1163 | tegra->carveout.limit, true); |
| 1164 | if (!alloc) { |
| 1165 | err = -EBUSY; |
| 1166 | goto free_pages; |
| 1167 | } |
| 1168 | |
| 1169 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1170 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1171 | size, IOMMU_READ | IOMMU_WRITE); |
| 1172 | if (err < 0) |
| 1173 | goto free_iova; |
| 1174 | |
| 1175 | return virt; |
| 1176 | |
| 1177 | free_iova: |
| 1178 | __free_iova(&tegra->carveout.domain, alloc); |
| 1179 | free_pages: |
| 1180 | free_pages((unsigned long)virt, get_order(size)); |
| 1181 | |
| 1182 | return ERR_PTR(err); |
| 1183 | } |
| 1184 | |
| 1185 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1186 | dma_addr_t dma) |
| 1187 | { |
| 1188 | if (tegra->domain) |
| 1189 | size = iova_align(&tegra->carveout.domain, size); |
| 1190 | else |
| 1191 | size = PAGE_ALIGN(size); |
| 1192 | |
| 1193 | if (tegra->domain) { |
| 1194 | iommu_unmap(tegra->domain, dma, size); |
| 1195 | free_iova(&tegra->carveout.domain, |
| 1196 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1197 | } |
| 1198 | |
| 1199 | free_pages((unsigned long)virt, get_order(size)); |
| 1200 | } |
| 1201 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1202 | static int host1x_drm_probe(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1203 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1204 | struct drm_driver *driver = &tegra_drm_driver; |
| 1205 | struct drm_device *drm; |
| 1206 | int err; |
| 1207 | |
| 1208 | drm = drm_dev_alloc(driver, &dev->dev); |
Tom Gundersen | 0f28860 | 2016-09-21 16:59:19 +0200 | [diff] [blame] | 1209 | if (IS_ERR(drm)) |
| 1210 | return PTR_ERR(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1211 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1212 | dev_set_drvdata(&dev->dev, drm); |
| 1213 | |
Michał Mirosław | 6e4228f | 2018-09-01 16:08:51 +0200 | [diff] [blame] | 1214 | err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false); |
| 1215 | if (err < 0) |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1216 | goto put; |
Michał Mirosław | 6e4228f | 2018-09-01 16:08:51 +0200 | [diff] [blame] | 1217 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1218 | err = drm_dev_register(drm, 0); |
| 1219 | if (err < 0) |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1220 | goto put; |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1221 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1222 | return 0; |
| 1223 | |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1224 | put: |
| 1225 | drm_dev_put(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1226 | return err; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1227 | } |
| 1228 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1229 | static int host1x_drm_remove(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1230 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1231 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1232 | |
| 1233 | drm_dev_unregister(drm); |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1234 | drm_dev_put(drm); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1235 | |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1239 | #ifdef CONFIG_PM_SLEEP |
| 1240 | static int host1x_drm_suspend(struct device *dev) |
| 1241 | { |
| 1242 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1243 | |
Souptick Joarder | 53f1e06 | 2018-08-01 01:37:05 +0530 | [diff] [blame] | 1244 | return drm_mode_config_helper_suspend(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | static int host1x_drm_resume(struct device *dev) |
| 1248 | { |
| 1249 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1250 | |
Souptick Joarder | 53f1e06 | 2018-08-01 01:37:05 +0530 | [diff] [blame] | 1251 | return drm_mode_config_helper_resume(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1252 | } |
| 1253 | #endif |
| 1254 | |
Thierry Reding | a13f1dc | 2015-08-11 13:22:44 +0200 | [diff] [blame] | 1255 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1256 | host1x_drm_resume); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1257 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1258 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1259 | { .compatible = "nvidia,tegra20-dc", }, |
| 1260 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1261 | { .compatible = "nvidia,tegra20-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1262 | { .compatible = "nvidia,tegra20-gr3d", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1263 | { .compatible = "nvidia,tegra30-dc", }, |
| 1264 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1265 | { .compatible = "nvidia,tegra30-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1266 | { .compatible = "nvidia,tegra30-gr3d", }, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1267 | { .compatible = "nvidia,tegra114-dsi", }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1268 | { .compatible = "nvidia,tegra114-hdmi", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1269 | { .compatible = "nvidia,tegra114-gr3d", }, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1270 | { .compatible = "nvidia,tegra124-dc", }, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1271 | { .compatible = "nvidia,tegra124-sor", }, |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1272 | { .compatible = "nvidia,tegra124-hdmi", }, |
Thierry Reding | 7d33858 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1273 | { .compatible = "nvidia,tegra124-dsi", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1274 | { .compatible = "nvidia,tegra124-vic", }, |
Thierry Reding | c06c793 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1275 | { .compatible = "nvidia,tegra132-dsi", }, |
Thierry Reding | 5b4f516 | 2015-03-27 10:31:58 +0100 | [diff] [blame] | 1276 | { .compatible = "nvidia,tegra210-dc", }, |
Thierry Reding | ddfb406 | 2015-04-08 16:56:22 +0200 | [diff] [blame] | 1277 | { .compatible = "nvidia,tegra210-dsi", }, |
Thierry Reding | 3309ac8 | 2015-07-30 10:32:46 +0200 | [diff] [blame] | 1278 | { .compatible = "nvidia,tegra210-sor", }, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1279 | { .compatible = "nvidia,tegra210-sor1", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1280 | { .compatible = "nvidia,tegra210-vic", }, |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1281 | { .compatible = "nvidia,tegra186-display", }, |
Thierry Reding | 4730795 | 2017-08-30 17:42:54 +0200 | [diff] [blame] | 1282 | { .compatible = "nvidia,tegra186-dc", }, |
Thierry Reding | c57997b | 2017-10-12 19:12:57 +0200 | [diff] [blame] | 1283 | { .compatible = "nvidia,tegra186-sor", }, |
| 1284 | { .compatible = "nvidia,tegra186-sor1", }, |
Mikko Perttunen | 6e44b9a | 2017-09-05 11:43:06 +0300 | [diff] [blame] | 1285 | { .compatible = "nvidia,tegra186-vic", }, |
Thierry Reding | 5725daa | 2018-09-21 12:27:43 +0200 | [diff] [blame] | 1286 | { .compatible = "nvidia,tegra194-display", }, |
Thierry Reding | 4744319 | 2018-09-21 12:27:44 +0200 | [diff] [blame] | 1287 | { .compatible = "nvidia,tegra194-dc", }, |
Thierry Reding | 9b6c14b | 2018-09-21 12:27:46 +0200 | [diff] [blame] | 1288 | { .compatible = "nvidia,tegra194-sor", }, |
Thierry Reding | d6b9bc0 | 2018-10-26 10:59:38 +0200 | [diff] [blame] | 1289 | { .compatible = "nvidia,tegra194-vic", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1290 | { /* sentinel */ } |
| 1291 | }; |
| 1292 | |
| 1293 | static struct host1x_driver host1x_drm_driver = { |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1294 | .driver = { |
| 1295 | .name = "drm", |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1296 | .pm = &host1x_drm_pm_ops, |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1297 | }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1298 | .probe = host1x_drm_probe, |
| 1299 | .remove = host1x_drm_remove, |
| 1300 | .subdevs = host1x_drm_subdevs, |
| 1301 | }; |
| 1302 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1303 | static struct platform_driver * const drivers[] = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1304 | &tegra_display_hub_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1305 | &tegra_dc_driver, |
| 1306 | &tegra_hdmi_driver, |
| 1307 | &tegra_dsi_driver, |
| 1308 | &tegra_dpaux_driver, |
| 1309 | &tegra_sor_driver, |
| 1310 | &tegra_gr2d_driver, |
| 1311 | &tegra_gr3d_driver, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1312 | &tegra_vic_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1313 | }; |
| 1314 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1315 | static int __init host1x_drm_init(void) |
| 1316 | { |
| 1317 | int err; |
| 1318 | |
| 1319 | err = host1x_driver_register(&host1x_drm_driver); |
| 1320 | if (err < 0) |
| 1321 | return err; |
| 1322 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1323 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1324 | if (err < 0) |
| 1325 | goto unregister_host1x; |
| 1326 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1327 | return 0; |
| 1328 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1329 | unregister_host1x: |
| 1330 | host1x_driver_unregister(&host1x_drm_driver); |
| 1331 | return err; |
| 1332 | } |
| 1333 | module_init(host1x_drm_init); |
| 1334 | |
| 1335 | static void __exit host1x_drm_exit(void) |
| 1336 | { |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1337 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1338 | host1x_driver_unregister(&host1x_drm_driver); |
| 1339 | } |
| 1340 | module_exit(host1x_drm_exit); |
| 1341 | |
| 1342 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1343 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1344 | MODULE_LICENSE("GPL v2"); |