blob: b74362cb63ebdd174ea4feedf2b408fa445443e6 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002/*
3 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02004 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00005 */
6
Mikko Perttunenad926012016-12-14 13:16:11 +02007#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +02008#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01009#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020010#include <linux/iommu.h>
Sam Ravnborgeb1df692019-08-04 11:41:30 +020011#include <linux/module.h>
12#include <linux/platform_device.h>
Thierry Reding776dc382013-10-14 14:43:22 +020013
Thierry Reding1503ca42014-11-24 17:41:23 +010014#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010015#include <drm/drm_atomic_helper.h>
Sam Ravnborgeb1df692019-08-04 11:41:30 +020016#include <drm/drm_debugfs.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_fourcc.h>
19#include <drm/drm_ioctl.h>
20#include <drm/drm_prime.h>
21#include <drm/drm_vblank.h>
Thierry Reding07866962014-11-24 17:08:06 +010022
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +030023#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
24#include <asm/dma-iommu.h>
25#endif
26
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000027#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020028#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000029
30#define DRIVER_NAME "tegra"
31#define DRIVER_DESC "NVIDIA Tegra graphics"
32#define DRIVER_DATE "20120330"
33#define DRIVER_MAJOR 0
34#define DRIVER_MINOR 0
35#define DRIVER_PATCHLEVEL 0
36
Mikko Perttunenad926012016-12-14 13:16:11 +020037#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030038#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020039
Thierry Reding08943e62013-09-26 16:08:18 +020040struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010041 struct idr contexts;
42 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020043};
44
Thierry Redingab7d3f52017-12-14 13:46:20 +010045static int tegra_atomic_check(struct drm_device *drm,
46 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010047{
Thierry Reding1503ca42014-11-24 17:41:23 +010048 int err;
49
Peter Ujfalusia18301b2018-03-21 12:20:26 +020050 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010051 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010052 return err;
53
Peter Ujfalusia18301b2018-03-21 12:20:26 +020054 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010055}
56
Thierry Reding31b02ca2017-10-12 17:40:46 +020057static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010058 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053059#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010060 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010061#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010062 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020063 .atomic_commit = drm_atomic_helper_commit,
64};
65
Thierry Redingc4755fb2017-11-13 11:08:13 +010066static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
67{
68 struct drm_device *drm = old_state->dev;
69 struct tegra_drm *tegra = drm->dev_private;
70
71 if (tegra->hub) {
72 drm_atomic_helper_commit_modeset_disables(drm, old_state);
73 tegra_display_hub_atomic_commit(drm, old_state);
74 drm_atomic_helper_commit_planes(drm, old_state, 0);
75 drm_atomic_helper_commit_modeset_enables(drm, old_state);
76 drm_atomic_helper_commit_hw_done(old_state);
77 drm_atomic_helper_wait_for_vblanks(drm, old_state);
78 drm_atomic_helper_cleanup_planes(drm, old_state);
79 } else {
80 drm_atomic_helper_commit_tail_rpm(old_state);
81 }
82}
83
Thierry Reding31b02ca2017-10-12 17:40:46 +020084static const struct drm_mode_config_helper_funcs
85tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010086 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010087};
88
Thierry Reding776dc382013-10-14 14:43:22 +020089static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000090{
Thierry Reding776dc382013-10-14 14:43:22 +020091 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020092 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000093 int err;
94
Thierry Reding776dc382013-10-14 14:43:22 +020095 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020096 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020097 return -ENOMEM;
98
Thierry Redingdf06b752014-06-26 21:41:53 +020099 if (iommu_present(&platform_bus_type)) {
100 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300101 if (!tegra->domain) {
102 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200103 goto free;
104 }
105
Thierry Reding24cfdc12018-04-23 08:57:45 +0200106 err = iova_cache_get();
107 if (err < 0)
108 goto domain;
Thierry Redingdf06b752014-06-26 21:41:53 +0200109 }
110
Thierry Reding386a2a72013-09-24 13:22:17 +0200111 mutex_init(&tegra->clients_lock);
112 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100113
Thierry Reding386a2a72013-09-24 13:22:17 +0200114 drm->dev_private = tegra;
115 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000116
117 drm_mode_config_init(drm);
118
Thierry Redingf9914212014-11-26 13:03:57 +0100119 drm->mode_config.min_width = 0;
120 drm->mode_config.min_height = 0;
121
122 drm->mode_config.max_width = 4096;
123 drm->mode_config.max_height = 4096;
124
Alexandre Courbot5e911442016-11-08 16:50:42 +0900125 drm->mode_config.allow_fb_modifiers = true;
126
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200127 drm->mode_config.normalize_zpos = true;
128
Thierry Reding31b02ca2017-10-12 17:40:46 +0200129 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
130 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100131
Thierry Redinge2215321f2014-06-27 17:19:25 +0200132 err = tegra_drm_fb_prepare(drm);
133 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100134 goto config;
Thierry Redinge2215321f2014-06-27 17:19:25 +0200135
136 drm_kms_helper_poll_init(drm);
137
Thierry Reding776dc382013-10-14 14:43:22 +0200138 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000139 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100140 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000141
Thierry Redingb9f8b092019-02-01 14:28:33 +0100142 if (tegra->domain) {
143 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding02be8e42019-02-01 14:28:34 +0100144 u64 dma_mask = dma_get_mask(&device->dev);
Thierry Redingb9f8b092019-02-01 14:28:33 +0100145 dma_addr_t start, end;
146 unsigned long order;
147
Thierry Reding02be8e42019-02-01 14:28:34 +0100148 start = tegra->domain->geometry.aperture_start & dma_mask;
149 end = tegra->domain->geometry.aperture_end & dma_mask;
Thierry Redingb9f8b092019-02-01 14:28:33 +0100150
151 gem_start = start;
152 gem_end = end - CARVEOUT_SZ;
153 carveout_start = gem_end + 1;
154 carveout_end = end;
155
156 order = __ffs(tegra->domain->pgsize_bitmap);
157 init_iova_domain(&tegra->carveout.domain, 1UL << order,
158 carveout_start >> order);
159
160 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
161 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
162
163 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
164 mutex_init(&tegra->mm_lock);
165
Thierry Reding03011962019-09-04 13:00:30 +0200166 DRM_DEBUG_DRIVER("IOMMU apertures:\n");
167 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
168 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
169 carveout_end);
Thierry Redingb9f8b092019-02-01 14:28:33 +0100170 }
171
Thierry Redingc4755fb2017-11-13 11:08:13 +0100172 if (tegra->hub) {
173 err = tegra_display_hub_prepare(tegra->hub);
174 if (err < 0)
175 goto device;
176 }
177
Thierry Reding603f0cc2013-04-22 21:22:14 +0200178 /*
179 * We don't use the drm_irq_install() helpers provided by the DRM
180 * core, so we need to set this manually in order to allow the
181 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
182 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300183 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200184
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100186 drm->max_vblank_count = 0xffffffff;
187
Thierry Reding6e5ff992012-11-28 11:45:47 +0100188 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
189 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100190 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100191
Thierry Reding31930d42015-07-02 17:04:06 +0200192 drm_mode_config_reset(drm);
193
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000194 err = tegra_drm_fb_init(drm);
195 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100196 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100199
Thierry Redingc4755fb2017-11-13 11:08:13 +0100200hub:
201 if (tegra->hub)
202 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100203device:
Thierry Redingdf06b752014-06-26 21:41:53 +0200204 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100205 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200206 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200207 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200208 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200209 }
Thierry Reding051172e2019-09-25 13:26:59 +0200210
211 host1x_device_exit(device);
212fbdev:
213 drm_kms_helper_poll_fini(drm);
214 tegra_drm_fb_free(drm);
215config:
216 drm_mode_config_cleanup(drm);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200217domain:
218 if (tegra->domain)
219 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200220free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100221 kfree(tegra);
222 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223}
224
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200225static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000226{
Thierry Reding776dc382013-10-14 14:43:22 +0200227 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200228 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200229 int err;
230
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000231 drm_kms_helper_poll_fini(drm);
232 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100233 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200234 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000235
Thierry Reding776dc382013-10-14 14:43:22 +0200236 err = host1x_device_exit(device);
237 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200238 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200239
Thierry Redingdf06b752014-06-26 21:41:53 +0200240 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100241 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200242 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200243 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200244 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200245 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200246 }
247
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100248 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000249}
250
251static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
252{
Thierry Reding08943e62013-09-26 16:08:18 +0200253 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200254
255 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
256 if (!fpriv)
257 return -ENOMEM;
258
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100259 idr_init(&fpriv->contexts);
260 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200261 filp->driver_priv = fpriv;
262
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000263 return 0;
264}
265
Thierry Redingc88c3632013-09-26 16:08:22 +0200266static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200267{
268 context->client->ops->close_channel(context);
269 kfree(context);
270}
271
Thierry Redingc40f0f12013-10-10 11:00:33 +0200272static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100273host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200274{
275 struct drm_gem_object *gem;
276 struct tegra_bo *bo;
277
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100278 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200279 if (!gem)
280 return NULL;
281
Thierry Redingc40f0f12013-10-10 11:00:33 +0200282 bo = to_tegra_bo(gem);
283 return &bo->base;
284}
285
Thierry Reding961e3be2014-06-10 10:25:00 +0200286static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
287 struct drm_tegra_reloc __user *src,
288 struct drm_device *drm,
289 struct drm_file *file)
290{
291 u32 cmdbuf, target;
292 int err;
293
294 err = get_user(cmdbuf, &src->cmdbuf.handle);
295 if (err < 0)
296 return err;
297
298 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
299 if (err < 0)
300 return err;
301
302 err = get_user(target, &src->target.handle);
303 if (err < 0)
304 return err;
305
David Ung31f40f82015-01-20 18:37:35 -0800306 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200307 if (err < 0)
308 return err;
309
310 err = get_user(dest->shift, &src->shift);
311 if (err < 0)
312 return err;
313
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100314 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200315 if (!dest->cmdbuf.bo)
316 return -ENOENT;
317
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100318 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200319 if (!dest->target.bo)
320 return -ENOENT;
321
322 return 0;
323}
324
Thierry Redingc40f0f12013-10-10 11:00:33 +0200325int tegra_drm_submit(struct tegra_drm_context *context,
326 struct drm_tegra_submit *args, struct drm_device *drm,
327 struct drm_file *file)
328{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200329 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200330 unsigned int num_cmdbufs = args->num_cmdbufs;
331 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300332 struct drm_tegra_cmdbuf __user *user_cmdbufs;
333 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300334 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200335 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300336 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200337 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300338 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200339 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200340 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200341 int err;
342
Mikko Perttunena176c672017-09-28 15:50:44 +0300343 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
344 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300345 user_syncpt = u64_to_user_ptr(args->syncpts);
346
Thierry Redingc40f0f12013-10-10 11:00:33 +0200347 /* We don't yet support other than one syncpt_incr struct per submit */
348 if (args->num_syncpts != 1)
349 return -EINVAL;
350
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300351 /* We don't yet support waitchks */
352 if (args->num_waitchks != 0)
353 return -EINVAL;
354
Thierry Redingc40f0f12013-10-10 11:00:33 +0200355 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200356 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200357 if (!job)
358 return -ENOMEM;
359
360 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200361 job->client = client;
362 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200363 job->serialize = true;
364
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200365 /*
366 * Track referenced BOs so that they can be unreferenced after the
367 * submission is complete.
368 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200369 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200370
371 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
372 if (!refs) {
373 err = -ENOMEM;
374 goto put;
375 }
376
377 /* reuse as an iterator later */
378 num_refs = 0;
379
Thierry Redingc40f0f12013-10-10 11:00:33 +0200380 while (num_cmdbufs) {
381 struct drm_tegra_cmdbuf cmdbuf;
382 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300383 struct tegra_bo *obj;
384 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200385
Mikko Perttunena176c672017-09-28 15:50:44 +0300386 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300387 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200388 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300389 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200390
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300391 /*
392 * The maximum number of CDMA gather fetches is 16383, a higher
393 * value means the words count is malformed.
394 */
395 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
396 err = -EINVAL;
397 goto fail;
398 }
399
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100400 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200401 if (!bo) {
402 err = -ENOENT;
403 goto fail;
404 }
405
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300406 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
407 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200408 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300409
410 /*
411 * Gather buffer base address must be 4-bytes aligned,
412 * unaligned offset is malformed and cause commands stream
413 * corruption on the buffer address relocation.
414 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300415 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300416 err = -EINVAL;
417 goto fail;
418 }
419
Thierry Redingc40f0f12013-10-10 11:00:33 +0200420 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
421 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300422 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200423 }
424
Thierry Reding961e3be2014-06-10 10:25:00 +0200425 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200426 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300427 struct host1x_reloc *reloc;
428 struct tegra_bo *obj;
429
Thierry Reding06490bb2018-05-16 16:58:44 +0200430 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300431 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200432 file);
433 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200434 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300435
Thierry Reding06490bb2018-05-16 16:58:44 +0200436 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300437 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200438 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300439
440 /*
441 * The unaligned cmdbuf offset will cause an unaligned write
442 * during of the relocations patching, corrupting the commands
443 * stream.
444 */
445 if (reloc->cmdbuf.offset & 3 ||
446 reloc->cmdbuf.offset >= obj->gem.size) {
447 err = -EINVAL;
448 goto fail;
449 }
450
451 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200452 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300453
454 if (reloc->target.offset >= obj->gem.size) {
455 err = -EINVAL;
456 goto fail;
457 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200458 }
459
Mikko Perttunena176c672017-09-28 15:50:44 +0300460 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300461 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200462 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300463 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200464
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300465 /* check whether syncpoint ID is valid */
466 sp = host1x_syncpt_get(host1x, syncpt.id);
467 if (!sp) {
468 err = -ENOENT;
469 goto fail;
470 }
471
Thierry Redingc40f0f12013-10-10 11:00:33 +0200472 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300473 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200474 job->syncpt_incrs = syncpt.incrs;
475 job->syncpt_id = syncpt.id;
476 job->timeout = 10000;
477
478 if (args->timeout && args->timeout < 10000)
479 job->timeout = args->timeout;
480
481 err = host1x_job_pin(job, context->client->base.dev);
482 if (err)
483 goto fail;
484
485 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200486 if (err) {
487 host1x_job_unpin(job);
488 goto fail;
489 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200490
491 args->fence = job->syncpt_end;
492
Thierry Redingc40f0f12013-10-10 11:00:33 +0200493fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200494 while (num_refs--)
495 drm_gem_object_put_unlocked(refs[num_refs]);
496
497 kfree(refs);
498
499put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200500 host1x_job_put(job);
501 return err;
502}
503
504
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200505#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200506static int tegra_gem_create(struct drm_device *drm, void *data,
507 struct drm_file *file)
508{
509 struct drm_tegra_gem_create *args = data;
510 struct tegra_bo *bo;
511
Thierry Reding773af772013-10-04 22:34:01 +0200512 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200513 &args->handle);
514 if (IS_ERR(bo))
515 return PTR_ERR(bo);
516
517 return 0;
518}
519
520static int tegra_gem_mmap(struct drm_device *drm, void *data,
521 struct drm_file *file)
522{
523 struct drm_tegra_gem_mmap *args = data;
524 struct drm_gem_object *gem;
525 struct tegra_bo *bo;
526
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100527 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200528 if (!gem)
529 return -EINVAL;
530
531 bo = to_tegra_bo(gem);
532
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200533 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200534
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300535 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200536
537 return 0;
538}
539
540static int tegra_syncpt_read(struct drm_device *drm, void *data,
541 struct drm_file *file)
542{
Thierry Reding776dc382013-10-14 14:43:22 +0200543 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200544 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200545 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200546
Thierry Reding776dc382013-10-14 14:43:22 +0200547 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200548 if (!sp)
549 return -EINVAL;
550
551 args->value = host1x_syncpt_read_min(sp);
552 return 0;
553}
554
555static int tegra_syncpt_incr(struct drm_device *drm, void *data,
556 struct drm_file *file)
557{
Thierry Reding776dc382013-10-14 14:43:22 +0200558 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200559 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200560 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561
Thierry Reding776dc382013-10-14 14:43:22 +0200562 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563 if (!sp)
564 return -EINVAL;
565
Arto Merilainenebae30b2013-05-29 13:26:08 +0300566 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567}
568
569static int tegra_syncpt_wait(struct drm_device *drm, void *data,
570 struct drm_file *file)
571{
Thierry Reding776dc382013-10-14 14:43:22 +0200572 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200573 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200574 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200575
Thierry Reding776dc382013-10-14 14:43:22 +0200576 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200577 if (!sp)
578 return -EINVAL;
579
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300580 return host1x_syncpt_wait(sp, args->thresh,
581 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200582 &args->value);
583}
584
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100585static int tegra_client_open(struct tegra_drm_file *fpriv,
586 struct tegra_drm_client *client,
587 struct tegra_drm_context *context)
588{
589 int err;
590
591 err = client->ops->open_channel(client, context);
592 if (err < 0)
593 return err;
594
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300595 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100596 if (err < 0) {
597 client->ops->close_channel(context);
598 return err;
599 }
600
601 context->client = client;
602 context->id = err;
603
604 return 0;
605}
606
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200607static int tegra_open_channel(struct drm_device *drm, void *data,
608 struct drm_file *file)
609{
Thierry Reding08943e62013-09-26 16:08:18 +0200610 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200611 struct tegra_drm *tegra = drm->dev_private;
612 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200613 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200614 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200615 int err = -ENODEV;
616
617 context = kzalloc(sizeof(*context), GFP_KERNEL);
618 if (!context)
619 return -ENOMEM;
620
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100621 mutex_lock(&fpriv->lock);
622
Thierry Reding776dc382013-10-14 14:43:22 +0200623 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200624 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100625 err = tegra_client_open(fpriv, client, context);
626 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200627 break;
628
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100629 args->context = context->id;
630 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631 }
632
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100633 if (err < 0)
634 kfree(context);
635
636 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200637 return err;
638}
639
640static int tegra_close_channel(struct drm_device *drm, void *data,
641 struct drm_file *file)
642{
Thierry Reding08943e62013-09-26 16:08:18 +0200643 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200644 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200645 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100646 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200647
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100648 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200649
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300650 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100651 if (!context) {
652 err = -EINVAL;
653 goto unlock;
654 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200655
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100656 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200657 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200658
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100659unlock:
660 mutex_unlock(&fpriv->lock);
661 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662}
663
664static int tegra_get_syncpt(struct drm_device *drm, void *data,
665 struct drm_file *file)
666{
Thierry Reding08943e62013-09-26 16:08:18 +0200667 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200668 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200669 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200670 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100671 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200672
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100673 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200674
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300675 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100676 if (!context) {
677 err = -ENODEV;
678 goto unlock;
679 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 if (args->index >= context->client->base.num_syncpts) {
682 err = -EINVAL;
683 goto unlock;
684 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200685
Thierry Reding53fa7f72013-09-24 15:35:40 +0200686 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200687 args->id = host1x_syncpt_id(syncpt);
688
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100689unlock:
690 mutex_unlock(&fpriv->lock);
691 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200692}
693
694static int tegra_submit(struct drm_device *drm, void *data,
695 struct drm_file *file)
696{
Thierry Reding08943e62013-09-26 16:08:18 +0200697 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200698 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200699 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100700 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200701
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100702 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200703
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300704 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100705 if (!context) {
706 err = -ENODEV;
707 goto unlock;
708 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200709
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100710 err = context->client->ops->submit(context, args, drm, file);
711
712unlock:
713 mutex_unlock(&fpriv->lock);
714 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200715}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300716
717static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
718 struct drm_file *file)
719{
720 struct tegra_drm_file *fpriv = file->driver_priv;
721 struct drm_tegra_get_syncpt_base *args = data;
722 struct tegra_drm_context *context;
723 struct host1x_syncpt_base *base;
724 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100725 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300726
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100727 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300728
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300729 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100730 if (!context) {
731 err = -ENODEV;
732 goto unlock;
733 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300734
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100735 if (args->syncpt >= context->client->base.num_syncpts) {
736 err = -EINVAL;
737 goto unlock;
738 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300739
740 syncpt = context->client->base.syncpts[args->syncpt];
741
742 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100743 if (!base) {
744 err = -ENXIO;
745 goto unlock;
746 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300747
748 args->id = host1x_syncpt_base_id(base);
749
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100750unlock:
751 mutex_unlock(&fpriv->lock);
752 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300753}
Thierry Reding7678d712014-06-03 14:56:57 +0200754
755static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
756 struct drm_file *file)
757{
758 struct drm_tegra_gem_set_tiling *args = data;
759 enum tegra_bo_tiling_mode mode;
760 struct drm_gem_object *gem;
761 unsigned long value = 0;
762 struct tegra_bo *bo;
763
764 switch (args->mode) {
765 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
766 mode = TEGRA_BO_TILING_MODE_PITCH;
767
768 if (args->value != 0)
769 return -EINVAL;
770
771 break;
772
773 case DRM_TEGRA_GEM_TILING_MODE_TILED:
774 mode = TEGRA_BO_TILING_MODE_TILED;
775
776 if (args->value != 0)
777 return -EINVAL;
778
779 break;
780
781 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
782 mode = TEGRA_BO_TILING_MODE_BLOCK;
783
784 if (args->value > 5)
785 return -EINVAL;
786
787 value = args->value;
788 break;
789
790 default:
791 return -EINVAL;
792 }
793
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100794 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200795 if (!gem)
796 return -ENOENT;
797
798 bo = to_tegra_bo(gem);
799
800 bo->tiling.mode = mode;
801 bo->tiling.value = value;
802
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300803 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200804
805 return 0;
806}
807
808static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
809 struct drm_file *file)
810{
811 struct drm_tegra_gem_get_tiling *args = data;
812 struct drm_gem_object *gem;
813 struct tegra_bo *bo;
814 int err = 0;
815
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100816 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200817 if (!gem)
818 return -ENOENT;
819
820 bo = to_tegra_bo(gem);
821
822 switch (bo->tiling.mode) {
823 case TEGRA_BO_TILING_MODE_PITCH:
824 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
825 args->value = 0;
826 break;
827
828 case TEGRA_BO_TILING_MODE_TILED:
829 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
830 args->value = 0;
831 break;
832
833 case TEGRA_BO_TILING_MODE_BLOCK:
834 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
835 args->value = bo->tiling.value;
836 break;
837
838 default:
839 err = -EINVAL;
840 break;
841 }
842
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300843 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200844
845 return err;
846}
Thierry Reding7b129082014-06-10 12:04:03 +0200847
848static int tegra_gem_set_flags(struct drm_device *drm, void *data,
849 struct drm_file *file)
850{
851 struct drm_tegra_gem_set_flags *args = data;
852 struct drm_gem_object *gem;
853 struct tegra_bo *bo;
854
855 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
856 return -EINVAL;
857
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100858 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200859 if (!gem)
860 return -ENOENT;
861
862 bo = to_tegra_bo(gem);
863 bo->flags = 0;
864
865 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
866 bo->flags |= TEGRA_BO_BOTTOM_UP;
867
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300868 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200869
870 return 0;
871}
872
873static int tegra_gem_get_flags(struct drm_device *drm, void *data,
874 struct drm_file *file)
875{
876 struct drm_tegra_gem_get_flags *args = data;
877 struct drm_gem_object *gem;
878 struct tegra_bo *bo;
879
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100880 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200881 if (!gem)
882 return -ENOENT;
883
884 bo = to_tegra_bo(gem);
885 args->flags = 0;
886
887 if (bo->flags & TEGRA_BO_BOTTOM_UP)
888 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
889
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300890 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200891
892 return 0;
893}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200894#endif
895
Rob Clarkbaa70942013-08-02 13:27:49 -0400896static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200897#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200898 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
Emil Velikovd6891db2019-05-22 16:46:59 +0100899 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200900 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
Emil Velikovd6891db2019-05-22 16:46:59 +0100901 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200902 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
Emil Velikovd6891db2019-05-22 16:46:59 +0100903 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200904 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
Emil Velikovd6891db2019-05-22 16:46:59 +0100905 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200906 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
Emil Velikovd6891db2019-05-22 16:46:59 +0100907 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200908 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
Emil Velikovd6891db2019-05-22 16:46:59 +0100909 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200910 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
Emil Velikovd6891db2019-05-22 16:46:59 +0100911 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200912 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
Emil Velikovd6891db2019-05-22 16:46:59 +0100913 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200914 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
Emil Velikovd6891db2019-05-22 16:46:59 +0100915 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200916 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
Emil Velikovd6891db2019-05-22 16:46:59 +0100917 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200918 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
Emil Velikovd6891db2019-05-22 16:46:59 +0100919 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200920 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
Emil Velikovd6891db2019-05-22 16:46:59 +0100921 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200922 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
Emil Velikovd6891db2019-05-22 16:46:59 +0100923 DRM_RENDER_ALLOW),
Thierry Reding6c68b712017-08-15 15:42:39 +0200924 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
Emil Velikovd6891db2019-05-22 16:46:59 +0100925 DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200926#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000927};
928
929static const struct file_operations tegra_drm_fops = {
930 .owner = THIS_MODULE,
931 .open = drm_open,
932 .release = drm_release,
933 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200934 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000935 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000936 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000937 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000938 .llseek = noop_llseek,
939};
940
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100941static int tegra_drm_context_cleanup(int id, void *p, void *data)
942{
943 struct tegra_drm_context *context = p;
944
945 tegra_drm_context_free(context);
946
947 return 0;
948}
949
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200950static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100951{
Thierry Reding08943e62013-09-26 16:08:18 +0200952 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100953
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100954 mutex_lock(&fpriv->lock);
955 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
956 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200957
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100958 idr_destroy(&fpriv->contexts);
959 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200960 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100961}
962
Thierry Redinge450fcc2013-02-13 16:13:16 +0100963#ifdef CONFIG_DEBUG_FS
964static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
965{
966 struct drm_info_node *node = (struct drm_info_node *)s->private;
967 struct drm_device *drm = node->minor->dev;
968 struct drm_framebuffer *fb;
969
970 mutex_lock(&drm->mode_config.fb_lock);
971
972 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
973 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200974 fb->base.id, fb->width, fb->height,
975 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200976 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000977 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100978 }
979
980 mutex_unlock(&drm->mode_config.fb_lock);
981
982 return 0;
983}
984
Thierry Reding28c23372015-01-23 09:16:03 +0100985static int tegra_debugfs_iova(struct seq_file *s, void *data)
986{
987 struct drm_info_node *node = (struct drm_info_node *)s->private;
988 struct drm_device *drm = node->minor->dev;
989 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100990 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100991
Michał Mirosław68d890a2017-08-14 23:53:45 +0200992 if (tegra->domain) {
993 mutex_lock(&tegra->mm_lock);
994 drm_mm_print(&tegra->mm, &p);
995 mutex_unlock(&tegra->mm_lock);
996 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100997
998 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100999}
1000
Thierry Redinge450fcc2013-02-13 16:13:16 +01001001static struct drm_info_list tegra_debugfs_list[] = {
1002 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001003 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001004};
1005
1006static int tegra_debugfs_init(struct drm_minor *minor)
1007{
1008 return drm_debugfs_create_files(tegra_debugfs_list,
1009 ARRAY_SIZE(tegra_debugfs_list),
1010 minor->debugfs_root, minor);
1011}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001012#endif
1013
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001014static struct drm_driver tegra_drm_driver = {
Daniel Vetter0424fda2019-06-17 17:39:24 +02001015 .driver_features = DRIVER_MODESET | DRIVER_GEM |
Thierry Reding6c68b712017-08-15 15:42:39 +02001016 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001017 .load = tegra_drm_load,
1018 .unload = tegra_drm_unload,
1019 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001020 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001021 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001022
Thierry Redinge450fcc2013-02-13 16:13:16 +01001023#if defined(CONFIG_DEBUG_FS)
1024 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001025#endif
1026
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001027 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001028 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001029
1030 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1031 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1032 .gem_prime_export = tegra_gem_prime_export,
1033 .gem_prime_import = tegra_gem_prime_import,
1034
Arto Merilainende2ba662013-03-22 16:34:08 +02001035 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001036
1037 .ioctls = tegra_drm_ioctls,
1038 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1039 .fops = &tegra_drm_fops,
1040
1041 .name = DRIVER_NAME,
1042 .desc = DRIVER_DESC,
1043 .date = DRIVER_DATE,
1044 .major = DRIVER_MAJOR,
1045 .minor = DRIVER_MINOR,
1046 .patchlevel = DRIVER_PATCHLEVEL,
1047};
Thierry Reding776dc382013-10-14 14:43:22 +02001048
1049int tegra_drm_register_client(struct tegra_drm *tegra,
1050 struct tegra_drm_client *client)
1051{
1052 mutex_lock(&tegra->clients_lock);
1053 list_add_tail(&client->list, &tegra->clients);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001054 client->drm = tegra;
Thierry Reding776dc382013-10-14 14:43:22 +02001055 mutex_unlock(&tegra->clients_lock);
1056
1057 return 0;
1058}
1059
1060int tegra_drm_unregister_client(struct tegra_drm *tegra,
1061 struct tegra_drm_client *client)
1062{
1063 mutex_lock(&tegra->clients_lock);
1064 list_del_init(&client->list);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001065 client->drm = NULL;
Thierry Reding776dc382013-10-14 14:43:22 +02001066 mutex_unlock(&tegra->clients_lock);
1067
1068 return 0;
1069}
1070
Thierry Redingaacdf192019-02-08 14:35:13 +01001071int host1x_client_iommu_attach(struct host1x_client *client, bool shared)
Thierry Reding0c407de2018-05-04 15:02:24 +02001072{
1073 struct drm_device *drm = dev_get_drvdata(client->parent);
1074 struct tegra_drm *tegra = drm->dev_private;
1075 struct iommu_group *group = NULL;
1076 int err;
1077
1078 if (tegra->domain) {
1079 group = iommu_group_get(client->dev);
1080 if (!group) {
1081 dev_err(client->dev, "failed to get IOMMU group\n");
Thierry Redingaacdf192019-02-08 14:35:13 +01001082 return -ENODEV;
Thierry Reding0c407de2018-05-04 15:02:24 +02001083 }
1084
1085 if (!shared || (shared && (group != tegra->group))) {
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +03001086#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
1087 if (client->dev->archdata.mapping) {
1088 struct dma_iommu_mapping *mapping =
1089 to_dma_iommu_mapping(client->dev);
1090 arm_iommu_detach_device(client->dev);
1091 arm_iommu_release_mapping(mapping);
1092 }
1093#endif
Thierry Reding0c407de2018-05-04 15:02:24 +02001094 err = iommu_attach_group(tegra->domain, group);
1095 if (err < 0) {
1096 iommu_group_put(group);
Thierry Redingaacdf192019-02-08 14:35:13 +01001097 return err;
Thierry Reding0c407de2018-05-04 15:02:24 +02001098 }
1099
1100 if (shared && !tegra->group)
1101 tegra->group = group;
1102 }
1103 }
1104
Thierry Redingaacdf192019-02-08 14:35:13 +01001105 client->group = group;
1106
1107 return 0;
Thierry Reding0c407de2018-05-04 15:02:24 +02001108}
1109
Thierry Redingaacdf192019-02-08 14:35:13 +01001110void host1x_client_iommu_detach(struct host1x_client *client)
Thierry Reding0c407de2018-05-04 15:02:24 +02001111{
1112 struct drm_device *drm = dev_get_drvdata(client->parent);
1113 struct tegra_drm *tegra = drm->dev_private;
1114
Thierry Redingaacdf192019-02-08 14:35:13 +01001115 if (client->group) {
1116 if (client->group == tegra->group) {
1117 iommu_detach_group(tegra->domain, client->group);
Thierry Reding0c407de2018-05-04 15:02:24 +02001118 tegra->group = NULL;
1119 }
1120
Thierry Redingaacdf192019-02-08 14:35:13 +01001121 iommu_group_put(client->group);
Thierry Reding0c407de2018-05-04 15:02:24 +02001122 }
1123}
1124
Thierry Reding67485fb2017-11-09 13:17:11 +01001125void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001126{
1127 struct iova *alloc;
1128 void *virt;
1129 gfp_t gfp;
1130 int err;
1131
1132 if (tegra->domain)
1133 size = iova_align(&tegra->carveout.domain, size);
1134 else
1135 size = PAGE_ALIGN(size);
1136
1137 gfp = GFP_KERNEL | __GFP_ZERO;
1138 if (!tegra->domain) {
1139 /*
1140 * Many units only support 32-bit addresses, even on 64-bit
1141 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1142 * virtual address space, force allocations to be in the
1143 * lower 32-bit range.
1144 */
1145 gfp |= GFP_DMA;
1146 }
1147
1148 virt = (void *)__get_free_pages(gfp, get_order(size));
1149 if (!virt)
1150 return ERR_PTR(-ENOMEM);
1151
1152 if (!tegra->domain) {
1153 /*
1154 * If IOMMU is disabled, devices address physical memory
1155 * directly.
1156 */
1157 *dma = virt_to_phys(virt);
1158 return virt;
1159 }
1160
1161 alloc = alloc_iova(&tegra->carveout.domain,
1162 size >> tegra->carveout.shift,
1163 tegra->carveout.limit, true);
1164 if (!alloc) {
1165 err = -EBUSY;
1166 goto free_pages;
1167 }
1168
1169 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1170 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1171 size, IOMMU_READ | IOMMU_WRITE);
1172 if (err < 0)
1173 goto free_iova;
1174
1175 return virt;
1176
1177free_iova:
1178 __free_iova(&tegra->carveout.domain, alloc);
1179free_pages:
1180 free_pages((unsigned long)virt, get_order(size));
1181
1182 return ERR_PTR(err);
1183}
1184
1185void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1186 dma_addr_t dma)
1187{
1188 if (tegra->domain)
1189 size = iova_align(&tegra->carveout.domain, size);
1190 else
1191 size = PAGE_ALIGN(size);
1192
1193 if (tegra->domain) {
1194 iommu_unmap(tegra->domain, dma, size);
1195 free_iova(&tegra->carveout.domain,
1196 iova_pfn(&tegra->carveout.domain, dma));
1197 }
1198
1199 free_pages((unsigned long)virt, get_order(size));
1200}
1201
Thierry Reding9910f5c2014-05-22 09:57:15 +02001202static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001203{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001204 struct drm_driver *driver = &tegra_drm_driver;
1205 struct drm_device *drm;
1206 int err;
1207
1208 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001209 if (IS_ERR(drm))
1210 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001211
Thierry Reding9910f5c2014-05-22 09:57:15 +02001212 dev_set_drvdata(&dev->dev, drm);
1213
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001214 err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
1215 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001216 goto put;
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001217
Thierry Reding9910f5c2014-05-22 09:57:15 +02001218 err = drm_dev_register(drm, 0);
1219 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001220 goto put;
Thierry Reding9910f5c2014-05-22 09:57:15 +02001221
Thierry Reding9910f5c2014-05-22 09:57:15 +02001222 return 0;
1223
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001224put:
1225 drm_dev_put(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001226 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001227}
1228
Thierry Reding9910f5c2014-05-22 09:57:15 +02001229static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001230{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001231 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1232
1233 drm_dev_unregister(drm);
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001234 drm_dev_put(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001235
1236 return 0;
1237}
1238
Thierry Reding359ae682014-12-18 17:15:25 +01001239#ifdef CONFIG_PM_SLEEP
1240static int host1x_drm_suspend(struct device *dev)
1241{
1242 struct drm_device *drm = dev_get_drvdata(dev);
1243
Souptick Joarder53f1e062018-08-01 01:37:05 +05301244 return drm_mode_config_helper_suspend(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001245}
1246
1247static int host1x_drm_resume(struct device *dev)
1248{
1249 struct drm_device *drm = dev_get_drvdata(dev);
1250
Souptick Joarder53f1e062018-08-01 01:37:05 +05301251 return drm_mode_config_helper_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001252}
1253#endif
1254
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001255static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1256 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001257
Thierry Reding776dc382013-10-14 14:43:22 +02001258static const struct of_device_id host1x_drm_subdevs[] = {
1259 { .compatible = "nvidia,tegra20-dc", },
1260 { .compatible = "nvidia,tegra20-hdmi", },
1261 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001262 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001263 { .compatible = "nvidia,tegra30-dc", },
1264 { .compatible = "nvidia,tegra30-hdmi", },
1265 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001266 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001267 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001268 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001269 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001270 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001271 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001272 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001273 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001274 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001275 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001276 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001277 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001278 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001279 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001280 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001281 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001282 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001283 { .compatible = "nvidia,tegra186-sor", },
1284 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001285 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding5725daa2018-09-21 12:27:43 +02001286 { .compatible = "nvidia,tegra194-display", },
Thierry Reding47443192018-09-21 12:27:44 +02001287 { .compatible = "nvidia,tegra194-dc", },
Thierry Reding9b6c14b2018-09-21 12:27:46 +02001288 { .compatible = "nvidia,tegra194-sor", },
Thierry Redingd6b9bc02018-10-26 10:59:38 +02001289 { .compatible = "nvidia,tegra194-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001290 { /* sentinel */ }
1291};
1292
1293static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001294 .driver = {
1295 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001296 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001297 },
Thierry Reding776dc382013-10-14 14:43:22 +02001298 .probe = host1x_drm_probe,
1299 .remove = host1x_drm_remove,
1300 .subdevs = host1x_drm_subdevs,
1301};
1302
Thierry Reding473112e2015-09-10 16:07:14 +02001303static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001304 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001305 &tegra_dc_driver,
1306 &tegra_hdmi_driver,
1307 &tegra_dsi_driver,
1308 &tegra_dpaux_driver,
1309 &tegra_sor_driver,
1310 &tegra_gr2d_driver,
1311 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001312 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001313};
1314
Thierry Reding776dc382013-10-14 14:43:22 +02001315static int __init host1x_drm_init(void)
1316{
1317 int err;
1318
1319 err = host1x_driver_register(&host1x_drm_driver);
1320 if (err < 0)
1321 return err;
1322
Thierry Reding473112e2015-09-10 16:07:14 +02001323 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001324 if (err < 0)
1325 goto unregister_host1x;
1326
Thierry Reding776dc382013-10-14 14:43:22 +02001327 return 0;
1328
Thierry Reding776dc382013-10-14 14:43:22 +02001329unregister_host1x:
1330 host1x_driver_unregister(&host1x_drm_driver);
1331 return err;
1332}
1333module_init(host1x_drm_init);
1334
1335static void __exit host1x_drm_exit(void)
1336{
Thierry Reding473112e2015-09-10 16:07:14 +02001337 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001338 host1x_driver_unregister(&host1x_drm_driver);
1339}
1340module_exit(host1x_drm_exit);
1341
1342MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1343MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1344MODULE_LICENSE("GPL v2");