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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +030018#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
19#include <asm/dma-iommu.h>
20#endif
21
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000022#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020023#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000024
25#define DRIVER_NAME "tegra"
26#define DRIVER_DESC "NVIDIA Tegra graphics"
27#define DRIVER_DATE "20120330"
28#define DRIVER_MAJOR 0
29#define DRIVER_MINOR 0
30#define DRIVER_PATCHLEVEL 0
31
Mikko Perttunenad926012016-12-14 13:16:11 +020032#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030033#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020034
Thierry Reding08943e62013-09-26 16:08:18 +020035struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010036 struct idr contexts;
37 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020038};
39
Thierry Redingab7d3f52017-12-14 13:46:20 +010040static int tegra_atomic_check(struct drm_device *drm,
41 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010042{
Thierry Reding1503ca42014-11-24 17:41:23 +010043 int err;
44
Peter Ujfalusia18301b2018-03-21 12:20:26 +020045 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010046 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010047 return err;
48
Peter Ujfalusia18301b2018-03-21 12:20:26 +020049 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010050}
51
Thierry Reding31b02ca2017-10-12 17:40:46 +020052static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010053 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053054#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010055 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010056#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020058 .atomic_commit = drm_atomic_helper_commit,
59};
60
Thierry Redingc4755fb2017-11-13 11:08:13 +010061static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
62{
63 struct drm_device *drm = old_state->dev;
64 struct tegra_drm *tegra = drm->dev_private;
65
66 if (tegra->hub) {
67 drm_atomic_helper_commit_modeset_disables(drm, old_state);
68 tegra_display_hub_atomic_commit(drm, old_state);
69 drm_atomic_helper_commit_planes(drm, old_state, 0);
70 drm_atomic_helper_commit_modeset_enables(drm, old_state);
71 drm_atomic_helper_commit_hw_done(old_state);
72 drm_atomic_helper_wait_for_vblanks(drm, old_state);
73 drm_atomic_helper_cleanup_planes(drm, old_state);
74 } else {
75 drm_atomic_helper_commit_tail_rpm(old_state);
76 }
77}
78
Thierry Reding31b02ca2017-10-12 17:40:46 +020079static const struct drm_mode_config_helper_funcs
80tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010081 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010082};
83
Thierry Reding776dc382013-10-14 14:43:22 +020084static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000085{
Thierry Reding776dc382013-10-14 14:43:22 +020086 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020087 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000088 int err;
89
Thierry Reding776dc382013-10-14 14:43:22 +020090 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020091 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020092 return -ENOMEM;
93
Thierry Redingdf06b752014-06-26 21:41:53 +020094 if (iommu_present(&platform_bus_type)) {
95 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +030096 if (!tegra->domain) {
97 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +020098 goto free;
99 }
100
Thierry Reding24cfdc12018-04-23 08:57:45 +0200101 err = iova_cache_get();
102 if (err < 0)
103 goto domain;
Thierry Redingdf06b752014-06-26 21:41:53 +0200104 }
105
Thierry Reding386a2a72013-09-24 13:22:17 +0200106 mutex_init(&tegra->clients_lock);
107 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100108
Thierry Reding386a2a72013-09-24 13:22:17 +0200109 drm->dev_private = tegra;
110 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000111
112 drm_mode_config_init(drm);
113
Thierry Redingf9914212014-11-26 13:03:57 +0100114 drm->mode_config.min_width = 0;
115 drm->mode_config.min_height = 0;
116
117 drm->mode_config.max_width = 4096;
118 drm->mode_config.max_height = 4096;
119
Alexandre Courbot5e911442016-11-08 16:50:42 +0900120 drm->mode_config.allow_fb_modifiers = true;
121
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200122 drm->mode_config.normalize_zpos = true;
123
Thierry Reding31b02ca2017-10-12 17:40:46 +0200124 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
125 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100126
Thierry Redinge2215321f2014-06-27 17:19:25 +0200127 err = tegra_drm_fb_prepare(drm);
128 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100129 goto config;
Thierry Redinge2215321f2014-06-27 17:19:25 +0200130
131 drm_kms_helper_poll_init(drm);
132
Thierry Reding776dc382013-10-14 14:43:22 +0200133 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000134 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100135 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000136
Thierry Redingb9f8b092019-02-01 14:28:33 +0100137 if (tegra->domain) {
138 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding02be8e42019-02-01 14:28:34 +0100139 u64 dma_mask = dma_get_mask(&device->dev);
Thierry Redingb9f8b092019-02-01 14:28:33 +0100140 dma_addr_t start, end;
141 unsigned long order;
142
Thierry Reding02be8e42019-02-01 14:28:34 +0100143 start = tegra->domain->geometry.aperture_start & dma_mask;
144 end = tegra->domain->geometry.aperture_end & dma_mask;
Thierry Redingb9f8b092019-02-01 14:28:33 +0100145
146 gem_start = start;
147 gem_end = end - CARVEOUT_SZ;
148 carveout_start = gem_end + 1;
149 carveout_end = end;
150
151 order = __ffs(tegra->domain->pgsize_bitmap);
152 init_iova_domain(&tegra->carveout.domain, 1UL << order,
153 carveout_start >> order);
154
155 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
156 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
157
158 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
159 mutex_init(&tegra->mm_lock);
160
161 DRM_DEBUG("IOMMU apertures:\n");
162 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
163 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
164 carveout_end);
165 }
166
Thierry Redingc4755fb2017-11-13 11:08:13 +0100167 if (tegra->hub) {
168 err = tegra_display_hub_prepare(tegra->hub);
169 if (err < 0)
170 goto device;
171 }
172
Thierry Reding603f0cc2013-04-22 21:22:14 +0200173 /*
174 * We don't use the drm_irq_install() helpers provided by the DRM
175 * core, so we need to set this manually in order to allow the
176 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
177 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300178 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200179
Thierry Reding42e9ce02015-01-28 14:43:05 +0100180 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100181 drm->max_vblank_count = 0xffffffff;
182
Thierry Reding6e5ff992012-11-28 11:45:47 +0100183 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
184 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100185 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100186
Thierry Reding31930d42015-07-02 17:04:06 +0200187 drm_mode_config_reset(drm);
188
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000189 err = tegra_drm_fb_init(drm);
190 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100191 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100194
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195hub:
196 if (tegra->hub)
197 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198device:
199 host1x_device_exit(device);
200fbdev:
201 drm_kms_helper_poll_fini(drm);
202 tegra_drm_fb_free(drm);
203config:
204 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200205
206 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100207 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200208 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200209 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200210 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200211 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200212domain:
213 if (tegra->domain)
214 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200215free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100216 kfree(tegra);
217 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218}
219
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200220static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221{
Thierry Reding776dc382013-10-14 14:43:22 +0200222 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200223 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200224 int err;
225
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000226 drm_kms_helper_poll_fini(drm);
227 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100228 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200229 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000230
Thierry Reding776dc382013-10-14 14:43:22 +0200231 err = host1x_device_exit(device);
232 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200233 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200234
Thierry Redingdf06b752014-06-26 21:41:53 +0200235 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100236 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200237 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200238 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200239 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200240 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200241 }
242
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100243 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000244}
245
246static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
247{
Thierry Reding08943e62013-09-26 16:08:18 +0200248 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200249
250 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
251 if (!fpriv)
252 return -ENOMEM;
253
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100254 idr_init(&fpriv->contexts);
255 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200256 filp->driver_priv = fpriv;
257
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000258 return 0;
259}
260
Thierry Redingc88c3632013-09-26 16:08:22 +0200261static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200262{
263 context->client->ops->close_channel(context);
264 kfree(context);
265}
266
Thierry Redingc40f0f12013-10-10 11:00:33 +0200267static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100268host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200269{
270 struct drm_gem_object *gem;
271 struct tegra_bo *bo;
272
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100273 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200274 if (!gem)
275 return NULL;
276
Thierry Redingc40f0f12013-10-10 11:00:33 +0200277 bo = to_tegra_bo(gem);
278 return &bo->base;
279}
280
Thierry Reding961e3be2014-06-10 10:25:00 +0200281static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
282 struct drm_tegra_reloc __user *src,
283 struct drm_device *drm,
284 struct drm_file *file)
285{
286 u32 cmdbuf, target;
287 int err;
288
289 err = get_user(cmdbuf, &src->cmdbuf.handle);
290 if (err < 0)
291 return err;
292
293 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
294 if (err < 0)
295 return err;
296
297 err = get_user(target, &src->target.handle);
298 if (err < 0)
299 return err;
300
David Ung31f40f82015-01-20 18:37:35 -0800301 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200302 if (err < 0)
303 return err;
304
305 err = get_user(dest->shift, &src->shift);
306 if (err < 0)
307 return err;
308
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100309 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200310 if (!dest->cmdbuf.bo)
311 return -ENOENT;
312
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100313 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200314 if (!dest->target.bo)
315 return -ENOENT;
316
317 return 0;
318}
319
Thierry Redingc40f0f12013-10-10 11:00:33 +0200320int tegra_drm_submit(struct tegra_drm_context *context,
321 struct drm_tegra_submit *args, struct drm_device *drm,
322 struct drm_file *file)
323{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200324 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200325 unsigned int num_cmdbufs = args->num_cmdbufs;
326 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300327 struct drm_tegra_cmdbuf __user *user_cmdbufs;
328 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300329 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200330 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300331 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200332 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300333 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200334 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200335 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200336 int err;
337
Mikko Perttunena176c672017-09-28 15:50:44 +0300338 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
339 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300340 user_syncpt = u64_to_user_ptr(args->syncpts);
341
Thierry Redingc40f0f12013-10-10 11:00:33 +0200342 /* We don't yet support other than one syncpt_incr struct per submit */
343 if (args->num_syncpts != 1)
344 return -EINVAL;
345
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300346 /* We don't yet support waitchks */
347 if (args->num_waitchks != 0)
348 return -EINVAL;
349
Thierry Redingc40f0f12013-10-10 11:00:33 +0200350 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200351 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200352 if (!job)
353 return -ENOMEM;
354
355 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200356 job->client = client;
357 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200358 job->serialize = true;
359
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200360 /*
361 * Track referenced BOs so that they can be unreferenced after the
362 * submission is complete.
363 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200364 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200365
366 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
367 if (!refs) {
368 err = -ENOMEM;
369 goto put;
370 }
371
372 /* reuse as an iterator later */
373 num_refs = 0;
374
Thierry Redingc40f0f12013-10-10 11:00:33 +0200375 while (num_cmdbufs) {
376 struct drm_tegra_cmdbuf cmdbuf;
377 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300378 struct tegra_bo *obj;
379 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200380
Mikko Perttunena176c672017-09-28 15:50:44 +0300381 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300382 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200383 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300384 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200385
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300386 /*
387 * The maximum number of CDMA gather fetches is 16383, a higher
388 * value means the words count is malformed.
389 */
390 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
391 err = -EINVAL;
392 goto fail;
393 }
394
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100395 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200396 if (!bo) {
397 err = -ENOENT;
398 goto fail;
399 }
400
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300401 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
402 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200403 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300404
405 /*
406 * Gather buffer base address must be 4-bytes aligned,
407 * unaligned offset is malformed and cause commands stream
408 * corruption on the buffer address relocation.
409 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300410 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300411 err = -EINVAL;
412 goto fail;
413 }
414
Thierry Redingc40f0f12013-10-10 11:00:33 +0200415 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
416 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300417 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200418 }
419
Thierry Reding961e3be2014-06-10 10:25:00 +0200420 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200421 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300422 struct host1x_reloc *reloc;
423 struct tegra_bo *obj;
424
Thierry Reding06490bb2018-05-16 16:58:44 +0200425 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300426 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200427 file);
428 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200429 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300430
Thierry Reding06490bb2018-05-16 16:58:44 +0200431 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300432 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200433 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300434
435 /*
436 * The unaligned cmdbuf offset will cause an unaligned write
437 * during of the relocations patching, corrupting the commands
438 * stream.
439 */
440 if (reloc->cmdbuf.offset & 3 ||
441 reloc->cmdbuf.offset >= obj->gem.size) {
442 err = -EINVAL;
443 goto fail;
444 }
445
446 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200447 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300448
449 if (reloc->target.offset >= obj->gem.size) {
450 err = -EINVAL;
451 goto fail;
452 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200453 }
454
Mikko Perttunena176c672017-09-28 15:50:44 +0300455 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300456 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200457 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300458 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200459
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300460 /* check whether syncpoint ID is valid */
461 sp = host1x_syncpt_get(host1x, syncpt.id);
462 if (!sp) {
463 err = -ENOENT;
464 goto fail;
465 }
466
Thierry Redingc40f0f12013-10-10 11:00:33 +0200467 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300468 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200469 job->syncpt_incrs = syncpt.incrs;
470 job->syncpt_id = syncpt.id;
471 job->timeout = 10000;
472
473 if (args->timeout && args->timeout < 10000)
474 job->timeout = args->timeout;
475
476 err = host1x_job_pin(job, context->client->base.dev);
477 if (err)
478 goto fail;
479
480 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200481 if (err) {
482 host1x_job_unpin(job);
483 goto fail;
484 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200485
486 args->fence = job->syncpt_end;
487
Thierry Redingc40f0f12013-10-10 11:00:33 +0200488fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200489 while (num_refs--)
490 drm_gem_object_put_unlocked(refs[num_refs]);
491
492 kfree(refs);
493
494put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200495 host1x_job_put(job);
496 return err;
497}
498
499
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200500#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200501static int tegra_gem_create(struct drm_device *drm, void *data,
502 struct drm_file *file)
503{
504 struct drm_tegra_gem_create *args = data;
505 struct tegra_bo *bo;
506
Thierry Reding773af772013-10-04 22:34:01 +0200507 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200508 &args->handle);
509 if (IS_ERR(bo))
510 return PTR_ERR(bo);
511
512 return 0;
513}
514
515static int tegra_gem_mmap(struct drm_device *drm, void *data,
516 struct drm_file *file)
517{
518 struct drm_tegra_gem_mmap *args = data;
519 struct drm_gem_object *gem;
520 struct tegra_bo *bo;
521
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100522 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200523 if (!gem)
524 return -EINVAL;
525
526 bo = to_tegra_bo(gem);
527
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200528 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200529
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300530 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200531
532 return 0;
533}
534
535static int tegra_syncpt_read(struct drm_device *drm, void *data,
536 struct drm_file *file)
537{
Thierry Reding776dc382013-10-14 14:43:22 +0200538 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200539 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200540 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200541
Thierry Reding776dc382013-10-14 14:43:22 +0200542 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200543 if (!sp)
544 return -EINVAL;
545
546 args->value = host1x_syncpt_read_min(sp);
547 return 0;
548}
549
550static int tegra_syncpt_incr(struct drm_device *drm, void *data,
551 struct drm_file *file)
552{
Thierry Reding776dc382013-10-14 14:43:22 +0200553 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200554 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200555 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200556
Thierry Reding776dc382013-10-14 14:43:22 +0200557 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200558 if (!sp)
559 return -EINVAL;
560
Arto Merilainenebae30b2013-05-29 13:26:08 +0300561 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200562}
563
564static int tegra_syncpt_wait(struct drm_device *drm, void *data,
565 struct drm_file *file)
566{
Thierry Reding776dc382013-10-14 14:43:22 +0200567 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200568 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200569 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200570
Thierry Reding776dc382013-10-14 14:43:22 +0200571 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200572 if (!sp)
573 return -EINVAL;
574
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300575 return host1x_syncpt_wait(sp, args->thresh,
576 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200577 &args->value);
578}
579
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100580static int tegra_client_open(struct tegra_drm_file *fpriv,
581 struct tegra_drm_client *client,
582 struct tegra_drm_context *context)
583{
584 int err;
585
586 err = client->ops->open_channel(client, context);
587 if (err < 0)
588 return err;
589
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300590 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100591 if (err < 0) {
592 client->ops->close_channel(context);
593 return err;
594 }
595
596 context->client = client;
597 context->id = err;
598
599 return 0;
600}
601
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200602static int tegra_open_channel(struct drm_device *drm, void *data,
603 struct drm_file *file)
604{
Thierry Reding08943e62013-09-26 16:08:18 +0200605 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200606 struct tegra_drm *tegra = drm->dev_private;
607 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200608 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200609 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200610 int err = -ENODEV;
611
612 context = kzalloc(sizeof(*context), GFP_KERNEL);
613 if (!context)
614 return -ENOMEM;
615
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100616 mutex_lock(&fpriv->lock);
617
Thierry Reding776dc382013-10-14 14:43:22 +0200618 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200619 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100620 err = tegra_client_open(fpriv, client, context);
621 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200622 break;
623
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100624 args->context = context->id;
625 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200626 }
627
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100628 if (err < 0)
629 kfree(context);
630
631 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200632 return err;
633}
634
635static int tegra_close_channel(struct drm_device *drm, void *data,
636 struct drm_file *file)
637{
Thierry Reding08943e62013-09-26 16:08:18 +0200638 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200639 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200640 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100641 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200642
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100643 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200644
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300645 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100646 if (!context) {
647 err = -EINVAL;
648 goto unlock;
649 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200650
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100651 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200652 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200653
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100654unlock:
655 mutex_unlock(&fpriv->lock);
656 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657}
658
659static int tegra_get_syncpt(struct drm_device *drm, void *data,
660 struct drm_file *file)
661{
Thierry Reding08943e62013-09-26 16:08:18 +0200662 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200663 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200664 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200665 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100666 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200667
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100668 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200669
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300670 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100671 if (!context) {
672 err = -ENODEV;
673 goto unlock;
674 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200675
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100676 if (args->index >= context->client->base.num_syncpts) {
677 err = -EINVAL;
678 goto unlock;
679 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200680
Thierry Reding53fa7f72013-09-24 15:35:40 +0200681 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200682 args->id = host1x_syncpt_id(syncpt);
683
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100684unlock:
685 mutex_unlock(&fpriv->lock);
686 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200687}
688
689static int tegra_submit(struct drm_device *drm, void *data,
690 struct drm_file *file)
691{
Thierry Reding08943e62013-09-26 16:08:18 +0200692 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200693 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200694 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100695 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200696
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100697 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200698
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300699 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100700 if (!context) {
701 err = -ENODEV;
702 goto unlock;
703 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200704
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100705 err = context->client->ops->submit(context, args, drm, file);
706
707unlock:
708 mutex_unlock(&fpriv->lock);
709 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200710}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300711
712static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
713 struct drm_file *file)
714{
715 struct tegra_drm_file *fpriv = file->driver_priv;
716 struct drm_tegra_get_syncpt_base *args = data;
717 struct tegra_drm_context *context;
718 struct host1x_syncpt_base *base;
719 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100720 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300721
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100722 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300723
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300724 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100725 if (!context) {
726 err = -ENODEV;
727 goto unlock;
728 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300729
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100730 if (args->syncpt >= context->client->base.num_syncpts) {
731 err = -EINVAL;
732 goto unlock;
733 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300734
735 syncpt = context->client->base.syncpts[args->syncpt];
736
737 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100738 if (!base) {
739 err = -ENXIO;
740 goto unlock;
741 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300742
743 args->id = host1x_syncpt_base_id(base);
744
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100745unlock:
746 mutex_unlock(&fpriv->lock);
747 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300748}
Thierry Reding7678d712014-06-03 14:56:57 +0200749
750static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
751 struct drm_file *file)
752{
753 struct drm_tegra_gem_set_tiling *args = data;
754 enum tegra_bo_tiling_mode mode;
755 struct drm_gem_object *gem;
756 unsigned long value = 0;
757 struct tegra_bo *bo;
758
759 switch (args->mode) {
760 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
761 mode = TEGRA_BO_TILING_MODE_PITCH;
762
763 if (args->value != 0)
764 return -EINVAL;
765
766 break;
767
768 case DRM_TEGRA_GEM_TILING_MODE_TILED:
769 mode = TEGRA_BO_TILING_MODE_TILED;
770
771 if (args->value != 0)
772 return -EINVAL;
773
774 break;
775
776 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
777 mode = TEGRA_BO_TILING_MODE_BLOCK;
778
779 if (args->value > 5)
780 return -EINVAL;
781
782 value = args->value;
783 break;
784
785 default:
786 return -EINVAL;
787 }
788
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100789 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200790 if (!gem)
791 return -ENOENT;
792
793 bo = to_tegra_bo(gem);
794
795 bo->tiling.mode = mode;
796 bo->tiling.value = value;
797
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300798 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200799
800 return 0;
801}
802
803static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
804 struct drm_file *file)
805{
806 struct drm_tegra_gem_get_tiling *args = data;
807 struct drm_gem_object *gem;
808 struct tegra_bo *bo;
809 int err = 0;
810
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100811 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200812 if (!gem)
813 return -ENOENT;
814
815 bo = to_tegra_bo(gem);
816
817 switch (bo->tiling.mode) {
818 case TEGRA_BO_TILING_MODE_PITCH:
819 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
820 args->value = 0;
821 break;
822
823 case TEGRA_BO_TILING_MODE_TILED:
824 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
825 args->value = 0;
826 break;
827
828 case TEGRA_BO_TILING_MODE_BLOCK:
829 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
830 args->value = bo->tiling.value;
831 break;
832
833 default:
834 err = -EINVAL;
835 break;
836 }
837
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300838 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200839
840 return err;
841}
Thierry Reding7b129082014-06-10 12:04:03 +0200842
843static int tegra_gem_set_flags(struct drm_device *drm, void *data,
844 struct drm_file *file)
845{
846 struct drm_tegra_gem_set_flags *args = data;
847 struct drm_gem_object *gem;
848 struct tegra_bo *bo;
849
850 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
851 return -EINVAL;
852
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100853 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200854 if (!gem)
855 return -ENOENT;
856
857 bo = to_tegra_bo(gem);
858 bo->flags = 0;
859
860 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
861 bo->flags |= TEGRA_BO_BOTTOM_UP;
862
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300863 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200864
865 return 0;
866}
867
868static int tegra_gem_get_flags(struct drm_device *drm, void *data,
869 struct drm_file *file)
870{
871 struct drm_tegra_gem_get_flags *args = data;
872 struct drm_gem_object *gem;
873 struct tegra_bo *bo;
874
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100875 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200876 if (!gem)
877 return -ENOENT;
878
879 bo = to_tegra_bo(gem);
880 args->flags = 0;
881
882 if (bo->flags & TEGRA_BO_BOTTOM_UP)
883 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
884
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300885 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200886
887 return 0;
888}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200889#endif
890
Rob Clarkbaa70942013-08-02 13:27:49 -0400891static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200892#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200893 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
894 DRM_UNLOCKED | DRM_RENDER_ALLOW),
895 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
896 DRM_UNLOCKED | DRM_RENDER_ALLOW),
897 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
898 DRM_UNLOCKED | DRM_RENDER_ALLOW),
899 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
900 DRM_UNLOCKED | DRM_RENDER_ALLOW),
901 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
902 DRM_UNLOCKED | DRM_RENDER_ALLOW),
903 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
904 DRM_UNLOCKED | DRM_RENDER_ALLOW),
905 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
906 DRM_UNLOCKED | DRM_RENDER_ALLOW),
907 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
908 DRM_UNLOCKED | DRM_RENDER_ALLOW),
909 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
910 DRM_UNLOCKED | DRM_RENDER_ALLOW),
911 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
912 DRM_UNLOCKED | DRM_RENDER_ALLOW),
913 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
914 DRM_UNLOCKED | DRM_RENDER_ALLOW),
915 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
916 DRM_UNLOCKED | DRM_RENDER_ALLOW),
917 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
918 DRM_UNLOCKED | DRM_RENDER_ALLOW),
919 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
920 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200921#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000922};
923
924static const struct file_operations tegra_drm_fops = {
925 .owner = THIS_MODULE,
926 .open = drm_open,
927 .release = drm_release,
928 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200929 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000930 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000931 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000932 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000933 .llseek = noop_llseek,
934};
935
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100936static int tegra_drm_context_cleanup(int id, void *p, void *data)
937{
938 struct tegra_drm_context *context = p;
939
940 tegra_drm_context_free(context);
941
942 return 0;
943}
944
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200945static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100946{
Thierry Reding08943e62013-09-26 16:08:18 +0200947 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100948
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100949 mutex_lock(&fpriv->lock);
950 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
951 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200952
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100953 idr_destroy(&fpriv->contexts);
954 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200955 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100956}
957
Thierry Redinge450fcc2013-02-13 16:13:16 +0100958#ifdef CONFIG_DEBUG_FS
959static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
960{
961 struct drm_info_node *node = (struct drm_info_node *)s->private;
962 struct drm_device *drm = node->minor->dev;
963 struct drm_framebuffer *fb;
964
965 mutex_lock(&drm->mode_config.fb_lock);
966
967 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
968 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200969 fb->base.id, fb->width, fb->height,
970 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200971 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000972 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100973 }
974
975 mutex_unlock(&drm->mode_config.fb_lock);
976
977 return 0;
978}
979
Thierry Reding28c23372015-01-23 09:16:03 +0100980static int tegra_debugfs_iova(struct seq_file *s, void *data)
981{
982 struct drm_info_node *node = (struct drm_info_node *)s->private;
983 struct drm_device *drm = node->minor->dev;
984 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100985 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100986
Michał Mirosław68d890a2017-08-14 23:53:45 +0200987 if (tegra->domain) {
988 mutex_lock(&tegra->mm_lock);
989 drm_mm_print(&tegra->mm, &p);
990 mutex_unlock(&tegra->mm_lock);
991 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100992
993 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100994}
995
Thierry Redinge450fcc2013-02-13 16:13:16 +0100996static struct drm_info_list tegra_debugfs_list[] = {
997 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100998 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100999};
1000
1001static int tegra_debugfs_init(struct drm_minor *minor)
1002{
1003 return drm_debugfs_create_files(tegra_debugfs_list,
1004 ARRAY_SIZE(tegra_debugfs_list),
1005 minor->debugfs_root, minor);
1006}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001007#endif
1008
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001009static struct drm_driver tegra_drm_driver = {
Daniel Vetter0424fda2019-06-17 17:39:24 +02001010 .driver_features = DRIVER_MODESET | DRIVER_GEM |
Thierry Reding6c68b712017-08-15 15:42:39 +02001011 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001012 .load = tegra_drm_load,
1013 .unload = tegra_drm_unload,
1014 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001015 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001016 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001017
Thierry Redinge450fcc2013-02-13 16:13:16 +01001018#if defined(CONFIG_DEBUG_FS)
1019 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001020#endif
1021
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001022 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001023 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001024
1025 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1026 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1027 .gem_prime_export = tegra_gem_prime_export,
1028 .gem_prime_import = tegra_gem_prime_import,
1029
Arto Merilainende2ba662013-03-22 16:34:08 +02001030 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001031
1032 .ioctls = tegra_drm_ioctls,
1033 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1034 .fops = &tegra_drm_fops,
1035
1036 .name = DRIVER_NAME,
1037 .desc = DRIVER_DESC,
1038 .date = DRIVER_DATE,
1039 .major = DRIVER_MAJOR,
1040 .minor = DRIVER_MINOR,
1041 .patchlevel = DRIVER_PATCHLEVEL,
1042};
Thierry Reding776dc382013-10-14 14:43:22 +02001043
1044int tegra_drm_register_client(struct tegra_drm *tegra,
1045 struct tegra_drm_client *client)
1046{
1047 mutex_lock(&tegra->clients_lock);
1048 list_add_tail(&client->list, &tegra->clients);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001049 client->drm = tegra;
Thierry Reding776dc382013-10-14 14:43:22 +02001050 mutex_unlock(&tegra->clients_lock);
1051
1052 return 0;
1053}
1054
1055int tegra_drm_unregister_client(struct tegra_drm *tegra,
1056 struct tegra_drm_client *client)
1057{
1058 mutex_lock(&tegra->clients_lock);
1059 list_del_init(&client->list);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001060 client->drm = NULL;
Thierry Reding776dc382013-10-14 14:43:22 +02001061 mutex_unlock(&tegra->clients_lock);
1062
1063 return 0;
1064}
1065
Thierry Reding0c407de2018-05-04 15:02:24 +02001066struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1067 bool shared)
1068{
1069 struct drm_device *drm = dev_get_drvdata(client->parent);
1070 struct tegra_drm *tegra = drm->dev_private;
1071 struct iommu_group *group = NULL;
1072 int err;
1073
1074 if (tegra->domain) {
1075 group = iommu_group_get(client->dev);
1076 if (!group) {
1077 dev_err(client->dev, "failed to get IOMMU group\n");
1078 return ERR_PTR(-ENODEV);
1079 }
1080
1081 if (!shared || (shared && (group != tegra->group))) {
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +03001082#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
1083 if (client->dev->archdata.mapping) {
1084 struct dma_iommu_mapping *mapping =
1085 to_dma_iommu_mapping(client->dev);
1086 arm_iommu_detach_device(client->dev);
1087 arm_iommu_release_mapping(mapping);
1088 }
1089#endif
Thierry Reding0c407de2018-05-04 15:02:24 +02001090 err = iommu_attach_group(tegra->domain, group);
1091 if (err < 0) {
1092 iommu_group_put(group);
1093 return ERR_PTR(err);
1094 }
1095
1096 if (shared && !tegra->group)
1097 tegra->group = group;
1098 }
1099 }
1100
1101 return group;
1102}
1103
1104void host1x_client_iommu_detach(struct host1x_client *client,
1105 struct iommu_group *group)
1106{
1107 struct drm_device *drm = dev_get_drvdata(client->parent);
1108 struct tegra_drm *tegra = drm->dev_private;
1109
1110 if (group) {
1111 if (group == tegra->group) {
1112 iommu_detach_group(tegra->domain, group);
1113 tegra->group = NULL;
1114 }
1115
1116 iommu_group_put(group);
1117 }
1118}
1119
Thierry Reding67485fb2017-11-09 13:17:11 +01001120void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001121{
1122 struct iova *alloc;
1123 void *virt;
1124 gfp_t gfp;
1125 int err;
1126
1127 if (tegra->domain)
1128 size = iova_align(&tegra->carveout.domain, size);
1129 else
1130 size = PAGE_ALIGN(size);
1131
1132 gfp = GFP_KERNEL | __GFP_ZERO;
1133 if (!tegra->domain) {
1134 /*
1135 * Many units only support 32-bit addresses, even on 64-bit
1136 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1137 * virtual address space, force allocations to be in the
1138 * lower 32-bit range.
1139 */
1140 gfp |= GFP_DMA;
1141 }
1142
1143 virt = (void *)__get_free_pages(gfp, get_order(size));
1144 if (!virt)
1145 return ERR_PTR(-ENOMEM);
1146
1147 if (!tegra->domain) {
1148 /*
1149 * If IOMMU is disabled, devices address physical memory
1150 * directly.
1151 */
1152 *dma = virt_to_phys(virt);
1153 return virt;
1154 }
1155
1156 alloc = alloc_iova(&tegra->carveout.domain,
1157 size >> tegra->carveout.shift,
1158 tegra->carveout.limit, true);
1159 if (!alloc) {
1160 err = -EBUSY;
1161 goto free_pages;
1162 }
1163
1164 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1165 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1166 size, IOMMU_READ | IOMMU_WRITE);
1167 if (err < 0)
1168 goto free_iova;
1169
1170 return virt;
1171
1172free_iova:
1173 __free_iova(&tegra->carveout.domain, alloc);
1174free_pages:
1175 free_pages((unsigned long)virt, get_order(size));
1176
1177 return ERR_PTR(err);
1178}
1179
1180void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1181 dma_addr_t dma)
1182{
1183 if (tegra->domain)
1184 size = iova_align(&tegra->carveout.domain, size);
1185 else
1186 size = PAGE_ALIGN(size);
1187
1188 if (tegra->domain) {
1189 iommu_unmap(tegra->domain, dma, size);
1190 free_iova(&tegra->carveout.domain,
1191 iova_pfn(&tegra->carveout.domain, dma));
1192 }
1193
1194 free_pages((unsigned long)virt, get_order(size));
1195}
1196
Thierry Reding9910f5c2014-05-22 09:57:15 +02001197static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001198{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001199 struct drm_driver *driver = &tegra_drm_driver;
1200 struct drm_device *drm;
1201 int err;
1202
1203 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001204 if (IS_ERR(drm))
1205 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001206
Thierry Reding9910f5c2014-05-22 09:57:15 +02001207 dev_set_drvdata(&dev->dev, drm);
1208
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001209 err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
1210 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001211 goto put;
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001212
Thierry Reding9910f5c2014-05-22 09:57:15 +02001213 err = drm_dev_register(drm, 0);
1214 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001215 goto put;
Thierry Reding9910f5c2014-05-22 09:57:15 +02001216
Thierry Reding9910f5c2014-05-22 09:57:15 +02001217 return 0;
1218
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001219put:
1220 drm_dev_put(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001221 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001222}
1223
Thierry Reding9910f5c2014-05-22 09:57:15 +02001224static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001225{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001226 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1227
1228 drm_dev_unregister(drm);
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001229 drm_dev_put(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001230
1231 return 0;
1232}
1233
Thierry Reding359ae682014-12-18 17:15:25 +01001234#ifdef CONFIG_PM_SLEEP
1235static int host1x_drm_suspend(struct device *dev)
1236{
1237 struct drm_device *drm = dev_get_drvdata(dev);
1238
Souptick Joarder53f1e062018-08-01 01:37:05 +05301239 return drm_mode_config_helper_suspend(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001240}
1241
1242static int host1x_drm_resume(struct device *dev)
1243{
1244 struct drm_device *drm = dev_get_drvdata(dev);
1245
Souptick Joarder53f1e062018-08-01 01:37:05 +05301246 return drm_mode_config_helper_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001247}
1248#endif
1249
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001250static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1251 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001252
Thierry Reding776dc382013-10-14 14:43:22 +02001253static const struct of_device_id host1x_drm_subdevs[] = {
1254 { .compatible = "nvidia,tegra20-dc", },
1255 { .compatible = "nvidia,tegra20-hdmi", },
1256 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001257 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001258 { .compatible = "nvidia,tegra30-dc", },
1259 { .compatible = "nvidia,tegra30-hdmi", },
1260 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001261 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001262 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001263 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001264 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001265 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001266 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001267 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001268 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001269 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001270 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001271 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001272 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001273 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001274 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001275 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001276 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001277 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001278 { .compatible = "nvidia,tegra186-sor", },
1279 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001280 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding5725daa2018-09-21 12:27:43 +02001281 { .compatible = "nvidia,tegra194-display", },
Thierry Reding47443192018-09-21 12:27:44 +02001282 { .compatible = "nvidia,tegra194-dc", },
Thierry Reding9b6c14b2018-09-21 12:27:46 +02001283 { .compatible = "nvidia,tegra194-sor", },
Thierry Redingd6b9bc02018-10-26 10:59:38 +02001284 { .compatible = "nvidia,tegra194-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001285 { /* sentinel */ }
1286};
1287
1288static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001289 .driver = {
1290 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001291 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001292 },
Thierry Reding776dc382013-10-14 14:43:22 +02001293 .probe = host1x_drm_probe,
1294 .remove = host1x_drm_remove,
1295 .subdevs = host1x_drm_subdevs,
1296};
1297
Thierry Reding473112e2015-09-10 16:07:14 +02001298static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001299 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001300 &tegra_dc_driver,
1301 &tegra_hdmi_driver,
1302 &tegra_dsi_driver,
1303 &tegra_dpaux_driver,
1304 &tegra_sor_driver,
1305 &tegra_gr2d_driver,
1306 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001307 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001308};
1309
Thierry Reding776dc382013-10-14 14:43:22 +02001310static int __init host1x_drm_init(void)
1311{
1312 int err;
1313
1314 err = host1x_driver_register(&host1x_drm_driver);
1315 if (err < 0)
1316 return err;
1317
Thierry Reding473112e2015-09-10 16:07:14 +02001318 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001319 if (err < 0)
1320 goto unregister_host1x;
1321
Thierry Reding776dc382013-10-14 14:43:22 +02001322 return 0;
1323
Thierry Reding776dc382013-10-14 14:43:22 +02001324unregister_host1x:
1325 host1x_driver_unregister(&host1x_drm_driver);
1326 return err;
1327}
1328module_init(host1x_drm_init);
1329
1330static void __exit host1x_drm_exit(void)
1331{
Thierry Reding473112e2015-09-10 16:07:14 +02001332 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001333 host1x_driver_unregister(&host1x_drm_driver);
1334}
1335module_exit(host1x_drm_exit);
1336
1337MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1338MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1339MODULE_LICENSE("GPL v2");