blob: de1d122ba8202a558e463af95cbf39704de97da8 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding1503ca42014-11-24 17:41:23 +010036static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010065 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080066 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010068
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010072 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010073}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020084 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010085{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020093 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010094 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
Maarten Lankhorst424624e2017-07-11 16:33:10 +0200103 err = drm_atomic_helper_swap_state(state, true);
104 if (err) {
105 mutex_unlock(&tegra->commit.lock);
106 drm_atomic_helper_cleanup_planes(drm, state);
107 return err;
108 }
Thierry Reding1503ca42014-11-24 17:41:23 +0100109
Chris Wilson08536952016-10-14 13:18:18 +0100110 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200111 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100112 tegra_atomic_schedule(tegra, state);
113 else
114 tegra_atomic_complete(tegra, state);
115
116 mutex_unlock(&tegra->commit.lock);
117 return 0;
118}
119
Thierry Redingf9914212014-11-26 13:03:57 +0100120static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
121 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530122#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100123 .output_poll_changed = tegra_fb_output_poll_changed,
124#endif
Thierry Reding07866962014-11-24 17:08:06 +0100125 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100126 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100127};
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000130{
Thierry Reding776dc382013-10-14 14:43:22 +0200131 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200132 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000133 int err;
134
Thierry Reding776dc382013-10-14 14:43:22 +0200135 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200136 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200137 return -ENOMEM;
138
Thierry Redingdf06b752014-06-26 21:41:53 +0200139 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200140 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100141 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200142 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100143
Thierry Redingdf06b752014-06-26 21:41:53 +0200144 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300145 if (!tegra->domain) {
146 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200147 goto free;
148 }
149
Thierry Reding4553f732015-01-19 16:15:04 +0100150 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200151 gem_start = geometry->aperture_start;
152 gem_end = geometry->aperture_end - CARVEOUT_SZ;
153 carveout_start = gem_end + 1;
154 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100155
Mikko Perttunenad926012016-12-14 13:16:11 +0200156 order = __ffs(tegra->domain->pgsize_bitmap);
157 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100158 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200159
160 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
161 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
162
163 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100164 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200165
166 DRM_DEBUG("IOMMU apertures:\n");
167 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
168 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
169 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200170 }
171
Thierry Reding386a2a72013-09-24 13:22:17 +0200172 mutex_init(&tegra->clients_lock);
173 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100174
175 mutex_init(&tegra->commit.lock);
176 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
177
Thierry Reding386a2a72013-09-24 13:22:17 +0200178 drm->dev_private = tegra;
179 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000180
181 drm_mode_config_init(drm);
182
Thierry Redingf9914212014-11-26 13:03:57 +0100183 drm->mode_config.min_width = 0;
184 drm->mode_config.min_height = 0;
185
186 drm->mode_config.max_width = 4096;
187 drm->mode_config.max_height = 4096;
188
Alexandre Courbot5e911442016-11-08 16:50:42 +0900189 drm->mode_config.allow_fb_modifiers = true;
190
Thierry Redingf9914212014-11-26 13:03:57 +0100191 drm->mode_config.funcs = &tegra_drm_mode_funcs;
192
Thierry Redinge2215321f2014-06-27 17:19:25 +0200193 err = tegra_drm_fb_prepare(drm);
194 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100195 goto config;
Thierry Redinge2215321f2014-06-27 17:19:25 +0200196
197 drm_kms_helper_poll_init(drm);
198
Thierry Reding776dc382013-10-14 14:43:22 +0200199 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000200 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100201 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000202
Thierry Reding603f0cc2013-04-22 21:22:14 +0200203 /*
204 * We don't use the drm_irq_install() helpers provided by the DRM
205 * core, so we need to set this manually in order to allow the
206 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
207 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300208 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200209
Thierry Reding42e9ce02015-01-28 14:43:05 +0100210 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100211 drm->max_vblank_count = 0xffffffff;
212
Thierry Reding6e5ff992012-11-28 11:45:47 +0100213 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
214 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100215 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100216
Thierry Reding31930d42015-07-02 17:04:06 +0200217 drm_mode_config_reset(drm);
218
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000219 err = tegra_drm_fb_init(drm);
220 if (err < 0)
Daniel Vetter00a91212017-05-24 16:52:08 +0200221 goto device;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000222
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100224
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100225device:
226 host1x_device_exit(device);
227fbdev:
228 drm_kms_helper_poll_fini(drm);
229 tegra_drm_fb_free(drm);
230config:
231 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200232
233 if (tegra->domain) {
234 iommu_domain_free(tegra->domain);
235 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100236 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200237 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200238 }
239free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100240 kfree(tegra);
241 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000242}
243
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200244static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000245{
Thierry Reding776dc382013-10-14 14:43:22 +0200246 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200247 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200248 int err;
249
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000250 drm_kms_helper_poll_fini(drm);
251 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200252 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000253
Thierry Reding776dc382013-10-14 14:43:22 +0200254 err = host1x_device_exit(device);
255 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200256 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200257
Thierry Redingdf06b752014-06-26 21:41:53 +0200258 if (tegra->domain) {
259 iommu_domain_free(tegra->domain);
260 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100261 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200262 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200263 }
264
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100265 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000266}
267
268static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
269{
Thierry Reding08943e62013-09-26 16:08:18 +0200270 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200271
272 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
273 if (!fpriv)
274 return -ENOMEM;
275
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100276 idr_init(&fpriv->contexts);
277 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200278 filp->driver_priv = fpriv;
279
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000280 return 0;
281}
282
Thierry Redingc88c3632013-09-26 16:08:22 +0200283static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200284{
285 context->client->ops->close_channel(context);
286 kfree(context);
287}
288
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000289static void tegra_drm_lastclose(struct drm_device *drm)
290{
Archit Tanejab110ef32015-10-27 13:40:59 +0530291#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200292 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000293
Thierry Reding386a2a72013-09-24 13:22:17 +0200294 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100295#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000296}
297
Thierry Redingc40f0f12013-10-10 11:00:33 +0200298static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100299host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200300{
301 struct drm_gem_object *gem;
302 struct tegra_bo *bo;
303
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100304 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200305 if (!gem)
306 return NULL;
307
Thierry Redingc40f0f12013-10-10 11:00:33 +0200308 bo = to_tegra_bo(gem);
309 return &bo->base;
310}
311
Thierry Reding961e3be2014-06-10 10:25:00 +0200312static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
313 struct drm_tegra_reloc __user *src,
314 struct drm_device *drm,
315 struct drm_file *file)
316{
317 u32 cmdbuf, target;
318 int err;
319
320 err = get_user(cmdbuf, &src->cmdbuf.handle);
321 if (err < 0)
322 return err;
323
324 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
325 if (err < 0)
326 return err;
327
328 err = get_user(target, &src->target.handle);
329 if (err < 0)
330 return err;
331
David Ung31f40f82015-01-20 18:37:35 -0800332 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200333 if (err < 0)
334 return err;
335
336 err = get_user(dest->shift, &src->shift);
337 if (err < 0)
338 return err;
339
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100340 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200341 if (!dest->cmdbuf.bo)
342 return -ENOENT;
343
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100344 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200345 if (!dest->target.bo)
346 return -ENOENT;
347
348 return 0;
349}
350
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300351static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
352 struct drm_tegra_waitchk __user *src,
353 struct drm_file *file)
354{
355 u32 cmdbuf;
356 int err;
357
358 err = get_user(cmdbuf, &src->handle);
359 if (err < 0)
360 return err;
361
362 err = get_user(dest->offset, &src->offset);
363 if (err < 0)
364 return err;
365
366 err = get_user(dest->syncpt_id, &src->syncpt);
367 if (err < 0)
368 return err;
369
370 err = get_user(dest->thresh, &src->thresh);
371 if (err < 0)
372 return err;
373
374 dest->bo = host1x_bo_lookup(file, cmdbuf);
375 if (!dest->bo)
376 return -ENOENT;
377
378 return 0;
379}
380
Thierry Redingc40f0f12013-10-10 11:00:33 +0200381int tegra_drm_submit(struct tegra_drm_context *context,
382 struct drm_tegra_submit *args, struct drm_device *drm,
383 struct drm_file *file)
384{
385 unsigned int num_cmdbufs = args->num_cmdbufs;
386 unsigned int num_relocs = args->num_relocs;
387 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300388 struct drm_tegra_cmdbuf __user *user_cmdbufs;
389 struct drm_tegra_reloc __user *user_relocs;
390 struct drm_tegra_waitchk __user *user_waitchks;
391 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200392 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300393 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200394 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300395 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200396 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200397 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200398 int err;
399
Mikko Perttunena176c672017-09-28 15:50:44 +0300400 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
401 user_relocs = u64_to_user_ptr(args->relocs);
402 user_waitchks = u64_to_user_ptr(args->waitchks);
403 user_syncpt = u64_to_user_ptr(args->syncpts);
404
Thierry Redingc40f0f12013-10-10 11:00:33 +0200405 /* We don't yet support other than one syncpt_incr struct per submit */
406 if (args->num_syncpts != 1)
407 return -EINVAL;
408
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300409 /* We don't yet support waitchks */
410 if (args->num_waitchks != 0)
411 return -EINVAL;
412
Thierry Redingc40f0f12013-10-10 11:00:33 +0200413 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
414 args->num_relocs, args->num_waitchks);
415 if (!job)
416 return -ENOMEM;
417
418 job->num_relocs = args->num_relocs;
419 job->num_waitchk = args->num_waitchks;
420 job->client = (u32)args->context;
421 job->class = context->client->base.class;
422 job->serialize = true;
423
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200424 /*
425 * Track referenced BOs so that they can be unreferenced after the
426 * submission is complete.
427 */
428 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
429
430 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
431 if (!refs) {
432 err = -ENOMEM;
433 goto put;
434 }
435
436 /* reuse as an iterator later */
437 num_refs = 0;
438
Thierry Redingc40f0f12013-10-10 11:00:33 +0200439 while (num_cmdbufs) {
440 struct drm_tegra_cmdbuf cmdbuf;
441 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300442 struct tegra_bo *obj;
443 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200444
Mikko Perttunena176c672017-09-28 15:50:44 +0300445 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300446 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200447 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300448 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200449
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300450 /*
451 * The maximum number of CDMA gather fetches is 16383, a higher
452 * value means the words count is malformed.
453 */
454 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
455 err = -EINVAL;
456 goto fail;
457 }
458
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100459 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200460 if (!bo) {
461 err = -ENOENT;
462 goto fail;
463 }
464
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300465 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
466 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200467 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300468
469 /*
470 * Gather buffer base address must be 4-bytes aligned,
471 * unaligned offset is malformed and cause commands stream
472 * corruption on the buffer address relocation.
473 */
474 if (offset & 3 || offset >= obj->gem.size) {
475 err = -EINVAL;
476 goto fail;
477 }
478
Thierry Redingc40f0f12013-10-10 11:00:33 +0200479 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
480 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300481 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200482 }
483
Thierry Reding961e3be2014-06-10 10:25:00 +0200484 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200485 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300486 struct host1x_reloc *reloc;
487 struct tegra_bo *obj;
488
Thierry Reding961e3be2014-06-10 10:25:00 +0200489 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300490 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200491 file);
492 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200493 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300494
495 reloc = &job->relocarray[num_relocs];
496 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200497 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300498
499 /*
500 * The unaligned cmdbuf offset will cause an unaligned write
501 * during of the relocations patching, corrupting the commands
502 * stream.
503 */
504 if (reloc->cmdbuf.offset & 3 ||
505 reloc->cmdbuf.offset >= obj->gem.size) {
506 err = -EINVAL;
507 goto fail;
508 }
509
510 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200511 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300512
513 if (reloc->target.offset >= obj->gem.size) {
514 err = -EINVAL;
515 goto fail;
516 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200517 }
518
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300519 /* copy and resolve waitchks from submit */
520 while (num_waitchks--) {
521 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
522 struct tegra_bo *obj;
523
Mikko Perttunena176c672017-09-28 15:50:44 +0300524 err = host1x_waitchk_copy_from_user(
525 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300526 if (err < 0)
527 goto fail;
528
529 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200530 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300531
532 /*
533 * The unaligned offset will cause an unaligned write during
534 * of the waitchks patching, corrupting the commands stream.
535 */
536 if (wait->offset & 3 ||
537 wait->offset >= obj->gem.size) {
538 err = -EINVAL;
539 goto fail;
540 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300541 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200542
Mikko Perttunena176c672017-09-28 15:50:44 +0300543 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300544 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200545 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300546 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200547
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300548 /* check whether syncpoint ID is valid */
549 sp = host1x_syncpt_get(host1x, syncpt.id);
550 if (!sp) {
551 err = -ENOENT;
552 goto fail;
553 }
554
Thierry Redingc40f0f12013-10-10 11:00:33 +0200555 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300556 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200557 job->syncpt_incrs = syncpt.incrs;
558 job->syncpt_id = syncpt.id;
559 job->timeout = 10000;
560
561 if (args->timeout && args->timeout < 10000)
562 job->timeout = args->timeout;
563
564 err = host1x_job_pin(job, context->client->base.dev);
565 if (err)
566 goto fail;
567
568 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200569 if (err) {
570 host1x_job_unpin(job);
571 goto fail;
572 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200573
574 args->fence = job->syncpt_end;
575
Thierry Redingc40f0f12013-10-10 11:00:33 +0200576fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200577 while (num_refs--)
578 drm_gem_object_put_unlocked(refs[num_refs]);
579
580 kfree(refs);
581
582put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200583 host1x_job_put(job);
584 return err;
585}
586
587
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200588#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200589static int tegra_gem_create(struct drm_device *drm, void *data,
590 struct drm_file *file)
591{
592 struct drm_tegra_gem_create *args = data;
593 struct tegra_bo *bo;
594
Thierry Reding773af772013-10-04 22:34:01 +0200595 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200596 &args->handle);
597 if (IS_ERR(bo))
598 return PTR_ERR(bo);
599
600 return 0;
601}
602
603static int tegra_gem_mmap(struct drm_device *drm, void *data,
604 struct drm_file *file)
605{
606 struct drm_tegra_gem_mmap *args = data;
607 struct drm_gem_object *gem;
608 struct tegra_bo *bo;
609
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100610 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200611 if (!gem)
612 return -EINVAL;
613
614 bo = to_tegra_bo(gem);
615
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200616 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300618 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200619
620 return 0;
621}
622
623static int tegra_syncpt_read(struct drm_device *drm, void *data,
624 struct drm_file *file)
625{
Thierry Reding776dc382013-10-14 14:43:22 +0200626 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200627 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200628 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629
Thierry Reding776dc382013-10-14 14:43:22 +0200630 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631 if (!sp)
632 return -EINVAL;
633
634 args->value = host1x_syncpt_read_min(sp);
635 return 0;
636}
637
638static int tegra_syncpt_incr(struct drm_device *drm, void *data,
639 struct drm_file *file)
640{
Thierry Reding776dc382013-10-14 14:43:22 +0200641 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200642 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200643 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200644
Thierry Reding776dc382013-10-14 14:43:22 +0200645 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200646 if (!sp)
647 return -EINVAL;
648
Arto Merilainenebae30b2013-05-29 13:26:08 +0300649 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200650}
651
652static int tegra_syncpt_wait(struct drm_device *drm, void *data,
653 struct drm_file *file)
654{
Thierry Reding776dc382013-10-14 14:43:22 +0200655 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200656 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200657 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200658
Thierry Reding776dc382013-10-14 14:43:22 +0200659 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200660 if (!sp)
661 return -EINVAL;
662
663 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
664 &args->value);
665}
666
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100667static int tegra_client_open(struct tegra_drm_file *fpriv,
668 struct tegra_drm_client *client,
669 struct tegra_drm_context *context)
670{
671 int err;
672
673 err = client->ops->open_channel(client, context);
674 if (err < 0)
675 return err;
676
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300677 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100678 if (err < 0) {
679 client->ops->close_channel(context);
680 return err;
681 }
682
683 context->client = client;
684 context->id = err;
685
686 return 0;
687}
688
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200689static int tegra_open_channel(struct drm_device *drm, void *data,
690 struct drm_file *file)
691{
Thierry Reding08943e62013-09-26 16:08:18 +0200692 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200693 struct tegra_drm *tegra = drm->dev_private;
694 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200695 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200696 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697 int err = -ENODEV;
698
699 context = kzalloc(sizeof(*context), GFP_KERNEL);
700 if (!context)
701 return -ENOMEM;
702
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100703 mutex_lock(&fpriv->lock);
704
Thierry Reding776dc382013-10-14 14:43:22 +0200705 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200706 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100707 err = tegra_client_open(fpriv, client, context);
708 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200709 break;
710
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 args->context = context->id;
712 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200713 }
714
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100715 if (err < 0)
716 kfree(context);
717
718 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200719 return err;
720}
721
722static int tegra_close_channel(struct drm_device *drm, void *data,
723 struct drm_file *file)
724{
Thierry Reding08943e62013-09-26 16:08:18 +0200725 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200726 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200727 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100728 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200729
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100730 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200731
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300732 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 if (!context) {
734 err = -EINVAL;
735 goto unlock;
736 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200737
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100738 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200739 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200740
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100741unlock:
742 mutex_unlock(&fpriv->lock);
743 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200744}
745
746static int tegra_get_syncpt(struct drm_device *drm, void *data,
747 struct drm_file *file)
748{
Thierry Reding08943e62013-09-26 16:08:18 +0200749 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200750 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200751 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200752 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100753 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200754
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100755 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200756
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300757 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100758 if (!context) {
759 err = -ENODEV;
760 goto unlock;
761 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200762
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100763 if (args->index >= context->client->base.num_syncpts) {
764 err = -EINVAL;
765 goto unlock;
766 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200767
Thierry Reding53fa7f72013-09-24 15:35:40 +0200768 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200769 args->id = host1x_syncpt_id(syncpt);
770
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100771unlock:
772 mutex_unlock(&fpriv->lock);
773 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200774}
775
776static int tegra_submit(struct drm_device *drm, void *data,
777 struct drm_file *file)
778{
Thierry Reding08943e62013-09-26 16:08:18 +0200779 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200780 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200781 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100782 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200783
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100784 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200785
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300786 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100787 if (!context) {
788 err = -ENODEV;
789 goto unlock;
790 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200791
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100792 err = context->client->ops->submit(context, args, drm, file);
793
794unlock:
795 mutex_unlock(&fpriv->lock);
796 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200797}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300798
799static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
800 struct drm_file *file)
801{
802 struct tegra_drm_file *fpriv = file->driver_priv;
803 struct drm_tegra_get_syncpt_base *args = data;
804 struct tegra_drm_context *context;
805 struct host1x_syncpt_base *base;
806 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100807 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300808
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100809 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300810
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300811 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100812 if (!context) {
813 err = -ENODEV;
814 goto unlock;
815 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300816
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100817 if (args->syncpt >= context->client->base.num_syncpts) {
818 err = -EINVAL;
819 goto unlock;
820 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300821
822 syncpt = context->client->base.syncpts[args->syncpt];
823
824 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100825 if (!base) {
826 err = -ENXIO;
827 goto unlock;
828 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300829
830 args->id = host1x_syncpt_base_id(base);
831
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100832unlock:
833 mutex_unlock(&fpriv->lock);
834 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300835}
Thierry Reding7678d712014-06-03 14:56:57 +0200836
837static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
838 struct drm_file *file)
839{
840 struct drm_tegra_gem_set_tiling *args = data;
841 enum tegra_bo_tiling_mode mode;
842 struct drm_gem_object *gem;
843 unsigned long value = 0;
844 struct tegra_bo *bo;
845
846 switch (args->mode) {
847 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
848 mode = TEGRA_BO_TILING_MODE_PITCH;
849
850 if (args->value != 0)
851 return -EINVAL;
852
853 break;
854
855 case DRM_TEGRA_GEM_TILING_MODE_TILED:
856 mode = TEGRA_BO_TILING_MODE_TILED;
857
858 if (args->value != 0)
859 return -EINVAL;
860
861 break;
862
863 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
864 mode = TEGRA_BO_TILING_MODE_BLOCK;
865
866 if (args->value > 5)
867 return -EINVAL;
868
869 value = args->value;
870 break;
871
872 default:
873 return -EINVAL;
874 }
875
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100876 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200877 if (!gem)
878 return -ENOENT;
879
880 bo = to_tegra_bo(gem);
881
882 bo->tiling.mode = mode;
883 bo->tiling.value = value;
884
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300885 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200886
887 return 0;
888}
889
890static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
891 struct drm_file *file)
892{
893 struct drm_tegra_gem_get_tiling *args = data;
894 struct drm_gem_object *gem;
895 struct tegra_bo *bo;
896 int err = 0;
897
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100898 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200899 if (!gem)
900 return -ENOENT;
901
902 bo = to_tegra_bo(gem);
903
904 switch (bo->tiling.mode) {
905 case TEGRA_BO_TILING_MODE_PITCH:
906 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
907 args->value = 0;
908 break;
909
910 case TEGRA_BO_TILING_MODE_TILED:
911 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
912 args->value = 0;
913 break;
914
915 case TEGRA_BO_TILING_MODE_BLOCK:
916 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
917 args->value = bo->tiling.value;
918 break;
919
920 default:
921 err = -EINVAL;
922 break;
923 }
924
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300925 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200926
927 return err;
928}
Thierry Reding7b129082014-06-10 12:04:03 +0200929
930static int tegra_gem_set_flags(struct drm_device *drm, void *data,
931 struct drm_file *file)
932{
933 struct drm_tegra_gem_set_flags *args = data;
934 struct drm_gem_object *gem;
935 struct tegra_bo *bo;
936
937 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
938 return -EINVAL;
939
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100940 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200941 if (!gem)
942 return -ENOENT;
943
944 bo = to_tegra_bo(gem);
945 bo->flags = 0;
946
947 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
948 bo->flags |= TEGRA_BO_BOTTOM_UP;
949
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300950 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200951
952 return 0;
953}
954
955static int tegra_gem_get_flags(struct drm_device *drm, void *data,
956 struct drm_file *file)
957{
958 struct drm_tegra_gem_get_flags *args = data;
959 struct drm_gem_object *gem;
960 struct tegra_bo *bo;
961
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100962 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200963 if (!gem)
964 return -ENOENT;
965
966 bo = to_tegra_bo(gem);
967 args->flags = 0;
968
969 if (bo->flags & TEGRA_BO_BOTTOM_UP)
970 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
971
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300972 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200973
974 return 0;
975}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200976#endif
977
Rob Clarkbaa70942013-08-02 13:27:49 -0400978static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200979#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200980 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
981 DRM_UNLOCKED | DRM_RENDER_ALLOW),
982 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
983 DRM_UNLOCKED | DRM_RENDER_ALLOW),
984 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
985 DRM_UNLOCKED | DRM_RENDER_ALLOW),
986 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
987 DRM_UNLOCKED | DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
989 DRM_UNLOCKED | DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
991 DRM_UNLOCKED | DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
993 DRM_UNLOCKED | DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
995 DRM_UNLOCKED | DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
997 DRM_UNLOCKED | DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
999 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
1001 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
1003 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
1005 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
1007 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001008#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001009};
1010
1011static const struct file_operations tegra_drm_fops = {
1012 .owner = THIS_MODULE,
1013 .open = drm_open,
1014 .release = drm_release,
1015 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +02001016 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001017 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001018 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001019 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001020 .llseek = noop_llseek,
1021};
1022
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001023static int tegra_drm_context_cleanup(int id, void *p, void *data)
1024{
1025 struct tegra_drm_context *context = p;
1026
1027 tegra_drm_context_free(context);
1028
1029 return 0;
1030}
1031
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001032static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001033{
Thierry Reding08943e62013-09-26 16:08:18 +02001034 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001035
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001036 mutex_lock(&fpriv->lock);
1037 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1038 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001039
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001040 idr_destroy(&fpriv->contexts);
1041 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001042 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001043}
1044
Thierry Redinge450fcc2013-02-13 16:13:16 +01001045#ifdef CONFIG_DEBUG_FS
1046static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1047{
1048 struct drm_info_node *node = (struct drm_info_node *)s->private;
1049 struct drm_device *drm = node->minor->dev;
1050 struct drm_framebuffer *fb;
1051
1052 mutex_lock(&drm->mode_config.fb_lock);
1053
1054 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1055 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001056 fb->base.id, fb->width, fb->height,
1057 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001058 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001059 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001060 }
1061
1062 mutex_unlock(&drm->mode_config.fb_lock);
1063
1064 return 0;
1065}
1066
Thierry Reding28c23372015-01-23 09:16:03 +01001067static int tegra_debugfs_iova(struct seq_file *s, void *data)
1068{
1069 struct drm_info_node *node = (struct drm_info_node *)s->private;
1070 struct drm_device *drm = node->minor->dev;
1071 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001072 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001073
Michał Mirosław68d890a2017-08-14 23:53:45 +02001074 if (tegra->domain) {
1075 mutex_lock(&tegra->mm_lock);
1076 drm_mm_print(&tegra->mm, &p);
1077 mutex_unlock(&tegra->mm_lock);
1078 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001079
1080 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001081}
1082
Thierry Redinge450fcc2013-02-13 16:13:16 +01001083static struct drm_info_list tegra_debugfs_list[] = {
1084 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001085 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001086};
1087
1088static int tegra_debugfs_init(struct drm_minor *minor)
1089{
1090 return drm_debugfs_create_files(tegra_debugfs_list,
1091 ARRAY_SIZE(tegra_debugfs_list),
1092 minor->debugfs_root, minor);
1093}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001094#endif
1095
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001096static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001097 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001098 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001099 .load = tegra_drm_load,
1100 .unload = tegra_drm_unload,
1101 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001102 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001103 .lastclose = tegra_drm_lastclose,
1104
Thierry Redinge450fcc2013-02-13 16:13:16 +01001105#if defined(CONFIG_DEBUG_FS)
1106 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001107#endif
1108
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001109 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001110 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001111
1112 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1113 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1114 .gem_prime_export = tegra_gem_prime_export,
1115 .gem_prime_import = tegra_gem_prime_import,
1116
Arto Merilainende2ba662013-03-22 16:34:08 +02001117 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001118
1119 .ioctls = tegra_drm_ioctls,
1120 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1121 .fops = &tegra_drm_fops,
1122
1123 .name = DRIVER_NAME,
1124 .desc = DRIVER_DESC,
1125 .date = DRIVER_DATE,
1126 .major = DRIVER_MAJOR,
1127 .minor = DRIVER_MINOR,
1128 .patchlevel = DRIVER_PATCHLEVEL,
1129};
Thierry Reding776dc382013-10-14 14:43:22 +02001130
1131int tegra_drm_register_client(struct tegra_drm *tegra,
1132 struct tegra_drm_client *client)
1133{
1134 mutex_lock(&tegra->clients_lock);
1135 list_add_tail(&client->list, &tegra->clients);
1136 mutex_unlock(&tegra->clients_lock);
1137
1138 return 0;
1139}
1140
1141int tegra_drm_unregister_client(struct tegra_drm *tegra,
1142 struct tegra_drm_client *client)
1143{
1144 mutex_lock(&tegra->clients_lock);
1145 list_del_init(&client->list);
1146 mutex_unlock(&tegra->clients_lock);
1147
1148 return 0;
1149}
1150
Thierry Reding67485fb2017-11-09 13:17:11 +01001151void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001152{
1153 struct iova *alloc;
1154 void *virt;
1155 gfp_t gfp;
1156 int err;
1157
1158 if (tegra->domain)
1159 size = iova_align(&tegra->carveout.domain, size);
1160 else
1161 size = PAGE_ALIGN(size);
1162
1163 gfp = GFP_KERNEL | __GFP_ZERO;
1164 if (!tegra->domain) {
1165 /*
1166 * Many units only support 32-bit addresses, even on 64-bit
1167 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1168 * virtual address space, force allocations to be in the
1169 * lower 32-bit range.
1170 */
1171 gfp |= GFP_DMA;
1172 }
1173
1174 virt = (void *)__get_free_pages(gfp, get_order(size));
1175 if (!virt)
1176 return ERR_PTR(-ENOMEM);
1177
1178 if (!tegra->domain) {
1179 /*
1180 * If IOMMU is disabled, devices address physical memory
1181 * directly.
1182 */
1183 *dma = virt_to_phys(virt);
1184 return virt;
1185 }
1186
1187 alloc = alloc_iova(&tegra->carveout.domain,
1188 size >> tegra->carveout.shift,
1189 tegra->carveout.limit, true);
1190 if (!alloc) {
1191 err = -EBUSY;
1192 goto free_pages;
1193 }
1194
1195 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1196 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1197 size, IOMMU_READ | IOMMU_WRITE);
1198 if (err < 0)
1199 goto free_iova;
1200
1201 return virt;
1202
1203free_iova:
1204 __free_iova(&tegra->carveout.domain, alloc);
1205free_pages:
1206 free_pages((unsigned long)virt, get_order(size));
1207
1208 return ERR_PTR(err);
1209}
1210
1211void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1212 dma_addr_t dma)
1213{
1214 if (tegra->domain)
1215 size = iova_align(&tegra->carveout.domain, size);
1216 else
1217 size = PAGE_ALIGN(size);
1218
1219 if (tegra->domain) {
1220 iommu_unmap(tegra->domain, dma, size);
1221 free_iova(&tegra->carveout.domain,
1222 iova_pfn(&tegra->carveout.domain, dma));
1223 }
1224
1225 free_pages((unsigned long)virt, get_order(size));
1226}
1227
Thierry Reding9910f5c2014-05-22 09:57:15 +02001228static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001229{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001230 struct drm_driver *driver = &tegra_drm_driver;
1231 struct drm_device *drm;
1232 int err;
1233
1234 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001235 if (IS_ERR(drm))
1236 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001237
Thierry Reding9910f5c2014-05-22 09:57:15 +02001238 dev_set_drvdata(&dev->dev, drm);
1239
1240 err = drm_dev_register(drm, 0);
1241 if (err < 0)
1242 goto unref;
1243
Thierry Reding9910f5c2014-05-22 09:57:15 +02001244 return 0;
1245
1246unref:
1247 drm_dev_unref(drm);
1248 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001249}
1250
Thierry Reding9910f5c2014-05-22 09:57:15 +02001251static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001252{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001253 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1254
1255 drm_dev_unregister(drm);
1256 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001257
1258 return 0;
1259}
1260
Thierry Reding359ae682014-12-18 17:15:25 +01001261#ifdef CONFIG_PM_SLEEP
1262static int host1x_drm_suspend(struct device *dev)
1263{
1264 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001265 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001266
1267 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001268 tegra_drm_fb_suspend(drm);
1269
1270 tegra->state = drm_atomic_helper_suspend(drm);
1271 if (IS_ERR(tegra->state)) {
1272 tegra_drm_fb_resume(drm);
1273 drm_kms_helper_poll_enable(drm);
1274 return PTR_ERR(tegra->state);
1275 }
Thierry Reding359ae682014-12-18 17:15:25 +01001276
1277 return 0;
1278}
1279
1280static int host1x_drm_resume(struct device *dev)
1281{
1282 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001283 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001284
Thierry Reding986c58d2015-08-11 13:11:49 +02001285 drm_atomic_helper_resume(drm, tegra->state);
1286 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001287 drm_kms_helper_poll_enable(drm);
1288
1289 return 0;
1290}
1291#endif
1292
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001293static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1294 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001295
Thierry Reding776dc382013-10-14 14:43:22 +02001296static const struct of_device_id host1x_drm_subdevs[] = {
1297 { .compatible = "nvidia,tegra20-dc", },
1298 { .compatible = "nvidia,tegra20-hdmi", },
1299 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001300 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001301 { .compatible = "nvidia,tegra30-dc", },
1302 { .compatible = "nvidia,tegra30-hdmi", },
1303 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001304 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001305 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001306 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001307 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001308 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001309 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001310 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001311 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001312 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001313 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001314 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001315 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001316 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001317 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001318 { .compatible = "nvidia,tegra210-vic", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001319 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001320 { /* sentinel */ }
1321};
1322
1323static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001324 .driver = {
1325 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001326 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001327 },
Thierry Reding776dc382013-10-14 14:43:22 +02001328 .probe = host1x_drm_probe,
1329 .remove = host1x_drm_remove,
1330 .subdevs = host1x_drm_subdevs,
1331};
1332
Thierry Reding473112e2015-09-10 16:07:14 +02001333static struct platform_driver * const drivers[] = {
1334 &tegra_dc_driver,
1335 &tegra_hdmi_driver,
1336 &tegra_dsi_driver,
1337 &tegra_dpaux_driver,
1338 &tegra_sor_driver,
1339 &tegra_gr2d_driver,
1340 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001341 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001342};
1343
Thierry Reding776dc382013-10-14 14:43:22 +02001344static int __init host1x_drm_init(void)
1345{
1346 int err;
1347
1348 err = host1x_driver_register(&host1x_drm_driver);
1349 if (err < 0)
1350 return err;
1351
Thierry Reding473112e2015-09-10 16:07:14 +02001352 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001353 if (err < 0)
1354 goto unregister_host1x;
1355
Thierry Reding776dc382013-10-14 14:43:22 +02001356 return 0;
1357
Thierry Reding776dc382013-10-14 14:43:22 +02001358unregister_host1x:
1359 host1x_driver_unregister(&host1x_drm_driver);
1360 return err;
1361}
1362module_init(host1x_drm_init);
1363
1364static void __exit host1x_drm_exit(void)
1365{
Thierry Reding473112e2015-09-10 16:07:14 +02001366 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001367 host1x_driver_unregister(&host1x_drm_driver);
1368}
1369module_exit(host1x_drm_exit);
1370
1371MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1372MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1373MODULE_LICENSE("GPL v2");